Analog Electronics

INDEX
S. No Topic Page No
Week 1
1 Introduction to the course 1
2 Introduction to the constituent topics of the course and the Layout 19
3 Revisit to pre-requisite topics 40
4 Revisit to prerequisite topics (Contd.) 53
5 Analysis of Simple Non-Linear Circuit 62
6 Analysis of Simple Non - linear Circuit (Contd.) 77
Week 2
7 Revisiting BJT Characteristic 93
8 Revisiting BJT Characteristics (Contd.) 110
9 Revisiting BJT Characteristics (Contd.) 128
10 Revisiting MOSFET 152
11 Revisiting MOSFET (Contd.) 169
Week 3
14 Analysis of simple non - linear circuit containing a BJT 212
15 Analysis of simple non - linear circuit containing a BJT (Contd.) 226
16 Analysis of simple non - linear circuit containing a MOSFET 240
17 Analysis of simple non - linear circuit containing a MOSFET (Contd.) 254
18 Linearization of non - linear circuit containing BJT 269
19 Linearization of non - linear circuit containing BJT (Contd.) 285
20 Linearization of non - linear circuit containing MOSFET 298
21 Linearization of non-linear circuit containing MOSFET (Contd.) 311
Week 4
22 Linear models of Amplifiers (Part A) 322
23 Linear models of Amplifiers (Part B) 334
24 Common Emitter Amplifier (Part A) 348
25 Common Emitter Amplifier (Part B) 361
26 Common Emitter Amplifier (contd.) (Part A) 373
27 Common Emitter Amplifier (contd.) (Part B) 387
28 Common Emitter Amplifier (contd.) - Numerical examples (Part A) 400
29 Common Emitter Amplifier (contd.) - Numerical examples (Part B) 411
30 Common Emitter Amplifier (contd.) - Design guidelines (Part A) 425
31 Common Emitter Amplifier (contd.) - Design guidelines (Part B) 438
32 Common Source Amplifier (Part A) 450
33 Common Source Amplifier (Part B) 465
Common Source Amplifier (contd.) Numerical examples and design guidelines
34 (Part B) 480
Week 5
35 Frequency Response of CE and CS Amplifiers (Part A) 494
36 Frequency Response of CE and CS Amplifiers (Part B) 507
37 Frequency Response of CE and CS Amplifiers (Part C) 521
38 Frequency Response of CE and CS Amplifiers (Contd.) (Part A) 530
39 Frequency Response of CE And CS Amplifiers (Contd.) (Part B) 542
Frequency Response of CE/CS Amplifiers Considering High Frequency Models
40 of BJT and MOSFET (Part A) 554
41 of BJT and MOSFET (Part B) 567
42 of BJT And MOSFET (Part C) 577
43 Limitation of CE and CS Amplifiers in Cascading 587
Week 6
44 Common Collector and Common Drain Amplifiers 605
45 Common Collector and Common Drain Amplifiers (Contd.): Analysis (Part A) 625
46 Common Collector and Common Drain Amplifiers (Contd.): Analysis (Part B) 639
Common Collector and Common Drain Amplifiers (Contd.): Numerical
47 Examples (Part A) 653
Common Collector and Common Drain Amplifiers (Contd.): Numerical
48 Examples (Part B) 664
49 Common Base and Common Gate Amplifiers : Analysis (Part A) 682
50 Common Base and Common Gate Amplifiers : Analysis (Part B) 695
Common Base and Common Gate Amplifiers (Contd.) : Numerical Examples
51 (Part A) 714
52 (Part B) 726
53 (Part C) 738
54 (Part D) 749
Week 7
55 Multi-Transistor Amplifiers: Operation and Analysis (Part A) 759
56 Multi-Transistor Amplifiers: Operation and Analysis (Part B) 772
57 Multi-Transistor Amplifiers : Operation and Analysis (Part C) 783
58 Multi-Transistor Amplifiers (Contd.): Numerical Examples (Part A) 798
59 Multi-Transistor Amplifiers (Contd.): Numerical Examples (Part B) 809
60 Multi-Transistor Amplifiers (Contd.): Numerical Examples (Part C) 818
61 Multi-Transistor Amplifiers: Cascode Amplifier (Part A) 825
62 Multi-Transistor Amplifiers : Cascode Amplifier (Part B) 843
Week 8
Multi-Transistor Amplifiers: Cascode Amplifier (Contd.) â€“ Numerical
63 Examples (Part A) 854
64 Examples (Part B) 868
65 Examples (Part C) 882
66 Multi-Transistor Amplifiers : Amplifier With Active Load (Part A) 891
67 Multi-Transistor Amplifiers : Amplifier With Active Load (Part B) 903
Multi-Transistor Amplifiers : Amplifier With Active Load (Contd.)
68 â€“Numerical Examples (Part A) 923
Multi-Transistor Amplifiers : Amplifier With Active Load (Contd.)
69 â€“Numerical Examples (Part B) 934
Week 9
Single - ended Vs. Differential Signaling and Basic Model of a Differential
70 Amplifier 949
71 Amplifier(Contd.) 963
75 Differential Amplifier : Basic Structure and Principle of Operation 1011
76 Differential Amplifier : Basic Structure and Principle of Operation (Contd.) 1026
77 Differential Amplifier : Analysis and Numerical Examples 1041
78 Differential Amplifier : Analysis and Numerical Examples (Contd.) 1055
79 Differential Amplifier : Analysis and Numerical Examples (Contd.) 1070
80 Differential Amplifier : Analysis and Numerical Examples (Contd.)(Part B) 1085
Week 10
81 Current mirror circuits (Part-A) 1106
82 Current mirror circuits (Part-B) 1122
83 Usage of current mirror (Part-A) 1141
84 Usage of current mirror (Part-B) 1155
85 Usage of current mirror (Part-C) 1168
86 Numerical examples on current mirror and its applications (Part-A) 1186
87 Numerical examples on current mirror and its applications (Part-B) 1199
88 Numerical examples on current mirror and its applications (Part-C) 1212
89 Numerical examples on current mirror and its applications (Part-D) 1222
Week 11
90 Feedback system (Part-A) 1232
91 Feedback system (Part-B) 1248
92 Feedback system (Part-C) 1263
93 Feedback system (Part-D) 1281
94 Feedback system (Part-E) 1296
95 Effect of feedback on frequency response (Part-A) 1309
Week 12
96 Effect of feedback on frequency response (Part-B) 1323
97 Applications of feedback in amplifier circuits (Part-A) 1337
98 Applications of feedback in amplifier circuits (Part-B) 1351
99 Applications of feedback in amplifier circuits (Part-C) 1363
Analog Electronic Circuits
Prof. Pradip Mandal
Department of Electronics and Electrical Communication Engineering
Indian Institute of Technology, Kharagpur
Lecture - 01
Introduction to the Course
So, welcome to this NPTEL online course, titled Analog Electronic Circuit. Myself Pradip
Mandal, from Electronics and Electrical Communication Engineering department of IIT
Kharagpur. Today we are going to start with the Introduction to this Course and before I
go into the introduction just I like to highlight that, I am teaching this course for almost
more than 10 years.
So, most of the materials it will be covered from for this course, it is not only from
textbook, but also whatever the experience we have gathered throughout this program.
And prior to that I will must say that, before joining here I was in industry for nearly 7 and
half years. So, there I learned some of the practical aspects. So, I am trying to mix with
theory and practical aspects together to give you may be slightly different flavor than
normally available in textbook ok.
(Refer Slide Time: 01:52)
So, let us go into the, whatever the topic will be covering. I will start with few words about
the course and then we will be going more towards the introduction of analog electronics.
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So, to start with we will be discussing about the electronic circuits, then electronic systems
and then in the present scenario what we call it is digital era.
In this era what is the significance and importance of analog electronics or to be more
precise what is the fate of analog electronics in digital era. And then we will be talking
about how whatever the things we are planning in analog electronic circuits, basically the
scope of analog electronic circuits in this course.
So, let us move to next. So, about the course this course it has been primarily designed as
core course, and explicitly for UG level students. However, this course can also be used
as refresher course, particularly for those students who has gone through the UG level
before and now in mastered levels or the designer who were working in industry and they
like to look back the theory and correlate whatever their day to days’ performance or day
to days’ circuits they do design.
So, this may be looked into as both aspects; core course for UG and refresher course for
master level students or maybe 2 to 3 years experienced designers. So, the flow of this
course we shall start with basic components, circuit components and course circuit
concepts. And gradually we will be moving to practical circuits, which are essential parts
of analog electronic systems.
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So, that will be the flow. So, we will start with components, it may require a little bit
prerequisite of devices, may be prerequisites from electrical theory and so and so and then
we will be moving towards the main topic analog electronic circuits and systems.
Now, few more words to say; so, to continue with whatever we like to say about the under
course namely, while we have planned this course intentionally we made some emphasis,
so that we can make a good balance between theory and theory and practices. And also
while we will be going through this course materials, we will see that the circuit examples
we will be discussing; they are whatever the examples will be covering, we will try to
make a balance between theory and practice.
And the example circuit they can be easily constructed in a UG level instruction lab and
those circuits, the constructed circuits can be characterized or their performance can be
measured and the measured performance can be compared with analytically predicted
performance of the circuits.
So, the examples if you practice those examples along with this theory in lab classes; what
it helps is that, it will build up your confidence level about the circuit theory and not only
that probably you can get advantage of whatever the theory will be gathered here to add to
your practical experiences. So, this is the first feature or characteristic I should say of this
course content.
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The second feature of this course it is, we are going to discuss the both BJT and MOS
based circuit simultaneously; so that you can get a similarity of those circuits as well as
you can find the differences, particularly the they are not only their operation, but the
performance differences of BJT based circuit and then MOS based circuits. And not only
that, based on this simultaneous study you yourself can gradually understand that in what
context we should go for BJT based circuit and in what context you can go for the other
one
So, while we are simultaneously covering this BJT and MOS based circuit obviously, there
is a reason; first of all, there will be a lot of commonalities of these two classes of circuits,
namely say common emitter amplifier and common source amplifier they do have good
similarities. But then the basic important thing is that, why we like to cover both BJT and
MOS together; the reason is that BJT’s these components are easily available.
So, you can easily construct circuits different building blocks in your lab laboratory on
bread board and you can observe their characteristic, you can measure their performances;
which may be little difficult for MOS base MOSFET based circuit. So, to correlate the
theory with the practical measurement, I think the BJT based circuit is need to be covered.
But then at the same time we like to also cover MOS phase MOSFET based circuit; that
is because whenever we go down the line and in the present scenario where instead of
analog circuit alone in a typical system, electronic system we will see that both digital and
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analog counterpart, they are mixed together to get something called mixed signal
customized design.
Where instead of BJT, MOSFET based analog circuit is quite popular, mainly because this
MOSFET it is it helps to integrate the analog circuit along with the digital counterpart on
the same IC. So, if you look into the present scenario where instead of standalone analog
electronics circuits, analog VLSI circuits are more popular where most of the circuits are
getting implemented using MOSFET base.
So, here whatever the circuit analysis will be covering about the MOSFET’s MOSFET
based circuit that gives you the foundation for the next level course analog VLSI circuits
and systems. So, that is the main two features we will be having this in this course.
So, these two features namely this feature 1 and feature 2, these two features are helping
to make this program or this course quite distinct and different from normally available
courses. Apart from those two features, the content of this course we have tried to make it
aligned with the content of analog electronics course under AICTE model curriculum.
So, that those students who are having this program they are coming under this program,
AICTE program they can easily attend this course and make them prepared, well prepared
for maybe the get preparation or their own on engineer their college courses. So, the this
is how this course it is different from maybe the other online course available on this topic
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at present. Now let us move towards what are the things we like to cover in analog
electronics, particularly let us move to whatever the electronics or analog electronics mean.
So, let me start with electronic circuits. So, whenever we say electronic circuit what we
are looking for it is that, if I look into the circuit as a black box. So, if I say that this is my
electronic circuit, to make this circuit working what I need to do it is we need to put the
power on. So, we can give a DC supply to activate the circuit.
So, let you think of that, this is a power supply by which we are energizing the circuit. So,
we are having this electronic circuit here and then once it is getting energized then you can
apply the signal at the input port. And then you can consider the corresponding effect at
the output, namely you would like to see what will be the corresponding output coming to
this circuit.
So, whenever we are giving the signal, we will be giving the signal at this input port; it
may be with respect to the same ground of this or it may be having it is own DC. And
suppose this is the output port, we like to observe the corresponding signal at the output
port and let you consider that the output signal it is voltage. So, we like to observe the
voltage here with respect to the ground.
So, let you call this is output signal maybe in terms of voltage Vout and this is the
corresponding Vin. So, whenever we are talking about say electronic circuit what we mean
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it is, of course we do have a lot of activities within the circuit; but that will be getting
activated only when we turn on this power. And then we apply the input, namely what we
call input signal or stimulus and then we can observe the corresponding output.
So, unless otherwise it is stated we assume that, this DC power supply it is well connected.
And instead of showing this DC supply every time, we may say that this is the DC supply;
either we call this is VCC or sometimes you call VDD depending on the kind of circuit we
will be using and then this is the ground and so and so. The both input and output may be
with respect to the same ground or it may be with respect to some DC level, that we will
see it later.
But what we like to say that electronic circuit, whenever we are talking about electronic
circuit; it is basically it consists of different electronic devices. So, within this one we do
have electronic devices and those devices are getting activated by this DC and they should
be in proper region of operation and so and so. So, those details we will be seeing later,
but whenever you are talking about see signal, what we mean by signal?
So, in this case as an example, we are saying the signal can be voltage. So, both input as
well as output signal here it is shown as voltage and, but then need not be always voltage
it may be current also. In fact, it may be the other likes charges or powers and so on; but
unless otherwise it is stated in us in this course, in our context primarily we will be thinking
that the signals are in voltage or in current form.
So, whenever we are feeding some stimulus, we will assume that non electrical signals are
getting somehow converted into electrical signal either in voltage or current. And likewise
whenever we will be observing the signal we will be expecting that the signal it will be
observed either in voltage or in current form, ok. So, whenever we say that nature of the
signals, we will keep our focus either in voltage or current; but in general it can be power
or charges, ok.
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So, let us move into little detail of what are the things are there inside this electronic
circuits. So, we said that signals, now let us look into what kind of signals it is possible,
types of signals. So, whenever we say a types of signals, it is we are assuming signal means
it is voltage changing with time. So, the x-axis is t and then y-axis it is voltage, for the time
being let you consider it is V and then this is time axis t, it may be seconds, milliseconds,
microseconds and so and so, so this is in the scale of voltage.
And then, it may be changing with respect to time like this. And we are expecting that the
signal of course it is having it is own limit, it may be some higher limit and the lower limit
may be 0; but we are expecting the signal, it will be within this range. Now depending on
the emphasis and the allowable levels of the signal, the signal can be different types;
namely analog and digital kind of signal.
And if you see this analog or digital kind of signals it is basically indicates that, what are
the possible levels acceptable levels or meaningful levels of the signals the circuit can
recognize or we recognize. Say for instance, here this signal at any level, it may be
recognized as signal. So, we can say if the signal it is having so many possible acceptable
levels, then or you can say the resolution it is continuous, so we can say that the signal it
is analog in nature.
In contrast to that, in case if we are having a special situation where the signal, it is having
distinct levels; may be here also we may say that say V(t), but it may be having say two
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distinct levels, may be either high or low and so and so. In between if there is any transition
we may ignore, we may ignore this transition levels and the acceptable or meaningful
levels are only say this one or say whatever the level we do have.
So, we may say that this is level 1 and this is say level 0 or we can say this is high level or
low level. By the way it is not mandatory that these two levels it will be expected to be 1
V or 0 V; it may have a range of voltage, which may be accepted as meaningful logic 1.
Say for example, we may have a meaningful voltage range, over which we may say that
signal it is level 1.
So, likewise we may have another acceptable level for 0 levels. So, this 1 and 0 does not
mean that the voltage it will be 1 V or 0 V. And of course, it is having some acceptable
range, so whatever you say high level and low level. In between whatever the levels we
do have, in case if the signal it is falling within that; we may say that this is undefined
level. So, if it is within this range we call it is undefined level; for such scenario, since the
signal it is having only two levels we call it is binary signals.
In case if you are having such kind of distinct levels, need not be only two, but it is having
finite levels then we call it is digital signal. Which means that, in case if we have a scenario
like this, the signal maybe having say distinct levels need not be only two; but it is having
only some acceptable finite levels, then we call it is digital signal. So, both this case as
well as this case, these kind of scenarios are called a digital signal. So, these are digital
signal.
Whereas for this case, the signal it is it can continuously vary in the voltage level voltage
scale and this is called analog signal. So, we call analog signal here and these signals
whatever the signals we have discussed here, here as well as here they are digital signal.
Now for both cases whether in this case or this case, you see that the voltages they are
there continuously along the time axis; which means that at every time instances the
voltages are available, either here or here at every time instances the corresponding
voltages are available.
In contrast to that, in case if we have a situation where the voltages are available only at
distinct time point; namely say at this point time point we do have the signal available.
And then in between we do not have any information about the signal, but then at other
instances say here we do have the signal information available and so and so. This may be
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the case for here as well, if the signals are available here at some distinct points; then such
kind of signals we call it is of course, digital signal, but we call it is discrete time digital
signal.
In contrast to that whatever just now we have discussed, earlier we have discussed where
if the signal it is available for every time instances, it is called continuous time signal. So,
based on the availability of the signal along the time axis we do have one category;
basically one types of classification called continuous time versus discrete time signals.
On the other hand, whenever we see the signal voltage range, there again we do have two
types of signal; one is analog signal and digital signals.
So, whenever we are dealing with electronic circuit, it is expected that the circuit the
intended circuit should recognize at least one of these kind of signals and based on that we
may classify the circuit type also. In fact, in the recent scenario I should not say very recent,
but of course, in recent scenario there is the other kind of signals called mixed signal;
where the signal may be in digital form, but the information may be continuous.
Say for example, here we do have digital signal, but if you say that actual signal it is
something like this which we are knowing that the information is like this; but the signals
are captured by this different digital levels they are called mixed signal kind of in a circuits.
So, we will be going detail into that; but for the time being let me move on to classify the
circuit analog versus digital.
And so, based on as I said that, based on the kinds of signal they do recognize the circuit
recognized, those circuits will be classified as analog circuits, digital circuits or you know
mixed signal circuits.
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So, we may have a scenario where we may have one circuit here, another circuit here and
so and so. Now each of these circuits, they may have their own functionalities to perform.
And let me assume that the signal it is propagating from left hand towards the right.
And suppose say this signal, signal here it is analog and here also the signal it is analog.
So, these signals are analog. So, we called then this circuit, so we call this circuit it is
analog circuit. And so, likewise whenever let us consider say this last block, say we do
have different digital signals coming here and we are expecting the outputs are also digital;
which may be single or multiple signals and if I say that these are digital signals.
So, likewise this is also collection of say digital output signal. So, this digital outputs are
basically output of this block. Since it is input and output. So, this is of course, it is a
corresponding input signals. Since the input and output signals are digital in nature, we
call this circuit as digital circuit. Now you may say that if I want to cascade say this in
between, so if we want to cascade say analog circuit to digital. So, we need to place in
between a special kind of circuit, we suppose to convert analog circuit into digital.
Now, the question is that, then how do you name this circuit; shall you call it is mixed
signal, analog or digital. Normally this is referred as analog only, because this signal
whatever the signal it is received by this block it is analog in nature. So, without going into
any ambiguity, we call this is analog circuit; mainly because the digital signals it may be
treated as a special kind of output of analog signals so on.
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So, that is how we classify different circuits as different circuits either in analog, digital.
And then the next type or whatever I was telling that mixed signal, it is kind of a special
kind of signals, a circuits; which involves the information in analog form, but it may be
having digitization within that. So, that will be another the third class or third types of a
circuits called mixed signal.
Now, whenever we consider the next block and we may similar to or complementary to
this, we may convert this digital signal into the form of analog. So, again similar to this
circuit, this circuit we will also be called analog; that is how the classification goes, ok.
Whenever we look into the electronic system and that involves different modules; namely
analog circuits and then we do have digital circuits and maybe mixed signal also. And so,
how do we, how do you classify them? Of course, circuit wise we can definitely classify;
but main thing is how do we integrate them and what is the present scenario and so on so.
So, let you consider we do have different modules and this is we call say boundary of the
electronic systems and then we are interfacing the real world. So, we can say that this is
the scope of analog system, inside whatever the things we are doing end of it we like to
give the output to the real world. And whenever we are talking about say real world, we
may be having some device, special kind of device which may convert non electrical signal
in the form of electrical signal.
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So, this block which is called say typically it is called sensor. So, likewise at the other end,
we may be having a special kind of circuit which converts a maybe electrical signal in the
form of non electrical signal; say for example, this may be speaker, this may be a sensor.
So, here we do have maybe some sensing circuit which senses, may be pressure or
temperature or whatever it is; likewise, the output device it may give the signal in the form
of acoustic signal and so and so.
So, in this electronic system we are expecting that there will be a meaningful conversion
of a real world signal into the form of electronic signal; likewise, at the output side, there
will be a meaningful device which supposed to be converting electrical signal in the form
of non electrical signal. So, the first block since it is interfacing the real world, and the
signal here it is analog in nature; typically, this is what it is analog in nature, this first block
it is analog circuit. So, this first block it is analog circuit.
And then we do have digital signal here. So, likewise here also do you have digital signal
here. So, as you can guess that this block it will be digital. So, once this digital signal it is
coming to another circuit which is, so it is supposed to be interfacing with the device here
to convert electrical signal into non-electrical signal; it may be speaker, it may be display
or whatever it is and we may require to change this digital signal into the form of analog.
So, this is analog signal and this circuit maybe I will use this color. So, this is again analog
circuit. So, if you see here a typical system, it is mix of an analog circuit and digital circuit.
And if you see that it looks like within the electronics we do have a digital core, so we can
say that this is digital core. And these two circuits, particularly this part and this part which
are interfacing with the real world, you may say that they are peripheral devices.
So, you may feel that this is a digital core, digital core circuits and surrounding to that we
do have interface circuits. So, this portion, this shell you can say it is analog. Now of
course, then the natural question is that what may be the boundary of this digital core or
digital circuit and what may be the thickness of this analog shell to interface with the real
world, is it changing or is it evolving?
So, if you see a typical evolution of electronic system, this core circuit it is growing; it is
growing of course, it is having it is own reason. And then of course, also I know I miss the
another important thing is that, this whenever we say this analog circuit which is
interfacing with real world; then it is also it is another provision. In fact, if you see here I
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should I must mention that, you may be having some alternate means to interface with the
external world; either through RF for through optical.
But again there you may require some additional circuitry which is very similar in nature
of analog circuit. We may call it is optical circuit, optical sensor, optical driver or you may
say RF receiver or RF driver; but their nature it is similar to an analog circuit rather than
digital circuit. So, the knowledge you will be gathering here in this course related to this
analog circuit, that will help you to understand that how this interface circuit it is working.
Now so, we require different types of modules; namely analog circuits and digital circuit.
Now to summarize that why do we require and when do we require this analog and digital;
so analog circuit it is essential to interface with real world that is very much needed. So,
we required this analog shell. So, it interfaces with the real world.
On the other hand, whenever you look into the core, digital core, so it provides it is having
it is own advantage. So, this is digital and this is an analog and I should say it is kind of a
shell outside of this core, digital core. So, if you see the advantage of this digital core it is,
it provides flexibility and the programmability of the whole system. If I say that this is the
electronics system, this is a very much flexible.
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Even user can define the behavior of the digital core or maybe you can load the software
and you can change the behavior of the whole system and that is how this digital core it is
getting more and more popular. So, that is the first advantage of having digital code.
And of course, the it also easy to store information, it is easy to store in compact devices.
And of course, they are not only the storage part but also the implementation of the circuit
it is; we can say that they require a lot of this they require less amount of power compared
to the analog counterpart. And with progress of time, the implementation technology it is
very supportive for the digital kind of circuit, particularly if you say that CMOS
technology. It is very suitable for digital circuit.
So, with progress of time if you see the evolution of this analog electronics, originally
maybe it was having only analog circuits. So, that was self sufficient. But then with
progress of time this digital core it has been added and with progress of time this digital
core it is in fact getting more and more fatter, probably the analog shell it is getting thinner
and thinner. So, the natural question is that whether this shell it will be completely getting
vanished; the obvious answer is no; because the outside world, this external world is analog
in nature.
So, definitely for digital to interact with the real world, you require this analog shell; so
this analog shell it will be remaining there. And with progress of time, it is expected that
this digital core it will be further improving with more and more application, more and
more you know implementation and probably more and more development of the
technology. And as it is progressing the need of this shell definitely it will remain there.
The interesting part is that, as this core portion it is increasing; it is design and it is
implementation it is more, it is getting automated by computer. Whereas, this analog
portion of course, it is if we do use computer to design this analog portion; but it requires
very customized skill to design this analog circuit, that may be one of the reason why this
analog circuit is it remains very hard to implement. But at the same time you may say that,
the knowledge expert knowledge of analog circuit it the circuit design, it is value it will
remain there.
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So, the need of analog designer of course, it will be there. So, if you see the fate of the fate
of this analog electronics it is if it is in particularly in digital era. So, whenever we say the
digital era, basically we are saying we do have more and more digitization with progress
of time; but then it also has more and more application. But then as I said that along with
the digital core the requirement of this analog shell it will be remaining there; and hence
the and requirement of analog circuit it will be remaining.
But of course, you need to be careful, while this core portion it is; core portion it is
dominating in terms of volume. The nature or the format of this analog shell it may evolve
while it need to be integrated.
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So, to summarize, so before we summarize; so in this context I must say that, what are the;
what are the things we are going to covered in this analog electronics, to be more precise
what may be the emphasis of this course. We will start with analog building blocks, their
working principle, analysis and design and those building blocks.
So, here we will start with building blocks, different building blocks individually and then
we will move to whatever the challenges we will face while we will be interfacing different
blocks together to make a bigger system. So, we may make bigger analog system or I
should say analog module to be more precise by stitching individual analog building
blocks.
And then we will see that how this interface effects are making it more and more
challenging. And then we will make this circuit more towards practical analog modules.
So, when we will be covering these practical analog modules, we will be definitely, will
be discussing about their own on working principle. So, suppose this is the analog
modules, it may be having it is own building blocks.
But before we go into the building blocks, holistically we can look into this entire module
and we can see what is the input output behavior; based on this required input output
behavior how the circuit can be analyzed and designed. So, I should say we will start from
this block level, namely bottom and then we will try to see what will be the interface
effects. And then we will see that how we can make bigger system and then we will go
17
from top to bottom; we will start from system level and then we will go to the
implementation of the smaller level.
Now, moving to the conclusion; so what we have done is that, at least we got some idea
about what is electronic circuits and what is the typical electronic system consists of and
then also we have we got a sense of what may be the fate of analog electronic circuits,
particularly in the digital era which is more and more getting dominated. And then a little
bit about what may be the emphasis of this course, analog electronic circuit course that we
have covered.
Subsequently we will be making a plan, the whole course plan and the break up per week
what may be the topic it will be discussed. So, that is all I need to cover here.
Thank you.
18
Prof. Pradip Mandal
Lecture - 02
Introduction to Constituent Topics of the Course and the Layout
So, welcome to this 2nd module of Analog Electronic Circuits. So, today what we are
planning to do it is we will browse through what are the topics we will be covering in this
course and how each of those topics are related and how do they address the new topic
called analog electronic circuits. And we will also see that how those subtopics are related
to each other and then also what will be the weekly layouts of the content. So, primarily
we will be covering different subtopics of this course and their corresponding weekly plan.
So, let us move to the main topic. So, the content of like the today’s discussion it will be,
what are the tasks are performed by a one analog circuit or typically the analog circuits.
So, that is the first thing we will see and that probably it will help us to understand that
what are the importance of different subtopics are there. And then we will also see that
what are the constituent blocks are there within analog system typical analog system, and
how the analog system can be architecturally constructed.
So, this will help us to understand why a specific flow it has been followed here in this
course and how it is; how each of these subtopics are useful to construct say analog circuits
19
or analog systems or analog subsystems. So, these are the main two I should say sub topics
to be covered today. And then those sub topics are; however, they plan as I said; however,
they planned over the different weeks that we will be discussed.
So, let us move to the what are the tasks it will be performed by analog circuit; but before
that, let me recapitulate the last slide of our previous discussion.
So, what are the emphasis we say that will be given in this course namely the building
blocks of analog circuits and their working principle and analysis and design of those
building blocks and then while we are integrating different building blocks to construct
relatively bigger circuits. Namely if we cascade and cascode and so and so; what are the
interface effects it will be coming there so, that also we will be covering.
And then of course, will be looking into some of the practical analog circuits and their of
course, working principle, analysis and design. So, this is what the overall emphasis it will
be there for this course and now let us look into the what are the basic performance it is
done by a typical analog circuit.
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Now, if I see the typical analog circuit and if I say that what are the topmost objective it is
performed by a typical analog circuit is, basically it amplifies signal. Whenever we say
same amplify a signal what we mean it is we like to say that it may be voltage domain
signal and its nature it may be retained and then the at the output what we are expecting it
is same input signal, but of course, its strength it is expected to be higher.
So, if I say that this is the typical analog circuit, which is powered by say a DC voltage
here let me call this is Vcc and this is ground. And the analog signal we are applying here
say it may be having its meaningful DC bias and at the output what whatever the output
you are observing may be with respect to the main same ground or it may be with respect
to a DC voltage whatever the signal will be observing that you call it is signal in the form
of voltage and if we observe the signal at the input.
So, what we are expecting is that, this Vout and Vin they are highly correlated and what we
are expecting is that suppose we apply a signal with respect to say time. So, this is the Vin,
it may be having its own DC level on top of that suppose we do have some signal. So,
what we are expecting at the output which is the effect of the signal we are applying at the
input.
So, the Vout is we are expecting it may be having its own DC level, it may be different
from whatever the DC voltage you do have here and we do expect that corresponding
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output it will be amplified version. So, if I say that this is the signal part this is the signal
part so, that same signal it is coming here, but it is coming in amplified form.
So, the ratio of this Vin signal wise of course, Vin and Vout they are defined by a parameter
called gain of the circuit. In this case you may say it is voltage gain of the circuit. So,
whenever we are looking for this analog circuit, the first and foremost objective we try to
perform by this circuit is getting a good gain which is referred here in this case.
So, this gain in this case we have given an example saying this voltage gain need not be
always voltage gain, it may be current gain in that case input signal it will be current output
signal it will be current. It may be power. So, input may be power output may be power or
it may be different combination; for example, input may be voltage and output may be
current.
So, in that case of course, the definition of the gain instead of saying voltage or current
gain, it may be input as voltage output as current so, we may say it is transconductance
gain. So, likewise, if the input is current output is voltage it may be trans impedance gain.
So, whatever it is the first task performed by analog circuit is amplifying the signal with a
predefined or well defined gain. Now the second task or a while it is rather amplifying this
signal, it is assumed that the shape of the input signal whatever the shape we do have its
supposed to be retained in the output signal.
So, in other words you may say that linearity of the input to output transfer characteristic
must be retained. So, if I draw the input to output transfer characteristic say along the x-
axis we are plotting input in this case Vin and along the y axis we are say plotting Vout note
that we are talking here it is only signal part. So, if the signal may be with respect to ground
it may be positive or negative and as we see here this portion, if the signal it is positive
with respect to its DC level we are expecting that the output signal it is also positive in this
case and, but then it is amplified version.
So, if I say that input to output transfer characteristic and if say the x-axis and y-axis they
are having the same scale, the slope of this line if we are expecting it is having again, it
will be much higher than 1. So, likewise, whenever the signal it is negative which means
that we are concentrating say this part and the corresponding output it is here and the in
the input to output transfer characteristic, the characteristic curve it will be like this.
22
So, ideally we want this input to output transfer characteristics. So, this is called input to
output transfer characteristic. So, input to output transfer characteristic. So, this
characteristic should be as linear as possible, but of course, practically this characteristic
may be retained fairly linear around this operating point, it may be maintained linear
beyond some point, but later on it may get it may get saturated. But whatever it is you may
say that over this range of this transfer characteristic, the characteristic you may say it is
fairly linear.
So, ideally we want this portion it should be as linear as possible with a constant slope
which means with a constant gain. So, whenever we are looking for analog circuit,
basically we must be looking for what is again, what is the linearity of the circuit it is
maintained or at least you can say over what range of input the linearity of input to output
transfer characteristic it is maintained. So, these two important aspect we will be expecting
from analog circuit and of course, within this one so, that is the expectation.
So, within this one we must be having some meaningful circuit and in this course we will
be discussing about what are the circuits are there within this block, how they will be
maintained or how they may be biased in technical terms so, that this input to output
transfer characteristic it will be maintained to be as expected as linear and having a decent
or meaningful gain.
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So, this is the first task and then second task; the second task of this analog circuit is, it is
very important it is equally important rather.
The when we say amplification we are also expecting that how this characteristic may be
changing with frequency. So, what you are talking about the second task need to be
performed by analog circuit is the amplification of the signal or maybe even attenuation
of the signal or rejection of the signal based on the frequency of the signal, which means
that it does some intelligent tasks based on the signal frequency the circuit gain it may be
much higher than maybe one while in other frequency signal in other frequency the
corresponding gain it may be lower.
Vout
Which means that if we sketch say circuit gain namely say whatever we have
Vin
Vout
discussed which is a voltage gain defined as and if we observe this gain as function of
Vin
frequency. So, it may be expected that the gain may be remaining high in certain frequency
range and then if you go beyond some point, it may drop towards 0. So, this kind of
characteristics namely based on the frequency of the signal, it provides a decent amount
of gain or very good gain.
On the other hand, if you go beyond some frequency called say cutoff frequency, then
beyond this point the corresponding gain it is dropping or you may say that the signal at
the output it will be much weaker than whatever the signal we are obtaining having this
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frequency component. So, if I say that suppose you do have one frequency component say
f1 here and then you do have another frequency component of f2 in the input signal.
So, which means that suppose we do have one analog circuit which is having a good gain
in low frequency region; that means, it is having very good gain, but then suppose we do
we are feeding signal may be with respect to a DC voltage and we call this is Vin. Having
this Vin two frequency component say f1 and f2; now whenever you are observing the signal
at the output with respect to ground and if you are observing the corresponding Vout, this
component it may be having very good gain like this.
So, we may call this gain it is A at frequency f1; however, on the other hand if the if we
consider say this frequency component it is having very poor gain. So, we may say that
this gain it is A at frequency f2. So, this f A at f1 in this case in this illustration it is much
higher than A at f2 or what I mean is voltage gain Av basically the Av. So, if you do have
a signal it may be having different signal it may not be purely sinusoidal, it may be
combination of these two signals or it may be having different frequency components.
Now, depending on the frequency component, this circuit it appreciates say low frequency
signals, but then it rejects the high frequency components. So, you may say that this circuit
is having some special feature called a low pass which means that it allows low frequency
signal from the input to the output not only it is allowing, maybe it is having a very good
gain it may be much higher than 1. While in the frequency component in the higher
frequency region that may be getting attenuated or removed.
So, this is again for signal processing purpose, this kind of circuit is commonly used which
means that based on the frequency of our interest, we may put some filtering circuit here
within this so, that you can remove this unwanted part. So, we can simply say that this
unwanted part may be rejected, this part will be rejected and this part it will be appreciated
ok.
So, this is the; this is the second task it is performed and of course, based on the application
the requirement need not be always low pass, it may be high pass in nature and for high
pass characteristic as you may guess that in the low frequency region it may attenuate the
signals and in high frequency region it may appreciate the signal or it may be having band
pass which means that over certain frequency band it may allows the signal while it may
reject this part and this part.
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So, there may be different classes of you know frequency characterizing circuit namely
low pass, high pass and band pass. And this kind of characteristic it may be obtained by a
simple passive circuit. So, say for example, if you are having say simple RC circuit you
may be aware of this circuit from electrical technology.
So, if I say that this is input and if I observe the corresponding output here then of course,
this circuit depending on the value of this R and C you will be getting this kind of low pass
characteristic then you may say that what may be the task of this analog circuit is doing.
Well, if it is RC circuit the corresponding gain here low frequency gain here it is
theoretically less than 1 it may be very close to 1.
But if you are using analog circuit in combination with maybe this RC circuit, then this
gain you can make it much higher than 1. So, in case if you want to amplify low frequency
signal and reject the signal in the high frequency component, you may use combination of
active circuit along with the passive circuit. So, whenever we will be talking about analog
circuit it is primarily it will perform signal amplification and also it modulates the signal
based on the signal frequency component namely it amplifies and reject based on the signal
frequency component.
The other important task it is performed by an analog circuit is converting signal from
analog domain or analog nature to digital nature and it may be vice versa. However,
because of the restriction of the time, will not be able to cover this kind of circuit base
namely, analog to digital converter and digital to analog converter in this course.
So, whatever the circuit we will be covering primarily we will be covering the first two
features, but of course, there will be depending on the application there will be wide ranges
of the circuit and we will see that what are the different circuits we do have particularly
different circuit components. Now, let us look into how a how a one analog system how
an analog system looks like.
So, whenever we are seeing some analog system we may say that at top level this may be
say analog system, it maybe is supposed to be performing some task. Namely if we do
have input signal, it is supposed to be giving some what you say processed output signal
and it may be doing some of course, intelligent tasks namely amplifying rejecting all these
stuffs.
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Now, within this circuit, if I want to see what are the different blocks are there, based on
the system you know requirement for some specific application it may be having different
modules performing very specific tasks. So, you may say that the blue color it is say system
or subsystem within that there may be different modules interconnected modules. Now
they are having their own tasks whatever the task it is there and finally, if they are helping
to produce the and the primary output of the system.
Now, within this circuit within each of this module again they are there are different
building blocks. So, these are the building blocks. So, these are modules different modules
and now each of these modules there are different you know building blocks. They are
again they are constructed there they are interconnected and they are constructing each of
these modules.
Now, within this module within this each of this modules if I zoom in to this one, what we
will be seeing there it is different circuit components and those components may be
passive, those components may be active devices and so and so. So, it may be MOS, it
may be BJT, it may be diodes and so and so, it may be inductor and whatever it is. So, if
you see the system essentially it consists of different circuit components.
So, for a given task if you try to see one realized circuit. So, what you can see
architecturally, you will see that from the system we go to the module, from module we
can go to the building blocks and within that there are different components. So, this
decomposition of the system you may say that looking into the system in top down
approach. So, we are starting from system or subsystem and moving towards the
components.
But then if the circuit is already constructed or if somebody is already aware of what are
the constituent blocks are there, this may be the way it can be visualized. So, that is called
top down views of the system. The other view it is that, say whenever you have to construct
this circuit you need to go say bottom to up. So, we have to construct individual building
blocks and then you have to interconnect them in meaningful way so, that you can go from
components to building blocks and building blocks to modules and then finally, you can
construct the system.
So, if you see this analog circuits or analog systems if you see and whatever the topics we
will be discussing, it is better to have this fair understanding of this architectural
27
construction of the system. So, that you can correlate whenever any discussions are
happening either related to components or building blocks, you should be able to correlate
that how those blocks are important to achieve something at the system level.
So, whatever the topics it will be discussed here definitely they are aligned with this
building blocks components and so and so and since here we are trying to make system
definitely we will be starting from component and then we will be moving towards the
building blocks and then building blocks to modules, modules to subsystem and then
system. Of course, the boundary of subsystem and system it may vary depending on the
context.
But of course, there are a distinct boundary from component to building blocks, building
blocks to modules and so and so. So, whatever the different subtopics we will be discussing
in this course, we will be starting from here and let us see how what are the things it will
be there within these components and how they will be planned.
What will be the flow of this content or namely what will be the overall weekly plan
namely we will be discussing with this flow namely it is bottom up flow. So, the bottom
up flow it will be followed. So, we will start from components; in the first week we will
be starting with the components.
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First of all, while we will be connecting different components, we need to revisit this
electrical technology and while we will be discussing about this electrical technology,
primarily we will be focusing on say KCL KVL and so on. So, those are frequently those
topics it will be frequently used. So, after this introduction namely the previous discussion
and today’s discussion we will be moving towards the prerequisite topics related to
electrical technology and KCL KVL.
And then we will be moving towards the different components particularly the non-linear
circuit components starting with diode and how do we analyze the circuit and how this
non-linear circuit it will be converted into quote and unquote linearized with respect to
some operating point and so and so. And then after the diode then we will also cover the
other non-linear device to be more precise the active devices namely bipolar junction
transistor and MOSFET transistors.
There are different other transistors, but of course, these two transistors are quite dominant
in present context. So, our focus it will be only to these devices we may touch a little bit
about their operating principle, and then we will be going towards the characteristic
equation of each of these devices and then those characteristic equations how do we
represent in the form of equivalent linearized circuit called equivalent circuit of those BJT
and MOS transistors.
29
So, that is the plan for the first week. So, then in the second week what we are planning it
is again it will be as I said that it will be the bottom up approach and after the components
now we will be moving to the building blocks. So, in the building blocks before we will
be directly going to the building blocks, how do we analyze a typical building blocks
namely simple non-linear circuit?
When we say a simple non-linear circuit what we mean is that, it consists of a transistor
say and surrounding that there may be different biasing components and so and so. So,
then we will be analyzing this kind of circuit and then of course, we have to put appropriate
bias. So, in second week we will start with that and then we will try to introduce what do
you mean by signal amplification considering this circuit may be one example ok. And of
course, then the once we are comfortable of understanding the amplification of the signal
so, that is the input and this is the output.
So, then next thing is that how do you achieve the linearity, what may be the linearity of
their circuit or limit of the linearity and so and so, namely input to output transfer
characteristic of this circuit as an example or in general for non-linear circuit, how do we
get input to output transfer characteristic and then how do you get the corresponding
linearized part of it. So, something like this around the operating point how do you get a
linearized circuit. So, that is what it will be discussed here.
And then if I restrict this input and output within this linear range, we call the small signal.
So, if you restrict the input within this small signal range, then how do we translate this
small signal this portion as a notion of something called small signal equivalent circuit or
small signal characteristic so, that thing we will be discussing. So, basically this part it is
getting translated here. Anyway I will be discussing the detail, but what is important thing
to understand that there will be some notion something called small signal models of
analog building blocks.
Now, along that of course, we like to draw small signal equivalent of the transistor as well
which may be frequently used for analyzing bigger circuit. So, in the next week then what
we will be covering it is.
30
So, the building blocks we will continue the building blocks and so, we will continue this
building block in the second week. So, we will start with how do we model one amplifier
namely if I want to consider analog building block as a simple black box for its extension
of this black box for bigger system.
Keeping in mind that this black this building block it will be stitched together to construct
bigger circuit. So, we need to understand what may be equivalent circuit of this part,
equivalent circuit of this part so, that constructing bigger system will not be going little I
mean detail nitty gritty of within this circuit instead we may be considering simplified
circuit of this one and this one together. So, those simplified circuit it will it will be called
equivalent circuit.
Now based on the signal here and signal here or the nature of the signal there, we may call
this is their voltage amplifier, current amplifier and so and so, or transconductance
amplifier and so and so. And then once we are comfortable of representing one building
block in the form of simplified model, then we can stitch them together as I said that we
can cascade with another circuit and then we can construct multistage amplifier.
So, basically it need not be only two, it may be having multiple stages and then with this
overall understanding or understanding at abstract level, then we will be moving towards
more practical circuit called common emitter amplifier, which is I should say a very
fundamental building block for analog circuit. So, this is in BJTs realization likewise we
31
do have the MOSFET realization. And as I said that in this course we like to continue BJT
and MOS together side by side so, that we can understand that which is better and in what
context what are the similarities are there so and so.
So, while we discussing each of this amplifier, what are the emphasis will be giving is that
operating principle of those circuits and then biasing, how do we give the active device in
appropriate region of operation so, that it is successfully amplifying the circuit and then
what may be the analysis approach and then we will see that what are the design procedure
it will be followed ok.
So, now in the next week, week 4 we will continue this building blocks, but then and next
thing is the apart from the gain, what we are looking for it is the frequency characteristic
of those amplifiers. So, then this is where we will be discussing how this circuit is
performing in terms of frequency response whether it is band pass or high pass or low pass
those things it will be discussed, and then we will be moving to the transistor model.
Keeping in mind that individual transistor they have their own limitation in terms of the
frequency of operation. Namely each of these transistors they are having their own
parasitic restricting their performance over certain range, and hence each of those
transistor they will be having their own model representing the parasitic components,
which are called high frequency models of those transistors.
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And then after that we will visit or we will look into what are the limitations are there for
common emitter and common source amplifier, which implies that to overcome those
limitations we need to move for some other configuration. So, these two as I said that these
two are very vital configuration, but they cannot do everything. So, we need to look out
for other different configurations.
So, in week 5, week 5 we will be looking for some other configurations; namely common
collector, common train likewise common base, common gate and so and so. So then we
will see that how each of those different building blocks are judiciously getting you know
connected together to get multi stage amplifiers.
And so, basically it need not be just only CE we may be having CE followed by CC and
so, and so, or it may be preceded by another CC and so and so. So, those are the things it
will be discussed in week 6 and then the here so, far we will be discussing the connections
around one transistor. And the biasing arrangements are performed by passive
components, but then we will see that if we use passive components as biasing component
always, there will be its own limitation which invites that can we make a better connection
or better biasing arrangement namely what is called active load.
So, instead of having passive circuit there, can we have some load or can you have some
biasing arrangement performed by BJT or MOS and so and so? So, in the subsequent week
33
so, that is what will be here will be discussing up to the building blocks and then in the
subsequent week will be moving towards the modules.
So, you may recall that our flow our flow it is basically bottom up. So, we are expecting
the by this time we are done here, we are almost done here and then we are at the module
level. So, before we go into the module level circuit, it is very important to understand that
two different types of signaling namely called single ended signaling and differential
signaling.
So, some theoretical aspects and advantages and disadvantages of these two kinds of
signaling it will be discussed and then we will be moving to another special kind of circuit
called differential amplifier. When you are talking we will be talking about differential
amplifier definitely we need to understand the differential signaling and to appreciate that
what is the need of this differential signaling.
So, that is why we first compared single ended signaling with differential signaling and
then we move to this differential amplifier. Then within the differential amplifier which
again consists of different multiple transistors. We will see there the basic structure,
working principle, analysis to get their gain namely differential mode gain and common
mode gain and so and so output suing input common mode range and so, those things we
will see. Then we will be continuing this module in week 8 ok.
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So, we will be definitely in we will be moving towards the module, but then there is a
special kind of circuit again they are block level, but specifically not amplifier some bias
circuits.
So, in week 8 we will be going on discussing about the current mirror week 8 this special
kind of biasing circuit will be current mirror it will be discussed and then subsequently
how those current mirror it will be used can be used for biasing or the main amplifiers they
do to amplify the basic signals in better way, particularly for differential amplifier and then
the common collector stages how those current mirror it will be used. And then will be
actually into a situation to discuss about circuit module and to discuss about a practical
circuit.
So, the basic building blocks will be used there to construct this practical circuit. So, at
this point of time now we are already here maybe some more thing could can discuss at
module level and then we can move to the system or subsystem level.
35
So, before we go into the system or subsystem level, we need to understand another basic
concept called feedback which is very vital for analog circuit particularly analog circuit
for amplifier as well as oscillator.
So, basic feedback theory it will be discussed, different configurations it will be discussed
and what will be the effect of feedback configuration on frequency response of a typical
amplifier those things it will be discussed and then of course, how those feedback circuits
are deployed in practical circuit. So, these concepts particularly these theoretical concepts
it may be applicable for module level as well as it may be applicable for the subsystem
level.
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So, then we are getting ready to move towards the sub-system or system level. So, in week
10 we will be; will be moving to the sub-system circuit. So, there a little bit about theory
and then we will be moving towards the practical circuit. So, there what will do it is that
we will see that the oscillator circuit and what will be the oscillation criteria those things
we will discuss it will be discussed.
And for amplifier in presence of feedback system in feedback connection, how do you
ensure the stability of the circuit that will be discussed. So, these two are of course, more
towards the theory and then it will be discussed towards how those theories are getting
deployed for a practical circuit namely two stage differential amplifier and its stability
aspect it will be discussed there.
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Now, in week 11 we will continue this subsystem. So, in week 11 we will continue with
different subsystems namely, the comparator and then its application, then oscillator and
then square wave generator and so and so. And then week 12 we will be discussing
different kinds of sub circuit namely power amplifier and before going into the power
amplifier we must discuss about the power efficiency of a typical amplifier.
And then we will be discussing different configurations and how the power efficiency of
those circuits are there. It may be noted that for this topic particularly for power amplifier
instead of power gain what is important is that, power efficiency is important which means
that whenever we are drawing some power from the DC source and so, we are drawing the
power from DC source and those sources that energy it is getting utilized to amplify the
weak signal into the to convert the weak signal into the form of strong signal at the output
node.
So, how this input signal it is getting stronger and stronger by this power. And in this case
of course, gain may be important, but whether I should say gain may not be so, crucial,
but what is important thing is that how much the DC power is getting converted into the
output power that is what it is important. So, we will be discussing about something called
power efficiency which means that, how much the power we are drawing from the DC
getting actually to the signal. So, that power efficiency it will be discussed there. So, that
is the overall plan of this course.
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So, what we have discussed in today’s module it is what are the tasks are performed what
are the tasks are performed by typical analog circuits then what are the different building
blocks are there within analog circuit namely how do we split a system into different
modules, building blocks and then components those things it has been discussed. And
then we have discussed about what are the topics it will be there in this course namely
topics and subtopics.
How are they related to those that architecture and then of course, those things we have
discussed about how they have been planned in this course basically how weakly they will
be covered to move from component towards the system level. We also have discussed
little bit about what are the emphasis it will be given in this course, namely the working
principle of the circuit and then the analysis of the circuit and then design approaches and
some of the practical circuits it will be discussed. I think that is all we need to cover in this
module.
39
Prof. Pradip Mandal
Lecture - 03
Revisit to pre-requisite topics
So, welcome to the third module of this online program Analog Electronic Circuits, where
primarily we will be going into prerequisites of this course. Most of the topics you may be
knowing, but the purpose of revisiting this prerequisite is just to see what maybe the
important electrical technology theories are required to understand these analog electronics
better. So, let us see what are the topic we are going to cover.
Primarily Kirchhoff’s current law and its application specifically for the voltage; so, we
will be moving to the Kirchhoff’s law KCL and then KVL and specifically their
application with an example in analog circuit.
So, these two things obviously, as you know from passive circuit we will see that this case
KCL and KVL they are also applicable for a non-linear circuit as well which are very
common for analog circuit. And, then our next one is Thevenin equivalent voltage source
generation from a given circuit which is again commonly used in electrical technology.
And, we will see that what is its application in analog circuit and then we will be moving
40
towards the main topic analog electronic circuit, where circuit elements maybe non-linear
in nature which is in contrast to typical electrical circuit ok.
Whenever we do have some non-linear a circuit we will find that there will always be a
need of approximating non-linear circuit; sometimes approximating an actual non-linear
circuit into another simplified non-linear circuit or it may be all together we can line
linearize non-linear circuit with respect to a point called DC operating point. So, primarily
these are the subtopics we do have in our target today.
So, let us move to you may recall from the previous discussion. Whenever we talk about
say analog system for that matter we do have different levels of abstractions namely system
level, module level then building blocks and then we do have different components. Today
we are going to start with these components and also as I said that we will revisit some of
the prerequisite.
So, the first week of the main program we already have started with introduction to this
course and today we are going to revisit as I said electrical technology and theories. And,
then slowly we will be moving towards this actual circuit namely diode based circuit and
its analysis and then we will be moving to BJT and moss circuit, but of course, this it will
be done in the next class today we will be covering only these two. So, that is aligned with
our first week plan. Now, let us move to KCL and KVL.
41
So, as you may be aware already whenever we talk about Kirchhoff’s current law what we
consider there it is a circuit. So, there we consider one circuit node and we assume that to
this circuit node there may be different elements are circuit elements are connected. Those
elements maybe active or passive or whatever it is, in electrical technology most of the
time we consider with the elements which are resistive or maybe inductive or capacity and
so and so.
So, let you consider this is one circuit node and then we do have say different 4 different
elements. They are connected to another node and so and so, but when you consider say
this node and whatever the elements are connected to this node. And, then if you consider
the current flow corresponding to each of this elements say an element 1 is having a current
of say I1 element 2 is having a current of say I2 and so and so. So, what this KCL says that
all this currents departing this node is actually it is 0.
So, all summation of Ii ′s where, i in this case it is 1 to 4. So, this is equal to 0. So, we
frequently use this you know this equation to find some unknown quantity from some of
the other known quantities. Now, this equation as I said it will be frequently used and say
for example, these elements maybe say resistive and then one element maybe having a say
constant current and the other element may be having capacitive in nature and so and so,
it may be in the inductive kind of element and so and so connected to this node.
42
So, we can consider each of these currents and then we can add all of them those currents
and then we can find what maybe the expression of say some unknown element in terms
of some other known elements. Say for example, if you would like to know what maybe
this current from the expression of known current say this one this one and this one. So,
using this KCL we can find this the unknown quantity.
Now, what definitely as I say that you are already knowing it, but you must also be aware
this KCL is valid for AC current as well. What does it mean is that suppose whatever the
currents are flowing through each of these elements say I1; it may be having a signal having
a frequency say Im1 and the signal frequency it is an ω. So, we can see that this is Im1
sin(ωt) and I2 = Im2 sin(ωt) same ω we are talking about and so and so.
And, then again we can use the same KCL to find some unknown quantity from the known
quantities. So, we can say that whenever we will be dealing with a circuit which involves
a signals. So, each of the signals or each of these currents are having signals maybe time
varying sinusoidal signal or it may be something else there also we can use KCL. In fact,
it can be said that even if we have different currents are having different frequencies say
this may be ω1 this may be ω2 and so and so then also you can apply this KCL.
So, that sort will be frequently using and in case in general say each of this currents are in
time domain. So, in time domain definitely this KCL is valid and what next we will be
considering is that each of this time domain signals if you convert into their corresponding
Laplace domain signal say I1(s) then I4(s), I2(s) and so and so and there also you can use
this KCL. So, once you are representing each of this individual current from time domain
to Laplace domain then you can add up all of these currents in a Laplace domain and then
you can add them together and then you say that the summation is equal to 0.
So, that is what it is very important for us we are using this KCL which you are already
knowing it, but we are also going to extend that in the AC signal domain as well as in
Laplace domain based on our requirement.
43
So, this is what we like to say. Similarly, for KVL also; so, for KVL also we can deploy
the this KVL for AC signal in that case of course, the signal it will be voltage and also the
signal may be even in Laplace domain. So, there also we can use KVL. So, quickly just to
complete that in a KVL what you do suppose you do have a circuit where you do have
multiple elements are connected together and then if they are forming a closed loop.
Say let you consider we do have 3 elements or maybe 4 elements in a circuit and then we
do have different nodes here different circuit nodes are there. And, each of this node may
be having some other elements connected multiple elements they are in here and so and
so. And, then let you call this is element 1 and element 2, element 3, element 4 and so and
so forming a loop like this. And then through this loop what you can do? You can capture
or you can count each of the potential drop across each of this elements say starting from
say this node.
And, then if I say that from here to here the potential difference is node 1 to 2 or we can
say simply you can say that this is V1 drop here it is V1 from negative to positive. So,
likewise if you consider this drop and if I say that this is positive and this is negative and
let you call this is potential drop of V2. So, likewise you consider V3 which is having
positive side here and negative side here and so and so and then KVL suggests that the
summation of all these potential drop across each of these elements forming this loop
namely all this Vi’s together equal 0. So, this is what we know the KVL and this signals
44
each of the signals as I say that they may be in presently in time domain, but they are this
KVL is valid for even in.
So, if we consider V1, V1 may be say Vm1 sin (ω1t), V2 maybe it is having own amplitude
and then maybe having it is own signal frequency and so and so. So, likewise you may
have all of them maybe having their own signal and again you can add all of them and then
you can say that according to the KVL this is equal to 0.
So, whenever we will be dealing with the circuit which is having signals flowing through
each of these elements and if the signals are represented in the form of potential drop or
potential the voltage signal voltage. And, then we can add all of these signals together to
get equal to 0 and this equation maybe a fundamental equation to find expression of one
of these signals in terms of the remaining unknown signals. And, this is also valid as I said
that in general if we do have each of the signals are general in nature and if you convert
those time domain signals into Laplace domain signals.
So, instead of V4(t) if we are representing that signal in Laplace domain then also you can
deploy this KVL; in that case of course, we have to add up all the signals in Laplace domain
and then they add up to 0. So, again this KVL will be frequently using while will be dealing
with the analog circuit.
45
Now, let us move to another important theory in electrical technology what is called
Thevenin equivalent circuit. And, we will be frequently using and interestingly we can see
that how it can be used for not only DC, but also for AC and mixed kind of situation. So,
we will see that mixed kind of situation shown, but let we revisit what we mean by this
Thevenin equivalent voltage source. Suppose we do have a DC source, we do have a DC
source and it is connected across 2 elements say R1 and R2.
So, we do have R1 and then R2 and suppose this is our output node, this may be say
common node ground and then suppose this is the supply voltage VCC. So, what is the
R2
voltage here you will be getting? It is VCC × R2 +R1
and we may use a different notation for
this call VTh, Thevenin equivalent voltage. So, before you connect any load here whatever
the voltage you will be getting that is called the unloaded voltage coming here which is
Thevenin equivalent voltage.
Now, the moment you connect one load here of course the voltage it will not remain same
as the Thevenin equivalent voltage. Depending on the I should say the load here say RL
and depending on the strength of these two resistors who are trying to maintain this voltage
close to VTh you may you will be getting a voltage which will be in between threshold
voltage and of course, this ground.
So, we can say that by connecting this resistor the voltage here somehow it will drop. So,
in case if you are having a simple circuit like this probably after connecting this R L you
(R2 ⫽ RL )
can directly analyze the circuit saying that the voltage now here it will be VCC × R1 + (R2 ⫽RL)
.
But in general in case this circuit maybe fairly complex it may be non-linear and so and
so. So, if this portion it is not really visible to you then how will you analyze?
So, of course, without knowing any information it will be difficult, but in case if we
characterize the circuit looking into this port from outside as the load is seeing this circuit
probably along with this Thevenin equivalent voltage and something called Thevenin
equivalent resistance; you can model this circuit and you can handle the situation even
with a fairly complex situation.
So, suppose this is a voltage source called the Thevenin equivalent voltage and the
Thevenin equivalent resistance which is basically looking into this circuit and you can find
what will be the corresponding equivalent resistance. In this case it is R1 coming in parallel
46
with R2. Now, if I connect the load say RL and if I know that Thevenin equivalent resistance
here and let you call for simplicity say RTh. Then by analyzing this circuit we can say that
by connecting this RL the voltage coming and across this one it is VTh equals to it will be
RL multiplied by sorry.
I should say now it will be different voltage. So, let me call this is Vth′ or Vout whatever
VTh
you say. So, this RL multiplied by the current and the current it is R . In fact, it can be
Th +RL
shown that this expression and this expression they are same. So, I will be not being going
in detail of that, but you yourself can do it. So, we know that if we are having a complex
situation like this need not be having 2 resistors it may be having many more elements,
that can be equivalently represented by these two elements called Thevenin equivalent
voltage source this we know.
Now, this analysis we have done for a situation where the supply voltage is DC. In fact, it
can be extended for a signal also. Namely, instead of having a DC voltage here suppose
you do have a signal source and say this signal source it is applied across say R1 and R2
similar situation. And, then you like to know what maybe the voltage coming here. So, let
me call this is signal voltage vs.
So, the signal coming here across this R2 again it will it is a if you analyze this circuit you
R2
will be finding this is vs × R . Now, in this situation of course, again you can say that
1 +R2
this is nothing, but Thevenin equivalent voltage in this situation. So, whatever the under
DC condition whatever the Thevenin equivalent analysis you know Thevenin equivalent
circuit analysis you know. So, here also you can do the same thing or similar thing.
So, instead of seeing this entire circuit probably the circuit can be represented by two
elements one of them is this VTh and of course, the Thevenin equivalent resistance. So,
now, this circuit it can be replaced by Thevenin equivalent signal source in series with
Thevenin equivalent resistance and then of course, if we do have some unknown load is
getting connected here then you can find what maybe the theory or what maybe the
analysis approach to find the corresponding output voltage here. It will be the same way
as we have done here.
So, what I will like to say here it is whatever you know Thevenin equivalent representation
of a complex circuit it is applicable for AC situation also. But of course, here we have
47
assumed that the circuit is linear, the situation it may be different in case if the circuit
elements are non-linear in nature. So, those things we will see it later, but in case if you
have a circuit let you consider that everything is linear and in case if you have a situation
where you do have DC source as well as signal. So, in that case what may be the situation?
So, we call this is mixed situation. So, let me explain the mixed situation.
To start with we do have a say DC source and then we do have AC signal and then you do
have the potential divider and then you can find what maybe the corresponding Thevenin
equivalent voltage source and so and so. Note that this situation it is fairly simple and
straightforward. So, whatever VCC we do have and then signal source you do have a both
of them are seeing the same circuit. This analysis it will be simpler you may say that I do
have a Thevenin equivalent voltage source and Thevenin equivalent signal source and then
I do have the same Thevenin equivalent resistance.
So, the whole circuit can be represented by this equivalent circuit. So, we can call this is
VTh and we can we may call this is VTh for signal and so and so. Now, this situation you
may not be seeing always the situation may be even different. So, let us see what other
possible situation you may have. Suppose you do have a voltage source and then you do
have R1 and R2 and then you are feeding a signal at this node through different circuit. So,
probably you do have a signal source. This may be the same common node, but then the
signal is coming through different element.
48
Suppose you do have some capacitor and let us assume that this capacitor it is directly
connected here to this node. So, then what may be the situation. So, we may call this is Vs
we do have VCC. So, now, by analyzing this circuit I may be having a DC voltage. I may
be having a Thevenin equivalent resistance ok. So, this is DC Thevenin equivalent voltage
and then we do have RTh and then directly at this node we do have the signal coming there.
So, we do have the signal, the signal same signal it is directly coming here ok. So, of
course, this is a fairly complex, but this signal it is going through a capacitor. It is very
important thing. So, the capacitor of course, we do have this capacity element and this
capacitor of course, it will be seeing this resistor which is RTh ok. So, let me redraw the
circuit and probably you may appreciate that this situation we will be frequently using and
hence better we understand it in our intuition through our intuition.
So, suppose we do have R1 and R2 connected to ground. This node it is connected to a DC

source and then we do have a signal source connected to this node; simplistically I am
ignoring the resistance here. And, what you will be getting here it is of course, we do have
this circuit and then in addition to that we do have the DC part we do have the Thevenin
equivalent resistance and Thevenin equivalent voltage source. So, at this point; so, we do
have RTh we do have the capacitor and then we do have the signal.
So, what kind of situation will you find here at this node? Of course, we do have the Vth
now let us try to see what maybe the situation at this point. So, whenever you are talking
49
about a signal and we are feeding the signal through a capacitor. So, we are assuming this
is changing with time. So, let us plot the voltage coming at this node with respect to time.
So, this VTh it defines the DC voltage level. So, we can say that this is VTh. On top of that
this signal it is getting almost like super imposed. So, suppose it is sinusoidal signal then
you are getting the signal coming here.
So, whatever the signal you are seeing here this signal it is coming from this vs. So, we
can say that this signal is vs. So, it looks like by arranging this circuit we made a good
useful circuit where we do have a DC source. If I ignore say this resistance for the time
being in series with a signal. So, many a times we will see that this DC source it is used to
bias active device, whereas we do have completely independent signal source coming from
another element and we do de couple the two sources DC source and the AC signal source
through this capacitor C.
But of course, you may be wondering that what is the role of this C or what maybe the
suitable value of the C and where shall we get this condition. The assumption here it is of
course, we assume that this signal it will be nicely coming where this capacitor it is really
allowing the signal to coming to this point which means that very important point is that
we assume that the signal frequency whatever the signal frequency we do have it is much
1
higher than time constant or R time constant ok.
Th C
So, if you see we are where do I get this condition. Interestingly we do have CR circuit.
So, this signal if I consider this is input and this is the output we are having CR circuit
which means that in frequency domain we are getting some hypes circuit and the cutoff
frequency this cutoff frequency if it is the frequency in omega then this cutoff frequency
1
it is RC time constant; so, RTh and C.
So, if I assume that these signal frequencies will above this cutoff frequency then only you
can say that this signal it is practically entire amount it is coming there. So, that is how we
are doing. On the other hand, if you violate this condition say for example, if you have a
signal component somewhere here which is less than this one; obviously, it will be having
huge attenuation. So, you may not be getting this nice signal there.
So, the assumption here it is of course, the value of the C it is large enough in combination
with Thevenin equivalent resistance whatever, the cutoff frequency we are getting here the
50
signal frequency is will above this cutoff frequency. So, this is again we will be frequently
using. So, whenever we do have an at any node we do have signal or voltage we do have
one DC part and then we do have the signal part. So, the DC part typically suppose we call
this is the voltage at the output node Vo then we call this is VO the DC part and then this
part signal part will be using small vo.
In other words, the instantaneous value, instantaneous value it is having DC part as well
as the small signal part. This DC level it is represented by a capital VO and then small
signal part it is with respect to this DC level which is having average of 0 which is on top
of this DC level. So, this is the signal part. So, in general we can say that if we consider
some node voltage Vo = DC part + small signal part.
So, whenever we will be dealing with analog circuit both of them the signal part; the signal
part is important, but at the same time the DC operating point is equally important to make
sure that circuit is in good condition. So, whenever we will be dealing with analog circuit
ultimately we have to see some signal which contains the DC part and also the signal part.
And, many a times this DC voltage it plays very important role to give some active device
in proper condition ok. So, that is probably we do have yeah.
So, let me see what are the things are there, we will see whether it can be fine. Now, we
will be moving to another topic the non-linear circuit and its corresponding approximation.
So, we may start with simple DC diode circuit and the corresponding I-V characteristic
51
and then we can see that what maybe the input to output transfer characteristic. So, just to
give you as an example let you consider one simple circuit containing one resistor and one
diode and then we do have a voltage applied across this one. And, then if you are observing
this is the corresponding output for the time being let you consider this is DC voltage, but
it is changing with time slowly.
Or you can say we are slowly changing this DC voltage and then we are observing the
corresponding output. And, then what you may say about the voltage; the obvious answer
probably you may be knowing the diode characteristic and the diode characteristic which
VD∙ q
is I equals to diode current equals to ID = Io (e nkT − 1), reverse saturation current e to the
power the voltage across this diode divided by n Boltzmann constant k and then
temperature in Kelvin; typically, this non ideality factor n we consider 1, q is charge. So,
of course, we do have another part minus one. Particularly this minus 1 part is very
important if the diode is in reverse bias condition.
So, this is the relationship between the current flowing through the diode and whatever the
voltage we do have across this diode. So, this is the voltage across this diode and then this
is the current flow through this diode.
Now, if I change this one of course, the voltage here it may be changing and you maybe
you may anticipate that if this input voltage it is sufficiently high this diode it will be on,
the drop across this one it will be approximately 0.7 or 0.3 depending on whether it is
silicone or germanium diode or you may in general you may say that it is some voltage
call cut in voltage denoted by Vγ. So, we will see that more detail about this circuit
probably we will take a small break and then we will come back to this point.
Thank you.
52
Prof. Pradip Mandal
Lecture – 04
Revisit to Pre-Requisite Topics (Contd.)
Welcome to again the second part of this topic namely Revisit of this some of the
Prerequisite. In fact, prerequisite part we already have completed, but under this one we
are about to start some topic called non-linear; analysis of non-linear circuit.
Now, we are going to talk about analysis of non-linear circuit and the corresponding
approximation. We are considering a simple diode circuit as shown here. It consists of
the input voltage Vin which is applied to a series connection of a resister R and a diode.
The output you are observing is the voltage across this diode Vout. Now, as you know
that this diode I-V characteristic it is non-linear. So, we know that the current flowing
through a diode ID, it is a strong function of the voltage across this diode VD to be more
precise it is exponential, which can be written as
( )
53
Here, IO is reverse saturation current; is non-ideality factor and VT is thermal
equivalent voltage.
So, you may be aware that this IO reverse saturation current its value it is in the order of
10‒10 mA. So, it is very small current and then the it is slightly higher than 1 maybe 1.5
or sometimes 2 but for our discussion this is approximately 1.
And, thermal equivalent voltage VT = . Here, k is Boltzmann constant; T is absolute
temperature in Kelvin and q is charge of an electron. So, if you see this expression as it is
highly non-linear and in case if we have to find the output voltage as function of Vin we
need to know what will be the corresponding current flowing through the diode.
It is developing a voltage across this diode, which is (Vin ‒ ID × R). So, that is the voltage
drop across this one and if I say that this is the voltage across this diode it is VD. So, this
VD and ID must be consistent according to this equation. So, if you see this circuit the
voltage here it is (Vin ‒ IR drop) and since this I it is highly non-linear; if you directly try
to solve this equation to find the Vout in terms of Vin it will be highly non-linear.
This equation pictorially if you see now we can illustrate here by considering this ID
versus VD characteristic plot. So, if the diode voltage it is say 0, then this exponential
part it becomes 1 and then 1 ‒ 1, so that gives the VD = 0. So, at origin the characteristic
curve it is flowing through this origin. And then if you gradually increase this VD
towards maybe voltage called cut-in voltage, then also this exponential part it is still it
may be significant, but since this IO reverse saturation current it is quite small.
The value of this current it will be quite small and if we are plotting this current in say
mA scale, so that current practically it will be still 0. Unless we reach to this voltage
called cut-in voltage and once we reach this Vγ which may be having a value of 0.6 V to
0.7 V for silicon diode, then we do have the Rin this ID current it exponentially grows.
On the other hand, if you consider ‒ve voltage VD is ‒ve then the current it is again it is
very small and we can consider it is approximately equal to 0. So, this non-linear
characteristic curve it can be well approximated particularly for analysis of many analog
circuit that is what we do.
54
We can split this characteristic curve into two parts; one is when VD < Vγ the diode is
off, the other one it is when VD > Vγ so we can say then the diode it is ON.
So, you can see in OFF region this ID = 0 and if it is ON we can say that this is
exponential dependency. And this exponential dependency in the ON region namely if
the VD it is higher than Vγ, then we can say that the ID ≈ IO here assuming = 1. And
this can be further approximated by a linear characteristic curve here.
If the diode is ON then we can approximate this characteristic curve by a straight line.
On the other hand, if it is less than Vγ then we can say the current ≈ 0.
In this approximated straight line what we can say that this ID ≈ ; here ron is ON
resistance of the diode. In fact, this ron it is reciprocal of this slope.
Now, with this approximation we can easily find the corresponding output voltage as
function of this input voltage. So, if you plot the input to output voltage by considering
this approximated characteristic curve, then we can see that the analysis it becomes very
simple. So, let you consider that case.
So, here this approximated characteristic curve is valid for the case where the VD > Vγ.
With this, in fact this characteristic curve can be circuit wise, it can be said that the diode
can be replaced by a voltage drop Vγ and the diode on resistance ron.
55
So, if we replace this diode; by this circuit what we can get here it is the output voltage;
output voltage as function of this input voltage that can be simply obtained by
considering the Vout which is Vin ‒ R × ID.
So, here we are going to analyze the same circuit, but then the diode we like to replace
by its approximated I-V characteristic curve. Particularly, if the voltage drop across the
diode is VD it is more than this Vγ cut in voltage, then the corresponding current is given.
So, this characteristic curve, circuit wise it can be represented by on resistance in series
with Vγ as a voltage drop. So, we can see that the diode can be replaced by the simple
circuit particularly when the voltage drop across the diode it is higher than Vγ.
In this circuit if the input voltage it is higher than Vγ, we are expecting that the voltage
coming to the diode it will be more than Vγ and in that situation we can replace this
diode by the simple model of the diode. And if I consider this, the current flowing
through this circuit it will be .
And if I consider this ron it is much smaller than external resistor R then for all practical
purposes the voltage drop across this diode it is equal to Vγ. So, we can say that if I
consider ron it is much smaller than R, then the output voltage it is remaining almost
equal to Vγ.
56
On the other hand if the input voltage it is less than cut-in voltage, then this diode it will
be in OFF condition and then the current here it will be 0. So, the drop across this
resistance it will be 0, so the output voltage it will be same as the input voltage. So, the
in this characteristic curve what will be getting here it is Vout it will be same as this Vin.
So, this is where the diode it is ON and this is where the diode we can see here as well as
here it is the diode it is OFF. In fact, if I consider on the other hand the actual
characteristic curve then of course, there will be a deviation as anticipated.
So, if I consider this equation and then if we try to get the input to output transfer
characteristic curve, then this curve it will be in the actual curve it will be very close to
this approximation except a small deviation here. Instead of having a straight line there
this will be exponential characteristic curve.
So, as I said that for all practical purposes we may get good approximated characteristic
curve and to simplify the analysis many a times that is what we do. So, now let us move
to a situation where we can feed a signal here along with a DC voltage. Now, let me
move on about this diode circuit again.
So, whenever in a non-linear circuit we are feeding the signal then what may be the
situation? So, we have the resistor, we have the diode and then we do have DC, maybe
this is a DC and then in case if you have a signal coming in series with this DC as I said
57
that depending on this resistance and if we are observing this is the Vout. Now, note that
the input we have a DC so we may call this is VIN, and then we do have vin, these two
together you may say that we do have Vin.
So, this part is having two parts one is the DC part and the small signal part. So, likewise
at the output we may be having Vout having two parts, namely VDC; that means, VOUT in
series with vout. Now, as I said that depending on the value of this resistance either in the
transfer characteristic curve; either in this linear part or we may be this is approximation
or we may be in this part and this is where the voltage across this diode it is Vγ right.
So, this is of course, Vin, Vout. Note that the previous input to output transfer
characteristic we are dealing with DC voltage slowly varying with time. Now, we have a
situation some flexibility we have a DC part remaining constant and then it is having a
time varying signal. Now, if we are having this voltage say 0; that means, we are here
and if you change this input voltage with respect to time.
If you are applying a signal, the corresponding output you will be getting here. So, if this
is how it is changing with time the corresponding signal you will be getting it is it will be
like this. So, slope of this line is basically reflecting this input signal to this output signal.
Please do not get confused that this axis is for Vout. So in fact, this is time varying signal.
So, the input voltage it is going up and down with respect to this point.
Likewise whenever we are drawing this signal what we are drawing it is the voltage here
with respect to this DC level how it is going up and down. So, you may say that this is
representing signal at the output port and this is representing signal at the input port.
Now, if the DC voltage it is somewhere here and we do have the same kind, same levels
of signal which means the signal it is having the same amplitude as we do have here.
Now, here of course, this is the DC level. So, here the voltage if you see here it will be
changing with a small amplitude, because if you see that if the input voltage is changing
over this range the corresponding output change it is only over a small range. So,
depending on the DC level here either here or here we may be you know getting the
same signal as is from input to output or we may be having at the output and attenuated
version signal.
58
In fact, if I consider this idealistic situation where the drop across this diode it is almost
this cut in voltage, then hardly you will be seeing any signal. Now, let you consider the
other situation, probably we understand this part. In fact, whenever we are here if you
see the signal it is seeing R and then ron. On the other hand, if it is the transistor it is OFF
then the corresponding resistance here I have to consider roff.
So, this ron is the diode on resistance in this situation where VD is more than the cut in
voltage. And, the slope is and here the slope is . So, here it is resistance, it is
infinite or slope is 0. So, why in this case you are getting the same signal here because if
this DC voltage it is such that we are here then the diode it is OFF. So, , if I draw the
only signal part we have this resistance and then we have the output and here we have
open circuit. So, this is the situation when VIN = 0.
On the other hand, whenever we consider the situation at this point which means that we
need to consider this on and in that case the same input signal we are applying across this
R and then we do have ron. And, as I said that depending on the value of this ron and this
R we will be getting this voltage called small signal output voltage vout, from this
whatever the vin it is it will be defined by this ratio.
Now, intuitively if this resistance is very small compared to this one you will see hardly
anything coming here. And if it is comparable then you will be getting some attenuated
version on this one. So, this is a situation where DC as well as the signal both of them are
going through the same equivalent circuit. The situation it will be even more tricky if say
this signal instead of connecting here if it is getting a different path altogether.
So, we may be having a situation where the signal it is here and then the signal may be
connected to this output node through some alternate path and then if the Vin we you
have here then we have to see that how much the capacitor successfully feeding this
signal to this node while this ron it is present. Now, if again this and this DC voltage it is
such that if we are here then this capacitor it has to overcome these two resistances
namely this resistance and this resistance coming in Thevenin equivalent form right.
So, in that case the cutoff frequency of the CR circuit it will be constructed by this C and
(rin ⫽ roff). On the other hand, if we are here you have to consider now this and this and
the corresponding cutoff frequency it will be defined by the same C, but then this R
59
coming in parallel with ron this is very interesting thing. So, in that case in this situation I
have a signal, I have this capacitor and then I have the Thevenin equivalent resistance
and in this situation you have to consider this R and then ron coming in parallel.
Obviously, this small resistance it may create a difficult situation for this C to feed the
input signal to the output. In other words, say the cutoff frequency of the high pass CR
circuit it will be primarily defined by this C and then this ron. So, that gives you some fair
idea about the importance of this DC voltage while we will be dealing with the signal.
Most of the cases we may ignore, we may keep the focus only on signal we may ignore
this DC part. But here with this example I am trying to explain that you should not be
completely ignoring this DC part because that really defines the input to output transfer
characteristic and also it defines the input to output.
Whatever you say gain or attenuation based on the condition of the non-linear device.
So, in analog circuit which it will be having frequent non-linear circuit. So, there you
need to understand that keeping this non-linear device in appropriate region of operation
is very crucial.
Of course, appropriate it is relative term it depends on actually where you want to place
either it is here or here based on that the same circuit it may create different situations. I
think mostly that is what I like to cover. So, what we have covered today it is considering
this module and the other model.
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We have revisited the important theory KVL and their applications specifically in analog
circuit and then the Thevenin equivalent circuit.
In our context when we involve not only DC, but also the signals and their application in
analog circuit and gradually have moved into non-linear circuit which is of course, this
may be frequently used. We have considered in today's class a fairly, simple circuit
consisting a one diode and resistor of course, one coupling capacitor. But, that gives you
some idea that quite an extent electrical technology can be extended and used. But, once
we do have non-linear circuit we may required additional in a tricks what it is called
approximation.
So, this approximation again it comes from the experience, what kind of approximation
is valid to represent non-linear circuit in the form of linear. So, we have, we got some
test of a what kind of complexity it will be involved in to. Probably in the next class we
will be moving towards some more non-linear circuit involving BJT and MOS circuit
and their corresponding IV characteristic.
So, whenever we will be dealing with non-linear circuit say may be BJT or say MOS
there the IV characteristic it is very important. So, whatever the IV characteristic they
will be having in the form of equation, in the form of equivalent circuit those things are
very important. And whenever you say equivalent circuit it is nothing, but it is an
approximation. So, this topic again and again frequently we will be revisiting. So, today
we have basically just started to get into analog circuit.
Thank you.
61
Prof. Pradip Mandal
Lecture - 05
Analysis of Simple Non-Linear Circuit
So, dear students welcome to this course of Analog Electronic Circuits and today we are
going to discuss some of our early topics namely how do we analyze a simple non-linear
circuit. So, to start with we will be covering the diode circuits, but then whatever the
concepts it will be discussed here, it is equally applicable in other non-linear circuits as
well. So, let us see what are the plan we do have today and we will see that how it is
consistent with our weekly plan.
So, what we are planning today, it is that we will start with non-linear circuit, we will try
to seek how to find the circuit solution, namely the circuit voltage and circuit branch
currents consistent with the KCL KVL of the circuit and also we will be seeing that the
device characteristic need to be respected. So, then we will start with generalized methods
namely graphical method or graphical interpretation of the method to find solution, then
we will be covering iterative method which is finding numerical solution of a given circuit
with known parameters and then we will be moving to practical methods.
62
So, typically this non-linear iterative method to find the numerical values may be used for
a computer, using computer programs or circuit simulator, but for hand analysis that
maybe bit clumsy particularly when the circuit it grows and then we need some practical
method and we need some working model of diode which can be used to solve the circuit
equations to find a reasonably accurate solution.
And that diode models the working model it today we will see that how it can be deployed
for different examples and finally, will be giving a notion something called small signal
equivalent circuit. So, small signal equivalent circuit not only it is applicable for diode or
a simple non-linear circuit, it is also applicable conceptually for any other non-linear
circuit.
Essentially, in small signal equivalent circuit what we do is we do linearize non-linear

circuit, so whenever we do have non-linear circuit it is very essential to translate into a
simpler form for possibly to manage the situation. So, let we also see what is our weekly
plan and we will see how we are consistent with that.
So, this is our overall plan of this course, namely will be going for analog circuits in the
top down approach, namely the components, then building blocks and so and so. And in
the first week, so we are essentially some here, here and here and in the previous two
classes what we have covered is apart from introduction, we also have revisited some of
the prerequisite, and little bit we already have started about simple diode circuit.
63
Today, will be going little deeper into the analysis of diode circuits and as I said that the
analysis method it will be discussed here it is not only valid for diode circuit, it is also
valid for any other non-linear circuit particularly in the context of analog circuit.
So, let us look into one simple example. So, to start with in fact, we will be having this
example throughout, what we have in this circuit is we do have input voltage which is
applied across series connection of the resistor and diode. And our objective here is to find
what may be the voltage at this output port eventually this is same as diode voltage Vd.
Now, while we will be solving this circuit what to find the circuit solution essentially we
need to find Vout the voltage here and the branch currents here so that they are consistent
with other requirements. So, what are the requirements? We do have KCL. In fact, if you
see at this node the KCL implies that the IR and the Id should be equal. So, this is the KCL.
So, likewise we also need to satisfy KVL. So, in this circuit what we have? We do have
one loop here. So, we can say that KVL is giving us equation Vin = Vd + (V the drop across
this resistor), so you may rearrange this equation in this in different form. So, you may say
that this is Vd + R × (the current flow through this resistor).
So, we do have KVL and also we do have KCL and also we have to give a respect of the
behavior of the two elements, this element and this element. So, if you see here this element
it is having its own characteristic namely it is having some characteristic getting
64
represented this IR and VR relationship. What is VR? Voltage across this resistance. So, as
you know this is linear device, so based on the value of the resistance it will be going
1
through the origin and the slope of this line it is R.
On the other hand, when you see the other element we do have diode element and the
relationship of its current and voltage it is given here, the exponential equation. And what
is this equation? We do have for this element the voltage drop across this element is Vd
and current flow through this element is Id and it is you can say it is exponential kind of
behavior, ok.
Now, while we will be solving this circuit to get the final value of Vout and the currents
and all we need to as I said we need to respect KCL, KVL and then resistor characteristic
and then diode characteristic. Now, before I go into the solution, so let me introduce some
term. In general, if you see here we do have one element series with the other element
connected to ground, this is connected to Vin, incidentally this is resistor and this is diode
and VR to find what will be the voltage at this point.
Note that based on the strength of this element, this element if it is strong then it will take
this voltage towards this input voltage. So, it may pull up this output node towards this
input voltage. On the other hand, if you see the other element the diode in this case it will
try to based on again its strength it will try to take this node voltage towards the ground.
So, we may call this element as say pull down element.
So, likewise the upper element we may call it is pull up element. So, that is how will be
naming. So, we will say that pull up, in this case pull up characteristic is given here and
then pull down characteristic it is given here. Now, as I said that this is a generalized
method, so whatever the discussion we will be having it can be deployed, any other circuit
having these two paths pull up and pull down need not be this is linear or this is non-linear,
in general it can be anything.
And end of the solution or end of the analysis whatever the solution will be finding we
must as I said we must respect the KCL, KVL, pull up characteristic and then pull down
characteristic. Now, if we see that this KCL suggests that this current and this current,
these two currents are equal. So, we can say these two axis they are equal.
65
And on the other hand if you see the KVL the VR if you see here, VR it is essentially, VR I
can rewrite by following this KVL. So, if I use this KVL I can write VR = Vin – Vd. So, we
can say this is Vin – Vd. Now, this Vd and this Vd eventually they are same as Vout, but
unfortunately in this characteristic curve and this characteristic curve they are different.
Luckily, in this x axis equation we do have though this Vd present, but unfortunately it is
having a – sign here and also it is having Vin. So, as is if I try to overlay these two
characteristic equation or characteristic graphs it may not be giving us a meaningful
information. So, before we really try to compare these two characteristic curve on single
one let we try to rearrange this pull up characteristic.
So, we like to rearrange this characteristic so that after rearrangement the x-axis is
consistent with Vd. So, that is the next thing we will be doing. So, please keep in mind that
these terminologies pull down, pull up, basically referring the pull up characteristic and so
and so.
So, let us move to how do we rearrange the pull up equation. So, to start with we do have
pull up characteristic, it is originally we do have pull up characteristic which is going
through the origin as I said and y-axis is IR, x-axis it is VR, incidentally VR = Vin – Vd and
as I said that our main task is to translate this x-axis in different form and of course, the
1
slope it is R. So, the first translation what we will be doing is to get rid of this – sign.
66
So, let us see how we do, to avoid this – sign let we flip the characteristic curve. Namely,
let we plot this IR with respect to – VR. So, what is – VR? This is Vd – Vin and once you
flip this, the axis and the corresponding characteristic curve of the pull up element it is
1
going to the second coordinate where the slope remains R, but of course with a – sign
because the axis got changed.
So, we can say that this characteristic and this characteristic essentially representing the
same thing. So, here now we can see that we do have Vd, but still we do have – Vin. So,
still we need to have some more rearrangement. So, let us see how do we further rearrange.
So, with this – VR if we add Vin; that means, along this x-axis if we say that – VR + Vin
that eventually comes to Vd and let we retain this y-axis as IR.
So, yes we obtain this Vd and of course, by the virtue of adding this Vin which means that
the whole characteristic curve it is getting shifted, right by an amount of Vin. So, we can
say that this point of the characteristic curve it is getting shifted here and its value of this
expression or the Vd = Vin. So, at this point it is Vin, slope of this line; however, remains
1
same – R.
Now, this straight line having the slope information and this point information you can
easily find yourself that this point where this part it is equal to 0; that means, Vd = 0 then
we can say that the VR at this point equals to Vin. So, if VR at this point is equal to Vin
VR
which means that the corresponding current it will be this .
R
VR Vin
So, we can say that this is nothing, but or , because at this point when Vd = 0, VR and
R R
Vin they are becoming equal. So, that is how we define or rearrange this pull up
characteristic in this form. So, originally we are having this characteristic curve. Now, we
are happy to have this characteristic curve where the x-axis it is Vd and y-axis we are
happily retaining to the I-R characteristic. So, if you recall then we do have the diode
characteristic which is Vd Vs. Id that is remaining to be exponential.
Now, we do have the pull down element characteristic here and we do have the rearranged
pull up characteristic near. And both of them the y-axis and x-axis they are exactly
matching. So, if I overlay this two characteristic incidentally we are making this IR = Id
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which means that we are satisfying KCL. So, likewise this two characteristic, this two axis
since they are same we are actually satisfying KVL.
So, if I superimpose this characteristic curve here, what we mean is basically the pull up
and pull down characteristic curves are falling on the same graph and this two axis
matching of this two axis is ensuring the KCL and the KVL. So, along the y-axis we do
have not only Id, but also IR.
And if you see at this point at the intersection point of this two graph what we are getting
is both the curves are consistent to have the same current and the to support the same
voltage. So, whether you call Vd or Vout. So, we can say that pictorially this is our solution
point. So, corresponding to this point whatever the voltage you are getting either you may
call Vd* and you may call this is you know I*, either you call Id* or IR*. So, this current and
this voltage they are nothing, but whatever the solution we are looking for.
So, pictorially what we have done for non-linear circuit is that we are overlaying the pull
up and pull down characteristic curve, but definitely only after this nice rearrangement.
So, first of all we made this rearrangement first step and then we have rearranged further,
so that the x-axis of this characteristic curve is consistent with this one and that is how it
is by combining we can say that we are getting the solution. Now, this is referred as
graphical method of finding the solution of this simple circuit.
Now, in case if you want to find the numerical value of this point what may be the
procedure? That is also again it is generalized method and this circuit is an example.
68
So, let us see what is that method called, ok. So, this is what we already have just now we
have discussed. So, I will just probably redraw the whatever the characteristic we obtained.
So, along the y axis we do have Id and also we do have IR and along the x-axis we do have
Vd which is eventually Vout.
1
So, IR with respect to Vd characteristic is like this, slope is – R, this point it is Vin, and on
the other hand the diode characteristic curve, let me use different color. So, this is the diode
characteristic curve. Now, let us move to how we proceed to find this solution. Maybe we
can start from this point and then we can move to this point and then we can come to may
be this point and so and so on.
So, if we do not know what is the solution here somewhere you have to start and typically
we do start from this point. So, that is how pictorially you may say that from here we
maintain this current which means that at this point we do have IR and if we are moving
horizontally representing that we are equating this IR with Id because this curve is basically
representing Id. So, that ensures our KCL.
And then we come down here to, so this point of course, this point it is not consistent with
(1)
this line. So, we do come down here saying that, we are getting some Vd may be Vd , but
again this is not the solution, but it is we are coming here to make the diode and pull up
characteristic rearrange pull up characteristic consistent.
69
So, we do move from this point to this point and then we come to this point again and then
pull up character pull up characteristic may be consistent at this point, but then pull down
characteristic is not consistent. So, again we move along this direction to find the updated
current. So, that is how it is you know iteratively it is done.
So, let me again elaborate using the equation and here you may say that we call this is I1,
(1)
I1 the voltage you obtain this is Vd and after moving to this point the whatever you say
that the updated current in the second iteration and then wherever this current is
intersecting the diode characteristic namely the pull down characteristic curve we call this
(2)
is Vd and so and so. And they can then again from here you can go up here, so to find the
updated current.
So, you may say that we are moving horizontally satisfying KCL, we are coming down
satisfying KVL and in between you see that this is diode characteristic curve and this is
sorry this is the resistor or pull up characteristic curve. So, while you are moving from this
line to this line we are trying to respect both the elements pull up and pull down element
and at the same time we are also satisfying KCL and KVL, ok. And in a process we are
moving like this and finally, in an almost like a spiral way we are converging to this point
called solution point, ok.
So, let us move to what are the equations involve into this movement to have a better
understanding about the or different understanding rather.
70
So, we already say that we are superimposing the two characteristic curve and we are
respecting this two characteristic curve and iteratively we are moving to the final solution.
It is kind of reputation what just now we said, but this is what we are saying that we do
have this characteristic curve is basically the diode characteristic curve this is the
rearranged pull up characteristic curve and the other one it is the diode characteristic curve
or you can say pull down characteristic curve.
So, in this superimposed I-V characteristic curve of this either you can say Id Vs. Vd or IR
Vs. Vd we are trying to find this solution. So, while will be going through the numerical
procedure called iterative procedure we will be using this equation and also we will be
using this equation and let us see what are the steps involved into that. And as I said that
our movement is going like this coming here and then moving horizontally and then
vertically, and then horizontally and so and so on.
71
So, let us see how we are what are the equations involved. In step1, in step1 using this, so
this is pull up characteristic as I said. So, this is pull up characteristic, for simplicity I will
say up characteristic and we will see that this is down characteristic. And using this pull
up characteristic first we start with Vout = 0. So, you may recall that we do have pull up
characteristic like this and then we do have the pull down characteristic like this.
So, we are starting from say this point where Vd = 0 and Vd is nothing but Vout. So, we can
say that if I assume the Vout = 0, then by using this pull up characteristic we can say that
Vin
IR = and you can say this is end of the first iteration, so this is this level call IR1. And
R
then while you are moving horizontally what we are doing is we are saying that diode
characteristic curve after this iteration is nothing, but this IR1.
And then once you get this Id then you can find the corresponding Vd. So, let me use
different color here. So, we are getting this Vd using this down characteristic curve it is
I
equal to VT ln(Id), Io is basically the reverse saturation current. So, this is again end of the
o
(1) (1)
first iteration, so we call Vd and that gives us new Vout call updated Vout which = Vd
(1) (1)
because we know that Vd and Vout they essentially same. So, we started with this initial
guess, we are landing to some updated value.
72
(1) (1)
In the next step we will use this Vout. So, we will be using Vout = Vd or Vout and using
this pull up characteristic what you can get is, we can get IR this is updated 1 and now we
(1)
will be using nonzero value of Vout call Vd and whatever the value we are getting it is we
(2) (2)
called it is IR at the end of second iteration. So, again this will be giving us Id = IR ; that
means, we are satisfying this KCL, right.
(2)
And then once you are obtaining this Id , you can use the pull down characteristic to find
(2)
(2) I (2)
Vd = VT ln( Id ) and then that gives us updated Vout. So, now Vout is Vd , right. And
o
subsequently you can go to the third step.
(2) (3)
So, we can say that Vout sorry this Vout, new Vout it is Vd and then you can find this IR
(3) (3)
iteration and then that gives you Id , that gives you Vd and so and so on. So, that is how
you can as I said that you are progressing towards the solution and it looks like it is
converging. So, but still we do not know pictorially it looks like converging. So, we need
to check whether actually it is converging. So, how will you do that? Probably, we can use
one numerical example.
So, what you can do? You can take say as an example you can take Vin =10 V, R =10 kΩ.
Say for the diode reverse saturation current let you consider 10–13 A and thermal equivalent
voltage maybe we can take 26 mV, typically that is what we do get at room temperature.
73
Using this values of this parameter you can find the corresponding current here in the first
step, second step and in the third step. So, my suggestion would be please doing it yourself
and verify it with the answer given on the next page. So, what we have it is on the next
page? We do have the solution.
So, I guess you already have done it and you will be or maybe you will be doing it offline
and then verify whatever the solution we obtain. End of the first iteration we obtain say
current is given here and the voltage the updated voltage it is given here starting from 0,
now we obtained this voltage.
And then in the second iteration we are you know improving the accuracy of the voltage
the current as well as voltage and if you see here with progress of iteration you can see
that the difference relative difference of the previous iteration to the next iteration and so
and so they are gradually decreasing and even for the voltage also.
So, it looks like the numerically at least for this example it is converging and but the natural
question is that will it always converge? Yes. There may we cannot give a guarantee, but
of course, probably we can say something about special characteristic of this circuit and
we may say that under certain condition the way we have moved interestingly the way we
have moved from the pull up characteristic to the pull down characteristic and their nature
is helping us.
74
So, let me illustrate what does it mean is that while you are moving in this direction and
then coming back here we are converging to this point. In fact, if you see this shift and this
shift if you take the ratio that is nothing, but the slope of the pull up characteristic. On the
other hand, while you are moving say downwards like this and then moving horizontally
that is nothing, but the slope of the pull down characteristic.
So, the while you are coming from this point to this point essentially that is nothing, but
the ratio of the two slopes of the two characteristic curve and you can see that this is
resistive element and this is exponential curve. Numerically, if you calculate for whatever
1
the solution you have done the slope of this line which is R of course, having a – sign and
we are concentrating on the magnitude.
So, and on the other hand if you see the slope of this line. What may be the slope of this
∂Id
line? It is , and if you see the diode characteristic curve you may say that it is well
∂Vd
I
approximated to Vd . And this current it is in the order of mA.
T
1 1
So, if I say that this is 1 mA and this is 26 mV, so this is 26Ω and this slope of course, 10k,
26
ok. So, what does it mean is that if you take this ratio it is nothing, but 10k and interestingly
for this example it is I should say much lower than 1. So, as long as it is less than 1 there
is a guarantee that this will converge. And in this case it is very small and hence it is rapidly
converging. So, that is why this practical, you know method it is working fine.
Now, the natural question is that if you are not moving in the right direction, on the other
hand if you are moving in the wrong direction maybe in this way and then this way and
then this way then of course, the same situation with wrong movement you will be
diverging out. Whatever the initial guess you do have it will be diverging out. So,
movement of this characteristic curve is very important. I think, let me see what I do have
next.
75
So, before we go to the next slide probably let you take a break and then will be again
restarting from here. So, we have discussed about generalized method, but as I say that it
is an iterative method we may be looking for some practical solution. So, in the next part
after may be short break we will be coming, we will be resuming to look into some
practical method to solve this kind of circuit.
Thank you.
76
Prof. Pradip Mandal
Lecture - 06
Analysis of Simple Non - Linear Circuit (Contd.)
So welcome back, I hope you have solve the numerical problem and as I said that you
yourself have try to see, whether it is converging or not. But, interesting thing is that this
kind of method is very impractical for an analysis, because even for simple circuit if we
have to go through number of iteration and as I said that based on the slope.
The convergence may or may be there or it may converge, but it may take more time
based on this condition. So, it may not be good idea to stick to this one it is better to look
out some other alternative ok. There is a small correction here this supposed to be Vd(3)
anyway. So, let us move to what may be the practical method or can we have method to
solve just by one step itself.
77
Yes, if we consider the same numerical problem, namely if I consider the Vin here and
then we do have the resistance of 10 k, and then we do have the diode here, and then if
we observe the corresponding output, by considering one initial guess. And, this initial
guess it is not just arbitrary, typically we know that if it is silicon diode and if the diode
is on the drop across this diode is roughly 0.6 V.
And, with this guess, if I consider Vd = 0.6. The value of this IR you will be obtaining it
is . So, what you are getting here it is 0.94 mA. Now, if you compare our
previous numerical value, which it was close to if, I recall correctly 0.94023 something
like this mA. So, if I compare this value, this value after third iteration you obtain versus
this one, what we have it is the amount of error it is in fact, less than I should say 0.03 %.
So, we can say 0.03 %.
So, then just by one step itself we can find the solution. This is of course, one indication
that how we are trying to get a practical method by the virtue of guess and proceed by
one iteration, but then some people may say that no I do have a diode, it may be silicon
diode, but I know that it is diode drop it is roughly 0.7. And, if we use a instead of 0.6 if
you use 0.7, then also if you see the corresponding value of this IR is .
So, this is it is coming 0.93 mA. Of course, it is slightly different from this value; it is not
as close as this one, but still if you compare this value and this value. I should say this
78
amount of error it is in the order of just 1 % slightly above 1 %. So, even with this much
of I should say guess, we are getting some solution which is falling within this accuracy
level of accuracy and most of the time for hand calculation, this may be sufficient, most
of the time for engineering problem if it is well within 10 % we may say this is
sufficient.
So, this gives us one indication that probably we may have some practical method to
replace this diode by a something call some model. So, what is that model? We may
consider if the diode is on drop across this diode it is may be around 0.6 or 0.7 and let
you call this voltage is Vγ. And, but then if depending on the current level, the voltage
drop across this resistance diode it may not be remaining same.
So, whatever the little dependency of the voltage and current is there, that may be
represented by probably another element call ron. So, depending on the context we may
say that either this is 0 or it may be non-zero, and typically the value of this ron it will be
small. So, what we are getting is that by replacing this diode by this simple circuit of
course, here we have considered this is equal to 0, that is why with this whatever cutting
voltage of 0.6 we are directly getting this value. And, if you are plugging in this
meaningful value of this ron you will be getting even more accurate result.
So, depending on the situation most of the time we may be using this kind of model for
the diode, if the diode it is in on-condition, on the other hand if the diode it is in off-
condition we may use different model. So, we may say that the resistance of the diode in
off-condition it may be quiet high. So, in that case the diode may be replaced by a simple
resistor where this off resistance it may be quiet high. So, it may be even higher than 10
MΩ or may be beyond that.
So, we do have 2 models; one is this one, another is this one and both of them are we can
say you know linear. So, we may say depending on the condition of the diode we are
going to replace by linear model, but then single linear model is not working we do have
piece wise linear model. So, we do have one model here, we do have another model here.
This slope it is representing finite value of this ron and this is the cutting voltage and this
flat line indicates that roff it is very high ok.
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So, we can say that this is the model will be using instead of using our exponential
relationship for practical purposes. So, instead of this exponential relationship we will be
going for this piece wise linear model.
And, let us see how this model it is it can be used. So, let us move to the piece wise
linear model more detail. So, as I said that if the diode is on we may replace this diode by
simply on resistance, in series with Vγ call cutting voltage, and this r on. So, what is this
ron? How do we get that? The change in diode current with respect to diode voltage is
essentially this is .
And, if you see this that gives us . So, depending on the value of this current and
depending on the value of this VT you can easily find this voltage and as I said that Vγ
you may be having a good guess around 0.6 or 0.7 that may be sufficient.
On the other hand if the diode it is in off-condition as I said that this will be replaced by
the simply off resistance. And, the value of this resistance again if this can be obtained
by considering in cut off region. So, now what we can say that if I replace this Id by
the ( ). And, so if I take derivative of this expression of the current with respect
to Vd what will be getting is will be practically getting .
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Particularly, this will be getting at say Vd = 0. In fact, this is also valid if the Vd is ‒ve;
that means, in reverse bias condition. If the Vd is higher and if it is becoming comparable
with VT of course, this will be deviating from this number. But just to get a since of what
is the value of this resistance of this resistance which is reciprocal of this. So, which is
it is in this case right.
So, which means that it is 26 × 1010 Ω, that is very very high. So, we can say for all
practical purposes in reverse bias condition it is very high. Even, if say diode voltage is
say +ve, but as long as it is less than this cutting voltage, then also we may say that this
resistance it may be remaining in the order of 10’s of MΩ. So, that is the; that is the
circuit model. And, as I said that this two representation of the diode is essentially we do
have exponential equation is getting replaced by piece wise linear model.
So, we do have cut off region and then we do have the ok. So, let me we do have the
“on” region and we do have the cut “off” region here. So, based on these two pieces we
can simpler simplify the circuit. So, let us see how this piece wise linear model can be
practically used for the previous example circuit.
So, let us see the as I said let us see the application of this simple model. Let me redraw
this circuit by replacing this diode assuming this Vin is higher than cutting voltage and
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hence the diode is in on-condition. So, the diode it will be replaced by the equivalent
circuit in on-condition.
So, we do have the Vin here connected across this diode and we call this is Vout. In fact,
we call this is cutting voltage and the voltage drop across the series connection namely;
Vγ and drop across this on resistance ron together it is nothing, but the diode voltage and
this is the R.
So, you may say that this behavior, this part is essentially diode it is getting replaced by
piece wise linear model, essentially this piece wise linear model. So, now, if I replace
this diode characteristic in this form. So, how do I find the solution? Instead of going
through this iterative method can I get even a straight forward, you know straight
forward single step method.
So, here again we may say that I do have pull-up element and it is characteristic is given
here, and the voltage here it is Vin slope here it is with a ‒ sign. And, then if I say that
this characteristic lower element characteristic it is nothing, but this one, where this part
is Vγ. Now, if I know this slope then it will be well and good, but in case if we do not
know probably, you can assume that this is Vγ and then you can find the corresponding
current here, and from that using that Id current you can calculate this ron = whatever the
current will be getting here, say * + .
So, that gives you the slope here. So, that is whatever the IR you will get divided by VT
that will be giving you the slope. So, if you know this point if you know this slope then
you can find the intersection point of the 2 linear lines. So, that is how this equivalent
circuit it can be used? Now, next thing is that how do I use this simple model in case this
input voltage is changing with time and using the same you know equivalent circuit.
So, if this voltage it is say getting increased to some other this input voltage it is getting
increase, we can say that slope remains the same, but then the corresponding pull of
characteristic or rearrange characteristic, it is getting shifted up and we may say that this
may be new Vin call , this may be . So, and now the intersection point is getting
moved up here and the corresponding output voltage instead of this one. Now, it is
getting change to whatever Vout or Vd whatever you say it is going to from the
previous one it was .
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So, likewise if the they Vin it is changing to some other value, say lowered value with
respect to the previous Vin, the corresponding the cutting point of the pull-up
characteristic, rearranged characteristic. Now, it is shifted to some lower value call .
So, now, we do have and . So, the corresponding output here it will be and
all these Vd′s are essentially same as Vout.
So, now for different values of this Vin if I try to see what will be the corresponding Vd
or Vout what I will be getting is input to output transfer characteristic. And, if you see
here pictorial view as I say that pictorial discussion. So, if I change this Vin from say this
value to this value and this value, what I am getting is the corresponding Vout or Vd it is
changing slowly.
So, if you see that the amount of change here it is very small compare to whatever the
changes are there. So, even though Vin is changing over a wide range, the corresponding
output change or Vd change it is very small, that is mainly because slope of this line it is
very high. In fact, theoretically if I say that if this line it is vertical, this line it will be
horizontal indicating that if ron it is 0 at the output you will get only Vγ.
And, so you can say that input or output characteristics is like this, but it will be this
transfer characteristic it is valid as long as the diode it is in, the diode it is in on region.
So, if the voltage in the input voltage if it is less than Vγ on the other hand then load line
or you can say the pull-up characteristic it will be like this and then the it cuts the diode
characteristic at this point. So, if we change this Vin now say instead of this one if you
are changing the Vin here and so and so, the corresponding Vout will also be equally
changing.
So, in other words if the Vin it is less than say Vγ then input and output they are having
the same value. So, the input to output transfer characteristic of the circuit so, if I so, this
Vd is nothing, but as I said Vout. So, input to output transfer characteristic it is having 2
segments one is this one another is this one. This is mainly coming because of the 2
pieces of the diode characteristic. And, this part it is very small having very small slope
depend representing the high slope of this line and this is having fairly good slope.
So, that is the input to output transfer characteristic you can say. Now, having said that if
this voltage it is changing with time, we may be having different way of changing this
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voltage. So, you may say that this voltage may be having a dc value and then it may be
having the variable part.
So, which means that we may keep the dc voltage may be somewhere here and then we
may vary this input with respect to that. Either may be in sinusoidal form or it may be
triangular form or whatever it is. And, then the corresponding output whatever the output
you will be getting that can be directly obtained from this transfer characteristic. In other
words that using this input to output transfer characteristic, you can find what will be the
input to output relationship.
So, that is what will be discussing now instead of varying this input voltage arbitrarily
and may be over a wide range. If you rested this variation within this range and if the in
the variation is having certain pattern, then you can say that this linear segment it is also
say is suggesting that at the output you will also be getting the similar kind of pattern
without having much distortion.
On the other hand if the variation it is large enough and if the diode is entering into the
other region of operation, then of course, the signal at the output it may be having getting
distorted because of the highly non-linear nature. So, for the time being let you consider
situation where this signal variation it is getting restricted over this linear range.
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So, let you move to the corresponding example, where the input voltage. Basically, this
is the same circuit. Now, we do have the input it is combination of it is having
combination of dc part namely VIN and then the small signal part. So, we do have the
small signal part here.
So, as you can guess that if I analyze this circuit you will also be finding the
corresponding Vout, which will be having 2 components; one part is corresponding to dc
part, another part it is corresponding to small signal part. So, before we go into the actual
expression, let me redraw this circuit namely replace this diode by the corresponding
equivalent circuit.
So, we do have the small signal we do have the dc part and then we do have the pull up
element and then we do have the diode part. And, this diode part it is having cutting
voltage in series with this ron. So, this is I should say equivalent circuit. So, now we can
say that the actual circuit is getting converted into equivalent circuit and where what you
are doing is this model whatever we say this working model we are using for the diode.
So, we do have R here same R and we do have the ron here we do have Vγ. Now, if you
analyze this circuit if I consider this two together it is Vin having both dc part and the
small signal part, and if you see what is the corresponding output. I think you yourself
can find that Vout = it is having .
Basically, you are finding this output voltage by super position theorem by considering
this one first making this is 0 and with the second part is making this part 0 and your
giving this Vγ. Now, within this Vin as I said that it is having both dc part and the ac part.
So, if I rewrite this portion in terms of this Vin and then small signal part vin what will be
getting is we can say that, this is . In addition to in addition to we do
have .
So, this part you may say that this part it is coming from the dc part and the cutting
voltage of the diode you may say that it is not changing, but this part probably it is
changing with time and probably it is carrying a signal. So, this vin may be function of
time.
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So, this Vout you may say that it is having 2 parts namely, VOUT + small signal vout. So,
this small signal vout it is basically this part. So, we can see that VOUT or dc part is having
this expression and the small signal vout is ( ) .
So, you may say that this part it is transfer function of the system, which is transforming
this input may be in time domain this is also may be in time domain, but whatever it is
the signal it is getting reflected to the output. And, if you are not changing this point this
operating point, you may say that the corresponding ron practically remains constant.
So, we may say that the gain of this circuit remains constant. So, let we see the
corresponding input to output transfer characteristic curve and let we reinterpret what are
the things are there, please remember that this small signal part and then dc part in the
next slide.
So, let me rewrite this Vout part. So, we do have Vout is having dc part. I am just simply
denoting this is VOUT. So, you may assume that this is function of VIN and Vγ and so and
so and in addition to that we do have the small signal part, which is ( ) right.
So, this is what we already have now? What is the interpretation in the transfer
characteristic curve? So, you may recall that in the input to output transfer characteristic
curve. If, I say that this is the Vin having both dc part as well as the small signal part and
along the Y-axis we do have the Vout, and we say that the transfer characteristic curve it
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is fairly linear may be having a small slope. As long as this is not exceeding this Vγ
voltage, then we are safe. And, if I say that we do have Vin probably VIN with respect to
that we are applying some small signal vin.
So, over that with respect to VIN we are applying vin and changing this and the
corresponding Vin. What is the consequence here? At the output corresponding to VIN
you are getting VOUT, which is of course, it is function of VIN and R and then ron and Vγ
and so and so.
And, in addition to that what you are getting is because of this small signal applied at the
input we are also getting corresponding output. So, you may say that here we are getting
small signal output and this small signal output it is given there.
Now, many a times for analog circuit we may be keeping this point this dc part constant.
In other words we like to keep this point constant and then we like to apply this as signal.
So, it may be sinusoidal it may be non-sinusoidal or whatever it is and we like to keep
our concentration only over this range. So, if you vary the signal here you will be getting
the corresponding output here. And, we like to see the relationship between the small
signal inputs to small signal output.
So, what does it mean is that, our main interest for analog circuit instead of really sees
this much of dc shift and all we maybe rather more focusing on vin to vout, small signal vin
to vout characteristic curve, which means that we are basically concentrating on this part.
What is this part? This part of the input to output transfer characteristic curve, it is
getting shifted to the origin of this new graph. So, we can say that operating point is
getting shifted to the origin of this characteristic curve. And, the line segment it is getting
retained, it is retained.
Now, this characteristic curve. So, here if I apply input signal naturally I will be getting
the corresponding output here ok. So, here while we are retaining the dc part it is referred
as large signal input to output transfer characteristic curve and this is referred as small
signal transfer characteristic curve. So, what is the, what is the advantage here? First of
this entire characteristic curve it is not going through the origin whereas, this is going
through the origin. And, we are keeping the circuit in fact, the analysis probably simpler
because we are dropping the dc part ok.
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So, this whatever the translation of the characteristic curve from large signal to small
signal, it is circuit wise it is you may say that the original circuit we are representing by
another equivalent circuit call small signal equivalent circuit. So, this translation of de
transfer characteristic curve is basically circuit wise representing the circuit in a even a in
a simpler form. So, let see what is that simpler form?.
So, now we do have something some notion calls small signal equivalent circuit. So, to
start with we do have the signal in series with the dc part and then we do have the
resistor, we do have the diode part, along with the cutting voltage and then we are
completing the circuit.
So, this is what we said it is the large signal equivalent circuit consisting both Vγ and ron.
Now, whenever we are talking so, this is the large signal. Now, let us see what is the
small signal? So, in small signal what will be doing is that we will retain this part; we
will retain this part and the dc part. So, whatever you say VIN, we like to remove it, we
like to remove this one, we like to remove this one and we like to retain only this one.
So, the left out circuit what will be having here it is the signal part the same resistor R
and then we do have the ron and the corresponding Vγ it is completely dropped, this is vin
and whatever the corresponding output will be obtaining here note that this is vout. Here,
we are having Vout containing both DC as well as AC whereas; here we do have only
small signal part.
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So, this is referred as small signal equivalent circuit and as you can see here, what is
what the rules are? The dc part we are making it 0, the dc voltage whatever even though
it is coming from the you know device we are dropping to 0. And, the rest of the things
we are retaining and we are retaining of course, the small signal part.
So, that is the rule. And, graphical interpretation what we said it is translating the large
signal transfer characteristic curve to different graph and transfer characteristic curve it is
going through origin. This is very vital point that it is going through the origin, which
means that this circuit is basically representing linearize version of the original circuit.
Even though this circuit it is non-linear, but whatever the characteristic we are getting
and the equivalent circuit we are getting here it is nothing, but linearization.
So, whenever we are talking about small signal equivalent circuit I should say that it is
linearization of the large signal equivalent circuit. Now, we do have whatever we have
discussed is that the original circuit from that we obtain large signal equivalent circuit,
this large signal equivalent circuit it will be helping us to find the operating point. And,
in fact, that operating point helps us to find the value of this ron.
So, definitely that is important also we have to check whether we are in the linear range
of large signal characteristic. Probably you can find what may be the limit up to which
this linear characteristic is valid and then we move to small signal. So, it is having
importance large signal equivalent circuit it is having importance, but once you are very
sure that these point it is a good point and then better we translate to that the entire
circuit in to a small signal equivalent circuit or linearizing the circuit.
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So, as I said that we are linearizing the circuit and we have enlisted what are the different
advantages. Note that we are linearizing non-linear circuit with respect to the operating
point or quiescent point. So, first we find the operating point and then we are basically
linearizing the circuit. So, it is expected that once you linearize probably the obtain
circuit is simpler we already have seen that.
And, most important thing is that this will simplify the analysis and the other vital point
is that since the input to output transfer characteristic it is going through the origin of our
small signal transfer characteristic. So, super position theorem it is valid and that is very
vital to simplify circuit whenever we do have multiple signal sources. So, these are the
important advantages.
And, that is why for analog circuit we always do find the non-linear circuit, then we
move to small signal equivalent circuit or linearize circuit. And; however, you need to be
very careful word of quiescent that validity of the linear circuit we have to be
maintained. And, the signal level should be such that we should restrict our you know
voltage and currents within the linear range of operation. I think what you can do it is
probably you can try to take this numerical problem, and you can try to solve this.
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So, I have frame this numerical problem slightly I have change this voltage and rest of
the things I have kept as is. So, what you have to I think you yourself can find. So, you
need to find this Id and Vout by iterative method we already have discussed. And, also
practical model method considering Vγ = 0.6 V and ron probably can calculate the value
of ron which is non-zero. And from that you can find what will be the corresponding Vout,
of course that will be slightly different from Vγ.
And, then you can draw the small signal equivalent circuit you can find the small signal
vout, so this is small signal vout, for small signal input voltage here. So, this small signal
input voltage it is given there you need to find what will be the corresponding vout? So,
there may be 2 approaches; one is directly you can use large signal model, you will be
finding that it is bit tedious even though it is simplified model of the diode has been use
there and then you can see how easy to use the small signal equivalent circuit?
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So, in this part of our discussion what we have covered it is basically we are analyzing or
we have analyze non-linear circuit, diode circuit as an example to find it is solution. We
have discussed two generalized method one is in fact, both of them are essentially same
one is pictorial representation and where we have discussed how to rearrange the pull up
characteristic to you know get it suitable in combining form with a pull down part.
And, then the method of the iterative method of finding the solution, then in the second
part we have gone into the practical method of finding solution. Namely, using you know
guess and solution one step solution, which suggest that it is better to use some simpler
model, working model of the diode namely piece wise linear model.
And, that model we have discussed to with the same diode circuit and then we have gone
into you know linearization of the circuit. Basically non-linear circuit we can linearize
and we have discussed about a notion call small signal equivalent circuit and it is how
we obtain the small signal equivalent circuit. I think that is all I do have now so, I think
we will be moving to the next topic in the next class.
Thank you.
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Prof. Pradip Mandal
Lecture - 07
Revisiting BJT Characteristic
So, dear students, welcome back to this analog electronic circuits, one of the early
modules of the course. Myself Dr. Pradip Mandal from E and ECE department
associated with IIT, Kharagpur. So, today’s discussion, it will be on BJT characteristic.
From semiconductor device, you may be aware about the BJT, but today what will be
discussing is that its basic characteristic, what are the characteristics are necessary for
understanding analog electronic circuit.
So, essentially I-V characteristic is our main focus, but to appreciate the I-V
characteristic we need to get little bit into its working principle, and then subsequently
will be moving to the equivalent circuit. So, today our main target is to cover the basic
working principle along with the characteristic equation.
So, let us see the plan overall plan. So, today’s plan is to cover the basic structure of
BJT, and typically what are the bias conditions are followed for BJT particularly in
analog operation. And then will be starting with current equation of normal or standard
p-n junction it may be silicon or germanium. And we will start with isolated junction
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then will be gradually moving towards what are the two junctions, and particularly if the
two junctions of BJTs are in the near vicinity what are the interactions are happening
between the two junctions current. And particularly, if one junction it is forward biased
other junction is reverse biased, and then what may be the corresponding terminal
current.
So, this is the overall plan, the basic structure and bias condition of BJT, then current
equation particularly the terminal current equation of BJT.
So, let us see what our weekly plan is and let us see how we are there now. So, this is our
weekly plan and as you know that we are in this module particularly components and
device characteristics. And so far we already have discussed about the first three items or
plan for week-1. And today we are going to BJT; MOS characteristic will be seen in the
next class. So, this is the overall plan today and it is well synchronized with our weekly
plan.
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So, if you see the BJT as you may be aware from semiconductor device, what it is having
it is the basic structure it is having two junctions, say for example, n-p junction and then
p-n junction. And in this n-region, we do have electrical connection; we may be aware of
this called say emitter. So, likewise in the other side of the device the other n-region, it is
having a terminal called collector terminal, then the middle portion in between which is
p-type. And in this p-region, it is also having one terminal through which you can apply
voltage and you can observe the current and this terminal it is referred as base.
And as you as you can see that there are two distinct junctions, metallurgical junction
namely junction-1; so, this junction may be referred as base to emitter junction and so
this is base to emitter junction. Likewise, the other junction it is base to collector
junction. And pictorially though it is shown here the cross sectional area may be same of
this junction and this junction, but need not be.
Structurally, if they are different most of the time they are different and this junction may
be having a cross sectional area of say A1; the second junction may be having different
cross sectional area say A2. So, likewise there are some other important characteristic it
is having for example, this region even though we call n-region, but actually it is highly
doped n-region. So, you may say this is doping concentration why it is higher than
whatever the acceptor concentration will be having in the base region.
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So, I should say emitter is having the highest doping concentration compared to the other
two. So, it is having its own reason, but that detail I may not be getting chance to get
into, but let us see what is supposed to be the condition, so we deploy particularly what
bias condition we deploy for junction-1 and junction-2 and under that what are the
terminal currents.
So, in normal circumstances, particularly for analog operation unless otherwise it is

stated, base emitter junction the junction-1 it is forward biased which means that the p-
region it is having a +ve voltage with respect to the emitter n-region. So, this junction-J1
it will be forward biased by a voltage called base to emitter voltage.
So, on the other hand, base to collector junction again for normal operation, so this
junction-J2, it is reverse bias which means that this n-region it is having higher potential
than the p-region, ok. So, this is you may say this is VCB. So, this VCB this side is +ve
that is making the second junction getting reverse bias.
Now, we know that through a p-n junction if this junction is say a forward bias, and if
this second junction if it is far away from this junction, then we know that this current it
will be having exponential dependency of this forward bias on the forward bias voltage.
So, if I ignore the second junction and if I concentrate only junction-1, and if it is getting
forward biased by VBE, the current it will be flowing through this base terminal into the
device, the same current it will depart, the emitter terminal. And they are expression of
the both base current and emitter current it is given as say some constant we will see that
what is the constant involved multiplied by e power the forward bias voltage divided by
thermal equivalent voltage ‒ 1. So, this is nothing but a typical junction current.
In fact, this is true even if the junction it is getting reverse bias. In other words, if I say
that if we concentrate only at this junction and if we are biasing this junction by this, and
if I say that this is away from this junction, and then again because of this voltage the
current may be flowing through this loop. The current it will be entering to the device
through this collector terminal and it will depart the base terminal. And this junction
again it’s current, it will be well-defined by the same relationship, similar kind of
relationship.
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Of course, in that case this will be VCB, ok; so, if it is VCB and if it is large and then this
will be ‒ve and typically this part it will be much smaller than 1. So, the current you will
be getting whatever you know (reverse saturation current × ‒ 1). And the polarity of
course, it is getting reverse namely, it is the current is not really through p to n-region, it
is rather n to p-region.
So, this diode equation which we are already aware of, this may be valid only if these
two junctions are apart from each other. However, for transistor action, particularly for
this the BJTs action, we need these two junctions should be in the near vicinity. So, it is
expected that the current flow through this junction-1 and junction-2, they are going to
be interrelated.
So, what may be the corresponding expression of the current if these two junctions are
nearby, so that is what the main discussion today will be going through. So, let us see
little detail of this structure and let me focus in this junction.
So, here we do have the junction-1 portion we are focusing on. We do have zoomed this
part and then again we do have VBE voltage base to emitter voltage we are applying. And
since this junction it is getting forward biased of course, it will be having depletion
region around the junction. And, then across this junction the electrons it will be going
from the n-region to p-region because we do have lot of minority carrier majority carriers
here electrons in this n-region, they may be moving to the p-region, and of course, the
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while they are entering here they will be considered as minority carrier. So, likewise
holes are also moving from the p-region where it is majority carrier, but then once it is
entering into the n-region they will be working as minority carrier.
Now, beyond this depletion region as we are applying this voltage it is expected that in
steady condition, the carrier concentration it will be having exponential fall beyond the
depletion region. So, let us look into this profile of this minority carrier concentration
particularly around near the junction-1. And the assumption it is that J2, the second
junction we assume that it is very far away from this junction. So, it may not be really
influencing this minority carrier concentration.
So, suppose we do have this is the metallurgical junction and it may be having around
that significant depletion region, but of course, it depends on the amount of bias you do
have around there. And so we do have right side we do have the base region. So, this is
the p-region, and so this is the junction-1. And left side, we do have the n-region.
Depending on the doping concentration in the n-region, it will be having the minority
carrier concentration. In the neutral region, you may say that minority carrier
concentration here it is p in the n-region naught.
So, likewise in the p-region, the corresponding minority carrier concentration will be
may be denoted as in the neutral region, it may be denoted as n in the p-region in neutral
condition. And if it is getting forward bias, so from the p-region, it is expected that a lot
of electrons it will be penetrating. And as a result the, so if its concentration beyond
particularly beyond the depletion region, it will be having exponential falling this.
So, if you see here this exponential fall, it is coming due to two reasons; one is we do
have majority carriers n here, which is getting a junction here, and this junction it is
getting forward bias. So, what you can say that compared to its npo in the neutral region
whatever the minority carrier concentration we do have, near the junction we do have
this excess amount of carrier. So, if I do not say this minority carrier concentration say n
in the p-region as function of distance say x. And let us say that x is starting from here,
and it is going in this direction. So, x is +ve in this direction, it starts from the edge of the
junction say 0.
So, whatever the concentration we do have here at this point, we may say that this is
np(at x = 0). Of course, this is a strong function of whatever the forward bias we are
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applying here. And in fact, from Boltzmann equation you may say that np(0), it is having
exponential dependency on this VBE. So, this is what it is given np(0) which means np(at
x = 0) at this point, it is equal to npo neutral region concentration multiplied by e power
forward bias divided by thermal equivalent voltage.
And this npo of course, it depends on whatever the acceptor concentration we do have
and its expression is given here; so, which is equal to intrinsic carrier concentration
square divided by acceptor carrier concentration. So, based on the information available
here, probably we can find based on the forward bias, we can find this carrier
concentration here.
Now, as you are moving away from this edge of this depletion region towards deep into
the base region as I say that it is having exponential fall. And this fall it is you know
expression is given here np(x) equals to whatever the difference we do have which means
np(0) ‒ npo. So, this is the step and then it is having exponential fall which is indicated by
So, based on the Ln of course, the penetration of the carrier towards the base it may vary.
So, of course, it depends on the carrier whether it is electrons or holes. So, you may say
that this is a constant in length. And in addition to that we do have this npo, so that is why
we are writing this part. So, first part is the shaded part and the last part it is whatever the
height we do have. These two together it is giving us np(x).
So, likewise if you see the left side, you may say that similar kind of profile we do
expect, so but it may be having different levels. So, this is the profile of minority carrier
concentration in the n-region, which means that this is pn as function of distance. So, let
us say that this is distance is x, where, sorry y. So, y is indicating that it is going from 0
towards the emitter depth. So, you may say that this is y; in this direction it is +ve.
So, similar kind of expression similar to np(x), we can find the expression of p and y. We
will be finding that soon what will be the corresponding expression, but since these two
penetrations of the minority carrier whether it is holes or electrons since it is similar, let
you focus only one kind of carrier concentration. And since these carriers are moving
across this junction of course they are charged particles. So, as a result they will be
contributing current flow.
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So, for example, whenever these electrons are coming from the n-region to p-region, so it
is going from n-region to p-region, and as it is a charged particle, it is providing a current
in this direction. So, likewise when holes are moving from the p-region to the n-region,
namely base region to emitter region; and it is charged particle and incidentally this is
+ve charged particle so it is contributing the current in the same direction as the
electrons. So, though the electron and holes movements are opposite, but due to their
opposite charges, both of them are contributing the total current.
So, you may say that this junction current it is having two components; one is due to the
movement of the electron another one is due to the movement of the holes. And so as the
electrons are moving into the base region towards the or at the edge you may say that
most of the currents are carried by the nature of the movement of the charge, it is
diffusion kind. And as it is progressing inside the p-region, since we do have lot of holes
are available these electrons may get recombined.
So, as the electrons are moving inside the base region, the current carried by electrons it
may drop as it is getting recombined. And the responsibility of carrying the current of
course, it will be, partially it will be done by the majority carrier concentration. And of
course, along this across this device at any cross sectional you know area; we can say
that the current remains constant.
So, to find the net current what you can do you can find what may be the current at this
point coming due to the diffusion of the electron plus whatever the currents are coming
at this point due to diffusion of the holes. So, you may say that the total current, it may
be obtained just by considering diffusion current at x = 0 plus diffusion current due to the
holes at y = 0.
So, you may say that this current is having two components, let me say that this is due to
electrons In1 + Ip1. 1 stands for the first junction; n stands for the electrons and the p
represents the +ve charge or the holes current. So, we understand that because of the
diffusion of the minority carriers, there will be a current flow. Let us see what the
equation of that current flow is.
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So, you may recall this minority carrier concentration as you have discussed in the
previous slide. So, this is what it is given there in the previous slides and the expression
of np(0) is given here and npo and np(at x = 0) are given here.
Now, electron diffusion current it is whatever you say that In1 equals to minus charge of
electron, cross sectional area, diffusion constant and then gradients of the carriers. So, if
I say you let me redraw here. What we have seen that electrons are getting into the base
region and it is having a profile like this. And this profile it is given expression of this
profile it is given here. This is x and x = 0 here. And at this point, whatever the
concentration it is np(at x = 0), and whatever the concentration at other points it is given
by np(at x).
Now, if at any point, if you take the gradient of this np at any distance at x, then it will be
giving us the current the rate at which the electrons are now getting into the, I should say
moving from left to right. So, at any point, if you take the gradient here, and then if you
multiply charge, cross sectional area and then this diffusion constant, you will be finding
the net current carried by electrons. But of course, the since the electrons are moving in
this direction, the corresponding current it will be right to left. And that is of course, it is
coming due to this the ‒ sign, because the electrons are having ‒ve charge.
So, if I you say this expression of np(x) and then if I take you know derivatives with
respect to x, then what you are finding is that In1 equals to having this expression. Now,
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this part, of course, this part it is as I say that it is strong function of VBE. So, we may say
that this part it is ( ) . So, since I do have npo here npo here, probably you can take
npo outside, so we will be having . So, that is how the after rearrangement of this
equation or rather using the expression of np(at x = 0), we do find the expression of In1
equal to this one.
Note that it is function of x and as you can guess that as you are progressing inside the
base region, so this side is base region, and then current diffusion current carried by
electrons of course it is coming down exponentially. And at this point, we do have the
maximum current. So, at x = 0, this part it is getting removed; so, what we have it is at x
= 0, the current carried by electron is this one. So, of course, as you are moving as I say
that as you are moving away from this point x = 0, the current it will be then carried by
partially it will be carried by holes the majority carrier.
It may be noted that this exponential fall it is valid only if I assume that recombination it
is primarily dependent on the minority carrier. In other words, if the np(x) is much, much
lower than the available concentration here in the base region namely NA, then we may
say that it is low level of injection.
So, whatever the approximation we have done here, we have assumed that the
penetration here it is very low or the minority carrier concentration here it is much lower
than whatever the majority carrier concentration we do have in the base region. So, that
normally it is assumed that it is valid low level injection.
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Now similar to this movement of the electrons as I said that holes are also moving across
the junction so, they are also contributing the current. And it is having similar kind of
you know expression only difference is that it is the movements of the holes are from
right to left. And suppose this is the edge of the depletion region.
So, here also it is exponential change of the minority carrier in the n-region namely pn(y),
and y is changing from 0 to higher value here. And rest of the things it is similar, only
thing I must say that here it is pno, it is intrinsic carrier concentration square divided
by ND. So, this ND is donor’s concentration in the emitter region, ok. And rest of the
things is it is similar and of course, again this at this point whatever pn(0), it is function
of the forward bias, exponential function of the forward bias.
So, I think that it is very clear that now if I take derivative of the pn(y) in terms of y, we
can get the expression of the current carried by holes. In fact, similar to the previous case
if you see that you will be finding the expression of Ip1 current carried by holes, it is
similar. In fact, this part again you may replace by ( ) .
And if you do so, then here you can find that pno it will be available here, then to get the
current at this point which means y = 0, you can drop this part at y = 0. So, the
expression of Ip1, it will be qA1Dp, this is different parameter multiplied by pno here and
and then of course, this part it is dropped.
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So, the total current across the junction, so you may recall now the junction it is we may
say that this is isolated junction. We are not really concentrating on the second junction;
we are concentrating only at junction-1 and then we do have the VBE here, we do have
the emitter terminal here and the base terminal here.
And whatever the current is flowing through this junction due to this forward bias, of
course, we may say that this is also base terminal current and also it is emitter terminal
current IB and IE. They are also having the same exponential dependency on VBE
multiplied by Ino and Ipo. So, what is this Ipo, it represents qA1Dp and pno. So, this part it is
essentially qA1Dp and then pno.
So, likewise this part, it is having similar kind of expression it is q, same A1 cross
sectional area, but of course, it is having Dn and npo. Note that this npo and pno, they are of
course, strong function of the doping concentration in this portion and this portion
respectively. But if they are remaining constant, so we may fairly say that you may say
that this part is remaining constant. Now, similar kind of things it will be obtained for
reverse bias condition.
So, if I consider the other junction namely junction-2 and if I say that this junction it is
reverse bias, and then similar kind of expression will be getting assuming that the J1, it is
far away. So, now, we are concentrating at J2 and J1 may be somewhere here. So, this J2
junction now it is reverses bias.
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So, under reverse bias condition, in fact, it will be interesting to see that the previous
expression, it is valid for this reverse bias condition also. But, interesting information
here I like to share here, it is if I consider this is the depletion the metallurgical junction,
and then if I say that this is the depletion width around this J2. So, we do have the
collector region; we do have the base region.
So, we may say that this is the collector region n-type, base region p-type. And if we do
have 0-bias we know that the minority carrier concentration it will be like this. But if we
are applying reverse bias, the influence of the reverse bias here it is interesting to see that
it will be approaching towards 0 like this; so, same thing the other side also.
So, this is of course, p-region and you may say that this is np(x) or let you call this is y.
Now so, I have used x here so, let me call this is x and likewise we may call this is pn(y).
Now, you may say that x is it is sorry y is this going from say from the edge to dip into
the collector region and x is going from 0 to dip into the base region.
So, you may say that now we do have rather deficit with respect to npo, and then this side
it is pno. But then expression here it remains same. In fact, this expression, it will be
interesting to see that yeah, I should have given this is VCB, but a ‒ sign, VCB ‒ sign
reverse bias.
And due to that you can see that this profile, it is going to 0. As this VCB it is going
higher and higher with reverse bias compared to VT if it is large, so this part it is going to
0. So, that means, the minority carrier concentration it starts almost at the edge with a 0,
and then exponential it is rising like this, so that is the main difference. Otherwise the
expression of the current remains the same as whatever we have discussed in the
previous slide.
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So, just to conclude the current here, the reverse bias current it is essentially it is
remaining same as the previous one for both electrons as well as holes. And in fact, this
part it will be very small. So, you may draw this part and this part. So, we will be having
a ‒ sign and np(0) and this part. And this part at x = 0, you may say that this is 1; at x = 0,
this becomes 1, so becomes 1. So, we do have only this part.
So, under reverse bias condition, In1, well approximated by qA1Dnnpo. By the way now I
should use rather A2, so we are talking about second junction and this is current is also
second one. So, we can use subscript 2. So, likewise Ip2, it is well approximated by the
qA2Dpnpo. But you have to remember that this npo, sorry this is pno, it depends on the
donor and acceptor concentration in the collector and the base region that you have to
keep in mind.
And if you see the whole device, now we do have the base, this is the base region, this is
the collector region, and here we are applying VCB. So, the current is actually flowing in
this direction. So, you may say that this IC and IB due to this VCB both are equal to In2 +
Ip2, where expression of this In2 and Ip2 s are given here. So, this is what is expected that
the two junctions if they are completely isolated, then their currents it may be expressed
in terms of a diode current which we are already aware.
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And so in the next class or next session rather, we will be observing that what will
happen if these two junctions they are approaching to each other.
So, in case if these two junctions are approaching to each other, so then what will happen
is this base terminal it will be common terminal, and we do have this voltage to make J1
forward bias, VCB to make the second junction reverse bias.
But, interestingly what you are expecting is that if this electron it is in the near vicinity of
this junction, and we do have strong reverse bias. And this electron may be directly
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jumping into this one, and it may create abundant availability of the electrons and
contributing significantly to this collector current. In other words, based on this voltage
the electrons are getting injected into base region, and they are nicely collected by the
collector terminal by the virtue of this strong reverse bias voltage, ok.
So, if these two junctions are remaining isolated, we cannot get BJT operation, it will be
rather working as two back to back diodes. And this will be getting converted only when
these two junctions are moving close to each other in the near vicinity, if I make this
reverse bias junction in the near vicinity of whatever the other junction is there. Namely,
if the electrons are having profile like this and if this junction it is coming in the near
vicinity. So, instead of having an exponential fall of the minority carrier rather it will be
having going to drop to 0, because of the reverse bias.
So, if I push the second junction close to this junction-1, then that is what it happens. So,
from this profile of the minority carrier, the minority carrier profile, it will be going like
this. Anyway we will discuss this one, you please think over and we will continue our
discussion in the next class while we will be moving this J1 and J2 close to each other
keeping J1 remaining forward biased and J2 in reverse bias condition.
This is where we are talking about the current particularly current carried by electron. I
like to mention here a small correction; please make a note of that. Whenever we are
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( ( ))
taking say , then we do have , so that Ln part it will be coming here. So, this
is a correction. And rest of the things it is remaining same, namely this part it will be as
we say that it can be replaced by ( ) . And so the total current or diffusion current
we are getting here and the same mistake it is getting repeated here. So, it should be
divided by Ln.
So, expression of current carried by electron equals to ‧npo ( ) , and as
I say that if I consider x = 0. So, this part it becomes 1 and hence this is rest of the things
it is giving the current flow are carried by electron. If we take the derivative will be
getting along with Dp will be having Lp in the denominator because we do have we

do have.
And so, if you replace the pn(at x = 0) by its corresponding expression here, what we can
get is pno. And then pno you can take it out and in this position what will be having it is
Thank you.
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Prof. Pradip Mandal
Lecture - 08
Revisiting BJT Characteristic (Contd.)
We have done in the previous class it is; we have looked into the BJT characteristic; in
fact, we have started and today we are going to continue and we will try to consolidate
the I-V characteristic. So, we do have some extent we have a discussed on about the
working principle today will be going further detail and we will consolidate the I-V
characteristic equation. So, what we have today the today’s plan to cover it is the
following.
We will start with whatever the things we have discussed in the previous class namely
the current in through p-n junction in isolated condition both for forward biased and
reverse bias. And, then we will be going through the junction current of BJT particularly
if the two junctions one is in forward bias another is in reverse bias namely in active
region of operation.
Then what may be their junction currents and then using that information will be
consolidating to get the terminal current of the BJT in active region of operation and
from that we will consolidate the I-V characteristic equations of BJT; particularly for n-
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p-n transistor. And then later we will be moving to the further utilization of those I-V
characteristic namely what may be the graphical interpretation of the I-V characteristic
and then how do we draw the equivalent circuit of the BJT and so and so on.
So, we may have to split the whole plan; one is the part one and then we do have the part
two and as I say that this part we already have started. So, let me quickly go through
whatever the things we have discussed, but before that just to align ourselves with the
overall plan the weekly plan where are we compared to our overall plan.
We are at present we are at component level discussion; particularly active device and in
the in this week what we are at is we are going through the BJT operating principle,
characteristic and all and then we will be moving to this one in the subsequent class.
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So, what we have discussed about the BJT? So, BJT particularly say n-p-n transistor it is
having three regions namely n, then p-region and n-region. In between it is having
junction, junction-1 and also junction-2. They may be having different cross sectional
area A1 and A2. And, for active region of operation J1 particularly one of these junctions
to be forward biased by this voltage; base to emitter voltage and this junction on the
other hand; it will be reverse biased.
The polarity of the VCB it is such that the n-region, it is at higher potential than the p-
region. Whenever we talk about these two junctions and if we say that these two are wide
apart and they are not influencing each other; then whatever the minority carrier
concentration we have seen in particularly in the p-region; it is having an exponential
change. We do have J1 and likewise we do have J2. And, since J1 it is forward biased the
minority carrier concentration namely np in the base region may be as function of x, there
what we have observed that; in the neutral region it will be reaching to the level of npo;
depending on the doping concentration in the base region will be getting npo which is
equal to .
But near the junction beyond the depletion region for the time being considering this
depletion region is small. So, beyond this depletion region, it is having exponential
penetration of the carriers and or other carrier concentration it is exponential. So, this
exponential change of the minority carrier concentration it is of course it is characterized
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by the length up to which the electrons are penetrating namely Ln and the height here it
depends on how much the forward bias we do have; so that also we have discussed. Once
we consider the second junction which is in reverse bias condition; the minority carrier
concentration it drops to 0 because of the reverse bias; say approximately 0.
So, there is also a change of this minority carrier concentration with respect to J1. So on
the other hand, the minority carrier concentration on the side of the junction; it is seeing
similar it is also having similar profile. So, here also it is having a similar kind of profile
namely this is pn as function of whatever it is see many distance z; z starts from this point
and; so, likewise here we do have pn(y) minority carrier in the emitter region starting
from this point. So, this y it is starting from the age of the depletion region.
So, whatever it is the behavior of this junction and behavior of this junction namely the
junction current IJ1; it is exponential function of VBE. So, likewise in this junction also
the IJ2; it is having exponential dependency on VCB, but since it is reverse bias, you may
say that approximately this current is having almost reverse saturation current. And it is
having two components; one is current carried by electrons In1 plus and then current
carried by holes Ip1. So, likewise this is also having two current components In2 + Ip2.
Now, with this information we are trying to do is that we are reducing this distance and
we like to see what may be the consequences. Keeping of course, J1 forward biased and
J2 reverse biased namely physical distance of these two junctions we are trying to reduce
which means this characteristic and this characteristic they may interfere with each other.
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So, let us see what may be the consequence ok. Before we go into that as I said that there
are different current components; we already have mentioned that this IJ1, it is having
two current component namely the current carried by electrons and current carried by
holes. So, likewise IJ2 it is also having two current components namely we do have In2
and then we do have Ip2. And it may be noted that this junction since it is forward biased;
it is having very good exponential dependency on the VBE; both Ip1 and In1.
On the other hand, since this junction it is reverse bias; the corresponding current here it
is very I mean, it is getting saturated and we may say that this these two currents are
almost equal to the saturation current; remains almost independent of the reverse bias
condition. Also the convention wise, we are assuming that the +ve current it will be
flowing from p to n, but since we are applying the reverse bias here the actual current it
is flowing from n to p. So, that is why you do have these two; these two currents are
having ‒ve sign.
But whatever it is; the actual current here in this case it is flowing entering the current is
entering into the collector terminal, it is departing the base terminal. On the other hand,
here the current is departing from the emitter terminal and then it is entering to base
terminal. So, note that this base and this base they are actually same terminal which
means that at this terminal we do have this current and this current together. So, by
considering different junction current component; we may be able to easily get the
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terminal current namely this current IE; it is a summation of these two currents. So,
likewise IC; it is summation of these two currents and IB; it will be summation of these
two minus whatever these two currents are there.
Now, still we are keeping the two junctions since in isolated condition. Now, if I take
these two junctions close to each other; let us see what are the things are happening.
So, what we have done here it is we have taken these two junctions in the near vicinity.
And, due to that the interesting change of the minority carrier concentration; particularly
in the p-region the base region you see; so we do have the J1 and J2 and if I, if I ignore
for the time being if I ignore the depletion region and as you may recall in from the
previous discussion; here it was supposed to be exponential fall and here it is going to 0.
And since this spacing is very small practically it is going like linear of course, it will not
be exactly linear; it will be having little bent here.
So, definitely because of this change of the minority carrier concentration; the slope of
this characteristic at this point and this point may not be changing significantly.
However, if you see the other two minority carrier concentration particularly in the; in
the collector region its be the profile it remains like this. And similarly in the emitter
region also the profile of the minority carrier beyond the depletion region elements like
this which indicates that probably the current carried by holes in this J2 junction as well
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as in J1 junction; they will remain unchanged. Whereas, now the current carried by
electron in this junction and this junction; it is anticipated to be getting changed.
So, if you see; so the total IJ1 and this junction current and this junction current, they will
be as I said that they will be having two components one is due to the electrons and
another is due to the holes; they do have you know they are getting changed. Particularly
this is not changing this is remaining unchanged, but this is getting change. So, why is it
change? Because whatever the electrons are penetrating in the base region; they are just
experiencing a strong electrical field in the near vicinity across this junction.
So, as a result instead of electrons are really going into the terminal B; they may be
attracted to the towards the collector region. So, pictorially here we are trying to
illustrate that so many electrons; so many electrons whichever is crossing here are
actually getting collected to the collector terminal. So, this the red color arrow indicates
that many of these electrons are getting attracted by this collector terminal; that is mainly
due to the strong reverse bias and mainly due to this junction in the near vicinity.
So, before these electrons are really getting recombined with holes in the base region;
they are quickly pulled out from the base region. So, as a result whatever the current
component of this IJ1 namely In1; it is getting heavily affected. On the other hand of
course, this Ip1; it is remaining unchanged. So likewise here also Ip2 remaining
unchanged, but in fact, this part of course, Ip2; it is remaining unchanged. This electron of
course, whatever the original electron it was there due to this reverse bias movement of
this electrons due to this reverse bias in isolated condition that remains unchanged.
So, I should say In2; it is also remaining unchanged, the only component it is getting
affected is this part; this part it is getting change. That is because it’s if you see the
minority carrier profile it is heavily getting affected and the slope; it is very short
indicating that a lot of currents it will be flowing. So, you may say that as I say that this
current is see it is changing. So, we need to find that what will be the expression of that
current; in addition to that some of those electrons are getting recombined. So, whatever
the holes it is there in the base region it is getting recombined with whatever few of those
electrons here.
So, the current carried by electrons it is actually it is having two components; one is it is
getting recombined with the holes coming from this base region namely it is contribute
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in the base terminal current. On the other hand, the other component it is basically
electrons are moving here which is contributing additional current of the collector
terminal.
So, this current whatever the currents you are getting due to the penetration of the
electrons; we will be calling injection current. So, the electrons are getting injected here
and also it is having recombination currents. So, you may say that In1; fate of this In1, it is
getting changed to two parts. One is maybe injection current which is contributing to the
collector and then also it is having recombination current which is of course, it is
contributing to the base terminal current.
So, let us look into a little detail of that of these two different current components. So,
from this one what we have learned is that this minority carrier concentration it is getting
affected and also the corresponding junctions currents are also getting modified.
This is yeah this is what I just now we are talking about the recombination current and
whatever the current we do have here; whatever the electrons are penetrating here that
will be discussing. But before that as I said that Ip1 remain unchanged, In2 and Ip2 are
remaining unchanged. The changed current components are the following. So, this is
what the current which we will say that many of these the electrons are coming here. So,
you may say that this is the injected current; so injected current and this part the second
part on the other hand; it is the recombination current.
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So, if you see its expression here; so this part is representing the gradient of the minority
carrier in the in the base region. So, at this point we do have np at distance 0 and at this
point; we do have np reaching to 0 because if the reverse bias condition there and the
distance here it is base width. So, from that you may say that the gradient here. So, this is
np(0) at distance 0, this is approximately 0; so the slope here it is . So, that indicates
whatever the current it is coming to the collector due to the; the injected electrons from
the J1; is its expression is given here.
On the other hand, while this recombination is happening it depends on how much the
electrons are available here and they are minority. So, they in fact they dictate the rate of
the recombination and if I say that the shape of the concentration here in steady
condition; it is like a triangular shape. So, the available charge here it is np(0) × WB / 2.
So, this indicates the available carrier from there and τn and the other hand it indicates
the lifetime of the electron before they are getting recombine.
So, they are again contributing the base terminal current and interestingly both of these
terms are function of np(0). So, this is; this is what the important point is that this is np(0)
and this np(0) we know that this is exponential it is having exponential dependency on
the ; so which means that both of the terms are having exponent; exponential
dependency.
These two parts of course, they are almost constant; on the other hand this is have this is
also having exponential dependency on VBE; that of course, it is due to some other reason
namely pn(at y = 0); it is pno in emitter into So, all of them are luckily I mean most
of them are luckily function of VBE exponential function.
Now, if I has said that these two currents are very small if; so even though they are only
function of VCB; probably we may ignore particularly in the active region of operation;
so, to further consolidate different current components and try to see the terminal current.
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So, let us look into what are the terminal currents you do have ok; these are the
expression of the current and quickly; so this is what just I was telling that one Ip1; it is
exponential it is having exponential dependency of course, it is having a minus 1 part.
The injected current; so this is also having exponential dependency on the VBE.
Recombination part that is also having exponential dependency on the VBE. So, all of
them are having exponential dependency; these two currents they are since it is as I say it
strongly reverse biased by VCB, they are approximately independent of VCB and
incidentally these two currents are also very small compared to the other component.
So, that makes the approximate I-V characteristic simpler; in other words that most of
the current components. The current components of this one, current components of this
one or even this terminal current components are the practically they are exponential
function of VBE. So, let us look into the different terminal current.
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So, as I say that the base terminal current; it is summation of the two current components
of this one; namely In2 and Ip2. These two indicates the second junction current this is this
basically the junction current and also we do have Ip1. So, this Ip1; it is again part of this
one and that is due to the movement of the holes that is of course, it is not getting
change. In addition to that, whatever the d combination it is happening that current is
also mentioned here.
So, this terminal current incidentally of course, these two currents are very small and
also they do have a ‒ve sign. So, if I say that with that assumption if I say that these two
currents are dominating over the other two and if I approximate that the IB currently it is
a function of I mean it is having dominant terms of Ip1 and then recombination current
and both of them are having exponential dependency on VBE. It may be having different
constant part, but what is the important thing is that it is having exponential dependency.
On the other hand, the collector current the collector current is having as I say that in the
injected current namely whatever the movements of this electrons coming here; they are
contributing in this terminal current. So, this part under certain condition; this is also
dominating and this current it is again exponential function of VBE; that is because the
availability of the carrier here, it is it depends on how much the bias you are putting and
then how much the electrons are really crossing this junction.
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So, from that you can say that this current particularly the injection current at the at the
collector terminal; it is basically the exponential function of the VBE. And emitter current
of course, Ip1 then recombination current and then the injection current; all of them are
again exponential function of the VBE ok. So, all of them as I said that all of them are
having this dependency on VBE in the exponential form.
Now, if we consolidate this information and write the expression of the different current
components, that gives us useful information namely I-V equations of the; the BJT. So,
so far some extent we are engrossed within the device, but end of it what is important is
that the terminal current and the terminal voltage. And, this slide particularly here we are
summarizing the important current components. What we have it is they say that IC and
IB then IE. So, all of them are having exponential dependency.
So, if we recall the previous; so if you recall here that all of the current components are
having exponential dependency and so what we can say that this is having exponential
dependency, this is having exponential dependency and this is also having exponential
dependency. Particularly, if I draw this one part; if I approximate that this is very small
compared to the other part. So, all of them are having exponential dependency.
So, as the exponential part is present it is available everywhere; the next thing is that
what may be the constant part associated with each of this current component? So, let us
look into their relative value.
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So, if you consider the expression of terminal current. For example, if we consider the
collector terminal current IC, its expression is having q, charge of electron, then base
emitter junction area A1, then diffusion constant of electron divided by base width
multiplied by np0, that is the minority carrier concentration in the base region multiplied
by .
Assuming that the device it is in active region of operation and we are ignoring various
other small components. So, this is what the main dominant terms. So, likewise we can
get the expression of the base current. Now if you see here, all these parameters involve
into this part as a circuit designer, you may consider it is constant. Particularly when you
consider the device it is already got fabricated.
So, we can consider that is given to us and we like to see that as a device parameter, say
IS . So, this IS, we can assume as a circuit designer it is constant whereas, as a device
designer, they like to improve this IS by tuning some of the parameters. So, namely base
width and so and so.
So, apart from the I-V characteristic of a device, what we are looking for it is important
parameter of a transistor and one of the important parameters is the ratio of collector
terminal current and base terminal current, which is denoted by β of the transistor to be
more precise it is βF. So, if you see the expression of this terminal current, what you can
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see in the numerator if I consider the dominant term of the collector current in active
region of operation this multiplied by .
So, likewise if I consider the base terminal current it is also having this coefficient. In
fact, it is the dominant we do have two dominant terms and of course, multiplied by
and we do have two terms. The first one it is the current carried by holes and the second
term it is the current due to electron recombination in the base region.
Now, you can cancel out this in the expression of β and also you can cancel q and
A1 from the numerator and denominator. And then you can take np0 and this np0 in the
denominator term.
So, what we can see the expression of the β it can be simplified further. So, in the
numerator we do have , base width of the transistor. And then in the denominator we
do have Dp, diffusion constant of holes, then diffusion length of holes multiplied by ,
plus the other term it is base width .
So, this is τn is the lifetime of the electron in the base region. So, if you see this
expression and if we further try to get the expression of say pn0. pn0 it is the holes
concentration in the emitter region. And, it is expression can be given as ; here, ni is
the intrinsic carrier concentration and ND is the donor concentration in the emitter region.
So, we can see that this is ND and likewise the expression of np0 which is ; here, NA is
accepter concentration in the base region. So, if the ratio of np0 and pn0 will be .
So, by considering this equation of this β in terms of various device parameter, what
typically it is done that we like to get this β should be as high as possible because this is
very important parameter, which defines the base terminal to collector terminal current
gain. Namely, if we feed a signal at the base that current coming to the collector, the
signal current coming to the collector with an amplification of βF.
Therefore, typically we like to get this βF to be in the order of hundreds or so. So, the
value of this β typically it is getting increased by decreasing this base width and also the
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base width here. Moreover, by decreasing the ratio of or we can say that we can
increase this ND and NA we can decrease so that the β of the transistor it can be
increased.
Therefore, again typically the ND may be two orders magnitude higher than NA and that
is how we do get, a higher value of β. Therefore, this is also having some donor
concentration ND. To distinguish this donor concentration, with respect to donor
concentration in the emitter probably we can use a superscript C here.
Again, we like to know that what will be the consequence of this concentration of this
donor in the collector region, you may recall that this junction the base collector junction
it is being reverse biased. Therefore, if this ND it is high then the penetration of the
depletion region into the base it may be high, and more specifically if we change the
reverse bias VCB then the penetration here it is being increased. As a result the effective
base width after deducting this depletion region that may be modulated by this VCB
voltage.
In addition, in effect that changes the, directly influence the collector current. So, we do
not want that and hence we prefer to keep this ND in the collector region much lower,
then whatever the ND we have obtained in the emitter region. So, as a result the device
engineers the sets that and in case if you are using this collector as an emitter.
So, if you want to use this collector as an emitter, and then the emitter as an collector,
then what it may happen that what you are looking for that need to be low to get the β
that will not be satisfied. So, if you are connecting the BJT in the reverse direction, the
corresponding β which is denoted as βR that will be having much lower value than βF.
So, that is why we are putting the subscript βF and βR. Now coming to the other
important parameter which is the ratio of the collector terminal current and the emitter
terminal current, where we know that the emitter terminal current can be expressed. Now
we do have the other parameter apart from βF, we do have collector current divided by
emitter terminal current which is denoted by α.
That can be expressed in terms of β and this expression can be easily found that, if we
write the expression of emitter current which is collector current plus the base current.
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And from this relationship we can say that the base current it is collector current divided
by β. So, using that relationship we can directly get this parameter α in terms of β.
So, now these two parameters of the device is very important similar to βF we can get the
parameter called αR and of course, we do not want to utilize. Now, the other important I-
V characteristic aspect is the influence of VCB voltage on the collector terminal current.
So, let us see that the influence.
First of all the collector current we are approximating by this component dominating
namely the injection current and where we do have the WB. So, this base weight it is
basically the residue base weight after deducting and the depletion region both in the
emitter junction and the collector junction.
Now, if I increase this voltage then base width here since it is reverse bias; so this
depletion region it will be getting increased; as a result this base width it will come
down. So, you may say that if I increase the corresponding base width it will be
narrowing down. So, if you see in this equation if the base width it is getting decreased
with the increase of VCB. So, naturally the overall current it will be getting changed. So,
that part the dependency part of this WB on the VCB can be well approximated by linear
equation and that can be rearranged in this form.
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So, you may say that if I; if I model this WB in terms of say ok. So, this may this
( )
model it is fairly note that VA it is just a; just a coefficient I should say it is a parameter
fitting parameter and I may say that , it is unchanged. However, WB change of this
WB with VCB can be expressed in this form and so if I use this equation here what I can
get is that this factor; it it comes in the numerator and this part it can be consumed within
this part which may be considered as constant term.
So, this constant term it is having and also the other parameter and the dependency
on the terminal voltage it has been taken out; so that we can get the IC as function of the
VBE and VCB. And for practical purposes VCB instead of using VCB; we may use VCB +
VBE so that again with again with meaningful approximation for our convenience; this
does get replaced by VCE approximately ok. So, the equation of the current collector
current; it is actually instead of VCB, you may write it is VCE; that is what in the textbook
we write. So, what we have done here it is so with this modification; so let me write only
VCE part.
So, we do have expression of IC, we also have relationship of say IC and IB. So, if I know
this parameter; if I know this expression and if I know this parameter I can find the
expression of the emitter terminal current, base terminal current and also the collector
terminal current. So, as a circuit designer while you will be using this device as a circuit
designer; what we are looking for is that what may be the terminal current as function of
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these voltages? So, what may be this current particularly IC as function of VBE and VCB;
that is what it is important.
Here whatever the things we have covered till now; it is a little bit towards the device.
But, it is important to understand that little bit about the device so that while we are
designing a circuit we make sure that we give a respect to the conditions to get whatever
the equation we are using. Namely junction-2 should be in reverse bias, junction-1
should be in forward bias condition and also whatever the devices are there just to
understand, that if I put say two junction back to back; that will not form the BJT rather
their base width, it is playing very important role which is also playing important role to
define the important parameter; parameter called the current gain.
Thank you.
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Prof. Pradip Mandal
Lecture - 09
Revisiting BJT Characteristic (Contd.)
So, dear students, we will come back to this Analog Electronic Circuits course and as
you may know that we are Revisiting BJT Characteristic which is one of the prerequisite
items. And we already have seen the working principle of the BJT, and today we are
going to the second part of it and particularly how we use the equation to analyze the
circuit.
So, these are the concepts we have already have covered the blue colored first 3 items we
already have covered and today we are going to the I-V characteristic and how we use
the I-V characteristic to analyze say simple BJT circuits. And, also we look into the
difference between I-V characteristic of p-n-p transistor with respect to n-p-n transistor
because the working principle so far we have dealt with in detail about a n-p-n BJT
transistor.
So, we do not like to repeat for p-n-p transistor; however, you can deploy it for p-n-p
transistor. Then we are here we are primarily focusing on what is the basic difference
between the two device characteristic and then we are going for the equivalent model of
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the BJT. Particularly, what is the equivalent circuit we will be using; instead of equation
normally we prefer to deal with equivalent circuit. And, then we will be covering some
of the maybe two numerical problems related to that.
So, let me go to these slides where last we have concluded, yeah. So, this is the slide
where we have concluded in the previous part of this module. So, what we have
discussed here it is the biasing we already have discussed and then we also have said that
how do we vary the junction potential. Particularly, the VBE and then when you observe
the base current and then when you observe the emitter current and when you observe
the collector current what are their dependences are represented by primarily these two
equations. In fact, all these currents, all the 3 currents they are exponential function of
the base to emitter junction voltage.
And, so if we take the ratio of the collector current divided by the base current the
exponential part do get cancelled out and then whatever the constant or the remaining
parts we do have that comes as an important parameter called the β of the transistor or to
be more precise it is referred as base current to collector current gain. And, as you can
see in this expression that this is primarily it is function of a different device parameter
internal parameter, namely the base weight, then base to emitter junction cross sectional
area and so and so.
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In fact, we can also see that it is function of the npo which is the minority carrier
concentration in the base region. So, likewise we also have minority carrier
concentration in the emitter region. So, namely npo is nothing but NA the acceptor
carrier concentration in the base. So, this is corresponding to the base region. So,
likewise the pno the minority carrier concentration deep into the emitter region; so, that is
equal to , ND donors concentration in the emitter region.
So, whatever it is. Here you can say that if we really are looking for a device which is
working as a good amplifier. We like to have this base to collector current gain β should
be as high as possible. And this equation reflects that how we can make this β to be high,
one is the base weight and of course, another is the doping concentration in the base
region, and then also the doping concentration in the emitter region. So, those are the
detailed parameters related to the device.
As a circuit designer what will be looking for it is that if the device is given to us we will
be looking for a decent value of this βF forward direction current gain. And, also we have
just given a hint that this F stands for forward direction, namely if the emitter it is really
used as an emitter, collector it is really used as a collector and of the if the device it is in
active region then whatever the base to collector current gain we do get we call it is βF.
On the other hand, in case if we pretend the collector region or the collector terminal as
emitter and emitter terminal as current of course, then corresponding ND instead of this
region emitter region we have to consider ND of the collector region and its
corresponding concentration it is quite different from emitter. So, as a result whatever the
current gain in that case we will be getting that is also called β, but you may say that it is
in the reverse direction that may be much smaller than in the forward direction β.
So, while we will be using the device for our circuit, we should understand that the
emitter really should be used as an emitter and likewise the collector. Now, we also have
another parameter called αF which is the emitter to collector current gain. I should not
say normal it will be gain, but it is typically as you can see from this expression if the βF
it is very high compared to 1, it may be going approximately 1 though it will be slightly
less than 1.
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So, as a device user in our circuit we may not be really dealing with tuning these
parameters rather we will be assuming that these parameters are given to us. So, as a
circuit designer in that case we will be focusing on the current to voltage characteristic
relationship, namely IC as function of the base to emitter voltage through this exponential
function and rest of the things this portion we may assume it is constant.
So, say for example, we may consider since this equation current as function of VBE, it is
having exponential dependency and it is similar to forward direction diode or forward
biased diode, and in that case this whole part it may be considered as reverse saturation
current. So, we may use this whole factor as IS and probably you can use IS for the
collector terminal into .
So, it, so it basically this is this is what we are getting here that the main dependency of
the collector current as function of VBE and also you may be aware that if we if we
change this VCB collector to base voltage. So, it is expected that the second junction it is
also getting more and more reverse bias, particularly if you increase it and as a result the
depletion region around the assumption increases. So, naturally that decreases the
effective base width.
So, if this base width is getting decreased, so we can say that this base width if it is
function of VCB. So, naturally this part it is having some weak dependency. So, typically
instead of really modeling this WB as function of VCB since this dependence is very weak
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it is modeled as linear function of VCB and it is considered as additional factor and this
part we do consider it is really constant.
So, I should say if I consider WB it is remaining constant, and then only we can get the
expression of IS of the collector. But in case if we really want to capture the effect of VCB
on WB instead of really looking into how much the change it is happening we like to
capture that dependency as separate factor like this one plus VCB.
Further to that instead of for circuit convenience instead of considering this is function of
VCB we prefer to consider it is VCE because VCE of course, it is not same as VCB which is
VCB + VBE. And all practical purposes, if we change this VCB or VCE this part it is almost
remaining constant quote and unquote constant. So, we can say variation in VCB, it can
be well approximated by variation in VCE and invariably in our normal characteristic
equation instead of using VCB we use VCE. So, that may require additional adjustments,
but that can be ignored.
So, end of it what we are getting it is collector current as function of the VBE through this
exponential function and it is having a constant and also it is having linear dependency
on either you can see VCB or VCE. On the other hand, using this equation this expression
of the collector current and using the factor βF you can find the expression of IB, you can
also find the expression of IE. So, that is what we are expecting for circuit analysis, so
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that these equations you need to be given to us to go for further analysis of a circuit
containing BJT.
So, let us move little more detail or rather let us move away from the device operations
and detail equation of the devices and whatever the end of it, so whatever the equation
we have obtained let us go with that into the circuit, particularly a circuit where you do
have the BJT.
So, here again we are coming back to the little bit towards the biasing side, but if you see
that we do have n-p-n transistor. And, then we do have the two junctions of this
transistor base emitter junction we like to make it forward biased for active region of
operation of the device or to be more precise we like to keep the junction one to be
forward biased.
So, J1 it is forward biased by this voltage, base to emitter voltage. And this junction it
may be reverse bias the second junction by VCB. And then of course, there will it is
expected that there will be a current flow this terminal current, the emitter terminal
current and the collector terminal current. And, the dependency of those currents you
already have said that they are having exponential dependency which is given here and
then collector current is having exponential dependency in addition to that some linear
part depends on the these junction bias.
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So, likewise and what you also say that instead of using the bias here we may prefer to
say that it will bias the other junction by applying voltage with respect to emitter and let
me call this is VCE. So, if this VCE it is sufficiently high then we can say for a given value
of VBE, it is the second junction it is getting reverse bias under this condition. So, strictly
speaking to get the reverse bias condition for the second junction this is the condition,
but normally for practical purposes even if this junction it is slightly getting forward
biased still the device remains in quote and unquote in active region of operation.
And, instead of strictly following this condition we may say that as long as VCE it is a
higher than some voltage which may be even say smaller than VBE(on) we call it is
VCE(sat). We may discuss this why we call it a sat, but as long as this VCE it is higher than
some voltage then we can say that is the second junction all practical purposes it is
though it is it may get weakly forward biased, but still these equations of the currents
remains valid.
So, instead of in our circuit instead of using this view we may prefer to use the symbol of
the device. So, here we do have the symbol of the BJT n-p-n transistor, and its
corresponding bias as you said that we do have VBE and then we do have the VCE. So, so
we are biasing the circuit like this. So, we do have the VCE here and then VBE here, and
then we do have the base current entering into the base of the transistor.
Collector current enter into the device through this collector terminal and then the emitter
current it is departing the device through this emitter terminal. And, this is what the also
the actual direction of the current flow and the actual the polarity of the positive currents
of the collector and base terminal and emitter terminal currents and this is also the
corresponding positive polarity of the corresponding terminal and the voltages.
In case, if we have this VCE negative which means that this side it is lower than the
emitter side. So, that is how we do this kind of biasing arrangement for the n-p-n
transistor. And then further little going little detail of for the BJT circuit let me see what
is the next thing we do have if we apply that bias what we have the I-V characteristic
particularly graphical representation.
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Now, we have oriented the device differently. So, we do have the base we are taking
towards the left indicating that probably this will be one of the input terminal. And
emitter we are to taking down, so we may be assuming that lowest potential of the circuit
may be connected to this emitter terminal or at least we can say emitter should be at
lower potential than the base. On the other hand, collector terminal we like to keep at
higher potential.
So, we simply just reoriented the device for our convenience assuming that we will be
having probably at this point we will be having higher potential and we call this is VCE,
we call this is VBE and this is the base current, this is the collector current, and this is the
emitter current.
Now, their expressions are given here. Of course, these equations are very fundamental
equation we have to again and again revisit, but it is also it is important to see that how
intuitively we can make use of these equations and to be more precise what may be the
graphical representation of this I-V characteristics. So, that is what we are going to focus
now.
So, if you are considering say the first equation the IB versus VBE as this equation
suggests that it is similar to the diode current in the forward biased condition. So, this
will be having exponential behavior. So, this is the equation is getting represented
graphically. So, likewise, if you are also plotting the collector current as function of the
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VBE, so it may be noted that right now we are concentrating the dependency of the IC
current as on VBE and as you can see that this part is also exponential.
So, the nature of the two curves are essentially I should say quote and unquote identical.
Assuming, VCE it is sufficiently high and we assume that this is remaining constant, so
quote and unquote constant. In fact, if even if say this VCE it is changing since this part it
is very small and in other words you can say that this early voltage is very high making
this part is practically approximately one, so even if VCE is changing this exponential
nature of the collector current on VBE it is still valid.
So, this part of course, you can say it looks like it is a forward direction diode or rather
forward bias diode, but on the other hand if you see this characteristic it is kind of a
different in nature because we are observing the current at the collector terminal while
we are changing the voltage from base to emitter. So, in other words you can say that is
like a trans-characteristic. So, we are changing the voltage from base to emitter while
you are observing the corresponding effect at the other terminal and down the line we
will see that for many applications we consider this is the input.
So, we can say that this is the input port from base to emitter and at the collector we are
observing the corresponding effect and this will be treated as the output. So, we can say
that input to output port trans-characteristic it is primarily represented by this one. In
fact, this is very vital for to understand the amplifier where we feed a signal at the input
port and we are observing that corresponding effect at the output port. In this case of
course, it is voltage to current later on we will also see that voltage to voltage
relationship. So, whatever it is this is of course, it is trans-characteristic.
And you can also see that the collector current is function of VCE though it is a weak
function, but still it is having dependency. So, how do you represent that? So, if we plot
say IC as function of VCE keeping VBE constant. So, which means that we are keeping this
voltage constant we are simply varying this one and then we are observing the collector
current. So, if I assume that this second junction namely collector base to collector
junction if it is remaining reverse bias.
So, we can see that through this equation or this equation represents that dependence is
very weak. So, depending on the value of this VA, the parameter VA there will be slight
change; however, if the VCE it is sufficiently low and if this junction it is getting forward
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bias there will be bend of this current. In fact, you can you can say that if this voltage it
is this voltage it is 0 of course, it will go to the origin. So, there will be a big dependency
of the collector current on VCE only when this junction it is getting forward biased, but
till that point as long as it is reverse biased we can say that this current is fairly quote and
unquote independent of the VCE voltage. So, of course, depending on this value of this
VA we can say it is independent.
Now, what is the significance of this VA and the slope of this line is the following. So, if
you extrapolate this I-V characteristic wherever it intersects the VCE axis, then whatever
the value we will get that voltage it is ‒VA. So, this is this that represents that at VCE = ‒
VA this part it becomes 0 and hence the corresponding current the extended current it is
becoming 0. So, that is the significance. In other words, you can say that higher the value
of this point then in other words if this point it is far away from the origin slope of this
line it is less.
Now, if you see this the graphical interpretation of I-V characteristic, they do have other
meaning also particularly what presently whatever the characteristic we have plotted we
have changed this VCE and VBE quite a large extent pushing the device into heavily you
know saturated portion. Namely, we are we are seeing that the highly non-linear effect
from here to here. So, likewise here also we can see highly non-linear effect. Here also if
you push the device into this region beyond the active region of course, we can see the
highly non-linear part.
But whenever we will be focusing on amplifier we may be keeping our you know signal
will restricted within narrow range maybe somewhere here and probably around that
whatever the slope of the characteristic that may be important. So, likewise here also if
we keep the VBE the current my having linear dependency on that VBE that can be
represented by the slope of this characteristic line same thing for this also.
So, as we will be using this circuit particularly BJT as an amplifier particularly for
analog circuit, so we like to prefer to translate the non-linear characteristic or rather
restricting this non-linear characteristic within a certain range ensuring that linear
behavior of input to output relationship it is getting maintained. And, we will also be
seeing that apart from this large signal behavior what is important thing is that slope of
this line is very important. Slope of this line it is very important.
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So, whenever we will be going to the small signal model or equivalent small signal
model as you have discussed for diode the slope of this line it is important and slope of
this line equation wise it is . So, likewise here the slope it is and so likewise
here if you see the corresponding slope here that, can that is also of course, change in IC,
but with respect to VCE.
And each of these slopes they do have their own interpretation and since we will be
dealing with this slopes more frequently. So, it is better to give a different name and give
different you know you know parameter or symbol to represent this one. Say for
example, this is this is getting represented by gm, gm stands for trans-conductance, m
stands for mutual input to output port that is why it is trans, g represents conductance.
So, input port to output, so input voltage to output current relationship it is getting
represented by this slope or this parameter called gm. So, trans-conductance of the device
it is for the gm.
So, likewise, this slope it is having some meaning. In fact, if you see that it is expressing
the relationship between the input terminals current to input port voltage. So, you may
say that this is nothing, but 1 by input port resistance, it is . So, likewise if you see the
IC versus VCE characteristic curve, so this slope it is also having interpretation as the
output port conductance or , ro is the output port resistance.
Of course, this ro it is small signal resistance rπ it is small signal input port resistance and
gm it is trans-conductance keep keeping in mind that we are restricting the signal within
certain range. So, that the linearity model it is valid. So, that is the graphical
representation of this I-V characteristic equation.
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So, if we see how do we then in actual circuit how do we use this equation. So, that is
probably very important for the circuit analysis. So, I again I am going to use the same
kind of bias here probably we can keep the bias VBE here. And then we can have the VCE
and our main interest is to find what will be the corresponding current here, here and so
and so.
Now, what we will be doing is that since we already have seen that the IB. So, IB versus
VBE characteristic curve it is having similar kind of behavior of a diode. So, IB versus
VBE it is it looks like it is a diode. So, from base to emitter terminal probably its behavior
can be represented by a diode. So, you may say that this is our emitter terminal and this
is the base terminal and in between we do have a diode.
So, whatever the diode its corresponding reverse saturation current is this one it typically
it is a very small compared to normal diode, but still you may say that the diode can
represent its behavior. Though this value of this one it will be in the order of maybe 10 to
the power may be ‒15 Amp in comparison with diode, if I say that for a typical diode
normal signal diode this will be 10‒13 Amp so, but then the exponential relationship it is
getting maintained.
Now, next thing is that ok, this base to emitter port it is relatively simpler, but however,
the other ports the collector to emitter port where we do have IC. IC it is as a function of e
rather it is strong function of VBE that is what we see it and it is having exponential
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dependency. So, of course, this is a trans-relationship. So, directly we cannot put the
diode, but then we also know that it is quote and unquote remains constant. So,
whatever βF we do have.
So, probably this characteristic can be represented by say current control current source.
So, you may say that this is current control, current source and this current it is getting
controlled by IB, so we may say that this IC = βF × IB. In fact, this part it is well captured
by this relationship.
Now, in case, if you also want to represent this part probably the dependency of the total
current to collector current that can be also captured by this one, so you may put some
additional conducting path from collector to collector to emitter. Typically, since this
part is very small we do ignore this part, we assume that this resistance is quote and
unquote it is going to infinite and we may ignore. So, remaining things it fairly
represents the device characteristics.
So, if I say that this is our main model of the transistor and we do have the collector
terminal here we do have the emitter terminal here and base terminal here. So, that
represents this I-V characteristic fairly to good extent. So, we may say that this is
equivalent circuit. So, this is equivalent circuit of whatever the BJT we do have here. In
fact, being circuit designer we are more comfortable of seeing this kind of circuit, ok.
So, using this model probably we can use we can analyze the circuit. So, we can in the
next slide we will see how this equivalent circuit can be you know utilized to analyze the
circuit; so in the, yeah.
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So, what you can try to do in this exercise probably, let me connect this to ground and let
me put a resistor here and let it consider we do have a voltage source with respect to
ground and let me consider this is 10 V. And, here also we are putting a resistor we
frequently we will be seeing this kind of circuit in later discussion and let me consider
this is also 10 V. And let me assume that this is say 940 kΩ and let you consider the
other one maybe 4.7 kΩ.
Now, to move forward let me assume that whatever the condition we do have most likely
the device it is in active region of operation. Namely, this assumption is getting forward
biased; obviously, we obtain volts. So, even though we do have high resistance here that
is still it is making base to emitter junction forward biased. And of course, then we do
have the base current is getting multiplied by β. So, then it is having the corresponding
collector current. So, then there is a drop across this resistance. But for the time being let
me assume that this drop namely 4.7 k × IC this drop it is less than 10 V.
So, ensuring that this junction it is still you know in the reverse bias condition. So, the
device it is in active region. So, that is the assumption, but end of it we also have to
verify. So, let you consider the to calculate this one we need some more information,
namely we need this part. So, let you consider this is 10‒15 Amp and let you consider this
is 10‒13 Amp and for the time being let me assume that this early voltage it is very high
quote and unquote high.
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Now, with this condition, so how do you proceed? So, we already have discussed about
the equivalent circuit. So, let me draw the equivalent circuit of the transistor, we do have
the diode connected between base and emitter and then we do have the current controlled
current source assuming that the device it is in proper region of operation. So, IC equals
to. Now, if I compare say this IS and this IS if you take the ratio that gives us β = 100.
So, we can say that βF is 100 × IB. For the time being let we are ignoring assuming this is
very high. So, this is sufficient to; so, we do not require the additional conducting part
and we do have the collector here. So, that is the model of our BJT Now, around that of
course, we do have a ground connection here and then we do have the base resistance
base terminal resistance and then we do have the 10 V and this is 940 kΩ.
So, if you see that this diode is getting forward biased and it can be shown easily that if I
the method we have followed for the simple diode circuit particularly to analyze this
loop then we can see that the current flow through this one it is coming to be 10 µA. So,
how we proceed? Either you can go through iteration and you will be finding that this
voltage it is converging to close to 0.6 close to 0.6 V you can assume that the cut-in
voltage is 0.6 V with that you can calculate that this current is becoming consistent.
So, that is how I have picked up these numbers. So, that gives a corresponding collector
current it is approximately 1 mA, assuming that this is properly getting biased. So, we do
have the collector side we do have the 4.7 k and then we do have the 10 V connected
here and so if you see that if 1 mA is flowing through this resistance we do have 4.7 V
drop. So, the voltage coming here it is 10 ‒ 4.7, so that is equal to 5.3, so this is equal to
5.3. That is that is good we do have 5.3, we do have 0.6. So, naturally this is getting
reverse bias.
So, this gives you some idea, that how do we and in fact, that ensures that device it is in
active region of operation. So, this is a simple method of finding the different branch
current of a circuit involving BJT. So, this BJT we can as I said we can simply replace
by its corresponding equivalent circuit. We can do more practice on this one. In fact, if
you increase this resistor this voltage it will drop and beyond some point this junction it
will get forward biased. If you further increase this resistance this transistor it will be
entering into altogether different region operation called saturation region.
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So, we will be going little more detail with this kind of circuit. In fact, we will be varying
this voltage and then we will see that what kind of variation or effect it is coming to the
collector side that detail when we will be dealing with the amplifier.
Now, so far we are considering about the n-p-n transistor if you look into the p-n-p
transistor on the other hand it is very similar, but of course, it is the 3 islands or 3 regions
are different. Namely, we do have p-region and then n-region and then p-region, so we
do have p-n-p. And here also to keep the device in an active region of operation base and
emitter junction need to be a forward bias which means that at the emitter now we are
looking for higher voltage with respect to the base.
On the other hand, the other junction the base to collector junction we like to keep it is in
reverse bias, namely the base should be at higher potential with respect to the collector.
So, this is the corresponding symbol. So, here, so we may we may consider that the bias
here we require such that base at a higher potential and the emitter also at higher
potential with respect to on the other hand base. So, we do have higher potential here.
So, either we put the V since the positive side we are connecting to emitter we call it is
VEB. So, actually it is VEB, so here also we do have VEB. On the other hand, we do have
the other voltage this is VBC. So, VBC it is ensuring the second junction it is in reverse
bias and similar to the previous case instead of using this convention or this kind of bias
probably we can use the bias elsewhere namely with respect to emitter.
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And, if it is sufficiently the collector it is made sufficiently negative with respect to
emitter that ensures the second junction base to collector junction in reverse bias
condition. So, same thing here also in this view; so, we will be calling this voltage it is
VEC. So, we call this is VEC. Note that this for actual operation VEC should be positive
VEB should be positive that that is how we are ensuring the device it is in active region of
operation. And also if you see based on the polarity of the voltage you can expect the
current it will be flowing in this direction.
In other words, the emitter current entering to the device and the base current it is
emerging out of the base and the collector current also it is emerging out of the collector.
So, that is the axial direction of the currents. So, you may say that this is the actual
polarity a positive direction of the current and. So, we do have IE, we do have IB and then
we do have IC like this.
So, if you compare the notation or seem the equation we have used for BJT this n-p-n
BJT with p-n-p what you can see here it is. So, these are the equations it was used for n-
p-n. So, with respect to that we simply have to modify this part namely we can make it
VEB. So, likewise here we can replace this is VEB and this is into VEC. So, likewise here
also for the emitter this will be VEB.
In fact, if you simply change and if you change the polarity of the current positive
polarity of the current in appropriately then the same equations what we have discussed
for n-p-n that can be utilized for this circuit also. Now, this is the biasing and the how we
change the polarity of the currents and the voltages. For our convenience whenever we
will be dealing with this circuit since this node it is having highest potential and this
node it is having lowest potential if you see across the device.
So, for better arrangement what we will do we will make this is up and this is down. So,
we will simply you know rotate 90 degree this device for our convenience.
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So, if you see in the next slide that is how we have done. We have rotated this device and
then the corresponding biases are that can be explained like this the, ok. So, this was the
previous one and we have rotated. So, we made the collector towards the lower potential,
emitter towards the higher potential and here of course, this is p-n. So, this junction
should be forward biased and this is how the corresponding the battery will be
connecting here and we call this is VEB.
So, likewise we can the other junction we can make it reverse bias by connecting VEC
and the corresponding equation as I said the collector current it is coming out emerging
out of the device the emitter current it is entering to the device. And so, what will be this
current? This current of course, it is going out of this device. So, you can say part of this
current it is going out here as base current and remaining current it is going to the
collector from the emitter.
So, that is about the polarity of the bias voltages and the corresponding currents. And rest
of the things it will be similar namely the equivalent circuit and so and so. So, let us look
into that the equivalent circuit and the maybe little bit about the graphical interpretation
also. I think I do have separate slide for that.
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So, going back to whatever the biases we do have here. We do have emitter to base bias
here and emitter to collector bias here. And the corresponding base current is in this
direction, corresponding emitter current is getting into the device through the emitter
terminal and this is IB, this is what you say VEB and the collector current is coming out of
the device and this is VEC.
Now, you may recall whatever the graphical interpretation we do have or representation
of the I-V characteristic of say IB has function up now VEB. So, if you plot this
characteristic of course, it will be exponential in this like as you have discussed before.
Similarly, when you when you plot the IC versus VEB. So, VEB it will be of course, like
this and IC versus VEC not VCE, it is VEC. And here also it is having similar kind of nature
because of early voltage it is it is having some slight bend and till it is entering into the
saturation region.
Now, since we do have VEB here and here, and VEC instead of VCE that makes a slightly
different kind of convention with respect to n-p-n. So, sometimes people try to plot IB
versus, so IB versus VBE. So, actually it is supposed to represent this characteristic and
since we are flipping this polarity of the voltage here of course, this will be moving to
the second quadrant. So, likewise if we plot the IC versus VBE. So, here also if we change
the polarity of this bias here also it will be in this quadrant; so, likewise if we consider IC
versus VCE that will be in the second quadrant.
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And further to that if you say that no you like to keep the similar kind of convention of
the current as well. So, then you need to change the polarity of this current similar to the
similar to the n-p-n transistor and then if you follow this one. So, what you will get here
it is this if you change the polarity of this one and then of course, these two are having
opposite sign, so naturally the corresponding characteristic it will be coming to the third
quadrant.
So, if you there are two ways of dealing with n-p-n and p-n-p together either you can use
the same convention for n-p-n and p-n-p, but then you should be careful that then the
corresponding characteristic curve instead of sitting at the first quadrant it enters to third
quadrant. So, same thing for in fact, IC you also if you follow the convention positive
collector current convention it is entering the entering to the device through collector
terminal. So, in that case approaches this current it will be going to the third quadrant
and same thing here also it will be entered into the third quadrant.
So, we will be discussing this one later, but just to make it aware that there are two
approaches to go from n-p-n to p-n-p, namely change the polarity appropriately for p-n-p
keeping the I-V characteristic in the first quadrant itself or you can you know follow the
same convention of that of n-p-n, but then the corresponding characteristics are entering
to the third quadrant. So, probably whenever the situation comes we will be going in
detail of that.
Now, similar to similar to the n-p-n transistor for p-n-p also we to manage the or to
analyze as a circuit containing p-n-p transistor we need to replace the transistor by
equivalent circuit.
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So, probably I do have a separate slide for that. So, we can use this again the same
equations and we may have some bias here. Say for example, we may have bias here and
we may have some bias here and suppose we are asked to find what may be the
corresponding current here, current here and current here. So, instead of really dealing
with the equation we may prefer to move to the equivalent circuit. So, base to emitter
terminal if you see again we do have a diode
So, we can use this diode. We do have the emitter terminal and we do have the
corresponding base terminal. So, we can find, so we can apply the corresponding
external bias and then we can find what is the corresponding base current is flowing.
And then the emitter to collector you can say that we do have collector current that
current it is kind of linear function of the base current. So, we can see that this collector
current is β of the transistor times whatever the IB we do have. So, that is the collector
terminal current.
In case if you want to capture these two additional factor of course, you have to consider
the conducting path here along with this current control current source. Many here, for
many situation in fact, we may ignore this resistance as you have said before for n-p-n
and then this is the basic part of the equivalent circuit of the p-n-p transistor.
And then of course, externally we can use the other corresponding bias here. First, we
can analyze this part and we can find the corresponding IB current based on whatever the
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voltage we are applying. So, likewise here we can apply the VEC voltage VEC. So, this is
the VEC and you can find what will be the voltage whether this voltage is appropriate or
not to keep the device in active region of operation.
So, similar to n-p-n let me simply refer to one numerical problem. So, let you consider
similar situation let me try to understand that what kind of changes we do have here. Let
me have said again 10 V and again let me put the resistance of 940 kΩ. So, we do have
10 V and here we can put a resistance of 4.7 kΩ and we do have 10 V.
I am using the all the parameters are similar and say let me consider this IS(B) = 10‒15 A
and IS(C) reverse saturation current if you call it is reverse saturation current. So, this is
IS(C) for the collector terminal it is 10‒13 A and similar to the previous case let me assume
that this is very high, ok.
And, if you analyze this circuit again of course, we need to get this VT, you may use 26
mV typically that is what we do for at room temperature. So, here also you can see that
the voltage coming here it is the drop here it is close to 0.6, the voltage coming here it
will be whatever the voltage you do have plus this IR drop the base current it is 10 µA
and if I take the ratio of these two, on the β = 100. So, that gives us the corresponding
collector current is approximately 1 mA. So, the drop across this one is 4.7.
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So, if I say that this is ground this is 10 V with respect to 10 V we do have another 10 V
here of course, this is also going to be ground. So, in that case, so we do have this
voltage it is 4.7. In fact, since we do have the same voltage you need not to use this
voltage, you may simply remove this one and you can simply connect these two ground,
you will be getting the same circuit because we do have this is 10 V from this one and
this is also 10 V, so this is we call this is common terminal.
So, even if you are not using this one you can connect the circuit like this. And, we will
be going a little more detail of the circuit later.
So, what we have covered so far to summarize in this module. We have of course, in the
previous part we have discussed about the; we have discussed about the junction currents
and then terminal current of n-p-n transistor and then we have consolidated the I-V
characteristic. And, in the second part what we have done is that whatever the I-V
characteristic, we obtain from the device we have utilized that to analyze a circuit
containing n-p-n transistor. And also we have seen that what kind of biasing arrangement
we have to do in actual circuit. We also have seen graphical interpretation of I-V
characteristic.
And, then most important thing is that later on we have evolved the equivalent circuit or
equivalent model of the BJT both n-p-n and p-n-p. And, we have considered relatively a
simple example to illustrate that how that equivalent circuit can be utilized to solve
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numerical problem of the circuit containing n-p-n or p-n-p. I think, this information it is
sufficient to move for the next level namely amplifier design.
Thank you.
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Prof. Pradip Mandal
Lecture - 10
Revisiting MOSFET
So, welcome back to this course on Analog Electronic Circuits. Myself Pradip Mandal
associated with Electronics and Electrical Communication Engineering Department of
IIT Kharagpur. So, we are still revisiting some of the prerequisites. And, today we are
going to talk about MOSFET device, which is essential part of the analog electronics.
And, so we will start with some basic concepts. So, let us see what the overall plans we
do have are.
So, we are going to start with basic structure of the MOSFET particularly in MOSFET.
And, the then we will be moving to the operating principle, along with the biasing
arrangement of the device and then we will be going little detail of the I-V characteristic
of n-MOS transistor n-MOSFET.
And, then we will be going to graphical representation of the I-V characteristic of the
MOSFET. And, this module it is having essentially 2 parts one is related to n-MOSFET
or other n-channel MOSFET. In the first part and then say in the second part we will be
having p-MOSFET. So, will be subsequently will be covering p-MOSFET.
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Many of the concepts here for n-MOSFET, it will be applicable for p-MOSFET as well,
but there will be definitely certain differences. And, after that we will be addressing the
some of the numerical problems to give you an idea that how the I-V characteristic
equation can be deployed to solve analog electronics containing MOSFET. So, the
overall plan again will be seeing that with respect to our overall plan where we stand.
So, as we said that we are in the components or device level, and we are still covering
this week-1. We already have covered BJT bipolar transistor and today we are going to
start MOSFET. And, the plan is as I say that will be going into the basic structure and
then operating principle, characteristic equation, equivalent circuit later on will be
seeing, but at least will be going up to the characteristic equation. And, then as I said that
today will be covering in channel MOSFET or it is called n-type MOSFET and in the
next part we will be covering p-MOSFET.
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So, let us see the basic structure of say MOSFET. So, as you say that we are going to
start with the basic structure of the MOSFET. And, here we do have the basic MOSFET
structure. Most transport the metal oxide semiconductor and field effect transistor. So, of
course, we do have the structurally we do have metal then silicon dioxide this insulator
and then we do have the semiconductor.
And, in addition to that the field-effect transistor where, from the control input we apply
voltage to create field on the channel which supposed to modulate the characteristic of
the channel. So, here the controlling element is basically electric field. So, that is why it
is referred as field effect transistor.
Whereas, for BJT the instead of applying directly voltage we may say it is a combination
of voltage and current. And, in fact, it controls the current in the output port by applying
current to the controlling port. So, that is a basic difference of MOSFET with respect to
bipolar junction transistor.
Anyway, so the MOSFET before I go to the basic structure the MOSFET it is a very
important element in today’s context. In fact, for analog circuit of course, BJT is a better
option compared to MOSFET. However, in the recent scenario or in the present
situation, what we have it is whole system it is getting integrated and the system may be
having analog and digital.
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So, you may say that in a system if we are having said analog counterpart and then also
the digital part. And earlier when analog and digital they were implemented differently
maybe analog portion it was sitting in one chip IC say 1 and the digital portion it was in
IC-2.
So, based on the technologies, whichever it is suitable for digital we were able to select
that process to realize this IC-2. Likewise, whatever the process it is suitable for analog
circuit, it was used to implement this analog IC. And, invariably as I said that B J T is
preferred one for analog implementation. And, as long as these 2 ICs analog and digital
ICs are independent, it was having fear good option to go for BJT.
However, in last say 2 decades in fact, it may be more than that, the analog and digital
counterpart of a system they are getting integrated together within single IC. And, if we
consider it is getting implemented within single IC then we have to see which technology
is better.
Now, BJT of course, BJTs technology it is it may be good for analog, but definitely for
digital that may not be the good option. In fact, MOSFET it offers many advantages for
realizing the digital circuit. As a result as the digital with progress of time as the digital
portion of the whole system it is dominating. Naturally, the priority is given more
towards the digital circuit to decide the fabrication process. And, this IC the combined IC
of course, the MOS technology where basic devices are MOSFET is preferred 1.
Now, so the in this scenario the analog circuit which is of course, it is part of the same
system and if we want to make the system on single chip, then this analog circuit need to
be implemented and the same technology means the analog circuit need to be realized by
using MOSFET transistor. So, whenever you are covering the MOSFET is basically
preparing us for technology down the line particularly mixing signal implementation of a
system.
So, however, as I say that BJT we prefer to keep because at the board level
implementation BJT implementation is better, where we can verify some of the basic
concepts. Whereas, MOSFET normally it is not really frequently used for analog design
on board. So, anyway the now coming to the basic structure of the MOSFET, that as I
say that it is having the metal oxide semiconductor.
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So, this portion this is the cross section of the metal and then the middle thin portion it is
the oxide, silicon dioxide. So, you can say this is oxide. And, then this portion it is this
portion it is semiconductor. So, that makes the MOS structure. Historically, this portion
it was metal, but later on it is observed that so, instead of metal it is better to use
polysilicon for tuning the threshold voltage of both n-MOS as well as p-MOS.
Now, if you see here we do have this is as I say that metal. And, the semiconductor
portion it is weakly doped p-type semiconductor, then we do have the 2 islands, 2 n+
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islands left side, and the right side, and they are forming the I should say 2 terminal.
And, if you see here this is n+ and then p weakly dope though it is weakly doped it is p-
type and then we do have n-type.
So, you can say from this island to this island it is complete isolation. And, then by
applying a voltage at whatever this metal region, positive voltage with respect to the
substrate. We can change the property of this portion, which is referred as the channel.
And, later on we will see that this provides very vital information that, if we apply
positive voltage conductivity between these 2 islands can be modulated.
So, as a result we may say that this is the controlling terminal, by applying a voltage here
with respect to the substrate p ‒ substrate, by applying a voltage here. So, in fact,
electrically this p + island are working as port for the substrate. So, if you apply voltage
here which is positive, then you can change the characteristic of this region ensuring that
these two islands are getting connected.
So, now if I see the conductivity between these two external terminals that can be
modulated by this voltage. So, that is the basic you working principle will be doing little
detail.
But, structurally as I said that this is having metal oxide and semiconductor. And, this is I
should say it is though frequently in textbook it is referred as the MOS structure, but the
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actual view if you see oblique view it is shown here. So, I should say this is front view or
cross sectional view whatever you say you may say that this is front view and this is
oblique view.
So, in this oblique view what you can see here? So, this is of course, the metal portion
and then we do have the thin oxide. So, we do have the thin oxide here and then we do
have 2 islands. So, we do have this island. So, this island in factor it is getting extended
like this, this is also getting extended and then we do have the electrically 2 terminals are
there.
And, note that the substrate is weakly doped. So, if you directly try to access the
substrate from top through metal line, that may create you know schottky diode to avoid.
The schottky diode what we can do we can put p plus region and then you will be getting
ohmic contact.
So, this p + island is basically working as terminal for the substrate, it is referred as
body. So, that is why we do have we call this is body, we call this is gate. And, this 2
terminal essentially they are interchangeable they are in fact, similar in nature, though
this source is in this diagram it is shown close to this p plus region, but actually the these
2 terminals can be interchanged. And, depending on their voltage relative voltage
potential; one of them we call source namely whichever is sourcing the carrier and
whichever is collecting or wherever it is draining to we call it is drain.
So, that is the naming convention. The controlling terminal you call gate, the substrate
tab we call body and then one of these 2 islands between which we are changing the
characteristic, one of them we call source and other one is drain.
Now, if you see the top view of this device of course, whenever we are changing the
characteristic of this channel, what we are trying to do is that we may be applying a
voltage here and then we will see how much the current it is flowing from drain to
source? So, this current whatever the current is flowing, it is of course, it is a strong
function of whatever the distance we do have and whatever the orthogonal geometry,
which means this geometry.
So, the current device wise current is it is a strong function of this spacing called length
of this channel and also it is width of the channel. And, why you call it is channel?
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Because, as I say that once you apply the voltage here current it is flowing through this
region that is why it is called channel.
If you see the top view of this device on the other hand what you can see that we do have
MOS structure here. So, this is the top view of that main portion metal it is working as
gate oxide it is working as insulator through which we are applying the field in the
substrate region. And, S stands for the body here and in fact, that is nothing, but the
channel.
So, we can see that channel portion it is only here and as I said that the 2 important
dimensions one is the length and the width here. And, these 2 islands; these 2 islands are
on here. So, we do have one island here in this case we call this is drain and then we do
have another island here we call this is source and in the top view we do have this p +
island we call body.
So, that is the basic structure and I should say this is rather idealistic view of the basic
structure. Though it is idealistic view most of the times we will be using refer in this one.
And, just for your information the rather realistic views are like this.
The top view if you see here top view it is. So, this is the channel portion. So, you can
say the MOS structure it is here MOS, but then the metal portion it is getting extended
beyond this one. So, I should say the channel is of course, within this one and it is length
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is here and width is this dimension. And, the controlling element or the electrode, that is
getting extended beyond this channel for reliability reason.
So, this part the extended portion of the metal is basically helping to improve the
reliability of the device. And, then we also have something called connecting terminal.
So, we do have this portion it is referred as the contact and on top of that we do have a
metal. So, likewise we do have in the drain region we do have contacts here and then we
do have the terminal metal.
So, the box here whatever the box we are referring here it is you may say that it is at
higher level some metal. Note that this metal it is different from whatever the metal we
refer, this metal it is for making the circuit in integrated circuit. So, likewise we do have
the contact here and then we do have metal. And, in fact, in integrated circuit there are
different layers of metals. So, typically this metal layer it is referred as Metal-1 layer so
in fact, this is also Metal-1 layer. So, it is called Met 1 and we do have the p+ region here
for the body connection. So, here also you have the contact and then Metal-1.
So, if you see the top view here it is rather like this. So, if you take a cross sectional view
along this axis, if I say that a dashed then you can say that cross sectional view it will be
similar to whatever it is shown here. However, it will be different slightly different if you
are looking for more exact the interpretation say for example, in the drain region. So, the
contact portion it is quite says thick here and then on top of that we do have the Metal-1.
So, we may say that on top of that we do have the Metal-1. So, this is the metal one. So,
you may say that this is Metal-1 and this is the contact. So, this portion it is also metal,
but it is getting implemented by a different process step. So, that is why it is referred as
contact layer of course, it is material is also different. So, we will not be going detail of
that. So, likewise for the gate or the resource side also it is like that we do have a contact
and then on top of that we do have Metal-1. So, we do have Metal-1.
So, similarly for the body also and it is corresponding Metal-1 connection. So, here if
you see along this a dashed line, we are really not crossing this contact of the gate. So,
naturally we are we will not be able to see. So, you may say that it is there.
So, in our engineering drawing whatever the things it is not crossing we may say that it
exists, but probably in different plane different plane of the intersection. So, you may say
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that this Metal-1 and the corresponding contact particularly for the gate we are not really
crossing this one. So, this is rather more from I should say more realistic view of the
cross sectional view of the transistor.
And note that this oxide on the other hand let me use different color, this oxide whatever
we see thin oxide, this plays very important role, because we are applying a voltage here
and through this thin oxide it is trying to influence the substrate in the channel region to
change it is characteristic. So, this is very important, but beyond this beyond this region
channel region whatever the portion we do have in fact, they are also we do have the
silicon dioxide. In fact, everywhere here it is full of silicon dioxide.
So, if you see the structure wise, it looks like it is a sandwich of the structure and where
would you do have the controlling element, though we call it is metal, but actually this is
polysilicon as I said. So, this is the gate and everywhere as I said this is silicon dioxide.
And, so this is just for your information I am sharing this little realistic view.
In fact, beyond this beyond that this device if you see, which is part of relatively bigger
system in integrated circuit we do have many more devices on this. So, you may say that
this is the; this is the top surface of the substrate, and then we do have different devices,
and on top of that we have the contacts, and metals to make the connection, and then
everywhere silicon dioxide is there to isolate the device above the surface.
So, likewise below also we do have the silicon dioxide. So, it is silicon dioxide is here as
well. So, you may say that silicon dioxide it is also here it is also here like that. So, that
is rather more in a realistic view of the device, but for simplicity of course, we will be
using the simpler version of the cross sectional view namely we will be using this. So,
namely we will be using the so, this cross sectional view will be using.
So, we let me. So, in our next discussion we will not be really using this clumsy cross
sectional view for simplicity of our analysis we will be going for this schematic view
only.
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So, this schematic view of the cross sectional you will be frequently referred to. So, there
are a few notes to be taken here. So, first of all as I say that for further discussion we will
be going to, we will be using this cross sectional view for simplicity. Then the substrate
you should be noting that substrate it is not purely complete insulator it is rather weakly
doped p-type and the device it is planar structure.
So, you can see that the current is flowing horizontally. And, access to different
terminals it is coming from the top side of the device. In fact, you may say that this enter
portion it is the substrate. So, we cannot directly access this one. So, we have to use
access through whatever we discuss the contacts and the top the Metal-1 and so and so.
So, all the access it should be from the top.
So, and then the other thing is that in this basic structure we say that the substrate it is p-
type and by applying a voltage here, we are changing this portion into n-type. So, once it
is getting changed to n-type we may say that channel it is getting converted into n-type.
So, that is why this device it is referred as n-type MOSFET or for simply you may say
that n-MOSFET.
So, when you say n-type it refers to the type of the channel would be created. Of course,
originally it was p-type, but after applying the voltage here the channel it is getting
converted into n-type. So, similar to this structure there is also a counter device or I
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should say counter part of many circuits and it is structure it is very similar, but it is
complementary in nature.
So, if you see here the basic difference in this case for p-MOSFET. That is body it is I
should say body instead of substrate we may prefer to say it is body. Body is weakly n-
type in contrast to weakly p-type and these 2 islands. Drain source islands they are p plus
regions islands and of course, to tap the substrate we require n plus region to avoid the
schottky diode we can have the ohmic contact.
So, will be later on we will be going further detail for p-type MOSFET. So, let we
proceed with n-MOSFET for further discussion namely what you can see that the more
detail about working principle then I-V characteristic and so and so on.
So, let us go into the working principle. So, coming back to the basic device structure
and then let you also keep meaningful bias here. So, if we apply a voltage here at the
gate with respect to substrate. And, let you consider that this is also at the same potential
and try to see what kind of things is happening in this region.
So, for the time being let us also connect this drain region or the drain island together.
So, in our whole circuit we do have only this source we do have this source and this
source is gate to source. So, we may call this is VGS. So, we may say that this is VGS.
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So, if this VGS is positive then let us see what other things are happening. So, if we apply
positive voltage here with respect to source and in fact, source is also connected to body.
So, what we are expecting that since it is p-type substrate there will be holes as majority
carriers and because of this positive voltage they may be depleted from the surface
region.
So, you may say that whenever we are applying the positive voltage or the gate, it creates
a field on the surface across this thin oxide and as a result the holes are getting depleted.
So, that is why it is we say that the holes are getting depleted from this region from this
channel region and what happens it is effect it is that it is leaving behind negative ions.
So, these negative ions are basically the stuck with the crystals and they cannot move.
So, they are basically working as depletion region of diode. So, this static ions whatever
the static ions are stuck there of course, they cannot participate for current flow, but they
are whenever we are applying positive voltage, they are basically helping that the those
fields are getting properly getting terminated to that.
So, if I increase this VGS further then what happens? So, if I increase this voltage VGS
further then, whatever the holes it was there near the surface that got pushed away and
then what is happening is from the substrate region the electrons though they are
minority, they are getting attracted. So, in case if we have this n plus region in fact, most
of these electrons may be supplied from this region and this region. So, in as a result in
the channel region we do have a thin layer of electrons. So, let me redraw this part again.
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So, we are applying voltage here VGS and we want to see what other things are
happening particularly when the VGS it is sufficiently high. We do have the static ions
they are not participating for the current flow and in addition to that it is also having
electrons. So, these electrons may be coming from these 2 islands.
So, if you see the property of this channel region just below the oxide, it is property is
getting changed by applying this meaningful voltage. And, as a result what is happening
is more and more while more and more electrons are getting accumulated here; it is
providing electrical connection from this island to this island. In fact, that is what it is as
I said it is making the conductivity from drain to source or source to drain it is getting
modulated by VGS.
Now, if we of course, so, the there is one important value of this VGS. Suppose, this VGS
it is reaching to a critical value called Vth we will see what is the meaning of this Vth.
Such that the concentration of electron whatever the electron concentration in the surface
region. If it is exactly equal to holes concentration in the substrate exactly equal to that,
then you may say that the channel portion it is completely getting inverted into n type
from p type and it is strength is exactly equal to the strength of the substrate.
So, in other words if VGS it is exactly to this critical voltage you may say that this island
to this island, it is getting connected and it is strength it is defined by whatever the
strength it is there in the substrate region. Of course, within the substrate region the
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majority carriers are holes and here the majority or other carriers are electron. So, you
may say that around this. So, around or beyond this point image or at least at this point
you may say that the channel got inverted.
So, if I apply this VGS beyond this Vth then what we had expecting is that of course, more
amount of electrons it will be there and then they will increase the conductivity of this
region further. So, that is what I say that further if we increase this VGS, then what you
are expecting is that this portion the conductivity it will be more.
So, then instead of really connecting the drain and source together or keeping this is
floating if we apply some voltage here. So, you may call this is VDS. And, then it is
expected that since these 2 islands are getting shorted through this channel the electron
layer then there is a flow of current. In fact, electrons are moving from left to right. So,
these electrons are moving left to right and the current it is flowing on the other hand
right to left. So, that is why we call this current is current is flowing from drain to source.
So, whenever we say the I-V characteristic or characteristic equation of the device is
nothing, but this current how it is changing with the voltage here VGS, how it is changing
with VDS? We are going to further detail of how the characteristic equation can be
obtained in the next slide.
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So, here what you see it is that, suppose if we apply the voltage here VGS and also we
apply VDS keeping body and source they are connected. So, we call this is VDS and this is
VGS the current it will be of course, we do have insulator. So, through this terminal there
will not be any current, but then there will be a current flow.
So, this IDS it is flowing here. And, of course, this current it is carried by electrons. So,
these electrons are really moving from left to right by this field or by this voltage, you
may say this is lateral field. So, we can say this vertical field it is getting created by VGS,
which is changing the concentration of the electron on the other hand, the horizontal field
getting created by VDS, which is helping for the movement of the electron from left to
right and as a result we do have the IDS.
So, note that these electrons are coming from this side. So, that is why you call this is
source and it is getting drained to this terminal that is why you call drain. Now, it is very
clear that why you call this is drain and source. So, this current flow IDS it is a strong
function of this VGS, VDS and also it is strong function of the spacing from here to here
namely the length of the device.
So, it is a strong function of the length it is strong function of the other geometry namely
width of the device and also it is strong function of the device parameter, which includes
the thickness of this oxide. Maybe it is referred as tox, then dielectric constant here of this
portion it is referred as εox and of course, the mobility of the electrons in the channel
region.
So, that is what I say that this IDS it is strong function of all these things. And, as a circuit
designer what will be looking for if the device it is already fabricated. So, W’s and L’s
they are already defined then we will be looking for the dependency of IDS as function of
VGS and VDS. And, as a device engineer you may try to change this tox you may try to
change probably in the surface so that the mobility it will be better and so and so.
So as a device engineer of course, so, there are different tricks to improve the device
performance, but as a circuit designer we may assume that these parameters are given to
us and we may consider they are fixed.
On the other hand if it is you are a VLSI circuit designer where the device yet to be
implemented. However, technology is fixed; that means, these parameters are fixed. So,
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you may say that whenever we say technology is fixed device parameters are fixed, but
then you also have the flexibility to change the W’s and L’s of the devices.
So, for VLSI circuit designer not only you will be playing with the applied voltages, but
also the geometry of the transistor. So, in the next slide we will be going for the I-V
characteristic, but let me take a short break and then we will come back.
Thank you.
168
Prof. Pradip Mandal
Lecture – 11
Revisiting MOSFET (Contd.)
So, welcome back here again the second part of today’s module. What we are looking for
it is the expression of the current as function of the W’s and L’s and VGS and VDS. And
VGS and VDS of course, they are applied here. And also, just to get an idea that how this
current is it depends on the device parameter.
So, in the next slide we will be seeing that how the current while the current it is flowing
as IDS how this IDS current it depends on so these parameters.
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So, what will be the expression of this IDS? So, we do have, so this is the big question.
First of all let me quickly put the biases. For vertical field we do have VGS here, so that
creates vertical field. And let me assume that this VGS it is higher than Vth. So, the first
assumption is that this is higher than Vth; that means, the channel is existing. And then
we apply the other potential, so we do have the VDS which is providing the lateral field.
Then, if you see here I think it is let me go with intuitive way that IDS it is proportional to
what? It is proportional to W. In fact, it will be proportional to because if you see here
this is the L and this is the orthogonal dimension it is the W. So, if you are having higher
length for everything is remaining same it is expected that the resistance here it will
increase. So, as a result the corresponding current it will decrease. So, on the other hand
if the W is increasing the corresponding resistance it will decrease. So, you may say
directly that IDS it is proportional to or you can say that aspect ratio of the channel.
Now, how about the other parameters? So, this will be proportional to the conductivity in
the channel regions which is controlled by this VGS ‒ Vth which means that whatever the
excess voltage you do have beyond the threshold voltage that is effectively contributing
the to the conductivity or it is helping to increase the conductivity in the channel. So, we
can say VGS is, VGS ‒ Vth it is directly increasing this current. And also we do have the
lateral field which is getting produced by VDS, so we can also say that this is proportional
to VDS.
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So, if I combine all of them, so what we can say here it is IDS it is say proportionality
constant say × (VGS ‒ Vth) × VDS, ok. And this K, this K it encapsulates whatever the
device parameter is there in fact, this K if you see, if the mobility of the electrons is
flowing in this way. So, if the mobility of the electron is higher of course, the current it
will be better. So, mobility of the electrons is there. And also the dielectric constant of
the oxide . So, intuitively you may say that this represents the capacitance of this
structure which is per unit area of course.
So, for a given supply voltage here the amount of field it is getting created here it
directly depends on this or I should say rather the amount of carrier it will be
available it depends on this ratio. So, from that you can say that this K which is basically
coming from the device parameter they can be directly written in this form. In addition to
that of course, the device parameter is the Vth which is which of course, it depends on
whatever the doping concentration is there in the substrate and so and so, but as the
circuit designer you may assume that both K is constant Vth is also constant.
So, in summary what you can say that this expression of this IDS it is × × (VGS ‒
Vth) × VDS. But one important thing we are missing here it is that, whenever we say that
VGS is higher than Vth and whatever the excess amount we have it is contributing for
towards the conductivity of the channel, but this is valid probably in this portion. Then if
I consider we are applying a voltage VDS which is say +ve, that means, the voltage across
this structure it is not same as the VGS here. In fact, that supposed to be VGD which is VGS
‒ VDS.
So, necessarily the conductivity of the channel towards this drain side and source side
they are different. So, this equation it assumes that the VDS is very small compared to
VGS ‒ Vth. And if the VDS is going to be higher and higher or it is significant we need
some correction in this equation. So, we are starting with this one with the assumption
that VGS is higher than Vth and also we assume that VDS it is much smaller than VGS ‒ Vth
and then only this equation is valid. So, if we increase this VDS let us see what is
happening. So, let me go to the probably next slide.
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So, what you are saying here it is the VDS it is significant particularly compared to VGS ‒
Vth. So, again let me put the quickly put the bias here VGS and we do have the VDS. So,
we do have whatever L and W’s and all these things and as I said that if the length is, so
it is sorry, the VDS it is comparable with VGS ‒ Vth then the conductivity along this length
it is changing.
Hence, this IDS its expression as I said need to be rectified or you need to be changed
compared to whatever we have derived before. So, we are keeping the device parameter
same as µn then epsilon εox, oxide tox and those things it is remaining as is, but then
the conductivity we need to change. So, let us see: what are the changes we need to make
here.
Towards the source side we do have the VGS ‒ Vth. Whereas, on the on the other side on
the other end namely towards the drain side we do have the VGD which is VGS ‒ VDS ‒
Vth. So, we need to consider both this part as well as this part and on an average you may
say that let me take average of it. So, we just simply add them divided by 2. So, what you
are getting here it is we do have.
So, then IDS let me write in this space is this part let me let you call this is K and then W
by L, and then if you see here we do have two VGS and then two Vth and divide by 2, but
then VDS is not there. So, we do have VGS ‒ Vth ‒ VDS. And, also along with that this is
what it is contributing to the conductivity and then also we do have the VDS appearing as
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it is providing the lateral field. So, we are applying VDS also. So, we can multiply this by
VDS. So, you have here, this 2 it is coming there.
So, you may say that now the new equation it is like this and this is this is valid as long
as VGS ‒ VDS, it is which is actually VGD it is higher than Vth. So, as long as this is getting
satisfied then we can say that the expression of the current is like this. In other words, we
can say that the channel is existing here as well as here, but of course, they do have a
different strength. So, you may say that the strength of the channel is kind of tapered. So,
here it is having strong conductivity, here it is weak.
Now, what happens in a critical situation when we are just making this voltage higher
and higher keeping this VGS may be constant and such that the conductivity here it is
approaching towards 0, which means that if it is VGD it is exactly is equal to Vth then
what happens? In fact, till that point also this equation is valid. So, let me use this
equation and let me let me put the condition that VGD = Vth or you may say that VDS. So,
if I say this is equal, so we can say this is equal to VGS ‒ Vth. So, then what happens?
So, this is what we will see in the next slide that if we are increasing this VDS and if you
are increasing such that this is just at the drain in the conductivity is approaching towards
0.
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So, so that is what we are saying here that what happens if the VGD = Vth sorry this
comma should not be there. So, VGD if it is equal to Vth which implies, that VDS = VGS ‒
Vth and then what we have the current expression is and then (VGS ‒ Vth‒ ) × VDS.
Now, this VDS we can replace by (VGS ‒ Vth‒ ), so that gives us the expression here it
is into; so, this portion it is (VGS ‒ Vth) here also we do have (VGS ‒ Vth) here we do
have divided by 2. So, this portion it becomes .
And we do have VDS which is also (VGS ‒ Vth). So, directly you can say this is square.
And this is this is what it is happening when at this point the channel is about to
disappear. This is referred as something called pinch off will not be going in detail of
that, but till this point you may say that this equation of this current is valid. If I take this
VDS beyond this point then what happens? So, again let me let you consider this equation
in the next slide and then we will see what other things are happening there.
So, if the in this condition if I take the VDS higher than (VGS ‒ Vth); so, if I consider equal
then whatever the equation we do have ( ) . Now, if we exceed this one
what is happening is of course, in this portion the channel is disappearing, so obviously,

thinks it will be the obvious conclusion or maybe will be having the tendency that we
may say that the current is not flowing, right and however, we do have the lateral field
VDS.
174
So, if the current is not flowing then of course, from here to here there is no potential
drop. So, then what happens? They will the channel will completely break or what will
happen? Practically, what happens is that the channel is here it may be going till some
point which may not be really going to the drain end. So, you may say that the point
where the channel it is satisfying a condition that the voltage across this structure it is
exactly equal to Vth. You may say that till this point or till the left side of this point the
channel exists and beyond this one the channel does not exist.
The natural question is that then how the current is flowing. Of course, there will be a
current flow because this voltage major part of the voltage it will appear across a small
length or I should say small region of this length and as a result there will be a very
strong field. So, you may say that this portion of the device it is working as same as
whatever the device we have discussed here where at this age the conductivity is
approaching to 0 and whatever the current is flowing here whatever the injection of the
carriers are happening that carriers are basically jumping across this injunction from the
pinch of point till the age of the drain. As a result you may say that the total current
while the electrons are moving in this direction the total current is essentially defined by,
so this IDS it will be defined by whatever the current is flowing say through this device
and now the device it is getting modified namely its length is getting shortened.
So, you may say that this equation it is again valid even in this condition only thing is
that instead of L, I will be having shorter length. So, let me write that we do have KW
and also 2 here and then L minus shrinkage of the length say ΔL, rest of the things it is
remaining same. So, ( ) ; so, then you may say that I do have ΔL and how do I
express from outside. Of course, this ΔL it is getting created by this VDS. So, naturally
this ΔL it is a function of VDS.
So, we may write this (L ‒ ΔL) as like this, you can L take you can take the L outside,
you can make it ( ) in the denominator and then if you take, so that is the
denominator part and then if you take in the numerator what you can say it is is
remaining there if I assume that this part it is very small compared to 1, so by Taylor
series expansion you may take it only one part of it. Let me say that ( ). And this
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ΔL part it is a strong function of VDS. Since this portion is very small again it is normal it
( )
is considered as .
So, you may say that this part this part it is getting replaced by this. In other words we
may say that instead of this one let me directly write L here and let me put this factor
( ). In fact, this is what the equation normally we frequently use and the
condition here is of course, the device it is in this region referred as saturation region will
be discussing that pretty shown. But please make a note that going from this point to this
point it is having some discontinuity if you carefully look into the equation instead of
writing this VDS I should have written this is VDS minus whatever the limiting value and
then only there will be continuity of then only we will be having continuity of the
equation from the previous region to this region.
However, most of the time we considered that this part it is may be small compared to
VDS, so we do approximate this whole thing by ( ). And, if you see that this is the
limiting value of the VDS up to which it was having different kind of behavior and if you
go beyond this one, the characteristic it is all of a sudden it is having a change. So, we
will see that these two regions are having distinct behavior. So, we will be looking into
that in detail while will be comparing this characteristic in the across the two regions of
operation in the subsequent slides.
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So, if we summarize what we said is that the device characteristic it is, it can be said it is
having different regions of operation. Again quickly we do have the VGS here and we do
have the VDS here. So, that is producing rather that is VGS is generating the channels, the
electrons are moving in these directions and the consequence is that the current is
flowing in this direction.
Note that the channel is basically getting created by the electron layers and of course,
along with the electron layers we do have the static ions. Those static ions are working as
depletion region beyond the channel region, but they do not participate for the current
flow, so current is basically carried by the electrons.
Anyway, so the IDS while this IDS is flowing here from terminal side we will see this is
the IDS. So, as circuit designer we may not be knowing what other things are happening
internally, but from the terminal what we can say that some current is flowing and that
current is coming back here, and this current is getting produced by the combination of
VDS and VGS. So, let us see for this I-V characteristic for different conditions of these
voltages and let me summarize that.
First of all if the VGS is less than Vth, so we assume that this channel it is almost very
weak and you may say that instead of saying equal we may say approximately equal to 0.
On the other hand, when the VGS is higher than Vth and then we are applying VDS is +ve,
but it is less than this critical voltage, we may say that it is less than the VGS ‒ Vth which
means that even at the drain side we do have the channel may be the channel is stronger
here may be here it is weaker.
But finally, finally, we do have the channel is spreading across the length and with that
condition we may say that the current here it is (VGS ‒ Vth ‒ ) × VDS. And of
course, this K it is having its own internal device parameter, namely mobility then
dielectric constant of the oxide, thickness of the oxide. On the other hand, if the VGS is
say higher than Vth however, VDS is higher than VGS ‒ Vth in fact; this is referred as
VD(sat).
Of course, this is this is not constant it depends on the VGS sometimes it is referred as
VD(sat) we will see that why it is called VD(sat), but whatever it is if the VDS is beyond this
one indicating that pinch off already happened towards the near the drain end and the
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current it is it hardly depends on VDS and the corresponding expression of the current it is
( ) and in addition to that we do have ( ), ok.
So, ideally as I say that I should have written VDS ‒ VD(sat), but all practical purposes
most of the time we write VDS. So, this is what the overall I-V characteristic equation of
the transistor and if you see here what are the parameters we do have a device parameter,
of course, this is one device parameter and then we can say this is also device parameter
and also we do have device parameter here. So, these are basically device parameters.
The rest of the things are the voltages and the device dimensions.
And as I said that for board level design if the device it is already implemented which
means that W and L of the device it is already implemented, then as a circuit designer
will be having flexibility to change this VGS and VDS to get a meaningful current flow.
So, that is the I-V characteristic. Now, let us look into if I combine all these equations if
we consider the graphical interpretation of this I-V characteristic and the next slide, so let
us see the graphical interpretation of that.
First of all under this condition as I said this current is approximately 0, this is quickly,
(VGS ‒ Vth ‒ ) × VDS and then here we do have ( ) ( ).
So, if you plot this current IDS as function of VGS and VDS what you can see here, this is
of course, it is 0. So, now if we consider this region so probably you can consider two
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cases. So, let me keep the VGS constant and then let you observe IDS as function of VDS
and assuming this VGS is constant, but higher than Vth.
So, this equation indicates that VDS is appearing here in square form and in fact, it is
parabolic relationship. So, if the VDS it is small and if it is smaller than VGS ‒ Vth then
you may say that it is going like a parabolic way. So, this is the equation, I should use the
other color to represent this characteristic curve. So, this equation it is getting reflected
here. But then this equation is valid till this point where VDS = VGS ‒ Vth and if you go
beyond this point the current it hardly depends on VDS in fact.
Typically, this lambda is very small, so you may say that if I ignore this part the current
supposed to be remaining constant. And, if I consider some small that the actual value of
the lambda it may be having slight slopey kind of things which means that this change is
representing the effect of this lambda which is referred as channel length modulation
affect. The channel length is getting modulated by VDS; in fact, this is similar to base
width modulation of the BJT we have considered.
So, if you see here the different regions of operation from this point beyond the current is
getting saturated. So, here we may say that this is saturation region. So, saturation region
of operation and before that it is referred as triode region, triode region. Because the
current depends on both VGS and VDS sometimes it is also referred as linear, particularly
if you see this portion the device behaves like a linear, so either we may say it is triode
region or linear region.
Now, this is for a given value of the VGS. Now, if I change this VGS to some other value
of course, this point it will be changing. So, if I decrease this VGS, but still maintaining
this is higher than Vth we may get lower current and the corresponding current profile it
will be like this and so and so. So, the boundary between saturation and triode region;
however, for smaller value of this VGS it will come down like this.
So, you may say that the boundary between this linear and saturation region it is having
like this equation. In fact, this is a quadratic equation. We will see that what is why it is
really a quadratic equation. If you make this VGS smaller and smaller in fact if we take it
further down. So, what it will happen is that current it will be almost getting 0; that
means, the corresponding characteristic it will be coinciding with VDS line. So, this
characteristic it is referred as IDS versus VDS characteristic.
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Now, if you see say this equation, in fact, you can try to plot the IDS versus VGS also for a
given value of VDS. To start with let me consider the device it is in for a given value of
VDS. So, if I increase the VGS beyond Vth then only the current it will flow, but before
that the current is approximately 0. And if you if you are increasing this current sorry, if
you are increasing this VGS keeping the VDS constant and then you may say that the
device starts from this region or saturation region and hence the dependency it is like a
quadratic.
And, if you go beyond some point where probably we are satisfying rather this condition
instead of this one and the device instead of really going like this it will bifurcate from
that and it may continue to be like a linear one. So, from this point onwards the device
enters into triode region or linear region. And before this point the device it was in
saturation region. So, here the device it is in saturation region.
So, this is happening for a given value of VDS. So, which means that this point it is at this
point the VDS = VGS ‒ Vth or rather you may say that VGS = VDS + Vth, right. So, naturally
if I increase this VDS, I will be getting another characteristic curve where this bifurcation
it will be probably starting beyond this point and so and so. So, normally these changes
we can hardly see. So, in most of the textbook it says that, this is quadratic equation.
Note that this till this point the current is 0, only the current is flowing beyond this one
and the boundary of between this triode and saturation region it is nothing, but this
portion because this character the boundary point it is nothing, but the VGS ‒ Vth curve.
So, you may say that triode and saturation boundary is nothing, but this profile and this
profile it is obtained from this equation where IDS is basically proportional to VGS ‒ Vth
square. So, that is about the graphical representation.
So, let us see: what are the things we have covered today or rather so far we have
discussed in this topic.
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We have discussed the basic structure of the n-MOSFET, and then we also have
discussed about the operating principle of the circuit for different biasing situation. And,
then we have discussed about the I-V characteristic of the MOSFET, and then we have
discussed about the graphical representation of the I-V characteristic equation.
Note that, whatever the equation we have obtained here it is not having really a diode
kind of equation, but we will be having a tendency to utilize those characteristic equation
to represent in the form of you know equivalent circuit. So, later we will see that how
those equations can be used to represent the device by means of electrical circuit
modules. So, that will be discussed in detail whenever will be going to actual circuit
containing MOSFET.
So, in the next module, similar discussion it will be there as we have discussed today, but
then for PMOS transistor. I think that is all today.
Thank you for listening.
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Prof. Pradip Mandal
Lecture – 12
So, welcome back to Analog Electronic Circuits. Today, we are Revisiting MOSFET in
fact; it is continuation of the previous lecture. So, previous day we have discussed about
n-MOS transistors particularly n-MOSFET and, today we will be going for p-channel
MOSFET namely p-type MOSFET.
So, the overall plan what is as, I said that we have discussed in the previous class about
these 4 topics. So, these things we already has been discussed. And, today we are first we
are going to discuss about the similar kind of things, but for p-type MOSFET.
So, some of the things may be a kind of reputation of whatever we have discussed about
n-MOS, but then we will try to compare the situation of n-MOSFET and p-MOSFET. So,
that you should not get confused while you will be dealing with circuit containing n-type
as well as p-type MOSFET. And, then subsequently we will be in case if a time permit
then we will be covering some part of the numerical problems.
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So, to start with let we go for the basic structure of the p-MOSFET keeping in mind that
n-MOSFET in as background information.
So, here the MOSFET for p-MOS type I should say where the channel it is and the
channel it is supposed to be p-type and this is the cross sectional view of p-type
MOSFET. Just for your reference I am also keeping the n channel MOSFET. So, I
should say just for our reference we are keeping n-type MOSFET.
And, the basic difference here if you see that the substrate or the body here I should say
body instead of calling substrate. So, this is n-type, now weakly doped n-type in
comparison with p-type body there for n-MOSFET.
And, the 2 islands here they are which are working as source or drain; they are p-type
islands and rather highly doped p-type islands. And, similar to n-MOSFET here also we
do have the highly doped island for the body connection. In this case the body is n-type
so, we required n+ island and so on top of that we do have the metal connection and then
we are getting the body terminal.
And, similar to n-MOSFET we do have the gate electrodes here and just below that it is
having the silicon dioxide. So, it is having silicon dioxide here and then below that we do
have the substrate or the body. And, then in this case to really create the channel we have
to see what kind of voltage you have to apply at the gate with respect to source and then
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we will see that what are the things are happening in detail, but this is what the cross
sectional view.
The oblique view on the other hand the oblique view it is shown here where this is the
width of the gate or I should say a channel and this is the length of the channel, they are
the important parameters to define the behavior of the circuit rather performance of the
circuit, this is the oxide thickness tox that is also a critical parameter and so, this portion
is of course, it is substrate and so and so.
So, now let us so this is of course, it is more idealistic cross sectional view. So, we have
discussed for n-type device what may be more realistic things and also the top view. So,
let us see for p-MOSFET while we do have p-islands and then n-type substrate what may
be the difference of the top view in comparison with n-MOSFET.
So, here so this is the cross sectional view of the p-MOSFET and this is the top view of
the MOSFET. So, let us see what are the things we do have this is the gate electrode; so,
this is gate electrode and the entire thing actually it is polysilicon. And, then we do have
the other rectangle here which shows the boundary of the divisions region. In fact,
underneath this gate the division is not happening only this portion it is having the
divisions and this portion is also having divisions. And, in this case those divisions are
basically creating the 2 islands p-type islands; p+ islands here and this is also p+ islands.
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And, you might have observed that the gate region it is also not only this side, if this side
also it is getting extended, but then channel portion it remains the same as you have seen
for the n-MOSFET. So, the channel portion is here. And, this is the spacing between the
2 islands, we call length of the device and this is the orthogonal direction of the current
flow or it is called width of the device.
On the other hand we do have the n+ island also and this is the boundary of the other
diffusion region, but this diffusion it is of n-type so you can say n+ and, in fact, the rest
of the things; rest of the things here they are weakly doped n-type. And, similar to as you
have discussed for the n-device we do have the contact here, so this portion is contact,
this portion is contact and so and so.
So, this contacts are basically the substrate contacts and then drain contacts then the body
contacts and so and so, and, then also we do have the gate contacts here, but this is not
really in along this cross sectional view that we have discussed in the previous class. And,
on top of that there are different rectangular box here, so if you see here.
So, this portion it is basically representing the metal-1. So, on top of this contact we do
have the metal-1 here, we do have another metal-1 here and so and so. So, this portion is
metal, this portion is metal and so and so on. So, that is a little bit about the top view of
the actual device. In fact, if you see rest of the things it looks like it appears to be
hanging, but actually here we do have the silicon dioxide and, but then rest of the things
is also having silicon dioxide. In fact, everywhere we do have the silicon dioxide that
provides electrical isolation as well as the mechanical stability.
And, in fact, here also at the surface level also we do have the silicon dioxide; it is
referred as field oxide which isolates one device to the other on the surface. So, that is
the as I said that more realistic view, but we may not be really going in detail of this
structure again and again rather we will be preferring to follow the simple cross sectional
structure to explain the working principle of the circuit.
In fact, this cross sectional view it is more like cross sectional view along this axis may
call AA′, but you may be you might be observing that along this axis and this is not
really getting cut. So, this portion of course, it is not getting cut. So, I should say rather I
should draw this portion in dotted line for perfect engineering drawing, but anyway. So,
likewise probably you can make an atom to draw cross sectional view along this axis,
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say it may be called BB′ ok, along the W. And, you will be seeing that the gate is like it
is having a texture likes this, it is having up and down.
So, this is the gate portion get electrode and then you do have the contacts here you do
have this contact. So, that contact it is here and then it is having the metal connection;
metal connection I should use different color yeah. So, this is the gate connection and
underneath we do have the channel portion.
So, we can see that here we do have the thin oxide. So, here we do have the thin oxide
below of this you know gate region, but beyond this if you see beyond that, this thin
oxide is further getting extended like this. In fact, this portion it is also silicon dioxide,
but actually beyond the channel region. So, you may say that this is the width of the
channel and so, this is the edge of the channel and this is the extension of the gate
beyond the channel underneath us doing have the field oxide like this one.
In fact, this structure I have not covered for n-MOSFET, but it is there also it is similar.
And, for historical reason this gate region earlier it was metal, but then as I said that
because of better threshold voltage adjustment for n-type and p-type device, it has been
observed that it is better to keep this as polysilicon, because of the work from some
difference of the metal to substrate. So, anyway I will not be going detail of that, but
probably you can refer to any device course for that. Now, see how we bias the circuit?
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So, let us about think about the biasing. So, primarily we will be covering the
n-MOSFET p-MOSFET, but just for our reference we are also keeping the n-MOS
structure. So, for your reference if you see this is n-MOS and if you recall how we have
biased it so, for proper operation gate is at higher potential by VGS and most of the time
we prefer to keep this body and source connected together and then at the drain we do
have another potential source we call VDS.
So, for proper operation VGS should be higher than something called threshold, VDS
definitely it should be +ve for the electron to flow from the source to dream. So,
electrons are moving in this direction and that results the current flow in this direction.
Now, this we already have discussed in the previous part. Now, let us see how we bias
the p-MOS transistor on the other hand.
Now, here at the gate we like to prefer to apply some voltage. So, that the channel
supposed to be getting created and we want to convert this channel from n-type to p-type.
So, definitely we required applying ‒ve potential with respect to source as well as body
and because of the polarity the other way we may call this is VSG.
And, on the other hand at the drain we can apply ‒ve voltage. So, that; so, anyway I will
discuss that. So, we call this is since this is source side it is higher potential, we call this
is VSD. And, while you are applying this ‒ve voltage here, it is expected that holes it will
be coming into this channel region. And, because of this VSD it is offering lateral field
and this holes are moving from left to right.
As a result it produces a current in the same direction. And, now this current since it is
flowing from source to drain just to have proper convention of the +ve current flow, we
may call this is ISD. So, you can see the basic difference here particularly the polarity
here we call IDS whereas for p-type device. So, p-type MOSFET we are calling this is
ISD.
So, likewise if you see the polarity of the voltage here based on that we are calling this is
VGS, on the other hand this bias it is called VSD and likewise instead of VDS we call this is
VSD. And, the current flow of course, ISD for this case IDS it is flowing in this direction
and whereas, ISD here it is flowing in this direction, ok.
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Now, since the current flow as well as the polarity they are different and for our
convenience, it is better to keep the device orientation such that the higher potential
terminal to be going upper side and lower side we will be having lower potential.
Namely, this side it will be pulled towards ground and this may be pulled towards the
supply +ve supply.
So, a similar thing probably we can do here also; since, this is a lower potential so,
probably we can pull it low and then we can pull it high like this one. So, let us see how
we; so, let us see how we reorient the device. So, that it will be more convenient to place
the device while we do have many circuits; while you do have many devices in the
circuit.
So, what kind of reorientation shall we do? First thing is that we will flip the p-MOS
transistor, because here we do have lower potential and here we do have higher potential.
And, so, source side as I said we can make it towards the ground and drain side we can
make it out.
So, likewise since you have flipped it, source side we have taken towards the right and
drain towards the left and we know that drain it will be at a lower potential than the
source. So, now, here also we can rotate the device in the same way as we are rotating
the n-MOS device. So, this is of course, n-MOS device and this is p-MOS.
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So, first thing is we have flipped it compared to the previous diagram and then we rotate
it 90°. So, as we are showing here. So, the body and source it is coming towards the
ground and drain it is going towards the +ve supply.
So, here also so, the source and body it is going towards the +ve supply, drain it is going
towards the ground. So, basically we are reorienting adjusting ourselves. So, that the
device orientation it will be consistent in the circuit, the whenever we will be discussing
with the circuit normally we will be placing the device like this. In addition here I am
also showing the corresponding symbol of the devices. So, this is for the n-MOS.
So, this is n-MOSFET symbol and this is p-MOS symbol and if you see here some
conventions, if you have observed carefully that the source is having an arrow. In fact,
this arrow it is consistent with the flow on the current IDS. So, you may recall that the
current is flowing from drain to source IDS though the electron is moving from left to
right and the current is flowing from top to down basically drain to source.
So, this arrow it is consistent with the flow of the current and then we also have the body,
though the body we are taking along this line, but for our convenience just we are
showing like this. And, in the biasing most of the time unless otherwise it is stated, we
may connect this source and body together. So, we may connect these two together on
the other hand if you see the symbol of the p-MOS.
So, here also we place an arrow, but if you see the polarity of the arrow it is from source
towards the drain. So, of course, that is also consistent with the actual current flow and
since the current is flowing from source to drain; so, we call this is ISD and as I say that
this arrow it is consistent with the current flow.
So, here also we do have the body and unless otherwise it is stated source and body may
be connected, but we do have the flexibility, if you are really for some reason if you are
not connecting it you have to ensure that this junction it is not getting forward biased. In
other words the body should be at higher potential than the source for p-MOS and vice
versa for n-MOS.
So, as long as we follow the, that constraint it is not a problem, but for this course unless
otherwise it is stated we assume that body and source they are connected. Sometimes, in
some books we also place an arrow on the body connection and for n-MOS the arrow of
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the body connection it is in this direction from body towards the channel. This arrow it is
really not consistent with the current flow rather there is no current flow rather in fact,
we like to keep this arrow. So, in a direction who is supposed to be representing the
polarity of the diode getting formed between the channel and the substrate.
So, the channel is n-type and the substrate is p-type; so, you can say that arrow of the
body it is basically in this direction. So, this arrow on the body line it is consistent with
that. Please, do not get confused with the arrow on the body line and arrow on the source
terminal. So, similarly here also the polarity of course, in this case it is p-type channel
and the polarity of this diode it will be from the channel to towards the body. So, the
polarity of or direction of the arrow it should be consistent with that namely from
channel to body.
So, that is about the symbol that is about the rotation and all and now let us see how we
get the I-V characteristic of the device.
So, what is the working principle of the circuit and then that will be helping us to really
derive the expression of the current in terms of explain the terminal voltages. So, quickly
let us apply the voltages here. So, what we said is that this is the channel it is we have to
make it p-type. So, it should be at gate should be at a lower potential than the source by
VSG and we have to apply the VSD, yeah. So, we do have the VSD here which makes the
drain side at lower potential.
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So, this is of course, you know we have to make the drain at a lower potential with
respect to source. So, that the current actually it is flowing in this direction and also we
said that the hole supposed to be flowing in the same direction. Now, what other things
are happening here. If, the VSG; if the VSG it is if you are making it more and more +ve.
So, what happens is that the majority carrier namely electrons they are departing the
channel portion. So, which means that by this VSG we are forcing this electron to be
moving away from the channel as a result it leaves behind +ve ions there. So, let me use
different color to represent that. So, it leaves behind the +ve charges at the end, but they
are the static ions of course, they do not participate for the current flow, but they are
instead working like a depletion region.
So, then if you further increase this voltage, namely if you make this gate further ‒ve
with respect to source, then the holes may be getting attracted from the substrate maybe
they are minority carrier, but they will be attracted. In fact, it seems we do have this
island holes it may be rather supplied from this island more. And, as a result there will be
a thin layer of the ions, I should say it is not ion it is holes. So, there will be free holes.
So, let me redraw the channel portion with the change of this voltage.
So, if we further increase this VSG. So, we are expecting that there will be holes just near
the surface. And, of course, there will be the static ions as I say that they are not
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participating for the current flow, but they are basically neutralizing some part of this
potential. So, now, if we apply the voltage here, at the drain with ‒ve voltage here with
respect to the source and then the holes it starts moving in this direction.
So, as a result there will be a current flow and this current it is flowing from source to
drain and then it is going to the drain. So, this ISD it is flowing from source to drain. Now,
before we go for this flowing in fact, similar to n-MOS, VSG it reaches to a value a
critical value called threshold. And, if the holes concentration here it is exactly equal to
the electron concentration deep into the substrate, then we call that channel portion or the
surface of the channel got converted from n-type to p-type and their concentrations are
exactly equal.
So, you may say that the channel got inverted with this and the channel got inverted to a
critical level, where you may say that the channel concentration; channel strength and the
substrate strength in terms for the carrier concentration they become equal. And, if you
increase this VSG further then of course, there will be more and more holes it will be
getting accumulated in the surface. And, of course, they will be contributing more
towards the, they will be rather helping this current to be flowing more and of course, we
are assuming that the body should be connected the end.
So, that is the basic working principle. Now, we will try to see what is the expression of
this current ISD as function of this VSG and VSD, ok? So, we are from let us looking into
what other things are going to happen if we apply the voltage, yeah.
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So, quickly let me apply the voltage. So, we have as I said for our convenience we have
rotated the device. So, let me apply this VSG. Now, it is very convenient that the +ve side
of the potential source, we are connecting towards the upper side and this is VSG body is
connected together; body is connected to the source and then we do have the VSD and the
current it is flowing in this direction.
So, let me use different color here. So, current it is flowing in this direction and that is
ISD and we like to find what will be the expression of this ISD. So, as I said that this
current of course, it will be it depends on these two basic potentials and also it depends
on the size of the channel namely the length. So, this is the dimension, this is length of
the channel and the orthogonal direction is the width W. So, it is function of that in
addition to that it depends on the oxide thickness and then dielectric constant of the oxide
and then mobility of the holes.
So, the expression of the current in fact, it is let me. So, you may recall that for n-MOS
device we say that this is µp, there it was µn and in this case it will be µp. If epsilon oxide
divided by thickness of the gate oxide multiplied by the aspect ratio of the channel,
multiplied by VGS and this VGS it is entire amount it is really not contributing to the
channel.
Some part it is going to the in fact, I should write rather VSG sorry, this should be VSG
and some part of it is going to convert or invert the channel. So, we may say that that part
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it is we have to subtract and then this is what the VSG ‒ |Vth| that is contributing towards
the conductivity of the channel.
And of course, and based on the VSD we do have the current flow due to this whatever
the potential we are generating from source to drain. So, this is the expression of the
current ISD and this is it looks like valid, but similar to the previous case. In fact, this
expression it assumes that the conductivity of the source portion is a function of VSG ‒
|Vth|, but if you see the other end and if you are applying VSD is +ve.
This end, the drain end may not be having the same potential across the assumption. As a
result we have to if the VSD is significant compared to VSD ‒ |Vth|, then you have to apply
probably different formula instead of just considering this one. And, the trick is that
instead of considering only VSG and the VSG ‒ |Vth| we also should consider VDG ‒ |Vth|.
And, this VDG of course, it is function of VSG and VSD. So, if you take average of these
two instead of considering VSG ‒ |Vth| then we will be getting more accurate expression
particularly when the VSD is higher. So, let us see what is the corresponding expression
we will be getting there?
So, for significant VSD what you are expecting there it is the expression of the current it
will be × (VSG ‒ |Vth| ‒ ) similar to n-MOS device multiplied by VSD.
Only difference is that instead of VSG there it was VGS and instead of VSD it was VDS, rest
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of the things it is similar; of course, we do have the µ also it is different, but we can
think of it is just a constant.
So, as long as we are very sure that we have to get the correct polarity of the potential.
And, if it is consistent for the operation of the circuit then it is not a problem. And, this is
valid as long as the channel is existing at this end, but then and this is true only when the
VDG it is higher than the threshold voltage, ok. So, if VDG it is higher than threshold
voltage then only we will be having this channel. In fact, we can rearrange this or we can
rewrite this expression of VDG in terms of VSG ‒ VSD.
So, as long as this is higher than the |Vth|, then only we can say that this equation is valid.
In fact, at the limiting case when this two are equal this part and this part is equal, then
we can say the pinch of it is happening. And, at the limiting case the corresponding
( | |)
current it becomes; so, this portion it becomes, this becomes . Particularly
when so, we can say that under VSG ‒ VSD = |Vth|. So, under this condition, we can write
that this part it is like this and rest of the things it is coming there.
So, if you see; so, if I consider how it is as I say that VDG = |Vth| the expression of the
( | |)
current it is, expression of the current it is . And, if you increase
this so, beyond this one if you rather if you valid this condition namely, if you retain this
VSG to a value and then if you of course, if body is connected to the source.
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And, if you increase this VSD beyond some point particularly if you are valuating this one,
then the pinch of it will happen here the channel will get tapered like this and all these
things it will happen. And, then the corresponding current it will be practically remains
the same as this one, but then of course, depending on the value of this VSD the pinch of
point it will be departing the drain. And as a result the effective channel length it will get
shortened compared to the metallurgical or the otherwise initial length we are having.
So, this length it is getting shortened here to L ‒ ΔL as you have discussed earlier. And,
this ΔL it is of course, it depends on what is the VSD we do have beyond this critical
value and to capture this effect then we consider (1 + corresponding λVSD) part, ok.
So, now we to capture this effect we can say that so, the expression of the current under
this condition. Namely, whenever pinch off it is happening then we can say that the
current here it will be maybe 2 we can take it here. And, then we do have the
VSG ‒ |Vth| in fact, I should take mod I will explain why we are taking mod here
whenever it comes to the situation, but for the time being let me assume that we are
dealing with only the magnitude and this multiplied by VSD.
In fact, we should write VSD instead of VSD we should write VSD ‒ VSD(sat) where VSD(sat)
= VSG ‒ |Vth|. In fact, that is the value where the pinch of it is happening. So, VSD(sat) is
basically the voltage at this point at the drain source drain. So, that the pinch of it is just
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happening, but then most of the time we do ignore instead of considering VSD ‒ VSD(sat),
we prefer to write only this VSD. So, unless otherwise it is stated at least in this course we
will be assuming that VSD ‒ VSD(sat) it is approximately equal to VSD.
So, that basically summarizes the I-V characteristic equation. Probably, we already have
said can you make an attempt to write this summarize this expression, I will not be again
repeating here probably you can do this one and then we will see the graphical
interpretation of this one.
So, let me take a break of 5 minutes and then we will get back to you to go for the
graphical interpretation of the I-V characteristic.
Thank you.
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Prof. Pradip Mandal
Lecture – 13
Ok, so after the break so we are back here. So, let me continue the graphical interpretation
of the I-V characteristic and as an exercise I have asked you to make rewrite this
expression of the current. As I said that if VSG it is less than a threshold voltage or practical
purposes you may say that this is equal to 0.
On the other hand if VSG is higher than Vth and VSD it is less than ( | |). In fact,
this is nothing but the pinch off condition we are avoiding and in this case the current is it
is (VSG ‒ |Vth| ‒ ) ‧VSD. And we will see that as you have discussed for
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n-MOSFET this is nothing but referred as linear region of operation or it is also referred as
triode region of operation.
On the other hand if the pinch off it is happening namely if VSD it is more than VSG ‒ Vth or
so, in that case I must say that the pinch off already happened and then the x the current it
is having hardly any dependency on VDS. So, and this is the k part and then into we do
have 2 here and then ( ) ( ).
So, let us see what the graphical interpretation of this is, and to start with let me let you
consider say for a given value of VSG let you observe ISD as function of VSD. So, initially if
you see a VSD it is less than this voltage which is referred as VSD(sat). So, till that point we
may say that it is parabolic in nature or second order kind of things, but then instead of
really going this parabola beyond that. So, this is the point where VSD = VSD(sat) and beyond
that point the current do get saturates. So, the current remains constant and whatever the
small slope it may be contributed to this lambda called channel length modulation.
So, this portion we call so beyond this point it is called the saturation region and this region
it is from here to here it is missing triode region. And so this is we obtain for a given value
of VGS or rather VSG higher than Vth magnitude. And so if you are decreasing the VSG will
be getting similar kind of characteristic. But of course, the corresponding pinch off it will
happen a different point, because the pinch of course it depends on and the corresponding
VSD(sat) so it enters to the saturation at different voltage and so and so.
So, if you decrease the VSD it will be going like this; so, VSG if you are decreasing and if it
is going towards Vth then it enters to the cutoff region. So, in here we do have the cutoff
region, so the cutoff region it is coinciding with VSD-axis. And on the other hand if you are
observing the corresponding current as function of VSG as function of IS sorry ISD as
function of VSG.
So, here what you can see, it starts with rather saturation first. So it of course, initially it
will be have been cutoff then it is having saturation. In the saturation region, it is having
square dependency and then it goes to the linear or triode region and below this of course
we do have the cutoff region.
So, that is the different range of the; so, this is of course for a given value of VSD and if you
change the VSD two different values, then for smaller VSD it may enter into triode region
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before, then this point or maybe later depending on the value of the VSD. So, this is what
the graphical representation. So, it is very similar as I said except of course, the instead of
IDS we call ISD and instead of VGS we call VSG and so and so.
There is an alternative way of representing this. So, I should say people call it is alternate
representation graphical representation of the same thing, what is the difference there it is
instead of plotting this ISD verses VSD. If you try to plot say ISD verses, rather IDS versus
VDS to maintain the consistency with the n-MOS. In that case the curve it will be I-V
characteristic curve it will be getting shifted to the third quadrant. So, this will be the triode
region and then it will be entering to the saturation region.
So, for different values of, different values of the VGS or VSD you will be having different
kind of different I-V characteristic plot. So, of course, this is for we are discussing about
p-MOS. So, for p-MOS you may say that whenever we are observing we are claiming that
or we are trying to pertain that IDS is the +ve the actual direction polarity of the current is
from source to drain. As a result it is having you may say ‒ve direction current.
So same thing for the voltage also, so if you say that for actual operation source is at higher
potential then drain which means that VDS is actually ‒ve. So, same thing you can it can be
also discussed about the IDS versus VGS. So, if you plot IDS versus VGS instead of VSG as
you can guess that the corresponding I-V characteristic plot it will be it starts with beyond
threshold, it starts with the saturation region and then it enters to the linear region.
And this voltage of course, up to this voltage the current is 0 and if you see that if you
consider VGS is your parameter, then this is the point where the device starts working or
you may call this is the threshold. And, since it is coming on the ‒ve side so, you may say
that the threshold here it is now ‒Vth. So, that is why whenever you are talking about
p-MOS transistor, we may say that the actual threshold voltage is actually ‒ve.
So, Vth in other words for p-MOS device Vth it is ‒ve and to avoid this confusion in this
plot and this plot to get the correct interpretation, we prefer to use the mod here Vthp. So, if
say Vth is given to us it is a ‒ve and if you take the mod then we will be getting on the +ve.
So, in this representation the first representation where we are plotting ISD verses VSD, we
know that the threshold voltage it will be right side of the origin and hence it is +ve. On the
other hand some people as I said are trying to plot IDS versus VGS for p-MOS transistor,
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there of course the threshold point it will be lying on the left side of the origin and hence it
is actually ‒ve, ok.
So, that is about the representation graphical representation of the I-V characteristic of the
MOS transistor. It is better to consider this convention rather than this one, because of the
similarity of the I-V characteristic with respect to npn, but as I said that we need to be
careful about the subscript part, the direction of the voltage and the direction of the current.
So, let us go to some of the numerical problems, probably when you consider the circuit
particularly on an electronic analog electronic circuit where the device may be or really
existing or maybe the technologies already decided. So, in that case what we can say that
whether you consider this equation or this equation.
The parameter there it is we can say that this portion it is constant called K and similar to of
course the n-MOS device and here since it is mobility of the p-type device. So, or I should
say mobility of the holes is involved here and this K it will be different from K for n-MOS
transistor, as a result we may use different value of K and we prefer to use subscript p.
So, this is called transconductance parameter and then if you already have so this is also kp
trans conductance parameter and in case if the device it is already got implemented then W
and L is also decided. So, in that case the whole thing it can be considered as constant. So,
you may say that the whole thing either this one or excluding this two part, this factor is
given to us. So, this is also referred as another constant k with a kp excluding this two. So,
this kp it is referred as transconductance factor.
So, this is parameter and this is factor. So, that you need to be careful and of course later on
we will also see that some another parameter small signal parameter called
transconductance gm. So, this transconductance part it is utilized in multiple places please
do not get confused, one is transconductor parameter K and transconductance factor k and
then transconductance of the device.
So, this one we will see it later. So, in case if we are dealing with a circuit probably the
value of this k or this K it will be given to us along with maybe W and L or maybe you
have two different decide what will be W and L, and maybe for given value of VSG, VSD we
may have to find the current and so and so. And also maybe you have to see whether the
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device it is in triode region or it is in saturation region based on that we may use this
equation or this equation, ok.
So, let us go to some as I said let us move to some numerical example. So, let us see what
we have this numerical example here. So this is of course numerical example using
n-MOS transistor. So, we do have n-MOSFET and the value of key transconductance
parameter it is given to us 1 mA/V2. A threshold voltage of the n-MOS transistor it is given
1 V, λ you can; in this example you consider it is very small which means that channel
length modulation we are almost ignoring, the aspect ratio of the channel it is given to
us as 2.
Now, we do have three parts, so let us let you consider part-(a) and the VGS is given to us is
3 V. We assume that this is connected to source and without loss of generality let us
assume that this is connected to ground. So, we do have 3 V here and then we do have
different values of the VDS and we need to find what will be the corresponding IDS current.
So, we do have VDS. So, if you see here this is 0.5 and VGS is 3 V threshold voltage is 1. So
of course, the device it is on VGS is more than Vth, but you have to also see whether the
pinch off it is happening or not by considering VGD. So, in this case VGD if you see here so
VGD = 2.5.
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So, 3 ‒ 0.5; so, that is 2.5 which is of course higher than Vth, which means that channel is
existing to the drain end also in other words the pinch off is not happening. So, we have to
use the equation the corresponding equation of the IDS. So, let me use this you may recall
this IDS expression that (VGS ‒ Vth ‒ ) × VDS.
So what we have here it is 1 m that means 10‒3 this is into 2, then we do have 3 ‒1, so that
is we do have 2 here and VDS = , yeah. So, this is ‒ 1.25) × VDS so that is 2.5; so, this
much of ampere so you can find what will be the corresponding value. So, only thing is as
I said that you need to be careful that the device whether I have to consider this triode
region or we have to consider in the saturation region, so this is now done.
Now, let us look into the next part-(b) so here VGS we are keeping same, but then VDS we
are changing to 3 V. So, what we have here it is to consider this part we do have 3 V here,
body is connected with this and then we do have here also we do have 3 V. So, as you can
see here VGS is more than Vth of course, the device is on and however VDS since it is equal
to VGS. So, drop across this one it is just 0 voltage.
So, for this case VGD = 0 V, so that means the pinch off is happening because it is less than
threshold voltage. So, the equation will be using for this case it is to find the IDS current we
need to use this IDS equals to and this K which is 10‒3 × which is 2. Then VGS ‒ Vth so
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that is again 3 ‒ 1, so that is also 2. So, that square divided by 2 into ( ). So, that is
λ = 0 into this 3. So, this part becomes 1 and that is how we are getting equal to 4 mA.
So, the current here it is actually 4 mA current. So, likewise you can find this one, here it is
very straightforward the device the pinch off the VDS is further increase compared to this
one. So, the in fact VGD if you see here, now it is ‒ve rather; so, definitely this is the pinch
off is happening. And again, I should use the same equation, only difference is that this
VDS instead of 3, now I should use 5. But anyway we do have this is equal to 0, so here also
we are getting IDS = 4 mA.
So, pictorially you may recall that different region of operation. So, we do have different
region of operation. In first part we are so this is for all cases we do have the same VGS,
VGS = 3 V, but then we do have different VDS. So, for one case we do have 5 V here, so this
is VDS; so, this is VDS-axis, this is IDS-axis.
So, for case-(c), we are here and for case-(b), they are also we are in the saturation region
and on the other hand for case-(a), we are somewhere here. So, (a) is here then (b) is here
and then (c) is here. So, for this case since λ is very small; so, we are getting same level of
current namely 4 mA here the current it was less. So, that is how we can solve numerical
problems probably you can try out now one numerical problem on p-MOS transistor.
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It is similar but of course, I have changed the parameter. So, what are the changes we do
have here, the Vth, |Vth| it is instead of 1 we are considering 1.5. In fact, you may recall Vthp
sometimes if it is given directly it may be given this Vthp is ‒1.5 ok, it is I should say it is
same.
So, here also we consider λ = 0, the aspect ratio = 2 and the transconductance parameter
K it is 0.5 instead of 1.5 mA/V2. So, I will be giving just hint probably you can work it out
VSG, so whatever the difference we do have compared to the previous case now we do have
the VSG here. So, this is for case-(a) and (b) we do have 2.5 and then of course body is
connected here, and then VSD on the other hand we do have VSD this is for first case it is 0.5
V.
And so now, if you see whether in this case whether the device it is in triode region or not
what we have to do. Of course, the VSG it is 2.5 which is higher than the threshold voltage,
so the channel is on at the source end. Now, we have to find what will be the condition of
the VDG.
So, in this case VDG, so VDG it is drain voltage with respect to the gate. So, what we have
here it is the common is source. So, you may write this is VSD and this is VSG all right and
so you can write this is as VSG ‒ VSD. So, this is equal to we do have 2.5 ‒ 0.5 = 2, which is
of course higher than magnitude of this threshold. Which means that, so here also we do
have the channel so that means the pinch off yet to happen and as a result we may say that
this is we have to use the triode region equation and accordingly you can find the
corresponding current here the ISD, right.
So, please do not get confused about the different polarities and all the simplest way of
looking into the device is my suggestion will be like this. If you see here now we know that
gate will be at lower potential with respect to source and to have the channel and not only
the gate should be at lower potential than source. But of course, with at least with this
much of margin to have the channel existing and it is valid for the drain region also.
So, in other words the gate should be at lower potential than the drain to have the channel
and the difference should be at least the Vth. Now if you see here this is the common
terminal source with respect to that the voltage here it is 2.5 lower, whereas for this case it
is only 0.5 lower. Which means that the gate voltage and if I compare gate voltage and
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drain voltage, gate voltage is definitely lower than drain voltage, because this is smaller
and in fact the difference here it is 2 V.
So, I should say gate voltage VG ‒ VD; so, sorry I will take it to the other way VD ‒ VG. So,
that is what we call VDG so that is 2 V. So, as long as this is at lower potential and this is at
higher potential and the difference is at least this much, then you can say the channel is
existing; that means, the device yet to enter into saturation still it is in triode region.
So, that is how you can look into this one. In fact, instead of considering source as the
reference, in practical circuit will be having rather reference it will be towards the drain
and we may be having some circuit here. So, instead of trying to compare this VSG and VSD
and following this one we may prefer that individual node voltage gate voltage and drain
voltage with respect to the common voltage.
So, instead of this formula probably this is what it will be more convenient and you can
find whether drain is at higher potential than the gate by a margin of threshold voltage. So,
that may be a better way to judge whether the device it is already having pinch off or
whether it is in triode region. Probably you can work out for this case and it is of course the
actual solution is the device it is already in saturation.
So, in this case the if you recall the ISD ok, sorry I should write here ISD instead of IDS, so
that you will get +ve entity here. So, anyway ISD versus if you plot VSD. So, since we are
taking care of the subscript, so that the I-V characteristics should remain in in the in the
first quadrant.
So, we do have the saturation region here and then we do have the triode region here and
for case-(a) the device it is somewhere here, so this is the case-(a). Whereas, for case-(b) it
is the device it is it enters into saturation region and this is for VSG = 2.5 V and probably
you can find what will be the corresponding current.
On the other hand for case c of course, the VGS or VSG it is different instead of 2.5 now it is
we do have 3.5 rather. So, the corresponding I-V characteristic it will be different like this
and however this VSD it is sufficiently high probably it is somewhere here, so the case c it
is here.
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So, then you can of course, the device it is already in saturation you can find the
corresponding current. In fact, if you see here quickly the ISD for this case or this case
maybe we consider this case, here it is 0.5 × 10‒3 and then we do have is 2 then we do
have another 2 here and then VSG is 3.5 ‒ 1.5 that is 22 and ( ) = 1.
So, what we are getting here it is this two are getting cancelled we do have 4 here and then
we do have 0.5, so that gives us 2 mA. This is the case for this one, on the other hand for
this case this part instead of 2 it will be 1. So, there you will get for this case you will be
getting 0.5 mA. So, this is you should say 0.5 mA and this is 2 mA and likewise.
So, if you see here we are applying the terminal voltage directly, may not be the case
always like this. So, in case if it is rather if you are moving towards more practical circuit
instead of giving independent supply at the drain and source we may be having rather
different situation.
So, let me frame this problem for you, so we may be having a so this is using n-MOS. Of
course, so let you consider we do have a supply voltage, but then at the drain we do have a
resistance and this is called R and let you also have potential divider to generate the gate
voltage. So, we do have a potential divider here and this is say connected to ground and let
you consider that this is may be may be R1 and this is R2 and let you consider this is this is
getting a DC voltage from a battery say 5 V.
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So, we call this is Vdd = 5 V. Why is it Vdd, because this voltage it is not directly coming to
the drain, it is final it is going to the drain, but through some other element. So, the voltage
here it is referred as Vd to distinguish that Vd and this voltage normally it is used as dd’s.
So, we call this is Vdd and this is 5 V and for this case let me consider that this may be say
2 k or 20 k say, 20 kΩ and this is let you consider 30 kΩ.
So, that makes this potential divider making this voltage equal to so, 5 V it is getting
divided by these two resistors and the voltage coming here it is 2 V. From the potential
divider you can get and in fact since the current to the gate it is 0. So, even after connecting
this gate to this node the voltage remains 2 V unlike VGD. So, dc wise at least it is not
drawing any current.
So, the so that makes the voltage here directly coming from this 2 and so if this is 5 V and
then if this is a 1 kΩ, can you find what will be the IDS. So, how do you proceed, first of all
for simplicity suggestion will be first you assume that device it is in saturation region,
because the expression of the current in that saturation current it is relatively simple.
So, we considered IDS = and 2 also and then we consider ( ) , ok. So, we
assume that λ is approximately 0; so, we can ignore the IVDS dependency. So, this makes of
course which we are assuming this one and end of it we also have to verify. In case if the
device it is not really in this region saturation region, then you have to use the triode region
equation and then you have to solve the second order equation to find the VDS.
So, let you consider say this case first and probably in this case the device it is in saturation
region. So, the voltage here it is 2 V. So, this part it is 1 and so here whatever the
parameters are given here it is K = 10‒3 and it is 2 and then we do have another 2 here
and then we do have this is 12. So, that gives us 1 mA current.
So, we do have 1 mA of current and we do have 1 K resistance here. So, if this current is 1
mA then drop across this one it is only 1 K × 1 m. So, this is 1 V. So, we have 5 V here the
voltage coming here it is 4 V. So, the voltage here it is 4 V and if it is compared. Now we
do have 2 V here we do have 4 V here. So, if you see the gate voltage and says source the
drain voltage difference of course, gate voltage is lower than the drain voltage.
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As a result we already have the pinch off happening which means that the device is in
saturation. So, then our initial assumption is correct. So, then we are correctly getting this
1 mA of current. Now let us see the other case, so instead of this one let you consider this
case and again let you start from this assumption, that device it is in saturation and if that is
true then the current here it will be oh sorry we already have considered this case sorry. We
already have considered this 1 mA and if it is 1 K then the voltage drop here if this is 1 V
and then we do have 4 V here. So, the device in saturation in fact the device is here as well
as here it is in saturation.
In this case of course, the drop here it will be less rather it will be only 200 mV. So, for this
case the voltage at this point it is 5 ‒ 0.2. So, that is rather 4.8 V and anyway the device is
remaining in saturation. Next part it is that can you find the value of this R or rather
maximum value of R. So, that the device it is just in saturation.
So, to find that you need to know what will be the voltage require here. So, that the pinch
off it is just happening, if this is 2 V and threshold voltage is 1. So, the pinch off it will just
happen when this voltage it is 1 V. So, to find this one I should start with this 1 V and then
if the current here it is 1 mA for this VGS, if the device is remaining saturation. So of
course, at the verge of that saturation the current is also 1 mA assuming λ = 0.
So, the drop across this 1 for this Rmax; so, Rmax × this 1 mA should be equal to 5 V ‒ this 1
V so that is 4 V. So, that gives us Rmax = so that is 4 k. So, this R it can go as high as
4 k without any problem, but then if this resistance is more than this one. So, let us
consider this is 8 k. So, then what happens.
Probably you can find what will happen if R = 8 kΩ then what happens, what will be the
current. Whether the current will increase or decrease of course, the device would it will
enter into triode region. So, probably later on we will see what will happen. But for most of
the analog circuit we prefer to keep the device in saturation region, probably for analog
circuit then we will not be really venturing out to increase this R beyond this value, in case
if you are increasing the diode the device it will enter in triode region.
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So, let me at least give one numerical problem similar to the previous case and however let
me use different of course the appropriate bias condition. So, we do have the Vdd here Vdd
we consider this is 5 V. So, that is getting generated by a potential say 5 V with respect to
ground and then here we do have the bias circuit namely, the resistance connected to the
drain and finally it will be going to the same ground. And here we can probably we can
keep potential divider like this and this potential divider is providing a voltage for the gate
so here also the current is 0. So, whatever this R1 and R2 is ratio based on that we can find
what will be the voltage here.
So, that will set the, whatever gate voltage or VSG and then for different conditions here,
we can find know whether the device it is in saturation or not. So, for a similar situation let
me create the similar situation here also. So, let we assume that this is say 20 k and this is
saying a 30 k. So, the voltage here it is 3 V. So, that makes this voltage VSG = 2 V, it is
similar to the previous case where VGS it was 2 V and the parameter here it is given similar.
So, we can say that if I assume the device it is in saturation, the current flow here it will be
with the same calculation it will be 1 mA. So, if I consider first case then of course, the
drop here it will be 1 V. So, the voltage here it is 1 V and the voltage here it is 3 V. So, that
makes the gate voltage 3 V and this is a1 volt. So that means towards the drain we do not
have the channel. That means, the channel the pinch off already happened which means
that device it is in saturation region. So, then that assumption is correct and hence the
corresponding current it will be 1 mA.
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So of course, if the resistance is smaller definitely this drop it will be smaller. So, that
makes this device still I mean, rather comfortably remaining in saturation region. So now,
let me change this problem slightly different one. If I change this say the this resistance to
say 30 k and this resistance to 20 k and then for this case if it is 1 kΩ, can you find what
will be the corresponding ISD current.
So, this is I should write ISD, so probably you can find for this case. If R = 1 k you can find
what will be the ISD, and check whether the of course, procedure it will be same. You can
start with the assumption the device it is in saturation and then you can verify it. I think that
is all we need to cover related to device.
So, what are the things we have covered? So, far the basic structure of the and the p-MOS
and we have compared with a MOS transistor, then biasing and operating principle of the
MOSFET; p-MOSFET, characteristic equation, I-V characteristic equation of the mass
transistor, graphical representation of the characteristic equation and some of the
numerical examples. Simple numerical examples to find the current under certain bias
conditions. So, this ends to our prerequisite and from the next module we will be directly
going to analog electronics in detail, we will start with a simple circuit that is all.
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Prof. Pradip Mandal
Lecture – 14
Analysis of simple non - linear circuit containing a BJT
Welcome back to this course on Analog Electronic Circuits, myself Pradip Mandal
associated with E and ECE Department of IIT, Kharagpur. So, after our previous
modules in week-1, now we are in week-2 and we are going to discuss about the BJT and
MOS related circuits. So, we will start with Analysis of simple non-linear circuit
containing one BJT and later we will be discussing about one MOS and so and so. So, let
us look back what is the topic we do have and what are the overall flow we do have in
our program. So, this is what we do have in overall flow. So, we have completed the
component things.
So, this is already done and now we are at this stage in building block and as I said that
we are in week-2. And, we are going to start with analysis of simple non-linear circuit
containing transistor and today’s focus is BJT. So, what we will be doing is that we will
be focusing on input to output transfer characteristic of non-linear circuit. And, then also
we will be discussing about the signal amplification, how this non-linear circuit
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containing one transistor may be helping us to change the signal rather amplify the signal.
So, what are the concepts we are going to cover today it is the following.
So, as I said that we will be analyzing non-linear circuit containing one BJT and the
configuration will be discussing primarily it is common emitter configuration. Then we
will be going to the how to get input or output transfer characteristic of this common
emitter configuration. And, then we will be discussing about the signal amplification, the
notion of signal amplification through this non-linear circuit containing one BJT. So, we
are going to start with the in the first topic with an example. So, we do have this basic
configuration namely the CE kind of configuration.
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So, as you can see the circuit example is given here and the and also if you see the circuit
that at the base node we do have a bias VB without having any feminine equivalent
resistance. Emitter it is connected to ground and the collector it is connected to +ve
supply, but then through a resistor R. So, we do have the collector at which we are giving
a bias through this load resistor or sometimes it is called directly you can say RC, but
whatever it is. So, this circuit we are going to discuss more detail about how we analyze
this circuit and what are the things we do have it is information wise, if the transistor it is
in active region of operation.
Then its collector current, it is having exponential dependency on base to emitter voltage
incidentally that is base voltage VB. And, also it is having this the parameter of the
device; you may say that this is a reverse saturation current equivalent to a diode reverse
saturation current. In addition to that we do have a factor representing the effect of
collector to emitter voltage on the collector current; namely . And, also if the
device it is in active region the base current it is again it is having exponential

dependency. So, of course, here also we do have reverse saturation current, but of course,
this parameter and this parameter they are different.
Ratio of these two parameters are basically the current gain for in forward direction; so,
that we have discussed already. So, this is . So, this is what the information it is
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available to us and we are expecting that the device it will be retained in this active
region of operation, then only this equation it is valid. In this problem what you have to
do, we need to find the operating point of the transistor or operating condition of the
transistor; namely the base voltage intuitive is given. So, then the remaining things are
the base terminal current and then the collector terminal current and the collector to
emitter voltage or you can say directly the collector voltage as emitter voltage it is
connected to ground.
So, that is what we need to find and we will see that what may be the procedure to find
these three namely the base, base terminal current, collector terminal current and
collector to emitter voltage. So, how do you proceed? So, probably we can say that first
we can find the value of this or the expression of the IB, then we can get the IC and then
we can go to the VCE. So, let me take the next slide where we do have the detailed steps.
So, yeah; so, here you may you might have observed that we have dropped this term
( ); intentionally we have dropped this term. For simplicity that is what normally
it is done, we assume that this early voltage it is very high compared to the VCE and
hence we drop this part. So, let me drop this part and then we do have these steps.
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Namely first one it is, the step to find the base terminal current and the base terminal
current we can directly you can use this exponential equation. And, you might have seen
here that this is the actual circuit and the transistor it is getting replaced by the equivalent,
equivalent circuit here. As we have discussed in the when the device related discussion
where whenever it is required the transistor may be replaced by equivalent circuit. This
equivalent circuit consists of the base to emitter diode and whatever the current it is
flowing; if you multiply this by βF that gives us the collector current.
In other words the collector to emitter current, it is actually current dependent current
source and the influencing current is the base current and the corresponding factor it is βF.
So, this is the equivalent model of the BJT. And so now, if I consider the base part
particularly base bias part namely this loop; since we do not have any resistor we can
probably directly find the expression of the base current in terms of VBE because, the VBE
it is directly available.
So, VB which is coming to the base; ground is; emitter is connected to the ground; so,
VBE it is actually VB. So, we can directly use this equation. So, we are assuming that the
reverse saturation current namely , it is given to us and then using this equation we
can find the IB.
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In case if we consider a generalized one later we will discuss in case if you consider a
resistor thermal equivalent resistor, then the procedure it will be different. Now, once we
find the base current next step it is we need to find the collector current. So, either for
collector current either we can directly use this equation because the base emitter voltage
it is given to us. So, this part it is actually as I said that it is nothing, but the VB.
So, either we can directly use this one or we can use this equation and then we multiply
with βF to get the IC current. So, we may get IC = βF × IB part, ok. And once we so, either
we can use this one or we can use this one and once we find this collector current then
our next step is to find the collector to emitter voltage.
So, this is the collector to emitter voltage VCE. Now, how do you find the collector to
emitter voltage? We do have this circuit where we do have the VCC connected here. You
might have observed that whenever we are writing this node as VCC indicating that with
respect to ground one DC source is connected here as you can see here. So, that has been
that has been equivalently you know drawn like this. So, if we consider this circuit,
particularly this circuit where this node it is connected to VCC and then we do have a
resistor here. And, then we do have a current dependent, current source and its
expression it is given here.
Now, our task is to find the VCE and as you can see here at this node KCL suggests that
this current is the current flow through the resistor, it is supposed to be same as on the
current here and also the voltage here it should be consistent. So, that the voltage across
the resistor after deducting this VC from VCC divided by whatever R should be consistent
with this IR. So, we need to satisfy both KCL and KVL for this demarked network and
for that we may say it may be having a generalized procedure. Namely, we can say that
this part is pull apart and this is pull-down part and then we can compare their
characteristic.
And, then we can find what may be the solution point which is giving us consistency of
both the circuit; the pull-up and pull-down. So, we call this part is the pull-up and this
part it is pull-down part. So, let us see the generalized procedure to find this VCE and
since this kind of circuit will be frequently experiencing; so, it is better let me discuss
little detail considering this is as an example. So, what we have there it is yeah. So, this
is the as I say that let us look into the generalized procedure to find the VCE voltage.
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So, what we are trying to get basically let me use a different color here, we like to find
what will be the VCE voltage here. So, that this collector current after obtaining this
collector current this current need to be consistent with the current flow here namely IR.
And, when you say that consistent is basically these two currents are equal because no
other branch it is connected to the collector terminal. So, the IR should be equal to IC; so,
that is the first thing IR should be equal to IC for KCL at the collector node.
And, then on the other hand if we consider KVL; so, we do have VCC here. In fact, VCC it
is basically saying that we do have VCC connected to ground, ok. So, if I consider say
this loop on the other hand what we can say that KVL suggests that VCC equals to the
drop across this resistance R and then plus VCE, in other words that the VCE and this one
should need to be consistent. So, this is this is the equation we are getting by following
the KVL. Now, individually if I say that this part and this part they do have their own
characteristic. So, say for example, if I consider resistor it is having its own
characteristic.
So, what we have for the characteristic for the resistor? In fact, if we if we say sketch the
current IR as function of the voltage drop across this resistance, it is basically a
characteristic going through the origin. And, the value of the resistance it defines the
slope namely the slope here it is ; so, slope here it is . So, we do have as I said we do
have KCL, we do have KVL and then we do have the characteristic of the resistor or the
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pull-up element. So, we call this part it is pull-up element. Why do you call it is pull-up?
Because, in case if nothing is connected the output node it will be pull to VCC through
this element; so, we call this way it is pull-up element.
On the other hand and the lower one which is we are calling with the same logic we are
calling this is pull-down element. So, this pull-down element is also having its own
characteristic and what is that characteristic is basically the device characteristic. So,
either we consider this model or either you consider this model or from the device
equation we may write say IC as function of VCE.
So, as you can see here for a given value of VBE, if the early voltage is very small. So, we
can say if the device it is in active region of operation the IC it is having a hardly any
dependency on the VCE voltage. So, you may say that it is practically this is flat.
Now if I so, this is the so, these are the things we do have in our hand and we have to
make all of them are consistent; namely the pull-down characteristic, pull-up
characteristic and KCL and KVL. So, if you see here if we if you say that KCL; that
means, these two axis need to be same; whereas, VR and VCE of course, they are not
same, but they are related like this. So, we may rearrange this equation and we may say
that VCE = VCC ‒ VR. So, we may say that this is nothing, but VCC ‒ VR.
Now, KCL suggests that these two IC and IR at the solution point should be equal, but
then of course, VCE and VR they are not same, but of course, they are related through the
KVL. So, what you can do? The we can retain this pull-down characteristic; so, we call
this is pull-down character or pull-down element characteristic and then on the other
hand this is pull-up characteristic. So, one of them probably we can rearrange. In this
case normally what it is done is that since we need to find the VC voltage; so, we can
probably retain this one and then we can rearrange.
So, while we are rearranging we have to end of the rearrangement we like to get the
x-axis need to be consistent with this. So now, let us try to rearrange this one. So, we will
retain this one; so, then let me try to write the VR in terms of VCE namely VR = VCC ‒
VCE. Now, to get this VCE for this axis; since it is having minus sign first thing is that we
can probably plot this IR versus ‒ VR so, that we can get rid of this ‒ sign. So, once we
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plot this IR versus ‒ VR which is now VCE ‒ VCC. So, then of course, this characteristic it
is instead of in the first quadrant it will be getting shifted to the second quadrant, ok.
So, the slopes of this characteristic namely pull-up characteristic in this graph it will be ,
but of course, having a minus sign. Now, still this x-axis of this graph, it is not consistent
with VCE it is having ‒ VCC part. So, what you can do? Probably we can add VCC here
and we can get rid of this VCC. So now, let us do the further rearrangement. So, we have
rearranged this graph here and then still it is not consistent. So, let me further rearrange
this pull-up characteristic. So, IR versus instead of ‒ VR let we observe VCC ‒ VR.
Now, this is of course, it becomes equals to VCE and once you consider this x-axis as VCC
‒ VR, this characteristic it is getting shifted by VCC amount. So, this characteristic curve
it is getting shifted by this amount which means that this point is getting shifted by VCC
amount. So, the point here it is actually this this point it is VCC and the slope here since it
is ; it can be shown that at this point where the x-axis namely (VCC ‒ VR)-axis it is 0,
it is the corresponding current it is .
Now, if you see this characteristic the graph here the y-axis and x-axis if you observe and
if you see the corresponding KCL then of course, these two quantities need to be equal at
the final solution point and also this two axis we already have translated to be equal. So
now, if we overlay this two characteristic namely the original pull-down characteristic
and the rearranged the characteristic. So, what we are getting here it is the corresponding
solution point.
So, if we overlay here what we are getting the load line what normally it is referred as
load line characteristic. In fact, load line characteristic is nothing, but the characteristic
of the pull-up element after this rearrangement, where the characteristic it is cutting the
x-axis at VCC and as I say the slope it is . So, the slope here it is and hence the
point here it is and for this characteristic of course, the y-axis it is IR.
Now, wherever these two characteristic they are intersecting indicating that this is the
value of the current and the corresponding voltage namely the value of the VCE which is
making both the pull-up and pull-down consistent; that means, they are satisfying KCL
KVL, their characteristics are also respected and hence that is the solution point.
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So, the, this point as we see it that and the procedure wise what we do? We rearrange the
pull-up character characteristic in this form. So, that they are x and y-axis they are
consistent and then once we overlay the intersection point represents the solution.
Equation wise of course, you may say that this is this is pictorial generalized method, but
of course, the equation wise what we can say that let me use different color here.
So, the VCE whatever the VCE we are getting here. So, let you call this is yeah. So,
this is and then corresponding . So, it is let me use this space. So, is
VCC ‒; so, this × R. How do you get that? So, at this point the corresponding current
of course; so, we probably we can write here this is and here it is or . And so,
the V CC it is here, slope here it is and if you see that the point at which the current
is ; so, then this voltage, this slope and this current and this voltage that makes
consistent.
So in fact, if you see since this is straight line you may say that VCC ‒ right and
since this is 0 current and this is IC current. So, the slope here it is divided by this
difference and this difference is VCC ‒ and that is equal to . So, from that we can
get this solution. So, this is as I said pictorial one and this is the actual one and of course,
here to simplify the analysis we have assumed that this early voltage is very high that
makes this IC current it is independent of VCE. In fact, if you know this value of this IC
from this equation you may directly say that this is .
So, you may say that this is approximately equal to and this approximation involves
that early voltage it is very high. So, we considered this early voltage is very high and
hence this whatever the current you are obtaining here we can directly say that this part
is the approximately and this directly you can plug in to get the VCE.
So, practically what you do it is basically once we get the IB current we multiply with βF
and that gives us . Then we multiply with IR and then from VCC we subtract this part
which is nothing, but the drop across this resistance that gives us the VCE, ok. So, that is
the procedure of finding the solution point or you may say that is the analysis procedure.
Let us see what may be the variance in case if we have a resistor in the bias circuit at the
base.
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So, let us consider the corresponding example where we can put a resistor here and
instead of calling this is VB; we may call it is something some other we can use different
notation; let us call it is VBB. And, this may be whatever RB and of course, that voltage it
is not directly giving the voltage at this one. So, we require additional procedure to find
the corresponding IB current, because the VBB it is not giving us the VBE voltage. So, let
us look into that example. So, let me go to the next slide yeah.
So, yeah this is the circuit where we do have the same circuit the BJT, its emitter it is
connected to ground, collector it is connected to the supply, VCC through a resistor called
RC. Earlier we are calling this is R, now we are calling RC and at the base basic
difference here it is at the base we are connecting a positive voltage here to make this
junction forward biased. We do have a resistor here and in this case what may be the
procedure to find the operating point.
So, here we need to again here we need to find the corresponding operating point namely
IB finding IB, IC and then VCE voltage and the, but then first procedure it is; the first step
it is we need to find IB. So now, since as I say that since this external voltage it is not
directly coming to the base ok; so, this is the equivalent model of the BJT.
So, at the base we are getting a different voltage of course, this voltage it is function of
VBB, but it is not same as this one emitter node; however, it is connected here. And, once
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we get say IB probably either you can use VBE or the better approach is that simply
multiplied with βF to get the collector current.
And then of course, once you get the collector current to find the VCE we can analyze this
part and the procedure it is same as what we have just now discussed. So, compared to
the previous example here the additional thing we have to do it is we have to follow
some sub steps to find the corresponding base terminal current. So, what are their sub
steps? In fact, you may consider this and this loop this loop as equivalent non-linear
circuit, diode non-linear circuit which we already have discussed when we have
discussed about the simple diode circuit analysis, where instead of diode we do have
base to emitter junction diode of course.
So, here we do have VBB, we do have RB and then we do have diode here and drop across
this one instead of VD, we may call this is VBE. And, since it is non-linear again our task
is to find this current and maybe this voltage. So, since it is non-linear circuit, the
procedure to find the solution it may be we can deploy the similar technique. Namely, we
consider this part is the pull-up element and the diode we can think of it is pull-down
element. So, this part it is the pull-down element and then our main objective here is to
find this current. So, of course, at this node KCL we have to give it respect and then also
the KVL.
So, what we can do? Again the general procedure wise the pull-down characteristic we
can sketch. So, this is the pull-down characteristic, it is exponential relationship. So, let
me say that this is the current through the base and this is the voltage across this base to
emitter junction.
And, then if I consider the so, this is the pull-down characteristic and then the pull-up
characteristic if you see and then if you rearrange the pull-up characteristic as we have
discuss will be getting load line like this, where this point it is equal to VBB, this VBB and
slope of this line it is it is sorry this is RB.
And so, then the point here the load line it is intersecting the current axis it will be
and wherever they are intersecting that gives us the solution; namely that gives us the
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base current we may call that is the solution and then corresponding voltage here
it is , ok.
So, that is the graphical procedure, but what may be the actual method we should follow
to get the numerical value; namely what may be the equation and all. Well, either you
can go through iteration; so, if you know this characteristic and then if you know the load
line then you can start from this point and then whatever the for diode circuit we have
discussed about iterative procedure to find the solution.
Or, more practical method it is instead of considering this diode characteristic and the
detail diode characteristic what we can say, we can approximate it by considering this is
piecewise linear. And, in this piecewise linear what you can say that for diode we say
this is cut in voltage whereas, for this case we call it is VBE(on). Namely, it is once the
base to emitter junction it is forward biased and if the device is on then whatever the
voltage drop it will be appearing there you may say that is the VBE(on). But of course, it is
only showing this point and since this characteristic it is having a finite slope the voltage
here it will not be exactly this one.
So, what you can do is that you may say I do not have this value unless otherwise I know
this slope. So, it is more like a chicken and egg problem which one to where we can start
from. So, instead of iterating this actual load line and actual diode characteristic probably
you can you can iterate over this line and this line. And, if you know that the drop across
the diode here it is almost this VBE(on) it is almost close to this point. So, what you can do,
you can probably you can consider this it is approximately this point and then you
can find the corresponding approximate .
In other words we may see that practical procedure it is equals to or approximately

equal to; so, whatever the current will be having here. In fact, that current it is nothing,
but from the VBB ‒ VBE(on) assuming that this VBE(on) is given to us divided by RB. How
did you get this one? In fact, if you see here it is very simple the slope of this line it is
with a ‒ sign. And, if I know this point and if I know this point where the current is 0 and
the voltage it is VBB; so, the slope of this line you can get directly from that. So, you may
yeah; so, from that we can find what will be the and the corresponding current.
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So, in other words we can see now = , ok. So, that gives us the . So,
once you get this approximate ok; let me just write this equation where did I get
it from. As I said that if I consider slope of this line and if I know this point on this point,
then the slope of the line it is basically I do have or whatever you say approximate
minus current here it is 0 divided by the voltage here that is VBB and the voltage here
it is approximately VBE(on). So, this is nothing, but and from that we obtain on this
one ok.
So, anyway in case this if you really want to find what will be the more appropriate value
of this sometimes we consider this is approximately equal to VBE(on). Or, in case if
you are really interested of getting this value you need to find this slope. And, slope of
this line it is basically variation of the current divided by variation of the base to emitter
voltage. So, you may say the slope of this line it is , for diode it is ron; in this case it is rπ,
later we will discuss why it is called rπ.
So, if I know this rπ; so, from that you can get more accurate value of this one and in that
case to find this one what you have to simply do; you have to you have to basically
adjust this equation instead of considering only RB here you have to consider that
resistance. And, how do you get that? It is very simple, if I replace this diode by an
equivalent circuit like this where the drop here it is VBE(on) and the resistance here it is rπ
So, if that is connected here; so, instead of this one if I use say this circuit, now it is very
simple that to find this current I have to consider VBB ‒ VBE(on) that is the drop across
RB inside a series with rπ. So, that gives us the current.
So, it is as simple as that and as I say that once we know the IB then we can find the
corresponding IC by multiplying with βF. And then then of course, we consider this part
to find the corresponding output voltage namely VCE it will be equals to VCC minus drop
across this resistance RC × IC. I think that is all we have to consider. Now, we can
probably we can discuss some more circuits, particularly where if the voltage here it is
changing what may be the corresponding effect coming at the and the collector current as
well as the output voltage. So, let me take a short break and then we will come back.
Thank you.
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Prof. Pradip Mandal
Lecture – 15
Analysis of Simple Non - Linear Circuits Containing a BJT (Contd.)
Start sir.
Welcome back after the break.
So, we do have this slide which is as I said very busy slide. So, what we have seen is that
by considering the base loop we can find the base current and then we can precede for
finding the collector current and then we consider the collector loop. So, this is the base
loop and then we do have the collector loop. So, this loop it is getting completed by
whatever the DC voltage we are connecting here with respect to ground.
So, now let us see instead of giving this the voltage here by this mean. Let me see what
are the different ways the signal can be given to the base of the transistor and let us see
what is it is different implication for different cases of applying the in the voltage at the
base.
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So, here we are throwing this new you know words called common emitter circuit
configuration. So, let us see what it is. So far we are discussing about this transistor, it is
at the base we are connecting something and then the collector we are observing it is
corresponding effect. While keeping the voltage at this node some DC voltage with
respect to ground
Now, here if I give a voltage directly at the base and let you call that we are applying a
voltage here and let you call this is input voltage. And if we vary this voltage the
corresponding effect we like to observer the collector. So, we may say that we are
observing the effect at the collector and hence let you call this is the output port and so
and then this is input port.
So, the voltage you are applying here we are calling it is Vin and the corresponding effect
will be observing at the collector with respect to emitter let you call this is Vout Now, we
have discussed that what are the things it will happen for a given voltage at the base. So,
in case if the voltage it is directly coming to the base, we have said that at the base side
we do have I-V characteristic.
So, that gives us basically the base current. So, if I say that this is the V in which is
incidentally same as VBE of the transistor and we know that this is having either you may
say exponential in nature or we may say that we can approximate by linear line or
whatever it is.
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So, then from that we multiply with beta f to get the corresponding collector current. So,
what we are getting here directly if I write that this is the Ic versus the same Vin. So, we
are getting the Ic versus Vin like this. So, based on this scaling factor the corresponding
scale here it will be different, but the nature here and this one it will be essentially same.
So, we may say that the based on this condition we are getting the corresponding
collector current. Now, if you see the output port which is having the equivalent circuit
likes this. If I ignore the early voltage effect, so we do have Rc and then we do have the
VCC and then we are observing the corresponding output voltage here. So, you may call
this is Vout that is what we are calling and incidentally that is same as VCE. So, if we draw
the I-V characteristic of the output port on the other hand namely the Ic versus VCE
characteristic.
So, which means that for a given value of current say or let me start from here for a
given value of Vin say at this point we multiply with βF then we are getting the
corresponding collector current and this collector current is giving us at the output
terminal and that current is flowing through this Rc.
So, if I ignore as I said if I ignore the early voltage, then you may say that the collector
current it is almost independent of this VCE and so the you may say that pull-down
element characteristic it is you can say it is horizontal. On the other hand the load line
namely the characteristic of the Rc it is giving us the corresponding load line ok.
So, now this is what earlier also we have discussed. Now see what are the things it will
happen in case if we are changing this voltage. So far for a given value of Vin we are
getting the corresponding solution here namely the same collector current is coming here
and then we are finding the solution here do which is VCE incidentally that is equal to
Vout.
Now, if I increase the say input voltage by some amount, which means that VBE of the
device it is getting changed to some other value. So, from this point we are moving to
this point. So, likewise the corresponding collector current is also changing up. This
means that it is corresponding characteristic or what you say that pull-down element
characteristic got shifted up ok, assuming that the device it is still in active region
particularly while it is crossing this load line.
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And while we are increasing the input voltage the characteristic of this Rc did not change
only pull-down element characteristic it got changed from the violet color to the blue
color. So, due to this change of the Vin what you can say that this intersection point got
changed to this point, in other words the corresponding output voltage now will get
change to this point.
So, let me put a number here. So, let me call this is the first case, for first case we do
have this current. So, let me write this characteristic is for the first case and the
corresponding Vout here it is we call it is Vout1. So, this is also first case. Now, the second
one the let me use a different color here. So, now we do we are at this point so; that
means, at the input we are applying Vin2 earlier it was Vin1.
So, now we are at this point and then the corresponding characteristic also got shifted up
and the intersection point going from this point to this point. So, we call this
corresponding output it is say Vout2. So, likewise if on the other hand if we decrease the
input voltage to a lower value say here let me call this is Vin3. So, that gives us say
collector current somewhere here and that gives us the pull-down characteristic here.
So, now the intersection point it got shifted here. So, initially it was here it got shifted to
this point now it got shifted down on the other direction to this point. So, the
corresponding voltage here will be calling say Vout3. So, if I vary this voltage and if we
monitor or if you observe this voltage we can see that this variation it is creating an
effect here.
And this effect if you see here incidentally while we are increasing this voltage the
voltage here it is decreasing and vice versa, but most important thing is that, if we
change a small amount here the corresponding variation here it is more. In fact, it is
actually it is related to the slope of this line or slope of this line and slope of say the load
line. In other words if I vary this Vin and if I create the corresponding change in Ic.
So, if I vary this Vin like this the corresponding effect here it is in the current also it is
coming here and that makes this characteristic is also going up and down and making
this voltage it is remaining on this load line; however, it is going from this point to this
point. As a result the corresponding output corresponding effect it is coming like to the
output in the amplified form.
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So, if I say that this is the; this is the cause if I say this is the cause or input may be signal
input called say vin and the corresponding variation here whatever we are getting here it
is the vout. So, based on as I said that based on this slope and based on this slope we can
say that signal it is getting amplified. So, you may say that it looks like there are two
mirrors say this mirror it takes this signal converts the voltage signal in the form of
current. So, depending on the slope of this line you can see that for a given variation here
it is having good amplification.
And then this variation it is coming to this y-axis and then load line it is working as
another mirror working in opposite direction namely converting current into voltage. So,
if the slope of this mirror it is very stiff compared to the this mirror then we will be
getting the amplification. So, intuitively you can see that this I-V characteristic which is
of course, it is exponential which is having very sharp you know slope and on the other
hand this line slope of course it is decided by .
So, relative slope of these two so called mirrors they are providing a gain. So, if I say
that slope of this line it is gm called transconductance of the circuit why is it called
transconductance. Of course, it is current to voltage to current relationship. So, that is
why it is conductance and also it is relating input voltage to output current or collector
terminal current that is why it is called trans conductance and then if I consider the slope
here it is .
So, if I combine this slope here and this gm together and of course, it is bringing back
this the current to voltage so. In fact, if I take reciprocal of this one that gives us the
overall gain, namely this divided by vin. So, is this gm divided by slope of that line
or this Rc it is directly coming here. So, you can say that this is gm × Rc. So, instead of
writing like this we can directly write gm × Rc.
So, that gives you some idea that how this circuit can be utilized as an amplifier. So, we
are getting a notion of amplifier. So, instead of changing this voltage slowly, if we vary
rapidly probably we can find nice amplification.
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So, let us see so we do have; we do have the same circuit here. So, instead of giving the
DC signal we may call this is Vin and whatever the things we are observing here we call
it is Vout. And as we have discussed in the previous slide, so if I vary this input over a
wide range.
So, if I vary this input over a wide range, what we have seen is that Ic it is changing with
respect to Vin and this change it is coming to the output port. So, Ic versus VCE which is
of course incidentally that is Vout. So, this characteristic this characteristic curve it is after
multiplying with beta it is getting as output characteristic like this.
So, for different input, so for different input if I consider the corresponding output of
course let me draw the load line. So this load line of course, this is slope it is with a ‒
sign this point is Vcc. And what we said it is so for we are talking about input if we
change over a small range, then we have say we have say that the corresponding the pull-
down characteristic also getting shifted up or may be shifted down and so and so.
But then if I vary it if the if I vary this input over a wider range, say for example if I take
this variation even a smaller value. So, the corresponding output characteristic it will be
like this. So, the corresponding voltage here output voltage may get stuck at Vcc
particularly. If the Vin is less than this point you may call this is whatever cutting voltage
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or VBE(on) and if the input voltage is less than that of course, the output is a remaining
there.
On the other hand if the output is going beyond certain level. So, it may be going very
high here and the corresponding pull-up characteristic it may be like this, corresponding
to say this point and that may be making the transistor entering into the saturation region
and the corresponding output it will be almost to remaining close to 0.
So, if I vary this input over a wider range and then if I observe the corresponding output
here. So, this is corresponding to the middle one this is corresponding to this point and
this is corresponding to say this point and so and so. Then what whatever the behavior
we observe namely let me use this space, Vin to Vout characteristic that we get something
like this.
So, till Vin is VBE(on) the corresponding output it is stuck at Vcc and then it goes down
fairly in linear way or rather whatever the characteristic we do have here. And then again
once the device it is entering into the saturation region, output remain close to ground
like this. So, this point is corresponding to this point, on the other hand once you exceed
say beyond some point here we are going to this point.
So, you may say that in the middle range; middle range is the behavior input to output
transfer characteristic behavior it is quote and unquote linear. On the other hand if you
are going here due to this part the input output transfer characteristic it is getting
saturated on the other hand due to the other side due to this part is getting saturated. So,
this non-linear behavior it is coming from the trans characteristic non-linear part and this
non-linear part it is coming due to the output port characteristic and on the other hand in
the middle we are getting fairly good linear part.
So, whenever we are considering say this circuit as an amplifier. What we like to do here
it is we like to keep the device in this middle portion preferably with respect to a middle
point here. And then input will be varying with respect to that and we should rather avoid
this part and this part where the signal it is getting clipped.
There may be different application specific application where we may push this device
into this two non-linear part. But unless otherwise it is stated for analog circuit we prefer
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to keep the circuit here and how do you do that we make sure that Vin it is beyond VBE
and also the VCE it is such that the device it is not entering into the saturation region.
Where you may be you may recall that one important thing is that, in this portion the
device in if the device is entering into a region where the input to output transfer
characteristic it is getting saturated. So, in other words you may say that if I want to use
this circuit as an amplifier, it is corresponding output is getting saturated that is why this
portion this portion. If the VCE is less than some value called VCE(sat), if it is less than that
we call it is the device it is in saturation region.
So, now at least we are moving to a direction that we will be keeping the device at some
stable point called Q-point or operating point. In other words we like to keep the device
somewhere here called whatever it is Q-point. So, you may say that the corresponding
pull-down characteristic it is basically this one and then with respect to that we like to
vary the input plus or minus with respect to the Q-point. And as a result we will be
seeing the corresponding intersection point of the pull-down characteristic and the load
line it is going up and down, which is making the corresponding output here.
So, in other words you may say that instead of a considering this signal as DC, we may
say that it is having some sinusoidal part and then also it is having a DC part. And this
Vin we may say that small signal part or the signal part we denote by vin. And on the
other hand the large signal part or the DC part which is defining the operating point by
say VBE or whatever VIN. Let me write here VIN.
So, you may say that this Vin it consists of this part small signal part as well as the DC
part and the DC part should be such that this operating point should be in the middle
preferably in the middle of the suitable range of the input to output transfer characteristic
and then we apply the signal with respect to that.
And likewise at the output whatever the voltage we will be observing, corresponding to
this DC it may be having a DC part called VOUT and then it is also having influence of
the small signal and the corresponding influence or effect we call small vout. So, we will
say that this is the small signal part.
So, this input to this output of course we are expecting gain and again what did we say
that the slope of this mirror or this trans characteristic to the load line slope or whatever
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you say this mirror, they are defining the gain of this to . So, end of it what you
are getting is so we are having this is vout and this part it is vin and is essentially slope
of this line which is gm divided by slope of this line which is . And so it is coming Rc of
course it is having a ‒ sign so that makes the ‒ sign here.
So, you may say that the circuit gain it is ‒ gm × Rc and as I said that we do have a notion
something called amplification. So, this circuit it is providing a good gain and we call
this circuit it is common emitter, that is because the signal we are applying here at the
base and we are observing the output at the collector and the emitter it is connected to
either DC voltage or in this case it is ground.
So, we may say that for the signal emitter it is also working as a reference terminal and
that is why you call it is common emitter amplifier. Note that emitter need not be
connected to ground, as long as it is this emitter it is connected to a constant DC voltage
then also we call it is common emitter amplifier. So, there will be different other
configurations, but before we go into that let me we summarize whatever we have
discussed here.
Ah so let me rather use different slide here. So, at the input; at the input as I said that we
do have a DC part and then we do have a small signal part together. And it is creating an
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effect here which is having a again the corresponding DC part and then it is having a
small signal part.
And from the input to output transfer characteristic what we said is. So, this is Vout and
x-axis is Vin and as I said that it is having fairly non-linear part initially and then it is
having a linear part and then it is getting saturated like this. And at the input at the input
whatever we are saying that VIN is basically capital VIN, that gives us VOUT.
And with respect to that we do have if we apply some input. So, with respect to that we
are applying input here. So, that is vin and the corresponding effect we are getting here it
is variation of the Vout and we call this is vout.
Now, so you may say that for every time this is our reference point. So, if I change this
Vin over this range and to find the corresponding solution, either we can use this non-
linear characteristic curve every time. Or the better option is that since we are interested
of the small signal to this small signal output. Probably it is better to consider only this
segment this segment of the characteristic curve and we can confine our discussion with
respect to that.
Namely let you consider now this is vin to vout and this whole characteristic now it is
getting shifted to the origin. So, you may say that the characteristic it is only this part.
So, this point it is coinciding with this origin and this segment of the transfer
characteristic curve it is here.
So, every time if we ensure that this operating point is not changing, that means this
point is not changing and then if you have any signal here ensuring that this Q-point is
not changing. Then this characteristic curve it is sufficient and slope of course slope of
this characteristic curve as you said that this will be gm × Rc with of course, a ‒ sign.
So, that is the slope of this characteristic curve and so from that we can find what will be
the input output relationship. Of course, if you go beyond this one then there will be non-
linear part which we are not interested in.
Since we are suppose if we ensure this Q-point always aligned with this origin of this vin
to vout transfer characteristic, and then we may say that the analysis of the circuit it will
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be much simpler. Which means that if we draw the corresponding equivalent circuit, so
instead of.
So, if you see the device large signal wise we do have this model of the BJT. So, this is
the base terminal and then this is the emitter terminal and this is the collector terminal.
So, this circuit of course, we do have Rc connected here and this model it may be
simplified or linearized
So, when you may recall that this consists of one on resistance and then the cut in
voltage in this case we call this is VBE(on) and this is base to emitter resistance called rπ.
So, whenever we are shifting this Q-point to this origin, equivalently saying that we are
dropping the DC part.
That means, we are making this is ground this is also ground and we are also probably
we will be getting this also ground and not only this external DC voltage need to be
dropped. But whatever the internal DC voltage is existing within the model itself that
also need to be drawn.
So, the whole circuit now it becomes simpler like we do have rπ here. So, this part it is
getting dropped and then here we do have I may say this is remaining current control
current source. So, here now it is only the signal part we will consider. So, we use small
ic which is β times ib where ib it is the small signal current flowing here.
So, then of course we do have the Rc connected here, but then Rc it is connected to DC
voltage which is AC ground. Emitter node anyway it is connected to ground and at the
input the signal, whatever the signal we are applying here that is the input signal and the
DC part it is getting dropped out. So, we may call this is the vin and the corresponding
voltage you will be getting here it is called the small signal vout.
So, instead of using this model now we are going to use this model. So, similar to diode
here also we do have a notion called small signal equivalent circuit, which is also giving
small signal model of the whole circuit. And once we translate this into a small signal
equivalent circuit the, as I said that we are simplifying the circuit not only by just
dropping the DC part, but also making all of the DC component internal to the device or
also getting removed.
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And most important thing is that since this characteristic curve it is going through the
origin ah, that means input to output relationship it is linear and hence superposition
theorem can also be deployed once we consider this configure this simplification. Only
thing is that we have to ensure that this Q-point is not getting shifted.
So, along with the signal amplification we are also getting a notion something called
small signal equivalent circuit. So, this is referred as small signal equivalent circuit ok.
So, we will be later on we will be frequently using this model, only thing is that you need
to be of course, we have to consider this model to get the value of the DC current and to
get the gm.
Of course, these gm it is a strong function of the DC collector current So, we will be

discussing that later, but just to highlight that in our later examples those are the things
we will be discussed more.
Now, probably we can try out one numerical solution numerical examples. So, suppose
we do have a circuit likes this, let you consider this is 10 V and let you consider VBE(on) =
0.6 V and at this point we are connecting a DC source through RB. And let you say this is
5 V and let you say that this RB = maybe 440 kΩ and β = say 100.
Then and also Rc = say 2 kΩ, then can you find Vout. So, how do you proceed, first thing
is that we need to find IB by considering this RB and VBE(on) and then 5 V. So, you may
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say that IB solution wise, so IB = . So, that gives us 10 µA and then Ic = β ‧ IB. So,
that gives us 1 mA and then drop across Rc = Ic × 2 kΩ. So, that gives us a 2 V. So, the
Vout which is 10 V, Vcc ‒ 2 V that is 8 V.
Now here of course, here we have assumed the device it is in active region and since this
is 8 V and the voltage coming here it is close to 0.6. So, definitely base to collector
junction it is reverse bias and hence the device it is in active region and hence everything
is consistent. But of course, if I increase this Rc then and if this drop it is approaching
towards 10 V the device it may be entering into the saturation region.
Now, on top of this one if I say that if I feed a signal here at the base, then what may
what it may happen. So, probably today we are running short of time. So, let me consider
that example maybe next day.
So what we have covered? So, far we have analyzed non-linear circuit containing BJT
and we started with two examples where we have applied voltage at the base and then we
have observed the corresponding currents at the collector and then the corresponding
output voltage.
Then we have entered into some circuit called amplifier, where we say that the circuit is
having specific name called common emitter configuration. We also have observed that
input to output large signal characteristic of the common emitter amplifier and then
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portion of the large signal characteristic can be considered as small signal input to output
transfer characteristic.
And slope of the transfer characteristic which is we have seen that it comes from the gm
and the load Rc together to define the slope of that and that is making if it is higher than 1
that is making the circuit as an amplifier. So, we have seen that notion of signal
amplification by this common emitter amplifier and we have given a slight hint of
moving to small signal equivalent circuit and a small signal model of the BJT. So, later
on we will be discussing that part for the detail, we just gave a small example numerical
example we will be having more examples later on.
I think that is all I do have today.
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Prof. Pradip Mandal
Lecture – 16
Analysis Of Simple Non–Linear Circuit Containing a MOSFET
Start sir.
So, dear students welcome back to this Analog Electronics Circuit. Myself Pradip
Mandal from IIT Kharagpur, I am associated with E and ECE Department of the
institute. So, we are going through the second module and so, it is continuation of that
namely we are going through Analysis of non-linear simple non-linear circuit containing
BJT and MOSFET.
In the previous sub-module we have seen that the circuit containing BJT how to analyze
it and today we will be going to similar kind of analysis, but containing MOSFET, and
we will also see what will be the difference. So, let us see what the things we are
planning to cover today are.
So, first we will cover the basic circuit configuration. As I said that it will contain only
one transistor and then through two examples we will see how we can find the circuit
solution; namely, the circuit current and voltage.
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And then, further we will be going through the example and in fact, incidentally that that
example it is common source amplifier where the source is common for input and output.
And, we will be seeing that what will be the output for varying inputs and then from that
we will be giving a giving any thought towards what may be the output variation
whenever we are changing the input. So, in other words input to output transfer
characteristic of the circuit.
And then, if we change the input in a regular pattern or maybe through some signal then
you can see at the output. What kind of signal they associated signal we can get at the
output namely, if we give a signal at the input of the common source configuration. What
kind of signal we are expecting at the output namely, we are expecting amplified version
of the signal.
And then, we do have a plan to cover some numerical examples, if time permits we will
go a little detail of that otherwise, probably we can give some hint and then you can
work out those numerical problems. So, according to our overall plan of this course this
schedule let us see where we are.
So, in this module namely week-2 modules, we are going through this non-linear circuit
containing only one transistor and as I said that previously we have covered circuit
containing one BJT. And, today we will be going through similar kind of circuit
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containing MOSFET one MOSFET and the overall plan as I said that to find the input-
output transfer function and then also how the circuit can amplify a signal.
So, in other words how this circuit simple circuit containing one transistor can amplify
signal. So, this is what the plan and has said that compared to previous days. It will be
the transistor instead of BJT will be going through MOSFET and whenever it is
appropriate. We may also discuss about the difference between the circuits containing
BJT versus circuit containing MOSFET.
So, let us see the basic circuit configuration. So, here we do have the example circuit, we
called example circuit-1 and you see where we do have supply voltage. Main DC supply
voltage VDD which is giving supply to the drain of the transistor through resistor R
normally referred as load and at the gate we are applying VG.
And, we are assuming that the device it is in saturation region which is equivalent to
active region of operation of BJT; namely, in the channel if you see the drain end the
channel pinch off it is happening. And if that condition is satisfied, in other words if VDS
is more than VGS ‒ Vth then the pinch of it is happening at the drain end.
And, then the expression of the current IDS of the device can be given by this formula
where ( ) it is having important role and in this circuit this VG incidentally that
is also same as VGS. And if the device it is in saturation region then the current is having
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very weak dependency only through ( ) part which it is commonly known as
channel length modulation factor.
On the other hand depending on the aspect ratio of the device of course, it is having
good influence on the current and the remaining part particularly this part it is you
may say that is a device constant. So, we may say that this is simply a constant K.
Now, if you compare; if you compare the common emitter amplifier circuit which is
similar to on this circuit common source amplifier, it is and the circuit just for your
reference which it has been discussed previous class; I am also showing the circuit. And,
here we will try to see that once the circuit is given how you find the current here of
course, the current equation is given here and then subsequently how do you find the
drain voltage or VDS or in this circuit incidentally that is the output voltage.
So, if you compare the common emitter configuration based on the bias condition at the
base we are suggesting to analyze the base loop to find the base current. Whereas, for
this circuit since the current is not flowing of course, this model it will not work and of
course, the dependency of this IDS on VG or VGS it is different from the BJT circuit.
So, let us see what kind of equivalent circuit we should be using and how this equation it
is playing important role. In fact, this circuit as I said that we do not have any notion
called beta of the transistor as we have seen for BJT instead the VGS. VGS it is directly
controlling the drain to source voltage, and hence, this equation it will be directly used.
Whereas, for BJT what you have done is that we have analyzed this circuit, then diode
we have replaced by its simplified linear model by whatever VBE and then its equivalent
resistance and so and so to find the Ib and then we have used this β.
So, in this case; however, this part it is quite different. But of course, once you find the
IDS then finding the output voltage using the load line characteristic that is similar; that is
similar to the discussion we made for the circuit containing BJT. So, let us see what the
model we use for this circuit is.
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And here again just for your reference I am keeping the model corresponding to CE
amplifier here and of course, this is our main circuit of our consideration. So, here as I
said that this gate voltage it is forming or providing the VGS. So, this is directly coming
to the gate, but then source at the source we do have 0 voltage. So, we can say VG is
nothing, but VGS and depending on this VGS drain to source current is flowing.
So, we can say that this device it can be modeled as voltage dependent current source
and so, we do have this IDS is function of VGS and also the VDS. So, this is the drain and
this is the gate, this is the source and whatever the voltage you do have across this output
port it is actually the VDS.
So, the current flow here it is it depends on the VGS as well as VDS and we know its
expression just now we are talking about it is . K is the trans conductance parameter
coming from the device multiplied by aspect ratio of the channel multiplied by (
) ( ), assuming that this condition is getting satisfied namely the device it is
in saturation.
So, once we get this the current definitely then we can see what may be the
corresponding voltage here. By considering the, this part and this part together namely
their characteristic, we can combine to find the output voltage as you have done for the
BJT similar kind of approach we will be following.
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So, once the circuit is given to us namely not only this voltages are given we are also
assuming that the corresponding device parameter namely, Vth then K and then maybe
the λ all are given. And here of course, in this module simplified module we have
assumed that this λn is very very small namely, you may say that approximately 0.
So, this factor dependency of this current on VDS you can say practically 0. So, that is the
assumption. Later on we will see that this approximation may be important only for DC,
but once you go for ac signal this may be very vital we may have to consider that part.
So, to find the operating point or to find the solutions point for given condition what are
the steps we need to follow. So, let see what are the steps we need to follow in the next
slide?
So, here we have written that this is the; this is the equivalent circuit. So, this is the at
this point we do have the VDS and we also assume that this part it is very small. So, we
do have only this current which is function of VGS alone and so, the first step it is we
need to find the IDS and then next one it is we can find the drop across this resistor while
this current is flowing through this resistor.
So, we can say that applying KCL here at the drain node the same IDS current is flowing
through this resistor creating a drop across this resistor called say VR which is having this
side + and this is ‒. So, second step it is; so, it is basically IDS × R it is giving us the drop
across this resistance.
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Now to find this VDS this is (VDD ‒ this drop). So, that is the third step and, following
this one we can find the circuit solution namely the current and the corresponding
voltage here. It is in fact, this procedure or from this whatever the steps we seen it is it
can be viewed as more generalized approach and graphically it will be very interesting to
see though actual circuit numerical solution we may be following this one.
But, many a times graphical representation may help you to understand whether the
circuit will be providing meaningful performance; namely, gain or whether it is gain is
sufficient, and under what condition the signal swing it will good or the signal will not be
facing much distortion. So, to appreciate all these qualitative things it is better to
understand these steps in graphical way also.
So, in the next slide what we are going to discuss is the generalized method. In fact, this
method we have discussed for the BJT circuit as well. So, let see what are the steps we
are following here, first step it is of course, we need to find the IDS. So, that is we have to
use this equation and the next thing is that we need to find this voltage we need to
combine the characteristic of the upper element and the lower element.
And as we said in the previous class that we let us call this is pull-up element pull-up
element and this one it is pull-down element; So, we do have the pull-down element.
And, if we combined say pull-up and pull-down characteristic namely, the voltage across
this one and their current need to be consistent and then we can find the solution point.
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So, pull-down element characteristic you may recall that similar to the BJT circuit. If we
plot the IDS; IDS versus VDS for a given value of VGS and as you said that lambda is very
small. So, we can say this current is practically independent of this VDS. Assuming that
the pinch of it is happening; that means, we are not entering into this triode region we are
keeping the device in the saturation region.
So, this portion it is saturation region which is equivalent active region of operation of
BJT and then the pull the pull-up characteristic; that means, the load line characteristic it
is of course, it is linear. So, if we draw the current through this resistor IR versus voltage
drops across this resistance. So, the VR is the voltage drop across this resistance and IR is
the current flow through this resistance.
And we know that if we plot this IR versus VR, this will be linear and slope of this linear
line it is with a ‒ sign and so, if we combine these two characteristic then they will be
giving us the solution. But, since the x-axis this is VR and then here we do have VDS,
they are not same, in fact VR if you see here it is nothing, but VDD; so, VDD ‒ VDS.
So, since these two axis they are not consistent even though finally, we want this IR and
IDS should be equal, but these two definitely we do not want equal, because rather it will
be VR should be VDS. So, since we cannot directly combine these two characteristic we
need to change this characteristic, what we call it is we rearrange this pull-up
characteristic and then we do the superposition.
So, similar to the BJT circuit what you do, first we flip this characteristic namely we plot
the IR versus ‒ VR characteristic which is equal to VDS ‒ VDD. So, that gives us the
characteristic of the resistor it is going to the second coordinate.
This slope sorry, this will not be ‒ this will be +, here the slope here it will be , and
then this axis of course, it is having VDS with + sign here, but still we do have the ‒ VDD
part. So, to get rid of this one what we do we further rearrange this characteristic namely
we plot IR versus; IR versus VDD ‒ VR. So, that is of course, it becomes equal to VDS.
So, now of course, if you plot this characteristic this characteristic it is getting shifted by
VDD amount to the right and so, this is getting shifted here. So, the origin it is getting or
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rather at this point of the characteristic curve touching the origin is getting shifted here to
VDD and the slope here of course, it remains .
So, considering this point and this slope what we are getting here it is that yourself
can find it, and now this IR to satisfy KCL at this point IR need to be equal to IDS and this
axis of course, it is VDS. So, now we can superimpose the two characteristic curve. So,
this is the characteristic of the load line and its slope it is . So, wherever and also this
point is VDD and wherever they are intersecting we call the solution point or the
operating point.
Now, so this procedure as I said it is very similar to the circuit containing BJT. If you see
so far, we are talking about the circuit containing a MOSFET, but this MOSFET is a
special kind of MOSFET or rather I should say it is n-type. In case if you are finding a
circuit containing PMOS transistor then of course, the situation you need to adjust
yourself; so, that whatever the technique we have we are following here that can be
deployed.
So, let us see an example having PMOS transistor sorry, before you go to PMOS, I sorry
I do have another case to discuss in comparison with BJT. What is this one is in case we
are having input voltage and then if it is having a resistance in series with that. So, let we
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call this is say R1 and then so, this is same as whatever VG and whatever the analysis in
this case can we deploy or how do we find in this the IDS and the VDS for this circuit.
In fact, if you see here since gate DC wise gate through the gate the current is 0 so, we
can say IG is practically 0, even though we do have this resistance the drop across this
resistance is 0. So, we can say that whatever the voltage you are applying Vin it is
directly coming to the gate and if you see the if we draw the equivalent circuit of the
transistor. What will be finding is that this resistor practically is not having any effect to
the operating point.
So, whatever the voltages you are applying here even though we are applying through
this resistor see R1 so, and let you call this is whatever I say Vin and since this current is
0. So, since IG = 0 at least DC wise that is valid. So, the drop across this resistance is VR1
= 0.
So, we can see that the voltage from the drain sorry, gate to source of this device namely
this VGS; VGS equals to same as this Vin. So, as a result; as a result whatever the whatever
the IDS equation we are using we can directly use that IDS = ( ) ( )
VGS = Vin, and all these things, but anyway we have considered this part is approximately
1. So, whatever the equation we do have here, it is essentially saying that this resistor is
not having any role to play.
However, if we are considering a signal you are applying here the gate to source there
will be capacitance. So, then for signal of course, this resistor it will be having some role
to play. So, that we will discuss later, but for the time being at least you can say that if
you are having a resistor here the DC condition wise it is not having any influence.
In fact, this is a contrasting difference compared to the compared to the BJT circuit
where if you put a resistor and then if you put say Vin to bias the base of the BJT, then
we know that then the current flow; current flow through this circuit it will be affected
by this resistance. And so, this Vin even though we are applying Vin here the VB it will
not be same as the Vin because there will be a finite drop across this resistance. So, this
drop it will be non-zero.
So, that is one important difference of the while you will be analyzing the circuit
containing MOSFET and circuit containing BJT and of course, later part it is this part it
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will be same further two cases. And let us see as I was giving a hint that so far we are
discussing about the circuit containing n-MOSFET, n-type MOSFET or rather n-channel
MOSFET in case if you are experiencing a circuit which is having p-MOSFET then what
do you do.
So, here we do have an example. So, in this case this is the transistor of our consideration
its source is connected to VDD. In fact, need not to call VDD it is connected to source, but
whatever the name you are giving it does not matter as long as this is at high potential at
least compared to the gate and creating a voltage drop here sufficiently high. So, that the
device it is on that is good enough.
Just for our consistency, we are naming this one VDD. So, you may you may not be
sidetracked by that, but after that once you apply the voltage at the gate by the other
source then how do you find the corresponding current through this device. Now, if you
replace this device by its corresponding model here, what we have it is the; so, this is the
source in this case, this is the source, this is the gate and this is the drain and we are
expecting the current it will be the actual current it will be flowing from source to drain.
So, we may call this is ISD and we are expecting that VSG should be higher than threshold
voltage of the transistor magnitude of the threshold voltage, and also at the drain end to
have the pinch of happening we need to satisfy VSD should be higher than VSG ‒ Vth.
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So, once we satisfy this condition then the expression of this current is given by
( | |) ( ). Again just for simplicity, we may consider this is
approximately 0, but the rest of the things it is very similar to whatever we have
discussed. Only difference is that the source is connected to the supply VDD, gate is
connected to at lower potential and then of course, drain it is preferably.
In fact, it is lower than the sword voltage and preferably this drain voltage should be
such that the pinch of it is happening namely, the channel is not appearing. In other
words the drain voltage should not be higher than gate voltage by a margin of magnitude
of the threshold voltage. So, that is the condition we are writing here.
And once it is done once this condition is getting satisfied then you can see what the VSG
is namely, VDD ‒ VG in this case this is VDD ‒ VG so, that is the VSG. So, we can say in
this case this is VDD ‒ VG and so, that voltage we can plug in here and then you can find
this current, and this current is of course, it is flowing from source to drain; this current is
also flowing through the resistor or load.
So, we can you may call this is IR which is equal to ISD and that is producing a drop
across this resistor called VR, and then this VR incidentally this is same as the output
voltage. So, you may say that Vout is same as VR = VDD ‒ VSD. So, of course, if you see
the circuit, it will be relatively straightforward to follow, but then there will be a
difference of whatever the generalized methodology we have discussed. So, let us see
what kind of changes it will be there in that generalized methodology or whatever we see
graphical interpretation of the steps.
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So, let us try to see what kind of things we have to do here, first of all again we may call
this element and this element they are trying to adjust themselves to converge to a point
where this Vout. It is consistent for the upper element as well as consistent for lower
element and this Vout of course, and this VDD ‒ Vout that is nothing, but the VSD.
So, since the device it is in saturation region you may say that this current again it is
primarily defined by VSG and this part it is approximately one, but then the main the
change here it is now we will be calling this is as pull-up and this element as a pull-down
element. So, this is the pull-down element.
So, then while will be rearranging the characteristic which one do we rearrange.
Interestingly, Vout is this one; so, first thing is that let us draw the pull-down
characteristic first. So, we do have the pull-down characteristic namely IR versus Vout and
incidentally that is the drain voltage and we know that this is a linear element. So, we
draw this one.
Now, if you consider the pull-up element on the other hand. So, we know that pull-up
element is basically ISD versus VSD, and the VSD what we said it is VDD ‒ Vout. So, this is
equal to VDD ‒ Vout. Now, again this Vout and this Vout they are same, but then this axis
and this axis they are not consistent. And of course, they are the characteristic this is the
pull-up characteristic, if I ignore λ part it will it supposed to be quote and unquote
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independent of the VDS or VSD, but then this axis we want this should be equal, but then
the x-axis parameter they are not same.
So, what you have to do we have to rearrange what we said we need to rearrange this
pull-up characteristic incidentally now this is non-linear in nature. So, it is bit tricky. So,
first thing is that we need to flip it. So, let we flip and let the characteristic is going to the
second quadrant and the characteristic it becomes like this, it is going to the second
coordinate. So, this is ISD versus ‒ VSD or whatever you say VDS, but then this is equal to
Vout ‒ VDD.
So, again we do have Vout, but still we do have ‒ VDD. So, to adjust that what you have to
do we have to shift this characteristic towards the right by an amount of VDD. So, if you
do that then the characteristic it is getting shifted. So, now, ISD versus VDD ‒ VSD. So,
that is of course, this is equal to Vout and since we are adding this VDD part. So, this
characteristic curve it is getting shifted to right by an amount of VDD. So, you may say
that this is the VDD part VDD point; so, Vout is equal to VDD here.
So, what are the things we have done is that we have flipped it and then we have shifted
right and now this took axis this axis and this axis they are same. So, now, I can overlay
this characteristic on the pull-down element namely the characteristic it becomes like
this. So, we do have the VDD here and wherever they are intersecting we call this is the
operating point.
So, that is I think the method it is remaining same only thing is that you need to be
comfortable to rearrange this pull-up characteristic even though it is not linear and
incidentally the pull-down characteristic it is linear. In general, so, you should be
comfortable even if say both the elements pull-up and pull-down elements they are non-
linear in nature. So, let me take a short break and then we will come back to the
subsequent point.
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Prof. Pradip Mandal
Lecture – 17
Analysis of simple non - linear circuits containing a MOSFET (Contd.)
Students welcome back to the topic of Analysis of non-linear circuit containing

MOSFET after the short break. So, we are discussing about what will be the generalized
method whether the signal or the input is applied to the NMOS or PMOS. And, we are
discussing about the situation when the circuit contains the PMOS and the on the other
hand the load as you can see here it is PMOS, and the load it is connected to ground and
so and so.
Now, let us see some numerical not numerical different situation, if the voltage it is
changing at the gate and then what happens. So, for a given value of the gate voltage and
the parameters of the device we understand that how to find the solution. And in case, if
the voltage it is changing then what happens to the solution point. In fact, this is similar
to whatever we have discussed with the circuit containing BJT.
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So, let us do the similar kind of exercise and we will see whenever the differences are
there we will be highlighting that. So, this is the circuit of our consideration that we do
have the N-type MOSFET, the signal or the input you are applying at the gate. The
source node it is connected to ground and drain it is connected to the, towards the +ve
supply through this resistance call RD.
And at the input, so, let you consider different situation. In case this input voltage we
vary with time, then what happens to the output voltage. So, as we have discussed so for
a given value of Vin what we can do, we can draw the I-V characteristic or the device or
you can say that output port I-V characteristic.
And so, this is IDS versus VDS and this is of course, for a given value of Vin calls a Vin is
equal to Vin1 and the load line it is given by this straight line. So, one point here it is VDS
= VDD. So, that point it is referred as VDD and 0 current and on the other hand this point it
is currently it is so, voltage it is 0, but then the current is . So, that is the RD here.
So, the slope of course is with a ‒ sign and what we said is that wherever they are
intersecting that gives us the solution point. So, wherever they are intersecting that gives
us the VDS solution or you may say that the corresponding Vout.
So, now for a given Vin, say Vin1 how do you find the current? So, then we need to
consider the input to output characteristic namely IDS versus VGS or in this case VGS it is
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same as Vin. So, you may say that this is VGS which is equal to Vin and we know that this
is square law namely. So, this equation it is you know what we say that ( ) .
So, I consider only this part, I am ignoring this ( ) part. So, for a given value of
Vin say this one Vin, we do have this current. So, that current is basically defining this
level and then the load line wherever this load line is intersecting this current that gives
us the corresponding out. So, you may say that starting from this point called Vin1 that
gives us IDS1. And, then this IDS1 it is getting reflected here and then the corresponding
output here it is out1.
So, now if I vary this voltage, say if I increase this voltage to some other value say Vin,
Vin2; so, this is Vin2. So, that gives us different current say maybe at a higher value like
this. So, this level of this current it is IDS2 and wherever they are intersecting that gives us
the output voltage namely the VDS. So, that is the Vout2.
So, likewise of course, here you can see that the device it is almost entering into the
triode region and beyond that if you do then of course, there will be heavy non-linear
part, we will be discussing that shown. So likewise if I; on the other hand if we decrease
this Vin to a smaller value namely Vin3.
So, then the corresponding current here it is IDS3 and then this IDS3 it is producing. So,
IDS3 it is producing another current level here and the corresponding characteristic curve
may be somewhere here. So, this is IDS3 and wherever they are intersecting that gives us
the other Vout called Vout3.
So, as you can see that if VGS is higher than threshold voltage Vth, then we can see that
this characteristic it is going up or down and, making this intersection point of the device
characteristic with the load line going up and down, but then along this load line and
making the variation of the corresponding output. So, for different values of Vin if I
observe the corresponding Vout what we can get it is input versus rather input to output
So, we may say that x-axis is Vin and then y-axis is the corresponding output and
whenever the Vin it is higher than Vth, then the current starts flowing, the voltage it will
be maybe close to VDD, but of course, it starts dropping. But before that so, here so, this
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is Vth and beyond this point the voltage starts deviating from the VDD level. And, if the
Vin is less than Vth current is 0 here and then the output it is of course, VDD.
So, as we are increasing this Vin beyond Vth this non-linear characteristic curve it is
basically some extent it makes it non-linear, but then this part you can say fairly linear.
And, then if you increase this Vin beyond some point then of course, the device it will be
it may be entering into the triode region and incidentally this crossing point it may be
close to 0, but it will not be going to 0. So, you can see that beyond some point this part
it will be entered into the non-linear side.
So, here the you may say that this portion this non-linear portion it is due to this part and
on the other hand this non-linear part of the characteristic curve it is due to the device
entering into the triode region. And, in between in between you can get a nice portion of
the characteristic curve namely this portion. Let me use a different color for this part.
So, this portion it is a very good part. Namely, if I change the input here then the
corresponding current variation here you can say that it is fairly linear with that voltage
and here of course, the load line is linear. So, that makes the input to output, input to
output relationship it is fairly linear.
Now, this slope of this line namely that gives us the gain; that means, if I vary this
input by some amount how much the corresponding effect will be observing at the output
that gives us the gain. And, as we have discussed for BJT circuit here this gain it is it
primarily depends on the slope of this line. So, you can think of it as a mirror.
Suppose, if we are changing the input voltage with respect to a point say Vin1 here in this
case, then if you vary this input centering this Vin1. Then based on the slope of this line,
you can get the corresponding current change and that current change is coming here and
then that current change again getting reflected by the load line to the voltage axis.
So, you may say that voltage to current variation and then current to voltage variation.
So, here the slope of this line, it is basically the . And, this is basically defines the
transconductance of the device denoted by gm transconductance.
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On the other hand this slope of course, it is the slope it is . So, these slope when we
say it is basically voltage to current slope is this one, in other words current to voltage
slope or current to voltage transformation it is basically RD. So, if I consider slope of this
line and then inverse slope of this line that gives us the voltage gain here.
So, the gain here it becomes actually gm × RD with of course a ‒ sign. So, how do you
find the gm? So, that we will see later, but just to give you a hint that if I consider say this
I-V characteristic. And, if I take , I can find what will be the corresponding gm.
So, if you if you use this equation you can find the expression of gm = ( ).
So, if you multiply this gm by this RD that will be giving you the gain of the circuit. So, in
other words if I see that at the input instead of giving varying input, if I consider a signal
riding on a DC then at the output we can get signal riding on a DC.
So, let me further instead of a complicating this slide further it is already becomes
clumsy. So, let us go to the next slide and start with a fresh look into the circuit.
So, what we like to say that; so, we already have discussed the input to output transfer
characteristics. So, this is the input and if we vary this one what kind of output we
obtain. So, I will not be further repeating that detail, but you may recall that we got input
to output transfer characteristic is like this. So, this is Vin and this is Vout.
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And, then if you consider that input we are changing with respect to a DC voltage
nothing, but say VIN and then if we vary with respect to that by some small amount, it
may be called vin. And, the corresponding effect, what we get at the output is when you
have a DC level here called VOUT. And, the corresponding signal we may get with
respect to that DC level depending on how much the variation we are giving here and
that may be called vout.
So, if you are applying input here at the input at the gate or gate to source some signal
here. The corresponding effect we are getting at the drain which is in fact, it goes down
and so, it goes down first and then it goes up like this. So, yeah; so, this input to output
relationship it can be say that, that is the gain. So, we may think of that this circuit it can
amplify the signal and yeah so, this is what we mean, sorry instead of going to the
amplifier gain I have framed one numerical problem to find the operating point and so
and so.
So, let us solve this one first and then we will be going to the notion of gain. So, the next
numerical example associated with this circuit is given here.
So, let me give some important parameter here to solve the numerical problem; say, say
we do have Vdd let me use a different color. So, say Vdd is given to us say 10 V, the
device parameter say K is say maybe 2 mA/V2, then Vth of the transistor it is a 2 V and
maybe λ we can approximate to be 0 to simplify.
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And now, let us see the Vin, this Vin if it is say 3 V and I need the other information
particularly RD also. So, let you consider this is 4 K, then with this condition Vin can you
find what will be the Vout. So, we need to find the corresponding value of the Vout. So,
how do you proceed?
To start with we assume the device it is in saturation and later on of course, we have to
verify it; otherwise, we have to use triode region equation. So, if I assume the device it is
in saturation. So, directly then we can write IDS; IDS = × VGS that is actually
( ) and, ok; I need this information as well.
So, for the time being let you consider W it is say 20 µ and L is say 2 µ. So, with that
what you are getting here it is K = 2 m, 10‒3 and by 2; W is 20, L is 2; Vin is 3, ‒ Vth and
square. So, what we are getting here it is 10 mA? Now, if you see if 10 mA it is flowing
through 4 K then of course, the drop here it is expected to be a 40 V then of course, then
this is not valid, ok.
So, now let we change the value of this resistance. So, this will not work out. So, let you
consider this is 0.5, 0.5 K, then what will be the situation. So, if I again if I start with this
assumption the device it is in saturation region and then the currents should be 10 mA.
So, the voltage drop across this R with 0.5 K, it will be 5 V, yeah; so, 5 V and we do
have 10 V here. So, we do have 10 V here. So, the voltage coming here it is 5 V, voltage
here it is 3 V.
So now, if you consider the gate and the drain voltage; drain it is higher than the gate
voltage itself; that means, the pinch of it is happening; so, then this equation is valid.
And hence, you may say that the voltage here Vout it will be 5 V. But of course, with 4 K
the device it will not be really in saturation region. In fact, you may recall that we are
talking about input to output transfer characteristic curve, it was like this.
So, the Vin, in this case Vin and combination of this resistance if it is say 4 K what we are
doing here it is the device it enters into the triode region so; that means, the device it was
actually in this region dip into this triode region. So, as a result the pinch of it was not
happening. This drain voltage it is very close to ground and then in that case you may
say that if this voltage it is close to ground. The current flow on the other hand it is
approximately 10 V minus close to ground divided by whatever 4 K.
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And in that case the IR is approximately 10 V minus whatever the VDS, it is
approximately. So, let me write this is equal. So, and this can be well
approximated by . So, that gives us 2.5 mA. So in fact, this is quite different from the
required current in the saturation region.
So, if you try to correlate the graphical interpretation of the input to output situation. So,
the device; in fact, let me let me draw the load line first. So, the load line it is based on
the value of the R we are getting it low. And whatever the 3 mA of current sorry, 3
voltage 3 V of the gate voltage the device actually already enters into deep triode region
like this. So, even though this current it is expected to be 10 mA, but actual current since
it is deep triode region that is much lowered here.
So, on the other hand if you decrease and the value of the resistance; in fact, that makes
this line the load line more stiffer and that makes this corresponding operating point it is
bringing the device into the saturation region. So, which indicates that the combination
of the input voltage, then the device characteristic along with W and L. And, the value of
the registrants supply voltage should be such that that device may be in the, it may
sometimes it may be in saturation region, sometimes it may be in triode region.
So, anyway so, it is not necessarily true that the device it will be nicely in saturation
region by default. So, we have to in fact, verify it. Now, let me consider if the input
voltage it is changing with time then what happens.
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So, in other words if I say that input it is varying, but instead of giving just variation with
time slowly. If we are having a situation where the we do have a DC voltage at the input
or at the gate on top of that if we are giving a signal. So, you may say that this is Vin, VIN
here and the blue part the signal part it is vin and at the output corresponding to this DC
voltage we may be getting one DC part. So, this DC part we may call VOUT and then on
top of that we may be having the small signal or the signal out.
Now, whenever we are talking about say these two basically they are representing the
DC part. And, if you are observing the signal here and signal here what we said through
the input to output transfer characteristic. So, we said suppose input to output transfer
characteristic is like this and so, this is Vin which is having DC as well as the small signal
part. And here, we do have the Vout which is also having DC as well as the small signal
part. And, let me assume that the Vin it is such that it is making the center point almost at
the middle of the linear part. So, the Vout part it may be nicely coming there.
So, this is the VOUT and this is the VIN and then here we are changing this VIN with
respect to time. So, if I say this is the time axis with respect to time, this VIN we are
changing up and down. So, at the output what we are expecting is so, at the output we are
expecting that this will be going down and then up, down and up with respect to time.
So, you may say that this is the small signal input the corresponding effect it is coming
here, here. And, as I said that the small signal input to a small signal output that gives us
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another transfer characteristic. Or in fact, you may say that this part rather this part of the
transfer characteristic, if we nicely shape to another graphical representation where x-
axis is representing only the small signal part.
And, likewise if the y-axis it is representing small signal output part and then the transfer
characteristic curve; input to output transfer characteristic curve it is such that it is going
through the origin. Beyond this of course, maybe it is having some significant non-linear
part, but as long as it is linear around and the Q-point the operating point maybe we are
happy.
So, this transfer characteristic curve it is referred as small signal. So, small signal input
to output transfer characteristic curve. On the other hand this is referred as large signal
input to output transfer characteristic curve.
In fact, if you see here this large signal input output transfer characteristic curve it is
having the capability to represent the small signal input to output behavior. But, many a
times we prefer to use this one assuming this operating point is not changing to simplify
the analysis to simplify the circuit behavior and so and so.
So, if you see here the equivalent situation. So, here the DC part if you drop which
means that this DC voltage we are making it is AC ground, even this part also we are
making it ground and that makes the equivalent circuit which is which is referred as the
small signal equivalent circuit.
So, if you see the equivalent circuit for small signal situation, you may say that at the
gate we are applying only the small signal part; namely, the vin part. And at the; so, this
VGS now, we will be calling this is small signal vgs. The current here on the other hand
whatever we call it is ids, now it is a ids; so, that is equal to it is just gm × vgs. So, which
means that this gm it is basically slope of the Vgs to Ids characteristic curve and that slope
it is basically the important parameter to represent this ids in terms of the vgs part.
So, if you see the circuit here, it is just if I assume that this part it is remaining constant,
then you may say that this relationship it is just linear one. And interestingly of course,
rest of the thing it will be linear the particularly the load part which is RD and this is
connected to you may say AC ground it is not DC ground, but it is connected to AC
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ground. Source node anyway it is connected to actual ground and then whatever the
voltage it is getting developed here it is small signal vout.
So, if I analyze this circuit, simple simplified circuit where the voltage dependent current
source it is represented by this one; so, which means ids = gm × vgs. So, that gives us the
output signal here, which is vout equals to this current is flowing through this resistance.
So, that makes gm; ‒ gm × RD × vgs, ok.
Let me rewrite this part it is getting clumsy. So, what we are saying that if I analyze this
circuit, we can get vout = RD × ids, but the current is flowing out of this node and the other
side it is connected to ground. So, which means, that I need to put the minus sign here.
Because, the drop across this one it is having plus here and then sorry, minus here and
then plus here and this side it is connected to ground. So, the voltage here it is ‒ RD × ids.
In fact, ids expression of the ids it is gm × vgs. And incidentally vgs it is vgs it is same as vin
so, we may say that then vout it is. So, you can say that vout = ‒ RD × gm × vin. So, that
gives us the gain of the circuit namely, = ‒ RD × gm.
So, what is this gm? So, at least we understand that the gain of the circuit namely voltage
gain defined by = ‒ gm × RD. So, let me wipe out this slide and discuss with neat
notation.
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So, what we said is that we are applying a signal here and then we do have a DC voltage
and then at the output you are observing the corresponding effect. We do have a DC
current IDS, in addition to that we do have small signal current ids. This ids part it is due to
small signal vin and the red part it is VIN. So, while these two currents are flowing
through this resistor.
So, both ids and IDS; so, this is IDS they are flowing through this resistance. So, that makes
the drop across this RD is VRD + vRD. In fact, if you see here this VRD part; this VRD part
it is RD × IDS and the signal part it is on the other hand it is RD × ids.
And this part, what we said is the DC part of the VOUT rather I should not say exactly DC
part, this gives the DC part in fact, I should say the (Vdd ‒ this part is the VOUT part). So,
I should say I should not be directly writing like this. We say that this gives us VOUT; so,
we can say that VOUT = Vdd ‒ this RD × IDS; whereas, this part this part it gives us vout = ‒
RD × ids.
Note that for signal we consider this is AC ground; so, for signal we do not have this Vdd
part there. And, it can be shown that as I say that this ids; so, I V part if you see in terms
of Vgs. So, if you if you consider the I-V characteristic; namely, Ids containing both DC
part as well as the small signal part versus Vgs containing both DC part as well as the
small signal part.
And, the characteristic equation it is let me uses this color like this and if I say that Vgs or
Vin part it is a remaining in the almost constant. So, you may say that this is VIN and then
that gives us the corresponding current here IDS. And, with respect to this VIN whenever
we change this Vgs so, may say that with respect to this operating point called operating
point.
If we vary then whatever the change we are applying here let you call vin and the
corresponding effect is coming there to the IDS, we call this current it is ids. So, from here
you may say that is nothing, but the slope of this characteristic curve or this = .
In fact, that is what we are defining as gm and this gm if you take the . As we have
just now we have seen that this gm = ( ). In fact, we may have different
expression; so, the gm is at least this is one nice form of the gm.
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So, let us consider one numerical example and try to see what may be the gain. First we
will we will find the operating point and then we will find the slope. By the way, the
slope of this line of course, it depends on wherever we are considering namely if the
center point it is somewhere here, the slope it will be less, if we consider above here
probably the slope it will be more and so and so. So, based on the DC voltage or the DC
operating point slope may vary, right.
So, first thing is that we need to find the operating point then surrounding that operating
point we need to find the corresponding slope. So, as I said that let me try to make an
attempt to find gain of a circuit, simple circuit how do I start, yeah.
So, this is a 10 V and let you consider that we are, yeah. So, if you have 10 V here and
then we are applying a signal here maybe this is a 3 V as we have just now consider
finding the operating for the DC condition. So, let it be 3 V and let you consider
everything together if I consider this is a maybe 2 mA/V2 and Vth. Let you considered 2
V, λ we may consider approximately 0, RD let you consider 0.5 k otherwise the device,
no we can consider.
In fact, we may consider RD equals to say may be 4 K. Note that we have considered
along with this K and then we are taking this parameter is equal to 2 mA. Earlier this part
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it was 2 mA and this part it was 10 that is why we are having the device entering into
triode region with RD = 4 K.
So, anyway with this we need to find what will be the corresponding gm. So, we may try
to see what will be the gm; gm is × (Vin or VGS ‒ Vth). So, what is the value here we
do have 2 m, 10‒3 and here we do have 1. So, 3 ‒ 2, 1; so, that is 2 mA/V. So, this is
basically change in current with respect to change in voltage; so, that is why its unit is
A/V.
So, the gain voltage gain is what we said it is ‒ gm × RD and the gm it is already we said
we obtained here it is 2 m and RD = 4 K. So, that gives us a gain of 8 with a ‒ sign. So,
yeah; so, that is a gain of the circuit for this operating point. In fact, if you if you of
course, you have to say that we need to verify whether the device it will be really in
saturation region or not. Probably, we can quickly verify say, if I consider the IDS, IDS the
DC current; so, that is let me use the other color, yeah.
So, IDS = ( ) . So, this is what we are having mA/V2 multiplied by this is
1. So, that gives us (1 V)2. So, let me let me ignore this part, the unit part. So, what we
are getting here it is then this is 1; so, that is basically 1 mA of current. And, once we
have this 1 mA of current flowing through this device and if it is flowing through this 4
K then drop across this 4 K it is 4 V. So, that makes this voltage = 6 V.
So, we do have 3 V here DC device and this is 6 V. So, definitely that ensures the device
it is in the saturation region. So, we have picked up appropriate value of the value of the
resistance on this voltage, in case if on the other hand if you are making say this is
something different. So, for example, if you consider this is 5 V and then the 5 V here it
will be making this corresponding current it will be very high. In fact, that will be 5 ‒ 2;
this is 3, this 9 mA. If 9 mA has to flow through this 4 K then drop across this resistance
it will be much higher than 10 V.
As a result the device it will be entering into the triode region and hence calculation of
the gm following this equation and finding this gain will not be having any meaning, ok.
So, later we will see that how to pick up the appropriate value or combination of the
voltages and all, yeah. So that is, that brings to the I think end of our main topic.
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So, what we have covered today it is we have analyzed a non-linear circuit containing
MOSFET. So, both we primarily have discussed with the examples having n-MOSFET,
but also we have considered one circuit containing P-MOSFET.
Then, we have discussed primarily the common source configuration and then also we
have seen the input to output transfer characteristic of the circuit. Then, we have seen
that this circuit it is able to amplify signal and its gain expression also we have seen. And
of course, we have covered we got some time to cover two numerical problems; one is
for finding the solution point and namely the DC operating point, other one is to find the
gain of the circuit.
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Prof. Pradip Mandal
Lecture - 18
Linearization of Non – Linear Circuit Containing BJT
Start Sir.
So, dear students welcome back to this course on Analog Electronic Circuits. Myself
Pradip Mandal from IIT Kharagpur, I am associated with the Department of E and ECE.
Today’s topic for this course is Linearization of Non-Linear Circuit Containing BJT. So,
we will be covering what are the topics let us see.
Before, I discuss about the subtopics let me see what is our position so far; as we are
mentioning that this is our main flow, from component to building blocks and so and so.
And, at present in this week we are the building blocks namely, the basic building blocks
and in this week we have covered the analysis of simple non-linear circuits. Today, we
are going to start with linearization of input or output transfer characteristic of non-linear
circuit containing transistors and this linearization it will be with respect to operating
point.
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So, then we will also see the notion of small signal equivalent circuit. Then from that we
can see that a different model of the transistors namely small signal model of transistors.
So, this is what we will be covering today considering the examples having BJT and in
the subsequent class we will be covering similar kind of things, but the circuit containing
MOSFET.
So, what are the concepts we are going to cover in today’s presentation? As I said that
we will be covering the linearization of non-linear circuit containing BJT, then the notion
of small signal equivalent circuit, particularly if you are having non-linear circuit then
how do you translate into equivalent circuit particularly the variations of the voltage and
currents are restricted, focusing the focusing the discussion within a narrow range; so,
that the non-linear circuit characteristic can be linearized.
So, basically when we say a linearization of non-linear circuit we are primarily focusing
the narrow range of the input or output transfer characteristic. So, they are related
basically the linear linearization of non-linear circuit and small signal equivalent circuits
they are related. From that we will see the new model or new concept of models of
transistors referred as small signal models. So, we will see that how the small signal
models are getting evolved and what is its usage of the small signal equivalent circuits
for some practical circuit ok.
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So, let us go to the example circuit now. So, this is the example we have discussed
before, but our focus here or our discussion center it will be different. Namely, it will be
as I said linearization of the circuit or you may say that linearization of the input to
output transfer characteristic of the circuit.
This circuit we have seen before, it contains the BJT NPN transistor and it is having a
base bias with a voltage. It is also having a collector bias through this battery VCC
through this resistor R and what we have seen that depending on the voltage here,
depending on the value of the resistance and the VCC. And, of course, based on the
parameter of the transistor the collector voltage of the transistor; or collector to another
emitter voltage of the transistor can be defined, or it can be expressed in terms of those
parameter.
And, then if we vary this voltage VB which is incidentally a VBE voltage we may call this
is Vbe or VBE whatever it is. So, if we vary this voltage it is expected that, if we retain
rest of the thing same the voltage at the collector it will change with this variation. So,
not only this collector voltage actually this variation it is happening due to the base
current variation, then the collector current variation and then the IR drop across this
resistance and hence the collector voltage here or emissive Vce.
So, then if I consider that, if we consider this is input and this is the corresponding
output, then we do get input to output transfer characteristics. So, that we have discussed
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for a given value of VBE how we get and also we have seen that if you change this
voltage, then how the base current and the collector current how are they changing we
have discussed in detail, we will be moving further on so, this is the Ib versus VBE
characteristic curve. So, likewise we do have if I multiply this curve by β of the transistor
we do get Ic versus Vbe characteristic curve.
And, then which is also assuming β is remaining constant these two characteristic curves
are having practically same profile. And, then to find the output voltage here, what we
have done it is for a given value of Vbe, we have drawn the transistor characteristic
namely the Ic versus Vce characteristic, and then also Vce characteristic. And, then also
we have drawn the characteristic of the resistor or the load, in this case whatever the
resistance we do have and then the intersection intersecting point it is defining the
corresponding Vce.
So, this is we have discussed and formed this one we also have obtain that, if I consider
this is input and this is the corresponding output, then if we vary this input and if you see
how this intersection point is changing and hence we can plot the input to output transfer
characteristic. So, if I just ask you to remember or recall whatever the discussion we are
having. So, if we change this Vbe with respect to some point and then the current is going
up or down; so, here if we vary this input or Vbe then the corresponding characteristic
curve it is going up or down.
And, then accordingly the intersection point is also changing and that gives us the
variation of the output voltage. So, that gives the variation of this output voltage. And,
from that if we plot the input and input to output characteristic. Namely, if I consider y-
axis is the Vce and x-axis is the Vbe, whatever what we have seen is that the characteristic
curve it is. In fact, inverse of this characteristic curve first it is going like this and then I
while the device is entering into the saturation region the characteristic becomes like this.
So, this is what we are referring to input to output transfer characteristic of the circuit.
Now, this input output transfer characteristic of course, it is quite fairly non-linear. And,
we have discussed about the sources of non-linearity, but just to recapitulate whatever
we discussed there, we say that because of the smaller Vbe, because of this portion it is
quite non-linear this part it becomes non-linear. And, on the other hand if the
characteristic it is going up here towards this point. Then the device it may be entering to
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the entering towards the saturation region and due to that due to have another non-linear
portion.
In between we do have the fairly linear part. So, we say that this part it is fairly linear,
but even then if you if you further zoom here and if you are trying to observe the exact
characteristic, it will be compared to this non-linear part it will be linear, but then again
depending on the range you are considering there will be non-linear part. Mainly,
because you may recall that this part it appears to be linear, but this part it is having
exponential dependency.
By the way here in this case we have assumed that this early voltage it is very high and
that is why we are considering this is flat. Now, in case if we are restricting our you
know voltage variation within this portion or within the middle of the input or output
transfer characteristic, then we may say that it is fairly linear. And, so, that is what we
are referring to linearization of the input to output transfer characteristics.
So, though the actual characteristic it is not linear, but if you restrict the voltage probably
we can we can as preteen or assume that this input to output the transfer characteristic it
is quote and unquote linear. So, what are the things we have so, far what we said is that,
if we restrict this Vbe then only we will be getting the linear region.
So, we assume that even if you are moving towards this point or this point accordingly if
we restrict the voltage variation probably the linearization is possible, but we are looking
for big range of linear transfer characteristic. And, hence we prefer that our focus or
discussion should be towards the middle of the input to output transfer characteristic.
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Now, let me go a little more detail of the linearization. So, what we are doing is basically
we are making use of these two equations and then we are considering instead of
considering this transistor we are considering the small signal equivalent circuit. And,
then using this equivalent circuit we are considering this loop and then we are
considering β and then we are finding the corresponding output voltage.
So, whenever we are talking about linearization, pictorially whatever we have discussed,
it is also having equivalent equations. And, let us see today we will be going little more
detail of those equations. And, let us see what are the equations involved into this
linearization, because conceptually graphically it is graphical discussion is fine, but
whenever we are looking for numerical solution definitely you have to refer back to the
underlying equations.
So, we will make use of these equations and we are considering that the voltage here it
will change. And, the variation here instead of thinking it is only DC what will be
considering it is having a signal part. And, then it is having a DC part and then this signal
part will denote by vbe and this part it will be VBE and this 2 together, we may call it is
Vbe.
In other words you may say that, with respect to time if we try to sketch the with respect
to time, if you sketch the Vbe part, it is having the dc part it is having the DC part. So,
this is this level it is VBE and with respect to that it is having the variable part. So, we
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may have either sinusoidal or maybe non sinusoidal or whatever it is as long as the
average of the small signal part it is 0, then you may say that the DC part with
progressive of time it is remaining same as this VBE. And, this part the variable part
whatever we see is vbe that we call it is signal.
And as long as this DC level it is not changing, it can be shown that the circuit
characteristic if we translate into linear kind of form the analysis the equations it
becomes very simple. So, in the in the next discussion and instead of varying this voltage
gradually, we may prefer to restrict our discussion that whenever we are changing this
VBE, it is having a quote and unquote constant DC, then on top of that we do have the
variation or fluctuation of the voltage, which is carrying the information.
And, we are assuming that it is the average of the fluctuation it is 0. So, it is not
necessarily that vbe will be sinusoidal it may be having any other pattern for that matter.
And, then if you want to see what kind of effect of this variation it is coming to the base
current, and then the corresponding collector current, and then corresponding the output
voltage or VCE voltage that is what we are going to discuss now.
So, the circuit now we will be considering it is as I said the same circuit, but the kind of
signal we are giving, it is writing over a DC part. So, as you can see here we do have it is
having a DC part, if you have a small signal part and these two together we do have Vbe.
Now, we do have the basic equations, namely the expression of this current it is again of
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course, this current will be having DC part and the small signal part. And, hence we will
be using different symbol for the base current namely Ib.
And, this is having 2 parts namely it is having IB plus the corresponding fluctuations due
to this voltage and that is represented by ib; so, likewise when we see the current at the
collector terminal. So, they are also the collector current this Ic, we will be using symbol,
Ic, which is having 2 parts; one is the DC part IC, and then in addition to that we do have
the ic.
So, now whenever you are trying to see what is the corresponding effect coming to the
collector, either we can find the effect on the base current and then you multiply with β
of the transistor, or probably you can directly use the exponential relationship of this
collector current on Vbe. And, then you can find the corresponding effect and our main
intention is to find the output voltage.
So, it is not necessarily that you have to go through Ib effect on Ib and then coming to the
Ic, you can rather directly you can go to the collector current expression in terms of Vbe.
So, as we have discussed that collector current. So, if we drop the early voltage the
collector current expression is the saturation current part and then . Now, as I say
that this Vbe it is having two parts Vbe + vbe.
So, if you see here when we when you talk about linearization in the in the graph, what
does it mean in this in the form of equation let us try to see that. So, we do have this
constant part part and then × ok. And, as I said that this part vbe part it is
function of time whereas, this part it is we can see that it is not changing.
So, you may say that this part it is remaining constant. So, the constant part let me write
in different color × . And, this part so this part on the other hand, we can write
in the form of 1 + + + . . . the higher order terms.
Now, if I say that the vbe, it is we are restricting which means that in our I-V
characteristic namely Ic versus Vbe characteristic curve, if we restrict our variation of this
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Vbe with respect to VBE within a narrow range. So, whatever the variation we are talking
here it is basically the vbe.
And, if the vbe, it is small compared to thermal equivalent voltage VT, then we may drop
the higher order terms and then we can find the so, these terms onwards if we remove
then we do have only this part. So, you can see that here if I drop rest of the things it is
nothing, but linearization of the characteristic. And, if I drop this part what we have here
it is the constant part. So, we do have this constant part × . So, that is multiplied
by 1 and then I do have this part. So, we can see this plus × into we do have the
VT part here and then we do have the vbe part.
And, whatever the other terms if I consider these terms if I assume that is small
enough. So, we are going to drop this part. So, we are removing rest of the things. So,
that is the linearization. Now, if you see with progress of time as I said that VBE it is not
changing with time. So, we may say that this is the constant part of the collector current.
And, the other part the linearized part after dropping the higher order terms namely this
part let me use a different color yeah. So, this part it is basically nothing, but this ic part.
So, whenever we say the ic it is changing with time due to vbe is changing with time, then
equation wise this ic part it is given by this. So, to say that the small signal collector
current it is this part which is nothing, but IC. So, that is why you would have . So, this
VT is there and then we have the vbe part. So, what we can say that this fluctuation it is
having an effect on the collector current and that effect it is given by this equation. And,
this of course, the constant current it is remaining the independent of the time and it is
remaining constant.
So, now we equation wise we obtain what will be the effect coming to the collector
current due to due to the variation here. So, now this current if it is, flowing through this
resistor; obviously, the drop across this resistance it will also vary. And, hence and the
supply voltage VCC on the other hand it is remaining constant.
So, if we do have this variation of this voltage with respect to time due to this vbe
naturally this will be having the corresponding effect coming there. So, then this output
voltage similar to Ic and the maybe Ib here also it will be having 2 parts; one is the time
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independent part on the DC part and then also it is having the time dependent part or the
variable part. And, this variable part we are denoting by vout and whatever the variation
you are observing here, it is again coming from this variation.
So, if I say that our source of variation is here that is creating variation here, that is
creating variation in ic, and that is also creating variation in this one, which means that
suppose this is carrying some information or say signal, this signal it is getting reflected
everywhere. And, if these signal somehow if you say that it is stronger than the original
signal, then you may say that this circuit is amplifying the signal strength ok.
But, of course, it has to retain the information or you may say that if the relationship of
here to here if it is linear then; obviously, variation shape of the voltage fluctuation here,
it is getting retained there. So, that is of course, now let us see what will be the
expression of this Vout we already obtain the expression of ic. And, now let us look into
the expression of vout in terms of this vbe.
So, let us go to the next slide yeah. So, what we have here it is we already have discussed
that, the collector current is this collector current is already having the variable part,
namely this part and then the constant part or the DC part the DC part. So, now, we are
observing the similar kinds of things are the output voltage Vout. So, here it is a very
straight forward if you see so, if you see the expression of Vout it is the voltage VCC
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minus this drop and this drop it is RC multiplied by whatever the total current we do have
and I say that it is having 2 parts.
So, we may write this is VCC ‒ RC × × or directly you can write this capital
part. And, then we do have whatever you see IC actually this part it is IC. So, this is same
as this IC here. And, then just to save some space I am using this capitalizing here and
then we do have the vbe part and then whole thing it is getting multiplied by RC.
So, now what you can do probably we can consider this part and this part along with this
one and we can separate this part. So, what we have here it is the time independent part,
it is VCC minus RC and this part it is as I said it is IC. So, that is IC and then we do have
and the time dependent part. So, it is having RC let me use this color RC × × vbe.
So, we may say that to summarize then vout, vout it is the small signal part or the time
dependent part or the information part, it is actually function of this vbe. However, it is
having a multiplication factor. So, as long as this multiplication factor is not changing
with time, then you may say that whatever the information we do have, that is getting
multiplied by this factor and probably if it is more than one then you can say that the
strength of the signal it is getting increased. And, of course, the VOUT it is having the DC
part. So, the DC part it is given here it is not changing with time.
So, what are the things we do have within this we do have and RC. Note that this IC of
course, it depends on this bias. So, depending on this bias the whole factor here, by
which this vbe it is getting multiplied that is that may get changed. So, if we if you are not
really fixing this DC part properly, then this multiplication factor may change with time,
then that may create disturbance here.
So, our objective here of course, we need to if we somehow managed to keep this part
constant or if you managed to keep this bias part constant, and then we may say that the
relationship this vbe to vout relationship it will be remaining constant. By the way this Vout
it is also it is Vce and incidentally this is Vout, likewise this is you may consider this is Vin
and this part you may say that this is vin. So, if I say this is vin then this gives us the input
signal to output signal relationship.
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So, equation wise you may say that this part it is representing input to output transfer
characteristic. Namely, whatever the input to output transfers non-linear input to output
transfer characteristic we obtain, out of that we are probably focusing may be central part
of it. And, then the slope of this line it is basically getting represented here.
Note that the slope here it is ‒ve that is captured by this ‒ sign and so, this is a large
signal Vin. So, you may say that this is Vin and this is Vout, large signal Vout it is having
non-linear effect, but then if we say that we are focusing only here, then you may say
that variation here it is vin and then corresponding effect here it is vout.
And, if we say that the variation or the DC part if it is not changing. So, suppose this is
DC part defining this point reference point namely this is VIN. So, if this part it is not
changing and if you are looking for the relationship of this vin to this vout or small signal
vin to vout then you may say that this is nothing, but translating or taking one part of the
transfer characteristic and considering only the small signal part.
So, if I take out this the input output transfer characteristic sorry this is vin. So, if I take
out this portion of the transfer characteristic and then what we are getting here it is the
transfer characteristic it is going through the origin. And, at this part we have discussed
some extent, but equation wise this is what we are getting.
So, to further get into that you may say that, we are linearizing this input to output
transfer characteristic to get small signal input to output transfer characteristic, centering
with this point it is called operating point, operating point or it is called question point or
Q-point. So, unless otherwise it is stated will be assuming that this point it will be not
changing with time of course, our first task is to find this meaningful operating point.
And, then only we can say that will be getting good part of the transfer characteristic
which is linear and then keeping our focus further subsequent focus around that.
So, whenever you are talking about linearization is basically linearization of the input to
output transfer characteristic with respect to Q-point.
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So, that is what we are saying that whenever we are talking about linearization basically
it is with respect to operating point or Q-point and which is referred as small signal
transfer characteristic. So, in the small signal transfer characteristic; in fact, we do have
two parts, we already have discussed, but one is a small signal ic with respect to small
signal vbe voltage. In fact, this is exponential part exponential behavior.
But, as long as our discussion is restricted within a narrow range of vbe namely if this
variation it is much less than VT. So, if I say that this is much less than thermal
equivalent voltage VT, then only you can say that linearization is meaningful. So,
similarly if I consider the vout versus vbe; so, there also either you can say that this is
small vout with respect to vbe which is incidentally vin. And, there what you have seen is
that the transfer characteristic it is we obtain it is like this.
So, since the both the characteristics are going through this origin and the biggest
advantage of translating the transfer characteristic into this form is that the circuit is
getting linearized. So, analysis it will be much simpler and if you are having multiple
signals influencing the circuit then you can directly apply the superposition theorem. So,
that is definitely it will be advantageous and also the overall analysis it will be
simplified.
So, here whenever we are talking about linearization is basically extracting the
meaningful part of the non-linear characteristic. In fact, you may recall if we extend the
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non-linear part it is like this and we are focusing around this. And, so, here also the if we
if we consider beyond this, it will be actually exponential kind of characteristic. So, if
you draw the corresponding circuit now. So, we do have graphical interpretation, we do
have equation information and then also we like to have the equivalent circuit. So, that
brings up the equivalent circuit something called small signal equivalent circuit.
So, what is that? First of all let me quickly draw this part, the equivalent circuit part. So,
we do have the diode and then we do have the either you may say voltage dependent
current source or the current dependent current source. So, if we are using the expression
of the Ic in terms of Ib then you may say this is current dependent current source or if you
are using Ic versus Vbe, then you may say that this is a function of Vbe.
So, whatever it is we do have the expression of this current Ic and then we do have the Ib;
that means, it represents both small signal part as well as the large signal part. And, then
we do have the small signal component and then we do have the DC part, this is
connected to ground and then we do have the resistor and this is connected to VCC. So,
whenever we are you know whenever we are considering the small signal transfer
characteristic, as I said that the operating point it is getting mapped on to the origin of
this characteristic.
And, this operating point is basically the Q-point. In actual characteristic of course, this
is not same as the origin in that, but in this small signal context the it is aligned with the
origin. So, circuit wise what does it mean. And, so, if you see here the current wise this
part this current is having two parts; one is the DC part and then it is also having the
small signal part. So, likewise this Ic it is also having the DC part capital IC as we have
discussed and then also the small signal part.
And, then this of course, it is DC, but and of course, the across the drop across the
resistance you may say that the drop across this one is VRC. So, that is having two part;
one is DC another is the small signal part. And, likewise whenever we are observing the
output the voltage here that is also having the DC part VOUT and then the small signal
part vout.
Now, whenever we are translating the transfer characteristic into this form namely the
small signal characteristic here and here. What does it mean is that we are dropping out
the DC part, which means that we are removing say this part, we are removing say this
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part, we are also removing this part and we are removing this part. In fact, if you see this
diode.
So, this diode is also it is non-linear it is in fact, highly non-linear rather, but if you are
see it is equivalent circuit this can be replaced by piecewise linear, by considering the cut
in voltage and in this case cut in voltage is VBE(on) and then we do have the resistance on
resistance incidentally we use rπ to denote that resistance. So, whenever we are
translating this one of course, we have to drop this part as well. So, we have to remove
this part as well.
So, what are the things are left behind, we do have in this part signal part we may call
this is vbe and then we do have this part. And, then of course, the current twice we do
have this part and that current if we multiply with β, then that gives us this collect
corresponding collector current. And, whatever the voltage it will be getting developed
in that situation, directly it is dropping this part, because VCC is dropped out, this part it
is dropped out, this part is also dropped out. So, whatever the voltage will be getting here
it is nothing, but this vout.
So, if I make an attempt to draw the circuit of the left out elements we do have the vbe,
then we do have the rπ. And, then we do have a current source either you may say it is
voltage dependent current source or current dependent current source, for the time being
let me call this is current dependent current source, which is ic , β‧ib and this ib, it is
basically whatever the current it is flowing through this new newly constructed circuit,
this is connected to ground and then of course, the resistor is there RC it is there and that
is connected to equivalent to AC ground.
And, so, we do have RC here. And, whatever the voltage it is getting developed here with
respect to this ground of this ground, that it is basically the small signal vout. So,
whatever the circuit now we are getting if I compare this circuit and this circuit. So, this
is referred as large signal equivalent circuit, where the mass transistor has been replaced
by this. On the other hand if you see here all the DC parts are getting suppressed or
removed and this is referred as the small signal equivalent circuit.
So, in fact, whenever you are talking about linearization of the input to output transfer
characteristic, it is taking us to a situation where the circuit is also getting translated into
different form called linearized circuit. And, though it is actually linearized circuit it is
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primary intention is to use this circuit for signal where linearity is valid. So, that is why
this circuit it is instead of calling linearized circuit it is referred as small signal equivalent
circuit. So, it is of course, it is having different parameters. So, what you can do?
I think in the next slide we will be discussing in detail of that how do we? In fact, we
have already have discussed this part we are dropping the DC part and we will be
directly going to the new set of parameters. So, yeah so, let me take a break and then we
will come back to this discussion of how do we get the small signal equivalent circuit
and new set of parameters in this circuit.
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Prof. Pradip Mandal
Lecture - 19
Linearization of Non – Linear Circuit Containing BJT (Contd.)
So, we are discussing that small signal equivalent circuit with respect to operating point
which is basically linearization and we are talking about how do we. Once we have the
circuit how we do linearize the circuit and so. So, whenever we are considering the
equivalent small signal equivalent circuit, if I quickly draw the circuit we do have the
small signal input and then base to emitter.
We have something called rπ and then we have the current source dependent current
source. So, either we write in the form of voltage dependent or current dependent. So,
this is ic we may write in terms of ib. In fact, there is another way of writing it you know
in terms of vbe.
The voltage drop across the base to emitter terminal, we call this is vbe and incidentally
since then there is no resistance here. We may say that this is also vbe and then. So, ic it
can be written in terms of vbe and we have seen that it is having some factor which is
and this is referred as trans conductance parameter called gm × vbe.
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Of course, we will come back to this point and then we do have the resistance RC and
this is connected to AC ground and of course, we obtain the voltage here. So, what we
are saying is that we have seen graphical interpretation of linearization, we have seen in
the form of equation and also we have seen in the form of equivalent circuit.
The equivalent circuit of the whole common emitter configuration involves the
equivalent circuit of the transistor. So, if you see this part, this is the equivalent circuit of
the transistor. So, this is the base terminal, this is the collector terminal and this is the
emitter terminal.
In this course, we have different elements or parameters involved say for example, we
already have discussed about the gm. So, likewise we have the base to emitter resistance
rπ and then we have from base to collector current gain and this is different from βF this
is actually referred as small signal current gain. And so far we are ignoring the early
voltage in case if we consider the early voltage depending on the voltage at the collector.
So, it will be having some variation of the collector current.
Namely based on the Vce variation we may be having some variation in the collector
current. So, if you consider that part also then across this current source. So, you may say
that it will be having some conducting element. So, across this one there will be another
conducting element it is actually it is going to the emitter.
So, this conducting element it is referred as output conductance in this case as you can
say that this we refer as output. So, that is why output it is referred as output conductance
and that is the meaning of each of these terms involve with the this equivalent circuit. So,
if you see here, they do have of course, their own unambiguous definition.
Whenever you are talking about say gm which is referred as transconductance of the
device. So, how is it getting defined? This transconductance is representing the
relationship between the collector current and Vbe. So, you may recall this collector
current Ic versus Vbe. So, this characteristic curve is exponential with respect to some dc
point or Q-point we are linearizing it and this linearization is basically a linear segment
of the line and that line can be represented by the slope of the line.
And this slope of the line is nothing, but the first derivative of this current with respect to
Vbe. So, the transconductance its definition it is change in collector current with respect
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to change in Vbe voltage. Note that this is Ic, this is Vbe. So, if we vary this base to emitter
voltage whatever the variation of this current we are observing keeping rest of the things
constant, this relationship it is getting represented by this gm trans conductance.
Since I am keeping other parameter constant particularly the collector to emitter voltage.
So, that is why we are considering this is partial derivative and we already have in
different way we have obtained this gm. Expression of the gm is . In fact, the expression
of this Ic in the form of a × and then if you take the derivative of first derivative
of this expression what you can get is you will be getting this is .
And this Ic of course, it is instantaneous Ic which is the slope of course, it depends on the
instantaneous value, but then if we restrict our discussion within a small range then we
can say that this Ic can be well approximated by IC namely whatever the current we do
have here at the DC operating point.
If you consider the slope of this line probably throughout this one we can assume that
slope is remaining constant and hence you may say this is . So, that is we obtain here
the expression of the gm is . On the otherhand the current flowing through circuit in the
small signal equivalent circuit if I say that this current is flowing through base to emitter
terminal or rather base terminal say ib. So, if I vary this voltage this current is changing.
So, you may say that if I take ratio of these two, then we may say that yes, it is basically
base to emitter terminal conductance. So, if I see the conductance here namely if I take
the if I observe the variation of the base terminal current with respect to Vbe then
equation wise . So, that is the input port or base to emitter port conductance, if I take
reciprocal of that that represents the base to emitter resistance its rπ.
Later I will see why we do have different subscripts, but at least we understand that the
unit here it is ohm. So, we call this is base to emitter resistance. And again if you use a
expression of this Ib in the form of × and then this part the internal part it
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becomes this is and then we may approximate that this Ib it is with respect to the Q-
point. So, we can say that this is * + .
So, depending on this IB of course, this value of this resistance it will vary. So, in fact, it
is intuitive if you see whenever you are observing the let me use a different color. So,
whenever we are observing the Ib versus Vbe characteristic curve. So, depending on the
operating point here we may get some slope here. So, that gives us one by rπ at that point.
Now, if I come somewhere some other point here of course, their corresponding slope
here it will be different so; obviously, at this point the corresponding rπ it will be
different.
But as I said that if we restrict our discussion or from our experiment with respect to
some operating point then you may say that this rπ it is remaining constant. So, based on
the at the dc current there IB we can say its resistance is .
So, likewise the other parameter if you see here namely the βo, βo of course, you may say
that sometimes we assume this βo it is quote and unquote close to or equal to βF. But
strictly speaking it is having its own definition and normally we use βo is the symbol
which represents the relationship between the collector current variation with respect to
base current variation.
So, obviously, this is different from . In fact, normally what it is; what it is used here
instead of writing here . The relationship it is fairly linear, but whatever it is normally
written in this form of . And I like to say here one thing that, if the βF it is remaining
constant for whatever the range of this ic and ib we are considering then we may say that
βo it is same as βF.
But in case if the βF it is different then; obviously, depending on the operating point their
dependency it will be different. So, ideally if we plot say Ic versus Ib. So, Ic along the y-
axis and this is along the x-axis is the Ib. So, if you see both of them are having
exponential relationship and so it is expected that if this both are exponential both are
having exponential dependency on the same parameter called Vbe then; obviously, it is
expected to be it will be linear and slope of this line of course, it will be the βF.
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But in practical case actually if you go to lower level of current it is having a different
slope. Here, it may be remaining constant and then again if you go to higher current
again it will be having a bend. I will not be going detail of the sources of those in non-
linear part, but as long as if you keep the transistor within certain range or if I say that if I
consider range of this collector current within sake few 100’s of µA to its maybe 10 mA
for normal transistor you may say that this range it is fairly constant.
So, if we are within this range. So, wherever we consider slope remains constant and this
if I say that, if I extend it if it is since it is going through the origin then the large signal
βF and βo they are same. But if you are say somewhere here; obviously, the slope here it
will be different which is the βo it will be smaller than this one likewise if you consider
the upper side.
If we sketch the variation of the β by that βF or βo with respect to say Ic what you can say
that in the middle range you may say that it is remaining fairly constant. If you go a very
low current it may drop and likewise if you go to a higher current it may drop.
This is the violation of low level injection and this is where the recombination current
starts also becoming prominent. Somewhere in this range you may say that low level
injection is valid as well as the recombination at the base region it can be ignored. And
hence both of these curves are having quote and unquote same kind of relationship and
hence the β is remaining constant.
That is about β. Now, if you consider other parameter particularly the conductance part.
This conductance is due to the early voltage or you may say if you consider this circuit if
I vary this collector voltage namely Vce voltage due to early voltage.
Due to early voltage effect, this Ic is having some dependency on the Vce. In other words
if we observe the collector current while varying the Vce it is having a increment of the
current. In other words if I increase this voltage, the total current is increasing which
means that the total current it is not just completely defined by the condition at the base.
In fact, some part it is also dependent on this one. And since where if we change this
voltage and if you are observing the same terminal current, you may say that if I take the
ratio namely change in the current with respect to changing this voltage that gives
nothing, but the output conductance.
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So, that is why we are saying here the output conductance go is defined by change in the
collector terminal current versus the collector to emitter voltage. And sometimes either
we put this element in the form of conductance or some people are writing in the form of
output resistance. So, if I take reciprocal of this one that gives us the output resistance or
rather is defined by .
So, in fact, if you see again to get the expression of this part you require the expression
of this Ic and so × . Now, I have to consider this additional factor namely
( ) part then only I will be getting this part is non-zero.
We have to take the expression of the collector current Ic which is having
( ).
Now, if I take the partial derivative with respect to Vce and then of course, since we are
changing only this one not this one. So, you may say that this part it is remaining
constant, only this part it will be changing. So, if I say that if I take the derivative of the
whole thing this part will be taking out and then we do have and that gives us
and this × .
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Now, we may approximate this whole thing by the collector current Ic. So, whole thing
of course, collector current is having this part, but since this part is appearing as this. So,
we may say that this part is very small compared to 1, only while you are taking
derivative we are considering this part. And then this part it is Ic and this is VA. So, the
expression of go it is basically .
So, we can say that all these parameters new set of parameters they are dependent on the
operating point and as the operating point we are trying to keep it constant. So, we may
say that for small signal equivalent circuit this parameters you may say that quote and
unquote remaining unchanged. So, whenever we will be drawing the small signal
equivalent circuit first step of course, we need to find this parameter and to get that first
thing is that we have to find the operating point. So, let us see what it can summarize
here.
We understand from our previous discussion that, whenever we are linearizing a non-
linear circuit, we are essentially drawing small signal equivalent circuit. And while you
are drawing the small signal equivalent circuit of an amplifier we are replacing BJT by
its small signal equivalent model and this model involves a certain set of parameter
device, we call it is device parameters.
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And they are given here, as you can see here we do have transconductance defined by
small signal collector current divided by small signal vbe and then the base to emitter
impedance. Which is defined by , small signal base current base terminal current then
current gain small signal current gain which is defined by .
Moreover, output conductance is here, ro is the output resistance. So, that is defined by
. So, all these parameters as we have discussed that they depends on the operating
point or to be more precise, if we express this small signal parameters in terms of the
operating point. So, the gm it is ; IC collector current at the operating point and VT is
the thermal equivalent voltage.
So, likewise when you consider rπ and since it is , so, it can be written in the form of
ic. So, we can replace ib by here and then we do have vbe and this part it is the . So,
the expression of gm we can write here or we can see that the expression of rπ = .
Where, β0 is the small signal current gain. Likewise, when you consider g0 it can be
expressed in terms of once again it is operating point namely , here VA is the early
voltage which is the device parameter.
Therefore, once we have the small signal parameters then small signal equivalent circuit
can be obtained. Namely, base to emitter resistance rπ and the current entering to the base
is ib, voltage drop across this rπ it is vbe. This vbe on the other hand it is producing a
current at the collector terminal. Collector to emitter we do have voltage dependent
current source which is ic = gmvbe and then also from collector to emitter, we do have
finite conductance g0. So, this is what the small signal equivalent circuit.
Now, this small signal equivalent circuit it would be very useful while we are converting
the actual circuit into in terms of its small signal equivalent circuit. Now, let see how it
can be deployed or what is its application, so, let see what its validity is.
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Now here we do have the small signal equivalent circuit of the BJT and let us try to see
that how it can be utilized to get the gain of the circuit. So, along with the small signal
equivalent circuit of the BJT let you also integrate the other components of the circuit.
Namely, the RC and then instead of connecting this to Vcc let you consider this is AC
ground. Likewise, at the input, we do have an input signal, which is applied at the base
with respect to a DC voltage, but for small signal, we consider the DC voltage it is zero.
So, this is vin small signal input and then at the emitter of course, it is connected to
ground and whatever the voltage will be getting here with respect to the ground. So, that
you call it is output and whatever the output you are getting here it is the small signal or
the signal output.
So, if we analyze this simple circuit we can find the expression of vout in terms of vin.
Incidentally, this vbe of the circuit is equal to vin. So, the output voltage if you see this
circuit vout it is the an output resistance RC which is coming in parallel with r0 of course,
r0 it is .
So, this multiplied by the current and the current flowing to this node it is gmvbe and if
you see the polarity of the current and if I considered this is the polarity of the developed
voltage this is plus and this is minus. Then we will be getting a ‒ sign here.
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Of course, this vbe it is vin. So, by combining this equation and this equation, what we are
getting here it is the expression of vout. The expression of = ‒ gm × (RC ⫽ r0). This is
nothing but the voltage gain of the circuit AV. So, that is how the utilization of the small
signal equivalent circuit. So, let us move to one numerical example to further illustrate
on this.
In this numerical example if you see we have the same basic circuit, the main thing is at
this bias we do not have any resistance. So, directly the voltage you are applying both the
bias as well as the signal to the base. So, that makes this circuit simple and then we have
say supply voltage say 10 V and let you consider this VBE such that the current here it is
say 10 µA. So, I am giving this VBE in term such that the IB it is 10 µA and then say β of
the transistor it is say 200.
And so that gives us the quiescent current here it is 2 mA. Now, to get a good linearity
range here namely to get good linearity range here we like to keep the operating point
will away from this point as well as whatever the saturation limit or active region limit.
So, this is may be the maximum voltage you can have here it is a 10 V. So, load line it is
intersecting there it its Vcc which is 10 V. This voltage it is very small, you may
approximate that this is 0.3 V. So, roughly you even if you are keeping this voltage say
at 5 V we do have good linearity range of this output I-V characteristic. So, if we do
have 2 mA of DC current is flowing for this base current and this β then we may say that
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we may prefer to have 5 V; roughly 5 V drop across this Rc. So, that gives us this
resistance maybe 2.5 kΩ.
So, suppose this information’s are given. So, what I have done here it is. In fact, there
may be two ways of framing the numerical problem, either we give this information and
then directly we can ask draw the small signal equivalent circuit, find the values of the
small signal parameters and then find the small signal voltage gain. Or probably we can
give this bias condition such that this is 10 µA, this may be given to us then find this
operating point and then we can go into this one, but whatever it is just for your practice
instead of say let you consider instead of 2.5 which is giving us exactly 5 V.
Let me consider this is something different may be 2.2 kΩ which is a practical value, 2.5
normally we do not get. So, probably you can try out find the operating point namely the
IB is given, collector current is also very straightforward. Then you can find the VCE
voltage which is nothing but VOUT also. And then you can find the value of the small
signal parameter gm considering the early not early the thermal equivalent voltage to be
25 mV.
So, this is . So, this is . Then the rπ it is not required. So, still you can write rπ
equals to . So, this is 10 µA divided by sorry this is reciprocal of that. So, * + so,
that gives us 2.5 kΩ.
By the way the base to emitter resistance where you can see that it is much higher than
typical diode on resistance, mainly because the base current though it is having
exponential dependency the base current is very small. And then we may assume that
early voltage it is very high. So, you may say that output conductance it is 0 and then βo
you can approximate to be βF which is 200.
So, from that you can find what will be the small signal voltage gain, the small signal
voltage gain it is if I consider magnitude it is gm × Rc and gm × Rc is . So,
this part it is 4.4; . So, that gives us right. So, whatever the value it is
coming.
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We have observed that linearization of non-linear circuit containing some transistor is

important. We are looking for linear behavior, then you may say that why are you
looking for non-linear circuit; learning non-linear circuit gives us possibility of
amplification. So, the non-linear behavior says like exponential behavior, it gives us
highly good gain.
In fact, this is one of the sources of one of the factor which is giving us good gain. So,
we require non-linear circuit, but then we are looking for linear circuit. So, that the in
output signal nature it will be same as the input signal nature and then what we have
done is that since you are looking for the linearization through that we are getting
something called small signal equivalent circuit.
Which is basically linearization of the total circuit, keeping our constraint namely with
progress of time dc wise the operating point should not change only the signal part it will
change with time and also the average of the signal should be 0. So, that the operating
point or the quiescent point should not change. So, that gives us some different notion
called small signal equivalent circuit. Now, whenever you are drawing some small signal
equivalent circuit of a given circuit the same notion it can be deployed for the simple
transistor also.
So, whatever if I consider BJT in this case if I restrict our signal within some range then
the BJT transistor can be represented by a linearized form which is referred as small
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signal model of the transistor. And why do you go for small signal model of the
transistor? That simplifies the analysis.
We have seen model parameter it depends on the operating point. So, it is having
different set of parameter, but once we get the value of those parameters and if we know
that quiescent point is not changing then we can make use of those parameter value and
then small signal model of the BJT or small signal equivalent circuit of the complete
circuit it will be basically simplifying the analysis and calculation.
This is the heart of analog circuit. So, today we have discussed primarily on BJT. So,
similar kind of discussion it will be there in our next class on MOSFET.
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Prof. Pradip Mandal
Lecture - 20
Linearization of Non – Linear Circuit Containing MOSFET
So, welcome back to this course on Analog Electronic Circuits, we are almost to the
verge of second week of on this course. And today’s topic of discussion is Linearization
of a Non-Linear Circuit which contains MOSFET. So, to simplify the analysis, we are
considering example having only one MOSFET transistor in the circuit.
So, let us see what is the where we are in the flow. In our overall flow the in the second
week discussion, we are basically linearization of input or output transfer characteristic
of non-linear circuit containing BJT or MOS. And in the previous module we already
have seen linearization of input to output transfer characteristic of circuit containing BJT.
Today it will be similar kind of discussion, but then instead of BJT we are focusing on
MOS transistor. And then similar to the BJT circuit, we will also be having a notion
called small signal equivalent circuit and from that we will see that there is the notion of
small signal model of MOSFET transistor. So, and then we will see that how the small
signal model helps us to speed up the analysis and helps us to find a gain of the circuit.
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So, that is where we are; so the concept it will be covered today it is linearization of non-
linear circuit containing MOS transistor; notion of small signal equivalent circuit and
then small signal model of MOSFET, particularly in MOSFET and then we will cover
how the small signal model of MOS transistor can be used to solve numerical problem.
So, to come to the example; so here we do have the running example; the here we do
have the common source amplifier; and at the gate we do have the voltage we are
applying; and at the drain we are applying supply voltage through RD; and then we are
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observing the output at the drain, namely drain voltage there, which is incidentally the
output voltage.
And what we are going to do that, we like to change the input here namely the gate
voltage Vg and we like to observe the corresponding effect on the Ids and on the Vd or
Vds. So, if you vary the gate voltage Vg, incidentally that we are changing Vgs of the
transistor; and we can see what is the corresponding effect at the Ids and the Vds, which is
the output of the circuit. And this is the information it is known to us; if the transistor it
is in saturation region, if it is in saturation region expression of this Ids in terms of Vgs
and Vds is given here.
So, we do have transconductance parameter K and aspect ratio of the transistor; Vgs ‒
Vth is the threshold voltage of the device square and ( ). And to keep the
device in saturation Vds should be higher than Vgs ‒ Vth; this is also denoted as Vd(sat).
Now you might have noted that, I am using a slightly different notation for each of this
parameter; say for example, Ids which means that this Ids is subjected to change with
time; and so, likewise Vds and then Vgs also.
So, if I vary this Vg or Vgs, we like to see what will be the variation there. And if I say
this is the input. So, if I say that this is the input and if I say that this is the corresponding
output; let me say this is also output, but let you consider this is the output; then input to
output variation what is known as input to output transfer characteristic. So, we are
expecting this transfer characteristic it will be highly non-linear, because the device it is
non-linear; and then we will be talking about how the non-linear characteristic curve it
will be getting linearized ok.
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So, let me use new slide for that to go for further discussion, yes. So, here we do have the
common source amplifier, where we are changing this Vgs and we are observing the
voltage at the drain as I said, we do have the VDD. Now here the known information as I
said before in saturation region, it may be typically it is well approximated by
considering this λ is very small; namely it is much smaller than 1.
So, we can ignore this factor and hence we can say that Ids is approximately defined by
only this part. So, which is indicating that the Ids current, the Ids current here though it is
function of Vgs and Vds; but we do approximate that this is function of Vgs only.
Whenever it requires we will be considering this factor, namely the dependency of the Ids
on Vds; but for the time being let me assume that Ids is predominantly defined by Vgs and
it is expression is given here, ok.
So, how do we find the transfer characteristic? So, first of all if we vary the Vgs or Vg, we
know that this Ids it will change and the dependency here it is square law; and then to find
the output voltage; so this is either you say this is Vg or Vgs. And to find the
corresponding output what we do, we consider the load line as well. So, the load line in
this case it is defined by this straight line having a slope of and this point is VDD as
we have discussed in our previous modules and this point it is and wherever it
intersects, that gives us the sorry ok.
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So, let me, I have committed a mistake. So, let me come back to on this point.
So, first thing is that we do have the Ids versus Vgs. So, that is the square law and then to
find the output voltage what you have to do; we need to plot the Ids versus the output
voltage. So, for a given value of Vgs, so the current it is hardly it depends on the Vds. So,
we may say that the device characteristic namely Ids versus Vds it is constant here in the
saturation. And then if you draw the load line, defined by this RD and the supply voltage;
so this is one end of the load line VDD and then the other end of the load line it is .
So, this defines the output voltage or the Vds. So, the Vds here it is given here. Now as we
discussed before, if we vary the Vgs with respect to some point; then what we are
expecting that the device characteristic it goes up and or it may come down. And as a
result the intersection point it is changing and that gives us the variation in Vds with
respect to variation in Vgs.
So, whatever we see here, if we plot the variation in say Vds with respect to variation in
Vgs. So, then what we will be getting here it is, in the middle portion it is fairly linear; but
then if you decrease this Vgs and say maybe towards the Vth, so it is expected that it will
be having a highly non-linear part. And then we do have beyond some point if I increase
this Vgs, then it may be, the device characteristic it may be approaching towards and
there we will be having another non-linear part which will be the other way.
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So, you may say that this non-linear part it is coming due to device entering into triode
region. On the other hand the, this non-linear part or rather here it is coming due to
device entering into the cutoff region. So, whatever the overall transfer characteristic we
are getting here it is as I said that; because of the device characteristic which is fairly
non-linear, we do have non-linear input to output transfer characteristic. So, this non-
linear input to output transfer characteristic we need to linearize.
So, we have seen that the this portion, middle portion of the characteristic of curve it is
fairly linear and whenever you are talking about linearization; if we are keeping our
linearization center around middle of this range, then the linearity range it will be bigger.
So, whenever we are talking about linearization, probably we need to fix a one point
called quiescent point or Q-point and with respect to that Q-point we may try to
linearize. And whenever we are linearizing we can say that, this Q-point it is defined by
the Vgs may be Vgs and the corresponding output it is say Vds; and with respect to we
may be having some variation.
So, if we are having some variation here, the corresponding effect it is coming here. And
in this plot input to output transfer characteristic we may say that, if we change this Vgs
with respect to this Q point here; we will be seeing the corresponding effect coming here
at the output. So, this after doing this linearization we are assuming that this Q-point or
operating point it will be unchanged, it will be remaining fixed; only the Vgs small
portion it will be changing centering to this Q-point.
So, the circuit now it will be having supply voltage, having a fixed DC part and the time
variant part. So, let us look into this circuit in different way, where the at the input we are
giving a DC voltage followed by one time varying component. And then we want to see
what will be the corresponding effect coming at the Ids current and also at the Vds
voltage.
So, that is basically graphically when we are saying that non-linear transfer characteristic
curve we are linearizing; here we are saying that we are changing the Vg with respect to
fixed DC voltage. And the variation here it is we are restricting, so that the effect coming
here it will be fairly linear with respect to whatever the variation we are imposing on the
gate voltage.
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So, let me start with new slide yeah; this is what exactly I was talking about, we do have
the supply voltage. So, again this is the same common source amplifier or common
source configuration. It is having at the gate we do have a DC voltage, so this is the DC
part; which is defining the operating point and on top of that along with that it is having
the small signal part.
So, you may say that this is ac part or time varying part. Though pictorially here you are
showing it is sinusoidal, but it is not necessarily be sinusoidal; only thing we want to say
that, it is average should be 0. So, with progress of time, the coefficient point or the DC
point it remains unchanged.
And it will be having impact on the Ids current. So, it may be having ac part and of
course, it will be having a DC part. So, likewise this output voltage it may be having a
DC part called VOUT and in addition to that it may be having small signal part say vout.
So, if I see the current here, it is having as I said that it is having DC part denoted by IDS
and then it is also having a small signal part ids. So, the total current flowing through
drain to source of the transistor that can be obtained by considering the same equation.
Only thing is that the Vgs part we are splitting into two part; one is the DC part, another is
the small signal part, rest of the things it is same.
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So, to know what kind of effect it is coming here, if we expand this equation probably
we can get the exact one and also we can get what will be the corresponding
linearization. So, if I expand this. So, we do have as is and then if we take this part
Vds sorry (VGS ‒ Vth) part separate from this vgs.
What we do have it is (VGS ‒ Vth) and then plus vgs. So, we do have square around that,
but let you take this part separate and let you take this part out. So, what we have it is
( ) . So, if I take this part out, what we will be having here it is [
( )
] .
Now, if I expand this part what you are having is, let me write this part ( )
[ ( ) ( )
].
So, now if I say that we are talking about linearization; which means that we are
essentially dropping this second order term. So, if you make this is approximately 0,
whatever the remaining term we do have here up to this point, that gives us the linear
linearized transfer characteristic.
So, if I say that if I multiply say one and this part, so that gives us the DC part. So, you
may say that this gives the DC part and after linearization if I multiply say this part with
say this part; then multiplied by vgs, so that gives us the ac part. So, we can say that the
small signal part or the a c part ids part it will be K divided by ok; 2 and this 2 and this 2
are getting cancelled. So, ( ) so, the square part it is getting eliminated,
because you do have ( ) .
So, you can see that it is having the vgs part and rests of the things are, if you see it is
unchanged. So, if I say that only vgs part it is changing. So, the corresponding change we
are getting at in the on the current, it is the DC part of the some factor here defined by
the DC part and then we do have the time varying part vgs. In fact, this part it can be
rewritten in different form. In fact, it is having three different forms. We do have say
form A, form B and then form C all are same; only thing is that if you see here, in this
form this part it is defined by ( ).
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Whereas for this case it is in terms of IDS and ( ) without considering in . And
then we do have the third combination it is IDS and the aspect ratio . So, depending on
the situation we may take one of these forms, but everywhere we do have the vgs
appearing.
So, I should say whether this form or this form or this form all the terms are essentially
representing the same thing; namely transferring factor from vgs to ids,. So, now, what we
are seeing here it is. So, if you recall the non-linear input-output transfer characteristic,
so I will be coming to this non-linear transfer characteristic.
So, let me go to the Vout part. So, now, we obtain the current part and now we like to go
to the final output voltage. So, you may keep this information in mind and we will be
making use of that. So, I say that this is what we obtain, the expression of ids part in
terms of vgs and the expression of IDS we already know.
So, let us see how we find the corresponding output voltage. The expression of the
output voltage of course, it is we do. So, this is the output voltage which is (VDD ‒ this IR
drop).
Now, the IR drop is basically we do have the RD multiplied by the total current; which is
having the DC part as well as it is having the ac part. And from the previous discussion
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we have already said that the expression of this the total current which is given here; it is
having the ac part and then also it is having the DC part.
And the DC part it is expression it is given here, it depends on the voltage here the DC
voltage and then the ac part it is having this part. One of those three factors, in fact, this
is the form one of those three forms we have discussed, it is basically the form c. So, we
can use any one of them that is not important right now. But what we like to say that, this
is function of vgs.
So, this Ids it is having an expression like this and this part it is having this expression.
So, which means that, if I multiply this RD with this IDS, so what we are getting here it is,
VDD. So, we are having this is VDD ‒ RD × IDS. So, this is the DC part which is I should
say that the DC part at the output and then we do have the ‒, I should say ‒here; we do
have ‒ RD × id, so this ids.
And then this ids part it is having this expression. So, we can write say this part
particularly, this part in the form of ‒ RD √ vgs. So, as I say that we do have a,
this Vout is having a DC part VOUT. So, this part it is basically the VOUT and this part is
the small signal part. So, in addition to that we do have the time dependent part or the
part which is coming from this one. So, that is vout. So, that is nothing but this ‒ RD
square root of so and so multiplied by the vgs part.
So, that gives us the input to output transfer characteristic considering this time variable
part. So, whenever you are talking about linearization is basically we are keeping our
focus on this relationship, ok.
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So, what we are going to do now it is; we do have large signal transfer characteristic
which is fairly non-linear and then out of that we are keeping our focus here and we are
talking about only this part. And whenever you are focusing on this part, the x-axis and
y-axis are essentially the small signal part. So, we may say that whenever you are talking
about this linearization, the x-axis is vgs and y-axis is vds or vout.
And whereas, if I consider the large signal transfer characteristic, the x-axis as we know
that it was Vgs in this circuit and then the output it is Vout; which is same as Vds, ok. So,
whenever you are talking about linearization is basically pulling out only this part,
pulling out only this part of the transfer characteristic. So, we are taking this part out
here. So, in other words we may say that linearization is basically getting a new kind of a
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So, that is what we are saying; that whenever you are saying it is linearization of the
transfer characteristic is with respect to one operating point finding the v; I should say
this is actually; I want to say it is vout versus vgs. So, we are basically talking about the
translating the large signal transfer characteristic.
So, we do have Vout with respect to Vgs; which is incidentally Vin and as you say that it is
having fairly non-linear behavior and out of that we are extracting the small signal part.
And once you pull it out and if we are observing the corresponding transfer
characteristic, it is x-axis is vgs or you may say this is vin. And then we do have the y-axis
it is vout; which is actually vds and this part, this part it is coming here.
So, if you extend of course, it will be having non-linear part. So, whenever we are
getting this small signal transfer characteristic curve it is basically we are getting new,
you know transfer the input output transfer characteristic curve. And this curve it may be
obtained by some simplifying the circuit through an equivalent circuit; where of course
we can suppress the DC part or the quiescent part, it is basically this is the Q-point or
quiescent point.
That part if you map it here that is equivalent of saying that; if we drop this DC part and
if you drop this DC part and also the corresponding and the DC part here VOUT, then that
gives us the equivalent small signal transfer characteristic curve. So, to get that you may
say that the circuit wise what we are doing is; this device whenever you do have this
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device, we may simplify that circuit in terms of the small signal. So, the current here
instead of IDS we may say that, this is ids as function of vgs. And we know that the this
function ids; if you see ids in terms of vgs, it is having a linear form, namely some factor
here multiplied by vgs.
So, that gives us and the vgs is basically gate to source voltage after dropping the DC
part. So, this is what the equivalent circuit out of the transistor and then of course, we do
have the RD connected here. So, whatever the circuit we are obtaining by dropping the
DC part is nothing but we can see another equivalent circuit; which is used for from
small signal transfer characteristic and hence this equivalent circuit it is called small
signal equivalent circuit.
And whatever the small, the total circuit it is referred as small signal equivalent circuit;
whereas, this circuit it is referred as small signal model of the transistor.
So, our next discussion it is this small signal equivalent circuit and small signal model of
the transistor. So, whenever you are talking about the linearization is basically going
towards that. So, let me take a short break and then we will come back to discuss further
about the small signal equivalent circuit.
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Prof. Pradip Mandal
Lecture - 21
Linearization of non – linear circuit containing MOSFET (Contd.)
Welcome back after the short break on the topic of Linearization of input or output
So, we are discussing about this a small signal equivalent circuit we are about to start
that, and the intension there it is of course, to get the simplified circuit. So, you may
recall the equivalent circuit if I consider the large signal behavior, what we said it is and
the transistor may be replaced by a current source dependent current source.
And, this current source it is Ids which is function of Vgs and Vds. So, that is what we
have discussed and the Vgs it is whatever the voltage it is appearing across get to source
and then we do have the so, this is the device part. And, so, this Vgs is controlling on this
current source and then we do have the RD part and this is connected to VDD.
So this is the Vout the voltage is coming here it is Vout and, the voltage you are applying
here it may be having a small signal part along with the DC part. So, we may we are
talking about this is VGS and this part you are talking about vgs. So, these two together it
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is defining the Vgs. So, this model it is a referred as large signal equivalent circuit and so,
this model it is large signal model of the transistor and the whole circuit it is large signal
equivalent circuit.
In contrast to that whenever we are doing the linearization what you are doing is we are
simplifying this current equation, namely the drain to source current we are considering
only the small signal part, which means that ids, which is having an expression like one of
the 3 expressions or ok. And, what is the vgs? vgs is the voltage across the
gate to source and this vgs of course, it is the small signal vgs.
And, the at the gate we are considering only the small signal part, whatever the vgs we do
have or vg we do have that part and then of course, we are retaining the resistor. But, then
at the end of the other end of the resistor we are connecting these to ground, which
means that we are dropping the DC part for the supply we are dropping this is 0. And,
also this VGS part we are removing here and then the corresponding whatever the circuit
we are getting here it is small signal equivalent circuit. So, this is what the small signal
equivalent circuit. And, so, this is the of course, the corresponding output we will be
observing here, it is showing only the small signal output voltage.
So, now we can see that this circuit it is; of course, it is simplified and most important
thing is that the linear relationship between this vgs and the vout it can be directly obtained
by analyzing this circuit. So, that is what it is referred as a small signal equivalent circuit;
one important thing is that, whenever instead of say this model.
So, I should say this is, this portion is the model of the MOS transistor, and this is
referred as large signal model whereas, in the small signal equivalent circuit whatever
the small signal equivalent circuit we obtain for the transistor, it is the small signal
model. So, this model it is small signal model.
Now if you see in this model and this model, here we do have one factor. So, this factor
it is it depends on the size of the transistor, it depends on the device parameter, it
depends on the operating point also. And, so, if I say that this is one parameter called gm;
why gm, it correlates the vgs to ids. So, it is conductance so, that is why g and m stands
for trans mutual from input port to output port.
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So, that is why this parameter it is referred as a trans conductance of the and the device,
particularly for the small signal. And this is one of the important parameter. So,
whenever you are talking about the small signal model of the device, it involves one new
parameter or new set of parameters rather and one of them is the gm.
So, whenever you are talking about small signal equivalent circuit or a small signal
model, we require new set of parameter. So, in the while you are going from large signal
equivalent circuit to small signal equivalent circuit. First thing is that we need to drop the
dc part and also we have to get this model involving new set of parameters. So, let us see
what are the other parameters are there along with this gm. And, very important thing is
that this small signal parameter it is a function of the operating point or it depends on the
operating point.
So, as just now I said that the small signal model of the device, which is having these ids
as function of vgs and then it is having this parameter gm. And, what is vgs, the voltage
appearing across this gate to source; so, this is the gate terminal, this is the drain
terminal; this is the source terminal of the device.
Now of course, if I add the rest of the things namely the resistance RD and then if you
make the connection to ground, if you make this to ac ground, and then if you also draw
the stimulus input signal stimulus, then that gives us the small signal equivalent circuit.
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But, if I for generalization if I concentrate say this part, this is one important information,
what is referred as small signal model of the device? And, the small signal model of the
device gm actually it is defined in this way, variation partial derivation of the ids with
respect to vgs. So, if I say that the circuit is linearized; so, you may see that this part it is
nothing, but this small signal ids likewise, this part it is vgs.
So, in fact, this representation and this definition actually they are same. And, the
expression of the gm as you have discussed, one of the form it is √ . So, this is one
form this is also same as ( ) and also it is having another form ( .

)
So, out of these 3 forms, whatever the forms you consider all of them are actually
essentially representing this gm. So, this gm maybe having different expression; in fact,
this expression you can directly you can obtain by considering this definition of this gm.
So, if you put the expression of this Ids and if you say that Ids is changing only with the
Vgs that is that is the meaning of this partial derivative, and from that you can directly
obtain these expressions.
It involves a small approximation, but actually eventually you will be coming to this
point. So, say for example, if I consider variation of Ids, and Ids it is ( ) (
) with respect to Vgs. So, what we will be getting it is you are almost getting this
one, except this vgs it will be vgs whereas, we are using Vgs and then ( ) part.
So, we can say that this is well approximated by ( ) , this 2 it is also
coming. So, these 2 and these 2 are getting canceled out, ( ) part it is there and
this part you can take it to be 1 and vgs part we are taking VGS and hence we are
obtaining this one.
Now, if you use the expression of this Ids in terms of Vgs and . And, probably then you
can replace these Vgs in terms of either Ids or this you can replace in terms of IDS and
VGS to get this three forms of the gm. So, what we like to say that the, this new set of
parameter gm, it is important thing is that whatever the forms are there. Each of these
forms are having indication that this value of this gm it is directly function of this the
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operating point either IDS or VGS or IDS and VGS. So, this parameter of course, it may it is
value, it may vary if you change the operating point.
So, to get a steady operation, steady linearized operation whenever we are talking about
linearization of the transfer characteristic with respect to Q-point, it is better to keep this
Q-point constant. So, that the value of this gm you can assume to be constant, but in case
if it is varying slightly over this linear range, still you may approximate that this is
remaining constant. Mathematically, you may say that that is equivalent of saying that
Vgs is same as VGS; that means, at this point and this point whatever the parameters are
there essentially they are same.
So, this is one small signal important parameter and we also have another important
parameter. So, far we are ignoring this ( ) part, which means the dependency of
this current on the output voltage. So, if you consider that, what we will be getting is that
of course, this Ids is dependent through this ( ) part, we may get a drain to source
one conducting element. And, that conducting element is nothing, but the output
conductance or drain conductance. So, it is definition is; so, again here it is partial
derivative of Ids, but with respect to Vds.
So, if you use this equation same equation, you can find the expression of this one. So,
please keep that in mind and once you consider this gd, this gd actually from drain to
source one conducting element. So, let me get the expression of this gd and then again we
will be coming back to the small signal model of the device. Probably, I do have a
different slide for that, ok.
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So, it is basically it is a similar thing here, but let me discuss on this. So, we already have
discussed this one. Now, we are going to discuss the expression of gd. And, that we are
getting from this definition and this Ids it is having an expression, it is (
) ( ).
So, this is the current expression and now if I take derivative basically whole thing, so,
we are taking partial derivative of this whole thing with respect to Vds. And, if you do so,
what we are getting is; so, we are not changing this part we are changing now Vds parts
or we can say this part is constant namely ( ) .
So, you may say that, this is we will approximated by so, this part if I multiply with
( ) part and then if I divide by ( ) part. Then, what we are getting here it
is this part along with this we are getting Ids and then in the denominator we do have
( ). So, this multiplied by λ. So, in fact, this is normally this part it is considered
to be a very small. So, we considered this is in fact, I should say this is not
approximation this is exact, whenever we are coming to this approximation we are
dropping this part. So, this is Ids × λ.
And, further to that we may say that this is IDS × λ. So, that is the expression of the
output conductance drain conductance λ × IDS, again here also you can see that it directly
depends on the operating point. We may draw the circuit of course, this is the expression
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of the gd, but we may draw the circuit either in the form of conductance or in the form of
resistance. So, then the corresponding resistance it is just reciprocal of this part namely
.
So, the small signal model of the device the transistor, we can say that it is the current
source which is ids = gmvgs, and in parallel with that we do have the conducting element
gd and then we do have the at the input, we are defining the vgs gate to source voltage.
So, this is the gate terminal, this is the drain terminal and this is the source terminal.
So, what we are now up to that we started with linearization of the non-linear circuit, and
while you are bring the linearization we are dropping the dc parts. And, finally, we
obtained different equivalent circuit of the whole circuit and that invites us to consider
equivalent circuit of the MOS transistor, and this equivalent circuit involves only the
small signals and that is what the completion of the small signal model.
So, this model of course, it is I should say it is a simple enough part then, if this model it
is sufficient for mid frequency range and low frequency range, but if you are going to
higher and higher frequency, then gate to source there will be some more components
namely gate to source capacitance, then gate to drain capacitance. So, those are the
additional elements again they will be popping up.
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So, gate to source we may be having capacitance. So, it is denoted by Cgs like gate to
drain there will be another element capacity of element is represented as Cgd. So, if I
consider this capacity of elements then this model of course, it is also it is small signal
model, but this model can I represent this circuit the device behavior in the high
frequency range also. So, if I add this capacity of element, then it is called small signal
model of the MOSFET in mid frequency as well as high frequency.
So just to simplify it is normally referred as high frequency small signal model, on the
other hand if we drop this to capacity of element it is simply said it is small signal model
of the MOSFET. So, what maybe it is application of this model? Of course, we can
simplify the analysis and then we can find the gain of the circuit so, let us consider one
numerical example just to highlight that. So, the same example will be going there, but
let us start with this new slide.
So, just to get some number here, let you consider these device parameters and then the
dc voltage and the, this dc voltage and the Vth and the RD. And, what we have to do here
it is we need to find what will be this vout. So, we need to find what will be the vout in
terms of this vgs or vin? So, this is same as vin also. Now, let me consider what are the
parameters are given to us it is a say this is 10 V, let you consider this is maybe 2 V and
let you consider Vth = 1 V for simplicity of calculation. And, then W say 10 µ, L = say
maybe 1 µ and let you consider K the transconductance parameter K = say 200 µA/V2.
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Then, we can find what will be the output, but of course, we require the resistance value
here. So, let me take how much probably 4 k it will be good let us see ok. So, how do
you proceed, first of all to get the gain namely, ok; so, what you have to do the statement
is that, we need to find our objective is to find and it is value. So, to do that how do
we proceed?
First of all the small signal parameters the depends on the operating point. So, first thing
is that we need to find the operating point and to do that what you do let you consider the
dc part and let me find the IDS. So, IDS = ( ) and then ( ). So, for
the time being let you consider λ is very small so, ≈ 0. So, what we are getting here it is
× ( ) this part it is approximately 1. So, that gives us 1 mA.
So, that is the IDS dc current.
So, the dc current flowing here it is 1 mA so, the drop across this resistance it is 4 V. So,
from that we can see that the VOUT. So, that gives us VOUT it is 10 V ‒ 4 × 1. So, that is
the 6 V, VOUT the VDS is 6 V. Now, we do have we can verify whether the device it is in
saturation region or not. So, we do have 2 V here we do have 6 V here; obviously, the
devices having pinch of happening at the draining. So, the device it is in saturation.
Now, then we can find the value of the small signal parameters. So, since we are
considering λ = 0. So, we can see that the, directly we can say that gd it is a small I mean
it is 0 and then gm. So gm it is having different expression. So, either we can write in
terms of IDS and VGS ‒ Vth say, for example, if we consider ( )

. So, that gives us
( )
. So, that is 2 mA/V, right. And, then what is said is that gd it is 0; so, that gd is 0.
So, that gives us the output voltage vout is RD of course, with a ‒ RD × gm × vgs.
So from this one what we can find is that this is it becomes ‒ RD, that is 4 K and then gm
it is 2 m so, that gives us the gain of 8. So, that gives us the final gain of the circuit. So,
what we have done is that first we obtain the operating point here and then after that we
obtain the small signal parameter value. So, this small signal parameter values are here.
And, then we obtain the small signal voltage gain by considering this one. In fact, we can
draw the small signal equivalent circuits whatever we already have discussed; the, this
part it is not there. So, this is this I should say gd = 0. So, this is for the MOS transistor
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and then we do have the RD part, this is connected to ground and then this is vgs we are
applying here, the current here it is gm × vgs. So, the voltage appearing here appearing at
the output node here it is, it is this current multiplied by this RD. So, that is why we said
that vout is this one.
I think probably you can try to make similar attempt in case if the circuit is in different,
namely if the circuit is a containing PMOS transistor and then you can see what maybe
the corresponding small signal model and so and so. I think that is all I need to discuss,
but let us see what are the things we have covered so far?
So, today we have discussed about linearization of a non-linear circuit containing

MOSFET device and then we have discussed about the small signal equivalent circuit.
So, whenever you are talking about linearization of the circuit is basically we are
translating the actual circuit into a small signal equivalent circuit. And, then in the small
signal equivalent circuit whatever the circuit we are having corresponding to the
MOSFET, it is referred as the small signal model of the MOSFET, which involves
different set of parameters namely say trans conductance gm and gd. And, they are values
of course, it depends on the center point of the linearization namely there are coefficient
point.
And, then what you have seen is that, if you use this small signal model of the device in
actual circuit, that will simplify the analyzes and also that will simplify the calculation.
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In fact, in today’s a simple examples, the simplification you may or may not appreciate,
but whenever it involves a circuit having many transistors, I am sure that then you will
appreciate the utilization of the small signal model of the transistor. I think that is all I do
have so.
Thank you.
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Prof. Pradip Mandal
Lecture - 22
Linear Models of Amplifiers (Part A)
Dear students, welcome back to this NPTEL course on Analog Electronic Circuits and
today we are going to cover the topic of Linear Models of Amplifiers. So, in fact if you
see, we already have covered few topics and today actually we are in the first day of 3rd
week. So, let see what where do we stand today, compared to our overall plan.
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This 3rd week we are planning to cover amplifier models and followed by cascading
multiple amplifier stages; and then followed by CE amplifier, common emitter amplifier
and common source amplifier. And under this topic of amplifier models what you are
going to cover it is; the voltage amplifier, current amplifier and trans-conductance
amplifier and trans-resistance or trans-impedance amplifier.
So, these are essentially simplified model of the different types of voltage amplifier.
Today we are going to discuss with simple example and we will cover the purpose and
the little detail of the model different, these four models.
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Now, what are the concepts we are going to cover today? It is, basically as I said that the
model of voltage amplifier, then model of current amplifier, model of trans-conductance
amplifier and trans-impedance amplifier.
So, primarily we will be discussing more detail of these two topics and whatever the idea
we will be gaining from that, we will be extending to the other two types of amplifiers
quickly. So, let see the voltage amplifier and let we start with two simple examples of
voltage amplifiers.
Say for example, the first one it is; it consist of BJT, second one it is having a MOS
transistor. And for each of the cases what we have here it is, the DC voltage source and
then of course the ground and along with the biasing element resister. The transistor it is
in this case the BJT is kept in the active region of operation with the help of VBE, the DC
voltage here.
And then on top of the DC voltage we do have the small signal called vbe. And on the
other hand here for the transistor having the MOSFET, it is again it is having a DC
voltage source and then of course the ground, main ground and then we do have the
biasing resistor call RD connected to the drain of the transistor. And then at the gate, we
are applying a DC voltage call capital VGS on top of this DC voltage we are applying a
small signal.
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So, the if you see the voltage here along with this vgs ; the voltage here we are applying
is, it is having a DC part as well as the small signal part. So, we can say Vgs. So, likewise
for the BJT circuit on the other hand we do have the Vbe. And it produces a voltage here
at the output, which is having a DC part plus small signal part called vout. So, same thing
here also, it is having a DC part and the small signal part.
So, whenever we are going for say model or linearization basically what you do; as I said
that the transistor we are keeping in the appropriate region of operation, and then after
that we try to find what is the relationship between the applied voltage here to whatever
the corresponding output we are getting. So, in our main operation the DC conditions are
kept intact, only the small signal part changes with time and then the corresponding
effect we observe here.
So, since the DC parts we are not changing what we can think of that; we can probably
simplify the circuit, which supposed to represent the relationship between this output and
this vbe. Rather dependency of this signal output with respect to the input signal here;
same thing for the circuit amplifier having the MOSFET transistor.
So, since the procedure it will be same for this circuit and this circuit and let you
concentrate only one of them; let you concentrate only on this circuit in the next slide
and let us see what is the linearized model or the voltage amplifier model. So, the same
circuit we are going to discuss here.
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What we have here as I said that, we do have the basic amplifier and at the input we are
having a DC voltage, on top of that we do have we are applying a small signal. So, if you
observe the voltage here and if we call this is Vin to the circuit; it is having a DC part
here which is VBE and then on top of that we do have the small signal part. So, you may
say that the small signal part is given here, and that small signal part is the vbe or you
may call this is vin.
So these two together; the DC part and the small signal part together they are
representing the total or instantaneous voltage which is of course, a function of time.
And the consequences of whatever the voltage you are applying here; if you observe at
the output, if you are keeping the DC voltage only, then at the output will be getting a
DC voltage.
So, this DC voltage it is given here, we may call this is VOUT. So, that is one part of this
VOUT. And now if we are applying the small signal at the input here, the corresponding
effect here it will be coming; which is shown by this variation of the output voltage with
respect to time.
So, if the input here it is sinusoidal, we are expecting that output will also be sinusoidal.
And this sinusoidal part it is referred as small signal and it is referred as vout. So, these
two together VOUT and vout together, they are representing the instantaneous output. So,
whatever we are seeing here it is essentially the instantaneous output for the given
instantaneous input.
Now, whenever you are talking about modelling of voltage amplifier what does it mean
is; we like to change the circuit, whole circuit by an equivalent circuit or you can say
equivalent linear circuit, which primarily correlates the small signal output with respect
to whatever the small signal input we are giving. So, that is what the meaning of the
voltage amplifier.
So, whatever the sinusoidal part we are applying here to what are the sinusoidal part we
are observing here; that is what it is getting represented by the voltage amplifier. So, let
we go little detail of that, but before that just to summarize what I said here in the next
slide.
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So, what we mean by the voltage amplifier? It is an equivalent linear circuit and it is
main purpose is to provide the dependency of output signal on the input signal. So,
dependency of this output signal on the whatever the input signal we are applying that
supposed to be captured by this one.
And as I said that with progress of time this DC part we are not changing. So, we can
probably eliminate the DC part in the simplified model to make the circuit simple
enough or probably the analysis we can make it simpler.
So, in general you might have observed that at the input, now we are not calling it is vbe ;
rather in general we are calling this is the signal source vs having a DC part. So, these
two together we may call this is Vin and then this voltage source may be having a
Thevenin equivalent resistance call RS or the source resistance.
So, we are stimulating the circuit with this kind of arrangement and at the output what
you are observing is that the voltage across the output point with respect to the common
node and we are placing one capacitor to remove the DC part. In fact, once we place this
capacitor, this DC part it is getting eliminated.
So, naturally whenever you are talking about voltage amplifier, we are not concerned
about the DC part or the rather we are simplifying the circuit just to keep the focus to
find the relationship between the small signal input to the small signal output. So, the DC
part we are eliminating.
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So, as you can expect that we can drop this part to 0, we can drop this part also to 0 in
the small signal model. And of course, while you are talking about the signal changing
with time; so we can assume that this capacitor it is also working as a short from this
point to this point.
So, what we can say here it is the DC part, after eliminating the DC part, of course with
appropriate meaning of the circuit namely keeping the circuit in the appropriate region of
operation. The simplified model must be expression the relationship between this signal
source or whatever the input voltage you do have to this output, ok.
So, the simplified model as I said that this DC part we need to drop to 0 and here also
this DC part, equivalently this DC part is also going to be 0. So, we can say that DC parts
not only in the circuit it is getting to be 0; but our focus is also on that, namely the signal
and making the DC part 0.
So, we may say that to again to summarize what we said is; that we like to get the input
to output signal relationship primarily. So, this is the say, you may say that input signal
and this is the corresponding output. So, the input signal of course, it may be coming
from the signal source it need not be same. And since we are expressing this output in
terms of the input signal, we the simplified model must capture one basic element called
voltage dependent voltage source, ok.
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So, we may say that this is representing the output voltage with respect to the common
node. And this is, in fact if you are not putting any load to the output; this supposed to be
representing the gain of the circuit. So, let we call Av is the voltage gain of the circuit.
So, Av × vin; if I call the input voltage is vin. So, Av × vin is giving the voltage here. So,
this is the first element, input to output voltage gain, so Av is that voltage gain.
Now, what are the other elements we require? Note that the basic purpose of having this
model of the voltage amplifier is that to simplify the circuit; but at the same time it must
represent whatever the necessary information we are looking for. So, apart from the
game next thing is that, the loading effect at the output port and the input port. So,
whenever we are talking about the loading effect at the at the output port; which means
that, the moment we connect load to the output of the circuit, so naturally the output
voltage signal it may not be remaining the same. In fact, theoretically it will not be
remaining same.
Now, how do we capture the variation of the output voltage based on the load? So, if I
connect a load at the output; say for example, I am connecting one load say RL. Probably
this RL it is not changing the DC operating point of the circuit; namely we do have a DC
blocking capacitor. And then if the moment if I connect this node here, obviously, I will
be getting the same output voltage. So, this is the output voltage.
So, naturally just by having this voltage dependent voltage source is not representing the
main amplifier. So, I do have the input port here and vin is the voltage at the input port,
that is how it is defined. So, I should say this is to be two port network; at the input we
are giving a voltage and at the output we are observing the corresponding effect called
vout.
Now, as I was mentioning that how do we capture the loading effect and so, what we can
do it is, we can put a resistance here. In fact, you can think of that; since at the output
port we are considering signal in the form of voltage, naturally we may be expecting one
Thevenin equivalent resistance. And let you call this is RO, output resistance of the
amplifier at the output node.
So, that takes care of the loading effect at the output port. Likewise the input port; in case
say I do have a signal source which is maybe getting loaded with the circuit, yeah let me
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use this color. So, I may be having a signal source called vs as we are saying here. So, vs
is here and the moment we connect the signal source to the input port or the amplifier;
depending on the source resistance and the internal behaviour of the circuit, the input
voltage coming to the circuit namely vin need not be same as the vs.
So, again once I connect this one whatever the reduced voltage you will be getting at the
input port to capture that, we need to put one element here. So, I should say, I must say
that we need to put one element called say input impedance or input resistance, if we can
simplify it.
So, this input resistance and whatever the external source resistance we do have, they are
forming one potential divider. So, the voltage coming at the input port of the amplifier
which is vin, definitely it will be lower version of this vs. So, we can say by keeping this
input resistance here, I can consider the loading effect at the input port. So, likewise by
keeping this RO at the output port, I can consider the loading effect at the output port.
So, I do have basically three important entities in the circuit; one is the voltage amplifier,
sorry voltage gain Av; then output resistance which is representing the loading effect at
the output port; and then other one is the input resistance Rin to take care of the loading
effect at the input port.
So, the circuits here what you can see, it is the small signal model of the voltage
amplifier or you can say that it is a model of the voltage amplifier, so model of voltage
amplifier, ok. So, what we are doing is that; so let me summarize what we said here.
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So, this is what the same thing we have discussed, we do have the model, we do have the
model of the amplifier; namely the voltage model, voltage amplifier rather, voltage
amplifier model. So, what it represents is basically the input to output relationship. And
as I said again to summarize the, it is having three important parameters called input
resistance, voltage gain and the output resistance.
So in fact, if we are applying one input signal here vs and if you like to know what will
be the corresponding vout; first of all Av it will be giving us the gain from this point, the
input port to the unloaded output. Why do I call it is unloaded? In case if this RL is
infinite, then there will not be any current flow; so the voltage coming here it will be
same as the internal voltage, which is Av times vin.
So, if I am not connecting any RL, whatever the gain I will be getting at the output port
with respect to input port is solely captured by Av. So, that is why this Av it is referred as
open out unloaded voltage gain or open output voltage gain. On the other hand the
moment I can need this RL; the available voltage here it will be the voltage here which is
Av × vin, multiplied by this attenuation, all right.
So, the vout, now if I say that what will be the vout; let me consider this
( ) . Now again this vin it is not same as vs. So, if you see, if I write this vs,
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sorry vin terms of vs what I will be getting here it is; Av and then
( )( ) , let me use this color vs.
So, this simple model it is helping us to find the input vs to final output voltage. And it
involves the, as I said that important parameters of the amplifier it is; it is having the
unloaded voltage gain, it involves the input resistance along with this source resistance
RS and also includes the RO along with this RL. So, I should say these three parameters
are sufficient to represent a voltage amplifier, all right.
Now likewise, so at least we understand that the simple model is good enough to capture
the behaviour of the amplifier, main behaviour; namely the linearized behaviour. And
probably then we can cascade not only this load and the source resistance here; probably
we can have multiple stages of voltage amplifier or you may have multiple voltage
amplifiers, they may be cascaded one to each and so and so.
And then at the input of course, we may be having the primary source. And then at the
output we can put the corresponding load resistance. And so, the output resistance of this
amplifier one, so output resistance looking into this output port. And input resistance or
the second stage or second amplifier looking into it is input port, they may be providing
the loading effect.
So, the loading effect it is not only just coming from the primary port element namely RL
and RS, but also whenever we are cascading say multiple voltage amplifiers together,
then the output resistance of one stage and input resistance of the other stage together
they are providing loading effect at this middle point.
So, that is how I should say that if we are having a circuit having many stages of
amplifiers. Then you can probably each of the those amplifier stages, you can represent
by the simple simplified model. And then you can probably cascade each of these
simplified model together to get the overall gain or overall transfer function of the
circuit.
Now, I must add few things; one is this load need not be always resistive, likewise this
resistance, input resistance need not be only resistive, it may be having reactive
components also. But the basic model, namely it will be having three elements, it will be
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there. And in case each of these elements are having reactive part also; so in that case,
we may consider in general it is a complex entity and we may call this is output
impedance call ZO. So, likewise this element instead of calling Rin, we may call it is Zin.
And so, that is one point and the second point is that, whenever we do have fairly
complex system, we may not be having always voltage amplifier; we may be having
some other amplifiers. So, that is what I said that, in this discussion we will be having
model of not only voltage amplifier but also the current amplifier and maybe other kinds
of things.
So, depending on the signal type here, this signal if it is current and likewise the output
signal it is current; then we can think of the corresponding model it must be different
from this model that is called the model of current amplifier, ok. So, let me take a short
break and then I will come back.
Thank you.
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Prof. Pradip Mandal
Lecture - 23
Linear Models of Amplifiers (Part B)
Welcome back after the short break. So, before the break we are talking about the Model
of Voltage Amplifier. And, as I have given a hint that the amplifier need not be always
voltage amplifier.
There may be based on the signal at the input and signal at the output we may be having
different types of amplifiers. So, let us talk about other kinds of amplifier called current
amplifier. And, whenever we are talking about current amplifier similar to voltage
amplifier, what does it mean is that, it is an equivalent linear circuit, which provides
dependency of the output signal output current signal on the input current signal.
So, note that the output signal and input signal both are current and that is why you we call
this is current amplifier. So, similar to the previous case here we do have one example
having this is also amplifier having 1 BJT. And, as you can see here, what are the things
we do have is the BJT is at the center place, and then it is having a DC bias through the
RC, we are giving proper voltage at the collector of the transistor.
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And, then we do have a DC current at the base which is providing a meaningful bias to the
base of the transistor. Either you can think of this VB it is sitting the VB or on the on DC
base current, but whatever it is this is also providing one bias in condition. And, depending
on this IB and beta of the transistor we may having a if the device it is in active region of
operation, we may be having this collector current DC collector current.
So, this DC collector current is flowing through this RC providing a voltage draw ensure
and most likely that even after deducting this drop the VCC it is sufficiently high. So, that
it is based to collector junction it is reverse bias. Namely keeping the device, it is in active
region of operation. So, there is the main part here. So, the main part it is here including
the bias.
And, all and then if we feed the signal in the form of current at the base as we are seeing
here. And, depending on the current here we are expecting this current to the flowing. Note
that in simplistic model here we are showing this is signal current, which means that it is
average it is 0.
And, need not be sinusoidal, but sinusoidal things we may consider as one special case.
So, at the base of the transistor what you can say that the base current to the transistor it is
having two components. Namely the IB, the DC part, and also the time varying part which
is shown here. So, it is having a DC part here and the time varying part.
So, the time varying part is given here. So, these two together they are giving the total base
current. So, as a result the current flowing through the collector it is also having two
components; one is the DC part and the small signal part.
Now, if you are observing the voltage at the collector without making any connection here,
then you may see the voltage is changing there, but in case if we are looking for this circuit
as a current amplifier, then at the output we like to extract the signal in the form of current.
So, what we do?
We like to short this output node to ground and then we like to extract the entire signal,
but while you are doing this, we have to make sure that the output node it is not really or
other the collector node it should not get shorted to DC ground. And, hence we need to put
one DC blocking capacitor or it is referred as AC coupling capacitor.
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So, for time varying signal, whether it is current or voltage whatever you say, that we can
think of this capacitor is essentially working as a shot. So, the current whatever the current
will be observing here is the variable part of this the collector current. So, we may call this
is a iout.
So, the collector current here we can say the total current here; it is having a DC part. So,
it is having a DC part here sorry, it is having a DC part here. So, the DC part it is IC, and
then it is having the on top of that it is having the small signal part ok. So, in case if we
are not connecting anything here actually this IC it will be flowing here or a iout will be
flowing here, but you in case if you want to extract the signal, you need to connect to AC
ground through this capacitor to extract this entire current.
So, naturally the voltage here ideally by making this connection it will not change. And,
then you can say that whatever the current it is flowing, the signal current it is flowing it
will not flow through this resistor. So, the current whatever we obtain here, which is
referred as the short circuit current or it is called unloaded current I must say it is unloaded
current. Since, the signal here it is current form. So, to get the entire current you must short
this to AC ground to extract the entire current.
For voltage signal we like to keep the output node open whereas, for current signal at the
output node we must sort it to AC ground. So, anyway so, this is what the amplifier overall
amplifier as I said that at the input we are giving say DC current here and along with the
signal current. And, at the output what we obtain here it is a DC part and a small signal
part, but then whenever we like to see this circuit as an amplifier the signal amplifier, then
our main focus is that this is the input and this is the corresponding output.
So, whenever you are talking about the model of the current amplifier, similar to voltage
amplifier. What we are looking for it is simplified equivalent circuit, which must represent
this entire circuit, in terms of finding the relationship between this final output to the this
input ok. So, what we have said here, let me again summarize in the next slide I think I do
have the next slide to summarize.
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Yes. So, whenever we are talking about the model of amplifier. So, what we are referring
to it is so, we are basically referring to one equivalent linearize circuit, which is
representing the entire circuit to find the input to output relationship, input to output
relationship. So, what may be the corresponding circuit here, that is what we are going to
say it is the model of the amplifier.
So, similar to the voltage amplifier here again we like to remove the DC part, we like to
exclude the DC part and the model to simplify the circuit. So, we will be definitely
excluding this part and also to avoid DC current we are or I should say that we are feeding
the signal only through coupling capacitor. Likewise, while we are extracting the signal
we are putting a DC blocking capacitor here at the output port.
So, we are assuming that these arrangements are there. So, for in the model; however,
since we are focusing on the signal which is having sufficiently high frequency for which
this capacitor it is working as a short, this is also working as a short. So, this as I said that
this DC part need to be made 0. So, likewise the DC part we are making it to 0 by putting
this capacitor. Now, to again to see what are the basic elements are there in the current
amplifier let me focus, let me start with a fresh slide.
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So, what we are going to do in the current amplifier model, it is we like to get the
relationship between the primary input call the source current to the primary output. And,
the model, whatever the model we are going to discuss here it must be having input to
output current game and it should be unloaded current gain.
So, the first element of the model we are expecting that, we must be having a current
dependent current source. So, if I say that the gain of this amplifier it is a AI. So, the output
current unloaded current should be AI times the input current iin. So, that is the current
here, which is the unloaded current.
And, then similar to the voltage amplifier and what is iin is whatever the current is entering
to the circuit, entering to the circuit. So, the circuit may be having elemental like say,
having one element which is having some finite conductance or finite input resistance, but
whatever it is as long as iin is entering here. And, then we are getting the corresponding
output here and the output it is in the form of current.
Now, this element AI as I said this is the first parameter or first element of this model. The
other 2 elements supposed to capture the loading effect at the output port and input port.
Now, the moment we connect to load at the output instead of directly shorting. So, if I am
having a finite resistance at the output so, it is expected that the practically the current
flowing through the circuit may not be same as the internal current.
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So, whatever the current will be seeing here call iout need not be the total current what we
are getting here. In other words, the we must add one we must add one non zero
conductance to this element in parallel with this current depending current source.
So, either we may say that this conductance is GO or you can write in terms of resistance
call RO. And, the output port of course, it is here. So, the moment we connect this RL;
obviously, then the total current it will be getting bifurcated one part it will be flowing
through this RL and another part it will be flowing through this RO. So, these 2 currents so,
this current and this iout together it is giving the internal current, which is of course, it is
what we call it is unloaded current.
When, I say unloaded current, which means that RL is equal to 0. If, I make this RL is equal
to 0 for a finite value of RO, then we can say that the current flowing here, it will be same
as this one, because the drop across this resistance if this is 0 then this is 0 so, the drop
across this Ro it is 0. So, the current here it will be 0. So, then iout it will be entirely same
as the internal current AI multiplied by iin.
So, again what I said is that this RO represents the practical loading effect in the circuit.
So, if we are having load resistance RL, which is non-zero, then whatever the reduced
current will be seen that reduce current it will be again it can be calculated by considering
this Rout.
So, same thing at the input side the input resistance ideally we want this input resistance
to be 0, but practically when you consider circuit and if we are stimulating the circuit by a
signal current. And, so if I say that this is is and if I directly feed this current to the circuit,
it the internal current iin or the current going to the circuit need not be same as this is, which
means that along with this is.
Practically if it is having some conductance and this conductance either we can call it is
GS the source conductance or we can write in terms of resistance say RS. And, the moment
we connect it here the it is not that entire current it will be flowing here, that is because
this Rin practically it is nonzero.
So, the moment I connect practical value of Rin or nonzero value of this Rin, the current iin
it is coming to the circuit it will be only a fraction of this is. Of course, depending on the
relative value of this RS and Rin, this iin it will be significant part or maybe small part of it,
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but whatever it is this iin it is producing the internal current AI times iin. So, what we have,
what we have seen here, again I am showing in different slide to summarize whatever we
have discussed the about the model.
So, the current amplifier model it is shown here by this dotted line. So, this is what the
current amplifier model. So, this is the model of the current amplifier. And, then as I said
that it is having 3 important parameters namely the unloaded current gain AI, which gives
the internal output current, after multiplying with iin.
Then other element is that RO which is representing the loading effect at the output port
and then Rin, which is representing the loading effect of the circuit, whenever we do have
this nonzero conductance. Namely, RS if it is finite, then whatever the bifurcation it will
be happening that will be getting represented by this Rin.
So, if you look into say this input port the iin it is as I said that it will be. So, we can write
that iin equals to. So, whatever the is we do have multiplied by the this parallel resistance
RS
it is developing the voltage divided by Rin is the current or simply you can say that R .
in +RS
So, we can say at the input we do have the loading effect getting captured by this Rin. So,
likewise at the output whenever we are talking about the output port, at the output port we
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RO
do have the output current i out, it will be internal unloaded voltage AI times iin × R .
O +RL
So, again so, these two important equations they are representing the loading effect.
So, by considering these two loading effects along with this AI you can find what will be
this iout and is relationship. So, in case if we have a circuit which is having multiple stages,
each of the stages if we can break into as current amplifier, then each of these amplifier
stages you can model by this circuit. So, we can have say one current amplifier followed
by another current amplifier and then maybe the primary input and primary output.
So, the output port parameter of the first stage along with the input port parameter of the
next stage together again it will be producing one loading effect. So, everywhere wherever
you are making connection from one stage to another stage or maybe feeding the signal or
you are connecting the load everywhere you will be having the loading effect. And, this
Rin and RO they are playing important role to capture this loading effect. So, that is about
the current amplifier.
So, the as we said that we have discussed about voltage amplifier and then also we have
discussed about the current amplifier and you might have seen that, whenever you are
talking about say current amplifier the signal here it is current, and the signal here it is
current.
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But, there may be a practical situation where we cannot say that signal always be of same
nature. In case say input is say current and output is voltage, then what kind of model will
be using or say, if the input is voltage and output is current then what kind of model we
will be using. So, based on the signal type here, if it is voltage and then current will be
having one kind of amplifier or third kind of amplifier.
And, likewise if I am having the input is input signal is current and then output signal it is
in the voltage form then we will be having the fourth kind of amplifier. So, utilizing this
port nature, namely if the signal here it is current, we are representing this the output port
in the form of not an equivalent circuit on the other hand if it is voltage then we are
representing this by Thevenin equivalent circuit.
So, depending on this signal type either we can have the Norton equivalent or Thevenin
equivalent, but then depending on the signal here the controlling elements it may be current
or voltage. So, based on whether it is current or voltage we can have different parameters
here. So, let us see that the other two types of the amplifiers and their corresponding model.
So, suppose you do have this situation like this. At the input you do have the signal in the
form of voltage and then at the output you do have the signal in the form of current. So, as
the signal at the output it is current. So, we are expecting that the in the model, it should
be not an equivalent is not it. So, we will be having a current source, but then it will not
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be current dependent current source, because the signal here it is a voltage rather it will be
voltage dependent current source.
So, since it is relating the input voltage to output current. So, we call this is conductance
and it is representing mutual relationship from input port to output port. So, we denote this
parameter by capital Gm call Trans conductance, then multiplied by of course, the
corresponding signal. So, what is the signal? It will be vin; vin is the signal appearing at the
input port of the circuit. So, we may call this is vin and the vin is basically the input port
voltage.
And, so since it is not an equivalent to take care of the loading effect as you might have
seen for the current amplifier we like to put one finite conducting element. And, it is
conductance you may write in terms of G conductance or you can for simplicity you can
write the resistance RO. And, at the input again to take care of the loading effect at the
input port we may have a finite input resistance.
So, note that if this Rin is higher it is better, in case if the signal it is in voltage. So, anyway
we do have these three elements; one is the Trans conductance of this amplifier, output
resistance and then input resistance. And, of course, at the input we are feeding the signal
in the form of voltage. And, this voltage source may be having it is finite resistance call
the source resistance Rs and, this is of course, the vs.
And, here again you can see that RS and Rin together it will be creating a potential division
of vs to produce this vin. So, likewise at the output side in case if we are connecting a load
here instead of directly shorting to ground to see the corresponding signal output. So, the
iout here, it will not be entirely this internal current in state there will be some potential
division.
So, there will be potential division or rather I should not say potential current division
between this RO and RL. So, here in this case we can say that iout it will be Gm times vin ×
RO
. So, this is again taking care of the loading effect. So, likewise at the input side the
RO +RL
Rin
vin it will be vs × R .
S +Rin
So, here again we do have this factor to take care of the loading effect. Now, if I combine
these two equation we can find the relationship between this the iout and the vs. So, we can
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say that iout it will be let me use this space iout it will be ok. So, if I replace this part by it is
Rin
expression in terms of vs. So, I do have R × vs . So, that gives us the overall gain of
S +Rin
the circuit capturing the loading effect at both the ports.
So, likewise if the signal if the signal it is at the input port it is say current, if this is current
and this is voltage, then we can again model the circuit and differently of course, but since
the output it will be voltage, then the output port it will be Thevenin equivalent. So, let us
see that model in the next slide.
So, here as I said that the output it is voltage. So, the output port, output port it will be the
Thevenin equivalent. So, we do have Thevenin equivalent. This is dependent voltage
source and also it is having Thevenin equivalent resistance call RO and this dependent
voltage source, it is it depends on the current.
So, what we write here the parameter it is actually it is impedance and since it is correlating
the output port to input port we call Zm mutual impedance or it is called Trans impedance.
And, this Trans impedance multiplied by the whatever the current it will be having at the
input port.
So, iin times Zm it produces a voltage here, which is referred as the unloaded internal
voltage. And, at the input again to take care of the loading effect, we are having finite
resistance call Rin. And, in case if we are connecting say load at the output say RL, the
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voltage here it will be reduced version of this voltage. So, likewise at the input of course,
it is current source. So, we will be having a signal current here say is and it is having a
finite conductance say RS.
So, again this RS and Rin they are providing the loading affected the input port and then
RO it is along with this RL finite value of RL, it is providing the loading effect at the output
port. So, the model what we are seeing here, basically this part is the Trans impedance
model of the Trans impedance amplifier.
So, now we are having 4 basic models or different types of amplifiers based on the signal
type. So, if we are having one amplifier having multiple stages and these stages need not
be only one type of amplifier say for example, this is a voltage amplifier ok. And, then we
do have say Trans conductance amplifier, trans conductance amplifier ok. And, then you
may be having say current amplifier ok and, then we may have say, Trans impedance
amplifier.
Note that while we are connecting it the signals are consistent. So, if you see here since it
is voltage amplifier the volt the produces a signal here in the form of voltage. So, the signal
here it is voltage and the Trans conductance amplifier it is also expecting input as voltage.
So, they are consistent.
And, here the output of the Trans conductance amplifier it is current and I do have current
amplifier. So, the current amplifier is expecting signal in the form of current. So, then there
is no problem. And, here we do have the signal coming from the current amplifier is of
course, in current form and then we do have the Trans impedance amplifier, which is of
course, producing the signal in the form of voltage.
So, we do have here it is the signal it is in the form of voltage final it is coming to the
voltage and it is going through different other modes of signals. So, that is why we can we
may have a chain of amplifiers having each of the stages are of different types of
amplifiers.
Now, the natural question is that, in case if the signal here and signal expected signal to
the next stage if they are not consistent, then what do you do? Luckily each of the stages
they do have their own practical output impedance or output conductance element and you
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can nicely convert the output port model into appropriate model. Namely, Thevenin
equivalent model you can convert into Norton equivalent and vice versa.
So, those kind of after seeing what kind of amplifier it is cascaded to you may have to
adopt those things, but as a individual building blocks, we do have this kind of 4 basic
model they are sufficient. And, each of those models are having primarily 3 elements.
I think, let us summarize what we have discussed in the today’s class. Primarily we have
discussed about the linearization of amplifier, namely simple amplifier and that results to
models or the amplifier. Depending on the signal type we do have voltage amplifier, we
do have current amplifier, Trans conductance amplifier and trans impedance amplifier.
And, each of these types of amplifiers what we are doing is we are simplifying the circuit,
into one equivalent circuit. The circuit is simple enough it is simple enough, but it is also
it is sufficient to capture whatever the information we are looking for. Namely, it
represents the input to output a signal relationship, whether it is voltage gain or current
gain or a Trans conductance and trans impedance particularly in unloaded condition. And,
also it is having the other 2 parameters namely output resistance and input resistance or
maybe output conductance and so, to capture the loading effect when you considered
practical circuit.
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So, I think these models are pretty handy when will whenever we will be having fairly
more complex circuit what we will be doing is that this basic models we have to keep in
mind. So, whenever we do have one amplifier we must always try to translate this circuit
in this form. Namely, whenever we do this amplifier we need to say suppose this is voltage
amplifier, then how do we find the basic three elements, namely the open loop voltage
gains output resistance and input resistance.
So, that will be the exercise we will be performing whenever we will be going to the actual
circuit and converting that into the corresponding model. I think that is all I do have.
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Prof. Pradip Mandal
Lecture - 24
Common Emitter Amplifier (Part A)
Dear students, welcome back to our NPTEL course on Analog Electronic Circuits.
Myself Doctor Pradip Mandal from E and EC Department of IIT Kharagpur. So, today’s
topic of our discussion it is Common Emitter Amplifier. So, this is a basic amplifier and
many of the concepts need to be getting cleared in this amplifier. Some of the prerequisites
we already have covered, which are necessary to understand and appreciate the operation
of the common emitter amplifier. So, according to our overall plan let us see how we are
into the overall plan.
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So, in the overall flow, we are in week 3 and in the previous day we have discussed about
the amplifier models, voltage current amplifier trans-conductance, trans impedance and so
and so. And, then we also have a plan to cover cascading multiple amplifiers, but we will
be covering after we consider some of the practical circuits like common emitter amplifier
and common source amplifier.
So, today’s main discussion here it is the common emitter amplifier and it is a working
principle, biasing scheme, then analysis, may be some part in case if time permits we can
cover some design also today or maybe next day. But, I must say that so far whatever the
topics we have covered namely the device model and then methodology of analyzing non-
linear circuit, then the notion of small signal and large signal model of the BJT and maybe
MOS, those concepts it will be frequently used.
In fact, while we have explained about this small signal model of BJT or MOS. We have
discussed some extent about the operating principle of the CE amplifier. So, we may not
be going detail of or rather we will not be repeating, whatever we have discussed in the
circuit operation, rather our primary focus it will be on biasing and then the corresponding
analysis.
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So, what are the concepts we are going to cover today? It is the we will start with the
operating principle of CE amplifier, but again as I said that we will not be going very deep
into that. And, then main thing is that the biasing of CE amplifier.
In this course primarily we will be covering 2 types of biasing of BJT amplifier; one is
fixed bias and, then subsequently you will see that, what may be a better option. And, then
in the fixed bias CE amplifier we will see that, how we find the operating point and then
how do we get the small signal model and small signal analysis.
And, then we will be covering the what are the issues are there particularly a very common
issue it is called DC operating point is very sensitive to beat our transistor. So, as a result
in case if you are replacing a transistor by another one having different beta then it is
operating point completely gets shifted elsewhere, or in if the beta may not be changing
due to replacing the device it may be due to temperature effect.
And, due to maybe higher temperature beta will increase and then that directly affects the
operating point of the common emitter amplifier. So, that issue we will be discussing and
then we will be giving a pointer what may be a better option or the solution of that problem
ok.
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So, yeah so, what we have the CE amplifier again we will be just touching the basic
operation, but before that I must say that, whenever we call the common emitter amplifier.
the input it is fed at the base of the BJT and then output it is observed at the collector node.
So, you can see that the input we are feeding here and then output we are observing at the
collector node.
And, whenever you are considering signal at the input and output terminals normally, the
signals we are considering in the form of voltage. It is possible to consider input signal in
the form of current as well, so likewise output also can be considered as current ah. So,
this same CE amplifier it may be considered as the current amplifier or trans conductance
amplifier or trans impedance amplifier, depending on our specific interest, but
predominantly unless otherwise it is stated this CE amplifier it is considered as voltage
amplifier.
So, what does it mean is that as I said that both input and output signals are voltage. So,
whatever the analysis will be doing now is basically from considering that the signal will
be will be feeding in the form of voltage. Namely, the signal source resistance thevenin
equivalent resistance we want it should be as small as possible, and while we will be
observing the output we may not be loading the circuit by any you know load at the output
and namely parallel resistance at the output. So, that it need to be taken care.
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And, now let us see how we proceed at the input you can see that the while we are feeding
the signal, it is also accompanying a DC voltage. And, while you are observing the output
this output may be having a DC part as well as the AC part.
So, probably the AC part we can extract we can block the DC by a capacitor or the output,
but typically getting a signal source having an appropriate or having a meaningful DC
voltage is most of the time it is not possible and feasible. So, whatever the input port we
are considering here namely the signal small signal source in series with DC voltage and
that DC voltage should be appropriate for the BJT, may not be you know you should not
be expecting.
So, it is of course, it is having some practical circuit. So, we will be covering we will be
discussing about the practical circuit. And, also the voltage amplifier parameters and any
voltage gain and input resistance, those parameters values are very strong function of the
bias condition or the operating point of the transistors. So, designing one amplifier it is
very important to consider the biasing concepts, how we get the operating point.
So, let us go little detail of that so, in the next slide we will be discussing that, but here as
I say that since you are looking for the circuit as an as a voltage amplifier. Typically, this
is a small signal model of the voltage amplifier right.
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And, as we can see that this is the boundary of the amplifier. it consists of open output
voltage gain AV. Then also it is having output resistance Ro and then the input resistance
of the amplifier, which we have discussed about these three parameters and significance
of these three parameters in voltage amplifier model. And, these three parameters of
course, they are very strong function of the operating point right.
So, this is one important point that while we like to get a voltage amplifier having a good
steady gain, we need to keep the DC operating point appropriate. In addition to that, since
we are feeding the signal here, signal it is voltage. So, at the input the signal it will be
voltage form, which may be having the main equivalent resistance called Rs.
So, likewise at the output while we will be observing the corresponding output, we need
to consider only the signal part. And, when you consider signal it is expected that in case
if we are connecting in any load, this load should not be directly affecting the operating
point of the circuit.
Otherwise, this load may change the operating point and then indirectly they may change
these signal parameters yeah. So, we need to be careful while we are fixing the operating
point of the circuit or the biasing of the circuit need to be properly taken care.
So, what we are considering now practical circuit biasing circuit. So, what we have it is
the requirement wise as I said that the input, we do have signal which is riding over a DC
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voltage. In this case we are calling this is Vbe. So, likewise at the output we do have a DC
voltage, so we need to remove those things.
So, just now what I was telling that the to have meaningful operation of the amplifier, we
need to keep this transistor in active region of operation right; so active region of operation.
So, for that we require a meaningful DC voltage that supposed to bias the base to emitter
junction in forward bias condition.
And, likewise at the output it should be having sufficient DC voltage, so that while at the
output we do have a signal and the instantaneous output voltage should be sufficiently high
even in this critical case, when the signal it is going to the minima. Even then this junction
base to collector junction should remain reverse bias condition. Otherwise, there will be
huge distortion at the output.
So, it is very important that the operating point should remain constant. So, that the gain
should be remaining constant and the second thing is that the DC voltage here should be
appropriate. So, that the base emitter junction is getting forward biased. And, whatever the
bias you do have here for that the DC current, which is DC current collector current
flowing through the transistor, which is incidentally flowing through this RC, then
whatever the voltage we are getting here namely VC, that should be so, this is the VCE that
voltage should be sufficiently high.
So, that while the signal it is riding over that the instantaneous voltage, even in this critical
condition the transistor remains in active region of operation. So, on the what may be the
practical circuit let us look into that. So, as I said that biasing is very important.
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So, let us look into the input port, so what you are talking about the ah whatever the
equivalent circuit we can see here. And, then after that we will see the output port circuit
here.
So, the input port if I consider, here you can see at the input port we do have we do have
this RB, which is connected to base terminal of the transistor, and base to emitter terminal
we do have a diode forward bias diode. So, equivalently I can say that we do have RB in
series with diode. Of course, this diode it will be slightly different kind of normal diode,
namely this junction though it is forward biased, but most of the collector currents are
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coming from the emitter junction. So, as a result the level of current flow here it will be
less.
However, if I consider the current and voltage characteristic of this diode ah; obviously, it
will be having the exponential relationship. So, for this analysis definitely we can consider
this is similar to a normal diode. Now, this diode can be replaced by it is equivalent circuit,
which is shown here, which is having a DC voltage in series with on resistance of the
diode.
The on resistance of the diode here we are representing by rп it is primarily coming from
the П – model of the BJT, but for the time being you can consider it is on resistance of a
diode and this resistance it is very similar.
Now, once you have say supply voltage and this circuit connected the DC voltage coming
here, it is I can say that VBE. So, we can say this DC voltage it is VBE(on) + rп multiplied
by this current, whatever the current we do have here call say IB, IB. And, this IB on the
Vcc – VBE(on)
other hand it can be obtained by considering this loop. So, that is .
RB + rп
Practically this resistance it is very high in the range of few 100s of kilo ohms to maybe
mega ohm. And, rп on the other hand it is very small; it is value it will be in the range of
few kilo ohms only. So, since this is 100s of kilo ohms and this is kilo ohm so, you may
ignore this part then from that you can consider the IB and from that you can find what will
be the DC voltage coming. And, that DC voltage it is this DC voltage.
Note that this base current as well as this rп, typically it is very small. So, this part it may
be very small compared to VBE(on). So, we can say that this DC voltage it is very close to
VBE(on), but slightly higher. So, once we have the DC voltage obtain there next thing is that
the capacitor ah it is helping for the signal to feed in.
So, we do have this coupling capacitor, signal coupling capacitor, which is coming from
in the original circuit there. And so, this signal; signal frequency we assume that it is
sufficiently high compared to the cut-off frequency defined by this C and the equivalent
resistance coming there, or you may say that the value of this capacitor it is sufficiently
large, so that the signal it is directly coming to this point.
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So, at this point if you observe the voltage, instantaneous voltage it is having a DC on top
of that it is having the small signal. So, it is equivalently it is making a small signal riding
over the DC voltage; So, it is riding over the DC voltage.
So, earlier we are having this simple stimulus at the base ah, but of course, it is an ideal ah
model. Practically, this is how it is obtained by combination of this RB and C, we are
getting a voltage here which is having a meaningful DC and on top of that we are
successfully feeding the small signal ok.
So, we will be seeing that what may be the equivalent circuit of this one later where small
signal equivalent circuit, where we may short this capacitor and then this DC voltage you
can consider it is the AC ground, and then this DC voltage you can drop. So, for AC signal
will be practically will be having this RB and this rп and then this signal it is also coming.
Since, we are not considering any Thevenin equivalent resistance here this resistance it is
0. So, as a result this voltage it will be for AC signal it will be directly Vc. So, just now
what I said is that for this is the total signal total circuit and for small signal on the other
hand at the base, we do have only the vs coming there and then this is the base node. And,
at the base node we will be having this corresponding rп which is connected to ground.
And, then of course, we do have the RB; RB also there, but since this RB as I said it is very
high, we may ignore. And, then we do have the DC voltage here which is of course, the ac
ground. And, so, that is what the voltage it is coming to the base terminal.
In case if we have a; so, the signal here it will be across this rп it will be same as vs, but in
case if I consider a practical source resistance say Rs, then of course, the voltage here it
will be slightly different. So, in that case these two resistances we can map into equivalent
input resistance together and these two together practically it is coming rп only and then
this rп. So, this rп it is and then Rs they will define what is the voltage coming here from
the signal source.
So, to further conclude what will be having at the base, we do have for small signal at the
base will be having the vs having a source resistance Rs. And, then the base to ground node
resistance, this resistance it is it is parallel connection of RB and rп, but we can say this is
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rп. So, this model will be using whenever we will be talking about the small signal analysis.
So, at the base that is the equivalent circuit we do have at this point.
Now, let us look into the output port of the circuit, let draw the corresponding the
equivalent circuit. To start with we will be going for the large signal first and when you
consider large signal this IB whatever the IB it will be flowing here, after multiplying with
βF we do have IC here. So, this IC it is coming from this IB after multiplying with βF.
So, we have to be we are assuming that this circuit once it is decided. Next thing is that so,
which means that the IC it is also getting decided, then we can see what is the corresponding
voltage coming here. So, let us look into the output port in the next slide.
So, at the output port what we are expecting that voltage here it will be like this it is shown
here, it is having a DC voltage called say VCE incidentally, this is CE or you may call this
is VOUT. So, this level we can say VOUT on top of that we do have the small signal. So, we
do have the small signal here.
So, now this small signal of course, we can extract by as I said by placing this capacitor.
So, we will see that part, but initially the DC part, what we have it is we do have Rc
connected to Vcc and then we do have the collector to emitter voltage. So, we do have the
sorry collector to emitter current Ic. So, this Ic it may be having both DC part. So, this Ic
may be having 2 currents; one is DC part IC. And, then also the small signal part, ic right.
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Then this IC as I said that it is β times IC whereas, the small signal part here whatever the
small signal we are seeing here, this is also β × ib. So, this β it is slightly different from βF
it is called large signal beta in forward direction, this is called a small signal current gain
beta, but practically we may consider both are equivalent, but you need to be careful there
they are not exactly same. On the other hand the small signal current here it is this β × ib
vs
and this ib it is essentially it is coming from the .
rπ
So, we will see this it is shown, but just to see that the current flow here it is having DC
component and the small signal component, then we do have if I consider the voltage at
this point. So, voltage at this point we do have DC part, it is generated by this DC current
RC and Vcc. So, we do have this VOUT, just now what we said is VOUT, which is Vcc – RC×IC,
which is of course, β × IB. In addition to that we also have ah small signal part so, we may
call small vout.
So, what is that it is for that small signal this is ground and so, we can say this is ground
and the ic current is flowing here. So, we may say that this is minus Rc × ic and this ic as I
said that this is β times ib and on the other hand this part it is βF times IB ok.
So, now we do have both the DC part and the AC part together that gives us this signal,
so, instantaneous signal. Now, by placing the capacitor here, by placing this capacitor here
we are removing this DC part and at the output what we see it is only this part.
So, if you are observing the signal here what we will see that it is a small signal with
respect to ground; so, with respect to ground. And, we call this is vout right. Now, if I
combine this information together we can get the small signal equivalent circuit.
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So, in the next slide we can look into the corresponding small signal side equivalent circuit.
But let me take a break and then we will be discussing in detail on this one.
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Prof. Pradip Mandal
Lecture - 25
Common Emitter Amplifier (Part B)
Welcome back after the short break.
So, we are discussing about the CE amplifier, then we are close to the small signal
equivalent circuit. So, large signal analysis we have done and based on the large signal
analysis, what we said is the DC voltage here it is fixed.
So, whenever we are going for small signal, first thing is that we will be considering this
DC part is 0. And so, we can say that this is AC ground; of course, we do have this ground.
Then next thing is that these capacitors are working as a short and whatever the circuit will
be having, it is now that we will call the equivalent circuit.
In addition to that base to emitter, we are also having one Vbe on internal DC voltage that
also need to be met 0. So, base to emitter what we have it is the rп. We do have this rп,
then we do have the signal coming here. So, we do have the signal directly coming here.
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Along with this rп of course, we do have RB and this is connected to ac ground which
means that this RB and this rп, they are coming in parallel and typically this resistance is
very high compared to this one. So, we may ignore this part, we can simply consider this
rп.
And the on the other hand the collector side so, this is the base node, this is the collector
side ah. At the collector side, we do have RC which is connected to Vcc which is now ac
ground. So, this is ac ground I am using red color ground here just to indicate that this is
valid for ac signal only.
And then from collector to emitter we do have the current this IC current, but here again,
here it is having the DC part as well as the small signal part. So, we should say that DC
part we are dropping it and what we have it is only the small signal part IC.
So, this IC equals to beta into ib and the ib it is whatever the current it is flowing from the
vs
signal source into the base. So, this ib if you see here this ib, it is this is . So, this is what
rπ
the ib. Now that ib it is after multiplying with beta, beta naught it is giving us the on the
small signal collector current.
That current is flowing through this resistance which is producing a voltage and for it may
be noted that the signal here though it can go positive and negative, but for correct polarity
and consistency of the input to output signal phases, we need to put a sign.
Say for example, here whenever you are talking about base to emitter voltage, this is signal
voltage it can go plus and minus, but then we are putting plus sign here and minus sign
here; same thing for polarity of the ib. So, we are considering this is the positive direction
of the base current.
Likewise, whenever we do have the collector current, this is the positive direction of the
collector current with respect to that if the collector current is flowing in this direction the
developed voltage here it will be this will be minus and this is plus. So, the voltage coming
at this point it is minus Rc multiplied by this ic in. So, that is – Rcβ0 × ib. Further to that we
vs
can write this as – Rcβ0 × ib it is .
rπ
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So, that is what the vout. So, we can say that this vout expression is this given here. So, this
vout expression it is given here. So, from that I can say that vout, I should use this is small
vout Rc ×β0
vout. = − . So in fact, this is nothing, but our voltage gain.
vs rπ
In small signal model, if we map this equivalent circuit into voltage amplifier small signal
voltage amplifier, then this is representing as the voltage gain Av. So, we will see that again
this Av, but its expression it is given here. Now this small signal equivalent circuit it may
be having two ways of representing. The first one just now we are discussing, the other
one it is again similar only difference is that let me use a different color to consider that
this ic instead of writing in terms of ib. Let me use blue color.
vbe
So, instead of using ib we can write ic equals to. In fact, we can write β0 ib it is all right.
rπ
And so, this vbe divided by rп this parameter, it is of course, it is a small signal parameter
we already have discussed earlier. This is gm trans conductance of the transistor multiplied
by then this vbe. So, this part it is basically the trans conductance of the amplifier. So, in
this red color what you have done is that this current, we are writing in terms of ib which
means that this current source it is current dependent current source.
On the other hand, if I you say, this model then this is voltage dependent current source
right. So, this v be it is defining this the current. And then the remaining things; however,
it remains same namely the output voltage here, it is – Rc×ic and instead of writing –β×i0,
now I can write this as – Rcβ0 – Rc×gm×vbe and incidentally this vbe, it is same as vs. So,
we can write this as – Rcgm×vs.
Again this is representing the same vout and with this we can say that vout divided by vs
equals to –gm×Rc. This is again the expression of the voltage gain if we are representing
this whole circuit as equivalent voltage amplifier.
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So, I should say that this circuit we do have while we are mapping this circuit in the form
of small signal equivalent circuit, there are so, this circuit whole circuit we are mapping in
this form and it is having two ways of writing this small signal ic here; one is in terms of
gmvbe the other one it is beta times ib.
Now, if we are mapping this circuit in the form of voltage amplifier, we prefer this
expression over this one that is because then input we are considering it is input signal we
are considering as voltage rather than current. So, maybe in other model while we are
considering say the same CE amplifier as current gain current amplifier or maybe
impedance amplifier, then we may use say the other model here.
So, if I use say this current source as gm×vbe, whatever we will be getting it is equivalent I
should say that will be the input signal it is the voltage. Now if I consider this output as
voltage; obviously, then this current source along with this Rc, we need to translate this
circuit in the form of Thevenin equivalent.
So, once we translate this into Thevenin equivalent model, then only we will be getting
the output port as voltage source and we need to map into this normal model the known
model which is Av times vin and in this case vin it is basically the vbe. And then we do have
the output resistance and incidentally this output resistance and this output resistance they
are same ok.
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So, now, if we map this small signal equivalent circuit into a voltage amplifier, what we
are getting it is the following.
So, we are discussing about this small signal model. And now if we translate this model in
the form of voltage amplifier, what is the voltage amplifier will be getting it is voltage
dependent voltage source at the output port and then we do have the output resistance Ro.
So, voltage dependent voltage source it is Av times the input port voltage
In this case vin it is vbe. So, this is plus and this is minus this is connected to ground and
then at the input we do have the a rп. So, the input resistance is rп of the transistor and at
the across this rп, we do have the vbe voltage. So, this is plus and this is minus indicating
if this is plus and this is minus the corresponding voltage here this should be in phase.
However, we already have discussed that expression of this A expression of the A, it is –

gm×Rc or we also have said that in terms of current. So, for the timing let me stick to this
one forget about this one and then output resistance it is same as the Rc.
So, this circuit whatever the circuit, we have discussed here small signal equivalent circuit
we can map into this model the voltage amplifier model. Having this three important
parameter AV, output resistance and then input resistance here. So, this is input resistances
rп
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And at the input of course, we are giving the signal with a 0 voltage here and at the output
we are getting the signal all right. So, that is about the how we are mapping the circuit into
voltage amplifier. Note that this model, it is valid for low frequency as well as in the mid
range frequency.
However, if you go to higher and higher frequency, then this device may be having this
device may be having its own parasitic capacitances from base to collector it may be
having one capacitance and then base to collector it is having another capacitance. So, base
to collector capacitance, it is referred as CП and then we do have the Cµ.
These are essentially small signal capacitance associated with the BJT. So, if we are
considering small signal equivalent circuit and particularly in the high frequency range,
then this capacitor and then this capacitor they are again popping up and we need to
consider them. So, we need to consider this CП and then Cµ ok.
Then of course, we can consider their equivalent circuit here which is having the CП and
then Cµ. Note that Cµ need to be connected to this point not this point ok. So, in addition
to that I must say that so far, we are ignoring the early voltage effect namely the
dependency of the collector current on the Vce we are ignoring.
But in case if we want to consider whatever the dependency, it is having slight whatever
positive slope in the active region and this slope will be represented by finite conductance
∂Ic
called g0 which is defined as .
∂Vce
And this is called small signal reciprocal of small signal output resistance ro. So, if you
consider this resistance or this finite slope, what will be getting here it is that one resistance
here which is either you can write in the form of conductance or resistance ro and so, this
resistance since it is coming in parallel with RC.
And as this is connected to ground, this is also connected to ground. So, the output
resistance RO, it will be rather RC⫽ro. So, this represents the complete model of the CE
amplifier small signal model of the CE amplifier which is valid for low frequency as well
as high frequency. And of course, in the low frequency region ah, then the CП and Cµ they
are effected to be very negligible and also this typically this ro it is quite high compared to
Rc. So, we may still consider this is Rc.
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But once we replace this passive element by active element which may be having output
resistance comparable with this and then we must have to consider this ro.
So, to avoid this so much of clumsy things, let me go to the next slide where I have the
clear diagram of the small signal model. So, what we have as I said that the in the small
signal model we do have rп and then RC which is the output resistance and so and so, and
then we do have this resistance this capacitance and this capacitance, they are getting added
up and also to take care of the early voltage effect we do have ro.
So, this small signal model, it is referred as high frequency a small signal equivalent circuit
of the CE amplifier. So, this derivation we already have said. So, nothing to discuss about
that and in case I must say one thing, I must add one thing that this in case the source
resistance is having source signal source is having source resistance Rs, then this voltage
need not be same as this one.
So, then we may have to consider this Rs and then rп to consider this voltage and once you
go to higher and higher frequency this Rs in combination with rп and then CП also effect
of Cµ, you may call it as equivalent input capacitance all of them are going to contribute
to define the cutoff frequency of the amplifier.
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So, this capacitor are they will be playing important role to define the bandwidth of the
circuit. So, whenever the situation comes, we will discuss that in detail. Now let us see or
lest let me highlight one issue of this fixed bias CE amplifier is having particularly the
operating point it is sensitive to beta of the transistor.
So, then to let me use a different slide to discuss that point. Sensitivity of operating point
as I said sensitivity of operating point of the CE amplifier particularly if it is fixed bias.
So, if it is fixed bias namely the IB, it if it is decided by this RB and Vbe one and Vcc then
the collector current IC which is beta times IB.
So, as a result if I fix this IB and then if I replace this transistor by another one having
different value of this βF, definitely the corresponding IC, it will be getting changed. So,
what will be the consequence? To explain that, let me go back to our previous method of
finding operating point of the circuit. So, where do we is to draw this IC Vs. VCE. So, we
used to draw IC Vs. VCE characteristic curve for a given value of IB.
So, IB it is fixed and then also we do, we used to draw the load line. So, is to draw the load
line defined by this RC and VCC. So, this node this point it is VCC and so, these two together
it was giving the operating point there.
Now typically we like to avoid of course, this point as well as the saturation point and
whenever it is to give a signal here, we are adding the IB as a result this total IB, we are
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expecting that if the signal is present, then it will be going up and down like this one. And
as a result this the crossing point of the device characteristic and the load line they used
to, it is to move from here to here and as a result it was products in the output voltage.
So, if this operating point is properly set, then if the in presence of IB the IC maybe it is
changing over this range and this the meeting point, it was shifting from this point to this
point and as a result it was giving the output signal.
And to get a very good swing we want this operating point should be middle of this range.
What is this range, which is defined by upper side it is defined by supply voltage VCC and
lower side it is defined by the limit of the active region which is referred as VCE set; VCE
set saturation.
So, we like to keep this operating point middle. So, that both the lower as well as the upper
swing of the signal is to get a good one. Now if you see that in case suppose, we are fixing
this RB which is deciding this ib and then if you replace this transistor having different
beta. So, then what it be it would be happening is that this line for the same IB because of
different beta it may be getting shifted here.
So, this beta if it is say βF2 from βF1, then the Q–point, now it is getting shifted from here
to here. And if the Q–point it is coming here; obviously, the signal swing if you see this
side it will be very much limited. This side it may be getting extended, but since this lower
side it is getting limited, then if you apply the signal the signal limit it will be decided by
the lower one out of these two limits.
So, as a result if the beta is getting changed from the previous value to this new one, the
IC characteristic it is getting shifted here. And then the operating point since it is coming
here so, that may create the signal and getting distorted towards the lower side. So, if you
still continue giving the same amplitude signal for this operating point so, what we are
expecting that, then the corresponding output signal let me draw here. It will be getting
huge distortion and this side it may be like this.
So, this distortion of course, for analog circuit it is not acceptable. So, that creates the main
problem the change of this beta, it may be due to various region. In case if you want to
replace this transistor by another one and you do not know the beta, then it may create
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problem and to get the same value of the beta using which you have obtained this operating
point may not be practically a good solution.
The other problem is which is the typical problem, it is that this beta it is a strong function
of temperature. So, in case if the junction temperature of this BJT is increasing this beta,
it may increase as a result this operating point it may be going up there. And that may
affect the Q–point operating point of the circuit drastically which is referred as thermal
runaway problem.
Why is it called runaway problem? If IC it is increasing due to increase of beta maybe that
is due to originally due to increase of temperature and if the IC is increasing and then that
may increase the power dissipation of the in the junction and that may further increase the
temperature and then that may lead to again increase the beta. As a result, it is having
cumulative effect to increase the beta and on this Q–point of the circuit it may it may go
towards the saturation limit or active region limit.
So, this problem can be as I said that this is a problem which is referred as the thermal run
away problem for CE amplifier particularly if it is fixed bias. So, what is the solution for
this is we can add a series resistor at the emitter. So, if you add one series resistor called
RE and then instead of fixing this current probably we can try to fix the voltage here by
different means and then we can then we will be seeing that the operating point will be
having a better stability.
So, that gives us something called from now voltage bias with emitter degenerated. So,
this RE it is referred as emitter degenerated which desensitize the operating point of the
circuit, but of course, will be discussing the topic later. But since we are desensitizing the
circuit by placing this RE that will that also an affect the gain of the circuit. Now to get
back the gain, we need to connect one bypass capacitor.
So, this is this will be discussed in the next day, but just to give a hint that yes CE amplifier
with fixed bias it is one good amplifier, but it is having this issue need to be addressed
differently and we will see that how this node it will be biased in the form of voltage
namely by using a potential divider, those things will be covered in the next class.
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So, what we have discussed today let me summarize. We have started with simple
operation of the CE amplifier rather earlier whatever the knowledge we already have
gathered that we have discussed. And then we have discussed the biasing of the CE
amplifier namely how we define the operating point of the circuit by connecting a base
resistor called fixed bias resistor RB at the base.
And then we put a DC decoupling capacitor to feed the signal. So, in combination with RB
and a capacitor C called coupling capacitor CC to feed the signal, we obtain the appropriate
arrangement of the circuit. And then we have analyzed the operating point little detail by
considering the input port situation and then output port situation for large signal and then
we have discussed about the small signal equivalent circuit.
And then we map that equivalent circuit into a voltage amplifier. At least as I said that
typically CE amplifier it is considered as a voltage amplifier. So, that is what we have
done. We have mapped into voltage amplifier.
And then finally, we have discussed about the issue for which is existing for fixed by a CE
amplifier namely the operating point is sensitive to beta of the transistor and that will be
that need to be addressed by different means. So, that will be our next topic of our
discussion. I think we are end of it.
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372
Prof. Pradip Mandal
Lecture - 26
Common Emitter Amplifier (contd.)
(Part A)
We are going to continue our previous topic namely the Common Emitter Amplifier, we
have started this topic in the previous class and we are going to continue the same thing.
In the previous class, we have discussed the CE amplifier with fixed bias. And, today we
will be going little detail of another kind of bias called self-bias and in the previous
discussion we already have cleared that fixed bias it is having some stability issue,
particularly the operating point stability issue which is resolved by this self-biasing that
is what we will be discussing in detail.
Then subsequently we will be discussing the self-biased CE amplifier and then its
corresponding analysis having two parts. One is the DC operating point analysis and then
small signal analysis which is eventually giving us small signal equivalent circuit of CE
amplifier having self-bias. And, then subsequently we will be talking about the mapping
of the small signal equivalent circuit of CE amplifier on a voltage amplifier.
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Typical voltage amplifier is having three important parameters; how those parameters
can be obtained in the small signal equivalent circuit as a methodology we will be
discussing as well as this example. Subsequently, we will be discussing two numerical
examples. So, under the numerical examples we will be having analysis for a given
design, we will do the analysis to find the numerical value of gain and operating point.
And, then we will be giving some design guidelines for achieving some performance of
an amplifier. So, this is what we will be covering today. So, let us talk about the biasing
scheme and then let me compare the two biasing schemes.
So, as we have discussed this is the fixed bias kind of circuit and here what we have done
it is the base terminal current particularly the DC current IB it is decided by the VCC and
then VBE(on) and this RB. So, in fixed bias circuit the base current is well defined by the
base resistor called RB and then supply voltage minus base to emitter diode on voltage.
So, this base current is defined and that is fixed then the corresponding collector current
of the transistor can be obtained by simply multiplying this IB with the βF of the
transistor. Since IC is a direct function of the βF; there may be a situation, in case if the β
of the transistor is changing then the collector current directly getting affected.
If the collector current gets affect then drop across this resistance as a result the collector
to emitter voltage of the transistor that may vary. So, we can say that operating point of
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the transistor was getting heavily affected by variation of the β of the transistor. In
contrast to that we are going to discuss about this circuit which is referred as self-bias.
This emitter resistor we are connecting in series with emitter to the ground. And, on the
other hand at the base we prefer to give a DC voltage rather of course, we do not want
from this voltage should be ideally a DC voltage because we like to feed the signal here.
So, but then the DC voltage here we want predominantly define in other words we want
Thevenin equivalent resistance of this bias circuit should be as small as possible in terms
of the bias stability. So, even if we consider practical value of RBB is much smaller than
whatever RB we do have.
We can say that the RBB in the self-based circuit is much smaller than the RB of the fixed
bias circuit. So, we can say that even the base current is flowing through this circuit; the
drop across this RBB is very small. As a result, we may say that this voltage is
approximately VBB.
So, VBB – VBE(on) divided by the whatever this RE that defines the current flow here. So,
in other words we can say that this emitter current IE in the self-biased circuit it is
defined by this voltage difference and then divided by RE. So, IE is independent quote
and unquote independent of this the β of the transistor. So, naturally the collector current
is also quote and unquote independent of the βF. So, in this circuit in the self-bias circuit
in contrast to the fixed bias the emitter current is . If the β is very high we can
approximate that the collector current is very close to that.
So, in this expression since β is not there; so, we can say that the collector current is
quote and unquote independent of β of the transistor so, that is the main purpose here. In
other words, so, based on our requirement if we fix the value of this RE and then VBB
assuming that RBB is very small, then the collector current it is almost decided. As a
result, the DC operating point of the transistor it is almost fixed. So, that is the main
advantage here. So, let us see what may be the analysis of this circuit to compare these
two circuits performance.
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In fact, if you see it carefully VBB you may consider as a special case; it is VCC and RBB it
is similar to RB. However, as I said that in this circuit RBB is much smaller than RB and
that can be obtained because we are adding this emitter resistor RE. In contrast to, this
circuit where emitter is connected to ground. So, we have the flexibility to change this
voltage and predominantly we can say that this circuit is more like a voltage bias rather
than current bias what we are seeing in the fixed circuit.
But, nevertheless we may consider that this circuit is more generalized and the self-bias
circuit may be treated as a special case where you may say that RE is going to 0. And,
then VBB is going to be equal to VCC and whatever the RB is there. So, to compare the
expression of the collector current in the two circuits probably we can analyze the circuit
and we can find the expression of IC.
And, then we can probably through equation we can compare the collector current
expression in the two circuits. Namely, in the fixed bias circuit; the collector current will
be having lot of dependency on the β of the transistor whereas, for self-bias circuit the
dependency it will be less. So, let us see the analysis of this circuit here. So, in the next
slide we are going to analyze this circuit in detail.
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We have the same circuit we have discussed so far. Here, we have the main transistor,
which is biased by VBB and then RBB. At the emitter, we have RE resistor and of course,
we have the signal coming through this capacitor and then at the output we are observing
through the capacitor. Moreover, we have the resistor at the collector terminal.
Now, if we want to know the DC operating point stability for this circuit, now we can
concentrate the DC part by ignoring the signal part. So, if we consider this loop, at the
base to emitter what we can get the expression of the VBB = VBE(on) + RBB IB + RE IE.
And the emitter current we are writing in terms of base current which is (β IB + IB). So,
this is the emitter current so the drop across this resistance is RE × IE. Now, if we
rearrange this equation to find the expression of IB in terms of VBB and βF; so from this
equation we can get the expression of IB = .
Now, from that we can find the expression of the collector current, collector current is
βIB. So, this expression is same as we have the multiplication factor βF. Now, to find the
sensitivity of this collector current on the β variation what we can do?
We can take partial derivative of this equation with respect to β. So, if we say that ,
assuming that this factor, is having practically no dependency on the β variation. In fact,
strictly speaking β is having influence on VBE, but if we consider the change in VBB ‒
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VBE practically the variation is very small. With this assumption considering this factor is
quote and unquote independent of the β. So, we can take this factor out and rest of the
things we can take the partial derivative. So, as you can see that, this factor it is coming
in the form of square here in the denominator and then in the numerator we have β.
Finally, we get = [{ }
].
If we try to get the engineering meaning of that, what we can rewrite this equation by
considering this factor into the left side. So, instead of ∂IC we are writing here it is
change in IC by IC which means fractional change in collector current divided by
fractional change in β.
So, this ratio if we consider its expression it is (RBB + RE) in the numerator and in the
denominator we have (RBB + (1 + βF) RE). Now, interestingly the same equation can be
used to find the sensitivity of the common emitter amplifier on operating point on β
variation for both fixed bias. So, if we consider fixed bias we can consider RE = 0.
So, RE if we take it is 0 for fixed bias and then what we are getting here it is, this
expression it is becoming . That means then the sensitivity is becoming 1; which
means that whatever the percentage variation we have in β same amount of percentage
variation is expected in the collector current.
On the other hand, if we consider say the emitter degenerated bias by putting this RE
non-zero and then if we consider that this part it is much higher than RBB. In that case, RE
is having some finite value. Moreover, if we consider this part is very high compared to
RBB. So, this becomes .
In addition, if we further simplify by considering this RE which is higher than RBB so that
is becoming equal to . Which means that whatever the fractional change you do
have in β, that is getting reduced by this factor almost times factor to get reflected in
the fractional variation in collector current.
That is the theoretical basis. If you put the emitter resistor and if you consider that RBB is
much smaller than (1 + β) RE. And also, if we consider RBB it is also less than RE then we
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get the advantage. And, typically for self-bias, what we do? It is we do take RBB ≤ ⅒ (1
+ β) RE to get meaningful effect on the bias point stability by placing this RE.
This is the practical circuit. Here, instead of independent voltage at the bias voltage at the
base we have here it is potential divider from . So, the voltage coming here if I
consider Thevenin equivalent voltage source of this one along with the VCC what we can
get is VBB it becomes .
And, the Thevenin equivalent resistance RBB we have drawn in the previous circuit. RBB
is parallel connection of R1 and R2 or . So, this is the practical implementation of
this self-bias and of course we have the RE part emitter resistor.
Typically, this circuit is quite popular and we use this emitter resistor to avoid the
thermal runaway problem or the dependency of the coefficient point on the β. Now, in
this circuit similar to fixed bias the voltage at this point is having a DC voltage defined
by this R1 and R2 and then VCC. Practically, this VBB is defining this DC voltage and then
on top of that we are feeding the AC signal through this coupling capacitor. So, we have
the AC signal riding over there. So, the voltage here it is having a DC voltage and then
on top of that we have the signal.
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Now, at the output similar to the previous case; is having a DC voltage level. So, this DC
voltage level at this point particularly having the drop across this RE plus whatever the
VC voltage you have or we may say that VCC minus the drop across this resistance that
gives this DC voltage. So, we can say this DC voltage is VCC – RC × IC. And, then to get
the IC we have discussed that once this voltage is given here then that minus VBE(on). So,
that divided by RE gives the emitter current and that actually gives the approximately the
collector current. So, IC ≈ . So, approximately that is the emitter current. So,
that is how we are getting DC voltage and once we have the AC signal at the base
coming from the signal source naturally this is also having the small signal current ic
along with the DC current.
As a result it is also producing a drop across this resistance and hence we have the signal
at the output. Only thing is that since we are subtracting from the DC voltage this drop
across the RC we are subtracting from the VCC. So, the signal here it is having 180-degree
phase difference with respect to whatever the signal we have. So, in this circuit let me go
a little detail of analyzing the input part and the output part.
So, if I consider input port is this one DC wise, in addition to that we have the signal.
And, the output port on the other hand consist of on the collector resistor, transistor and
also this emitter resistor. So, you need to see that this emitter resistor is part of the input
port as well as the output port.
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So, in the input port while we will be analyzing we need to be careful whenever we will
be talking about the IB current; we need to see how much the current actually is flowing.
In fact, the current here is not only IB but also the IC. So, whenever we are writing say IB
here the current here it will is (1+β)IB; so, that we need to be careful.
At the input port we have RBB = R1 ⫽ R2 and VBB is the voltage Thevenin equivalent
coming from VCC , R1 and R2 together. So, VBB = . From base to emitter we
have the base-emitter diode and at the emitter node we are having this emitter resistor.
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At the emitter of course, we have the additional current flowing into this. So, whenever
we will be talking about IB it is flowing here, we need to consider that IC also which is
β∙IB as a result the current flowing through this part it is (1+β) IB. Now, if I replace this
base-emitter diode by its equivalent circuit shown here. So, which is parallel connection
of the VBE(on) voltage and then rπ and again this node we need to consider that collector
current is coming here which is β∙IB.
If we analyze this circuit we can get here = IB∙(RBB + rп) + IB∙(1 + β )∙RE.
So, in this case we may or may not be able to ignore this rп in this case. So, we may have
to consider this entire portion. But if we consider say drop across these two resistances;
since RBB is much smaller than the RE part we get IB = .
And, once we get this βIB then the collector current is IC = βF × IB. We can approximate
IB as and then whole thing multiplied by βF. So, we may ignore this one
part and then we may cancel this part and this part. So, that gives us the collector current
is independent of βF; so, that is what again we are converging to the same point. So, that
is what we do, the input port we do this large signal analysis. Only thing as I said that we
need to be careful that this RE it is also taking the current of the output port. From this
circuit after getting the large signal current probably we can do the small signal analysis.
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For small signal analysis, we have to make it AC ground, we have to drop this part and
then we have to short it. So, we have a signal source shorted to the base node. Then we
have the AC ground and then we can keep this rп and then we have RE, but again we
need to be careful that we also have the collector current to be considered.
Collector current is IC that is also flowing to this RE. So, if we say this current we do
have say small ib. So, collector current is β0∙ib. As a result (1 + β0) ∙ ib × RE; so, that is the
drop. So, probably you may drop this current source, and then instead you may simply
say this resistor is getting multiplied by (1 + βo) of the transistor. You may forget about
this part, you may say that resistance is getting increased.
But, whatever the way you feel we need to be careful that we need to consider this
collector current or probably the emitter resistor we need to consider its amplified
version of the emitter resistor. Now, this vs is coming here and is going to the base
terminal. Note that, vs it is not same as VBE as it was for fixed bias. The base to emitter
voltage is different from this vs.
Now, let us look into the output side. So, whenever we will be talking about the small
signal equivalent circuit, we must consider this analysis. So, while will be going to the
small signal equivalent circuit for the entire common emitter amplifier then we have to
consider this circuit. But for the time being let we consider the output port. And, again
for this output port what we have emitter resistor it is common.
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So, let me go to the; so, here again we do have the large signal and a small signal notion.
And, here we do have the; here we do have the actual circuit and at this point we do have
the voltage shown here and we are going to talk about at this circuit along with this DC
decoupling capacitor.
So, what we have at the collector? We do have the R C, collector resistor connected to
the VCC and then collector to emitter we do have the current. And if it is of course, it is
having a DC current IC plus in case if it is having small signal small ic also.
But, whatever it is this entire current it is flowing through this emitter resistor and in
addition to that at this node the base current is also coming. However, this base current it
is small compared to this collector current. So, we may or may not ignore this part that
we can see, but that this is what the output port.
And, once to find the DC operating point one say IC it is known by analyzing the input
port then you can say that current is flowing here. And, the DC voltage coming here
which is VCC – RC × IC; so, that is the DC voltage. So, the voltage at the output node or
the collector node rather it is VCC minus this drop; so, this is VCC – RC × IC. Now, once
you obtain the DC voltage here let us look into the small signal part.
And similar to the input port here again for small signal what are the things we will be
doing, it is this terminal will be will be considering AC ground. This is AC ground and
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here the DC part will be removed. So, though it is having total current is (IC + ic), but this
will be dropped and whatever the current will be flowing through this one it is only ic; so,
this is also ic. And, the corresponding capacitor here of course, it will be getting shorted.
So, whatever the small signal voltage you are getting that will be called small signal
output voltage, while we are dropping this DC part. So, if I draw the small signal
equivalent circuit, we have the RC connected to AC ground and then we have the small
signal current, ic. At the emitter we have the RE maybe we can think of the base current
coming here ib and then at the output we can say this is the open circuit output signal.
So, this ic of course, we may be having a different expression. One of them it is ic equals
to transconductance of the transistor multiplied by base to emitter voltage and since this
is ideal current source; so, to find this output voltage we may prefer to see how much the
drop across this resistor is appearing while small signal current ic is flowing.
So, the output voltage at this point rather signal is – ic × RC which is of course, this is
equal to – gm × vbe × RC. So, while we will be combining this small signal equivalent
circuit at the output port and small signal equivalent circuit at the input port, then we can
get the combined small signal equivalent circuit.
So, let us see what you are going to get. So, we have this small signal equivalent circuit
shown here, where if you see at the collector side we are making AC ground. The
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capacitor here we are shorting; so, that is what we are doing and then the collector
current is having only the small signal collector current, ic which is gm∙vbe.
And, the vbe is the voltage drop between the base terminal and the emitter terminal. So,
this is the voltage drop across rп. So, the voltage coming at this point in this circuit since
we are eliminating the DC we have plus and minus kind of signal and the output we are
removing the DC.
So, we are getting only the signal part and in this illustration as I said that the signal here
is in opposite phase of the input signal that is because of the voltage coming here is – RC
× gm × vbe. Now, if you see here this vbe of course, it is not same as vs; so, this is not vs.
So, since the vbe it is not same as vs, it is rather only a part of it we need to do the detailed
analysis of the circuit. Now, we are going to take a small break. After we come back, we
need to find what will be the relationship between this vbe and the vs. So, vbe as function
of vs and while we will be doing this we may use this important relation that this ic we
may say that this is gm × vbe or, we may say that this is β∙ib.
386
Prof. Pradip Mandal
Lecture - 27
Common Emitter Amplifier (Contd.) (Part B)
So, welcome back after the short break. So, where we are discussing? We are talking about
the small signal equivalent circuit and then we are trying to find the corresponding gain of
the circuit.
So, the output voltage as I said that output voltage, it is this one. So, vout = – gm × RC × vbe.
Now, this vbe of course, it is function of vs, but we need to find what is the exact expression
of that. So, let me erase whatever the scribbling I have done and start afresh again drop
across this RE which is RE times (1 + β) times ib.
On the other hand, this ib it is; ib it is it can be expressed in terms of vbe and rп alright. So,
vbe β
we can write this as again vbe + RE × (1 + β ) times . In fact, if you see here it is
rπ rπ
nothing, but gm. So, if we drop this 1 and then if we consider this is equal to beta
approximately divided by rп so, this part it becomes gm. So, we can further simplify I am
saying that this is vbe + RE × gm × vbe. In other words, we may say that vbe equals to divided
by 1 + gm × RE.
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So, interestingly depending on the value of this RE, we can see that vbe it is rather a small
fraction of vs. Whatever it is this output voltage we said equals to – gm × RC × vbe. So, that
vs
becomes – gm RC × .
1+gm RE
So, as a result if I say that what is the gain of this circuit starting from primary source to
g Rc
the primary output, we can say the voltage gain Av = − 1+gm R . So, this is one important
m E
parameter of the voltage amplifier out of this circuit.
Now of course, we will be talking about its numerical value and all. But if we; if we recall
the if it is fixed by a circuit the expression of the voltage gain, it was only this much. Now,
we do have additional factor here which is in fact, degrading the gain of the circuit. We
will be talking about that, the circuit of this self-bias circuit because we do have this RE
present at the emitter, it is degrading the gain.
In fact, the a purpose more main motivation of putting this RE, it is to stabilize the operating
point of the circuit in case if beta is changing. So, you can think of that RE, it is
desensitizing the circuit or rather its operating point it is getting desensitized against the
variation of this beta. However unfortunately, this is also desensitizing this circuit against
input signal and as a result it is making the gain much smaller than whatever the original
gain of the CE amplifier potentially can provide.
So, we have to see what we can do for this part, but before that at least to you obtain the
expression of the voltage gain and the whenever we are mapping this small signal
equivalent circuit on a voltage amplifier model. So, apart from the voltage gain open loop
voltage gain, we do have two more important parameters namely input resistance and
output resistance of the model.
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So, you may recall that whenever we are going to map this circuit into voltage amplifier
at the input, we do have the equivalent resistance call Rin and then also we do have voltage
controlled voltage source, namely AV times whatever the vin and then we do have the
Thevenin equivalent resistance alright. And so, we obtain this parameter now and we like
to get the other two parameters of this model.
By the way, we have ignored this part; this part, if you want you can keep that as well.
Many a times we do ignore, but is for practical purposes we may consider this RBB and
since this RBB this node the voltage source it is directly coming here and it is a short. So,
the voltage at this point of course, it will be same as vs. However, whenever we are talking
about input resistance, whatever the input resistance we can see at this input port, it is
parallel connection of this RBB and whatever the input resistance coming from the rest of
the circuit ok.
So, while we will be talking about input resistance, we may consider this RBB, but while
here we are deriving this voltage gain AV, we have ignored because this voltage source it
is predominantly defining the voltage at the base node. So, let us find the expression of
this input resistance of this circuit. So, I do have another slide for that, yes.
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So, what we have? This is the main circuit and whenever we are going to find a small
signal parameter. In this case may be Rin expression of Rin what we will be doing it is as a
generalized methodology at the input we will be stimulating the circuit by a known signal
source and then we will be monitoring or observing the corresponding current say ix. So,
we call this is vx and then we are observing the ix and then ratio of this vx and ix that is
vx
giving us the resistance. So, is the resistance.
ix
So, one of this vx and ix is the cause and the other one is the effect. So, you may consider
say ix is the stimulus and then you can observe the voltage at the base node with respect to
ac ground or you may say that we are giving a stimulus called vx and then you are observing
the ix. Either way you will be finding the correct expression of the input impedance.
While we are doing this exercise we can keep rest of the circuits in DC operating condition
and we will be considering this is the only stimulus. And if I say that this is the vx, we may
say that this current it is flowing through this circuit as the base current. So, ibe = ix.
And the voltage vx it is again it is having two components; one is the voltage across this
rп which is Vbe and also the drop across this RE. To simplify what you can do, we may say
that if I do have ib which is ix flowing from base to emitter terminal. The current flow on
the other hand in the collector terminal it is ic which is beta times the ib which is
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incidentally, this is beta times ix. So, the total current flowing through this RE it is ix plus
beta times ix.
So, we can say that the voltage drop vx = vbe; vbe it is ix times rп plus ix times (1 + β) × RE.
vx
So, from that we can say that = rп + (1 + β) times RE. So, this is what we are defining
ix
the input resistance. So, this circuit is its input resistance is this rп in series with RE, but
then RE × (1 + β) times.
So, likewise you can find the output impedance of this circuit or output resistance of this
circuit. Note that this input resistance we obtained only coming from this part in addition
to that we do have the RBB. So, I should say this is only one part of it. So, let me call this
is R′in; R′in. So, R′in it is this one and then total input resistance of the voltage amplifier, it
will be RBB coming in parallel with in dash which is of course, this is RBB⫽(rп + RE(1+ β)).
So, similarly let us analyze the output port and let me see that what is the corresponding
expression of the output resistance. I think I do have another slide let me see, no let me do
it here itself.
While we will be doing this similar kind of exercise, we need to find as I said that we need
to find what will be the output resistance RO of this voltage amplifier, while we are
mapping this small signal equivalent circuit into a voltage amplifier. What you have to do?
391
Again we will be stimulating this circuit from this port by say a signal source called vx or
say vy and then we can observe the corresponding current let we mark it as say iy.
And while we are doing this exercise we have to keep this signal 0 since it is voltage signal
so, we are making this is ground. So, what we are and then if we take the ratio of this vx
vy
and ix so, that gives us the output resistance, so right. And here whatever you do here
iy
in fact, this rп it is coming in parallel with RE. But since we do have ideal current source
here so, these two elements it will be; it will be blocked by this ideal current source because
its resistance looking into this circuit it is infinite.
So, at the output port what we have it is only RC remaining. So, if I am applying vy here,
the current flow through this circuit it is mainly this is the current. Now, the current of
vy
course, that will be vy so, that is so, that is the iy. So, from that we can say directly that
RC
RO = RC. Now, this is of course, we are assuming that the conductance here it is 0. Now,
if I consider the additional conductance of course, will be having the influence of this part
also.
We will see that but so far what we have discussed, it is this amplifier it can be mapped
into mapped into the small signal model into a voltage amplifier. And expression of this
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gm ×RC
RO, it is RC; this is AV times vin where AV is with a – sign and then Rin ;Rin equals
1+gm RE
to.
So, if I consider RBB also, so Rin = RBB⫽(rп + (1+ β) RE). Now, yeah, so this is the voltage
amplifier model. If we consider as I said that if you consider the resistance here due to
early voltage called RO or finite conductance here, then; obviously, I need to consider the
resistance of this part coming in parallel with whatever the resistance we can see in lower
side.
So, let me discuss about that and that will of course, change the expression of this output
resistance. In fact, that will make the output resistance is RC in parallel with some other
component. So, let us see what is that component coming here. I think I do have next slide
to discuss that, yes.
Here again, what we will be doing to find the output resistance in presence of RO, we will
be stimulating this circuit by say vy. So, this is we are stimulating and then we are
observing this iy and while we are doing this exercise, we have to keep in mind that we
have to make this voltage input signal to be 0. And in fact, once you do that this rп, it is
coming in parallel with this. So, you may say that this is coming in parallel with rп.
So, RE and rп they are coming in parallel, so that is the representation. And on the other
hand since we are doing the exercise to find the output resistance which is of course,
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parallel connection of this RC and whatever the resistance you are seeing in the lower side.
So, for simplicity we may for the time being, we drop this part and let me analyze only
this part.
So, if you see this circuit, we may frequently come to this circuit again and again and so,
let me draw this circuit as a general one. So, we do have current source here which is gm
times whatever you say vbe and then we do have the ro here and then we do have the
resistance here.
And incidentally this is vbe, so this is – and this is +. So, we may call since the base is
connected to ground and emitter voltage whatever nonzero voltage, it is having. So, we
may say that this vbe, you may write this is gm × ve with a – sign. So, we can probably you
can write this ve with a – sign or we can put the current direction in this other way and then
we can say that whatever the current is flowing will; let we call this is iy and the
corresponding stimulus here it is vy.
So, since this current is flowing in this direction and of course, since we have changed this
direction of the current, we are we need to put the + sign here. And what is ve? ve is the
voltage at this point and this is the resistance RE coming in parallel with rп.
So, now, if you see this circuit that since we have we are considering only lower part and
we are not considering this RC at the moment. So, this iy it is actually flowing through
maybe bifurcating and then coming back to this ground. So, the current flow here it is same
as this iy.
As a result, ve voltage drop voltage at this point, it is iy × (RE ⫽ rп), right. So, that is the
voltage here. So, the current flowing on the other hand, it is function of this ve and then
current flow through this part of course, it is vy minus this voltage divided by ro.
So, at this node if you see since this current is coming here and then the current flow here,
it is basically summation of this two that must be equal to whatever the current is flowing.
vy −ve
So, current flow through this ro it is having one expression is . And the other
ro
expression it is (gmve + iy) and ve, it is having this expression right.
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So, what we can say that ve it since it is function of iy. So, we can take this v right side. So,
vy 1
what we are getting it is = (g m + r ) × ve and ve, it is having this expression which is
ro o
(RE⫽rп) × iy and also we do have this iy. So, we can say this (+ 1 × iy) alright.
vy
So, that gives us the expression and it can be shown that from this one, it can be shown
iy
vy
that vy; = {ro + (RE ⫽ rп) + ro(RE ⫽ rп)gm}. So, this resistance whatever the equivalent
iy
resistance, it is quite large primarily because of this term. But whatever it is the through
this analysis, what we can say that this is the resistance of the lower part then total
resistance of course, this will be RC in parallel with that.
So, let me rewrite whatever I just now have said that output resistance RO which is RC in
parallel with whatever the resistance it is coming from this circuit and that resistance it is
{ro + (RE ⫽ rп) + gmro(RE ⫽ rп)} and then whole thing it is coming in parallel with RC.
So, that is this mapping of the CE amplifier with self-bias things onto a voltage amplifier
and the corresponding different parameters. Now, what we have said that we are placing
this emitter resistor to make the circuits operating point desensitized against beta variation,
but it is making the gain also dropping to a smaller value namely what we say it is that
gm ×RC
voltage gain AV, it is magnitude wise .
1+gm RE
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So; obviously, this is not acceptable particularly if RE it is significant and this multiplying
RC
this two, it will be quite large and if this may give us a value which is close to that is in
RE
the order of maybe sometimes it may be less than 10 numerically. So, that is not acceptable.
So, we need to unless we address this issue this circuit definitely, we cannot use it. So, let
us see how this problem can be addressed.
So, what we say that how do you get back gain of the circuit. So, as you can as you have
discussed before in that whenever we are feeding the signal here say, vs significant part of
that voltage it is getting dropped across this one. And as a result we do have only a small
fraction as vbe and making this corresponding output voltage very small.
So, if we make this voltage whatever the emitter voltage; if we make 0, then we can then
force this vb to be equal to vs and then we can get back the gain. So, we like to make this
voltage 0, but then moment we make this is 0 just by hard connection. Again we will be
having the issue of the operating point getting sensitive to the beta variation. So, the clever
thing is that for dc, we do not want this circuit to be working; but for ac, we want the circuit
to be working.
So, as a result we can put a capacitor here and so the what you are looking for is basically
this capacitor, it will not be interfering the dc operating point, but then for ac signal this
will be making this ground. So, this is the solution of getting the voltage gain back and
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this is; this is not disturbing the circuit for dc operating point ensuring that the operating
point of the circuit it will remain insensitive to β variation. But for small signal or small
signal or high frequency signal, this is working as a short making the emitter node
connected to ground and making this emitter node it is going to be shorted to ground, as a
result we can simply shunt it.
So, if you draw the small signal equivalent circuit of this one, it becomes similar to
whatever we already have discussed for the fixed bias circuit. By the way we also have
this R; R1 and R2 coming in parallel and practically, we need to be careful that while we
are keeping it similar to the fixed bias. But in this case what we have said is that RBB need
to be very small compared to (1+β) RE. So, that is the basic difference remains there even
after cunning connecting this CE that RBB should be small compared to very small
compared to this one.
1
Typically to satisfy this condition what we said is that RBB, it will be ≤ 10 th of this (1+β)
RE to get this approximation is getting valid ok. So, that is the sorry this is not 2 this is 10.
So, this is what the practical design guidelines, we follow for this circuit.
So, you may say that smaller this resistance is better. So, can I make this resistance really
small or is there any trade off. Of course, if I make this if I want to make this resistance
smaller maintaining dc volt same; that means, both of these resistors I need to make it
smaller and smaller.
One consequence is that of course, there will be a dc current flow here so, that practically
increases the power dissipation. But then even more serious problem is that if this
resistance is getting smaller and smaller, then this capacitor will be having a difficult time
to feed the signal at this node.
In technical terms, you may call that this capacitor and then these two resistors coming in
parallel call RBB, they do define the lower cutoff frequency of the amplifier. So, far we are
talking about the mid frequency range operation and if you go to lower and lower
frequency then of course, the gain voltage gain it will be dropping.
So, this lower cutoff frequency, one of the candidate to define this lower cutoff frequency
is that this coupling capacitor C1 and parallel connection of R1 and R2. So, we need to be
careful that now while you are picking this RBB, we need to satisfy this condition to make
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sure that circuit is remaining insensitive to β variation. But at the same time the lower
cutoff frequency to keep it low the value of this R1 ⫽ R2 should not be very small.
But whatever it is once we follow all these guidelines the small signal equivalent circuit
of this circuit is given there which is essentially very similar to whatever we have seen for
fixed bias circuit.
So, for fixed bias as well as the self biased yeah. So, I should say not only for fixed bias,
but even for this is self-bias of course. In fact, I should have written this is self-bias instead
of writing fixed best.
So, even for this circuit also the small signal equivalent circuit it becomes like this.
Primarily this CE, it is making this node ac ground and in addition to whatever the things
we have discussed so far ah, the parasitic components namely Cµ and CП they are also
coming into play particularly for high frequency applications. So, for high frequency small
signal equivalent circuit of for sale by a circuit also, it will be similar. And of course, we
can retain this RBB here since RBB unlike fixed bias where RB, it was very high RBB we
need to consider. In fact, RBB may be comparable with this rп.
And once we connect this CE, I must mention that the input resistance input resistance
earlier it was rп in series with (1+β) RE, but then now this input resistance it is rп only and
that of course, coming in parallel with this RBB. So, that makes the small signal input
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resistance it is becoming smaller that may not be a good thing, but to get the gain back at
the cost of this input resistance, we need to ground this one.
And the other consequence is that the output resistance; on the other hand, it is RC⫽ro. So,
we are not having the other big things where we are having RE and so and so because the
emitter node it is getting grounded. So, the these are the two changes. Of course, the
corresponding voltage gain AV, now it becomes gm × RC.
So, we need to discuss some of the numerical problems, but today we are running short of
time probably in the next class we will talk about numerical problems from both angles
the design wise as well as analysis wise. That is all for now, we will be resuming this class
in the next day.
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Prof. Pradip Mandal
Lecture – 28
Common Emitter Amplifier (Contd.) Numerical Examples (Part A)
Dear students, welcome back to NPTEL online course on Analog Electronic Circuit.
Myself Pradip Mandal from E and EC Department of IIT, Kharagpur. So, this is a
continuation of our previous topic Common Emitter Amplifier. And, in the previous
class, what we have discussed about the relevant theories and today, we are going to
discuss more detail of some numerical problems.
So, I guess during this numerical problem solution some of your doubts it might get
clearer. So, as I said that primarily we will be focusing on common emitter amplifier.
And, it is having two basic biasing schemes namely the fixed bias and cell bias, and we
have discussed about the disadvantage of each of them and then advantages and all. So,
through the numerical problems, so, we shall address the limitation as well as the
advantages of the two circuits as well.
So, the overall plan we do have here it is as I said that the previous two rather theoretical
things we already have discussed namely the biasing schemes and then analysis, what are
the theoretical analysis we do follow, and then method of finding the parameters in the
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voltage amplifier where we like to map the circuit and on to and today we are going to
discuss more about this numerical examples of CE amplifier.
So, first one it is we will be talking about the bias point stability where we shall
demonstrate that fixed bias CE amplifier it is having a major issue in case if the β of the
transistor it is getting changed. And, it may require it may require the redesign of the
circuit in case if the beta of the transistor is getting changed.
On the other hand, whenever it is sale biased CE amplifier the operating point is pretty
stable and now we will see that if we vary the β the collector current hardly changes.
And, then after that we shall find the performance parameters of CE amplifier having
both the schemes biasing schemes namely fixed bias as well as cell biased and then we
shall discuss about what are the design guidelines we will be having.
Note that while we will be talking about the performance evaluation of a given circuit
which means that we are assuming somebody has given a design and our main task is to
find the gain and the input resistance and output resistance and so and so. Whereas, in
the third one whenever we will be talking about the third one there will be discussing
about suppose, we do have some requirement of gain and say supply voltage is given to
us and then how do we design the circuit, how do we find the values of different
components.
So, these two items are of course, complementing each other and of course, we need to
understand that how to do the analysis first. And, then of course, once we are reaching to
next level of maturity then for a given requirement we should be in a position to decide
how to pick the value of the different components right. So, on the as I said the first point
is that how do we demonstrate the bias point stability or instability for the two biasing
schemes.
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So, here what we have it is CE amplifier having fixed bias. So, we do have fixed bias,
the RB is given here and here we are starting with the design which is of course, it is a
proper design at least it is a proper design for β = 100. Supply voltage it is 12 V and base
to emitter on voltage approximately 0.6, this is true for silicon BJT and then this RB it is
given to us say 570 kΩ, and then on the collector resistance RC it is 3.3 kΩ.
Now, here let us try to find the operating point for β = 100. So, how do we proceed? First
of all, we can consider the input port and we can replace the base to emitter junction by it
is corresponding equivalent circuit namely the rп and in series with VBE(on). So, we do
have the VBE(on) here which we are given that this is around 0.6, we do have the supply
voltage 12 V and then we do have 570 kΩ and this is rп. And, later we will show that this
value of this rп it is very small compared to this RB.
So, we may ignore this part for simplicity and then what we are getting is that the current
flowing through this circuit is the DC base current IB. So, the IB = . So, we are
ignoring this rп of course, but strictly speaking we do have RB + rп. So, we can
approximate that this is .
So, we are getting this is by ignoring this part. So, we are considering this is very small
compared to the other term. So, this approximation involves that this we are ignoring.
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So, the base current we are getting it is 20 µA. So, the corresponding collector current
which is β times IB. So, this is equal to 100 × 20 µA. So, that gives us 2 mA.
Now, once you have the collector current it is 2 mA DC current the drop across this RC
let you call this is V voltage drop across RC. So, that is equal to 3.3 k × 2 m. So, that
gives us 6.6 V. So, the voltage coming at this node it is VC = 12 volt, VCC – 6.6. So, that
gives us 5.4 V.
So, the operating point of the transistor namely IC equals to as I said 2 mA and then VC
and VC or VCE since emitter is connected to ground so, this = 5.4 V and base current of
course, we can say that IB = 20 µA. So, that is what we get for β = 100. So, please
remember that this operating point and we will see that what will happen if we change
this beta to 200.
So, let me recalculate whole thing for β = 200. So, what we have here it is let me use a
different color here, maybe I can use red color. So, again we can consider the input port
circuit containing RB connected to VCC and then we do have the VBE which is around 0.6
V and again in this case we are finding that IB; IB it is same as the previous case namely
20 µA ignoring of course, this rп with respect to RB.
But, then since the β is 200 the corresponding collector current this is very important that
collector current it becomes 200 × 20 µA assuming the transistor it is in active region of
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operation. This is very important. We assume this assuming the transistor in active
region. Previous case, we have seen that VC voltage it was 5.4. So, it was supporting this
assumption, but in this case incidentally it is not. So, we will see that.
In case it has to support this 4 mA of current, the drop across this resistance in case this
is 4 mA, then the drop across this VRC is 3.3 k × 4 mA. So, that requires in fact, 13.2 V.
So, this is of course, it is surprising because we do have 12 V supply here, we do you
have a ground here. If the drop here it is 13.2 V, then what is the drop across this
resistance. So, that becomes impractical.
So, naturally this is a question mark. So, this is also question mark. So, practically what
happens is that once this current it demand is more the voltage drop across this RC if it is
getting higher rather close to the supply voltage of 12 V making this collector voltage
and it is sufficiently low enough, and then base to collector junction it gets forward
biased.
As a result, if the base to collector junction it is getting forward bias the VCE voltage it
will be very close to ground, of course it will not be negative and you may say that VCE it
is going to it is limit; normally referred as VCE(sat) and it may be in the order of few
hundreds of mV. So, let you consider this is say 0.2 V.
And, if the device it is forced into to this saturation region so, then the VCE = 0.2 V and
then of course, if this is 0.2 V then drop across this RC instead of 13.2 actually VRC is
equal to . So, that means, this is how much . So, that gives us maybe 3.5 I
made some calculation for you. So, it was 3.578 something approximately milli ampere.
So, instead of 4 mA actually the current is practically the current is this one and most
important thing is that the transistors this transistor enters into deep into the saturation
region and the consequence is that the gain from base to collector it will be much
different much smaller. So, later probably we will discuss about that, but just to say that
to keep the gain it is good we need to keep the transistor it is in active region which is
failing.
In fact, you may recall the methodology of finding the operating point. So, if we plot the
IC Vs. VCE characteristic curve for the transistor. So, what is happening is for β = 100 the
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device characteristic it was like this and then the load line load line it was this one and
we got nice operating point and the VC it was 5.4 V.
So, this is for β = 100. So, we may say that this is β = 100 and this is now if we change
this β if the device is getting replaced by another one having different β then the
corresponding device characteristic it is shooting out. So, this is for β = 200 and making
this device the transistor it is deep into the saturation region.
So, this boundary of the active region actually it is 0.3 sometimes it is also considered it
is 0.2. Basically, the voltage across this collector to emitter port is very small. So, we can
say that the operating point got changed from this point to this point. So, that makes this
fixed bias CE amplifier it is its operating point it is very sensitive to this beta.
So, you may say that yes, β also change from 100 to 200 is it somewhat abnormal? No, it
can be it may have even wider range the β can go even higher or it can go even lower
than 100. So, it is in the normal range of this β. But, then if the operating point it is going
here from here earlier if the operating point it was here for a given meaningful input
here, the output voltage probably we are obtaining having a nice signal swing.
But, sorry let me use a different color consistent color. So, for β = 100 we are getting
nice signal swing at the output. So, we are getting nice signal here. On the other hand, if
we have say β = 200 since the operating point got shifted here. So, we are expecting that
output it will be almost it is getting saturated here and only one side.
So, let me redraw in this case. The output voltage it goes heavy distortion at this point.
So, this part it is this part it is properly sinusoidal, but ideally it is supposed to be this
part also sinusoidal, but this entire portion is getting removed because the operating point
it is towards the in fact, outside of the active region. So, as a result we cannot use this
circuit. So, only one possible thing is that if the β is changing to 200 for some reason
probably the only option is remaining is that we need to adjust this IB to 100 µA by
changing this RB.
Now, this may not be practical particularly if we consider thermal runaway problem
where the beta may be continuously changing with temperature. So, the next thing next
as I said the solution is that cell bias.
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So, let us see that cell bias circuit and the same situation if we consider namely we
consider two values of beta and then we will see the changes of operating point of the
cell bias circuit ok. For consistency let me consider this is mistake. So, we should
consider this is 100, β = 100. So, let you consider β = 100 and for that let me calculate
what is the operating point.
Now, here also let me consider the input port we do have R1 and R2 and their values are
given here R1 and R2 supply voltage here it is 12 V and VB(on) it is approximately 0.6 and
then we do have the RC and RE also.
So, once you consider say the input port what kind of circuit we do have it is probably
we can translate this part this part by it is equivalent circuit namely VBB. So, we can say
that VBB which is the Thevenin equivalent voltage coming here from this 12 volt and the
potential divider R1 and R2. So, incidentally this is 12 × and that becomes 3 V.
And, then we do have the Thevenin equivalent resistance which is R1 ⫽ R2 and what is
the value here? It is . Why 4? I just consider summation on this one, but whatever
it is, it is coming around 2 point I think I made some calculation for you 2.475 kΩ. So,
that is the we call this is RBB and with that we do have the diode.
So, we can draw it is equivalent circuit having rп and then VBE(on) and then we do have
the emitter resistor RE. And, note that while the IB current it is flowing through this
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circuit we are expecting the current flow through this RE it is not only this IB let me is a
different color. So, not only this IB it is flowing through this circuit, but also we do have
β times this IB coming from the collector side. So, this is β times IB is also flowing.
So, we do have IB here plus β times IB. As a result, the current flowing through this
circuit it is (1 + β∙IB). So, that is the current is flowing. Now, in this circuit if you see if
we analyze to find the expression on the collector current it is what we have it is
. So, that is the expression of IB.
So, if you analyze this loop and then if we consider this current is 1 plus β times
whatever this current so, even though this β∙IB current is coming from the collector side
we can simplify this analysis to get the expression of IB. Now, this can be well
approximated by considering that this is dominating over these two elements.
So, if I consider this approximation if I consider (RB + rп) is much smaller than (1+
β)∙RE. Then we with this approximation we can say that this is . In fact,
further to that probably we can drop this one with respect to β, but whatever it is we are
getting this expression of this IB and from that we can say that the collector current
which is β times IB which is ×β.
So, if I ignore this one and then I can cancel these two beta, so, this we can approximate
by considering only this . So, that gives us this collector current equals to. So,
let me use the space. So, the collector current it is 12 V – 0.6. So, that is 11.4 sorry VBB,
VBB we do have 3 V.
So, we do have collector current IC equals to which is in this case it is given as 1.2
k. So, of course, this is approximation and it is 2 mA. In fact, the design wise we said the
value of this RE it is such that this 2 mA current is consistent with the previous circuit.
Now, here note that since in this expression let me use a different color here in this
expression of this IC since this part and this part it is getting cancelled. And, then
expression here after this cancellation it is becoming almost independent of β, but of
course, there are two approximations one is 1 + β we are approximating as β and also we
do have this approximation. So, VBB.
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Now, so, if these two approximations are consistent then we can say that this collector
current it is quote and unquote independent of β and in fact, the same analysis it can be
done for this β also and with this two approximation again we can say that the collector
current it is approximately equal to 2 mA.
So, what is the conclusion is that even if the β is changing from 100 to 200 and as long as
this is valid, then we can say that collector current is not changing. But, note that the
base current base current of course, it is function of β. So, what is happening internally
that because we are placing this RE and the voltage here it is approximately getting 3 V
by ignoring the drop across this RBB the current flow here it is maintained to be close to 2
mA or another IC it is very close to 2 mA and the IB on the other hand it is getting self
adjusting.
So, this equation if you see here this equation on the other hand equation of this I B if
beta is changing IB it is proportionately getting decrease, maintaining the collector
current independent of β. So, that is the catch. So, here we are saying that the collector
current is 2 mA.
So, the drop across this resistance it is RC it is 2.7. So, the drop across this is VRC = 2.7 k
× 2 mA. So, that gives us 5.4 V. And, the drop across this RE on the other hand VRE
approximately = 1.2 k × 2 mA approximately.
So, we are considering this IE and IC they are approximately equal. So, this is becoming
2.4 V. So, what we have here it is to find the operating point the voltage DC voltage here
it is 2.4 V and the drop here it is; drop here it is 5.4 and we do have 12 V. So, the VCE
voltage that gives us this VC voltage = 12 V – 5.4. So, that = 7.8 here and then we do
have 12 – 7.8. So, that gives us 4.2 V.
So, VC is 4.2 V and the voltage of course, here it is. So, the voltage here it is
approximately 3 V and the voltage here it is 12 – 5.4. So, that is how much, it is 6.6 V.
So, that ensure that this junction it is getting reverse bias. So, the transistor also it is
remaining in an active region.
So, that demonstrate that the CE amplifier with cell biased circuit the operating point is
not changing. In fact, it is even though beta is changing from 100 to 200 still it is
approximately remaining same.
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Intuitively or pictorially rather what you can say that the if we draw the IC Vs. VCE
characteristic curve, even for different beta we can say that this characteristic curve
almost remains the same. And, in fact, I should not say this is VCE rather I should drop
this part and then I should draw only the IC Vs. VCE, but whatever it is let me complete
what I like to discuss here. So, this is the load line.
So, even though β is changing from 100 to 200, this characteristic curve almost
remaining there, and not only that the voltage here also it is remaining close to 3 V – 0.6.
So, that is 2.4 V approximately and the voltage here it is whatever it is. And, however, if
I draw the voltage sorry IC Vs. VB not VBE, but VB voltage at this point.
So, instead of exponential characteristic curve actually we are getting this curve getting
shifted to something like this. So, if I apply a voltage here to illustrate that if I apply
voltage and if I vary this voltage and then if I observe the corresponding collector current
because we do have RE present here, this exponential characteristic curve instead of
exponential it becomes almost flat.
And, in fact, if we see the slope here which is gm change in IC with respect to base
voltage and then if I see the corresponding gm here the changed one if I call this is g′m it
is much smaller than this gm. And, it can be shown that this gm actually it is much
smaller. In fact, in the previous class we already have discussed that transconductance of
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the circuit in case if we do have this RE it becomes if I call g′m it is and this is
approximately .
So, the transconductance of the circuit if though it remains gm, but if I consider if the
transistor it is degenerated by RE the corresponding gm it is getting changed to this one.
As a result, gain of the circuit it was dropping. We will discuss that in the numerical
problem.
So, what we have discussed that we have demonstrated the stability of the operating
point, now we will be coming to calculate the gain and the other parameter of the voltage
amplifier for the two examples namely cell biased as well as the fixed bias.
So, we will be going to discuss this one, but let me take a small break then we will come
back.
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Prof. Pradip Mandal
Lecture – 29
Common Emitter Amplifier (Contd.)
Numerical Examples (Part B)
Yes, welcome back to our discussion Numerical Examples of CE Amplifier. And, we are
discussing about CE amplifier with fixed-bias.
So, what we said is that based on the value of RB and RC. We obtain the base current IB =
20 µA and then for the value of β = 100 the IC = 2 mA. And then, we are feeding the
signal small, signal here and we like to see that what will be the gain of this circuit
particularly if the signal frequency it is sufficiently high for considering these capacitors
to be short.
So, to get the expression the value of the gain of this circuit as well as input resistance
and output resistance, we need to find a small signal parameter of the transistor. Namely,
the important parameters are gm, which is IC. We have discussed about this IC divided by
thermal equivalent voltage VT. So, this is . So, we can say that this is and this is
A/V.
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And then the other parameter it is the rп base to emitter small signal resistance which is
in fact, defined as reciprocal of change in IB with respect to Vbe, I should use small vbe
and this is in fact, this is . So, in this case g m we already obtained and β is 100. So,
that gives us 100 × 13. So, that is equal to 1.3 kΩ. So, the small signal parameter of the
transistors is this.
In fact, we also have one more parameter, but since we did not get any information about
the early voltage we may consider this is approximately equal to infinite. So, rather it is
going to be very high compared to the RC and the other resistance RB.
So, then what is the voltage gain? So, let us draw the small signal equivalent circuit of
the amplifier. What we have it is RB connected to VCC which is AC ground and then at
the base we do have the rп, and then we do have the emitter terminal connected to
ground, and then we do have the voltage dependent current source which is gm times,
whatever the base emitter voltage we do have here small vbe.
And then we do have the RC which is also connected to VCC and then the voltage here it
is the vout. So, at the input on the other hand we are given the signal vs. And then
incidentally since we are not considering the source resistance the voltage coming here it
is vs and this is connected to ground, so from that we can say that vbe equals to vs.
So, that gives us this part is also vs, and then since this current is flowing through this
resistance then the voltage coming here at this point which is vout = – gm × vs × RC, so
that is the vout. So, from that we can say that the circuit gain voltage gain Av defined as
= – gm × RC.
And what is its numerical value? So, the value of this gain it is let me use this space here
gm it is and then RC it is 3.3 k. In fact, if you see here. So, whatever the value it is; so,
I should say that the voltage gain here it is magnitude wise of course, with a minus
sign.
In fact, if you see here the gm and RC we do have another expression of Av, particularly if
I consider the magnitude this is gm × RC and gm is thermal equivalent voltage. And
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this RC and IC it is nothing, but the voltage drops across this resistance which is VRC,
right, VRC that = 3.3 k × 2 mA. So, that is equal to 6.6 V.
So, this part it becomes , 0.026. In fact, that is become same as this one. So, anyway
so, that is the value of this voltage gain. And the next one is input resistance. So, the
input resistance of this circuit it is RB coming in parallel with rп. So, we can say that Rin
= RB coming in parallel with rп. RB here it is quite high compared to this rп, so we can
see that this is approximately rп which is equal to 1.3 kΩ.
And next one is the output resistance. So, the output resistance looking into this circuit,
since we do have ideal current source here and this node it is connected to ground, so the
moment I make this is ground this is also ground in fact, this current also becoming 0.
So, the output resistance RO it is nothing but this RC. So, next one is output resistance
which is equal to RC so that is equal to 3.3 kΩ, right.
So, if I summarize what we are getting here it is, if we draw the equivalent circuit of the
amplifier we do have the input resistance which is 1.3 kΩ and then we do have the
voltage gain, if I say this is + and this is – and then we can say that this is minus how
much was it ; sorry.
⁄
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So, that is the Av multiplied by whatever the vin we do have here vin and at the output we
do have the RO which is RC, so that is 3.3 kΩ. So, whenever we are feeding the signal at
the input port vs and if we are not connecting any load here whatever the voltage you are
getting here it is just this multiplied by this vs because the vs is directly coming equals to
vin.
So, this is the, this is the I should say voltage amplifier model or it is referred as macro
model of this whole amplifier. And this voltage amplifier model it can be used
particularly if this circuit is connected to maybe another circuit and then we can find the
corresponding model of the subsequent circuit.
So, if we cascade multiple amplifiers together then translating this amplifier into this
voltage amplifier model is very important and this voltage amplifier as I said that it is
having basic 3 parameters voltage gain, input resistance and output resistance. Now, let
me do the similar thing for the CE amplifier with cell biased circuit. So, I do have ok.
Before I go into cell bias circuit I like to say a few more points about the CE amplifier
with fixed bias. So, let me cover that part. So, we are talking about the voltage gain and
input resistance and output resistance. What are the other parameters being important for
this amplifier?
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Next to the amplifier gain I should say that output swing. Output swing means the output
signal amplitude, either you may say peak to peak or amplitude which is quote and
unquote distortion free. So, in this circuit depending on the operating point here and
operating point here while the signal it is riding over the DC we can say that what may
be the signal allowed here at the collector node before the transistor it is going out of
active region.
Say the voltage here, the voltage here it is let me use different color here voltage. DC
voltage here it is around 0.6 and on top of that we do have this signal. However, the
signal here it is quite small compared to whatever the signal we are getting here because
you already have seen that the gain of the circuit is , ok.
So, roughly close to 300 gain 270, around 270 to 300 gain which means that signal
amplitude at the output node it is very high. And also we have said that the voltage at this
node it is 12 V – 6.6. So, that gives us 5.4. So, the voltage here it is having 5.4.
So, with respect to time the VCE voltage or incidentally that is output voltage it is having
a DC which is 5.4 V and on top of that we do have the sinusoidal signal. So, the
sinusoidal signal if it is riding over this DC, it may be taking the transistor towards the
edge of the active region. And what is the limiting case here?
If this is 0.6 and if I say that VCE(sat) it is around 0.3, then the voltage drop here it is lower
limit it is 0.3 V. So, we can say that before the transistor it is going out of active region
the amount of signal here it is 5.4 minus this voltage. So, the negative side or we can say
that Vout, amplitude or magnitude it is equals to 5.4 minus this part which is 0.3.
So, we can say that 5.1 V, amplitude it can be supported by this circuit. So, this is 5.4 –
0.3, so 5.1V negative side swing. On the other hand, this voltage it can go theoretical it
can go as high as 12 V and since this DC voltage is 5.4, so positive side it can go even
higher than 5.4, in fact, this is the 12 V level. So, definitely this 5.4 V it will be well
supported.
So, I should say that Vout magnitude max equals to minimum of whatever the swing
positive side and negative side swing which is 5.1 V or sometimes it is referred as ± 5.1
V output swing or otherwise you can explicitly say negative side it will be – 5.1 and then
positive side it can go even higher.
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Note that DC voltage it is existing here, but whenever we will be seeing the signal here
we will be seeing this DC getting blocked, as a result output voltage it will be having
only the signal part. So, of course, depending on the limit of the signal handling capacity
of this transistor the swing at the output it will be getting restricted. So, that is the output
swing of the circuit.
Other point is the power dissipation. While the coefficient current is flowing through the
base terminal IB and then the collector current is IC, naturally there will be a power
dissipation and the whenever we talk about the power dissipation is basically the VCC
multiplied by these two DC power, IB + IC.
In fact, it can be shown that since the signal of the, even though the signal it is it may
vary this total current, but if I take average of the current it is same as the equation
current, as a result the average power it will be simply multiplication of this VCC and IB +
IC.
So, if the circuit is having higher current naturally the power dissipation, power
dissipation it will also be higher. So, there may be some application where you like to go
for low power application kind of things, then you may have to reduce this collector
current and then base current, but of course, to while you will be reducing this current
the corresponding resistance you need to increase to achieve the same gain namely as I
said the voltage gain is drop across this .
So, if you are decreasing this current and if you proportionately increase this RC then you
can maintain the gain to be remaining constant. However, of course, if RC if you are
increasing the corresponding output resistance of the circuit it will be getting increased.
So, there is of course, a trade off.
So, this is once the other set of performance parameter. And then also the other thing is
that the cutoff frequency. That is the other thing we must say that, so far we are assuming
that the signal frequency and the value of the capacitors and then associated resistance
and all recess that for the signal frequency the capacitors they are behaving like a short
circuit.
But you imagine that if the signal frequency here it is getting smaller and smaller the
signal may be having difficulty to come to this node. In other words, this C and input
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resistance of this circuit they are forming one C-R circuit. So, the C-R circuit, so R is the
input resistance and this C, it is this C. So, that is C-R circuit that is forming whatever
you see the hyper kind of circuit.
As a result, depending on the value of this capacitance if you go to lower and lower
frequency the available gain starting from this point to this point it will be getting
affected. So, in the mid frequency range you may get good gain, but if you consider low
frequency side the gain it will be getting affected.
So, let me illustrate differently. So, if you plot the gain, magnitude of the gain, with
respect to frequency maybe in the mid frequency range it will be having good gain
whatever the gain we talked about say whatever the value it is.
But then if you go to lower and lower cutoff frequency then there will be degradation of
the gain and we may come to a point where the gain it is times less than whatever the
√
gain we are getting and then we call this is the cutoff. So, we may say that this is cut off
in the lower side or you may say that lower cutoff frequency.
So, likewise if we go to higher and higher frequency the output resistance which is
eventually R-C, this output resistance in combination with maybe the load capacitance at
this node if I call CL, they are forming one R-C circuit. Though this circuit is working as
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a short in higher frequency, but then output resistance and then CL they are forming one
R-C circuit.
So, R-C is, what is it? It is low pass. So, we do have the low per circuit getting formed
by this RO and CL. And this R-C time constant it will be defining another corner
frequency. So, if you go to higher and higher frequency then again the gain it will be
dropping by times of this middle frequency and then it will be giving another cutoff
√
frequency.
Then this frequency it is referred as cutoff in higher side or upper cutoff frequency. So,
the entire frequency ranges over which the gain is remaining almost constant, this is
called the bandwidth of the circuit. So, if the signal frequency it is lying within this one
then you can get nice gain like this one. But if the signal frequency it is going beyond
this side or beyond this side then since the gain is getting affected, so we may say that
the amplifier performance it is getting changed.
So, while we are designing the amplifier not only you have to consider the gain of the
circuit, but it is also important to say that, what is the corresponding cutoff frequency,
the lower cutoff frequency and the upper cutoff frequency. And the particularly the lower
cutoff frequency it is predominantly defined by this one and the input resistance.
So, if I call this is C1 and this is Rin then this corner frequency it is . So, likewise
this upper cutoff frequency it is , whatever the load capacitance we do have here
or it may be coming from the next circuit as input capacitance which is working as load
for this circuit.
So, these are the other important parameters we must say. To summarize what we said is
that the voltage gain is important and then the swing, output swing. So, output swing. So,
while we will be defining this output showing it is very important that the question point
we should be setting properly so that both positive side as well as negative side it is
having equally getting priority, as a result we are getting maximum undistorted
amplitude signal.
And then of course, the power dissipation, and then the cutoff frequencies or rather
bandwidth. So, the bandwidth these are the important performance parameter. Indirectly,
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I should say that the bandwidth and Rin and Rout are related. So, these are the while we
will be designing a circuit we must be considering these parameters, right. So, let me as I
say that, so far we are talking about fixed bias amplifier, similarly let you consider cell
biased.
So, here is the numerical example this circuit we have discussed for different reason,
namely to check the bias point stability for different values of β and we have said that the
collector current it is IC it is approximately 2 mA for this circuit.
So, once we know the collector current then we can find the small signal parameter of
the transistor. So, since IC = 2 mA, so that gives us, that gives us the gm transconductance
of the circuit = which is A/V. So, it is same as the previous circuit.
And then rп which is . So, in this case we do have or so, this is actually 2.6 k,
right. So, these are the small signal parameters of the transistor. Now, to find the gain we
can and then input and output resistance of the amplifier.
Let me draw the small signal equivalent circuit and so, what we have at the input it is rп
and then we do have the RE, but then RE it is getting shunted by CE. So, we can say that
emitter node it is AC ground. And then at the collector to emitter side we do have the
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voltage dependent current source which is gm × vbe where vbe is the voltage drop across
this rп.
And then at the collector side we do have the RC connected to DC voltage which is AC
ground and this is the output node. And then of course, we do have R1 ⫽ R2 and they are
one of them it is connected to VCC another one is connected to ground, but both of them
are we can say considered as a C ground. And this is RBB or we can say R1 ⫽ R2 and then
we do have the signal source connected through the capacitor which is working as a
short.
So, we do have the vs here, we do have the base terminal here, we do have the emitter
node here and then the collector node. Now, incidentally say that the emitter node it is
getting shunted by CE. So, this vbe this is incidentally equal to vs. So, here also the output
voltage coming here, since this current is flowing through this RC. So, similar to the
previous example here also it is gm × vbe × RC.
And vbe since it is same as vs, so we can say that = gm × RC and this is what it is the
definition of the voltage gain. So, here also we are getting the voltage gain equals to the
gm which is . The RC unlike the previous case, so we do have slight different value it is
2.7. So, we do have 2.7 k, so it becomes . So, this is approximately equals to 200
may be how much 208 or something like that 7 roughly, with a – sign.
So, that is the voltage gain. Likewise, the input resistance it is if I look into this circuit to
find the input resistance, what you have to do we need to look into this circuit and
whatever the resistance you are finding if we consider this node it is connected to
ground. So, RE it is getting shunted. So, this is RE, so this is getting shunted. So, the input
resistance it is rп coming in parallel with RBB, right.
On the other hand, the output resistance if I look into this output port, the output
resistance = RC in absence of ro. In case if we have say ro then that r naught it will be
coming in parallel with RC. So, we do have these 3 important parameters the voltage
gains, and then input resistance and output resistance and this is directly coming 2.7 k
and this is rп it is 2.6 k in parallel with RBB.
420
So, that was roughly 2.7 k again, so in the order of 1.3 k. So, that is the different
parameters of this circuit. Similar to the CE amplifier with cell biased circuit we need to
check the output swing and also the cutoff frequency and the values of these cutoff
frequency of course, as I say it depends on output resistance and load capacitance, the
same way we can calculate.
The output swing on the other hand just to say that, ok. So, let me go to the other slide
where I do have the circuit diagram.
Here what we have analyzed that the voltage at this point it is 3 V and the voltage here it
is 2.4 V. Note that if we have the CE even though the voltage here it is having AC signal
on top of this 3 V, since the capacitor it is shunting here the voltage 2.4 it will be quite
steady. So, the voltage swing of course, we do have at the output node we do have the
output voltage which is the collector voltage VC = 12 V – RC × 2 mA.
So, the voltage here it is this part it is 2.7 multiplied by, so this is 2.7 × 2, so that is 5.4.
So, that gives us 12 – 5.4, so that is 6.6 V. So, we do have 6.6 V here and then we do
have 2.4 V here and 3 3 V here, it is steady. Roughly I should say the signal here it is
very weak compared to this one.
So, if I consider this node output node it is having a DC voltage on top of that it is having
some AC signal riding like this and the voltage here it is 6.6. The voltage at the emitter
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on the other hand it is, let me use different color. So, the voltage at the emitter is this one.
To keep the transistor, it is in active region of operation we require VCE(sat). So, we
require VCE(sat) of say 0.3 V.
So, the possible swing here possible swing here it is we do have 2.4 here and then +0. 3,
so the voltage here it is 2.7 V. So, the possible swing here it is 6.6 V minus this 2.7. So,
this is becoming 3.9 V. Positive side of course, it can go close to 12 V. So, positive side
we do not have an issue in fact, it can support more than and this 3.9 V. So, we can see
that Vout swing without having any distortion it can go plus minus 3.9 V, ok. So, that is
about the swing.
Power dissipation of course, it is having the collector current IC and then also it is having
the base current IB. In addition to that it is having a current flowing through this circuit,
whatever you say that I bias. So, the power dissipation it will be VCC × (IC + IB + IBias),
we can directly say the , so the current here it is IBias and each of these terms.
So, this is 2 mA, this is 10 µA. In fact, directly you can divide this collector current
divided by this β to get this 10 µA and this current is . So, how much? It is close to
0.9 mA.
So, roughly 0.9 mA, so it becomes 12. You may ignore this part. So, we do have 12 × 2.9
mW. And then about the cutoff frequency, as I said that the lower cutoff frequency it will
be decided by this C one and then input resistance. So, the lower cutoff frequency,
fcutoff(L); it is one possibility is that , depending on the value of this C1. So, this
is one possibility.
And also another thing is that depends on how successfully this CE it is bypassing this
node and then we will be having another candidate to define this lower cutoff frequency
and its value it is, so either maybe this one or . Why gm?
Because the resistance here it is not only this RE, but also the input the emitter resistance
of this transistor. So, either you can think that way or probably you can directly write
that multiplied by the gain of the circuit. So, anyway I will not be let me discuss
this one later. But at least we can say that CE also it is having one important role to play
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to define this lower cutoff frequency and we need to consider and the higher one, max of
this two, max of this two.
On the other hand, the upper cutoff frequency if cut off upper that remains same as the
previous one output resistance which is RC × Cl. So, that is the cutoff frequency and
then output swing and then the power dissipation.
So, mostly I have covered important things is that we how do we analyze the circuit. In
fact, I do have some more material to cover, but let me see, I will be. In fact, this you can
consider as one exercise. In case this CE part, sorry. In case if the CE part if you remove
what will happen to this circuit you can find the small signal parameter and then
correspondingly the voltage gain as an exercise. You can find what will be the
corresponding voltage gain.
And its expression it is in case CE is not there. And this can be well
approximated by . And so, this RC it is how much? Do you have . So, this is of
course, it is in the order of two point something, 2.25 or something like that, which
means that the important thing is that the gain is very bad.
So, that is what I was telling that the moment we put this RE without CE, the gain of the
circuit it will be very poor. And of course, the other thing is input resistance it will be
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RBB in parallel with rп in series with (1+β) RE. So, this is the other change you can see
that since it is coming in this β × RE it is coming in series with rп, so you may
approximate that this is practically this is RBB.
I think the analysis part I have covered, but as I said that he was having different plan we
will be covering that detail namely the design guidelines in the next class but let me
summarize what are the things we have covered so far.
The bias point stability we have covered, both theoretically we have covered in the
previous class and today we have numerically cover. This and the theoretical part,
analysis and method of finding the input resistance and output resistance we have
discussed in the previous class, and today what you have done is that through the
numerical problems we have obtained the value of those parameters, and we obtained the
operating point, and the voltage gain, input resistance, output resistance and also we
learn how we obtain the gain back in the CE amplifier.
So, by using the bypass capacitor how we get the gain back. And then, in the numerical
examples primarily we have covered the analysis and this part, the design guidelines part
it is remaining. So, I will take this design guidelines part probably in the next class, right.
I think that is all I do have.
Thank you.
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Prof. Pradip Mandal
Lecture – 30
Common Emitter Amplifier (Contd.)
Design Guidelines (Part A)
Hello, so now so, welcome back to this NPTEL online course on Analog Electronic
Circuits. This is of course, it is we are having this course for maybe last 2 to 3 weeks, it is
continuation of that topic of Common Emitter Amplifier. We have discussed about the
theoretical aspect and some of the numerical examples, and in the previous class we could
not complete the numerical problems all.
So, today we are discussing some more numerical problems. In fact, in the previous
numerical problem we have discussed about, how to find the gain numerically as well as
how to analyze the circuit? And, today what will be doing is that in case if we have to
design one common emitter amplifier for a given requirement, then how do you proceed
and what may be the design guidelines we need to follow. So, that is what will be
discussing.
And, also in case if you have see multiple common emitter amplifier cascaded to each
other, then how do you find the overall gain? So, these are the two things we do have in
mind.
425
So, as I said that this is what we are from in fact, we already have covered significant part
of the numerical examples. And, particularly the operating point and then the and it is
stability and then finding performance matrices. And, today we are going to discuss about
the design guidelines.
And, in case if we have say relatively bigger circuit then how do you proceed to analyze
that circuit? So, let me skip a number of slides here.
426
So, we have covered these numerical problems the CE amplifier and then this is where we
are going to discuss the design guidelines of common emitter amplifier. And, so, we are
going to discuss detail about the design guidelines of common emitter amplifier. And, in
case if the topology is fixed and if it is decided to be fixed by us topology.
And, then how do you proceed first thing is that we are assuming that these informations
are available particularly the supply voltage it is given to us. Typically, and the supply
voltage it is given by the customer who requires this circuit. And, also this information
may be available particularly, whether the BJT is silicon type or germanium BJT. Based
on that we can decide what is the VBE(on) of the device? And, also we are assuming that the
β of the transistor it is measured and may be 100 or 200 or whatever it is.
So, we assume that these 3 informations are given to us. Whenever then whenever we are
talking about we have to design, what do we mean by designing is that finding the value
of this bias resistors and also these 2 capacitors C1 and C2. So, our main task is to find the
value of this bias components as well as some guidelines of how to select the value of C1
and C2?
And, of course, the requirement here probably it will be in terms of the gain of the circuit
and then the output swing, of the circuit namely what may be the available voltage here or
available voltage here without having significant distortion and that is of course, very
much important thing. And, then the power dissipation of the circuit. Namely, if the supply
voltage is given to us next thing is that the power dissipation it will be decided by how
much the quiescent current is flowing through the transistor IC and IB.
So, we can say that IB and IC predominantly IC sorry IC is defining the total current. So, we
can say that in the power dissipation it is essentially means that, the value of the collector
current. And, then the additional information it may be required is that what may be the
input resistance of the circuit, small signal or large signal input resistance, then output
resistance of the amplifier and then what may be the input capacitance Cin?
So, input capacitance probably we can skip that part for the time being, but just to say that
to calculate this Cin or to get some information about Cin, we require additional information
from the device data set is that CП and Cµ.
427
So, from that we can calculate the what will be the Cin? So, as I said that may be in the we
will skip this part, because this Cµ it is contribution to Cin it is through Miller effect. So,
we get to cover that Miller effect whenever will be covering that we will discuss about this
part.
So, then what we are talking about that finding these components based on predominantly
from these informations. Now, if you see the voltage gain of the common emitter amplifier
Av, we have discussed that it is magnitude it is gm × RC. And, the g m it is and the quiescent
current IC divided by thermal equivalent voltage VT. So, this multiplied by RC what it is
R
giving us that voltage drop DC wise voltage drop across this resistance VC.
T
Now, of course, this upper limit of the drop across this resistance it is defined by this VCC.
VCC
So, it is hard limit is . So, we cannot get gain higher than this one. So, definitely I should
VT
say this is higher limit. And, in fact, if you consider drop across this resistance is VCC then
the required voltage here it is or rather the voltage here to be 0.
So; obviously, if we make this voltage 0 then output signal swing it will be getting affected.
So, this is just to say numerical limit of the gain. Practically, you know if we have to
consider output swing and to consider the output swing you may recall the load line and
then device characteristic and the operating point.
428
So, IC Vs. VCE characteristic curve of the device is say like this, then we do have the load
VCC
line, which is defined by this VCC point here and then the current here or which is .
RC
And, this is the operating point. So, lower side we do have a limit of the VCE or output
voltage it is VCE(sat). So, this VCE(sat) again of course, it depends on the device.
Typically, in the order of say 0.2 or 0.3 volt and then we do have VCC. So, over this limit
the VCE voltage or the Vout voltage it will be flying. As we are applying signal here the
corresponding voltage here it will be flying over this range.
Now, to have a meaningful swing of the signal from this with respect to this quiescent
point lower side and upper side, it is better to set this quiescent point at the middle. So, I
should say that if the quiescent point it is set at the middle, then we can say drop across
VCC −VCE(sat)
this resistance RC instead of this the it is limit it should be rather and then of
2
course, we have the VT.
So, I should say this is the upper limit of the voltage gain giving importance to the output
swing. And, in this case if I say that VCE(sat) is very small and then we can say that upper
12 V
limit of the voltage gains, we can practically you can say this is 2 × V .
T
So, that gives us upper limit how much this may be 4 around 460 something. So, beyond
this definitely we cannot get the voltage gain. Let me check whether the numerical value,
we obtain for this upper limit is this for 61 fine, 461 is the upper limit, but it is fine. So,
based on this information and of course, if we do so, the output swing, this output swing
VCC
it is becoming VCC approximately ± with respect to the quiescent point, ignoring of
2
course, this VCE(sat) assuming this is very small.
So, yes though we do have good swing and then we can have a very decent gain here. So,
it is in the order of 231 or so yeah around 230 ok. So, now to get this 230 again, what you
have to do that drop across this resistance is we are allocating this voltage drop close to
VCC
. Now, next thing is that the power dissipation. So, based on this power dissipation
2
information given to us, we can find the value of this current, because we can say this
power dissipation it is approximately equal to VCC × IC quiescent current of the collector
terminal.
429
So, if the power dissipation is given to us since we know this VCC. So, from that we can
find what will be the corresponding IC? So, then if I know this IC, if I know the drop across
VCC
this VRC = then I can find what will be the RC?
2
So, what is the sequence of finding different parameters, first of all we can set the drop
VCC
across this RC, in the order of or very close to , that will be giving us good gain as well
2
as output swing. Note that our target probably the again it is not specified it may be say
that the gain may be as high as possible and for that to make a balance between this gain
and output swing we can take this one.
So, the first thing is that a drop across this one we can take half of the supply voltage. And,
then from power dissipation we can find what will be the current quiescent current. So,
that is the power dissipation divided by VCC. So, then next thing is that we can find the
VRC
value of RC which is of course, .
IC
And, then from the information of the beta we can find what will be the I B and from that
we can calculate what will be the RB. RB = [VCC – VBE(on)]/IB and IB it is IC / β. So, from
that we can find what will be the value of this element. In fact, this voltage drop it is very
close to 0.6.
So, in you may ignore even 0.6 for approximate calculation with respect to 12 V and that
gives you the value of RB. And, from that we obtained the RB and RC and to find the
coupling capacitor a signal coupling capacitor or d c coupling capacitor say C1. We need
to find what is the input resistance Rin and you may recall in our previous example. So, if
the collector current it was in the order of you know it was 2 mA.
So, the corresponding Rin it was. So, Rin it was rп ⫽ RB, which ≈ rп and rп equals to β, which
is say 100 divided by gm. So, from that you can of course, the gm we know. So, once we
obtain say RC RB then we can find the corresponding rп. And, then rп gives us the input
resistance Rin and from that we can calculate this C1, because the depending on this value
of this R and C or time constant, we can find the we can get the lower cutoff frequency.
So, to be more precise to get meaningful value of this C1, we require additional information
about the performance requirement, namely the lower cutoff frequency. So, if I know that
if fcutoff(L) lower cutoff frequency from that we can say that what will be the C1. So, let me
430
consider that this parts are given to us next thing is that how do we find the C1? So, let me
clear it and then we assume that IC it is known to us.
β I
Then, Rin ≈ rп which is g which is VC . And, if I consider IC is say 1 mA as a special case
m T
26 mV
or one case and β is say 100. So, from that we can say that β× 1 mA . So, this gives us 2.6 k
all right.
1
And, the lower cutoff frequency fcutoff(L) = 2пR , where C1 is this one. Now, if I consider
in ×C1
this value of this Rin. So, from that we can see or we can rearrange this equation saying
1
that C1 = 2пR right. And, suppose this Rin it is say around 2.5 or 2.6 k and say lower
in ×fcutoff
cutoff frequency is a say 50 Hz. So, then what may be the value of this C1? Let us see 1
divided by 2 × п × Rin is 2.6 k × say 50. So, k is 1000 you have to write here yes.
So, we do have 100 here. So, this is 1 by or rather 10-5/(2.6×п) or you can say that this is
10
× 10−6 F, or you can say in the order of say µF to get a lower cutoff frequency of
2.6×п×10
50 Hz. So, that gives you an idea that for a typical example case the C1 should be in the
order of µF.
In fact, the other coupling capacitor may be in the same order assuming that this resistance
and input resistance there and also the output resistance here coming from the next stage,
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or I should say the input resistance of the next stage is may be in the same order of this
input resistance. And, hence we can say that C2 it is also in the order of C1.
So, what we have done here it is that we got guidelines that, how to design this C amplifier
to get a decent performance? Namely, the gain here it is whatever the 20 around 230 and
then output swing it is around ± 6 V. And, then power dissipation for say 1 mA of current
here it is 1 mA and 12. So, in the order of or close to 12 mW ok.
And, the cutoff frequency fcutoff particularly lower cut off frequency = 50 Hz right, for that
at least we learn how to design the circuit. Let us see the similar kind of guidelines can be
followed for CE amplifier with self-bias circuit.
So, here we do have self-bias and here again we are assuming that these informations are
given to us namely, the supply voltage is given to us VBE(on) it is coming from the data set,
the β also may be coming from the datasheet or it may be you can use multi meter or by
some other means to find the value of β.
So, here we are assuming that this informations are is given to us, we need to find the value
of different components namely the resistances here and the capacitor. So, we do have the
C1 C2 and in addition to that this bypass emitter bypass capacitor CE. And, here of course,
we do have the important informations are like this power dissipation also. And, maybe
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the lower cutoff frequency, if you if this information is provided then it will be better to
find the value of this C1, C2 and in fact, CE you also.
Now, compared to the previous circuit they approach it will be similar, but you need to
understand that the entire VCC voltage it is not available for this collector. So, we do have
VCE requirement, VCE(sat) minimum VCE(sat) requirement lower side, in addition to that there
is a voltage d c voltage require there. Note that while we are connecting the CE and if we
are applying a signal here the voltage here it will be d c.
So, this d c voltage it depends on how much the value of this RE we are taking and how
much the current emitter current or collector current is flowing through the device. Now,
since the voltage drop at this node, it is restricting the limit of this collector voltage of the
transistor, then definitely higher the emitter voltage will get lower swing.
So, I should say now the available voltage for output signal it is VCC – VE emitter voltage
divided by. So, this is the; this is the voltage of course, I need to consider the other part
also VCE(sat). And, then this is the entire swing available to us that divided by 2 may be the
possible signal swing. So, ± this is the swing.
Now, if I take higher value of this VE and that reduces the swing. On the other hand, if I
reduce this voltage at this node, which means that the value of this RE it is also getting
reduced and then you may recall that the role of this RE, namely the collector current
expression it is VBB – VBE(on) divided by the I should say not collected a to be more precise
the emitter current, divided by this RE.
And, here the assumption is that, assumption is that, R1 ⫽ R2, which you call RBB it is
much smaller than (1 + β) × RE. So, earlier we have discussed this part. And, we may of
course, we can we may approximate this is very close to IC. So, why we are looking for
this, because we like to make the quiescent point independent of β?
So, if I satisfy this condition then we can say that this is independent of β. And to achieve
this one I cannot take this RE small, if I take RE small that will reduce this RBB. So, this is
RBB that in turn it will reduce this input resistance, because RBB it is coming in parallel
with whatever rп you do have. So, if this resistance is smaller for a given value of C1 the
lower cutoff frequency it will be affected.
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And, moreover there will be a d c current, if I reduce the value of this R1 and R2 then there
will be d c current flow and that may increase the power dissipation. So, these 2 are having
some trade off the namely the output swing and the value of this RE to which is playing
the role to stabilize the operating point. And, the thumb rule it is that typically if the supply
voltage is say 12 V, the emitter voltage V DC emitter voltage we can take in the order of
1 to 2 volts.
So, the this does not mean that if you violate this range you may be having severe problem,
sometimes we may go lower side even 0.5 V it may be going towards even 3 V, but we
suggest that may be this may be a good choice. So, we can decide on this one. And, then
if we have say 12 V supply. So, from that if I use say if you use say this is the emitter
10−0.3
voltage. So, then the output swing it becomes approximately it is ± 5 V that is fairly
2
good.
So, once we decide that the output swing we want it should be 5 V this is a 2 V, then
naturally the drop across this resistance it is also getting fixed, because this is the we like
to say this operating point almost at the middle. So, ignoring this VCE(sat) part compared to
12 – 2; 10 V, we can say that this voltage in it may be 5 V.
So, that gives us 2 information; the first of all the VE, we are suggesting to take in the range
of 1 to 2 volt as an example if I take say 2 V, then VRC drop across this resistance RC. So,
434
10−2−0.3
that is . So, we can say that this is also in the order of say 5 V and then next thing
2
is that the power dissipation.
So, typically whatever the current it will be flowing here IC the current base current it will
be 2 order magnitude lower and we like to take this current may be in the order of one
order magnitude higher than the IB. So, still this current the current flowing through the
bias circuit lower much lower than this IC. So, the power dissipation still it may be
considered as it is getting dominated by VCC and IC.
So, from the power dissipation we can find what will be the value of this IC. And, that is
the 12 divided by sorry then this will be power dissipation divided by the 12 V; VCC ok.
So, once we have emitter voltage the voltage drops across RC and then IC which is also
approximately equal to IE so.
VRC VE
Now, we can directly get the value of RC and RE. So, and R E = ok. So, now, we
IC IE
obtain this to next thing is that these 2 resistances R1 and R2 should be such that, the voltage
coming here it should be consistent with the require 2 V here. So, we want this voltage
R2
drop here which is R × VCC.
1 +R2
So, that is the d c voltage here before we connect the transistor base. So, we can
approximate that this voltage it will be very close to whatever they require voltage here,
which is the emitter voltage plus VBE(on) namely in this case this is 2.6 V.
So, from that we can say that the R1 R2 ratio can be obtained right. In other words, you can
R1 VCC 12
say that 1 + = ; . So, that gives us the ratio of R1 and R2. So, either from this ratio
R2 2.6 2.6
and this information you can get the value of R1 and R2 or we can use the other the
additional information we have discussed that RBB, which is equal to R1 ⫽ R2, this should
be much lower than (1+β) × RE, RE we already obtained.
And, typically we can see that this is ≤ 1/10th of this. So, using these guidelines this is RE.
So, using these guidelines and the information we obtain here we can find the value of R1
R2. So, now we obtain all the bias resistors, next thing is that the C1. So, if you see the
input capacitance of this circuit it is in case CE it is dominating. So, for the signal the input
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resistance it will be the R1, parallel R2 in parallel with the rп. So, this circuit is having input
resistance of R pi.
So, from that we can get the Rin. Now, similar to the fixed bias circuit we can find the
expression of C1 = 1 by 2 П Rin, then the cutoff frequency, lower cutoff frequency. And
so, for a give for the value of this for a given value of this lower cutoff frequency and then
Rin. Since, this resistance may be in the order of rп, again this resistor the value of this
capacitor C1, it may be similar to whatever previously discussed value of the C1. So, again
this may be in the order of µF.
So, likewise the C2 also it will be in the same order of C1. Whereas, this CE, it will be
having another role to play to define the lower cutoff frequency. And, the lower cutoff
1
frequency decided or defined by this CE, it is coming from the g of this device, because
m
this capacitor it will be seeing the resistance of this circuit which is combination of RE and
1
coming from the transistors looking into the emitter. So, the CE on the other hand it can
gm
be defined by that and it is expression it will be similar.
So, let me clear and then write it about the expression of CE need to be followed. So, CE it
1
is 1 by 2 П then the fcutoff(L) frequency, and then of course, the resistance which is g of the
m
1 1
transistor. So, we have seen that this it is for say 1 mA of current it will be the
gm gm
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1
resistance is very small. As an example here if I consider IC = 1 mA, then gm = 26, because
thermal equivalent voltage it is 26 mV.
1
So, that gives us with this information the expression the CE, it is 1 by 2 П then gm it is g
m
it is. So, gm we do have here yes so, into 26 × fcutoff all right. And, you can see here in case
1
if I am looking for lower cutoff frequency of say 50 Hz, then this will be 2П×26×50.
10−3
So, we can write this as , then you know this is П then 2.6. So, it is almost in the order
2
of mF. So, we can say that this may be coming in the range of mF; no it will be 100s of
mF 100s of mF ok.
So, what I like to say that in case if this capacitor value it is in the order of 1 µF to support
say 50 Hz, then the required capacitor here capacitance of the CE, it is 100 µF. So, the
value of this capacitance it will be much higher than this C1 and C2 to get the same lower
cutoff frequency. So, that is about the overall design guidelines. Let me take a short break
and then again will be coming back to cover maybe a little different aspect of the design
guidelines.
Thank you.
437
Prof. Pradip Mandal
Lecture – 31
Common Emitter Amplifier (Contd.) Design Guidelines (Part B)
Welcome back after this short break and let me continue the Design Guidelines for CE
Amplifier.
So, far we have discussed about the design guidelines where or mean objective there is to
maximize the gain, voltage gain right. And, also the output swing we like to maximize
and the power dissipation probably it is given value. And, this maximization of output
swing of course, it is decided by the VCC predominantly.
So, likewise maximization of the gain is also it is decided by this VCC and thermal
equivalent voltage and of course, the output swing. And, we have seen that the Av(max) it
is to say 230 right. And, in case if we are looking for again higher than this one definitely
we cannot achieve that by this circuit, unless otherwise we modify the circuit by some
means.
Either we may have to in change this supply voltage or maybe we have to do something
here, but then and we may require the other possibility that we may cascade or multiple
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amplifier together to get higher gain. On the other hand, in case if we are looking for an
amplifier having again, which is less than this limit, then how do you design? And, of
course, having higher swing it is always better.
So, typically we like to keep the output swing towards it is maximum as much as
possible, but definitely there may be a requirement where say we require only 20 gain,
unnecessarily we will not be looking for say 230 gain. So, in case if this gain it is
specified and if it is less than this limit, then what may be the design guidelines or design
procedure to achieve that.
So, you may recall that we have discussed the gain of the circuit in case if this the CE
part is not there, then the voltage gain, Av it is expression it is , and that may be
well approximated by .
So, now in case if we are looking for low gain and then if we simply remove this CE and
then try to achieve the required gain by this ratio of this two, that may not be giving a
meaningful design. For example, if you are looking for say this ratio to be say or say this
gain, it is given to us is a 20. And, if you are taking this ratio to be 20, which means that
the drop across this resistance it will be 120 th of whatever the drop we do have.
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And, if you pick up that value of RE, then RE may not be meaningful meaningfully large
to get the operating point insensitive to β. So, as I said that the drop across this resistance
we take probably on may be one- fourth of this RC. So, this kind of value of this ratio,
definitely it will affect the bias point stability against β variation.
So, what may be the remedy for that instead of completely ignoring the CE or instead of
completely bypassing this RE, what you can do we can partially bypass this resistor? So,
what let me draw this circuit? The RC part we can keep as is and then the RE part we can
have 2 parts; one is the say RE1 and RE2 and only one of them it is getting bypassed by
CE. And, then of course, at the base side we do have R1 and R2 and so, we do have R1
and R2.
Now, these two together it is giving us RE. So, RE1 and RE2 they are helping us to decide
how to fix the voltage here to achieve whatever the operating point d sensitivity. Then on
the other hand for gain since this part it is unbypassed and this is bypassed by the CE. So,
we can say signal wise this is a C ground and this portion it is unbypassed.
So, the gain the voltage gain of the circuit now it will be RC. So, gm into rather let me
write the complete expression gm × RC divided by (1 + gm × un bypassed RE). This can
be well approximated by .
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So, now we do have the flexibility to decide the value of RE and the RE1 to achieve
whatever the gain we are looking for. So, in case if we have this ratio it is the gain is
given to be 20, let this ratio be 20, but by considering the other part of the RE, we can
have different ratio of this RC and RE which is necessary for from bias point stability.
So, say for example, this may be 2.5 k, this we may require say 1 k and this resistor on
the other hand we can make it say 250 ohms and then this part we can you say 750 ohms
and this is as I said that 2.5 k. So, that is how we can and rest of the things it is remaining
same?
So, the next thing is that in case if we are looking for a circuit having this gain, which is
higher than the limit of the maximum gain we are achieving from single stage for a given
value of VCC. So, there are two possibilities probably we can replace this resistor by
active device, that it will be discussed later. The second possibility or the other
possibility is that we can probably cascade to an amplifier to get total gain may be
multiplication of the 2 individual stages gain. So, let us see how do we find the gain of
that circuit?
Again we are going back to the circuit analysis, but it is different kind. So, say we do
have this C amplifier. So, this is fixed bias, also this is fixed bias and then as I say that
individual circuit gained it is upper limit it is only 230 and this is also 230, but if we are
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looking for higher gain. We simply feed the signal on the output coming from this point
and then we feed it to the input here.
So, that this will be getting further amplified and then we can get the final output. Now,
this circuit gain if the sizes of different resistors are given here, say RB1 it is 570 kΩ and
RC is a 3.3 k. Then earlier we have discussed that the gain of this stage and this stage
they were let me check the value are us having around 200 no 200 it will be 200, but 253.
So, the Av1 is 253 and likewise the Av2 also this is identical Av2 is 253. And, then also we
have seen that the input resistance of this circuit and the output resistance RO and then
Rin. So, the RO it is same as this RC which is 3.3 k. And, then Rin it is RB1 ⫽ rп and this rп
it is dominating.
So, it is approximately rpi1 and this is I guess it was 1.3 kΩ. So, likewise if I consider the
second stage it is also having it is own input resistance Rin =1.3 k and likewise the output
resistance. Now, if I replace this these 2 amplifiers by their corresponding model for
signal, small signal model and so, the first stage it is having it is own input resistance call
Rin1.
And, then it is having voltage gain defined by or modeled by voltage dependent voltage
source which is a V1 times it is input voltage vin1 and then it is output resistance let me
denote by Ro1 followed by the second stage. So, the second stage here we do have the
input resistance which is Rin2 and then it is having it is gain it is defined by voltage
dependent voltage source and then the output resistance Ro2
So, this is AV2 × vin2. Now, the of course, this is connected to a C ground or actual
ground actually it is a C ground I should consider in the model wise. And, then at the
input we do have the signal we are feeding here the vs. And, vs incidentally it is same as
this vin whereas, the vout; vout coming from the first stage, let me use this color this color.
So, the voltage coming here it is the Av1 × vin, this vin that voltage it is only here. The
voltage coming here is the vin2. So, the vin2 here vin2 it is not same as the voltage here. So,
what we have to do to find the final voltage here, if I call this is the final vout. So, we can
say that final vout = Av2 × vin2. And, then what is vin2 that is the voltage here, which is Av1
Vin1 multiplied by this attenuation offered by this Ro1 and Rin2 so, which means that
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So, then we can say that overall gain, now this Vin1 here, Vin1. So, this Vin1 it is
incidentally same as the vs. So, this is equal to vs. So, we can say that vout equals to vs ×
Av1, then AV sorry this Vin2 we are writing here. So, definitely I will be dropping this
part. So, I do have VA V1 and then AV2 and then vin is same as vs we already have written
multiplied by .
So, if I take this and this ratio . So, this part we are removing. So, that gives us the
overall gain. So, overall gain it is the individual gain of the stages multiplied by this
attenuation factor. This attenuation factor it is coming from the output resistance of the
first stage and then input resistance of the second stage.
So, that is how we can probably calculate in and you can find what will be the gain. In
fact, if you see in this circuit, if I consider Rout is this and then Rin is 1.3 k and then gain
individual stage gain it is 253, then the overall gain what we are getting here it is
something like, 253 each of this a V1 and Av2 are equal and so, that squared multiplied by
. So, that gives us the overall gain and I made some calculation here that is 18,000
something 18,203.
So, you can see that, how big this gain is it is quite large right. So, that is how we can get
higher gain. So, at least we understand that how to increase the gain and how to decrease
the gain by putting unbypassed RE? Now, similar kind of things it can be used for C
amplifier having sale biased arrangement. So, let you consider the other example similar
kind of example, where individual stages are the fixed bias sorry sale biased kind of
arrangement.
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Now, in this case so, the second stage intentionally I have considered it is different from
the first one. Particularly, here we do have the in the second stage we do have the CE
emitter bypass capacitor whereas, this RE1 which is remaining unbypass.
So, the first stage if I consider this one Ist, it is gain it is Av1. So, Av1 = and the RC and
RE are given here. So, that gives us . I am considering it is magnitude it is having
minus sign of course, and then likewise if I consider the IInd stage, since it is emitter is
bypassed by the CE. So, it is gain Av2 = gm × RC1 and I rather RC2.
And this gain we have seen before it is I think 207 roughly 207 or 208, 207.7. And, the
gain of the first stage it is which is given here that is I think 2.2 around 2.2. And, then
now, the resistances if you see the output resistance of the first stage RO1. So, RO1 it is
RC1. So, that is 2.7 k. And, on the other hand the input resistance of the second stage Rin1.
So, this Rin1 it is these 2 resistors coming in parallel. So, that is R3 and R4 in parallel with
the resistor here which is rп. So, we can consider this rп in parallel with the bias circuits.
And, again it is resistance keeping all of them together 1.26. So, that gives us 1.268 kΩ.
Now, this RO1 and then R sorry this is sorry this is Rin2. So, this Rin2 and Ro1 they are
making potential division and as a result that the overall gain.
444
Now, if I write the overall gain A overall the similar procedure will be following, which
is Av1 × Av2 multiplied by this attenuation offered by this RO1 and Rin2 which is .
So, if I plug in these numbers and the corresponding values of the resistances what we
are getting here it is in fact, we are getting 147.7.
In fact, if you see here, this gain it is lower than this one is not it. And, why even though
we do have gain of the first stage though it is low, but it is higher than 1 this attenuation
part attenuation factor it is killing the gain which we obtain from the first stage. In fact, it
is further reducing the gain.
So, while we are cascading we need to be little careful, that the if we are cascading in
wrong way, then this attenuation factor it may decrease the overall gain even with
respect to individual stage gain. So, on the other hand suppose if I put 2 circuits namely,
one is having bypass capacitor another is not.
The other way probably the situation it will be better, that is because the input resistance
of this circuit may be higher and it may not be very good, but at least still at least we can
say that probably the gain maybe in this order.
So, as an exercise what it can try. So, we can consider that if you remove this capacitor
making this RE2 unbypass. And, then if you put the bypass capacitor here. And, then you
can calculate what will be the overall gain.
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So, this you can do yourself and you can find this one. And, the also the procedure as I
say that though we have discussed about the 2 stage cascading together what may be the
gain. The procedure can be deployed for many stages and most important thing is that
these 2 stages need not be of same type.
When it is the same type or does it mean is that, we are analyzing these 2 circuits as
voltage amplifier. And, while you are cascading it is not mandatory to have both these 2
stages are having same nature. Say, for example, this stage may be transconductance
amplifier and this may be transimpedance amplifier. So, based on the signal type here
and signal type here we can define, what type of amplifier it is and accordingly you can
have the macro model of the first stage.
So, we can take this first stage here. And, then if I consider say this circuit second circuit.
Now, suppose this is at the input it is say voltage. And, you consider this is say
transconductance amplifier so; that means, the signal here it is current right. So, if the
signal you are considering this is current. So, the next stage it may be expecting the
signal in the form of current.
So, then this may be since it is current either it may be current amplifier, where this the
signal here it is current and the signal here also it is current or it may be this is current,
but this may be voltage and in that case the type of the second stage it will be trans
impedance amplifier.
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So, likewise then we can draw the corresponding macro model of this one. So, let you
consider this is current and then we are considering this is voltage. So, this is trans
impedance trans impedance amplifier and we have discussed about it is corresponding
model. And, the first one on the other hand based on it is input and output type this is
transconductance.
And, then based on the signal here and here, you have to see that how much the signal it
is really getting penetrated to the next circuit. So, that you can calculate accordingly you
can calculate what may be the loading effect. So, earlier we have seen that this middle
node it was the signal type it was voltage.
Now, in this case the signal here it is current. And, then the kind of analysis well be
doing is that out of the internally generated current, how much the current it is actually
going to the next circuit? Right. So, since it is transconductance the output port it will be
not only equivalent and then whatever the internally generated current part of this
internally, internally generated current it will be going through this and this. Then you
can find that how much the current it is entering, that is where defining the next stage
output voltage right.
So, here since the outputs it since it is Trans impedance output port it is termed an
equivalent model. So, this voltage of course, it is current dependent voltage source we
can say Zm into it is corresponding iin; iin2 it is here right. So, this iin2 it is not the entire
current here it is rather it is having this current flowing here.
Now, based on the value of the resistance here RO1 and the input resistance here Rin2 you
can find what will be the current here. So, the total current whatever the current is
flowing here out of that this current it will be; it will be getting divided. So, the Rin2 I
should say that iin2 it will be multiplied by whatever the current we do have here
right.
So, that is how will be getting some the loading effect and this loading effect it is I
should say this is offering the loading effect. And, the this loading effect depending on
the type of signal, you will be getting different way to analyze, but finally, you will be
getting this loading effect it will be less than 1. So, if I say the first stage first stage this is
transconductance.
447
So, maybe transconductance it is g m 1 and then the next stage Trans impedance is said
m 2. So, the overall gain overall gain it is g m of first stage multiplied by Zm of the
second stage multiplied by . So, the this is also similar only difference here it is
that, the now we understand that these 2 stages need not be of same type they can be of
different types of amplifier right.
So, likewise we can consider other different combinations and you can probably can
practice. And, in case say this models are given here. And, in case suppose the signal
here and the signal expected signal here if they are not consistent. Say, for example, this
is maybe transconductance amplifier which is producing output signal as current, but
then if the second stage it is a voltage amplifier may be expecting here the signal to be
voltage.
So, then how do you proceed? So, if this model is given to you then this part, this output
port part, you can change; that means, different colored here. I guess I can use green
color. So, this part you can change from not only equivalent to definite equivalent in that
case. So, likewise you can you know proceed in case if you have multiple such stages
and then you can find the overall gain. I think whatever the things we have planned
mostly you have covered.
448
So, far in this module in last say, 3 lectures what we have covered let me summarize.
And, the we have discussed the theoretical part before particularly the bias point stability
of CE amplifier and then how to find the gain of the circuit in through equation, as well
as numerically. And, then also we have discussed about how to find the parameter of say,
macro models either it may be voltage amplifier or current amplifier or transient variants
or transconductance.
So, those numerical analyses we have done here as a theoretical analyst or a theoretical
analysis we have done. And, then after that we have discussed about the how to get back
the gain of self-bias circuit, which is having stable operating point namely by using
bypass capacitor. And, then we have discussed lot of numerical problems starting from
individual C amplifier having either self-biased or the fixed bias and then we have also
given design guidelines, how to design a circuit?
And, also we have given some hint that how we extend the simple CE amplifier into a
bigger circuit namely, how do you cascade this circuit and then if you cascade it what
may be the corresponding gain and how to find the gain of to cascade amplifiers. I guess
that is all I do have.
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Prof. Pradip Mandal
Lecture - 32
Common Source Amplifier (Part A)
So, dear students so we welcome to this NPTEL course on Analog Electronic Circuits,
myself Pradip Mandal from E and EC department of IIT Kharagpur. So, today the module
will be discussing it is Common Source Amplifier and it is it is another basic amplifier
along with the common emitter amplifier.
So, lot of similarities are there with respect to common emitter amplifier and common
source amplifier. However, it is different also and if you move forward particularly
towards the micro electronics design and analog micro electronics design where instead of
BJT MOSFET is quite popular. So, this common source amplifier is plays a very important
role.
So, whatever the concepts it will be covered here you need to be very careful in case if you
are planning for micro electronics and VLSI design particularly in the area of analog.
450
So, in terms of our overall plan today we are in the third week’s module and we are towards
the end of it. So, what we have in our plan it is the common source amplifier we will start
with the basic operation. Some extent we have covered before, but in the present context
we may have to recapitulate. And then most important thing is that the biasing, analysis
and some numerical examples and some design guidelines.
So, whatever the concepts we will be covering today it is as I say that we will start with
the basic operating principle of common source amplifier and then biasing since the bias
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we do we are the gate and at the gate terminal the corresponding current is 0. So, at the
base sorry gate the bias need to be voltage. So, that is why voltage bias it will be used at
the gate.
And then analysis; analysis it will be having 2 parts one is for DC finding DC operating
point and the small signal analysis. And the amplifier in this case particularly for common
source amplifier typically it is mapped on a voltage amplifier as the input it is input signal
need to be voltage at the gate, but at the output the signal can be either voltage or current.
So, if the output signal it is voltage then the corresponding amplifier it is voltage amplifier.
On the other hand, at the output in case if we are detecting the signal in the form of current,
then the corresponding amplifier common source amplifier can be treated as trans
conductance amplifier and then of course, we will be covering some numerical exercise.
Now, the circuit wise you can see here this is the basic common node structure of the
common source amplified. We do have the MOSFET here and at the gate we are applying
a voltage. So, it is having the DC part along with the signal part and as I said that normally
it is considered as voltage amplifier. So, which means that the signal at the gate it is voltage
and the output of course, the signal can be either voltage or current and so we will be
discussing now at least the output signal in the form of voltage. So, we call it is voltage
amplifier.
452
So, the input has received that input signal it is basically we are feeding at the gate and we
observe the output at the drain and hence the source terminal it is common for both input
port and the output port.
So, that is why we call this structure it is common source amplifiers. So, the source
terminal it is common for both the ports. So, that is why you call it is common source
amplifier now the biasing aspect for this circuit it is as I said that it is voltage bias in nature
and yeah.
So, as I say that the biasing at least at the gate need to be voltage because the DC current
here if I say that IG = 0. So, the gate voltage need to be sufficiently high and while you are
keeping this gate voltage connected from a signal source we assume that the gate current
is 0 which is practically the case. Now, most of the time we will be dealing with this device
which is called enhancement mode device to turn it on we require a DC voltage at the gate
with respect to source.
So, we say that this VGS this voltage we required so that the device is on and typically this
voltage should be few hundred or maybe even a few volts higher than threshold voltage of
the device. So, gate to source node voltage; gate to source node voltage should be having
a positive DC to keep the device on. Not only positive DC it should be higher than
threshold voltage of the transistor.
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On the other hand, the gate voltage it should be sufficiently high so that; so that this
terminal and the drain trump terminal with respect to gate it satisfies the condition. So, that
the pinch of it is happening at the drain end or to be more precise the gate voltage or other
drain voltage should be higher than gate voltage –Vth. So, we need to satisfy this condition
not only for DC, but also whenever the signal it is present there.
So, the DC voltage that the drain it should be sufficiently high. So, that even if you have
the signal; even if you have the signal at least this minimum voltage at the drain which is
incidentally this is output voltage it should be sufficiently high and satisfying this
condition. So, to keep the device in saturation region we require this condition we may
keep this equal to also.
So, in fact to be more precise and not only the DC voltage ah, but also the instantaneous
voltage. So, I should say that Vd should be higher than or equal to the gate voltage which
may be having the DC part as well as the signal part and then this condition need to be
satisfied or we can say that Vds same source is common. We can write Vds should be higher
than Vgs – Vth.
So, the role of keeping this output voltage that is DC voltage sufficiently high, so that the
transistor remains in saturation. And as I said that the gate terminal current so this terminal
current has DC current so the biasing here you need to be voltage. So, we will be discussing
little detail of the practical circuit, but just before going to the practical circuit as I say that
we like to treat this circuit as a voltage amplifier and which means that this circuit we need
to map into a voltage amplifier model. So, we have discussed that voltage amplifier model.
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So, similar to common emitter amplifier here the model here it is given. So, this is the
voltage amplifier. So, in case if it is voltage amplifier we do have 3 important parameters
the voltage gain, then output resistance and input resistance and so these are the 3
important parameters and as I said that gate terminal for the main device the current is 0.
So, typically this vin it is coming from the bias circuit. So, the source of this vin or this vin,
it is basically from bias circuit and the so yeah.
So, the small signal equivalent circuit it will be mapped into this model in case if we like
to treat as voltage amplifier. On the other hand, in case if you are looking to map for map
this amplifier into say transconductance amplifier where the output we like to treat as
current. So, in case if you are looking for transconductance amplifier; transconductance
amplifier. So, in that case this port it will be different.
So, what will be the corresponding model? At the input we do have the Rin and at the
output port will be having voltage dependent current source. So, we may keep this polarity
in this direction or whatever the direction you would like to put as convention and then we
1
do have the output conductance. So, that is say GO = R and the voltage dependent current
O
source it is Gm trans conductance of the circuit multiplied by the input voltage and the
input voltage it is the voltage across this Rin. So, that is what the transconductance model.
455
So, this is a course it is again it depends on whatever the Gm of the device it is there, but it
is the overall trans conductance Gm. So, we will be coming back to this mapping into this
voltage amplifier model or transconductance amplifier model, but let me see the practical
circuit and as I said that and this.
Yeah, so we are going to look into the practical circuit how we generate this bias. So,
whatever the bias circuit we are discussing here we like to see what kind of practical circuit
will be having.
456
Now, let me go to the practical circuit yeah. What we have before we go into the in fact,
we do have the practical circuit in the next slide yeah. So, we will be discussing this
practical circuit, but before that let me this recapitulate what we have covered before
namely the analysis of this circuit.
So, what we are doing here it is at the gate we are applying a DC in combination with a
small signal and then that is defining the output port current. So, this current we call Ids
and this Ids it is having 2 parts. So, the IDS it is having the DC part which is coming from
this DC and also it is having AC part this ac part which is due to that this is AC signal.
And if you see the device characteristic equation we have discussed before which is
KW 2
× (Vgs − Vth ) .
2 L
Now here of course, we are ignoring this (1+λVds) part. So, we are assuming that this part
≈ 1 or namely this λ it is so small we are approximating this one that is fair enough in this
case later we may have to consider that term also, but for the time being let me draw this
part. And then as I say that it is the Vgs which is from outside we are giving which is having
the small signal part and then also it is having the DC part we do have the DC part.
KW 2
So, if we rewrite this equation we can get 2 parts one is the × (Vgs − Vth ) which is
2 L
KW
independent of the small signal part and then also we do have × (VGS − Vth ) × vgs
L
KW 2
then plus we still have one more term it which is 2 × (vgs ) part. And if we approximate
L
if we ignored this equation the second order term in this equation namely this part
compared to this linear part.
So, we are dropping this part to 0 by comparing the linear term, then what we have it is
the DC part and then the small signal part. So, this is the DC part which is representing
this DC part independent of the small signal. On the other hand, we do have the AC part.
So, we do have this part is the AC signal.
So, we can say that this signal part AC part it is the function the current signal it is function
of the voltage signal at the input or we can say that ids it is a function of the input voltage
and the remaining part of this expression it is function of the DC part. In fact, if I consider
the expression of IDS is given here this term the only the DC dependent part can be rewritten
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in this form typically one of these 2 forms it is used. In fact, we do have the third expression
also, so, but either this one or this one it is used multiplied by of course, this vgs.
So, we can say that ids equals to this part which is referred as, transconductance × vgs and
this gm transconductance of the device it is this one or it may be in this one either form it
is fine. So, both are representing the transconductance of the circuit. So, which means that
the small signal current at the ids here it is actually I should say ids in short form we can say
that gm × vgs in the linear form and then we do have the DC part.
So, as I said that the both these currents are flowing from drain to source and both the
components are flowing through this RD. So, we do have ids and also we do have the DC
part namely IDS as a result we do have a voltage here which is VDD minus this drop. So,
the output voltage; output voltage it is having an expression this (VDD – RD × the total
current). And in the total current as I said that it is having DC part as well as the small
signal part.
So, if I multiply these 2 terms what we are getting here it is the DC expression of the output
voltage and then the remaining part namely – RD × ids that gives us the small signal part.
And this is by the definition of this gm here it is or the expression of the gm here it is – RD
× gm × vgs ok, so that is the vout.
So, as I said that this part we have discussed earlier. So, we considered this discussion
actually recollection of whatever we already have discussed before in different form, but
anyway this analysis or this discussion it will be used in the practical circuit. So, please
keep this in mind that the Ids it is having 2 parts one is the DC and small signal part. Small
signal part it is gm × vgs.
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So, now let us move to the practical circuit as I said. Before we go into the small signal
analysis let me talk about the DC analysis part. So, as you can see here the DC voltage;
DC voltage here it is generated by this VDD and the potential divider constructed by R1 and
R2. So, I should say that this gate voltage or gate to source voltage now VGS earlier we are
R2
talking about VGS = VDD × alright.
R1 +R2
So, that is the DC voltage we are applying here. So, that is this voltage VGS. And then we
need to be it is important to make a note that unlike BJT, the voltage here it is remaining
unchanged even if you connect the transistor there unlike BJT where the base current it
was there and then we are ignoring the base current compared to the main current main the
current flowing through the bias circuit.
However, in this case this gate current anyway it is 0, so IG it is 0. So, even if you connect
the transistor the voltage at this point DC voltage at this point remains the same as
whatever it is given by this expression. And then once we have the DC voltage we do have
a signal coming to this gate through this capacitor.
So, this C1 signal coupling capacitor C1 it is allowing the signal coming to the gate and if
the signal frequency and this RC time constant it is satisfying a condition. So, we can say
that this most of the signal it is directly coming to the gate and making this VGS fluctuating
over this DC or I should say that small signal part it is riding over the DC part.
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So, with this arrangement we are making the series connection of the signal and the DC
voltage here. Now, with this Vgs of course, the DC and AC combination it is producing the
small signal current here and ids as I said before in the previous slide discussion in addition
to we do have IDS and the voltage here as I said that it is having a DC part which is VDD –
RD × IDS.
So, this is the VOUT part VOUT. So, that is equal to Vdd – RD × IDS and then on top of that
we do have does the signal; we do have the small signal. So, we do have the small signal
riding over this DC and then this small signal it is as we have discussed before that vout =
– RD × gm × vgs.
So, note that this provides amplification and then also it is having a minus sign. So, input
here and output here they do have 180-degree phase difference and then of course, it is
having a gain and we assume that while the signal it is riding over the DC the transistor
here it is remaining in saturation region namely the condition to keep the device in
saturation which is Vds or Vout it is higher than (Vgs – Vth). So, that is the assumption ok.
So, at this output now to suppress the DC part what we are doing here it is we are putting
the other capacitor C2 and then we are removing the DC part and then we are extracting
the signal part at this point right. So, that is the circuit here. Now, if we consider the small
signal part if we like to draw the DC part in our analysis we have to make this is AC ground
yeah and yeah.
So, we will be discussing that, but here in comparison with BJT I must see one important
thing that in MOSFET Ids Vs. Vgs characteristic curve it is it is a squared law right unlike
BJT, where the BJT on the other hand it was very sharp it was exponential. So, this is BJTs
characteristic curve and the blue one it is MOSFET.
So, what is the main important point we must convey here it is that for BJT even if you
consider say wide range of the current the corresponding voltage from ammeter to sorry
base to emit a voltage it is approximately equal to say 0.6 or 0.7 volt what do you call VBE
one.
On the other hand, if I consider the MOSFET we do have depending on different values
of currents here the corresponding Vgs it is quite different. So, the voltage here since we
are making this biasing by voltage the corresponding voltage should be such that the
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required currents are obtained. So, the DC voltage at the gate for the MOSFET and the
corresponding targets current the DC current is very important.
So, we need to frequently use this square law equation for this characteristic curve namely
KW 2
Ids = × (Vgs − Vth ) . So, this equation you have to use. So, the procedure here it is
2 L
that if you have a target value of this current and then if you know this parameter or
transconductance factor and then also the Vth from that we have to calculate we have to
back calculate rather required Vgs and then you can find the voltage here.
Will discuss this one in the numerical example again, but that is the basic difference
between the biasing of common emitter amplifier versus common source amplifier. For
common source amplifier we have to use this square law again and again whereas, for BJT
only VBE(on) is good enough all right, so ok. So, we are talking about the small signal
equivalent circuit of the practical circuit shown here.
So, before sorry most of the discussion probably which we have done just now we already
have yeah we do have the slide for the discussion, but again I like to say that this expression
of this Ids it is having the explicit expression or in terms of Vgs and this equation; this
equation is getting represented by this voltage dependent current source. It is in fact,
function of Vgs and also the Vds, but then Vds dependency it is only through (1 + λVds) part
and typically we drop this part considering this is approximately 1.
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So, we may say that Ids is function of Vgs and the Vgs it is having a DC part and the small
signal part and so this equation we frequently use. So, the previous circuit and the previous
circuit so what we have considered the practical circuit.
And so this circuit when will be analyzing we need to replace the device. We need to
replace the device by yeah we need to replace this divide by it is equivalent model and in
the equivalent model what we mean is that this Ids; Ids function of the Vgs
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So, this Ids is function of the Vgs and this equation and then rest of the things we already
have discussed that DC part here and then the DC part here how do you calculate and then
we find the relationship between ids and then vgs.
KW
So, what we have here it is ids = (VGS − Vth ) × vgs and what we said it is this part it is
L
the gm part. So, we said that ids = gm × vgs. In fact, if you look into the detail expression of
this part after ignoring this part it is as you say that it is having a DC current and these
small signal current and the small signal current expression is given here. And in that
expression gm it is very important and it is expression of course, it is function of the
equation point namely it is depending on the DC condition there.
Now, this circuit this equivalent circuit of course, it is it can be used for operating point
and if we have the value of this Vdd and then R1 and R2 from that you can find the DC
voltage here. And then you can find the corresponding DC current here and from that DC
current you can find what will be the corresponding drop here and then from that you can
find what will be the VOUT part. In addition to that the same equivalent circuit it can be
mapped into small signal also and in the small signal what you do it is simply we consider;
we consider this is AC ground.
So, in small signal; in small signal analysis what you do? We denote this DC part we make
it ground and then we short these 2 capacitors and then this part we removed the DC part
and then we take only the small signal part ids which is gm times vgs and the vgs is the
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voltage here. So, we are removing the DC part we are replacing this by vgs and this vgs it
is incidentally same as this vs assuming that this capacitor is working as a short.
So, by doing this conversion namely the capacitors into short circuit DC voltage to be 0
DC current and we are getting the corresponding small signal equivalent circuit. So, in the
next slide will be showing that the small signal equivalent circuit ok. So, we will take a
small break and then we will come back with this small signal equivalent circuit analysis.
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Prof. Pradip Mandal
Lecture – 33
Common Source Amplifier (Part B)
Welcome back after the short break and we are about to start the small signal equivalent
circuit for the Common Source Amplifier.
And, what we have said is that in the small signal equivalent circuit first thing is that we
are making the DC bias to be 0. And, then the capacitor we have sorted here and the
capacitor we have sorted here and then DC current in this voltage dependent current source
we made it 0; living behind the small signal current ids which is a linear function of the vgs
here. So, the vgs is given here and this linear function.
So, the linearity is defined by this gm. So, the expression of the ids it is given here, this part
is the gm as I was telling before or we can have another expression of the gm here. So, that
is the expression of the gm and then whatever the output we are observing here that is the
small signal output. So, just to highlight that in the signal here, it is not having any DC it
is having 0 here and whatever you are observing at the output that is also having DC equals
to 0.
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So, at the output we do have only the signal part and if you see this circuit and if you try
to analyze this circuit quickly what we are getting let me. So, let me write the expression
of this vout, it is vout equals to this what about the drop across this resistance you are getting
the current is flowing from drain to source. So, the output voltage it is – RD × ids and that
is given as – RD × gm × vgs and the vgs it is incidentally same as vs; so, that = – RD ×gm× vs.
So, that gives us the voltage gain Av define as vout small signal vout by the primary input vs
equals to – RD × gm. So, this is the first parameter of the voltage amplifier namely the
voltage gain.
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The second parameter it is the output resistance. So, if you look into this circuit and then
if you observe this circuit from outside and if you see what is a corresponding output
resistance. So, while we will be doing this as we said that we can connect a signal source
here and then we have to make this part equals to 0. So, once you make this is equal to 0,
this part it is 0. So, that makes this current it is also 0 and then if you stimulate this output
port by say vx and then if you observe the corresponding current here as ix.
In fact, the current it is only going through this resistance. So, then vx and the ix relationship
you will get is basically vx = RD × ix. So, that gives us the expression of vout which is
vx
defined as = RD; so, that is the second parameter we obtained.
ix
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Now, the third parameter it is; so, at the input port if we see and if you see what is the
corresponding resistance here. And, since the circuit here it is open namely the gate current
is 0 whether it is large signal or small signal as long as we are not considering the effect
of the capacitance from gate to source we can assume that this is equal to 0.
So, if we again stimulate this port by say vs and whatever the current we observe let you
say that this is is. And, this is incidentally it is the current flowing through this R1 and R2.
In other words, we can say that is × (R1 ⫽ R2) because this is connected to AC ground, this
is anyway it is ground. So, that is why that makes this R1 and R2 coming parallel while this
is current is flowing.
So, is multiplied by this parallel connection that gives us the voltage there which is vs or
we can say that is = vs divided by parallel connection of this one. But, whatever it is that
vs
gives us the expression . So, = (R1 ⫽ R2).
is
468
So, what do you obtain here it is Av expression of Av = – gm × RD; Rin = (R1 ⫽ R2); it is
coming from the bias circuit and then output resistance equal to RD. So, that is how the
entire circuit you can map into this voltage model. So, and the of course, the expression of
this gm it is given here either here or here.
So, as a result what we are getting there it is once we map the circuit into a voltage
amplifier what we are going to get here it is we do have Rin then Av. So, this is Av times
so, this side plus and this is – Avvin, where vin it is the voltage across the input port and
469
then at the output we do have the Thevenin equivalent output port resistance RO so, that is
the voltage model and we already obtained the expression of Av, RO and Rin.
And then of course, from outside if we are giving a stimulus say vs and then if you are
connecting some load here then you can find the corresponding primary input to primary
output voltage. Now, as we have given a hint that since the main circuit this current it is
this igs equals to 0 before we start considering the input capacitance.
So, we can say that the signal at this input port it will be always in the form of voltage. On
the other hand, the output port at the output port at the signal either can be voltage as we
are showing here, but then it can be even current also.
I have a call now; I am going to restart. So, what we are discussing here it is the voltage at
the signal at this point it can be either voltage and then we call it is voltage amplifier or it
can be current. So, or it can be current and if it is current then the corresponding amplifier
it will be called trans conductance amplifier. And, what may be the corresponding model?
At the input it remains the same namely Rin, but at the outputs will be having different
model. This is Gm × vin, note that this Gm it is in incidentally it may be same as the small
gm that is the trans conductance of the device, but in general need not be the same.
And, at the output side we do have a not an equivalent resistance or say conductance output
1
conductance GO = R . Now, these two circuits of course, they are equivalent. So, this Rin
O
and this Rin they are same whereas, this Gm and this Av must be having some relationship.
So, that this circuit and this circuit they are equivalent, namely this Thevenin equivalent
signal source need to be converted into Norton equivalent source here.
So, this GO relationship of GO and RO it is already given here. On the other hand, whenever
the circuit is open and we are getting the voltage here it is same as the internal voltage
which means that Av × vin that must be same as whatever the voltage it is getting developed
here.
So, let me rewrite this part, somehow here; so, Av × vin so, that is the open loop sorry open
output voltage. So, that should be equals to Gm × vin × RO with a – sign so, that gives us
the expression or the relationship between this Gm and this Av.
470
A
So, Gm = RV and of course, with a – sign here and what we have seen that Av it is – gm ×
O
RD and RO it was RD, Av the – sign. So, we do have one – sign here and then also we do
have one more – sign here. So, that gives us gm of the device; so, incidentally as I said that
incidentally this Gm it is same as this gm of the transistor of the MOS transistor, but in
general it need not be.
So, that is how now the amplifier sorry this is there is a small mistake, this should be
common source amplifier. So, there is the common source amplifier. So, that is how
common source amplifier we can either map into a voltage amplifier which is given here
or it can be mapped into this trans conductance amplifier.
Now, if we consider the high frequency situation; namely if we consider the signal you are
feeding here it is in the high frequency range; then we need to consider parasitic
capacitances here. Gate to source and then gate to drain capacitances and if you want to
also include the effect of λ, then at the output side it may be having finite conductance. So,
we may have to include the output conductance also which is defined as which is denoted
as RO and defined as change in Ids with respect to change in Vds.
So, if you see the corresponding model; so, what we will be getting there it is. So, this is
the high frequency model we can see that if we consider the device parasitics what are the
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components we do have it is, we do have the gate to source capacitance, this is the gate
terminal and then this is the source terminal and this is the drain.
So, gate to source we do have one capacitance internally and that is coming from basically
the this if you see if you recall the MOS structure; it is simplified cross sectional view and
this is where we do have the thin oxide. And, here we may be having the channel; so, this
Cgs is primarily due to this capacitance. So, this is source and this is gate terminal and this
is the drain terminal.
So, Cgs is this capacitance which is Cox capacitance per unit top view multiplied by W × L
and since it is in saturation you need to consider one factor two-third. And, on the other
hand if the device it is in saturation region we can say that the whatever the fringe
capacitance will be there that is primarily contributing the Cgd. So, there may be some
fringe or overlap capacitance and that capacitance is proportional with W. So, this is
something called another parameter called Cov × W and typically this is much smaller than
Cgs.
So, I should say magnitude wise this is dominating individually over this Cgd; however,
this Cgd it is at this end it is not; it is not AC ground rather it is having a signal. So, in case
if we are thinking of the small signal capacitance and if we translate this equivalent this
capacitance into an equivalent capacitance from input port to ground then we need to
consider Miller effect.
So, the effect of this part Cgs, Cgd at the input port it may be translated as equivalent another
capacitance. And, the this is due to the cgd and it is equals to (1 + this gain of the voltage
gain) of this circuit into this I should say magnitude wise Cgd. So, we will be discussing
this again later, but this is coming from the Miller’s theorem and it is referred as Miller
affected capacitance. In addition to that we are considering this rd into source resistance rd
or rds and this is coming due to Ids is having some dependency on Vds.
So, if I say that change in Ids with respect to Vds; so, that is the output conductance or we
1
can say output resisatnce and the expression here it is typically it is approximately rather this
1
= λ× IDS. So, that gives us this = λ× I .
DS
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So, this model as I said this model it is giving us the high frequency model and whenever
we will be talking about frequency response of the circuit; in the mid frequency region we
may ignore these two parts. And, whatever the in case if it is a resistive load then we may
ignore this part and then we may get the mid frequency gain.
But, if you go to say higher and lower frequency depending on the coupling capacitance
here and depending on the resistance here we may be having the lower cutoff frequency
defined by the C1 and R1 ⫽ R2. So, this lower cutoff frequency it is
1
and input capacitance is [Cgs + the effect of the Cgd which is (1
2П(R1 ⫽R2 )×inputcapacitance
+ Av Cgd)] sorry sorry; I will take it back I will take it back. So, the lower cutoff frequency
it is defined by let me rewrite here the.
So far we are talking about the high frequency effect and the low frequency effect. So, as
a result the previous analysis it was valid in the mid frequency region. And, if you go to
lower and lower frequency, the lower cutoff frequency it will be defined by fcutoff(L) =
1
, where C1 it is the signal coupling capacitor C1.
2П(R1 ⫽R2 )× C1
On the other hand, whenever we are going to higher and higher frequency we will be
having upper cutoff frequency here and that cutoff frequency it will be upper cutoff
frequency U here. So, that is 1 by 2П RO and then CL, CL we are assuming that to be
coming from the next stage or maybe whatever the load we do have.
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And, in case if we have the signal source having a source resistance say Rs and then in the
high frequency the upper cutoff frequency may be having one more possible candidate to
define this cutoff frequency, in case if we have this Rs. And, then if cutoff frequency upper
cut off frequency in presence of this Rs, it is 1 by 2 П × Rs × the input capacitance Cin and
then Cin it is having; so, this Cin it is having two part.
One is Cgs another part is contribution from the Cgd. So, this Rs × [Cgs + Miller affected
part of the Cgd namely (1 + |AV |) × Cgd]; so, that is the input capacitance. So, based on the
magnitude here this one, if I call say this is f upper cut off frequency 1 and this is f upper
cutoff frequency is 2, then whichever is the minimum we have to consider either this one
or this one.
So, that is the role of this Cgs and Cgd in the frequency response and for high frequency
analysis we must consider these two capacitors. And, on the other hand rd in case if you
consider the output resistance here including this rd then the output resistance RO it will be
RD coming in parallel with rd.
And, the gain on the other hand the voltage gain it will be – gm into this total resistance
which is RD ⫽ rd ok. Now, so we have discussed about the mapping to small signal
equivalent circuit and then biasing and all more from the analysis point of view.
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So, let me cover one numerical problem I think I do have I do have separate slide for that
yes. The same circuit here we are considering and also we have been given these
K×W
parameters that = 1 mA/V; suppose it is given to us. And, then threshold voltage of
L
the transistor is say 1 V. And, on the other hand the DC parameters are rather bias circuit
information it is given as that Vdd it is say 12 V and then R1 it is; so, 9 k and R2 it is 3 k.
So, how do you then find the gain, how do you find the gain of the circuit and or from this
information. So, what will be the procedure or sequence of calculation? First thing is the
DC operating point and to do that we need to get the DC voltage at the gate or gate to
source. So, if you consider this R1 and R2 value and then this is Vdd = 12 V, what we are
R2 3
getting is VG = Vdd × R . So, that gives us 12 × ; so, that gives us 3 V.
1 +R2 9+3
In fact, this is same as VGS so, VGS = 3 V here. Now, using this information I can say that
KW K×W
IDS which is and also 2 in the denominator, (VGs − Vth )2 . So, that gives us it is 1
L L
mA by 2 then 3 V is the (VGs − Vth )2 . So, that gives us 2 mA of quiescent current IDS.
So, the quiescent current flowing through the circuit IDS it is 2 mA and the value of this
RD ok; I think the value of the RD we also need to find the operating point. Anyway let me
consider that RD is also say 3 k and so, if this RD = 3 k then VOUT = Vdd – RD × IDS.
So, that is equal to 12 V – RD it is 3 k into 2 mA so, that gives us 6 V. So, the DC voltage
here it is 6 V. So, at the input so, at the input what you are getting here it is 3 V DC here.
So, this is 3 V, I should say Vgs and on the other hand at the output we are getting DC
voltage it is 6 V.
So, this is Vds and then what is the value of the gm? Now, to calculate the gm it is so, we
obtain IDS we obtained VOUT; now next thing is the gm. So, if you recall the expression of
KW
the gm it is ×(VGs − Vth ) right.
L
So, that is k is given as 1 milli so, multiplied by (VGs − Vth ); so, 1 × this is 2, 3 minus 1;
so, 2 mA/V. So, the gm it is 2 mA/V; so, the gain voltage gain Av. So, that gives us Av = –
(gm which is 2 mA/V) × (this RD which is 3 kΩ).
So, that gives us a gain of only – 6 of course, this is say for gain, but whatever it is we
assume that for the time being let you assume that is what we are looking for and that may
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be sufficient. And so, at the input at the input if we are giving say sinusoidal signal at the
output; so, we are expecting that corresponding effect coming here.
So, let us try to see what is the corresponding signal swing we can get or maximum swing
we can get. Note that at the input we are giving signal which is say one-sixth of the signal
and for the time being if I say that the output or with this Vds variation is much more than
whatever the variation we do have at the gate.
And, we do have the 6 V here and we do have the 3 V here. So, while it will be going to
the valley of course, this may be going to the peak here. And, if I ignore this variation
compared to this much of variation then the gate voltage DC gate voltage it is 6 V and gate
voltage sorry drain voltage DC it is 6 V and then gate voltage it is close to 3.
So, the minimum possible drain voltage we can say that (3 V – 1 V). So, the valley here it
can be as low as 2 V, if I ignore this variation and then the corresponding signal swing
from 6 V to reach to this 2 V, it is 4 V, 6 – 2 V. So, that is what we can say that the output
swing it can it can be as high as 4 V, but in case if we are also considering this variation
you need to consider the gate voltage going slightly above. And, based on the magnitude
4
of this gain you can say that the if this is 4 V the corresponding variation here it is 6.
So, then of course, the device it is just entering into the saturation anyway approximately
we can ignore that part and then you can say that the output swing in addition to this the
output swing. So, output swing it is plus minus at least lower side we had seeing that this
is 4 V positive side of course, it is not having any problem it can go higher.
And, to get this maximum swing of course, the required voltage at the input it will be and
4V
this ± . I think that is what I like to cover and so, let us see what are the things we have
6
covered in today’s module.
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Yes. So, basically to today’s primary discussion it was common source amplifier. So, we
started with the operation of the circuit and then now we have talked about the biasing of
the common source amplifier. Since, the gate voltage gate node is having 0 current we can
say that it must be through voltage bias. And, then along with the voltage bias which is it
is getting obtained by potential divider R1 R2 from the Vdd we need to consider signal
coupling capacitors at the input port and output port.
And, then we have discussed about the DC operating point analysis; so, we have basically
the MOS transistor it has been replaced by equivalent circuit which it is representing the
equation IDS in terms of VGS. And, then we have seen the small signal equivalent circuit
where the transistor it was replaced by gm × vgs and then we got the expression of the at
the output gain.
Then the small signal equivalent circuit after dropping the DC part we have mapped the
amplifier into voltage amplifier where the input signal it was voltage and then output also
was voltage. The other possibility of mapping the amplifier common source amplifier it is
trans conductance amplifier and they are the though the input remains voltage and then
output it was in the form of current.
And, in the trans conductance what you have seen is that trans conductance of the amplifier
it is incidentally same as trans conductance of this MOS transistor in this case. And, then
we have discussed about numerical examples where different biasing arrangements and it
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was given. And, then what we have seen is that the voltage gain it is quite low, magnitude
wise it was we obtained for this numerical example it was only 6. The output swing on the
other hand so, output swing we obtained it was ± 4 V approximately.
So, probably for 12 V supply output swing it is I should say it is lower. Now, if I compare
this numerical example of this common source amplifier with the common emitter
amplifier performance you may recall that the for common emitter amplifier the voltage
gain it was much higher in the range of 200. So, definitely this is higher than the 6 and
also the output swing in the common emitter amplifier it was in the range of ± 6 V ah; so,
close to ± 6 V.
So, we can say that performance wise common emitter amplifier it is better than the
common source amplifier. So, both the gain wise and the output swing wise. Then the
natural question is then why do we go for common source amplifier? The answer is that
whenever we will be going into micro electronics and VLSI design where MOSFET
transistors are they are the primary elements. And, to realize this amplifier voltage
amplifier we need to use MOS transistor rather than BJT.
So, I should say that whatever the technology will be it will be available to us and if we
integrate analog and digital circuit together, then it is better to explore this common source
amplifier. And, in case if we are not happy with this particularly the gain part maybe we
can try to use some other alternative.
Namely, instead of using say passive load we need to consider active load, we need to
consider active load. So, instead of RD we can use probably active device here or active
load. So, in case if we are successfully replacing this one, there is a possibility of improving
this gain and practically that is what it is done.
So, probably we will see that down the line whenever the situation permits we will replace
this passive load by active load. The other information I like to capture here it is that
particularly in the context of micro electronics and VLSI design situation in this numerical
K×W
example, in today’s numerical example we have considered that it is given to us.
L
This is the case whenever we are doing the board level design we assume that this not only
this parameter, but also aspect ratio of the channel of the device is given to us. But, when
you consider VLSI design the additional flexibility is that the designer can decide what
478
will be W and L. So, in the analog VLSI design W and L will not be given rather it will be
the freedom it will be given to the designer. And the designer of course, have to make a
meaningful selection of W and L to further optimize the performance of the circuit.
So, whenever we will be going for advanced level subject such as analog VLSI design then
we will be dealing with variation of the W and L or rather how do you select W and L of
the devices. But, in this subject in analog electronics we assume that this entire quantity
K×W
namely is given to us. And, then we proceed for design namely selecting the different
L
bias components and the load; I think that is what we like to cover.
479
Prof. Pradip Mandal
Lecture – 34
Common Source Amplifier (Contd.)
Numerical Examples and Design Guidelines
Yeah. Welcome to Analog Electronic Circuits NPTEL course; myself Pradip Mandal from
E and EC Department of IIT Kharagpur. So, we are continuing this topic of Common
Source Amplifier and what we are planning to do it is we have done the analysis. And,
today we will be covering some of the design guidelines, how we have to select values of
different components.
So, our plan today it is yeah; so, the concepts we are going to cover here today is this
guidelines of common source amplifier design. And, we will be going through numerical
exercise through that exercise we will know that how to select the value of the resistors
may be capacitors also some extent.
480
Now, so far what we have covered is the analysis; so, what we have done it is suppose you
do have this common source amplifier and then in case the device components or other
K×W
device parameters are given to us namely . And, then threshold voltage of the transistor
L
if it is given and also the supply voltage is given to us. In addition to that if the values of
R1, R2 and RD are given. Then what we have seen is that how to calculate the gain of the
circuit, how to calculate the input resistance of the circuit; those things we have discussed.
And, also we have seen the sequence of those calculation; namely we have started with
DC operating point namely DC voltage at gate node. And, then followed by calculating
the IDS which is of course, function of the parameter here and the (gate to source voltage –
Vth) from that then we have calculated gm, then voltage gain and so and so. So, whatever
the things we have done and the procedure we have followed it is referred as the circuit
analysis.
You may say that it is theoretical analysis or and or numerical analysis. Today we are
going to discuss the reverse process, namely in case the circuit is given to us and the circuit
topology is given to us along with device parameters and the supply voltage is given to us.
And, we need to find; we need to find the values of these resistors namely the bias resistors
R1, R2, then RD. And, the values of those components should be such that we should be
getting meaningful operation of the circuit.
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Namely at the output we should be having good signal swing and to achieve that what may
be the voltage here we like to obtain and then to get that DC voltage at the gate what may
be the ratio of R1 and R2 those things we will do. So, as I said that the main focus of today’s
discussion is primarily to find rather to how to select the value of different bias
components.
So, let me go to the next slide where we do have the have the problem defined, as I said
that here the circuit topology is given to us. And, what we need to do it is the circuit
topology is given to us and the value of this device parameters are given to us. The supply
voltage it is given to us and we need to find the value of resistors and capacitors, the value
of the capacitors may be obtained whenever we will be talking about frequency response.
But, primarily we will be finding the method or procedure to find the values of the
resistors. Now, how do you? Start first of all of course, while we will be keeping the circuit
in appropriate region of operation namely the transistor should be in saturation region.
And, also the DC voltage and the drain should be such that whenever we do have signal;
so, along with the DC we are expecting some signal will be there. So, whenever the signal
it will be coming here even if the signal is having good swing the transistor should remain
in saturation region.
Namely the gate voltage and drain voltage condition should be such that the pinch of it is
it is remaining there. So, if you consider that then you may say that the for a given VGS
482
voltage; so, if I say that we do have some VGS and then that (VGS – Vth) is the lower limit
of the drain voltage. So, if you see the output voltage its range of the output voltage in one
side we do have the lower side we do have (VGS – Vth). And, on the other hand higher side
it is of course, the supply voltage Vdd.
And so, we may give equality also, but maybe we can at least we can say that the output
voltage should be lined well within this one. And so, for meaningful operation a we want
both the positive swing as well as the negative swing may be equal. And, hence we like to
keep the DC voltage at the drain such that we should be getting both positive side as well
as the negative side, equal means the VDS should be middle of these two voltages.
In other words, if I take the average of these two voltages so, that gives the DC voltage.
And if we do so, if the DC voltage it is it is set at the average of this two then we can get
the positive side swing, a negative side swing it will be equal. And, at the limiting case the
Vdd −(VGS −Vth )
swing it will be . So, I should say the upper limit pictorially the upper limit
2
here it is Vdd, on the other hand lower limit it is (VGS – Vth).
And, if we are setting ah the DC operating point at the middle of this; so, we can say
whatever the total swing we do have divided by 2 will be the output swing. So obviously,
we want this swing should be as high as possible and this is the limit. So, if the DC
operating point it is skewed towards the Vdd of course, positive swing positive side swing
it will be less. On the other hand, if it is coming on the lower side, the negative side it will
be less. So, the practically what we should try is that the DC operating point we should sit
to this value. So, that is the first guidelines and then second one is the voltage gain.
So, once we obtain the gate voltage probably from that we can find what is the; what is the
corresponding IDS. So, this is IDS Vs. VGS characteristic curve. So, as we have discussed
before once we fix this operating point with respect to that operating point we can say that
slope of this line is the gm. So, that gm multiplied by RD that is the gain of the circuit. In
2IDS
fact, if you replace this gm by its expression earlier we have discussed which is ;
VGS −Vth
so, that gives us the gain.
So, then where do we start from? In case the device parameter is given to us and then also
we are expecting that the device the current range of the device may be given to us; that
means, the current should be maybe somewhere in maybe sub mA to maybe 10 mA or so.
483
So, based on that we may decide to ah use some IDS value and from that using this
K×W
parameter particularly and Vth we can we can calculate what is supposed to be the
L
value of this (VGS – Vth). And, then that will be helping us to find what will be the value
of R1 and R2.
So, let us see how we proceed and as I said that we will start with IDS and then will be ah
subsequently following the steps.
484
So, yes so, let me start that process yeah. So, what we have here it is just to start with as
an example let you consider that IDS = 0.5 mA. So, if 0.5 mA, IDS is our target which means
that we can follow the IDS Vs. VGS characteristic curve and so, this IDS Vs. VGS
characteristic curve. In fact, this characteristic curve equation we already know namely IDS
KW
=2 × (VGS − Vth )2. And, then we do have (1+λVDS) part that maybe we can ignore; so,
L
approximately you can say that this is approximately 1.
So, you may drop this part. So, since this parameter and this parameter is given to us and
also we do have a target value; so, from that we can simply find what will be the
corresponding VGS. In fact, if you use this equation namely 0.5 mA equals to 1 mA/V2 by
2 then (VGS − Vth )2 . So, that gives us (VGS − Vth ) = 1 V or VGS = Vth + 1 V. So, this 1 V
normally it is referred as overdrive voltage ∆VGS. So, the VGS = the Vth which is coming
from the parameter given to us 1 V and (VGS − Vth) which is we obtain that it is 1 V.
So, that means, to obtain this 1 mA of current we need this VGS should be 2 V. Now, that
2 V we are generating from 12 V supply by using this R1 and R2. So, we can say that we
R2 R2 2V
can use this equation VGS = Vdd × R . So, from this we can say that R = 12 V ,right.
1 +R2 1 +R2
1
So, we do have essentially 6 or we can say that so, this gives us R1 = 5 R2; so, this is one
relationship. So, we can say that R1 = 5 R2.
So, we obtain the ratio of R1 and R2, but we need absolute value of R1 and R2. So, how do
you find? This is again it is just guidelines, it is not necessary that this bias current we may
take almost 10 % of this IDS. So, we can say that Ibias = 0.1×IDS and this current since the
DC current to the gate is 0.
12 V 12
So, we can simply say that this Ibias = R ; so, that gives us (R1 + R 2 ) = 0.05 kΩ. So, that
1 +R2
means, it is how much? 240 kΩ. So now, I do have (R1 + R 2 ) = 240 kΩ and also we do
have R1 = 5 R2 which means that R2 = 40 kΩ and then R1 = 200 kΩ.
So, to achieve this 2 V or to be more precise to achieve this target current then we can we
can directly use this R1 and R2. In fact, you may find some other solution in case if you are
looking for different bias current, but this is one meaningful solution. And, we want this
current should be may be smaller because the power dissipation of course, and on the other
hand in case if this current is higher which means that R1 and R2 if they are smaller. Then
485
the lower cutoff frequency which will be coming from the C1 and input resistance which
is essentially R1 ⫽ R2 that lower cutoff frequency it may get affected; namely it may go
towards the mid range of the amplifier right.
So, what do you obtain here it is the value of this R1 and R2, namely R1 = 200 K and R2 =
40 K. Now, we need to find what will be the corresponding a meaningful value of this RD.
So, in the next slide we will be discussing about how to find this RD. So, of course, we this
is our target yeah.
486
So, how do you proceed to find RD? First of all, as I say that for IDS = 0.5 mA, VGS we
obtained, now the VGS the voltage here it is 2 V, threshold voltage it is 1 V. So, the lowest
possible voltage here it is and the voltage here it should be 1 V; so, this is the lowest
possible value; then higher side we do have the 12 V. So, to get the maximum swing we
should target this equation point at the drain node should be middle of this two and that
will be giving us the maximum swing.
So, the maximum output swing which we already have discussed that Vdd – (VGS – Vth).
So, this is the lower limit by 2, to obtain this maximum output swing what we can do we
can target this equation voltage to be half of this to limit. In other words, this I-R drop
namely RD × IDS should be such that this voltage it will be middle of this two. In fact, if
you consider that RD × IDS so in fact, I should write that the output coefficient point is
rather Vdd – RD × IDS. And, this is what we are targeting equals to middle of these two limit
Vdd +(VGS −Vth )
namely right.
2
So, this is our target to get the maximum swing of this one and from that if we rearrange
this equation what we can get here it is IRD equals to Vdd. So, from this equation we can
Vdd −(VGS −Vth )
get RD = . In fact, this is simple, we simply take the IDS here and whatever
2IDS
the drop we are getting it should match with this part and so, that gives us the
corresponding value of RD.
So, let us see what is the value you are getting using this equation Vdd we do have 12 V.
So, 12 – (VGS – Vth) that is 1 Vand then divided by (2 × 0.5 mA); so, that gives us 11 kΩ.
So, this RD we obtain this one. So now, we obtained this RD, R1 and R2. So, with this bias
or with this design let us see what is the performance we are getting.
487
So, the performance which whatever the design just now we obtained namely the R1 = 200
K and then R2 = 40 K and RD = 11 K. What are the performances matrices we are getting?
Vdd −(VGS −Vth ) 11
First of all the output swing which is actually ; that means, 5.5 V. The
2 2
possible swing here it is actually ± 5.5 V right and the corresponding gain what we can get
is gm × RD.
In fact, we can write the expression of the gm in terms of IDS and (VGS − Vth ); so, which is
given here this is the gm part. So, in this design what we have it is 2 × IDS is 0.5 and then
(VGS − Vth ) is 1 V and of course, this is mA multiplied by 11 kΩ; so, that gives us the gain
of 11. So, this is one performance parameter and this is also another one, in addition to
that input and output resistances of the amplifier. So, the input resistance in this case the
input impedance of the MOS transistor gate it is you may approximate it is very high.
So, we can say that Rin it is primarily coming from the bias circuit R1 and R2 or to be more
40×200 100
precise this is R1 ⫽ R2 and this is . So, that gives us so; that means, around 33.3
240 3
kΩ so, that is the input resistance and the output resistance it is of course, this is we are
ignoring this λ. So, lower side the impedance coming from the transistor it is you may say
it is very high. So, output resistance on the other hand it is RD which is 11 K.
So, the to summarize we are getting the performance of the circuit is the output swing,
gain then input resistance and then output resistance. So, this is here of course, we are
488
starting with IDS = 0.5 maybe you can work out yourself by targeting maybe different
current and, let us see what may be the possible yeah.
So, in case instead of considering current 0.5 mA, now if you say target current of maybe
2 mA. So, what kind of changes are happening here? First of all, if you follow the same
procedure (VGS − Vth ) with this target (VGS − Vth ) you will be obtaining equals to 2 V and
then VGS actually it is 3 V. So, to get this VGS, 3 V from 12 V supply what will be getting
R
here it is R1 equals to we do have 12 V we like to get 3 V. So, drop across this one is 9 V,
2
drop across this R 2 it is 3 V. So, the ratio here it is actually 3 by 1 or R1 = 3 R2 and then
again if we target a bias current it is just 10 % of these IDS.
So, from that we can say that so, this is 0.2 mA and Vdd is 12 V. So, that gives us (R1 +
R2); (R1 + R2) = 60 yeah 60 kΩ and in addition to that we do have R1 = 3 R2. So, if I
combine this two what will be getting here it is R2 = 15; 15 K and R1 = 45 K right. So, that
is the value of R1 and R2, you may you may recall that we obtain different value of this R1
and R2 while you are targeting 0.5 mA. Now, next thing is that we can find what will be
the corresponding RD; probably I do have another slide for that yeah.
489
So, once we obtain the VGS = 3 V with R1 with R1 = 45 K and R2 = 15 K. Then RD to get
the maximum swing what you have to do that and this is the maximum swing the
corresponding RD it becomes 12 V, Vdd – (VGS − Vth ) is 2 ohm now divided by (2 × 2 mA).
10
So, that gives us sorry this is 10 V. So, this is , 2.5 kΩ. So now, you can see the change
4
earlier RD it was 11 kΩ, now it is 2.5 kΩ and the voltage here it is 3 V. And so, the lower
limit of this voltage here it is 2 V, this is supply voltage is 12 V; so, our target voltage here
it is 12 – 2.
So, the upper and lower limit if I see; so, we like to place it at the middle of 12 V and 2 V
which means that the average of that it is 7 V and the drop across this resistance to get this
DC voltage of 7 V. So, here we require 5 V and 2 mA of current is flowing and hence 2.5
kΩ will be giving us the drop across this RD = 5 V. So, that gives us the RD and the
performance of this circuit in fact, we already have discussed in our analysis part where
we said that the current it was 2 mA right.
490
And once of course, then performance wise I guess I do have another slide for that, but let
me see you know; I let me here itself I can write the other information namely the with
2IDS
this values of R1, R2 and RD the gain the voltage gain = gm × RD. So, that is (V × RD.
GS −Vth )
2 × 2 mA ×2.5 K
So, we do have ; so, that gives us a gain of 5. So, earlier we are getting a
(VGS −Vth ) is 2
gain of 11, now we are getting a gain of 5 and the input resistance on the other hand ah let
me use different color.
15 ×45 45
So, input resistance on the other hand it is R1 ⫽ R2 so, that is ; so, that is . So, that
60 4
is equal to 11 point whatever 25 and the output resistance of course, the same thing; so,
this is the output resistance. So, that is the guidelines to design common source amplifier
to get good swing, a meaningful gain and so and so yeah.
491
So, the what are the things we have covered here it is basically from the device parameter
and the supply voltage information. And, if we start with a meaningful current then we can
find the value of different resistors. Once we find the resistances particularly input
resistance from that you can find what will be the corresponding C1, because if I combine
1
these two namely the first coupling capacitor; so, that gives us the lower cutoff
Rin ×C1
frequency. And, on the other hand C2 typically we may take in the same order of C1; so,
that signal can propagate from the output node drain node to the subsequent stages.
So, this may be clear once we covered the frequency response of the amplifier, but yeah
this is this is what the guidelines we should follow. If the lower cutoff frequency is given
to us typically we may target say 10 maybe 10 Hz. So, we can convert this Hz into radian
and from that you can find what will be the corresponding C1, its value may be coming in
the range of µF. So, we have discussed these guidelines through this numerical exercises.
Yeah, I think that is all to cover now and in the next session we will be moving for the
frequency response yeah.
492
493
Prof. Pradip Mandal
Lecture - 35
Frequency Response of CE and CS Amplifiers (Part A)
Yeah, dear students welcome back to this NPTEL online program on Analog Electronic
Circuits, myself Pradeep Mandal from the E and ECE Department of IIT Kharagpur. We
are going through different modules and presently we are in the 4th module of this
course. And, today’s topic of discussion it is Frequency Response of CE and CS
Amplifier; Common Emitter and Common Source Amplifier.
In the previous module we have seen how to find the gain of common emitter and
common source amplifier. And, today what we will see that if we change the frequency
of the input signal how the gain of the circuit whether it is common emitter or common
source amplifier, it is it changes with frequency. So, the overall situation if you see the
flow wise as I say that we are in the 4th module.
And, today we are going to discuss in the 4th module we are going to discuss about
frequency response of common emitter and common source amplifier. And,
subsequently we will be covering the frequency response considering high frequency
model. So, today primarily we will be ignoring high frequency model of the BJT and
494
MOSFET and whatever the frequency response we will be seeing it is due to the
coupling capacitor and then bias circuits and so and so.
Now, what do we have in this plan, in this module; it is the or rather today and the next
classes are the following. So, we are planning to cover as I said that we are going to
cover frequency response of common source and common emitter amplifier. To
understand that first what we will do that we will revisit the frequency response of R-C
circuit and C-R circuit. And, then based on the R-C and C-R circuit we will be talking
about the transfer function of a typical system R-C or C-R combination.
And, then we will also discuss about what is the relationship between transfer function
and then frequency response and then location of the pole zeroes in Bode in Laplace
domain transfer function. So, and then what is the relationship between the pole and
zeroes and the cut off frequency in the frequency response. So, those things we will be
discussing in detail with simple R-C and C-R circuit as an example. And, then using that
knowledge you will be discussing about the frequency response of common source
amplifier; particularly the analysis part we will be covering today, the numerical part we
will be covering on the next day.
So, today’s plan is only up to the analysis and then also we will be discussing about the
frequency response of common emitter amplifier having fixed bias. And, there also we
will be going only up to the circuit analysis, numerical examples that we will be covering
495
in the next class. And of course, subsequently we will be discussing about the CE
amplifier having self bias and its frequency response it is slightly tricky compared to the
fixed bias. So, we like to consider this frequency response analysis in a separate lecture.
Then also we do have planned to cover design guidelines, once we once we recover the
frequency response.
I like to mention one thing in the previous module we have covered numerical examples
of common source amplifier, but we did not discuss about the design guidelines of
common source amplifier. If time permits we will be covering that after covering the
frequency response. So, the design guidelines we will be covering both CE and CS
amplifier considering frequency response of the amplifiers. So, to start with let we go for
the R-C and C-R circuit; I must say that this is more like recapitulation of whatever you
know.
And, to start with let we go with C-R circuit. So, the C-R circuit is given here, the input
we are applying across the series connection of C and R. And, then the output we are
observing across the resistance. And the how do we find the frequency response? First
we go to the Laplace domain then we analyze the circuit. Namely, let we draw the
equivalent circuit in Laplace domain where the C part its impedance it is and for the
resistor on the other hand it is directly it is same as R.
496
And, then the input we are feeding a signal which is Vin time domain whereas, in Laplace
domain we call this is Vin(s). So, this is in time domain whereas, in the Laplace domain
the signal it is in Laplace domain. So, we are using different notation here Vin(s). And,
the output on the other hand we are observing across this resistance and the
corresponding output, it is Vo(s). So, if you simply analyze this circuit what we are
getting is that Vo(s) = R into the current flow which is Vin(s) divided by the series
connection of R and the capacitor; so, R + .
So, if we simplify this equation what we are getting is that so, this becomes sCR in
the numerator and in the denominator we do have 1 + sCR. So, this is what the input to
output transfer function in Laplace domain. So, this is what we are we have summarized
here. So, Laplace domain it is . Now, this in the Laplace domain of course, the
s is basically I should say it is having two part; two parts one is the real part and then the
imaginary part.
And, corresponding to each of this s the basis function it is est which is essentially eσt ×
ejωt. Now, this σ it is significance of this σ it is in case the signal amplitude it is changing
with time, then that may be captured by this σ part. And, in case if the signal frequency is
changing or rather if we have sinusoidal component and its frequency it is represented by
this ω.
So, on the transformation of the transfer function from Laplace domain to the frequency
domain it can be obtained simply by considering rather dropping this σ = 0. In other
words special case of est it becomes ejωt. Or, we can say that in the transfer function in
Laplace domain whatever the s we do have, if we simply replace this s by jω, then
whatever the transfer function we will we will get that that basically gives the frequency
response of the circuit.
497
So, what we said here it is if we have say Laplace domain transfer function from that we
can get the frequency domain transfer function or rather frequency response can be
obtained by this one. Now, if we say that this is input to output transfer function in
frequency domain or Fourier domain, then if we take the magnitude of it; so, it is
basically it is a complex number.
And, if we consider its magnitude and phase then we can see how the system behavior or
this network behavior changes with so, the frequency of the stimulus. In other words the
whenever we are talking about frequency response of a circuit say in this case this C-R
circuit, what does it mean is that how the behavior of this block it is changing with the
frequency of the input stimulus. And, whenever in this case in this study whenever we
are talking about behavior is basically the output to input ratio, we may call it is voltage
gain or transfer function or whatever it is.
So, this transfer function it is changing with frequency and that has been captured by this
equation. So, if we simply make a plot of this function with ω, then we can get how the
individual signal it is getting transformed before it is arriving to the output. So, if we plot
in fact, the frequency response it is having as I said that since it is a complex number it is
having two parts; one is the magnitude part and then the phase part.
498
So, if I consider that the magnitude part namely and then if you take mode of it
and then if we plot with respect to ω. In this case what will be seeing here it is due to the
presence of ω in the numerator at very low frequency or if I consider ω = 0, due to this ω
in the numerator it will be 0. And, then as you go higher and higher so, probably at then
this part it may be prominent compared to 1.
And, then beyond some frequency it becomes this part it becomes dominate over this
one. And, whenever this the jωRC part it is dominant over 1, then it becomes the whole
ratio it becomes 1. So, in other words we can say that beyond some frequency it becomes
1. So, it is going to be the value it is going to be 1. And, the change over from this linear
part to whatever you say the constant part it is happening at a frequency, where ωRC this
part it becomes 1 or if I say that this is a particular ω called say ω1.
So, the corresponding ω1; so, this gives us this ω1 = . In fact, what is the significance
of this part? It is before this frequency ω1 we are assuming that 1 was dominating over
ωRC magnitude wise and then beyond this point we started saying that you know this
part it is now it is going to be dominant. And, exactly at this point at ω1 = both this
part and this part they are equal. So, if I ignore one of them I may be getting the
approximated 1 say in this part I may be getting the approximated 1 which is linear
function of ω.
On the other hand, if I say that this part it is dominating namely the jωRC part it is
dominating over 1, then it becomes constant. So, again if I consider the second part it is
completely dominating then I can get another approximation. This two approximation
curve they are intersecting precisely at the same point, where ωRC it becomes 1. In fact,
yeah so we can many a times instead of going through this blue line which is the actual 1
for simplicity we consider these two linear parts. And, this is what we said the magnitude
part.
In fact, if you see here from this equation if I consider the magnitude it is ωRC in the
numerator and in the denominator it is a √ . So, that is the gain plot of the
transfer function. Now, since it is a complex number, it may happen that if we are giving
a sinusoidal signal here at the output while it is going through this system, not only its
499
magnitude may be getting changed because of this magnitude variation ah, but also its
phase might get shifted.
So, that phase shift can be captured by considering whatever the phase we can see here.
So, the next to the gain variation with respect to ω we can also observe the corresponding
phase variation. So, if you see in this circuit or this transfer function if we plot the phase
of this ; what we have in the numerator? We do have the jω part and in the
denominator we do have 1 and jω part.
So, at low frequency before this ω1 frequency what you call it is cut off frequency we
may say that so, the numerator part it is primarily defining the phase. And, the
corresponding phase here it is you may say it is 90° +. And, as we are approaching to this
ω1 frequency the corresponding phase it is becoming 45°. So, exactly at this point it is
45°. And, beyond that once you start increasing this ω further, then ωRC it may be
dominating and then this ω and numerator ω and rather numerator j part and denominator
j part they are getting cancelled.
And, it becomes basically 1 real part so, which means that phase shift it will be 0°. So, in
other words we can say that suppose we stimulate this circuit by one frequency maybe at
this point. And, then if I say that this is ω say x, the output will be obtaining that you can
see that compared to 1 this is much lower. So, at the output we can say that the amplitude
it will be diminishing, in addition to that it will also be having the phase shift almost 90°.
On the other hand, if I change this frequency to exactly at ω1, then the magnitude here it
will be it is magnitude change it can be obtained from this one. And, if you see that at ω1
this part it becomes 1 and this is 1 so, we can say that this part is of course 1. So, at ω1
the precisely this value it is . Approximated equation it is saying that it will be 1, but
√
actual value if you see the blue line and if you consider the equation there in the
denominator you will be getting √ .
Which means that if we stimulate this circuit with a frequency exactly equal to ω1, the
output at the output whatever the signal will be getting it is times of the input signal
√
amplitude. And, also there will be 45° phase shift in fact; this is phase lead I should say.
500
And, then if we if we further change this stimulus to even higher frequency maybe
somewhere here.
And, then if we see the gain plot it is showing that the its magnitude it will be; it will be
almost the same at the output with respect to its corresponding input and the phase shift
is also going to be almost 0. Which means that this meaning of the gain plot and phase
plot in fact, intuitively if you see that if we feed a signal here sufficiently high frequency,
where in case if the capacitor is almost behaving like a short circuit then at the output we
will get the same input signal coming there. So, that is corresponding to say maybe a
frequency at this point where now the gain it is 1 and then phase is 0.
On the other hand, if you consider now very low frequency then the signal it may fail to
propagate here and at least the magnitude wise that you can say that the signal did not
arrive there. So, if I based on for a given value of C and R or CR or RC time constant
depending on the value of this stimulus frequency the behavior of this circuit you may
say that either it is passing the signal to the output or it may be blocking the signal. In
fact, if you see here the high frequency region the circuit it is working like a pass circuit.
And, on the other hand in the low frequency region, if you see in the low frequency
region they the circuit it is attenuating the signal which means that the signal is the
circuit it is working like a filter. And, this behavior of the filter it is like say a high pass
kind of nature. So, whenever we are talking about as I said the frequency response is
basically we want to see how the circuit behavior changes with the frequency of the
stimulus. Now, this two plots; these two plots are as I said that they are storing the
information of the behavior.
Typically, instead of considering these two plots the commonly used plot it is something
called bode plot, where this ω the frequency it is in log scale. And, and the corresponding
magnitude here instead of considering magnitude, the corresponding data is converted
into decibel form. So, instead of taking only the magnitude, it is log transformed with a
base 10 multiplied by 20. It is having some reason why we multiply with 20, but at least
to make you understand that why we consider log and why do you consider log scale is
basically capturing wide range of the variation of the gain; particularly in this portion
and in this portion.
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This is where the gain it is going to be 0 and also along the frequency axis we like to
cover wide range of frequency all the way from almost 0 frequencies, 0 Hz to maybe in
the range of maybe 100’s of MHz or it may be even GHz. So, in case if you want to keep
this ω in linear scale of course, it will be difficult to cover that entire scale. And, getting
the inside of the variation of the behavior over the frequency, wide frequency range.
So, the natural tendency is to use this log scale. So, that within a same graph we can see
the behavior of the circuit over a wide range of frequency. So, whenever we are going to
change this log scale as I said the corresponding plot name it is different and it is referred
as Bode plot.
So, what is this Bode plot? Is as I said basically this is a gain plot and phase plot, but the
instead of gain or you can say magnitude of the transfer function it is 20 log10. And,
multiplied the ( ) and of course, they are in frequency domain and this is of
course, the ω. Note that in this is in log scale.
So, once say this is in log scale; obviously, we cannot reach to the 0 frequency, we may
be starting with some +ve frequency. Say for example, this may be 1 Hz, this may be 10
Hz, next point it is say 100 Hz and so and so, this may be 1 kHz and so and so. And, then
previous one it is 0.1 Hz and so and so. On the other hand if you see the data since we
are converting the data in log scale, the y axis scale on the other hand it is linear.
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So, if it is say this is maybe say 0 dB or maybe ‒ this 1 is maybe say 20 dB, ‒20 dB and
this may be say ‒10 dB, this may be 0 dB and so and so. And, the scale here of course, it
is linear whereas, the x-axis which is basically the ω since it is in log scale so, its ah
spacing of this minor lines are getting compressed here. And, then again it starts with so,
this is say 10 Hz, then this point it is 100 Hz and the next one it is 200 Hz and then again
the scale is getting compressed.
So, this graph it is referred as semi log graph paper where x-axis is in log scale, y-axis it
is in linear scale ah, but then y axis data it is getting converted into logarithmic form. So,
what is the change you will see compared to; so, in this Bode plot with respect to the
frequency response in linear scale. If it is a linear scale then let me also try to sketch that
linear scale whatever we have done just now. So, if I consider the linear scale and only
the magnitude, we have seen for this RC circuit the frequency response it was like this.
So, the y-axis is and its magnitude only and what we said is this corner frequency or
we call cut off frequency, where ω equals to what we call ω1 . Now, this is 0 frequency
of course, this 0 frequency we cannot see in log scale, it has gone to ∞, so ‒ ∞ distance
or rather towards the left extreme beyond our from this graph. On the other hand
depending on whatever the value we do have and in case if we are focusing somewhere
here, probably we can we can map all the data points into this Bode plot.
So, how will you plot? First of all this magnitude since it is simple CR circuit and we
have seen that as it is saturating towards a value of 1 and if you take we will get 0.
So, this means that this level it is coinciding with 0 dB ok. So, this is coinciding with 0
dB and sees this frequency suppose it is somewhere here, maybe it is say here. So, we
call this is ω1 = and at this frequency the corresponding difference here if you see it is
times.
√
And, if we if we take ; so, 20 what we do get here it is ‒3 unit and its unit is
√ √
disabled dB. So, with respect to 0 at this frequency what we are seeing here it is that it
reached to ‒3 dB. And, then if you go to some other lower frequency of course,
depending on the value here it may be point something or so, we will be getting some
other point here and so and so on. So, if I consider different data points here and if we try
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to plot here what we will be seeing here it is yeah actually we will be getting a linear
almost linear here.
And, then there will be a bend like this and then it is getting saturated. And, if you
consider if the data is going to be the magnitude it is going to be 0 which means that the
corresponding log it is going to be infinite. In fact, this will be linearly dropping. So, I
should say this part it is getting extended here, since it is a log scale in the x-axis. And,
the linear behavior it remains here also it is linear and this saturation part it remain
saturation.
And, whatever the point we do have here where the magnitude it was times of this
√
one, the steady level and that gives us a point here which is ‒ 3 dB. So, I should say this
corner point here it is corresponding to ‒ 3 dB point which is which is commonly
referred as ‒ 3 dB point. So, these plot this gain plot in log scale it is referred as the gain
plot of the Bode plot. So, Bode plots it is also having two components: one is the gain
part and the phase part.
So, similar to the gain if you consider the phase with ω in log scale, what will be seeing
there it is; let me use the same graph here and same axis here. So, at this frequency, the
phase it was 45° and then at lower frequency it was going 90°. So, maybe this was 90°
and then it was going to 0°. So, of course, I do have different scale for this phase. So, this
part the phase part it is I should say this is 0°, this is 90° and this is 45° and so and so.
So, the phase plot it is having the scale here which is again linear and the corresponding
the scale corresponding to the gain plot in dB it is in this it which is shown here. So, this
gain, part and the phase part together it is giving us the Bode plot. So, typically when we
are talking about frequency response of any circuit, say a CR circuit what we refer it is
basically this gain plot and the corresponding phase plot.
Now, here this frequency as I said that this is behaving like a high pass and this
frequency it is referred as the corner frequency or cut off frequency beyond which the
signal it is passing. So, I should say that this frequency range, this frequency range it is
the pass band. And, on the other hand this portion; this portion or the lower frequency or
frequency lowers than this corner frequency it is referred as the stop band. And, this
corner point it is referred as the cutoff of this behavior or the band pass.
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I should not say band pass, this is a basically high pass filter; so, this point is the cutoff
frequency. So, for C-R circuit we can say that cutoff frequency it is , in case if the
frequency it is it is expressed in rad/sec. If it is Hz then of course, it will be .
So, one interesting thing is that this if you see here the cutoff frequency expression of
cutoff frequency. And, if you see the previous slide where you are talking about the we
are talking about the yeah the transfer function in Laplace domain. There is one
important information that this denominator polynomial of this transfer function it
becomes 0 at s is equal to .
So, this s is equal to so, at this point this transfer function it becomes infinite which
means that this transfer function it is having a pole at s = . So, this pole and whatever
just now we said that the cutoff frequency of the frequency response which is ω1 =
they are related. So, we will see that the pole in the transfer function in Laplace domain
and the cutoff frequency of the frequency response they are having a direct co-
relationship.
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We will discuss that in detail ah, but let we cover one more circuit which is
complementary of this circuit, namely that is RC circuit and its behavior it is more like a
low pass kind of behavior. So, let me take a short break and then we will come back to
this frequency response of this RC circuit. And, we will then further we will correlate the
frequency response on the pole of the transfer function in Laplace domain.
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Prof. Pradip Mandal
Lecture – 36
Frequency Response of CE and CS Amplifiers (Part B)
So, welcome back to this R-C circuit frequency response after the short break.
So, similar to the C-R circuit again here what you are doing is that we are taking the
circuit into Laplace domain, namely the impedance of both the elements we are going in
Laplace domain for C it is and this is directly same as this R. And then input it is Vin
Laplace domain s and then the corresponding output also we are considering in Laplace
domain which is Vo(s).
And, if we analyze this circuit what you are getting here it is Vo(s) = . So, from
that what your yeah what you are getting is = . It is similar to the previous
circuit except of course, we do not have the sRC part rather in the numerator we do have
simply 1.
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Now, to get the frequency response as I said for the previous case what you have to do,
we have to take this replace this s by jω or rather I was having say sigma part in s which
I am making it 0. So, we are dropping this part and that gives us the transfer function in
Fourier domain and it becomes .
Now, this transfer function in Fourier domain again you can make the gain plot and the
phase plot to get the frequency response.
So, again here what you can do? We can plot the magnitude. So, if we consider the
| | and with respect to ω. So, if you see here at low frequency; if we ignore this part
with respect to 1, then the corresponding magnitude it is 1. But then if you go to higher
and higher frequency and if this part it is dominating over this 1, then the magnitude wise
what we will be seeing here it is 1 by ω nature. So, I should say it is more like a
hyperbolic curve if we consider this part, it is dominating.
So, beyond some frequency it is going through this hyperbolic nature. So, initially it may
be it was approximated like this and beyond this point it is approximated by this
hyperbolic part. And, the changeover it is happening again at the same frequency where
ωRC magnitude wise ωRC it becomes equal to 1. So, I should say if I call this is ω1 at ω1
what you are getting is that ω1RC = 1 which means ω1 = .
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So, if I consider the actual curve instead of considering this two asymptotic or
approximated curve will be getting the actual curve going like this. So, here again, it is
having complementary behavior as I said with respect to the previous one. Before this
frequency the circuit it is passing the signal to the output and that is very obvious from
the intuition of this R-C circuit because if the signal frequency it is low enough, then the
capacitor it may not be shorting this output signal as a result at the output we can get
almost this input signal.
On the other hand, if you go to higher and higher frequency, this capacitor it is
impedance it may drop and then the signal at this output it will be dropping. So, if you
consider frequency beyond this ω1, then you can say that behavior of the circuit it is
working like the signal is getting attenuated. So, beyond this frequency the signal it is
getting attenuated. So, I can say that the circuit it is again it is having two range of
frequency – one is pass band, another is the stock band. And, in this case it is we can say
low pass low lower frequency it is getting allowed through this circuit.
Now, the similar to the previous case here again we can make the phase plot and then the
if you consider the phase plot at very low frequency this part it is almost 0. So, we do
have 0 phase shift. So, you can see that the phase shift here it is 0°. So, this y-axis is the
phase shift offered by this network.
So, it if you consider it is phase then at low frequency it will be 0° and then as we
are approaching towards this ω1, then the this part it will be more and more prominent
and then at ω1 that will be equal to it is magnitude wise it will be 1 and so, it will be jω.
So, in this part it will be simply ω.
So, the corresponding phase here it will be ‒ 45° that is because in the denominator at
this point I do have 1 + j all right and if you go to a higher frequency beyond this ω1,
this part it will be dominating and as a result then will be going towards ‒ 90°. So, this
phase plot and this gain plot they are giving the total frequency response of this R-C
circuit.
Now, similar to the previous case again since we like to see the wide range of frequency
and the behavior of the frequency response over wide range. So, we need to change this
scale into logarithmic form and magnitude also we like to change in logarithmic form.
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So, whatever we get is the Bode plot. So, here again in the Bode plot what will be seen it
is similar to the previous case that if you consider ω in log scale then of course, 0
frequency it will be pushed to ∞ distance and then this one part it will be coinciding with
0 dB.
And, then this hyperbolic part on the other hand, it will be having a linear behavior and
then at the corner frequency, there will be there will be rule of started and exactly at
corner frequency at ω = ω1, we will be having ‒ 3 dB. So, again here we can say that this
corner frequency whether it is in; so, this is gain in gain or magnitude in dB. So, these
this corner frequency and whether it is in this frequency response or in Bode plot, it is
related to this location of the pole.
So, here again we are getting a direct relationship of this pole and this corner frequency.
So, just by seeing the transfer function; if we know that the location of the pole probably
from that we can tell what is the location of this corner frequency. And, in this case if we
consider lower frequency with respect to this corner frequency, then the gain it is
remaining constant. And, beyond this point the role of it is linear and in fact,
mathematically it can be shown that or you may be already knowing from other subject
that the slope of this gain variation with ω it is ‒ 20 dB per decade.
So, whenever you are talking about frequency response in fact, what we are looking for
is that in some range gain it is remaining constant and then we are hitting say something
called corner frequency and beyond that it is having a roll off like this ‒ 20 dB per
decade. In case if we consider lower side for the other circuit, then we have seen that
beyond some other corner frequency or below of this corner frequency, the slope here it
is 20 dB per decade.
So, I should say that the whenever you are talking about this frequency response what we
are trying to capture it is the location of the corner frequency and that can be directly
obtained from the pole of the transfer function in Laplace domain. So, the natural
curiosity is there why this pole and this frequency response cutoff frequency why they
are related. So, let us see that part yeah.
510
Yeah, this part we already have covered; Bode plot we already have covered yeah.
So, this is what the we are about to discuss that the transfer function pole of transfer
function in Laplace domain and the cutoff frequency they are related. And, let us
consider this simple R-C circuit which is having one pole and the location of the pole, it
is if you see here the location of this pole it is p = ‒ which means that s = ‒ the
transfer function the magnitude here it will be going to be ∞.
511
So, if I say that this gain or transfer function if we denote by say AV(s) since it is we are
dealing with voltage and if you plot this magnitude as function of s and s is note that s is
having two components; one is the σ part the real part and the imaginary part. So, if we
plot this magnitude over this s domain; so, this horizontal part, the horizontal part
consists of this σ-axis and jω-axis basically this is the axis. So, we may call this is the s
plane s domain.
So, over this domain s domain if we plot this magnitude of this transfer function what we
are seeing here it is since it is having a pole it is having a pole at this frequency or say let
me consider this one. So, at ‒ , so, if we sketch this plot obviously, or the surface if
you see this will be going to ∞ at this point. So, if you see this surface it is more like a
tent and at this frequency the tent it is going to ∞.
So, this is imagine that this is 3-dimensional plot and the location of the pole it is here.
So, if you see this surface and then if you consider the vertical plane constructed by this
jω-axis and then this AV(s) axis; that means, this plane consists of this vertical plane and
this plane it is cutting the surface whatever the surface just now we are plotting here
which is basically representing the variation of the gain over this s domain.
Now, if I consider this cut set of this surface which is getting cut by this vertical plane
constructed by this AV and jω. What we are what we can see here it is, it is a cut set
having a profile like this. So, the cut here will be seeing a profile like this and if you see
this cut what is the significance or importance of this one, it is that along this axis this is
also this axis is also representing some value of s, but along this axis of course, the σ part
= 0.
So, which means that whenever we are talking about σ = 0; we are restricting our, s-
domain only along this line. So, if we move along this line each of this point is
representing one frequency component corresponding to whatever the ω we do have.
And whatever the surface profile we are seeing here, it is basically representing how
much the gain or the attenuation of the input signal it will be experiencing through this
circuit based on its frequency this variation it will be obtained.
In other words, if I say that in this experiment if we change this ω frequency starting
from say 0 towards higher and higher frequency and keeping the magnitude input
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magnitude of the input signal say constant and if you observe the magnitude of the
output signal what we will be seeing that the with ω how the magnitude its changing that
profile we can get by this line.
So, this line as I said this line it is nothing, but the response of this circuit for say
stimulus whose magnitude is not changing with time. Why magnitude is not changing
with time because we consider the corresponding stimulus it is having a ω = 0. So,
whatever the signal we are feeding here if we consider it is a steady sinusoidal signal that
represents two ω components - one is + ω and ‒ ω part. And if you consider this part +
part, then if you see the corresponding variation of the magnitude with the ω nothing that
is nothing, but this line this curve.
And, incidentally this curve it is the frequency response right and the interesting thing is
that in this case for R-C circuit, the value here it = 1 and if you go to a frequency say ω =
, the corresponding magnitude here you will see it is . So, if I compare the value of
√
this frequency response at this point and at this point, then where it is . And if you see
√
that ω = they are what they are revealing that the location of the pole at . It is
having an impression at the frequency response.
So, I should say if I draw one say circle centering the origin having a radius of , then
that circle it will be cutting this jω-axis at this point and at this point the magnitude here,
it is . So, you may recall that whenever we plot this frequency response of this circuit,
√
we have seen that magnitude it was diminishing with ω. Note that this is in of course, it
is in linear scale and this is the magnitude and here it was 1 and at ω1 = the magnitude
here it is .
√
So, this point the cutoff point or cutoff frequency point which is basically the image of
the location of the pole. In fact, if this location of the pole it is going far away then the
point at which the frequency response it becomes of this point that will also be
√
moving away. So, location of this pole in the Laplace domain and the location of the
cutoff frequency they are related. So, in fact, if you see this circuit this is of course, RC
circuit. So, based on the location of the pole, we can directly as I said that we can find a
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cutoff frequency whether it is whether it is the frequency response in linear scale or
whether it is in Bode plot the cutoff frequency in fact, this is also .
So, now let us see the; so, here we have considered R-C circuit which it was having a
pole and we have seen the relationship to cutoff frequency. Let us look into the other
circuit namely the C-R circuit which is having slightly different transfer function.
So, yeah so the C-R circuit the denominator part it is same which means that this is also
having a pole at s = ‒ in addition to that it is also having a 0 which means that
numerator polynomial of this transfer function AV(s). It becomes 0 at s = 0 which means

that here also it is having a pole it is having a pole at ‒ . So, if I am having only one
pole, the function supposed to be going to be the surface supposed to be going to be ∞

this point.
But, then unlike the previous case here it is having a 0 which means that. So, it is also
having a 0 at this point. So, if it is having a 0 then of course, this surface it will be turned
down to 0 here. And, if you see the impact of this the pole and 0 combination that gives
us a nice surface here so, this part it is going to ∞ on the other hand this part it is going to
be 0.
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And, if you see here if we travel along this sigma axis we can see this ∞ and 0. But, if
you consider see in other direction maybe along the jω also so, what kind of profile we
will be seeing here it is it will be going up here and then it will get saturated like this. So,
earlier whatever the cut set we have drawn here along the along the jω-axis or rather if I
consider this surface whatever the surface, we are trying to explain here. If that surface it
is cut by this vertical plane constructed by AV and jω-axis, then whatever the cut set will
be seeing here it will be having a cut like this.
So, whatever the cut set we are getting here again this is representing the frequency
response. And, again depending on the location of this pole this frequency response of
course, it will be going to steady and it will be having a corner frequency where the yeah.
So, let me use a different color here yeah. So, we do have a corner frequency where the
magnitude of this frequency response it will be times the saturated level.
√
If I turn this curve and if I see the in this direction what we can see here it is this is jω-
axis and this is the σ-axis which is coming out of the surface and this is AV magnitude.
What we are trying to explain here it is having a plot like this. So, this is what the
frequency response. In fact, so, this line it is basically the same line here and again the
location of this pole it is basically deciding the point where it is going to a point which is
having a magnitude which is times of this saturated level and the saturated level of
√
course, it is 1.
So, this point it will be whatever you call points or in Bode plot it is referred as ‒ 3 dB
√
point and this frequency again which is ω = . So, what is the summary here we like to
say here it is that based on the location of the pole based on the location of the pole of
this transfer function in Laplace domain we can directly say that what is the
corresponding cutoff frequency.
Now, so, we have so far discussed about simple circuit R-C circuit and C-R circuit and if
we combine this R-C circuit and C-R circuit together of course, then whatever the
transfer function will be getting it will be having multiple poles and zeros those things
we will see that. So, let we see the combination of C-R and R-C circuit and while you are
combining we need to be careful that loading effect if we cascade the two circuits of
course, one circuit it may load the other one.
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To avoid the loading effect what we have done here it is we do have the C-R circuit we
do have the C-R circuit and also we do have the R-C circuit. And, in between we are
putting some ideal kind of block saying that this block it is what it is doing is that
whatever the voltage it is getting developed called say V1 it produces a voltage here
which is a V2 which is equal to constant times this V1. So, I should say that this model
this ideal model of this voltage dependent voltage source I should say this voltage
dependent voltage source ensures that loading effect of this R-C circuit is not falling on
this C-R circuit.
So, if this Ao it is having some magnitude which is higher than 1, so, we can say that this
voltage dependent voltage source is an ideal voltage amplifier. So, the whole circuit if
you see you can call it is combination or cascaded of C-R circuit followed by amplifier
and then followed by R-C circuit and if we stimulate this circuit from this point and if we
like to observe the corresponding output here, what we can see here it is we can get the
transfer function of the whole system by considering each of this part.
So, from primary input to primary output transfer function if we try to see we can split
this transfer function into three components one is coming from this C-R circuit,
namely . So, this is the first part this is coming from the C-R circuit and then the
second part which is coming from the amplifier. So, we do have this amplifier here. So,
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this part it is basically representing the amplifier. On the other hand, the third part it is
the R-C circuit and its transfer function it is basically the here.
So, now, if we recall that transfer function of this C-R circuit let me use different color
here. So, this part it is having a transfer function of s corresponding C and corresponding
R divided by 1 plus s corresponding C and R. So, this is the first part and then the second
part is from here to here. So, the corresponding transfer function it is simply this Ao.
And, then the third part which is R-C circuit and we have seen before that it is transfer
function it is 1 by s multiplied by the corresponding C and the corresponding R.
So, overall the input to output transfer function what we are getting here it is this one and
what you can see here again what we are looking for is the frequency response and hence
the pole of the transfer function or whatever the factors we do have in the denominator
polynomial one is here another is here.
So, the if I consider this factor it is having a pole called say p1 = with a ‒ sign.
Likewise if I consider this part this part we do have the second pole say p2 which = ‒
. And, this is C-R circuit and we have seen that it is a frequency response it is high
pass in nature this is low pass in nature. And, for our convenience let we consider that
the high pass frequency cutoff frequency it is lower than this one and then try to see what
kind of frequency response intuitively we can get out of that.
517
So, so, let us yeah. So, as we have discussed that the transfer function of the whole
system it is given here and it is having as I said it is having two poles one is coming from
here another it is here and then also it is having a 0. And, if you see the frequency
response and let you consider the first one C-R circuit and the C-R circuit frequency
response it is.
So, if we plot the ω in log scale and dB; that means, if we take 20 log base 10 what
will be getting here, it is basically the high pass behavior. So, we will be getting a
frequency response like this. If I consider this is 0 dB level and then it is corner
frequency it is here which is . So, the frequency response of the first part it is given
here.
Second part it is if I consider it is remaining constant. So, I should say that this part. So,
it is remaining constant and this level it is 20 log whatever Ao we do have. So, it is
remaining constant. On the other hand, the third part which is R-C circuit it is having, it
is low pass kind of behavior and let me use different color here for axis .Let me use this
color and the Bode plot of the R-C circuit it is going like this and then it is having a role
of like this. And, the role of it is happening here which is say the second pole let me call
this is ω2 = .
Now, if I combined this pink characteristic curve and then the middle one and then the
blue one what we are expecting that it will be just if we overlay the three parts what will
be getting here it is. So, this part it is coming from the C-R circuit and the amplifier
again this remains high pass, but then instead of having 0 dB here I do have some
positive gain here. And then if I combine the pink part then what will be getting here it is
at some frequency beyond ω2 it will be having a roll off.
So, the overall frequency response what we are getting here which is shown here by this
red color which is having a cutoff frequency ω1 and ω2 in the middle range we do have
very good gain which is defined by this one. And, this is coming from and this is ω2
it is coming from . So, I think this intuition will be helping you or and of course, this
role of since it is single pole roll off later. We will discuss about what will happen in case
if you have say double pole roll off.
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Namely if you have say two poles exactly at the same frequency what will happen but,
for the time being they are single pole roll off. So, this is ‒ 20 dB per decade slope and
here we do have the slope it is + 20 dB per decade and the middle gain, it is this one. So,
so far whenever we are talking about say CE amplifier or common source amplifier we
were dealing the amplifier in the mid frequency range, to be more precise we are talking
about this frequency range and then we talked about the voltage gain of CE amplifier and
other things.
But, if you go to lower and lower frequency depending on the value of this capacitor and
then this R the corresponding gain definitely it will drop. And, on the other hand
depending on this R and C then again beyond some point it will be dropping. So, the
actual frequency response or the circuit behavior it is given by this combined Bode plot
and as I said that it is coming from the three elements. So, whenever we will be dealing
with the actual circuit it is better to identify which is the R-C circuit and which is the C-
R circuit, they are defining the corresponding that the cutoff frequency or corner
frequency.
So, since our main purpose here it is to use this circuit as an amplifier. So, we can say
that this is the suitable range of the amplifier and if you go beyond this point then the
circuit it is it is gain is dropping so, we are not interested to that. So, likewise if you go
beyond this point then again gain is dropping. So, we are not interested to that. So, we
can say that our suitable range it is only this one and. So, this two are the limit of the
suitable range or we can say cutoff range or cutoff frequency one is called lower cutoff
frequency and this one it is called the upper cutoff frequency.
So, whenever we will be talking about say amplifier along with the mid frequency range
gain, these two information basically these two frequency cutoff frequencies are also
very important to define the frequency response of the amplifier. So, presently whatever
the circuit we will be dealing with this model or this C-R followed by amplifier followed
by R-C circuit. This model it is pretty handy and pretty sufficient to explain the behavior
of simple frequency response of the simple voltage amplifier.
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So, we will be talking about this C-R circuit sorry, common source amplifier and
common emitter amplifier circuit, but let me take a short break and then we will come
back to the frequency response of the amplifiers the actual amplifier.
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Prof. Pradip Mandal
Lecture - 37
Frequency Response of CE and CS Amplifiers (Part C)
So, welcome back after the short break. And we are talking about Frequency Response
of the Amplifier and we have seen that generalized form of a network consists of C-R
circuit and R-C circuit and in between we do have an amplifier. Now, let we try to map
that model or rather actual circuit mapping to that unified model.
So, say to start with we do have common source amplifier and the circuit is given here.
The circuit is given here for your reference and if you see here we do have the main part
main amplifier here and then, we are feeding the signal through this capacitor called say
C1. At the output we are observing the signal after removing the DC part through the C2.
In addition to that, it may have some capacitive load coming from the next subsequent
circuit. So, let you call this is CL. Now, if we draw the small signal equivalent circuit
after obtaining the quiescent point and other things are defined by R1, R2; then, Vdd and
then RD.
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What we obtained in our previous discussion we say that at the middle, at the middle we
got the main amplifier circuit and here of course, it is the small signal equivalent circuit;
where, Vdd it is Vdd node, it is AC ground and the transistor it is getting replaced by its
small signal model which is voltage dependent current source called ids. And its
expression it is given by transconductance gm × vgs. vgs is the voltage appearing across
gate to source of the transistor. So, this is the vgs.
So, based on this vgs, we are getting this current and then that current it is flowing
through this RD and then, of course, we are getting a voltage here. Note that still this is
not on equivalent, but it can be easily converted into Thevenin equivalent, namely we
can make the amplifier which is having a gain of ‒ gm × RD. So, the voltage here you can
say equivalently whatever you say v2.
So, this voltage here it is ‒ gm × RD × vgs and of course, the corresponding Thevenin
equivalent resistance, it will be same as this RD. So, this part the output port part, it can
be translated into this circuit and once you translate this circuit in this form, then we are
moving towards our unified model of the amplifier.
Likewise, input side again this two part these two resistors you can translate into
equivalent resistance here, which it will be R1 ⫽ R2. So, what we can see here that C1;
this C1. So, this is the C1 and then, this Rin which is R1 ⫽ R2, they are forming one C-R
circuit. This the C-R circuit is getting formed here and then, output resistance which is
RD and then this CL along with this C2 coming in series, they are these two are farming
another circuit which is of course, this is R-C circuit.
And this capacitor value, it is it is basically C2 ⫽ CL and its expression it is sorry, this is
in series; this is in series. So, its expression it is . Typically, this CL it is much
smaller than C2; rather C2 ≫ CL and this part dominate as a result this becomes
approximately CL. So, we can say that at the output we do have approximately CL.
So, what we are getting here? It is that the amplifier, it can be translated into that unified
model which we have discussed just now, before the short break; where, it is having C1,
then Rin and then across this Rin the voltage it is vgs and that vgs, it is generating a voltage
which is whatever ‒ gm × RD time times this vgs. And then it is also having the Thevenin
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equivalent resistance RD and then, we do have the output capacitance approximately
same as the CL. And at the input we are giving the stimulus.
So, now as I said that we do have C-R circuit, we do have this is the amplifier part and
then, we do have the R-C circuit. And from that directly we can say that who are the
contributors of the cutoff frequency and the gain. So, in the next slide, I am just
summarizing the same information; yes.
So, what we have for our reference again, I am just keeping this diagram, we just now
we have discussed and this circuit we are mapping into this generalized form. We do
have the C1 here. So, this C1 it is coming here and the middle portion, middle portion
particularly this portion, the amplifier portion we are modeling in this form. So, I should
say that this amplifier, it is getting modeled into this one which is voltage amplifier,
where it is having three important parameter namely Rin.
So, Rin equals to if I say R1 and R2 coming in parallel and then, vgs is basically here we
are calling it is v1 and then v1 × Av or Ao that gives us the voltage at this point. So, we
can say that this Ao = ‒ gm × RD and then, this Ro which = this RD and then, the CL, it is
dominating compared to the C2. So, this capacitor it is approximately the CL.
Now, as we have said that the frequency response now if you are asked to draw the
frequency response or the bode plot particularly the gain plot, I think you will be able to
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do it yourself. ω in log scale right and then, the mid frequency range the gain it is defined
by this Ao. So, if I consider magnitude. So, we do have the gain here and then, the lower
cutoff frequency. It is coming from C1 and that this Rin.
So, this frequency, it is (

. So, that is the lower cutoff frequency and then, upper
)
⫽
cutoff frequency it is defined by this RD. So, if I say this is the upper cutoff frequency
which is this RD and CL are defining. So, this is and then gain here it is of course, in dB
| |. So, I should say that this as we have discussed before this C-R circuit, it
is contributing this part. So, this is C-R part and then the R-C part, it is contributing this
part. So, this is the R-C part and the middle portion which is coming from this part. So,
this middle portion, it is coming from this the amplifier.
So, that is how we do get frequency response of the amplifier. Now, if you are asked to
plot the phase; phase also ah, so this is gain or magnitude; sometimes it is also referred
as amplitude. Now, if you are asked to draw the phase plot, what you can see in the mid
frequency range note that we do have a minus sign here. So, as a result in the mid
frequency range, the phase it will be; so, we will start from the middle and then as you
were.
So, this phase is either you may say that ‒ 180° you are 180°. And then, it is having a
role of towards this corner frequency and then, it goes a step of 90°, ‒ 90°. So, this
phase, it will be if I consider this is plus 180° ah. So, this phase, it will be 90° and at this
corner frequency, it will be 180° ‒ 45°. So, that is 135°. On the other hand, here it is the
step, it is the other way. So, the phase it rises here and here also it will be having a step
of 90° phase up. So, this is 90° plus.
So, we may say that this is 270° at this level and at this point here, it will be this + 45°.
So, that is at this point it is 225° ok. So, in case if you’re instead of calling this is + 180°,
if you are calling this is ‒ 180° degree. So, you need to change this one to ‒ 270° and
then, this one you need to change to ‒ 90°. But whatever it is. So, we are getting this
corresponding gain plot and phase plot easily by using this unified model of the
amplifier. So, similar thing it can be done for the CE amplifier.
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So, let us see what the things we have done for CE amplifier are. As I said that is very
similar. So, you may recall this is the CE amplifier with fixed bias and this middle
portion is the main amplifier and it is also having this 2 signal coupling capacitor C1 and
then C2 alright. And in the middle portion of course, we do have the transistor and the
middle portion can be converted into small signal model which consist of this RB. We do
have RB there and then we do have RC here and base to emitter junction, we do have rπ
this is the.
This is a part of the small signal model of the BJT. And then, we do have the ic; small
signal ic = gm × vbe, sorry this will be vbe. So, this vbe it is of course, the voltage between
this base to emitter terminal or emitter node or voltage across this rπ. So, here again this
part it will be straightforward to convert into Rin or equivalent input resistance.
So, Rin = RB ⫽ rπ and typically, this is getting dominated by this rπ. On the other hand,
the not on equivalent circuit. So, this is of course, AC ground. So, this not on equivalent
circuit we can convert into Thevenin equivalent for our convenience and once you
convert this voltage dependent current source into voltage dependent voltage source,
what we are getting is this voltage here. It is gm, ‒ gmRC into this voltage vbe.
And then, Thevenin equivalent resistance of course, this will be same as this RC and
similar to our previous discussion as I said that there will be load capacitance coming
from the subsequent stage CL. So, the C2 and CL together they will be giving us giving
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the load to this circuit and typically, the C2 it is much higher than CL. So, the series
connection of the C2 and CL together it is approximately with this condition
approximately CL. So, at this output node, we do have the CL.
So, similar to the common source amplifier, again here we are getting R-C circuit or
rather C-R circuit constructed by or consist of the C1 and Rin. In the middle we do have
the voltage amplifier, define and it is gain it is defined by gm × RC with a ‒ sign and then,
next one is the R-C circuit. So, here again, we can map this amplifier into the unified
model to get the frequency response of the overall circuit. So, that is what we are
summarizing in the next slide.
Yes. For your reference again I am keeping this circuit and this circuit it is getting
mapped into this unified model and the Rin, it is in this case RB ⫽ rπ which is
approximately rπ and Ro = RC and then, Ao = ‒ gm × RC ok. And here again, the
procedure it will be same. If you are asked to draw the bode plot of the entire circuit,
what will be getting here it is and the mid frequency range you will get decent gain
defined by this Ao and then, the lower cutoff frequency it will be coming from the C-R
circuit.
So, the lower cutoff frequency say ω1, it is and the on the other hand, the upper
cutoff frequency, it is RC and CL they are defining. So, it is defining the upper cutoff
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frequency and this is the gain which is | |. I think that is the frequency
response of the normally used simple voltage amplifier. Now, I must say that few more
information that if you recall the so far we are talking about the fixed bias circuit.
So, in this circuit, we are not having any emitter resistor. And in case if we put emitter
resistor here say RE and of course, then I have to put voltage bias here maybe this is R1
and this is R2 and so, that gives low gain, the corresponding gain it is simply . And to
get back the higher gain we need to bypass this RE bias a CE. Now, this CE, it is also
having some role to play to define the upper or lower cutoff frequency that can be seen
later. So, probably we need to have a dedicated class to discuss about the frequency
response of this cell biased common emitter amplifier.
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So, yeah so, the yeah so, we are all yeah, let me instead of stretching today’s class
towards the CE amplifier with the cell biased. Let me summarize what are the things we
have covered today. Ok, before I forget actually this should be self-bias ok. Anyway,
what we have covered today, it is the R-C circuit frequency response, we have revisited
because this frequency response of R-C and C-R circuit, it helps us to get the frequency
response of an amplifier.
And what we have seen there with these two examples independently that the transfer
function and the frequency response particularly transfer function in Laplace domain in
s-domain. And the frequency response while you are changing the frequency in ω along
the ω line we have seen that they are definitely they are related. Particularly, which is
important thing is that the pole in transfer function in Laplace domain and the cutoff
frequency in the frequency the response they are directly related.
So, what we have seen is that we started with simple C-R circuit and then, we have seen
that for C-R circuit, the location of the pole defines the lower cutoff frequency of high
pass nature. And pole location of R-C circuit on the other hand, it defines the cutoff
upper cutoff frequency of the low pass filter. And those frequency responses, if we
combine together along with the middle ideal amplifier, then they are helping us to get
the frequency response of common source and common emitter amplifier.
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So, in today’s discussion that is what the main thing is that how we make use of C-R and
R-C circuit along with the ideal amplifier to get the frequency response without really
going in detail of the analysis or equation. Intuitively, we can say that which are the
contributors of which cutoff frequency and so and so.
Now, the in this module as I say that we need to cover some more things. So, we do have
the pending items listed here; the frequency response of CE amplifier having self-bias.
So, it required some dedicated class to cover this frequency response and whatever the
analysis we have done, we can we can make use of that to find the numerical value of the
cutoff frequency of a filter and so and so.
So, we need to cover the numerical examples and then we will be talking about the
design guidelines. Note that under this design guideline, we have talked about design
guidelines of CE amplifier for both self-biased as well as fixed bias. But primarily that is
related to the mid frequency gain. Cutoff frequency, we have somehow we have touched,
but we did not go in detail.
Now, we like to cover similar kind of things for common source amplifier; this thing we
need to cover and also the information about the frequency response and the analysis of
frequency response of CE and CS amplifier, how they are they will be helping us to find
selecting the coupling capacitors namely C1 and C2 and CE. They are also in fact, part of
the design. So, once you cover the frequency response, then we can revisit the design
guidelines of CE amplifier to get rather more appropriate expression of C1, C2 and CE.
I think that is all I need to cover in this module ah. So, we will be coming back in the
next class with these pending items.
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Prof. Pradip Mandal
Lecture – 38
Frequency Response of CE and CS Amplifiers (Contd.) (Part A)
Dear students, welcome back to this NPTEL online course on Analog Electronic
Circuits. Myself Pradip Mandal from E and EC Department of IIT, Kharagpur. Today,
we are going to continue the Frequency Response of Common Emitter and Common
Source Amplifier and so it is primarily whatever the remaining topic, it was there we are
going to cover today and will be mainly focusing on common emitter amplifier.
So, in the previous day we have discussed about common emitter amplifier with fixed
bias and today we are going to discuss more about the self-biased common emitter
amplifier.
So, what we have today the overall plan; as I said that in the previous week we have
discussed about the frequency response of CE amplifier for which we have detail
discussion about R-C and C-R circuit and then you know we have discussed about the
common source amplifier particularly with circuit analysis.
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Numerical portion it was not covered, so today we are going to discuss numerical
examples of common source amplifier. Likewise, for common emitter amplifier as I said
that for fixed bias we have covered. So, circuit analysis portion it was covered before and
today, we will be discussing about some numerical examples. But before that we are
going to discuss about the frequency response of common emitter amplifier with self-
bias arrangement.
So, we are going to start with the common emitter amplifier with self-biased and its
corresponding circuit analysis. And later on of course, we will be going to discuss about
numerical examples. From these numerical examples, we will get an idea that how to
select the value of different capacitive components in the circuit. In fact, that will help us
some design guidelines. In other words, in if say lower cutoff frequency and upper cutoff
frequency is given to us, then how do we find that the coupling capacitor and what may
be the you know the possible load capacitance, ok.
So, again we are since we are going to start from the previous topic where you have left,
so we need to just recapitulate some part of it, particularly the R-C circuit and C-R
circuit analysis which it has been deployed for fixed bias circuit and then we will be
moving to the common emitter amplifier with self-bias.
So, in the previous week what we have discussed? It is in case if we have say common in
any amplifier which is having say preceded C-R circuit and then followed by the R-C
531
circuit, then the corresponding model of the circuit, it is given here. And what we say it
is that this portion, this portion is the amplifier part, and on the other hand this portion
the C and R, they are forming the C-R circuit and then on the other side we do have this
R and then C2, R2 and C2 it is forming the R-C circuit.
And what we said is to get the overall frequency response starting from the primary input
to the primary output what we what you have done is that we obtain the frequency
response from this point to this point, and then from this point to this point like v1 to v2
and then from v2 to vo. So, the overall frequency response it is having three parts. So, is
one is the frequency response of the C-R part and then frequency response of the main
amplifier part and then followed by frequency response of the R-C circuit.
And as we have you may recall that the first part it is C-R circuit frequency response it is
having at 0 frequency and then 1 pole at . So, its transfer function it is given here.
The middle portion it is having a voltage gain of Ao. So, Ao it is given here. And then the
R-C circuit on the other hand its frequency response it is ; this is also having a
pole at .
So, the frequency response what do you obtain, it is this part it was giving us low pass
sorry high pass characteristic and this value it was 0. I should say let me let me redraw
here. So, this portion it is it was having low pass characteristic sorry high pass
characteristic having a cut off frequency it is . The middle portion on the other hand,
it was having constant gain defined by whatever this Ao and then the R-C part, it is
having a pole and its behavior it was a low pass kind of behavior and combining the high
pass, low pass and then all pass, it was giving us the frequency response of the entire
system. And note that, the upper cutoff frequency of course, here it is . So, overall
frequency response we are obtaining is it was like this.
So, this we have discussed in the previous class. And we are going to use the same model
for CE amplifier having emitter de-generator namely it is referred as the self-biased CE
amplifier.
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Now, again just for a slight recapitulation; in case, if you recall the fixed bias circuit
where this is the circuit diagram given here, which is having coupling capacitor here C1
and C2 signal coupling capacitor and then we have drawn the small signal equivalent
circuit of the amplifier which is basically the core part.
And then we have translated this circuit into this form namely the input resistance of the
core part, Rin, it is it was giving us say R1 and then C1 it is the capacitor signal coupling
capacitor. On the other hand output side, we are having output resistance of this circuit
which is equals to RC, and Rin it was RB ⫽ rπ and then it was having the gain which it was
‒ gm × RC. So, this circuit frequency response of this circuit, it was obtained by
considering its small signal equivalent circuit and then further to further from this it has
been mapped onto on this generalized C-R amplifier R-C circuit and then we obtain the
corresponding frequency response of this amplifier.
Now, let us; so, that is what we have discussed in the previous day, now we are going to
discuss about CE amplifier having self-biased arrangement.
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So, you may recall that in this self-biased circuit we do have the emitter resistor and so
and also the at the base we do have R1 and R2 from this Vcc to generate one DC voltage
here. And then of course, the signal it was coming here through this signal coupling
capacitor C1, at the output we do have the C2.
Now, this circuit of course, if we consider the core portion and if we consider its small
signal equivalent circuit it is given here. So, this is the small signal equivalent circuit
coming from the CE part. And if you, again if you may recall that the overall frequency
response Laplace domain it is having three basically, three parts one is the C1 and
then input resistance of the amplifier that C-R part and then this amplifier part, and this is
the R-C part which is coming from output resistance which is RC and these two
capacitors, they are coming in series and equivalently normally C2 it is much higher than
CL.
So, we can say that this series connection it is giving us, with this condition, it is giving
us the net capacitances CL. So, the frequency response of this part it is similar to the
previous case namely the CE amplifier with fixed bias. So, we need not to repeat say this
part and this part rather we will be giving a focus on the middle portion or you may say
that the core portion.
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So, let us see what is the analysis of this core portion, and out of this what we are looking
for it is the voltage gain whatever Av and then Rin and then Rout. So, let us now go in
detail into this circuit. And to get this parameter, so what we have to do? Let me consider
this signal it is directly given to this point and then we like to see what is the
corresponding output you are obtaining and if we take the ratio of the two then that gives
us the on the voltage gain Av.
And on the other hand, if we stimulate this circuit and then if you observe the
corresponding current and then if you take the ratio that will be giving us the input
resistance. So, likewise for the output also in this case of course, output resistance is
straightforward to say that RC, Ro = RC, but these two parts are a bit involved. So, let us
go in detail of this core portion and let we derive the expression on the Av part.
So, yes; so, this is the core part of the circuit and as I said that the signal we are directly
feeding here at the input and the output we are observing at this point. Now, what you
are doing? That input we are giving at the base node and with respect to ground, but then
emitter of the transistor it is not connected to ground rather it is connected to ground
through this RE as a result this vs and vbe they are not equal but of course, they are
related. So, let us try to see how they are related.
It may be noted that since vs we are directly giving here. So, irrespective of this R1 and
R2, we are getting the signal at this point same as this vs. So, I should say that the signal
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coming here it is vs. And out of this vs, we do have vbe part and also we do have some
additional drop here. So, what is this drop? This drop with respect to ground we may call
this is ve. So, the ve equals to this RE multiplied by the current and there are two parts of
the current flowing through this RE one is ic which is gm × vbe and then another one it is
. So, these two together it is giving us the emitter voltage here.
On the other hand, the vs is the total voltage, total voltage here which = ve + vbe. So, we
can see that this vs equals to now we do have vbe here and what we have it is vbe we can
take it out. So, we do have ( ) + 1. So, so this gives us the relationship
between vbe and vs. So, vbe = and if you see here this rπ = . So, if I put that
( )
expression of this rπ here what I will be getting here, it is I will be getting gm here and
then divided by β. So, that gives us . Typically, we considered that this β ≫
( )
1, so we can approximate this part this part is equal to 1. So, we can say that this is
. So, that is the vbe.
Now, vout, on the other hand vout this is RC × ic with a ‒ sign and ic = gm vbe. And then if I
if I put the expression of vbe here, so this is the vbe expression. So, that gives us =‒
, ok. So, that gives us the gain of the circuit, which means that the mid frequency
gain it is basically it is coming from here. So, that is what we have written here. The gain
is given here.
So, on the other hand, the input resistance if I see the circuit and if I look into this port
and if I want to know what will be the input resistance, input resistance we do have R1 ⫽
R2, sorry this will be R2 and then parallel with whatever the resistance it is coming from
this circuit. Earlier we have discussed that this; the resistance looking into this circuit is
rπ in series with this emitter resistor multiplied by (1 + β), ok. Why β, (1 + β)? That is
because in case if we are stimulating this circuit with a current ib then current flowing
through this collector it is β times that ib. So, the total current flowing here it is (1 + β) ib
as a result the drop across this RE it will be ib × (1 + β) RE.
So, if I take the ratio of the voltage here to here and then ib which gives us the input
resistance of this circuit. So, there we got this what you say that = rπ + RE (1 + β). In
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fact, this is what the resistance it is coming here. So, the total resistance is R1 ⫽ R2 and
then in parallel with whatever the resistance we do have.
So, if you see here that is the expression we are giving here. So, to summarize, so what
we are obtaining here it is this circuit, this circuit is having voltage gain of a and
then input resistance it is R1 ⫽ R2 and then rπ + RE (1 + β). And this part, this part
depending on the value of this RE we may approximate that this may be given by .
Likewise here we can say that R1 ⫽ R2 that dominates over this resistance, so the input
resistance may be like this.
And on the other hand, the output resistance looking into the output port what we do get
is that Ro = simply RC. So, this is also we have done before in some of our lecture, but in
case if you have forgotten probably you if you see this circuit since this portion it is ideal
current and if we look into this circuit and if you try to see what is the resistance of this
entire circuit it will be having only RC left behind. So, as a result the output resistance it
is RC, input resistance is practically R1 ⫽ R2 and then the input on the other hand the not
input the voltage gain it is ‒ , ok.
So, what we said here it is this should be R2 and in addition to that Ro = RC. So, this
information these three expressions basically the information about the core CE
amplifier, we are going to use to get the frequency response of this entire circuit.
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So, then if you see what will be the overall frequency response; now, as we said that this
is the this is the small signal circuit where the core portion we have discussed just now
and what we have obtained that the gain here, the amplifier gain here it is a with
a ‒ sign. So, this is the gain Ao.
And input resistance on the other hand, it is it is R1 ⫽ R2 that dominates R1 ⫽ R2 and on

the other hand the output resistance = RC. So, to get the frequency response of this CE
amplifier with the emitter degenerator, what we can do here it is if you consider the first
part this part and as you have said that the frequency response of that it is having high
pass nature and the cutoff frequency. Here it is (
, assuming that frequency we are
)
⫽
talking about rad/sec. So, this is basically decibel that means, we have to take log of
this ratio and then we have to multiply with 20.
So, it is frequency response of the C-R circuit is it is given here and then middle portion
it is, so the middle portion it is basically the amplifier part which is having good gain and
the gain here it is coming from this . May not be very high, of course we have to
convert in db a scale. So, and the frequency it is radian per second. And then the right
part, the RC part, it will it will be similar to the previous case it is having the low pass
nature and its cutoff frequency it is . Of course, we are assuming that this CL it is
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much smaller than C2. So, that is the assumption. So, we are assuming that C2 it is much
higher than CL.
So, the if I combine now these three graphs together, so what we can get that frequency
response will be getting something like this, right. And the lower cutoff frequency it is
coming from here and the upper cutoff frequency it is coming from here and mid
frequency gain it is obtained from here. So, here again it is very similar to whatever we
have seen for CE amplifier in fact, for common source amplifier also. But one thing I
must say that because we do have in the denominator the corresponding gain
which is you can say that this is all practical purposes, magnitude wise it is very small
compared to that CE amplifier with the fixed bias.
And then what we have done is that we to get back the gain we have suggested to use
bypass capacitor call CE to bypass these RE, and then in the frequency response it will be
definitely it will be having some impact. So, what you are expecting here is that this CE
part it will be here and intuitively what we said is that in the mid frequency range this CE
it may be completely bypassing this RE making this is AC ground and hence the vbe it is
it = vs the primary input. And as a result, we say that the gain instead of having this
denominator in the denominator if CE it is bypassing it, so this portion it will
be 0. As a result the gain we can get higher. That is what we said by intuition.
But of course, depending on the value of the CE when we will be getting this gain, the
high gain with respect to that may vary. So, depending on the value of the CE and
probably the effective resistance at this node there will be some cutoff frequency or
rather I should say you know the CE will be having direct influence on the frequency
response. It cannot go directly here. We prefer to have a smooth gain, but if we are
arbitrarily selecting this CE, then we may not get this frequency response. So, what you
can do? Now, let me look into the frequency response of this CE amplifier having RE and
CE together, and let us try to see what the corresponding frequency response is.
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Yes. So, this is the circuit I was referring to. Instead of RE, now we do have RE and CE
together. And if you look into the core CE amplifier which is of course, it is the different
part compared to the previous case. So, let we focus on this. In fact, if you go back and if
you see the previous circuit, sorry, yeah.
So, if you see here this part this part it is not having the CE part, but then its gain
expression we can see that this RE, it is directly coming there. So, whatever the analysis
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we have done for this circuit, similar kind of analysis we can do by considering this CE ⫽
R E.
So, try to remember that what are the things you have done or at least this is the
expression of the voltage gain. So, the same voltage gain or similar kind of expression
we will be getting in case if this RE it is shunted by CE. So, what will be; yes. So, from
that previous analysis, so what we can say that the voltage gain namely , it can be
written as ‒ in parallel with CE and its corresponding Laplace domain transfer
function, sorry this is RE. RE ⫽ .
Of course, now, we are talking about Laplace domain. So, I should use different symbol
( )
for this one. I should say rather ( )
in Laplace domain instead of the time domain. And
then, what we can do that we can simplify this expression and then we can see that it will
be having additional pole 0 combinations. So, let me take a short break, and then we will
start from here.
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Prof. Pradip Mandal
Lecture – 39
Frequency Response of CE and CS Amplifiers (Contd.) (Part B)
Welcome back after the short break and what we are discussing so far that, the CE
amplifier with the with self-biased arrangement with CE, that bypass capacitor CE ⫽ RE.
And what we said is that input to output gain, it is having this expression and let we
rearrange this expression and let us see how it looks like, maybe it is having some
meaningful expression.
So, this is denominator part it is 1 + gm RE and then we do have 1 + sRECE. And if we

further rearrange and what we will be getting this factor we can take into the numerator.
So, numerator part it will be gmRC × (1 + sRECE) divided by. So, this factor it is getting
multiplied here. So, we do have 1 + sRECE + gmRE.
Now, this is independent of frequency, this is also independent of frequency; we can take
together. So, 1 + gmRE you can take them together. And then if you take it as
as a factor. So, what we are getting in the denominator it will be seen; but let me write
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( )
the numerator part-1 . So, we are taken together; and then if we take this
factor as out, we do have 1 + .
So, what we have here it is; one part is this one, which is independent of s, independent
of the frequency and then we do have the other part, it is dependent on frequency. In fact,
if you recall that, this part it is same as the previous case when the CE was not there. And
due to the CE, then we do have this additional part and note that it is having a zero at s =
‒ and also a pole at s = ‒ .
In fact, you may approximate this location of the pole. So, pole location it can be
approximated by considering this part it is dominating and RE part it is getting cancelled
and then you may say that, this is gmCE. So, what we like to say here it is, this is what we
have written and that the expression of the gain voltage gain; it is not only this part,
rather it is having a frequency dependent part. So, since it is having pole zero, I think it is
better to go a little deeper into the frequency response of this Ao itself.
Now, instead of telling this is Ao, I should say Ao(s) which is function of frequency. So,
let us try to sketch the bode plot of this gain; unlike the previous case, this portion it is in
got change.
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So, let me clear and then let me try to plot the gain or magnitude plot of this Ao. So, Ao is
having; of course, we do have low frequency gain something like this and which is
assuming that this part it is more than 1. So, we can see that it is above 0 dB. So, it is
having a gain like this. So, which is coming from this part and then we do have one 0
here. So, ones with it is having a zero, then it is frequency dependent part it will be
changed and it will be linearly increasing. So, the corner frequency here, it is .
And then once you see the denominator part and at some higher frequency, which is
and that point we do have here pole. And once you have this pole we can say that
the variation of this gain with frequency, it got compensated by this pole. So,
mathematically we can say that once we have this part dominating over one and this part
dominating over this one; then s and this s they are getting cancelled, then we do have RE
and CE this part is also getting cancelled, and then 1 + gmRE that is also getting cancelled
with this.
So, what we have here it is gmRC. So, in conclusion what we said is that, the gain here it
is basically gmRC and the gain here it is . And location of this the pole here, which
is 1 by I should not say 1; this is rather let me write this is . So, if you see the this
expression and this expression, they are differing by this factor . In fact, if you
see since this is bode plot and then ω it is in log scale and y-axis is also in dB; that means
the data got converted into log.
So, you can see that ratio of this and this is consistent with the ratio of the location of the
pole and location of the zero. So, at this point we do have a zero and then we do have a
pole. So, anyway and beyond this point of course, the gain it is continued to be
remaining constant. Earlier, now if we recall if it is say fixed bias, where the gain it was
gmRC. So, there the gain it was like this, it was continuing like this. So, this is again for
CE amplifier with fixed bias.
And on the other hand if it is if we have say self-biased, and if we do have only RE; then
the corresponding gain it was continuing like this So, this is self-bias and with RE only.
On the other hand if we have self bias, but then we do have both RE and CE; then in the
low frequency before the CE it is really showing its effect, before this 0 frequency, it was
matching with the gain of this self-bias circuit with RE. And beyond this point then it is
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having a changeover starting. And then once it is reaching to this point, then it is
catching up with the gain of the fixed bias.
So, the self-bias circuit with CE it is having both the behavior; one is for self-biased with
only RE at low frequency. But then if you consider sufficiently high frequency, then the
corresponding gain it is matching with the fixed bias. And of course, this will be
appearing in the frequency response and in addition to if I consider the coupling
capacitor here and then the CL here; of course their corresponding effect it will be
obtained by considering their the high pass behavior coming from C1 and Rin, and then
low pass behavior coming from Ro and CL.
So, if I consider this part, effect of that part depending on the input resistance of the
circuit which may be R1, R2 coming in parallel and then rest of the things. So, depending
on that we may be having seen a low pass behavior sorry high pass behavior; and if we
say that this kind of high pass behavior it is coming from C1 and Rin of the amplifier, and
the corresponding cutoff frequency it is in fact, . And on the other hand if I consider
say C2 which is sufficiently high compared to CL, then this RC and the CL it is showing
the low pass behavior.
And let me consider the low pass behavior, it will be somewhere here. So, it is having
low pass behavior, but then it is cutoff frequency it is sufficiently high and the cutoff
frequency it is coming from RC and then CL. So, if I combined say this part and then the
blue part, which is having three component and then we combine this one; what will be
getting here it is, the overall frequency response it starts from here and then it goes with
this blue line. Since this is 0 dB for the passive circuits and then it is going here and then
again at high frequency, this . So, this part it is coming there.
So, the entire circuit, frequency response it is having a behavior like this. So, what are
the; what are the different poles and zeros are there; this at this point we do have, this is a
indication that it is having a pole at high frequency and then also it is having a pole at
this frequency. Then we do have a zero at this frequency, then we do have a pole here at
this frequency coming from C1 and Rin and also it is starting from a slope of 20 dB per
decade; so that means, it is having a zero at 0 frequency.
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So, it is having one zero at zero frequency, we do have another zero here and then the
three poles. So, that is how the frequency response of this entire CE amplifier with RE
and CE looks like.
In fact, I was having different slightly explained, but we already have discussed this part.
Again just to summarize here, the frequency response of this entire circuit; it is having a
pole here coming from C1 and Rin and then it is having zero here, which is coming from
RE and CE and. So, this is .
And then we do have frequency here which is 1 by I should not say 1 by; . And
then we do have high frequency pole, which is coming from . So, that is the
frequency response of the CE amplifier. Now one additional information I like to say
here; while say this part it is indicating that it is location of this pole it is depending on
one RC time constant, likewise this zero it is another no it is coming from another time
RC time constant and so is for the high frequency pole.
Whereas for this case I do have a different kinds of expression; but it is having a
meaning, in case if you approximate that the numerator part it is practically gmRE. So,
this expression of the, this cutoff frequency it becomes . So, what does it mean is that,
whenever the CE it is looking into this node; the effective resistance it is saying, here it is
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not only this RE and then rπ, but most important thing is that we do have a one active
device here.
So, if you are applying a voltage here that, voltage it is directly appearing as vbe or veb
and that is making a huge current flow because of this gm. So, the net resistance seen by
this CE, it is I should say that RE in parallel with whatever the rπ we do have; in case if I
consider this is connected to ground and then in parallel with . So, this is getting
dominated by . So, the corresponding RC time constant is basically this resistance and
then CE.
So, as a result whatever the corresponding pole we are saying, it is . So, this time
constant and that gives us . So, this CE in combination with the equivalent impedance
coming from this active device which is ; it is giving us the corresponding corner
frequency. Now, in case if the depending on the value of this of course, C1 and Rin; it is
possible that this corner frequency it may exceed this corner frequency.
But most of the time what we do, we take the value of this CE sufficiently high, so that
this corner frequency it is not exceeding this one. That is because; you may remember
that our main purpose is to get an amplifier having a good gain. So, this is our main
frequency band and if we are having higher band, it is better most of the time. And so, if
one of them it is you know exceeding the other one; whichever is lying on the right side
that defines the lower cutoff frequency.
In this case the lower cutoff frequency it is defined by this; but in case if we take a value
of C1 very small and in case if it is crossing this point and then this may be; this may be
defining the corner frequency. So, typically we try to see that value of this CE it will be
taken sufficiently large, so that in the optimum case we may say that, these two corner
frequencies they are coinciding. So, depending on in case if it is exceeding this point; of
course, it will be having the behavior of the frequency response, it will be slightly
different.
But nevertheless I should say that, I do have to define the lower cutoff frequency, I do
have two candidates; so one is , another one is . And whichever is higher, I should
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say that is the lower cutoff frequency. So, what we are saying is that, let me write in
terms of ω, lower cutoff frequency if I say ωL. So, that is equals to max of these two
candidates; one is , the other one it is .
So, whichever is higher that defines the lower cutoff frequency. Of course, we can
convert this into Hz. So, this is 2πfL. On the other hand on the upper cutoff frequency
there is no ambiguity. So, 2πfU which is ωU. So, that is coming from 1 by Ro which is RC
and then CL. I think that is completes the analysis part of the CE amplifier and in a
common source amplifier frequency response. Let us see some of the numerical
examples.
So, here we do have this common source amplifier, CS amplifier and this part we already
have done; namely if the device parameter , it is given to us; then threshold voltage is
given to us, supply voltage it is if it is given to us, and then bias elements are given to us.
From that what we have obtained is that, we obtain the DC operating point, and then
small signal parameter namely gm and Ro in case lambda is given; but anyway here
lambda is not given, so at least small signal parameter wise it was gm.
And from that gm we obtained this voltage gain Av, which is gmRD. And then input
resistance we obtain here it is primarily R1 ⫽ R2, and then output resistance we obtain
same as this RD. So, this part we have done before. Now today in addition to that in case
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if we have these two capacitors value and also the CL is given to us. So, this is C1, this is
C2, and then we can find what will be the corresponding Rin and then we can find what
will be the cutoff frequency, lower cutoff frequency.
So, in this case what will be the lower cutoff frequency? ωL = (

. So, whatever the
)
⫽
value it is we are getting, we can calculate our self. And likewise since C2 is much higher
than CL. So, we can say that this series connection, CL it is connected here. So, the series
connection of CL and C2 it is giving us the load capacitance, which is load cap = .
Now, you see this value here it is the C2 it is 10‒4, and then CL it is 100 pF, 10‒12 divided
by 10‒4 + 10‒12. So, this is what we say that, the denominator part it is dominated by this.
So, we can easily write that this is 10‒12, right. And so, the upper cutoff frequency ωU it =
1 by the CL and this RD; and RD it is given to us this is 3 k, 3 × 103. And then CL it is 10‒
12
to, no sorry we do have 100 p, 10‒10 anyway.
So, this is becoming or we can say that, Mrad/sec, ok. And we can convert this in
terms of the in terms of Hz and what will be getting is that; f u it will be in the order of
few 100’s of kHz. So, that is ; so roughly it maybe 400 something, 400 something
kHz, ok.
Whenever you are talking about CL, it may be coming from maybe next stage or maybe
from measuring probe capacitance or instrument. Typically in a hardware lab we have
seen that, the CL it is in this order somewhere 30 to 100 pF. So, that with that CL and this
practical value of this RD, you may get this upper cutoff frequencies like this.
Lower one what we have it is R1 and R2, if they are in parallel. So, that is how much?
This is Rin = . So, that is , right. So, this is , it is again 10‒4 and then Rin, it is k,
103, right. And so, that gives us how much; this is no this is what we said is it 10 µF
sorry, this will be 10‒5, earlier we have written ‒ 4, anyway it is still this approximation
is valid.
So, we do have. So, this is rad/sec. And so, this is how much? Around whatever 40
maybe 40 less than 45. So, maybe 43 rad/sec and divided by 2π. So, if I divide by 2π
roughly because 6, so that is becoming around 7 Hz. So, that gives you some idea that
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what may be a typical value of the lower and upper cutoff frequency of this common
source amplifier.
So, likewise you can consider say CE amplifier also. So, again for this circuit we have
done the mid frequency range analysis; namely by considering supply voltage and then
RB we obtain the base current. And then from the β we obtain the collector current; it
was you may recall that it was 2 mA current or you can calculate here IB = 20 µA. And
from that we obtain gm it was . So, that was A/V. And so, from that we obtain the
gain, which is gmRC and RC it is 3.3 k.
So, we got something around 240 gain. Now similar to the previous example here, so we
do have this additional information. So, C1 and C2 it is given to as say 10 µF, and we do
have the CL here which is a 100 pF. And then input resistance of this circuit it is RB in
parallel with whatever you say rπ and rπ. So, I should say Rin = all practical purposes it is
rpi which is . So, that is 1.3 kilo ohm and then the lower cutoff frequency it is one ωL =
So, that is , so that gives us rad/sec. So, roughly you can say that this is
how much around 70 in the range of 70 around 70 to 80 rad/sec. And if you convert into
Hz, then it will be in the order of maybe it around 12 Hz all right. And on the other hand
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the upper cutoff frequency, it is ωU = ; CL it is dominating with respect to C2. So,
this is equal to RC we do have 3.3.
So, CL it is 10‒10 F × 3.3 k, 103. So, that = . So, that is becoming how much, this is
around 3 roughly 3 Mrad/sec, and in Hz that is in the order of 500 kHz. So, that is what
the typical you know lower and upper cutoff frequency. So, in case if you are doing lab
experiment with whatever the components it is given to us; then you will be getting the
lower and upper cutoff frequency of this circuit.
So, likewise if you consider the CE amplifier having RE and CE and if we have the
similar kind of value of this R, or rather R1, R2 it is given such that the current here it is
similar namely 2 mA of IC. And then here we do have the C1 and C2 similar to the
previous case 10 µF and CL also it is given to us, it is a 100 pF. And depending on the
value of this R in of course, you will be getting the input resistance.
And of course, as I say that for the lower cutoff frequency ωL, we do have two candidates
to define the lower cutoff frequency; one is and the other one it is . Now, if you
see that previous case if we consider that Rin = rπ, ok. So, of course, there will be a doubt
that, why we consider rπ; but for the time being let you consider if it is in this Rin = rπ.
And there we have seen that the lower cutoff frequency it was coming from this part, it
was around 70 rad/sec around this value.
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Now let us calculate numerical value of this part; gm it is for IC = 2 mA this is A/V.
And CE it is given here, so the . So, that is it is becoming into, CE it is 100 µF, so
that is 10‒4. And this is becoming how much, this is rather .
So, what you can see here it is this is definitely higher than . And so, as a result
while in this case, practically then this becomes . And its value it will be somewhere
in the close to 1 k, may be around 800 rad/sec. And in case this is the situation then,
actually we should have considered this Rin = R1 ⫽ R2 ⫽ rπ + RE (1 + β).
And since this part it is higher than this one, so then Rin ≈ R1 ⫽ R2. And if you see this R1
⫽ R2, earlier we have discussed it is value it was, no we have not discussed. So, we have
to consider these two in parallel and since we do have 3.3 k here and 9.9 k, so what will
be getting here, it is . So, if I cancel this part it will be 4 so. In fact, this is
becoming ; k.
So, if I consider even say k, and C1 it is 10 µF; then also the it is becoming
dominant. But of course, in case if you are picking say this value, this C1 it is say maybe
1 µF; then of course, the candidate to define the lower cutoff frequency, it will be the
first one, ok. So, most of the time what you do that, this value of this capacitor it is
almost 10 to maybe a few, 10 times higher than this one or rather sometimes it may be
even 100 times higher than this one C1. On the other hand C2 normally we take same as
this C1.
Now this numerical examples as I say that, indirectly it is giving you some idea that what
may be the typical value of this C1 and C2 to get the whatever we have discussed that
lower cutoff frequency and upper cutoff frequency, right. And upper cutoff frequency of
course, again it is coming from this RC and CL and RC it is it was in the similar value or
at least it is an order of magnitude it is similar to the previous example.
So, the upper cutoff frequency again it will be in the order of around few 100 of kHz. So,
that gives you some idea that what may be the practical value of those lower and upper
cutoff frequency you can get, or the frequency response you do gain.
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So, what we have covered today, let us let me summarize that, today and previous day.
So, the first part, this part we already have discussed before, and today we have covered
this part. The frequency response of the CE amplifier having fixed bias, and when you
say fixed bias it may be only with RE or RE ⫽ CE. And then we have discussed about
numerical examples for common source amplifier, common emitter amplifier with two
category two types; one is fixed bias, another is the self-biased, sorry this is self-bias.
Today we have discussed the self-bias, but not the fixed bias, this is the type of. So, we
have covered the numerical examples for common source, common emitter with and
without CE and RE and then that gives us indirectly some design guidelines. So, later on
if we find sometime, probably we may revisit to this design guidelines; but for the time
being at least we got some idea that what may be the value of this C1, C2 and CE to get
meaningful upper and lower cutoff frequency, so that the mid frequency range it will be
sufficiently wide.
And as we say that, this is in the order of say or roughly 50 kHz and this is in the range
of maybe 10’s of Hz. So, that gives us one amplifier which is definitely suitable for
audio kind of application. I think that is all we do have.
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Prof. Pradip Mandal
Lecture – 40
Frequency Response Of CE/ CS Amplifiers Considering High Frequency Models Of
BJT And MOSFET (Part A)
So, dear students so, we will come back to our NPTEL online certification course on
Analog Electronic Circuits, myself Pradip Mandal from E and EC Department of IIT
Kharagpur. Today’s topic of discussion it is Frequency Response of CE, CS Amplifiers
Common Emitter and Common Source Amplifiers Considering High Frequency Model
of BJT and MOSFET.
In fact, we already have started about this frequency response of CE amplifier and CS
amplifiers, but there we did not consider capacitances associated with the MOS transistor
itself. So, today’s discussion it is a we will see what will be the impact of the
capacitances associated with the devices the transistors on its frequency response
particularly for common emitter and common source amplifier.
Compared to our overall flow and overall plan where we stand today it is we are in
module-4 we have done quite an extent about the frequency response of common emitter
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and common source amplifier. Today we will be extending that for frequency response
considering high frequency model of BJT and MOSFET transistor.
So, the concepts we are planning to cover today is the following. First of all we like to;
we like to highlight the points that the impact of the high frequency response on the
frequency response of CE and CS amplifiers and then we will see that there is a need of
some theory, proposed by Miller called Miller’s theorem.
And then we shall use that Miller’s theorem to calculate effective capacitance associated
with the transistor in the frequency response and then we shall see the need of a
frequency response analysis for a special kind of circuit namely R-C followed by R and
Cin parallel. So, this frequency response of this kind of circuit we have not discussed.
We have discussed only R-C and C-R circuit, but here whenever we will be talking about
the equivalent circuit of common emitter and common source amplifier, containing the
capacitance is coming from the transistor, then we will see that there is a need of a R-C
circuit followed by C-R circuit. So, that is what we have to consider. So, we will be
having R-C and then R and Cin parallel. So, this kind of circuit we have to consider and
then after that we will be talking about some numerical examples. So, this is what the
overall plan.
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So, let we look back what is the frequency response we have discussed for common
source and a common emitter amplifier. So, this is a recapitulation as I say recapitulation
of whatever we have discussed so far. So, here we do have the CE amplifier and here is
the corresponding small signal equivalent circuit for that.
And so, likewise here we do have the common source amplifier and its corresponding
small signal equivalent circuit is given here. So, note that in this model in this small
signal equivalent circuit, for this transistor we do have rπ from base to emitter terminal
and then we do have gmvbe. In fact, this will be vbe.
So, this current source it is basically voltage dependent current source in addition to that
we may consider ro, but whatever the model we have considered so, far it does not
include the inherent capacitances associated with this transistor namely base to emitter
terminal capacitance called Cπ and then base to collector terminal capacitance called Cµ.
So, if you consider these two capacitances in this equivalent circuit, we are expecting we
will be having a Cµ part here and then Cπ part here.
So, likewise if you see the common source amplifier, here in the model of the MOS
transistor we do have the voltage dependent current source gm into Vgs and then we may
consider from here rds, but so far we have not considered inherent capacitances of the
MOS transistor namely gate to source capacitance Cgs and then Cgd. So, if I consider that
Cgs and Cgd what we are expecting that we will be having Cgd here and then Cgs here.
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Now, if I consider generalized model and here we do have the generalized model of the
two amplifiers namely common emitter amplifier and common source amplifier. So,
what you can see that the dotted portion is the macro model or the voltage source or
other voltage amplifier where we do have this is the input port and then this is the output
port within that we do have output resistance, input resistance and then also the voltage
gain.
Now, if I consider the Cπ, Cµ what we are expecting that from say input to output node
there will be one capacitance. So, likewise from input to ground there will be another
capacitance. Now, this capacitance input port capacitance for CE amplifier it represents
primarily the Cπ part and if it is a common source amplifier, then this capacitor
represents Cgs part on the other hand the input to output port bridging capacitance this
one it is representing Cµ or common emitter amplifier and then Cgd for common source
amplifier ok.
So, in summary so far we have discussed these two small signal equivalent circuit and
they are we have seen the frequency response now in our present discussion, we need to
consider two more capacitances in our discussion and that will lead to a frequency
response particularly for high frequency behavior.
So, what we have to consider now, it is given here as I said just now we need to consider
Cπ and Cµ for common emitter amplifier. Likewise, here we need to consider Cgs and Cgd
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for common source amplifier. So, this Cπ or Cgd depending on whether we are talking
about common emitter or common source amplifier, which increases the input
capacitance or that, contributes to input port capacitance and then we do have Cµ or Cgd it
is the bridging capacity capacitance between input and output terminal.
Now, we also consider since so, this Cπ and Cµ effectively they are providing input
capacitance, input parallel capacitance called say Cin to see its effect it is also we
consider the source resistance rs. Of course, if I do not consider source resistance even if
you consider say input capacitance, in the frequency response it will not be having any
effect because the signal applied at the primary input, it will be directly coming to the
input port of the amplifier.
On the other hand if I am having this rs if I consider the source resistance rs and then in
presence of Cin, I will be expecting one R-C circuit and naturally that will affect that will
change the frequency response of the amplifier. So, while we will be talking about the
frequency response considering high frequency model, we do consider this non zero
value of this rs, rs here and rs are here so we will consider the source is having rs here and
this source is also having source resistance rs.
So, if I consider this model and this model together we do have generalized model which
is given here. So, we do have C3. C3 representing either Cµ sorry Cπ or Cgs likewise, C4 it
is representing Cµ or Cgd depending on CE or CS amplifier. So, I should say this is the
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generalized model of the amplifier whether it is common emitter or common source that
can be analyzed by considering this circuit.
So, here while we will be talking about the frequency response, what we can see that
impact of these two capacitances we have to consider. And in this frequency response of
course, I have committed a small mistake in this circuit we should be having C2 here. So,
this is the C2 and this additional capacitance. So, whatever the capacitance you are
putting here that is basically the CL instead of C2 it is CL ok.
So, now our task is to find the frequency response of this equivalent amplifier
representing both common emitter and common source amplifier. So, to analyze this
circuit let we try to see that, what the additional things we have to do are.
So, if you see carefully in this circuit as I said again I have repeated this mistake, we
should be having C2 here and then this should be CL. Now, as I said that this C3, C3 it is
the input port capacitance and this input port capacitance, it is forming R-C circuit with
this Rs and whatever the equivalent parallel capacitance. So, do have. So, it is
introducing additional RC effect at the input port earlier in absence of say Rs and R3 we
used to consider only C1 and R1 to get the frequency response.
Now, we do have this resistive element and this capacitive element. In fact, we also have
this capacitive element, but before we translate this capacitive element we need to be
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careful that C4 it is connected between the input port of the amplifier and the output port
of the amplifier.
So, we need a special treatment to translate this C4 in terms of or into two equivalent
elements one is at the input port and another one it is at the output port either you can
consider here or here. Now, I must say that this splitting of this C4 capacitance a one for
input port another is for output port, it is normally done by a theory proposed by Miller
which is commonly known as Miller’s theorem.
So, before we go into the detail analysis let me go through this Miller’s theorem first and
then we split this C4 into these two equivalent components and then we will be going for
the frequency response of the amplifier right. So, and the other point I like to mention is
that whenever we will be talking about the frequency response considering say rπ sorry
Cπ and Cµ or Cgs and Cgd we may consider that whenever these capacitors are prominent
the C1 and then C2 they may be successfully allowing the signal to go through this.
So, for simplicity whenever we will be talking about the effect of C3 and C4 we may
short this one. So, that you have to keep in mind mainly because the typical value of say
C1 and C2 if you see, this these capacitors maybe having higher than microfarad. On the
other hand typical value of say C3 and C4 they may be in the range of 10 pF ok.
So, naturally the frequency range over which we will be considering the effect of C3 and
C4 there you may consider that C1 and C2 effectively they are simply shorting their two
terminals. So, now, we like to go into this Miller’s theorem and try to see what it is and
how we split the input to output bridging capacitance into two parts; one is for input port
another is for the output port.
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Now in general here suppose we do have one amplifier and let me consider the signal at
the input it is voltage. So, likewise we do have output signal also in the form of voltage
and then we do have that mean amplifier A, which means that Vo = AVin right. So, the
signal it is going from left to right. So, we do have input port and then we do have the
output.
So, you may say whenever you are talking about Vo we are considering the voltage at
this terminal with respect to common terminal called ground likewise at the input we are
feeding the signal Vin with respect to the common terminal. Now, we do have this
bridging element. So, in general it may be resistive, it may be inductive or it may be
capacitive or it may be combination of that but whatever it is, this element it is bridging
the input port and output port.
Now this input port to output port relationship signal relationship can be represented by
this one excluding this Z element the bridging element. Now, in presence of this Z that
makes the analysis a little complicative. So, a better approach and efficient approach is to
split this capacitor sorry I should say this Z element into two equivalent element; one is
for the input port, which is connected with respect to common node ground and let me
call this is Z1 and since the other terminal it is connected to the output port we also need
to consider its effect before we remove it and let we call this is Z2.
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So, we can say that effect of Z it is getting captured by the Z1 and Z2. So, we can see
once it is getting translated into the it’s equivalent parts then you can remove this one.
So, that is what your this diagram it is representing that we are splitting the bridging
element into two equivalent parts called Z1 and Z2 one for input port another is for the
output port.
Now, when do I say that they are equivalent? So, first of all if we feed a signal Vin, then
if I call that these two circuits are equivalent and then if you feed the same signal Vin,
then the condition for this circuit and this circuit should be same which means that if I
am feeding a voltage here and then whatever the current supposed to be flowing through
this element, that should be seen for this circuit also.
Now, for this circuits the current or the if I call say this is I1. So, for this case the current
expression I1 = . Now, we also know that Vo = AVin. So, this can be written as
Vin(1 ‒ A). So, by replacing this Vo by expression we are getting .
Now, on the other hand if you see in this case and if I call this current it is say I1 dash.
So, I1 dashed we can write this is equal to . Now, to claim that these two circuits are
equivalent we have to equate these two currents or these two currents should be equal
and so, we can say if I equate these two, what we are getting here it is Z1 = right.
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So, likewise if I say that these two circuits are equivalent for the output port, then similar
kind of things we can do for the output port. So, please try to remember this relationship
Z1= .
So, then if I consider a output port and if I stimulate this circuit by say Vx or instead of
calling say Vx say this Vo. So, if I say that this Vo if it is coming here. So, let us not
stimulate sorry. Let us not stimulate suppose we are applying Vin and then we do have Vo
here and if the voltage here it is Vo the current run through this circuit, it is say if I call
I′2.
So, I′2 dashed it is equal to . On the other hand the current flowing through this circuit,
if I call it is I2 and in this case I2 = and we know that Vo = AVin. In other words
we can write Vin = . So, this Vin you can replace by this expression. So, what we are
getting here it is ( ).
Again if I say that these two circuits are equivalent for this output port, then we can say
that this current and this current expression they should be equal. So, if I equate this with
. So, that gives us the expression of Z2 = or you can say that this ( .
)
( )
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So, in summary these two circuits it will be claimed as equivalent provided the Z1 =
and then Z2 = right. So, and so, this is what the whatever it is called Miller’s
( )
theorem and as I said that this Z it may be capacitive, it may be the inductive or it may be
resistive element or it may be combination.
Now, in our application in our today’s discussion we do have one amplifier and then we
do have input to output bridging capacitance either it may be Cµ or it may be Cgd
depending on CE or CS amplifier and then we can try to see what will be this
capacitance it can be splitted into two parts one for the input port another is for the
output port ok.
So, the in the next slide we consider a special case of this Z and we consider this C and
then we will try to find what will be the corresponding equivalent capacitance, we do
have a here and here.
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So, here we do have the circuit of our discussion namely we do have this amplifier and
its gain it is a and we do have the C it may be as I said it may be Cµ or a Cgd that you call
it a C and this capacitor it can be replaced by its equivalent two parts. One is for input
port another is for the output port and how do we say that this is the equivalent? So, the
impedance of this capacitance which is should = .
( )
Now if I rearrange this equation what we are getting here it is Cin = ( ). Note that
here this whenever we are defining this A we consider Vo = AVin. Now, in case if A is
having ‒ sign so; that means, this part it will be getting plus. So, that you have to keep in
mind whenever we will be talking about the actual circuit. On the other hand the so,
that is the you see Z2.
So, this was Z1 this is Z2. So, this = right ok. So that gives us Cout = C ( ). In
( )
fact, ok. So, these two equations it will be used for our analysis and this is valid even if
you consider the finite output resistance. So, in this case of course, the bridging element
it is not connected here instead it is connected after the resistors, because this may be
part of the model of the amplifier.
So, we can say this is the terminal equivalent resistance of the amplifier output port right.
So, even for this circuit if I consider the signal coming here and the signal coming here
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they are almost equal. So, if I say that even though we do have this resistance, if I say
that this Vo it is practically Vin × A. So, then also we can use this relationship namely Cin
= C (1 ‒ A) and Cout = C ( ).
Now, in case if you want to really consider this Ro then this A part. So, this A part should
be replaced by whatever the gain you get from this point to this point. So, in case the
corresponding gain from here to here it is A′, then this A should be replaced by A′ this A
should also be replaced by this A′ right. So, depending on the situation we may consider
this A′ or we may say that A′ ≈ A. So, this is the Miller’s theorem it will be used in our
frequency response analysis ok.
So, let me take a break and then we will come back for continuing this topic.
566
Prof. Pradip Mandal
Lecture - 41
Frequency Response of CE/CS Amplifliers Considering High Frequency Models of
BJT and MOSFET (Part B)
Yeah. So, welcome after the break. So, we are talking about the, in fact, what we got it is
the generalized model of CE and CS amplifier here. What it is having here it is the input
signal source, having the source resistance of Rs, and then signal coupling capacitor C1,
and then if I consider this is the main amplifier where we do have the input resistance
represented by this R1.
And then we do have voltage dependent voltage source, which means that this is the core
of the amplifier, then we do have the output resistance R2. And then C3 and C4, they are
representing you know either Cπ, Cµ or Cgs and Cgd based on whether the circuit it is CE
amplifier or CS amplifier.
So, this particular this capacitor it can be converted into two equivalent capacitance; one
is for the input port, the other one is for the output port. And then, the input port part
coming out of the C4 it is what we said is that C4 (1 ‒ Av) or in this case Av is equal to
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Ao. In fact, if you see here we are putting a ‒ sign here assuming that the polarity of the
voltage dependent voltage source, here it is +ve.
And on the other hand, so this is the contribution coming to the input port earlier we used
to call C1. Now, let me put a different name C4-in; that means, the input port capacitance
coming due to C4. So, likewise the output port capacitance coming due to C4, let you call
this is C4-out. So, this is equal to C4 ( ). So, if I consider this gain it is very high and
in case if it is having ‒ sign here or the polarity here it is opposite then we can consider
that C4-in it is just C4 multiplied by 1 plus magnitude of the voltage.
So, this capacitance it is coming in addition with C3 as a result we are getting the net
input capacitance Cin = C3 + C4 and then multiplied by (1 ‒ Ao). On the other hand the
output capacitance net output capacitance of course, we do have CL. So, the CL is coming
as is plus this part namely C4 ( ).
Yeah, I like to mention one thing here it is in the actual circuit CE amplifier or CS
amplifier, typically we do have one DC decoupling capacitor or a AC coupling capacitor
and typically used to name as C2. And then the C2 and CL if I consider their typical
magnitude, this may be in the order of say 10 µF whereas, the CL may be in the range of
say 100 pF.
So, as a result the load coming at this node due to the series connection of C2 and CL
practically it is dominated by CL. So, that is why at this node or at this node whatever the
effective load capacitance we do have coming out of say these two parts it is getting to
be equivalent to CL, ok. So, that is why we are not considering this C2 in this analysis.
So, in summary what we have it is at this node we do have the Cin and then at this node
we do have the net Cout. Now, to get the frequency response of this circuit namely
starting from this point till the primary output what we have it is we do have one network
here and then we do have of course, the main amplifier starting from this point to this
point and then of course, at this point we do have the Cout. The board looks like clumsy,
so, let me clear and then summarize it.
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What we have what I said is that from here to here the gain it is defined by Ao, in
addition to that we do have this resistance coming in series with or getting loaded by net
output capacitance called Cout. On the other hand, from this point to this point if we see
the circuit we do have one R, we do have one C and then we do have one R here and
then the effective input capacitance coming from C3 and C4 together. So, that gives us a
network something like this.
So, once to get the overall frequency responses we need to get the frequency response
from this point to this point and then of course, here to here. So, just to start with let we
see the first part, namely this part and the corresponding circuit it is given here, in this
diagram. We do have the input signal, we do have the source resistance, we do have the
C1 in series and then we do have the effective input resistance, in this case you may call
it is R1, but whatever the resistance we may name as Rin. And then C3 and C4 together it
is contributing to the net input capacitance with respect to ground that is called Cin.
So, our first task is to find the frequency response from this point to this point, namely
may be in Laplace domain we can see, and then we can find what is the
corresponding transfer function we are getting. So, in the next step, next slide what we
are going to do? We are going to analyze this Rin series with C, in series with Rin ⫽ C.
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So, we do have this circuit, we do have R, and then C, and then R and the C coming in
parallel. Now, if you see here to get the frequency response of this circuit namely in
( )
Laplace domain ( )
we can get the transfer function by considering this impedance
which is Rin ⫽ and then Rs in series with + Rin ⫽ .
Now, the numerator part, you can further simplify, and you can see that this is .
And in the denominator, we do have Rs + +, this part it will be the same as this
. Now, if I further simplify, so this factor, once it is coming in the numerator it is
getting cancelled with this factor, but then we do have sC1, so that gives us in the
numerator we do have sRinC1.
And in the denominator we do have all these things getting multiplied. So, what we
have? We do have, this RssC1(1 + sRinCin), so that is the first term. And then we do have
the second term where we do have 1 + sRinCin and then we do have the third term which
is sRinC1.
So, in the denominator we do have force one and then we do have the s term; s term we
do have here we do have here and also we do have here, in addition to that we do have a
square term as well. So, in the denominator if I further expand it, what we are getting is
that numerator is remaining sRinC1 divided by 1 plus s. We do have RinCin +, we do have
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RinC1, and then also we do have an sRsC1, and then we do have a square into C1 Cin Rin
and Rs, right. So, the transfer function here which is written here you can see that it is
having a 0 here, due to this s term, and also since it is second order polynomial in the
denominator, so we are expecting two poles.
Now, let we consider a typical numerical value and based on that we make some
assumption here. So, what we have here it is Cin which is a typically much smaller than
C1. So, probably we can ignore this part and then we can consider this term and then we
can take C1 outside. So, in the denominator if we do this approximation we do have sRin
and then C1 that is coming in the numerator and in the denominator we do have 1 + s,
then Rin + RsC1 and then we do have the s2 term, coefficient of s2 it is given here which is
RinRsCinC1.
In fact, this can be well approximated by considering two factors and if I consider a
typical value again we can do some assumption valid assumption to simplify the
denominator and what we can get that we can get two factors one factor is coming from
here, namely 1 + s(Rin + Rs)C1. So, this is the first factor.
And then the second factor, it should be such that the coefficient of s square should
match. In fact, that can be shown that the second part; second factor it will be 1 + s. So,
then we do have Rin then , ok. So, in fact, if you if you multiply of course, there is
an assumption that here this term of course along with this term we do have one more
term which is one multiplied by this part, but we assume that term it is very small and
then product of this s term and this s term it is matching with this.
So, here we may say that the first term it is giving a pole called p1. So, we can say that p1
it is coming from the first one and the location of the pole it is ‒ ( . And then the
)
second pole p2, it is coming from the second factor and it is given by ‒ . In
( )
addition to that, this since we do have the s term here in the numerator. We also have a 0
at 0 frequency.
Also if you see that the in the mid frequency range, what may be the attenuation? When I
say mid frequency, what does it mean is that if you consider the coefficient of s is
dominating over this one and s square term, and if I say that if this is dominating; that
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means, if I drop this two part then what we can get in the numerator we do have R in and
C1 and in the denominator we have (Rin + Rs)C1, C1 C1 it is getting canceled, s s getting
canceled. So, we can say that mid frequency gain, if I call say whatever it is, A defined
by mid frequency that is coming .
Let me explain the intuitive way of ah analyzing this circuit. What we have it is the
frequency response let me use this space. The frequency response if you see probably I
can use this space no; that means, this space. So, if I see that the gain of this circuit it is,
so this is the frequency in log scale and this is dB. So, in very low frequency we do
have a 0 and then we do have pole, and after that the gain it is getting stabilized; that
means, this is the attenuation and that attenuation is given by this and then we do
have the second pole.
So, we do have the first pole here p1 given by that expression and then we do have the p2
given by this expression and it starts with a 20 dB/dec slope at the beginning which
means that it is having a 0 at 0 frequency. And this attenuation it is essentially and
this needs to be converted in dB.
So, now coming to the intuition in very low frequency this capacitor it is blocking this
signal to propagate here. So, that is why you do have lot of attenuation here, but then
with progress of frequency this capacitor it starts allowing the signal to come to this node
and that is what the indication that as we are increasing the frequency the signal it is
propagating here. And then we do have a situation where this capacitor almost it is
working as a short and leaving behind we do have only this Rs and Rin.
This capacitor yet to show its effect. So, in the mid frequency range what we have it is Rs
and Rin series input we are applying at this node and then the output you are observing
here. So, if you see this circuit of course, the attenuation from this node to this node it is
defined by . So, that is what the attenuation we are getting here in the mid
frequency range.
Now, once we have this circuit. So, entire portion it is working as a Thevenin equivalent
signal source, and its Thevenin equivalent resistance now it is Rs ⫽ RE, right. And then
we do have then Cin connected here, right. And this signal it is not just vin it is attenuated
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version of vin. So, I should say this is vin × . So, from this frequency onwards this
is the model. And then based on this resistance Rs ⫽ Rin and then Cin we do have a pole.
So, that is why the expression of this pole if you see it is coming from this resistance
which is Rin and Rs in parallel and then we do have the Cin. So, that is why the pole we
do have here. So, that is the interpretation of this frequency response.
So, in summary what we like to say here it is the frequency response of this circuit
starting from this point to this point is given by; so, this is the frequency maybe we call it
is radian per second and then we do have the gain in dB. So, this is in log scale, typical
bode plot, right, and very low frequency we do have we do have a 0 and then we do have
a pole where this capacitor it is just sorting the signal beyond that that frequency, and
then after that this capacitor it starts sorting the signal creating a pole here. And location
of this pole and this pole as I said this is and location of the other
( )
pole it is ( .
⫽ )
So, that is the frequency response of R-C in series with parallel connection of another R-
C. And this attenuation it is we should see this value, so this is the 0 dB level. So, this
value it is ‒ of course, it will be coming ‒, but they to write the expression 20
( ). Now, we shall use this frequency response for our frequency to get the
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frequency response of the CE and CS amplifier considering the high frequency model of
the transistor in the next slide, ok.
So, this is, so we are coming back to the generalized equivalent circuit; generalized
equivalent circuit of the C and C is amplifier which is given here and from this point to
this point we got the frequency response and then from here to here will be getting the
another part of the network. And hence, we can get the frequency response starting from
the primary input till the primary output.
So, to start with we already have discussed that if you consider say and we obtain the
corresponding frequency response like this, so this is and we already have discussed
the location of the pole and then we do have from this point to this point or say this
point. So, we can say and that is defined by this Ao. So, this Ao it is pretty high. So, we
can say that Ao it is constant. So, this is . So, if I combine this two; if I combine this
two, so what we can get it is that . So, if I plot, it will be similar to this one, but
it got lifted up. So, this is the this is .
And then we do have another R-C circuit and that R-C circuit of course, we do have
the resistance here, we do have the capacitance maybe primarily coming from the load
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capacitance and maybe some part of the C4 it is also contributing to the C. So, if I
consider on the other hand . So, there what we get it is of course, here to here it is
passive network, so it is starting with almost 0 dB and probably it is having a pole like
this, right. So, this is .
Now, if I combine say and this curve together. So, then we can get the overall
frequency response now let me use a different color here maybe black color yeah. So, to
get that is the complete overall frequency response to do that I need to combine this
curve and this curve; so that v2 and v2 are getting canceled we do have vo in the
numerator and then vin the denominator.
Since, it is having this curve it is having 0 dB here, so I should say this is not disturbing.
So, this characteristic curve it is supposed to be same as like this and then it will be
coinciding like this and then probably we do have the pole here, second pole, so this
pole.
So, now, we like to say that the location of this pole, so the net frequency response now
we obtain it is like this, and so this is the overall frequency response blue color. And
location of this pole p1 it is coming from this network, initial network you may recall its
expression is and then we do have the Cin. And Cin, we have Cin that
( )
C3 and C4 they are contributing, this pole we say that p2 which is ( , earlier who is
⫽ )
to say that this is Rin that is multiplied by sorry, this is not Cin this is rather C1 and here
we do have the Cin.
And then also we do have the other pole coming from this network and this pole it is we
may call this is p3 and that is defined by this R2, and the net capacitance at this output
node probably this may be CL and then contribution coming from the C4 and that may be
C4( ) and all practical purposes you may consider this is , ok.
( )
So, this is typically what the frequency responds we do expect. But of course, it depends
on the numerical value of the different components. Say for example, in case if this pole
third pole if it is appearing before the second pole which means that if this violet color
instead of; instead of having a pole here if it is having a pole somewhere here, then
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obviously, if I call say this is a possible situation maybe say this is p′3. And then if I
combine this pole or rather this frequency response; this frequency response with this
one and if the location of the third pole it is here which is a before this one obviously,
that will define the overall frequency response having a pole here.
In other words, the lower cutoff frequency typically it is coming from this one, so we
may say that ω lower cutoff frequency it is defined by p1. On the other hand, the upper
cutoff frequency it is defined by minimum of this p2 and p3 whichever is minimum, so
that defines the, so that defines the upper cutoff frequency. So, in our numerical
example, so we will see that two cases where for one case maybe this p2 is lower, in the
other case maybe the p3 is lower. So, probably with that numerical example thing it will
be even clearer.
So, we are going to talk about numerical examples, but before that let me take a short
break and then will come back.
576
Prof. Pradip Mandal
Lecture - 42
Frequency Response Of CE/CS Amplifliers Considering High Frequency Models of
BJT and MOSFET (Part C)
Welcome back after the short break. So, we are going to discuss about numerical
example, and the circuit it is still that equivalent circuit we do have and what we are. So,
we do have the generalized equivalent circuit, but then also we do have additional
information namely the value of different components, R1 this input resistance is 1.3 k,
then R2 output resistance it is a 3.3 k and then let you consider source resistance 650 Ω
that is also a typical value one possible value of typical signal source.
And then the load capacitance CL 100 pF, C1 it is given here it is say 10 µF and then C3
which is one of the element contributing to input capacitance it is say 10 pF, C4 the
Miller effected capacitance the capacitor which is breezing the input and output terminal
of the circuit is 5 pF. And let you consider this voltage gain Av or Ao in this case we are
denoting this by Ao which is a 240 with a ‒ sign.
So, that means, actually this is ‒ and this is +. So, anyway with this information let we
try to get the frequency response and particularly containing the mid frequency gain and
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then lower cutoff frequency and then upper cutoff frequency. So, how do we proceed?
First of all this resistance directly given there, but then need to calculate the input
capacitance.
So, to start with let we calculate Cin and Cin = C4(1 ‒ (‒240)), then + C3. So, we do have
5 here and then × 241 + 10. So, that gives us how much; we do have 1215, 1215 pF, yes.
So, we do have the Cin is given here, with this Cin we can calculate the location of the
second pole and let we calculate the first pole first. So, p1 which is defined by if I express
this in the unit of Hz then we have to consider 2π. So, 2π× , so this = .
Rs it is 650 and then R1, R1 it is 1.3 k, so that is 1950 this resistance and then C1 it is 10
µF which means 10‒5. And if you calculate it, I have done this calculation for you. So,
what you will get it is 8.16 Hz, right. So, you got the lower cutoff frequency is this one
and then we can get the second pole p2 which is coming from again Rs and R1 in parallel
and since it is in Hz.
So, we have to consider 2π, so 2π (Rs ⫽ R1) Cin and the value of the Cin it is given here.
So, this becomes into this resistance, these two resistances in parallel, so we do have
650 and 1.3 k it is coming close to 400. In fact, to be more precise it is 433.3 Ω and then
Cin it is 1215 × 10‒12. And if you do this calculation what you will be getting it is close to
300 and to be more precise 302.4 kHz.
So, we do have the second pole it is given here 302 kHz. Now, you can also calculate the
third pole p3 which is coming from R2 and then output resistance. So, p3 it is it is 3.3
k, so you have 3300 Ω and then output resistance it is when you have CL = 100 pF and
then the C4 it is almost coming as is, so we can see roughly 105 pF, 10‒12. So, if you do
this calculation what you will be getting it is 459, in my calculation that is what I obtain
459 kHz.
And as I said that since this is higher. So, the upper cutoff frequency it will be decided
by p2 and lower cutoff frequency it will be coming from this one. And also to get the mid
frequency gain, so mid frequency again it is of course, this multiplied by whatever the
attenuation coming from these two elements. So, what is that attenuation? So, I should
say mid frequency range equals to and R1 it is 2.3 this is 0.65 k, so that and
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that gives us the overall gain, let me use different color. So, overall gain, Av-overall, so that
= × 240 with a ‒ sign and this = 160, right.
So, we should say that the overall frequency response of this circuit, it is something like
this. So, I do have some space here. So, let me utilize this space. So, mid frequency gain
it is given here, maybe we can convert that into dB and then we do have the lower cutoff
frequency here and then upper cutoff frequency. So, the lower cutoff frequency it is 8.16
and then the upper cutoff frequency it is this one and this is because this is lower than the
p3 part.
Now, let we go to a one axial circuit. So, as I say that this is equivalent circuit and of
course, the value we have picked up here it is very close to whatever the equivalent
circuit we get out of actual circuit, but for you to get a feel of that let me consider one
practical circuit.
So, in the next slide we do have CE amplifier having fixed bias arrangement and
different components of, so different components of this bias as well as the other value
the capacitors and all it is given here. So, RB, RB it is 570 kΩ, supply voltage it is 12 V
and then VBE(on) it is approximately 0.6. So, that gives the base current = 20 µA.
Earlier we have done this calculation and with multiplying with beta we do get the
collector current it is 2 mA, question collector current is 2 mA. So, that gives us the gm =
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. So, this = ℧. And in rπ, rπ of the transistor which is , so that is is that
means, 13 × 100, so that = 1.3 kΩ.
And then we have C1, C1 it is given here. So, this is C1, C2 it is also = same 10 µF. And
then we can connect a CL here, and this CL it is given = 100 pF. In addition to that we are
assuming that we do have a source resistance Rs to see the effect of this Cπ and Cin. So,
Cπ it is given in 10 pF and then we do have the Cµ it is given us 5 pF.
So, from that let we and of course, the RC it is given here. So, from this parameter, so we
can probably we can try to find the voltage gain, and then input capacitance, input
resistance and so and so. So, first of all input resistance Rin which = RB in parallel with
the input resistance coming out of the device, so that is rπ. And this = 570 k in parallel
with only 1.3 kΩ. So, you can approximate this by considering 1.3 kΩ, it is dominating.
So, that gives us the input resistance.
Now, before we calculate the input capacitance, so we need to know what will be the
gain from this point to this point and that gain if I call say Ao = gmRc, and so this = ×
3.3 k, 3300. So, that is becoming equal to close to whatever earlier we obtain or earlier
we have taken, but to be more precise I think it is 254, of course, with a ‒ sign. So, the
voltage gain here it is ‒ 254, input resistance it is 1.3 k and then we can calculate the
input capacitance, Cin = Cπ as is + 5 pF, Cµ × whatever (1 + 254).
So, if I put the value here it is 10 and then value here it is 5, so that gives us 10 + 5 ×
255. So, that is giving us 1285 pF capacitance, ok. So, now, we can calculate by
considering this Rs, we can calculate the pole location of the pole. So, let you consider
first pole p1 which = . In fact, this calculation we already
have done for the previous example and that gives us 8.16 Hz.
On the other hand, we can calculate p2, p2 also it will be very similar. So, let me use this
space here to calculate p2. So, the expression of p2 it is 5 sorry (650 ⫽ 1300) × Cin, so
that is 1285 pF, 10‒12. So, with this, so this is again this part it is coming whatever 433
and with that what we get of course, this capacitance it is slightly different and this gives
us 286 kHz.
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Now, if I calculate the third pole namely the pole coming from the output resistance
which is RC and then the CL, and RC it is given here. So, the third pole let me use this
space. To calculate the third pole which is which is RC and then
output capacitance which is 100 and then also Cµ coming there, so that is 105 pF. In fact,
if we calculate this what we can get by putting the value of this RC = 459 kHz.
Now, if I compare the p2 and p3 since p2 it is lower, so p2 defines the upper cutoff
frequency fU. And then of course, p1 it is defining the lower cutoff frequency fL. And
then the gain overall gain, of course it will be this multiplied by; this multiplied by
whatever the attenuation coming out of Rs and Rin. So, the overall gain Av-overall = so this
= , in fact, that is × 254 of course, with a ‒ sign and that is becoming close to ‒
169.
So, in summary the mid frequency gain it is 169, lower cutoff frequency it is 8.16 Hz and
then upper cutoff frequency it is 286. So, that is the overall frequency response or the
common emitter amplifier given here. Now, we can similar kind of exercise you can try
for common source amplifier.
So, again this circuit is very similar, but we need to be careful here that gm of this
transistor MOS transistor, since it is much lower than gm of BJT, so we are expecting the
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gain here it will be much lower and then we can see what is its consequence in the
frequency response.
So, here we do have the value of different bias elements namely R1 and R2 are given
here, 9 k and 3 k respectively. We do have the supply voltage 12 V. And then for this
device parameters are given here namely transconductance factor it is 1 mA/V2,
threshold voltage it is 1 V and then RD the passive load it is 3 k.
Now, if I analyze say this part to find the voltage here, since it is 9 and since it is 3 the
voltage coming here it is 3 V from this 12 V, right. And once we have the gate voltage 3
⁄
V and threshold voltage is 1 then we can say that this IDS = × (3 ‒ 1), (
) , so that = 2 mA.
In fact, with this we can also get gm of the transistor it is 2 mA/V. Earlier we have done
this calculation and we can assume that the λ is very small. So, we can say that ro or rds is
very high; we may consider this as very high. So, the voltage gain voltage gain from gate
to drain of this amplifier it is gm × RD with a ‒ sign and that = 6. So, we got voltage gain
from here to here it is only 6.
Now, we can calculate the input capacitance using this information. So, we do have
voltage gain it is only 6, so the Cin, so the Cin part it is we do have Cgs which is 10 pF and
then Cgd 5 (1 ‒ (‒6)). So, that gives us 45 pF only. And on the other hand, if we connect
the CL here which is 100 pF given here and if this is 10 µF, so effectively these two
together it is giving us 100 pF and of course, we have to consider effect of Cgd and this is
Cgs, so effect of Cgd it is coming here almost as is.
So, we can say that Cout it = CL + Cgd approximately, right and so that is we can see it =
105 pF. Now, based on this information of course, we need to know the input resistance
here Rin and gate to source resistance of coming out of the device it is very high. So,
input resistance it is coming from the bias circuit only and also we consider the source
resistance to get the effect of Cin and the source resistance it is given here it is 750.
So, Rin now it is R1 ⫽ R2, so that = 2.5 kΩ. So, we do have Rin = 2.25 kΩ, then Rs is 750.
So, the first pole let me use different color here. Fi=rst pole p1 coming due to series
connection of Rs and Rin and C1, C1 it is here C2 it is here So, this is 2π, then (Rs in series
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with Rin) × C1. So, that = into we do have together series connection of Rs and Rin this
is actually 3 k, 3 k and then C1 it is 10‒5.
So, that gives us the lower cutoff frequency of this circuit it is even lower than the
previous case. So, this is equal to 5.3 Hz only. So, we got the lower cutoff frequency it is
coming here. Then p2, if you consider p2 which is then (Rs ⫽ Rin) and then × Cin and
Cin it is only 45 pF, so this = ×. So, these two coming in parallel, so that gives us let
me check in my calculation.
So, this is Rs = point or let us say 750 ⫽ 2250 and then 45 pF. In fact, this is becoming
quite high particularly the capacitance, it is low this = 6.28 MHz. So, note that the value
of this capacitance it is higher, sorry the lower that makes this p2 it is higher.
Now, let me also calculate p3 which is coming from RD the output resistance here let me
use this space here, ok. So, we do have 2π here and then RD and then Cout. In fact, if you
consider the corresponding numerical value here, so this is × RD it is 3 k and then Cout
it is, so this is 3 k sorry. Cout it is 105 pF and in fact, this is becoming 505 kHz.
Now, this is the case where what we are getting is that this frequency it is lower than this
one. So, naturally the upper cutoff frequency it will be decided by p3 of course, the lower
cutoff frequency it will be decided by p1, ok. So, this is the; this is the example where I
was talking about that this p2 it is not defining the upper cutoff frequency, it is rather p3
the output node pole it is still defining the upper cutoff frequency.
And then what is the mid frequency gain? We do have the gain of 6, that need to be
multiplied by the attenuation coming from Rs and Rin and the attenuation there it is of
course, that is 0.75 and we do have the input resistance it is 2.25. So, overall gain Av-
overall = we do have ‒ 6 × . So, this part it is becoming 3 and. So, this is ‒ 6 × ,
so that gives us ‒ 4.5. So, the mid frequency gain it is only 4.5 and the lower cutoff
frequency it is 5.3 Hz, upper cutoff frequency it is 505 kHz, ok.
So, anyway we know that this circuit will be having low gain, but the exercise here what
you have seen here it is because of the low gain the input capacitance, it is not so high.
As a result the upper cutoff frequencies it is still getting decided by the pole coming from
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RD and CL or output capacitance. Now, we can do probably one more exercise which is
cell biased, but I suggest that probably you can try it out to solve this problem.
So, I will be giving little hint to solve this problem. First of all here again we shall try to
find the operating point of the transistor. So, if you consider R1 of 9.9 k and R2 it is 3.3 k.
Again, the voltage coming here it is 3 V. So, we do have the value of this resistance it is
9.9 k and we do have 3.3 k, so that gives us 3 V here. And with this 3 V if you consider
that we do have the base to emitter voltage drop of 0.6, in fact, that gives us this voltage
= 2.4 V.
Now, of course, we are assuming that while the base node it is connected here and then
the base current it is flowing here we are assuming that this voltage the base voltage it is
not changing. And in this case it is valid because the internal current here through this
resistor R1 and R2 before us connects this base terminal it was much higher than the
anticipated base current. So, even after connecting this base terminal we can see that the
VB still it is very close to 3 V, right.
So, once we have 3 V here then if we reduce this drop of point 6 then we do have 2.4 V
coming at the emitter. And then if we consider RE which is 1.2 k that gives us the emitter
current IE = which means that the IE = 2 mA. And we can also approximate that this IC
is also equal to same, so that is also 2 mA. And then from that you can calculate gm
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which is ℧, then we can calculate rπ which is 200, β, is . So, that is , so that = 2.6
kΩ.
Now, the input, so that gives us the input resistance Rin = R1 ⫽ R2 ⫽ rπ. Probably, you
can check I think in my calculation it was coming 1.268 kΩ and the voltage gain of
course, the internal circuit voltage gain from base to collector Ao which is gm × RC
assuming that this emitter register it is successfully bypassed by this capacitor CE. So,
this it becomes RC we do have 2.7 and then gm it is , so that gives us a gain. So, this is
k of course, × 1000. So, this gain it is coming close to 200, in fact, 207.7 with a ‒ sign.
And using this you can calculate what is the input capacitance, namely Cπ + Cµ (1 +
207.7). I think in my calculation I was getting close to 1 nF, in fact, 1053 pF, right. So,
using this information of say Cin and then Rin you can calculate what will be the p1 by
considering the source resistance Rs which is given here. So, p1 again you can calculate
this is equal to and C1 it is given here it is 10 µF.
So, you can find the value of this one. Likewise you can calculate p2 and then you can
calculate p3. So, I will not be doing this one, probably, you can simply try it out and get
the corresponding solution.
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So, in summary what we have so far we have covered it is. So, in this module what we
have covered here it is basically we have considered high frequency model of transistor
and particularly in presence of source resistance Rs, what is its impact on the frequency
response of common emitter and common source amplifiers. And what you have seen
primarily, it is the change of the lower cutoff frequency and upper cutoff frequency and
also the mid frequency gain.
So, this is the main thing we have done and that has been done by properly calculating
the input capacitance for which we have considered Miller’s theorem. So, we have
touched upon the basic Miller’s theorem and then we have seen that that theorem it was
helping us to calculate the input capacitance Cin which primarily it was defining the
upper cutoff frequency. And then, also to get the overall frequency response we also
have analyzed R-C followed by R and C in parallel circuit and we obtain the
corresponding frequency response.
So, these two underlying theory it was helping us to get the frequency response of the CE
and CS amplifier. So, we started with analysis and then the expression of the poles and
all. And later in the third part of it we have considered numerical examples and
particularly for common emitter amplifier with fixed bias and common source amplifier
in detail, and we have given a hint of how to do similar kind of you know analysis for
common emitter amplifier having self-bias arrangement. I think that is all I do have.
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Prof. Pradip Mandal
Lecture - 43
Limitation of CE and CS Amplifiers in Cascading
Dear students, welcome to this NPTEL online certification course on Analog Electronic
Circuits, myself Pradip Mandal associated with E and EC department of IIT Kharagpur.
So, today’s discussion is primarily the Limitation of Common Emitter and Common
Source Amplifier particularly when it is when those blocks are getting cascaded. We
have discussed about the main feature performance of common emitter and common
source amplifier in our previous lectures.
But, then today what we will be discussing it is what are the limitations of this
configurations are there particularly when we cascade them. So, let us look into the flow
what we have and where we stand today. So, this is the overall flow, present we are in
the building blocks and under the building blocks we do have the fourth module or week
fourth modules and in this fourth module we are very close to the last item namely the
limitation of common emitter common source amplifier while we are cascading the
circuit.
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And hence, we establish the need of some other circuit configurations which are referred
as buffer. So, we will be discussing those things in detail. So, what are the concepts it
will be covered in this today’s class.
It is to appreciate what are the limitations or restrictions are there for common emitter or
common source amplifier configuration will revisit frequency response of common
emitter and common source amplifier, but then the basic difference is that we will
cascade to common emitter amplifier.
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And then we will see that what is the effect of cascading is there in the frequency
response. The effects are similar for common source also, but for completeness we are
keeping both the circuits. So, those effects are getting reduced or I should say almost
getting eliminated by introducing a buffer and hence, again we will be revisiting the
frequency response of common emitter followed by buffer and then followed by
common emitter.
So, by presence of this buffer in between we will see that it helps to retain the frequency
response of the original common emitter amplifier or whatever the things we are
expecting, similar thing for the common source amplifier also. Now, when we are talking
about buffer, we will see that to achieve meaningful cascading what are the features are
required out of this buffer. So, that also we will be highlighting. So, that is the overall
plan.
Now, the frequency response of say common emitter amplifier in this case we have
discussed more detail of frequency response of individual common emitter amplifier. Let
we talk about today it is we do have two maybe identical common emitter amplifiers or
architecturally they are identical. And to achieve say maybe higher gain or maybe for
some other reason we like to cascade this CE stage, it is first stage and then you may call
it is the second CE stage together.
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So, how we do that output of the first CE amplifier will be connecting to the input of the
second CE amplifier. But of course, with the use of C2 we can isolate the DC operating
point of the first stage and the second stage. And of course, the capacitor C2 it is
supposed to be allowing the signal going from the output of the first stage to the input of
the second stage.
So, in nutshell C2 it is helping us to separate the DC operating point of the first stage and
the second stage DC operating point. Now, while we will be connecting this circuit we
may be expecting that suppose we do have a gain of this stage; it is say A1 and then gain
of this stage it is say A2 we may be expecting that the overall gain say A = A1 × A2. So,
that is what we are expecting.
And also in case this A1 the first stage circuit, in case if it is having some certain
bandwidth and the second stage may be having similar kind of profile; maybe it is having
certain bandwidth. And then if we combined, so if we; so this is the second stage maybe
second stage frequency response.
And if we combine these two stages through this cascading we may be expecting that the
overall frequency response it may be having very high gain, and then the lower cutoff
frequency it is may be defined by whichever the lower cutoff frequency of the two stay
out of these two stages are higher.
And likewise the upper cutoff frequency it may be decided by the upper cutoff frequency
of the circuit which is having lowers value. So, this is what we are expecting the A
should be having higher gain and then the lower and upper cutoff frequency may be
decided by whichever is minimum or maximum out of this individual cutoff frequency.
But, in our surprise once we connect the circuit and if we if we make the observation
from the primary input to primary output we will see a significant amount of change of
this gain namely this gain may drop off here to some other value and also may be the
upper cutoff frequency may come down.
So, the out of the observation we may see two important thing; that the gain low free or
mid frequency gain it may be different from the product of mid frequency gain of the
two individual stages, and also the upper cutoff frequency may be different. So, how and
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let us see why we see that; here we have drawn the frequency in the low small signal
model of the individual stages and if I say that these two stages they are connected here.
So, if we connect the two stages then the resistance here RC one it is coming in parallel
with whatever the resistance it will be seen by the next stage. And also, if I see that input
capacitance coming from the second stage; if I call say Cin of the second stage which
may be primarily due to the Cπ of the second stage and then miller affected Cµ.
So, this Cin2; it is getting contributed by miller affected Cµ2 and then Cπ2 together and
then this Cin2 it may be forming a pole coming from this RC1 and maybe the input
resistance here. So, let we rearrange this circuit just to give a brief that in the small signal
equivalent circuit what we have it is voltage dependent current source here gm1 × vbe1;
where the vbe1 it is vbe of transistor 1. And then we do have the bias resistance RB1 and
then base to emitter we do have rπ1 and then base to emitter we do have Cπ1 and then base
to collector we do have the Cµ1.
So, considering all these small signal parameters what we obtain here is the overall small
signal model out of the first CE amplifier. Similarly, for the second stage second CE
amplifier; we do have the corresponding small signal equivalent circuit. And let it
consider that one load is connected here CL after the C2, rather C3. Now, if we further
simplify; this two small signal equivalent circuit, we can translate into maybe simpler
version. So, in the next slide we will be showing that.
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So, here these two small signal circuits are coming from the previous slide, and we can
simplify individual circuits like this. Say, we can translate this RB1 and rπ1 together in the
form of input resistance Rin1, which means that Rin1 is RB of this stage in parallel with rπ1.
And, then we are keeping this Cπ1 and then Cµ1 and this part we may translate into
Thevenin equivalent
So, the voltage dependent current sources; it is getting converted into voltage dependent
voltage source. So, the voltage here it is Av1 × vbe1; vbe1 is here, and as you know that Av1
it will be gm1 × RC1 with a ‒ sign ok. So, that is the Av1 part. So, likewise for the second
stage also we do have the rearranged or simplified equivalent circuit, it is having its
corresponding Rin again Rin it = RB of the stage RB2 and rπ2.
And likewise here we do have gain; we do have gm2 × RC2. And the resistance here it is
basically it is RC2, and here also this is RC1. So, that is how we can translate this
transconductance amplifier in the form of voltage amplifier and then input resistance and
output resistance you can express in terms of internal resistances.
Now, after this if you see here whatever the signal we are getting here before we connect
this circuit, we obtain the voltage here; it is same as whatever almost same as whatever
the internal voltage you do have. So, we can see the voltage here it is Av1 × vbe1, before
we make this connection. But, then the moment we make the connection; the moment we
make this connection what will what will happen is that this Rin2, it is loading the
previous stage as a result whatever the voltage now will be getting here it will be
different from this one. And the difference is coming due to the loading effect.
In other words, it introduces one attenuation factor which is defined by Rin2 and this
output resistance here. So, . Now, depending on the relative value of this Rin2
and Ro1 it may be having different value, but typically these two resistances may be
having the same order of magnitude.
In our previous example, we have considered that RC it was in the range of kΩ; may be
around say 2 to 5 kΩ. And this resistance also may be in the similar range may be in the
range of say 1 kΩ, as a result we can see this factor it will be one-third.
So, this factor with this value of RC1 and Rin2 this is becoming one-third. So, the overall
gain; whenever we see from primary input to primary output here to here the gain of the
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first stage considering the loading effect of Rin2, it is already having one-third
attenuation. But, whatever the voltage it is we are getting here of course, that is
considered as vbe2 and the second stage it is amplifying that.
So, the voltage coming at the primary output we can say, it is say vout = Av2 × vbe2 and
then this vbe2; this vbe2, it is Av1 × vbe1 multiplied by the attenuation factor . So,
what we are getting end of it is and of course, vbe1 it is same as say vin.
So, we can say end of it what you are getting here it is vin × Av1 × Av2 × the attenuation
factor. So, that attenuation factor it is . So, this is one attenuation it is getting
experience due to this cascading.
The second effect; second effect is on the cutoff frequency. So, let us see the cutoff
frequency. So, what we can say let me clear here yeah, the cutoff frequency particularly
the upper cutoff frequency it is having two candidates one is the cutoff frequency coming
due to this R.
And then CL and second one it is of course, this resistance loaded with Rin2 and then
whatever the input capacitance. So, do have that may be coming from Cπ and Cµ of the
second stage.
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So, this new candidate to define the upper cutoff frequency if you write. So, we can let
me write the expression of that cutoff frequency if I say that is ω; upper cutoff frequency.
So, it is coming due to the resistance Ro1 and Rin2 ⫽ Ro1 ⫽ Rin2 and then multiplied with
the input capacitance here.
So, the input capacitance in the high frequency of course, this C2 it will not be there
whatever the input capacitance it is coming primarily from this Cπ and Cµ. So, that we
can write say this is Cin of the second stage; and then this Cin it is Cπ almost yeah Cπ and
almost the Cµ × the (1 + the second stage gain Av2); and.
Since, we do have very good gain of the second stage that makes the Cin this Cin it is very
significant, and as a result the pole may be created or whatever the upper cutoff
frequency may be created by the Cin2 and then this effective resistance at that node that
may define the lower cut the upper cutoff frequency. Of course, if this upper cutoff
frequency it is less then whatever the original upper cutoff frequency defined by Ro2 and
CL was there then only it will be prominent.
So, I should say that whatever the ωU we have written, this is only one candidate and
affect that the overall we can say that ωU of overall. So, that will be of course, minimum
of minimum of this ωU and whatever the original upper cutoff frequency we do have;
namely ok. So, depending on the situation this upper cutoff frequency may be
different. So, what we have said here it is in the next slide we are going to summarize
yes.
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So, in the frequency response what we have seen in the CE cascaded amplifier. First of
all, its voltage gain; voltage gain overall voltage gain Av-overall, so, that = Av1 × Av2 × this
attenuation which is . So, this is one change and the upper cutoff frequency as I
was discussing there it is f; if I if I write in terms of the Hz then fU so that is minimum of

whatever the cutoff frequency we obtain; the candidate of this cutoff frequency as you
would say.
So, that is . So, this is this is miller affected capacitance here

⫽
coming to the input and the Cπ2 as I say that it is as; as it is. So, this is one candidate and
then other one it is the original one .
So, out of these two whichever is minimum we have to consider that is the upper cutoff
frequency. So, the similar kind of exercise it can be done for a common source amplifier.
So, let us look into the common source amplifier also.
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So, here again so, we do have stage I common source amplifier and then another
common source amplifier. Architecturally, we have taken they are very similar and we
are cascading it to get a higher gain.
So, basically connecting the output of the first stage to the input of the second stage
through this DC blocking or DC decoupling capacitor C2. And, here what you have
drawn it is the small signal equivalent circuit out of the first CE amplifier. Note that here
we have done the similar kind of exercise namely, converting the transconductance
amplifier in the form of voltage amplifier.
So, we do have Av1 again Av1 it is its expression is ‒ transconductance or transistor gm1 ×
RD1 and here this Ro1 it = RD1, similar to the previous circuit CE amplifier circuit and
here Rin2 it is coming from the two bias resistors in parallel. So, I should say that Rin of
this stage Rin1, it is R11 ⫽ R12.
So, similarly for the second stage we do have a input resistance Rin2 which is R21 ⫽ R22
and its voltage gain Av2. So, this is equal to ‒ gm2 × RD2 ok. So, now again for this case
also the moment we make this connection there will be attenuation; there will be
attenuation because, this resistance and this resistance they are forming a potential
divider kind of circuit.
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So, whatever vgs will be getting to the second transistor it is not just the entire internal
voltage rather will be having one attenuation factor. So, vgs; vgs2 it is . So, this is
the attenuation part multiplied by of whatever the Av1 × vgs1 we are having. And of
course, this vgs it is getting multiplied by Av2 to get the output voltage here.
So, the voltage coming here again if I call this is the final output. So, that becomes the
input voltage multiplied by first stage gain if you want. In fact, input voltage it is same as
vgs1. So, this gives the voltage coming here and then we do have the attenuation factor
× Av2.
So, if I take the if I take the Av1 here in the denominator. So, that gives the gain, so here
again the original gain it was Av and Av2. Av1 and Av2 coming from the two stages and
then in addition to that we do have this attenuation factor. And, similar to the CE
amplifier again here also we do have the upper cutoff frequency it will be getting
modified. So, for upper cutoff frequency the new candidate to define the upper cutoff
frequency it is.
If I call say ωU, the new candidate for the upper cutoff frequency; it is coming due to the
input capacitance here Cin2 and whatever the impedance we do have at this node namely
Ro1 and Rin2.
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So, the expression of this new upper cutoff frequency you are candidate of upper cutoff
frequency. It is Ro1 ⫽ Rin2 multiplied by whatever the Cin2 we do have. And then this Cin2,
it is Cin2 = Cgs of the second stage; Cgs2 and then + Cgd2 (1 + Av2) right.
So, that is the new candidate and of course, we have to consider the original upper cutoff
frequency defined by CL and the output resistance of the second stages by the way this
resistance it is nothing but, this RD2. So, the previous; so, if I consider these two
candidate one is this one another is coming from this one. I have to consider minimum of
the two. So, again to summarize what we have it is in the next slide will be considering
the effect on the gain as I said Av-overall.
So, that is Av1 × Av2 × . So, we do have this attenuation part and as I said that
this Ro1 it is RD for the first stage; and Rin2 this part, it is coming from the bias circuit
namely R21 and R22 in parallel and the upper cutoff frequency so again if we write in; in
the unit of Hz.
So, fU it is minimum of the two candidate one it is coming from the Cin2 and the
resistance there at the cascade cascading node. So, we do have 2π then (Ro1 ⫽ Rin2); ×
Cgs2 + Cgd2 × (1 + Av2).
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So, this is the new candidate and then previous one we are having . Now, next
thing is that how we minimize these two effects namely what may be a solution. So, let
us see what may be the possible solution for that.
If we put a buffer; so if we put a buffer say or say some intermediate circuit having some
important feature we will be discussing that such that, the input resistance of this stage;
call Rin_buff. If it is quite high then whatever the attenuation it will be getting introduced
by Ro1 and Rin_buff.
If that is approximately 1 then we can say that the cascading effect here it is very small
and also at the same time, now if the input capacitance of this stage buffer stage if it is
very small that is also needed to avoid the effect on upper cutoff frequency. So, the basic
requirement here it is this resistance of the buffer stage should be very high, input
capacitance of the buffer stage should be as small as possible. And similar kind of thing
the; the loading effect it is also possible at this node alright.
So, to avoid the loading effect at this node what you are looking for that input resistance
of the second CS amplifier or CE amplifier. We may not be having much control, but
then in case if we say that if we make this resistance as small as possible then the
attenuation factor here it will be less. And, on the other hand if this resistance it is as
small as possible even if we have decent amount of Cgs and Cgd and the input capacitance
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coming from the second stage still it we can say that is the effect can be almost
ignorable.
So, if I if I write the expression of the gain of the overall circuit. So, Av-overall; so, we do
have Av1 × Av2 multiplied by may be the buffered circuit having some gain Abuffer
multiplied by the attenuation factor coming at this node; first cascade node cascade node.
So, that is . So, this is one factor and then the second factor it is coming
from this node; and this factor it is ok.
So, first of all to get rid of the this these two effect of this two factor what we can do we
may say that we are not allowed to change this original Ro1 because, if I try to change
this Ro1 which is coming from the RD1 that may directly that. In fact, that wills effects the
Av1. So, we are not allowed to change here. So, same thing we are not allowed to change
the input resistance here only thing is let us see what is the thing we can do on this
buffers circuit so that we can remove this effects.
So, if you see that if I want to make this part equals to 1. What you have to do it is, we
have to make this; this part Rin_buff should be as high as possible compared to this one.
So, if I make this part it is as high as possible; so we can say this input resistance should
be as high as possible then I can make this part equal to 1. On the other hand, if I see the
second factor if I want to make it approximately 1. So, what I can say that; this part this
part I can make it as small as possible ok. So, if I do it at least in the gain of the entire
cascade; cascade circuit you can say that we are retaining the gain of Av1 Av2 and Abuffer.
Now, this buffer circuit is we do have a special requirement on this impedance namely
we have to make this output resistance as small as possible input resistance should be as
high as possible. So, after assuming that we may not be able to really do get good gain,
but we have to keep in mind that this A buffer should not attenuate the original signal.
Namely, we should be rather happy in case if this part it is approximately 1 ok. So, from
gain point of view that is the requirement.
And then if I see that cutoff frequency point of view if I say that this resistance it is this
resistance say is very high. So, at this node whatever the pole defining the may be the
potential candidate to define the upper cutoff frequency which is . And, since this
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resistance is very high I can ignore that part and then Cin of the buffer it is there. So, to
make this pole in to make this pole very high, so, that the overall upper cutoff frequency
should not get disturbed by this cascading; what you have to do we have to make this
part as small as possible.
So, likewise if I consider this node the cutoff frequency there it is defined by Ro_buffer and
in parallel with Rin2 and then we do have the corresponding Cin of the second stage. So,
here we are already saying that we do require this Ro_buffer should be as small as possible.
So, if this is very small. So, that makes this resistance very small and then corresponding
pole here it will be it will be going to high frequency.
So, if I consider this two new candidate possible new candidate of defining the upper
cutoff frequency if you push both of them beyond whatever the original cutoff frequency
we do have namely and then CL then we should be very happy about that. So, in other
words, if both of these two poles new poles if we push them beyond the original cutoff
frequency; then we can say that is it will be the cascading will not be having effect on the
bandwidth of the circuit. So, in summary the requirement of the buffered it is the
following ok.
This similar thing we can get for C followed by buffer and C. So, I will not be repeating
this part.
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So, you can you can you can do yourself. Now, what we are saying is that what are the
necessities or necessary features of the buffer particularly if the circuit is in voltage mode
what we just now said that, output resistance of this buffer this resistance should be as
small as possible quote and unquote low.
So, on the other hand the input resistance of this buffer should be as high as possible. So,
quote and unquote high and then input capacitance again it should be as small as
possible. So, that the cutoff frequency should not get upper cutoff frequency should not
get affected. So, again here it is quote and unquote low. And, then the voltage gain of
this circuit preferably it should not be very small. So, we should be rather happy if it is in
the order of 1 ok.
Now, this kind of requirement it is essentially it will be obtained by different circuit

configuration namely; common collector if it is implemented by BJT. If it is
implemented by MOS transistor it will be common drain; which means that this buffer
particularly for voltage mode amplifier cascading this buffer it will be implemented by
common collector or common drains stage.
Now, we so far we are talking about voltage mode similar kind of things we may
experience whenever we will be dealing with current mode amplifier. Namely, cascading
current mode amplifier and for that buffer of course, we will be requiring complimentary
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kind of features. So, what kind of circuits and what kind of features are needed, let us see
in the next slide yeah.
So, this is the required buffer for current mode amplifier cascading. What we are looking
for it is that output resistance for this case to avoid the loading effect, output resistance
particularly the resistance wise, it should be as high as possible quote an unquote high.
And, then input resistance it is the dual effect to avoid the loading effect the input current
should be consumed by this circuit without any problem, so, that we can get the signal
propagating there.
So the input resistance it should be quote and unquote low. And then of course, the
current gain we should be happy in case we are not attenuating the signal, it may be in
the order of 1. And such kind of requirements are getting implemented by the third
configuration say for BJT it is common base and if it is MOSFET based then it is
common gate.
So, I should say that current mode buffer it will be implemented by this common base
configuration or and or common gate. I think yeah, so most of the things whatever we
have planned we have covered.
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So, what we have we are going to conclude now it is that the common emitter amplifier
we have seen it is having some limitation particularly whenever we are cascading and the
its not only its gain, but it is not only its gain it is the bandwidth is also getting affected.
So, that can be avoided or minimized by adding appropriates buffer, if you put in
between wherever we are doing the cascading and that improves or rather brings back
the bandwidth and expected a high gain of the cascaded amplifier. You also have talked
about the necessary features of the buffer particularly for voltage mode buffer input
resistance should be as high as possible, input capacitance should be as small as possible,
and output resistance should be as small as possible.
And the complementary things are required for current mode amplifier. In case, if you
have say transconductor or transimpedance amplifier you yourself can now find what
kind of features are necessary for the corresponding buffer. And so this buffer it as I said
that it invites new kind of configuration; it is either you can see that common collector or
common drain stage for voltage mode buffer or common base or common gate for
current mode, current mode buffer.
So, I think in the next class we will be able to discuss more detail about those different
kinds of configuration and we will discuss about how they can be design that is all.
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Prof. Pradip Mandal
Lecture – 44
Common Collector and Common Drain Amplifiers
So, dear students welcome back to our NPTEL online certification course. The course
title it is Analog Electronic Circuit, and now myself Pradip Mandal from E and EC
Department of IIT, Kharagpur. Today’s topic of discussion it is Common Collector and
Common Drain Amplifiers. Based on our overall flow let us see where we stand.
We are in week-5 and we are discussing about the building blocks, specifically we are
going to discuss as I said common collector amplifier and common drain amplifiers. We
will discuss about the basic operation and biasing, and then also we will be discussing
about circuit analysis to find its performance parameter expressions. Design part will be
covering later, so in the next week probably next discussion will be covering that.
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So, the concepts we are going to cover in today’s discussion it is the following. We shall
start with the motivation of going for this new configuration namely common collector
and common drain amplifiers, and then basic operation biasing, and then analysis for
specifically for voltage gain, input and output impedance of those amplifiers and then
input capacitances.
So, let us see what the basic motivation is, rather let we try to recapitulate whatever the
discussion we had in the previous class. Namely, what are the limitations it was there for
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common emitter and common source amplifier specifically when we are cascading say
two stages by connecting output of the one CE amplifier to the input of the next CE
amplifier.
What we have seen here, it is suppose this is the small signal equivalent circuit and then
small signal equivalent circuit of the second stage, and then if you directly connect it
what we have observed that the input resistance and then output resistance of the
previous stage, they were dividing the signal. As a result the signal arriving to the input
of the second amplifier it is not same as whatever the signal we obtained there in
unloaded condition.
And also what we have seen that the input capacitance at this the second stage, it is
affecting the previous stage, namely output resistance of the previous stage and input
capacitance of the second stage they were forming one pole and it was affecting the
upper cutoff frequency. In fact, this is true for common source cascaded with common
source amplifier also.
So, even for common source to common source amplifier. What you have observed that
the output resistance of the first stage and input resistance as well as input capacitance of
the second stage they were affecting the overall performance. So, the affected parameters
are in listed here. Namely, the voltage gain it was getting degraded and also the upper
cutoff frequency of the overall amplifier it was getting and getting limited by input
capacitance and then output resistance defined pole.
So, what is the solution for that? It is we can use a buffer in between these two circuits
and if you have some specific buffer protecting the previous stage of the first stage from
the loading effect coming from the second stage, then we can say that the overall gain of
the system or overall the amplifier performance it remains intact even if you are
cascading it. So, what is this buffer?
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So, the model of the buffer it is given here. So, we can think of it is also a voltage
amplifier. And what are the basic requirements of this voltage amplifier? It is that the
input resistance here it will be it should be as high as possible and on the other hand
input capacitance would be as small as possible. And then the output resistance of the
buffer should be as small as possible. So, if we have this 3 important performance
parameters are getting achieved by some circuit, then we can say that this is working as a
buffer for cascading to amplifier so, whether it is CE-CE or CS-CS.
And this buffer it is to get this buffer what we are looking for it is as we said that the
input resistance to be high, output resistance should be small, then input capacitance
should be small, that is getting obtained from different configuration. If it is BJT based
circuit it is common collector configuration, if it is mass based circuit then it is common
drain configuration. So, that is what the basic motivation of going for this new
configuration.
But while we will be going for these two new configurations, we need to establish that
we are really achieving these requirements namely the input resistance to be high, output
resistance should be small, and then input capacitance should be small. In addition to that
the gain should be should not be say very much less than 1.
In fact, we want this gain should be high, but since we are trying to achieve low output
resistance achieving this voltage gain along with output resistance to be small is not
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really a practical one. So, on the other hand while you are trying to achieve the low
output resistance at least we can say that the buffer should not attenuate the signal. So,
even if the voltage gain it is may be close to 1, we should be happy with that, ok.
So, this is the background of going for this new configuration, and let us sees how and
what are the performances we are getting out of the common collector stage.
So, as I said this is the summary of that. Just know what we said is we are looking for
this buffer circuit particularly for voltage mode amplification, and the important
performance matrices we are looking for it is in summarized here. Namely, the output
resistance should be low, input resistance should be high, and then input capacitance
should be as small as possible, and then voltage attenuation should be low rather we
should say the voltage gain even if you are not getting good gain, but the voltage
attenuation should not be very high.
And that leads to this new configuration or different configuration namely a common
collector and common drain for BJT and MOSFET version of the amplifiers. So, let us
now go to this new configuration common collector configuration, ok.
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So, let me start with the common drain first say. So, here we do have the basic common
drain configuration are listed here. So, we do have the MOSFET here, and at the input
namely at the gate we are feeding the signal, the signal we are giving at the gate along
with a meaningful DC voltage, so that the transistor it is really on and then the signal we
are giving in series with that. So, this is the input signal.
So, on the other hand at the source of the mass transistor we are having a DC bias
current. So, that it consumes the whatever the drain current drain to source current is
flowing at the same time it is ensuring that this node towards the ground it is quote and
unquote open. That means, it is having high impedance looking into the bias circuit.
And the output you are observing at the source; the third terminal namely the drain it is
connected to Vdd, ideally it should be connected to Vdd which is AC ground. So, we can
say that we are feeding the signal at the gate and we are observing the output at the
source and the drain preferably we are connecting to AC ground and hence we call this is
common drain. So, that is why this terminology it is their common drain.
Now, in ideal situation if I say that ideal biasing situation, the drain it is connected to Vdd
and at the source we like to have ideal current source. Namely, its conductance should be
as small as possible. But then if I consider a practical circuit what normally will be
getting it is may be close to that. So, at the source we may not be having ideal current
source, we may be having current source along with a finite conductance connected to
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ground. The drain side on the other hand, so the drain side it need not be connected to
Vdd directly, even if it is connected to through a resistance or some other element
connected here, then also we call it is common drain.
At the gate on the other hand at the gate while you are feeding the signal we are
expecting that there will be a DC voltage. So, either we may provide a meaningful DC
here by using a potential divider and then feed the signal through a AC coupling
capacitor or what we can say that we may say that the previous stage, whatever the
previous amplifier stage it may be feeding the signal along with a meaningful DC
voltage.
Note that if you observe carefully at the gate the current flow current flow of this
transistor it hardly depends on the gate DC voltage. So, even if say this DC voltage may
not be precisely to a target one then also it is it will be fine because the Ids current of the
transistor, it is primarily defined by whatever the current we do have we are sitting there.
So, in case if the gate voltage it is not precisely at our target then the corresponding
source voltage may change and maybe this current may change, but then assuming that
this resistance is relatively high and the whatever the current changes we do have
because of the gate voltage it is not exactly the target one then also it is ok, because even
if the current is slightly different it hardly matters. So, instead of having a potential
divider and fixing the DC voltage at the gate, what we have done for the common source
amplifier, in this case it is very common to directly feed the signal at the gate, ok.
611
So, what we like to say that the previous stage DC voltage, whatever the previous stage
DC voltage may be there that may be good enough along with whatever the signal we do
have. So, that is why whatever the biasing arrangement we do have that is I should say it
is quite practical. So, that is about its operation and its biasing.
So, what we are expecting that at the gate node? If you see at its gate we are having a
voltage, DC voltage, defined by this VG or whatever you say. And then on top of that we
do have a signal riding over that and so this is the gate voltage vg as function of time.
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Now, at the source node if the current is remaining constant then you can say more or
less you can say that this Vgs, Vgs it is quote and unquote remaining constant. So, if I am
having a signal, if I am having a signal at the gate, so it is expected that at the source
node it will try to follow signal wise, it will try to follow the gate voltage.
So, if I observed the source voltage with respect to time and since this current is
constant, this current is constant and that is making this Vgs it is almost constant that is
obtained by maintaining the same signal coming to the source. Note that the gate voltage
and the source voltage amplitude it is quote and unquote equal and they are also in the in
same phase. So, operation wise whatever the voltage you are applying here signal we are
getting almost the same voltage at the source node and so we can say that its voltage gain
approximately equals to 1.
And now we claim that the input resistance of this circuit it is very high and output
resistance it is quite low. In fact, output resistance it is . So, that is what we will we
will derive that, but intuitively you can say that this is the basic operation of the circuit.
At the gate we are feeding the voltage signal. At the source we are observing the
corresponding output and the output it is almost having the same magnitude and having
the same phase.
So, this the voltage gain approximately 1, what we said it is quote and unquote it will be
again it will be approximately remaining 1, even if we put say significant amount of
conductance. Mainly because the output resistance coming from the device here it is
which is expected to be much smaller than this conductance path here.
So, even if you consider practical cases, namely even if you are having a load connected
here or finite conductance coming from the bias circuit still the voltage gain it is
approximately 1. In fact, this is also valid if even if you are having said drain resistance
in between the drain terminal of the transistor and the supply voltage. So, that is the basic
operation. So, similarly let us look into the common collector stage, its basic operation
and how it is getting biased.
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So, here we do have similar to the previous case, here we do have the base node it is
getting the input signal and emitter node, at emitter node we are expecting that the signal
will be sensing.
So, if you see here the again the biasing here it is at the emitter, we are fixing the current
and whatever the voltage you are applying here and the emitter node it is getting self-
adjusted to maintain the same current which means that at the base node if we are
feeding a signal having a meaningful DC and then on top of that if you are having a
signal, so this is the base voltage with respect to time, at the emitter node what we are
expecting that the base to emitter voltage Vbe it is almost constant.
In fact, if this is ideal current source then I should say it is constant, and as a result Vbe if
it is constant then at the emitter we do have a voltage DC voltage, on top of that we do
have the signal.
So, we can say that the emitter voltage and the base voltage they are almost the
difference is remaining constant. So, the signal here and signal here they are same, only
the DC voltage level here and DC voltage level here they are different, they are different
by VBE(on). Now, so this is the basic operation and it is biasing wise at the emitter we are
connecting a we are expecting that will be having a good current source.
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But even if we do not have a good current source, even if we have finite conductance of
this bias circuit or even if you are connecting some load then also it is expected that the
output voltage very close to the input voltage and here also we are expecting that Rout,
Rout to be very close to of the transistor which is low, this is low.
Now, let us go a little detail of this both the circuits, namely a common collector and
common drain using their small signal equivalent circuit to really find whether the input
resistance and output resistance, input capacitance whether they are at part of whatever
our requirement we do have.
615
So, this is the small signal equivalent circuit of the common collector amplifier. So, we
do have the common collector stage here the small signal equivalent circuit of the BJT. It
is given here it is having rπ and then collector current it is gmvbe. vbe voltage it is the
voltage across base to emitter terminal and then at the collector we do have the Vdd
connected which is AC ground. We are also keeping this collector to emitter resistance ro
and at the base we are given the signal, and at the emitter we are observing the output.
Since, this is ideal current source this circuit is open.
Now, to get the input resistance or the voltage gain let us see if we apply KCL at the
emitter node. So, if we apply say KCL at emitter node, so what we are getting here? It is
the current coming through this rπ it is . So, this is the current. So, this is the first
part. And then we do have the voltage dependent current source gmvbe and vbe is vin ‒ vo.
So, this is the gmvbe part, the second part.
And then if this is vo at this node it is vo the current flowing through this resistor it is in
this direction which is . So, summation of this current and then ic together it is giving
the current flowing through this ro.
So, that is what we are getting here from the KCL if you rearrange this circuit and taking
a vo on the left side, what we are getting here it is vo = vin × (gmrπ + 1) ro. In the
denominator we do have (gmrπ + 1)ro + rπ. So, this is the; this is the input and output
616
voltage relationship. From that directly we can get the voltage gain . In fact, that is
what we do have here, voltage gain.
And then in fact, if you further look into this expression gmrπ it is nothing, but β of the
transistor. So, it can be written in the in terms of β. So, in the numerator we do have (β +
1) ro. In the denominator we do have (β + 1) ro + rπ. And typically this term it is much
higher than rπ, so we can approximate this equal to 1.
On the other hand, input resistance, so looking into the base terminal and with respect to
AC ground if I want to know what will be the input resistance. So, that is if I call this is
the input current iin. So, Rin it is and iin it is . So, iin it is .
And here we do have the expression of vo in terms of vin, so if you directly put that
expression of vo here vin s getting cancel and after simplification what we have it is (gmrπ
+ 1)ro + rπ. Again, this can be written in terms of β namely (β + 1)ro + rπ. And as you can
see here this is you can say that rπ coming in series with (1 + β)ro, and since this part is
very high we can say that the input resistance overall input resistance it is very high.
So, the first two properties namely input resistance is very high that we obtain voltage
gain. Of course, voltage gain we are not expecting much, but at least it is the circuit is
not attenuating the signal. So, we do have the voltage gain approximately 1. So, similar
kind of analysis it can be done for common drain. But before that so, let me go for the
common drain circuit in the next slide and then after that we will see the output
resistance.
617
So, this is the common drain circuit and its small signal equivalent circuit is given here
the. So, this part is the small signal equivalent circuit of the MOS transistor. Signal we
are given here vin at the gate, so we do have the vgs here, gmvgs is the current flow from
drain to source.
So, this is the source terminal, this is the gate terminal, this is the drain which is AC
ground and in this case again if we apply KCL at the source node, KCL at source node so
what we have of course this side, we do not have any current flow we do have this
current is flowing here and the voltage here it is vo. So, we can directly say that this
current equal to this current who is or we may say that this current is flowing through
this one developing this vo voltage. So, vo it will be (gmvgs × whatever rds) we do have.
So, that is what either we can say it is KCL or if you analyze this loop and find the
expression of vo that gives us this vo in terms of vgs. And then vgs is vin ‒ vo. So, from this
relationship we can rearrange the equation and we can get the expression of vo in terms
of vin which is vo = vin ( ).
Now, from this one we can directly get the voltage gain. So, , it is given here. Even
for this case also this part it is much higher than 1, as a result this is approximately 1.
And note that the input resistance since this gate to source input impedance is infinite.
So, we can say that because of the property of the MOS and this Rin any way it is very
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high. So, that is what we are getting two important characteristic. This Rin it is anyway it
is high, it is high for even say common source amplifier also, but this is what it is
important that voltage gain at least it is not very different from 1.
Now, let us see the output resistance. So, for output resistance what we have it is again
the small signal equivalent circuit of the common source and common drain amplifier.
So, this one is the common drain, small signal equivalent circuit of common drain and
common source circuit model it is given here. So, to get the output resistance of this
circuit, of course, the output terminal is the source 1. And so we have to make the signal
at the gate to be 0, so at the gate we are applying 0 signal which means this is AC
ground.
Drain anyway it is AC ground. And to get the output resistance, what we do? We
stimulate this source by say signal source of vx and let me observe the corresponding
current ix and if this if you take the ratio of vx and ix that supposed to be giving us the
output resistance. So, that is why this RO = .
Now, how do you get this ratio? If you see here whenever we do have this ix and this
current is basically gmvgs with a ‒ sign and also this current which is actually this is .
So, on the other hand if gate voltage it is 0 source is vx, so we can directly say that vx, vgs
= (0 ‒ vx). So, vgs we can say that it is ‒ vx. So, from that we can say the ix = . So, that
619
is this current and then we do have gmvgs in this polarity, but we do have a ‒ sign, so we
can say that this current it is same as gmvx.
Now, if we rearrange this equation what we can get is ratio of that is . So, that
is the output resistance. In fact, you can further simplify this is we can say that this is
. And this is you can see it is a normal approximation is . So, the output
resistance it is which is quite low.
Now, similar kind of analysis can be done for the common collector amplifier also to get
the output resistance. So, in this case again vbe it is same as ‒ vx, where vx is the voltage
stimulus at the emitter terminal. So, this is emitter terminal, this is base terminal and then
this is drain. So, vbe it is (0 ‒ vx). So, vbe = ‒ vx and if you see here this ix, ix it is having 3
compound.
Student: (Refer Time: 36:11).
So, what you are talking about is that common collector analysis. So, we do have at the
base we do have ground connected, AC ground. At the emitter we are having the
stimulus vx and we are observing the current flowing through the emitter terminal. At the
base we are having 0 and at the emitter we do have vx. So, we can say that vbe = ‒ vx.
Now, we like to get the expression of this current ix and ix it is having 3 components, one
is the current flowing through this rπ which is the voltage here and then this current
which is , so this is the second part. And then the third part it is gmvbe and its direction
it is in this direction and vbe = ‒ vx.
So, we can say that this current it is gmvx in the other direction. So, we can say that ix it is
summation of all these 3 current components. So, we can say that ix = gmvx, then + .
So, from that we can say that the , it is . So, that is nothing but the output
resistance.
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So, this again this can be well approximated by this gm terms which is a dominant term
and we can say that this is equals to . So, for both the cases the output resistance it is
and it is quite low. So, we can say summarize that this is low resistance.
Now, coming to the input capacitance. So, we already got the expression of the voltage
gain and its magnitude is very close to 1. So, let we use that information and let we draw
the small signal equivalent circuit now we are including the parasitic components namely
the Cgs and Cgd for the common drain, likewise for common collector Cπ and Cµ we are
including. So, let us see the common drain amplifier and let us try to see what is the
input capacitance will be getting for this circuit.
So, input capacitance if we see at this node, Cgd it is other end of this Cgd is connected to
AC ground, so the Cgd it is contributing to this Cin as the and On the other hand, Cgs it is
breezing the input and output of this circuit and we know that its voltage gain it is
approximately 1. So, if I say that voltage gain it is Av then through Millers theorem we
can say contribution of the Cgs to input capacitance is Cgs(1 ‒ the voltage gain).
And if we put the expression of this voltage gain in terms of gm and rds which is given
here, then we do have 1 ‒ . So, this part it becomes . So, the contribution
of the Cgs it is essentially Cgs divided by this part. And then of course, Cgd it is appearing
as is and we can approximate this by Cgd.
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So, unlike common source amplifier, where the input capacitance it was quite big, in
fact, Cgd it was getting multiplied by Millers factor and the gain it was quite high. In this
case we do have the input capacitance it is only Cgd which is very small
So, similarly if I consider common collector amplifier. So, here also the input
capacitance looking into the circuit it is having two components, one it is coming from
Cµ, another part it is coming from Cπ. And its expression, it is Cµ + Cπ (1 ‒ voltage gain)
and this voltage gain expression of the voltage gain earlier we have seen.
So, if we put its expression and then this part it becomes ( )

. And this part it is
very small, so this part it is very small. So, again in this case also we can say that Cin, it
is approximately Cµ. So, that basically says that whatever the in the characteristic we are
looking out of the voltage mode buffer that is directly coming from common collector
and common drain circuits.
Now, in case if we have some more realistic circuit, namely in case the bias circuit it is
having the conductance or maybe some load it is connected, so to represent that we are
adding this RL. So, we can say that this circuit it is common collector stage, but it is more
realistic. Then what is its consequence on the input resistance, and then input capacitance
and then voltage gain let us try to see that.
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So, if you see here the small signal equivalents circuit earlier this part it was open, now
we do have RL. And if you see this RL its connection, RL it is connected from this emitter
terminal to the AC ground. In fact, this RL it is coming in parallel with ro. So, whatever
the previous derivation we already have, wherever we do have ro we can replace this ro
by this RL ⫽ ro. So, that is what we are saying here. If you see the input resistance
expression earlier it was ( ) . Now, in presence of this RL instead of only
having ro I do have ro + RL coming in parallel.
So, even though this RL it is coming in parallel with ro, but this part it is quite high. In
fact, this part is β, so we can say that this = (β + 1) (ro ⫽ RL) + rπ. So, as long as this RL it
is really not very small, even if say RL it is in the order of kΩ since we are multiplying
with β, so that gives fairly 100s of kΩ. So, again even in presence of this RL we can say
that this input resistance is quote and unquote high.
Likewise, if you see the voltage gain whatever the previous expression we had where ro
was there, instead of using only ro now we can replace that by (ro ⫽ RL) and this is the
corresponding expression. And even in this case since this part it is dominating over rπ
because we do have gmrπ getting multiplied with this, so this is again it is approximately
1.
So, likewise if you see the input capacitance the input contribution of the input capacitor
and it is coming from Cµ, and this Cµ it is appearing as is. And then we do have the Cπ
here and its contribution here it is Cπ × (rpi divided by this big resistance) again this can
be well approximated by Cµ. So, even if you consider this practical value of this RL the
input capacitance it is remaining low.
In fact, similar kind of analysis you can do for the common source amplifier also. And
there also you will be converging to the similar conclusion, namely the voltage gain
remains approximately 1, input resistance anyway it is high and input capacitance for
that case with if I consider Cgs and Cgd in place of Cπ and Cµ, so this will be equals to Cgd
for common drain, ok. So, I think this analysis is helping to establish that common
source, sorry common collector and common drain amplifier really working as buffer for
voltage mode amplification.
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So, this is the conclusion of today’s discussion. What we have seen in our discussion that
common collector and common drain amplifier they are really working as a buffer in
voltage mode amplification.
So, we have discussed about the basic operation, namely where to fit the input signal and
where to observe the corresponding output, and then also some biasing basically the
source or emitter terminal, we need to put a quote and unquote current source. And then
we have done detailed analysis using small signal equivalent circuit to verify that the
voltage gain it is remaining close to 1.
Input impedance it is remaining high, output impedance it is low and then input
capacitance it is quite low. So, these are the important analysis. It is helping us to
establish that it is really that common collector and common drain can be used as buffer
for voltage mode amplification.
Related to this common collector and common drain we need to cover numerical
examples and designs that it will be done in the next class. I think that is all.
Thank you.
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Prof. Pradip Mandal
Lecture – 45
Common Collector and Common Drain Amplifiers (Contd): Analysis (Part A)
Dear students, welcome back to our online NPTEL certification course. The topic of this
course is Analog Electronic Circuit. Myself, Pradeep Mandal from E and ECE
department of IIT Kharagpur. Today’s topic of discussion it is Common Collector and
Common Drain Amplifiers, rather I should say it is continuation of this topic. Previous
day we have discussed about relatively idealistic bias situation and today we are going to
a little detail considering some practical circuit components also.
So, what we have to cover today, as I said we have discussed the motivation part of the
common source and sorry common collector and common drain amplifier, basic
operation and biasing also it is done. And we are going to go a little detail of analysis of
voltage gain and impedance, input capacitance, considering realistic biasing and their
associated components.
In fact, in the previous class we have discussed about the analysis of the circuit for
voltage gain, impedance and input capacitance ignoring these components, and today we
are going to see that what will be there you know consequences if we consider on a
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practical components. So, let us start with the common collector amplifier, considering
the RL, and then we will be moving to the next one is considering the source resistance
RS, and then we will go for the collector terminal resistance.
So, to start with let we let you consider the common collector amplifier and also in the
common collector amplifier we are including this RL. So, this RL may be coming from
the bias circuit, representing the finite conductance of the bias circuit or maybe and or
maybe additional load resistance we are connecting at the output node with respect to
ground.
So, whatever it is let you consider this RL in our analysis and here we do have small
signal equivalent circuit of the common collector amplifier having this RL included. So,
we do have rπ here and then gmvbe, ro coming from the MOS at the BJT transistor, and
then we do have this RL bias circuit it is then the IBIAS part it is 0 in this small signal
equivalent circuit. So, likewise the DC part also it is 0, we do have only the signal
coming to the base terminal. So, we do have base terminal here, and then we do have the
emitter terminal here and then we do have the collector terminal. And this is the output
port, so the output voltage it is vo and the emitter with respect to ground.
Now, in our previous analysis where we have excluded this RL there we have seen the
expression of the input capacitance. Basically, the input capacitance at the base with
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respect to the AC ground. And there what we have seen if you consider the two parasitic
components capacitive components one is Cµ and then we do have the Cπ here.
So, what is the contributions Cµ the right side of Cµ it is connected to ground. So, it is
directly contributing to the input capacitance as is, as you have discussed before. On the
other hand, this Cπ it is making a connection from input to output of this amplifier. And
the gain of this circuit we have discussed if you see here in fact, if we recall Cin it is
having two parts; one is Cπ(1 ‒ voltage gain of this amplifier) + Cµ, and this voltage gain
to get the expression of this one we need to get the voltage gain.
So, in our previous analysis we obtain the voltage gain where RL it was very high.
Now, if we consider this RL what you are getting this RL ⫽ ro. So, whatever the previous
expression we are having namely ( ) , and in the denominator it was (
) .
Now, if we have this RL which is essentially coming in parallel with ro then whatever the
derivation we have done before that can be as well utilized just by replacing this ro by ro
and RL in parallel. So, wherever we do have ro in our previous derivation if you replace
that by ro ⫽ RL, then we do get the corresponding voltage gain.
So, if you put this expression of this voltage gain here, so this is Av. So, if you put that
voltage gain expression here, what we will be getting here it is Cin it is having Cµ and
then Cπ part it is having a factor which is a having in the numerator we do have rπ and in
the denominator we do have ( ), then ro and RL in parallel + this rπ. So, that is the
expression of Cin.
Likewise, when you consider the input capacitance if you see the expression or if you
recall the previous expression of the input resistance without considering this RL, what
we had it is Rin it was ( ) .
Now, in presence of this RL what you have to do? Again, instead of ro here we need to
replace this by ro ⫽ RL. So, the expression of the input resistance we do have it is
( )( ⫽ ) . So, that is how when you consider this RL in our circuit. What
we are getting it is this additional you know modification and that is that is good enough
to get its effect.
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In fact, you can further simplify this one wherever we do have the you may replace
this by β of the transistor. So, here also we can write this is ( )( ⫽ ) . So,
likewise here also you can write this part you can write ( ) into this one. So,
similarly for the voltage gain here you can write in terms of β instead of gm and rπ, so we
( )( ⫽ )
can say that this is .
( )( ⫽ )
So, whatever it is all practical purposes, for all practical purposes even if you consider
the this RL you can well approximate that this part after multiplying with ( ), it will
be very high and you may say that this part it is almost 0 compared to Cµ. So, as a result
you may say that Cin it is practical it is Cµ.
Likewise, when you consider the input resistance it is we do have rπ coming in series
with β (ro ⫽ RL). So, though ro or ro ⫽ RL, but even though if I consider the effect of RL
since we do have ( ) it is coming in the multiplication again this may be you may
consider this is very high. So, we may say that this is going to be a very high compared
to other resistances in the circuit. So, likewise when you consider the voltage gain even if
I consider the effect of RL this is this can be well approximated by close to 1.
So, the bottom line is at even if I consider RL the main property of the input resistance to
be high, voltage gain it is close to 1, input capacitance is very small defined by Cµ, those
things are getting retained. Also the other parameter we have to think of is that the output
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resistance. So, if you see this circuit and at this point if you see what is the output
resistance, it is basically the output resistance coming from the rest of the circuit coming
in parallel with RL.
So, that is I guess it is very straight forward to converge. So, I do have, yes. We do have
this is the expression of Ro. The derivation of the Cin, Rin and voltage gain we already
have done, so these things are already done. Now, in addition to that if you want to know
what will be the output resistance is basically this resistance coming in parallel with
whatever the resistance we do have in this circuit.
And again, if we refer back to our previous analysis without considering this RL, where
to get the output resistance what you have done is that we made this is AC ground and
then we stimulate this circuit by say vx, and then we observed the corresponding current
say ix, and then if you say what is the; so, this is ix then if I take the ratio of that is
supposed to be giving us the output resistance.
And earlier whatever the discussion we had you may recall, that if I apply vx here the
current flow here it is , current flow here it is gmvx because the vbe = ‒ vx, and then
current flow here it is since this is AC ground, so this is 0, vin is 0. So, this current it is
again . So, likewise the current flowing through this circuit it is .
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So, the total current ix it is actually summation of all these four currents. And so if you if
you simplify that what will be getting is that output resistance is reciprocal of the total
conductance; total conductance coming from all these four elements, one is gm part,
another one is , then another one is here and then . So, the total resistance again it
is its expression is given here, but all practical purposes, even if I consider practical
value of RL this gm it dominates over rest of the things, so you may approximate this =
. So, this is as I said that basic property we are looking out of this common collector
which is buffer voltage buffer it should be low, so that is what here also we are obtaining
the same thing.
Now, that is about the common collector amplifier if you consider its counterpart mass
counterpart namely the common drain stage and then if you consider this RL for that,
what you will be getting it is similar kind of things we can get only difference is that this
rπ, it will be it will not be there. So, you may say that because this rπ is theoretical, it is in
finite for common drain amplifier. So, this input resistance for common drain stage any
way it is high. So, we may ignore this part. Rest of the parameters namely Cin voltage
gain and then output resistance we can think of. And everywhere again we can converge
to the same conclusion.
So, let us see what I do have for you, yeah.
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So, the common drain stage considering RL and its voltage gain, voltage gain it is given
here. So, again you may recall the previous analysis where we have not considered RL,
for that the voltage gain it was .
Now, in presence of this RL this RL it is coming in parallel with rds. So, you may say that
wherever we do have the rds, we can we can replace this rds by rds ⫽ RL and that gives us
the corresponding voltage gain. So, likewise if I use this expression to find the input
capacitance and its expression it is Cgs(1 ‒ voltage gain) + Cgd, where Cgs it is the
capacitance from gate to source.
So, we do have Cgs here, and then likewise we do have the Cgd gate to drain and so this is
Cgd. So, the expression of the input capacitance is Cgs(1 ‒ Av) + Cgd, so that gives us if I
use the expression of the Av here, what we are getting is that Cgs it is getting divided by a
big factor here and as a result you may approximate again this by Cgd.
So, note that even if I consider the effect of RL since this part it is much higher than 1, its
effect it is very negligible and as a result the effect of Cgs it is very small. So, in fact, it is
also very clear that if the voltage gain it is approximately one then this part it becomes
approximately 0 or very small. So, we do have only Cgd left behind for the Cin. And again
for the output resistance if I consider this RL in addition to the other components what we
have it is; so, let me use different color, yeah.
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So, if I want to know what will be the output resistance, let me use red color, yeah. So,
we have to make it this is ground and then we need to stimulate this circuit by say vx and
then current flowing through this is ix and the moment we are applying say vx here the
current flowing through this rds it is and then vx incidentally it is same as ‒ vgs.
So, as a result the current flow through this active device it is gmvx because vgs = ‒ vx. So,
this ‒ sign it is suggesting that the direction of the current it will be from source to drain
and gmvx. So, here of course, we do not have any conducting path and then the current
flowing through this RL it is .
So, we do have these 3 components. And what gives us this ix = + + gmvx. Now,
from this one we can directly say that the = reciprocal of these total conductance.
Again, even if I consider the effect of RL for all practical purposes we can say that gm it
dominates, as a result here also we can say that the output resistance is approximately ,
which is you may say that low cut and uncut low, input capacitance is low and the
voltage gain it is approximately 1, right. And of course, the Rin it remains ∞. So, this
summary is that even if I consider RL the basic property of the buffer it is getting
maintained.
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Now, so far we have discussed about the effect of RL and so likewise we may think of
the resistance at this terminal resistance at this terminal considering some practical
purposes.
Now, if I consider say source resistance and still if I consider this is 0 then even if I
connect the source resistance Rs, since from this terminal to this terminal, there is no DC
path. So, you may say that even if I consider Rs the behavior of the circuit remains
unchanged. So, for common drain stage we need not to consider this case because we
know that whether we consider Rs or naught or it is impact it is not there.
However, if I consider say common collector stage; obviously, there will be the
corresponding element here called rπ. So, it is better to in case if we consider Rs, then we
need to; need to analyze its effect particularly for common collector stage.
So, let us see the common collector amplifier considering this source resistance, signal
source resistance. So, we do have the circuit given here. So, we are considering this
source resistance Rs. Again, RL we are ignoring, so we are considering one effect at a
time. And then the small signal model of this circuit is given here and of course, we
should have considered the signal here. Now, this supposed to be the output vo. Now,
what are the parameters we need to consider, the voltage gain? Input resistance, then
output resistance, and then Cin.
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Now, if you see that if I consider this Rs the behavior of the circuit from here to the
output from the base terminal to the emitter terminal, the behavior remains the same. In
fact, if you see the input resistance of this part and if I call this is the input resistance that
remains the same as what we have discussed before. So, we are not going to consider the
analysis for again repeating this Rin. Same thing for Cin also.
So, whatever the c in we do have, so c in also remains unchanged from base terminal to
the emitter terminal. Even if I consider Rs and the voltage gain if you see of course, if I
consider this is the primary input and this is a corresponding primary output, and if I say
the voltage gain from again from base to collector, the emitter terminal gain remains the
same namely close to 1, only difference is that if I consider Rs, I do have vin here and
then we are applying the signal through this source resistance Rs to the effective input
resistance, whatever the effective input resistance we do have.
Now, to consider the effect of this Rs in the in the voltage gain we need to consider what
is the potential division it is happening before it before the signal arrives to it is a base
terminal. So, what is the additional factor we will be getting in the voltage gain? It is
. So, this is the additional factor. So, if I multiply this with vin that gives us the
base voltage, and then from the base point to the corresponding collector point the gain it
is approximately 1.
Now, if you see here most of the time this Rin as I said Rin is very high. So, this factor
whole factor it is approximately 1. So, I should say that the voltage gain Av which is in
this case multiplied by whatever the previous voltage gain we is having. Namely,
if you recall it was . So, it was it was I should say rather this portion it was
approximately 1, and this is also getting approximately 1, as a result overall it is also

becoming approximately 1.
So, again we are not going to discuss about the output similar to output input resistance,
we are not going to discuss about the voltage gain. Only thing we are going to discuss
here it is the output resistance.
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So, let us see what is the output resistance of the common collector amplifier will be
getting in presence of this source resistance Rs. Now, to get the source resistance sorry
the output resistance of this circuit, what you have to do? We need to stimulate the
circuit by say vx and we need to observe the corresponding current here ix. So, before we
go into the ix expression, we need to make the voltage, the signal here it is 0, so that is
why you are making this is a c ground and if we apply vx here, the voltage coming at the
base to emitter terminal, so between base to emitter terminal what we have it is vbe that is
it is essentially the potential division of this vx appearing across this rπ.
So, we can say that the voltage appearing across rpi it is vx × , but then this side we
for vbe we call this is +ve and this is ‒ve and vx we are applying here it is +ve and this is
‒ve So, as a result the expression of the vbe in this case it is ‒ vx × . So, this is one
relationship we obtained between vbe and vx. Now, the current flow through this active
device is gmvbe, so that becomes gmvbe, instead of vbe we can write ‒ vx into so and so on.
So, we may say that the current actually it is; so, this starts flowing in this direction and
its expression is this one. So, this current expression is given here. On the other hand, the
current flowing through this io , ro, it is vx whatever the voltage you are applying here
divided by ro and the current flowing through the base terminal towards the base, namely
this current it is . So, this is what we are getting. So, the total ix current we can
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write in terms of vx. So, from this one we can get the ratio of and that gives us the
output resistance. So, which is reciprocal of the conductance of the 3 parts and the first
part conductance it is gm × , second one is , third one it is .
So, in this case again depending on the value of this Rs we may consider say this Rs with
respect to rπ, but most important thing is that we do have gmrπ getting multiplied. So,
now, we can directly see that compared to this term this term it is dominating, and same
the similar kind of conclusion we can make because this ro it is reasonably high, as a
result you can say that this term it is dominating. So, the resistance you may say
that .
Now, if I say that Rs is varying, Rs is maybe comparable with rπ then it remains low, but
if say Rs is very high if it is very high then of course, we may not be able to approximate
this by . So, depending on the relative value of this Rs and rπ, we can get the
corresponding output resistance. But again even if the Rs it is in the order of same as rπ
then also you can say that this is in the order of . So, in case say Rs = rπ, then this may
be that that gives you some idea that what may be the effect of this Rs on the output
resistance.
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So, this is the effect coming from the Rs. So, likewise if I consider, yeah. So, so far we
have considered the Rs, earlier we have considered the effect of RL and then other part is
also possible depending on the circuit connection. It may not be intentional, but there
may be some practical situation due to which there may be resistance coming in the
collector terminal, in between the collector terminal and the Vdd.
So, let us consider the effect of this resistance call Rc on different parameters of the
common collector amplifier.
So, what we have it is, yeah. So, here we do have the circuit the corresponding circuit,
we do have the common collector circuit having this Rc connected to Vdd. Note that,
please do not get confused that output still remains, the output terminal is basically the
emitter of the transistor even though we do have a meaning maybe some signal coming
to the collector terminal, but we may not be really concerned about this signal unless
otherwise it is stated.
So, our input and output terminal remains base and emitter respectively. And even
though we do have Rc connected here still we call this is common collector amplifier.
We may say that collector is having some resistance, but still we call it is common
collector without any you know confusion.
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And here we do have the small signal equivalent circuit and if you see the small signal
equivalent circuit we are adding this Rs. And then, if you see this circuit we can go step
by step and we can you can find what will be the impact of this Rc on different
parameters namely voltage gain, then output resistance, and then input capacitance and
so and so.
So, let me take a small break and then we will come back to discuss all those things,
namely we will start with voltage gain.
Thank you.
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Prof. Pradip Mandal
Lecture – 46
Common Collector and Common Drain Amplifiers (Contd.): Analysis (Part B)
Yeah, welcome back after the short break and we are discussing about the Common
Collector Amplifier, considering the; considering the resistance Rc connected in the
collector terminal in between collector and supply voltage Vdd. So, let us see the circuit,
which is the small signal equivalent circuit given here. The input voltage vin, we are
applying at the base and then, we do have the collector terminal which is not AC ground
rather it may be having a signal called say vc. So, this is very important change compared
to our previous analysis. So, we do have non-zero value of vc and then, a rest of the
things are same namely at the emitter we are observing the collector sorry, the output
current output voltage vo.
So, the vbe; vbe it is vin ‒ vo as you have discussed before and but then vc if you see once
we have this output terminal is open, whatever the current it is flowing here, base current
that is flowing through this circuit and finally, it is going to the ground here. Because this
current need to come back to the source through the ground.
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So, we can say that the current flow after reaching to the emitter whether it is branching
to the active device or through this ro; finally, they are converging to the ground and we
can say that this is also same as the base current ib. So, if I call this is ib, this is also base
current. So, if ib is flowing through this Rc, the voltage getting developed here it is we
call vc. So, we can say that vc at this point with respect to ground is Rc × ib. On the other
hand, ib is . So, what we can say that this vc = Rc × ib and ib, it is .
So, this is what the important thing and that directly affects the current flow through this
ro. So, now, if I apply KCL at the emitter node, what we are getting? Here, it is current
flowing through this this ro which is . So, that is equal to the summation of the two
currents; one is the base current and other is the through the active device. So, the base
current is and the current flowing through this voltage dependent current source,
it is gmvbe rather ‒ vbe going from going from yeah, it is basically coming here yeah vbe.
So, we do have .
So, summation of this current and this current, it is equal to this current so that is what
we have written here. Now, this expression of this vc, it is in terms of vin and vo. So, this
equation, it can be utilized to replace this vc as a result we can get an expression which
involves only vo and vin. Now, if we rearrange that equation, what we will be getting is vo
( ) = vin ( ).
So, from this relationship, between vo and vin that gives us the voltage gain. In fact, we
can say that vo = vin ( ). In fact, if you see here this part it is common
here and here. So, effectively you may say that the relationship between vin and vo if I
say, it is the impedance here which is rπ and the impedance of rest of the circuit there.
Before we connect anything here whatever the impedance, we are having it is (

). So, this part is essentially the impedance at this point, before we connect
anything of course, here. So, whatever it is in this case again this part, it is typically
dominates and so, we can see compared to rπ, definitely this is higher because we do
have . So, we can say that this part you can ignore and this can be well
approximated by 1.
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So, the voltage gain even if we have say Rc getting connected here and if we have say the
vc voltage, it is allowed to develop then also the voltage gain it is close to 1. Now, let us
see what will happen for the other parameters namely the output resistance and then,
input capacitance and so and so and input resistance right. So, we do have let us move to
the next slide to do that.
So, let us concentrate on the input resistance and here, we do have the same small signal
equivalent circuit and for input resistance, what we have it is if we are applying vin here
whatever the iin it is flowing. If I get the expression of iin in terms of vin that gives us the
corresponding input resistance. So, Rin it is ; whereas, iin, it is the base terminal current
and base terminal current is . So, the expression of iin it is . Now, probably
you can rearrange this equation namely, we can write in this form .
So, expression of this which is the voltage gain, we already have seen and that is
essentially this part. So, if I make (1 ‒ this part), what will be getting here in the
denominator it is rπ. It will be getting here and then, below of that will be having this
whole thing. So, I should say this whole factor , it is becoming divided by the
whole thing here and this and this is getting cancel, we can take this is in the
numerator.
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So, as a result input resistance what we can get it is this only. So, here we are just
summarizing that. Input resistance is in series with Rc in series with ro and then, the
active device contribution. Again, because we do have this term coming in series, even
though we do have this Rc this is also going to be very high. So, we can consider this is
very high. It is quite obvious that since we are considering this resistance in series, it is
increasing the overall resistance, only by this part and this part earlier, we obtained that
whatever the input impedance we are having.
So, the effect of non-zero value of this Rc, it is increasing this resistance even higher. So,
anyway that is in our favour considering the required input port characteristic. So, we
have seen the voltage gain, we have seen the input resistance. Now, let us see the other
parameter in the next slide.
So, if you see the output resistance. So, we do have the same small signal model and to
know the output resistance, we have to make the signal = 0 namely base terminal we are
making it AC ground. We are stimulating the circuit with vx and we are observing the
corresponding current flowing through the circuit. So, what we have here it is this ix, it is
summation of all these currents. So, the current flowing through the device here
whatever voltage dependent current source, it is gmvbe and incidentally vbe = ‒ vx. So, we
can say that this current is gmvx and then, we also have the current flowing through this
device and that device, it is we do have say vx, ‒ whatever the current flow we do have.
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Now, for simplicity what we have done is that since we are stimulating this terminal by
vx directly, instead of considering this entire circuit and try to find what will be the
impedance. We may split this part; one is this part and then, rest of the things. Now, if
I get the impedance of this rest of these things, then the total output impedance it will be
simply this output resistance coming from the insertive one in parallel with .
So, let us do this exercise considering only the insertive part. So, if we say that the
current flowing through this this vx without considering this one it is ix, then this current
flow actually it is same through this Rc. So, the current flow through this Rc it is ix. So,
the voltage here vc, it is Rc × ix. So, the current flow through this ro it is vx here ‒ and
vc it is Rc × ix.
So, that it is a small you know small trick by which we can we can simplify the analysis.
If you want you can consider the entire circuit and you can find the output resistance. But
if you do this one, it will be the analysis it will be simpler. Now, what we obtain here, it
is the relationship between ix and vx and from that we can get the ratio of that gives us
( ).
So, interestingly, the resistance coming from this circuit, it is again it will be quite small.
This part it may be dominating. So, we may approximate this by ( ). In later of
our discussion, in other circuits, we may come across the similar kind of circuit and try
to remember this sorry this party you may ignore; try to remember this outcome of this
analysis.
So, there based on the value of this Rc and then, ro it may be in the order of that may
be the conclusion. Now, since we do have the rπ here, the total resistance, output
resistance; it is the resistance coming from this encircle part and then, rπ part. So, this is
again you may consider this is rπ ⫽ ( ) and if I say that this is this may be
dominating over this Rc. Then, you may approximate this by rπ ⫽ which is again it can
be said that it is dominating over rπ.
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So, the conclusion is that this output resistance in the order of which is quote and
unquote load ok. So, let us see the effect of this Rc on the input capacitance that is very
tricky. So, in the next slide, we will be analysing the circuit to get the input capacitance.
Yes. So, things are getting really getting complicated, let us see what are the
complications are getting here. So, we do have the small signal equivalent circuit, we do
have the Cµ and then, Cπ and note that compared to our previous discussion, the voltage
here it is not AC ground rather voltage it is vc and vc, it is of course, it is function of
input voltage.
Now, we may recall that the voltage at the output node vo, we already have this
expression of this vo in terms of vin having this factor. So, numerator it is smaller than the
denominator by this rπ and then, the expression of the of the vc, it is the Rc multiplied by
whatever the current is flowing and that is that we have discussed before.
This can be rearranged in this form. We can take vin outside. We are getting a factor
. So, if I use the expression of vo in terms of vin and if I plug in that expression
here for , what I will be getting here? It is this factor in the numerator, I will be having
this part ‒ this part and will be having rπ in the numerator and in the denominator
whatever the things we do have here, it will be coming there. And the numerator this rπ it
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is getting cancelled here. So, what we have it is in the numerator, we do have Rc and then
vin and then, rest of the things in the denominator.
So, the expression of the vc, it is vin in terms of vin it is vin( ). So,
anyway this is as expected; this is smaller than the input voltage. Note that we are not
connecting any resistance here, the moment we connect the resistance here, the voltage
here at the collector terminal it is expected to be having much higher value. But right
now, we are not considering. If I consider RL is ∞ here, earlier we consider RL.
So, if I consider that this gives an indication that vc, it is a fraction of the vin. In fact,
intuitively we can see that if this side is open and if I start from the base terminal and
then, if you go to the emitter terminal, then if you go to the collector and then if you go
to the ground, what we can see here it is we are seeing one resistance rπ; here, we do
have one resistance Rc and also we do have this resistance ro(1 + gmrπ), that can be
expanded in this form.
So, from here to here that is the impedance and then the drop across this Rc is the vc. So,
you may say that vin it is getting potentially divided by this factor. So, that makes sense
this expression of this one makes sense. So, whatever it is over the both Cπ and Cµ are
getting miller affected. So, both Cµ other terminal of the Cµ, it is a non AC ground. And
of course, Cπ, it is also the other end, it is connected to vo that is also non ac ground right
they are having signals.
So, the input capacitance at the base terminal, what will be getting it is Cπ (1 ‒ gain from
base to emitter and let you call this is gain it is AvE and this AvE), it is . On the other
hand, contribution of the Cµ, it is Cµ(1 ‒ AvC) and what is AvC? We are defining this
and we already have the expression of these two ratios; one it is from here; another it is
from here. So, if you plug in those expressions and if we subtract from one, the first part
if you see, what will be getting in here? It is the denominator and if I compare
denominator and numerator, we do have only rπ is the difference. So, in the first part,
what we will be getting is that Cπ getting multiplied by rπ divided by the entire thing.
So, likewise when you consider the contribution of the Cµ and if I take this ratio getting
subtracted from 1, what will be getting? Here, it is except Rc which is here rest of the
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things it will be there. So, that is why this Cµ, it is getting multiplied by this part which is
having Rc, then ro, gmrpiro and then, denominator it is same as this one. So, you may say
that this part this factor, this factor it is approximately 1; whereas, this part it is very
small. So, approximately 0. So, we can say that the Cin ≈ Cµ for all practical purposes.
So, again, we are converging to the similar kind of conclusion, namely the input
capacitance is low, input resistance of this circuit it is high; output resistance, it is
remaining low, voltage gain it is approximately remaining 1. So, we have done this
analysis for a common collector circuit considering this collector resistance.
Similar kind of things we can do for the MOS counterpart and there instead of Rc, we
may say that we may be connecting RD at the drain terminal and this may be the
corresponding MOS transistor and we can do the similar analysis and in the small signal
equivalent circuit, it will be very similar except this corresponding rπ will not be there or
whatever the analysis so far we have done, that can be utilized judiciously by considering
this rπ approaching to very high value ok.
So, this is what you can share the analysis across different types of the circuit
configuration rather different types of circuit namely analysis from common collector,
you can propagate to common drain. Note that it is not possible the other way because in
common drain circuit. We do not consider this gate to source resistance. So, as a result
deriving the expression, it will be for the common collector from the common drain, it is
not possible.
I should say rather analysis for common collector, it is relatively generic that can be
extended for the common drain circuit. So, as I said that let us look into the common
drain amplifier considering the resistance connected to the drain terminal.
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So, we do have this resistance connected to the drain terminal and then, we do have the
RD coming in the small signal equivalent circuit and then, we do not have any rπ here. So,
rather if I say that whatever the previous analysis we have done, if I consider the rπ in
those equations approximately going to be very high. Then, we can get the equation for
the common drain. So, let us start with the voltage gain and let us follow that approach
for common. So, this is the equation, we obtain for common collector circuit and let us
try to do for the common drain circuit, namely this circuit.
So, if I say that expression of the vo can be obtained by considering this equation which
you already have derived and that can be done by making this is going to be very high
and this is going to be very high and this is also going to be very high. Namely, in the
numerator if I keep this term and in the denominator if I keep this term and this term and
then, if I pull out this rπ and if I cancel it what will be getting here it is vin × gmro in the
numerator and in the denominator, we will be having 1 + gmro.
So, from here directly we can say that the voltage gain, it is ( ) ok; yeah. So, here
this RD, I should say on the in the voltage gain, it is hardly having any effect and again
finally, we approximate this by 1. Now, similar kind of things we can do for the output
resistance. This part let me clear; yeah.
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So, if I consider say this part, earlier we have seen that if I want to know the resistance or
impedance at the output terminal and if I stimulate this circuit by a voltage source called
vx and then, if I consider the corresponding ix and then, if I take the ratio of this two that
is supposed to be given as the resistance coming from this circuit. And the previous
analysis shows that the corresponding resistance is ( ).
Now, this Rc instead of Rc, we can write RD for this case and rest of the things it is same.
Now, if I consider this part also while you are considering this output resistance of
course, you have to make it ground and since, this rπ it is very high. So, this is very high.
So, we can say that you can neglect this part and you can consider only this one.
So, what we have it is Ro or Rout, it is RD. This is ( ) right. So, that is how we do
get the expression of output resistance. Again, this is in the order of . Now similarly,
we can find what will be the input capacitance. Again, for this circuit let me clear it up;
yeah.
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So, to get the input capacitance Cin, we do have the contribution coming from Cgs earlier
it was for common collector it was Cπ. So, we need to replace this by Cgs. So, likewise
here also we are having now it is Cgd; earlier in common collector circuit, it was Cµ. So,
that need to be replaced by Cgd and then, we do have the voltage gain from here to here.
So, it is it should not be emitter this rather from gate to source and gate to drain and this,
this gate two source gain we already obtained here which is given here.
And we say that the corresponding voltage gain it was ( ) and so, that that
gives us the corresponding ratio likewise you can find what will be this AvD. So, that is
vD; vD is the voltage here divided by vin. And if you plug in that expression, what you
will be getting is that Cin, it is Cgs multiplied by a factor like this and then, Cgd multiplied
by this factor. Now, whatever the factor we are writing here, here and here of course,
therefore, common collector. To convert the equivalent factor for common drain, what
you have to do you have to you know make this term, this term and this term dominating.
So, likewise here also we can see that these terms are dominating. So, in this case what
we will be getting is that Cin it will be Cgs multiplied by ( ). So, let me write here
Cin = Cgs ( ) and then, Cgd. Here Cgd multiplied by we do have here ( ). So,
this part it is approaching to 0; this part it is approaching to 1 ok.
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So, then we can say that Cin; Cin ≈ Cgd right again this is quote and unquote low. This is
approximately 1; output resistance is in the order of which is quote and unquote low.
Input resistance of course, remains high. So, then you can say that for common drain
even if I consider RD, then the basic required property of the buffer, it remains the same.
Now, so far, we have considered either RD or RL here or maybe Rs here. Now, if I

consider maybe multiple elements together, things of course, it will be getting more and
more complicated.
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You may try out; you may try out to solve say this kind of circuits, where we do consider
we do consider say the Rc part and then, RL part. So, likewise we can consider RD and RL
together and then, you can try to see what is the corresponding input resistance voltage
gain and then, input capacitance ok. So, I rather suggest you, you can work it out in our
numerical examples. So, we will be covering. So, we may not be repeating the analysis
again here ah. But in our numerical examples, we will be discussing that. I think what we
have, it is I think today let we let we conclude whatever the things we have covered.
So, far as I say that we are talking about common collector and common drain amplifier.
Previous lecture, we have discussed about this part namely the c in common collector
and common drain as voltage mode buffer. Basic operation and biasing, we just touched
upon and then, we did the analysis for voltage gain and then, impedance and then, input
capacitance for idealistic bias. And today, what you have done it is, we have done the
analysis considering realistic components to get the voltage gain, impedance and input
capacitances.
Realistic components are the load resistance may be connected at the emitter or common
or the source of the transistor respectively for BJT and MOS transistor and then, source
resistance, then also we have discussed about the effect of resistance at the collector
terminal or drain terminal. What we are planning to go for the next class, it is numerical
examples and some design guidelines. I think that is all I do have to cover.
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Prof. Pradip Mandal
Lecture – 47
Common Collector And Common Drain Amplifiers (Contd.): Numerical Examples
(Part A)
Yeah, dear students, welcome back to NPTEL online certification course on analog
electronic circuits. Myself, Pradip Mandal from E and EC department of IIT, Kharagpur.
So today, we are going to continue the discussion on Common Collector and Common
Drain Amplifiers.
So, the outline of today’s presentation, it is given in the next slide. What we are going to
do today it is primarily, we will be focusing on numerical examples and design
guidelines of common collector and common drain amplifiers.
So, I should say whatever the knowledge we have gathered in our previous discussion
namely, the analysis of voltage gain impedance and capacitance of common collector
and common drain circuit for ideal situation as well as considering the different
parasitics namely, source resistance, load resistance and collector or drain terminal
resistances that will also be getting utilized in the numerical examples.
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So, let us start with one numerical example where we do have idealistic bias. So, we do
have the common collector amplifier given here; and then we do have the bias circuits, it
is given here. In fact, I should say that VBB it is given yeah, so we do have the VBB, it is
making a bias at the base terminal and then we do have the DC supply of 10 V. So, VBB
it is given here, it is 6 V.
And then we assume that the thermal equivalent voltage it is 26 mV; then, we are also
considering that load capacitance connected at the output node; CL and its value it is say
100 pF. So these are the situation, load situation and then the device parameters are given
here namely the VBE(on) it is 0.6 V; β of the transistor it is 100, early voltage it is say 50
V. And then the parasitic capacitances namely the Cπ it is 10 pF, Cµ base to collector
terminal Cµ, it is 5 pF.
Now what we need to do it is, as we have discussed earlier, the important parameters are
the voltage gain and we are expecting this voltage gain it will be as small as possible; or
rather I should say attenuation is as small as possible. So, the voltage gain we are
expecting it will be close to 1; input impedance should be as high as possible, output
impedance should be as small as possible. Input capacitance also should be as small as
possible; and then based on the output impedance and the load capacitance, we can find
what is the upper-cut of frequency of the frequency response.
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So, these are the things we need to find, these are the final performance matrices, but the
intermediate steps are, we need to find the operating point of the transistor or the circuit
and then small signal parameters values namely, gm and gd of the transistor.
So, let me start going to the operating point first. So, if I analyze this circuit and if I
consider bias current it is, 0.5 mA it is given to us. So, we can say that the collector
current, it is also approximately equal to the emitter current. So, that is 0.5 mA, then the
base current quotient current it is .
So, that is µA. So, 5 µA, then the VBE it is given to us; so, VBE it is approximately 0.6
now, we do have the current is flowing through transistor and we do have 6 V at the DC
coming to the terminal here. So, if I consider drop across this resistance RS that gives us
the base voltage.
Now, for this case let us consider the source resistance is very small. So, we can say that
the base terminal it is also = 6 V because, the source resistance it is 0. And then the
emitter voltage it is the 6 V, the base voltage ‒ VBE(on); so, that is we do have the 6 V ‒
0.6.
So, the emitter voltage it is 5.4 V. On the other hand, the collector voltage anyway it is
10 V, Vdd. So, we can say that (VCE = 10 V at the collector ‒ the emitter voltage which is
5.4 V). So, this is 4.6 V.
So, from this one we can see that the transistor, it is in active region of operation. So, that
is that gives us the operating point of the transistor. Now, let us look into the small signal
parameters values; namely, gm and then rπ and then the rds or rather in this case it is not
rds rather, ro collected to emitter terminal resistance.
So, let it go one by one small signal parameter; values of small signal parameter. Let we
start with gm and you may recall its expression in terms of the quotient current, it is
collector current divided by thermal equivalent voltage and collector current it is 0.5,
. So, we can say that this is A/V.
And then rπ the base to emitter impedance, rπ. So, that is you may recall that this is .
So, it becomes 100, β × it is 52 Ω. So, this multiplied by 52 Ω, so that gives us the
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value of 5.2 kΩ. On the other hand, the collector to emitter terminal resistance ro; which
is early voltage .
Now early voltage it is given as here it is . So, that = 100 kΩ. So now, we obtain
the small signal parameters. So, you can recall these numbers; so, we are going to utilize
the same space to calculate the voltage gain than then input impedance output impedance
and so and so.
So let me clear the space and then again. Let me start with the voltage gain, small signal
voltage gain Av = ; if I say that small signal voltage here it is vo and the voltage
coming here it is vin, so for small signal of course, this this terminal it will be AC ground.
So, we may see that this is connected to AC ground.
Now, the expression of the voltage gain you may recall for this circuit, it is (gmro + 1) in
the numerator, and then in the denominator we do have (gmro + 1) rπ + rπ right. And just
now we have discussed about gmro. So, gm it is and then ro it is 100 k right.
So, (100 × 103 + 1) and in the denominator we will be having this gmro. So, that is equal
to whatever, ( )rπ; that is 5.2 kΩ + this are yeah I think this is this should be rπ and
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this is ro anyway yeah. So, let me write this values of this gmro which is 105 divided by no
the; let me clear it.
( )
The voltage gain it is Av = ( )
. The other form it was having some any
anyway, this this is the correct one. So, now ( = β; + 1) ro; and in the denominator
we do have ( ) .
So, in the numerator we do have β is 100. So, I should say and then ro it is what we said
( )
is 100 k. So, . So naturally, you can drop this part and then you may
( )
say that this is approximately 1. So, that is what we are expecting the gain it should be 1.
But here, numerically you can say it is really close to 1. And then input resistance of the
circuit looking into this circuit; so, what we have it is Rin, you may recall from our earlier
derivation Rin = ( ) right. Because this bias circuit we are assuming it is
having ideal situation; so, its conductance is 0. So, this is rπ it is 5.2 k + ( is β; + 1)
ro it is, 105. So again, this =, so this is 101 × and then 105.
So again, this part it will be very small. So, we can directly approximate this by 10, 101
× 105 Ω or what you say, it is 10.1 MΩ. So, this is quite high. So, the input resistance it
is as you said it is very high, and this is approximately 1, this is 10’s of MΩ. Now,
coming to the output impedance, so let me again clear it.
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And, let you go for the output impedance. So, output impedance it is looking at the
output terminal, what we have it is at this point. So, we do have conductance
here, conductance of the rπ, then ro and then also the gm part.
So, the output resistance it is namely, gm then due to rπ, and then due to
ro alright. So, yeah so, we do have the values here 1 by so, this gm, it is 1 by 5 point
rather 52, + this rπ it is kilo alright.
And then ro it is 10. So that is 100 k, 105; and again, this is it can be well approximated
by this term. So, that gives us 52 Ω. So, that is the output impedance. Now coming to
the; so, you can remember this one; you can remember this one for calculating the upper
cutoff frequency. So, we will be coming back to that.
Now the input capacitance; so, we do have input capacitance Cin looking into this circuit,
it is what we said it is Cπ multiplied by a very small factor.
So, what was that factor? It was rπ divided by as you may recall. Yeah, so Cπ
(( )
). And then Cµ as is; so again if you consider this is β and this is very
high. So, compared to that we can see that this is anyway small and this is also small. So,
we can approximate that this is Cµ and that = 5 pF.
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So, we do have the output resistance looking into this circuit it is 52 Ω and then we do
have the load capacitance here; CL it is 100 pF. So, we can say that the upper cutoff
frequency now, so this is done. Now the upper cutoff frequency if I say that fU upper
cutoff frequency, it is . So that is, let me use different color should see
( )
RoCL.
So, we do have . So, that is 1010 alright, and so this is 10‒10. So, that
comes to be 1012, 1010 divided by approximately or say to be more precise 104 × π. So,
that is .
So, roughly we can see that approximately if I say that this part it is 3 and then this is
almost 100. So, that is 10, 10 to the power it is now, this is we do have another 100. So,
this is 108. So, we do have 100 divided by no.
So, what we have here it is . So, roughly this is 100 × MHz yeah. So, it is more
or less in the 10’s of MHz. So, rather I should say; no, I should say close to 30
approximately 30 MHz.
So, here it is close to 30 MHz right. So, that gives us some idea that even if say load
capacitance it is 100 pF, the output, the bandwidth of the circuit coming from the output
node it is quite big and we are considering the source resistance is approximately 0.
So, the Cin is not having much role to play, but even if I consider practical value of this
source resistance since Cin is small then, the corresponding bandwidth coming from the
from the input pole will also be quite big. So, let us see in the next circuit that if we
consider source resistance RS which is say may be having some practical value.
Then you can see what will be the corresponding impact.
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So, in the next slide, it is basically the same circuit except, here we are considering the
RS different from different from 100 k. So, if you see this circuit if you analyze this
circuit with the bias current of say 0.5 mA and then if you try to analyze what will be the
operating point.
So, we do have at the base we do have the 6 V of this VBB, and then we do have the RS
and then base to emitter we do have a voltage drop. So, so I should say I am just circling
it to indicate that this is representing VBE(on). And then we do have that is the bias current
of 0.5 mA. And then here we do have the and the collector current, right.
So, this collector current we may approximate that this is also equal to 0.5 mA. Now to
find the voltage here, what you have to do? So, we can say that IC it ≈ 0.5 mA or other to
be more precise it will be 0.5 ( ) all right.
So that is to be more precise, so I but then we can say that it can be well approximated by
0.5 mA; which gives us the base terminal current it is ( ). Again so, this = 5 µA.
Now once we do have the 5 µA flowing through this RS; obviously, then there will be
finite drop here since it is 100 k, 100 kΩ resistance that is quite large. So, we need to see
what the drop across on this resistance is.
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So, the voltage drop across this RS equals to resistance is 105 and the current is 5 × 10‒6.
So, that is giving us a voltage drop of 0.5 V.
So I should say, so, this gives us the base voltage = 6 ‒ 0.5. So, this is the drop across the
resistance RS. So, that gives us 5.5 V. And then the emitter voltage VE = the VB which is
5.5 ‒ 0.6, VBE(on). So that gives us 4.9 V.
So, we do have the base voltage, we do have the emitter voltage and collector voltage
anyway, it is 10 V. And then base current is here, collector current is also approximately
this one. So, that gives us the operating point.
So, note that even though the voltage here it is different from significantly different from
6 V bias here due to finite value of this source resistance. But since we do have the bias
current here it is ideal quote and non-quote ideal of the same value of 0.5 mA the
collector current and base current hardly gets affected, only thing is that the voltage here
and voltage here they are getting changed compared to the previous case.
So anyway, since the collector current is a still remaining 0.5 mA so, the small signal
parameters on the other hand it is remaining same as the previous one; namely the value
of the gm. So, gm it is again it is A/V.
Then rπ it is 5.2 kΩ, and then ro = 105, so that is 100 kΩ right. So, since the small signal
parameter it did not change; so, the voltage gain and then input impedance, output
impedance they will be remaining unchanged.
In fact, if you see the output impedance there will be a small change we will we will see
that, but the voltage gain no need to repeat here. So, again this will be very close to 1,
input impedance looking into this circuit it is remaining same. So, this will also be same.
So, we will not be considering this calculation.
So, if I consider this is the input impedance looking into the base that is remaining
unchanged; but then of course, due to the source resistance RS the output impedance it
will be different. So, that probably we can see what is the output impedance?
Input capacitance again, it will be approximately Cµ. So, only thing is that let us try to
see what is the corresponding output impedance of this circuit in presence of the source
resistance RS.
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So, let me clear it. So, what we are going to do, we need to see what will be the output
resistance. So now, you may recall that at this point if we give a give a stimulus of say vx
in the small signal equivalent circuit; then if we try to calculate what is the corresponding
ix and of course, this node it will be AC ground.
So, we do have RS and then this RS coming in series with rπ, if I try to sketch the small
signal equivalent circuit here and then here we do have the gm part and then we do have
the ro part here. So, looking into the emitter here and if we stimulate the circuit with the
vx here ; we will be having 3 current components one is this, then another one is this one
which is gmvx, and then the resistance here.
So, you may recall that we do have the 3 conductances to contribute to ix. So, that gives
us a hint that the output resistance it will be 1 divided by all the 3 conductances. One is
gm, then and then .
Now here, we do have and this is gm it is and then ro it is 100 k. So, we do have 100 k
here, 105 and then . So, Rs we are taking 100 k. So, this is . Again,
compared to this term the other terms we can drop. So, it is again it is coming ; that
means it is 52 Ω.
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So, even though we are connecting this RS; since, we do have the ideal current source
and the small signal parameters remains the same, so, the performances of all the circuits
it is remaining same. In fact, output the upper cutoff frequency also remains the same.
Only thing is that whenever we are feeding the signal at this point, so, since you are
feeding the signal at this point and then we do have the RS and also the input capacitance
coming here then we do have one more candidate to define the upper cutoff frequency
and that is let me call fU2 which is coming from RS and the Cin. Of course, we have to
consider the 2π part.
And if you see in this case, I should say that predominantly this again this since Cin it is
coming from Cµ. So, we can say that this is then RS is 105 and then Cin it is 5 × 10‒12.
So, that gives 5 and 2 gives 10. So, this is 106 it becomes 106 and then we do have 10‒12.
So, that gives us 106 in the numerator divided by π; and π is approximately 3. So, we can
say that this is approximately ⅓ MHz. Whereas, the pole coming from the output node, if
I call that is fU1 which is coming from the output resistance 2πRo and then CL.
And this one it we have seen it was approximately 30. In fact, around 28 to something
like that; so, 30 MHz. So the upper cutoff frequency of course, it will be defined by
whichever is minimum.
So, I should say that the upper cutoff frequency it is getting changed, but still it is
remaining high; primarily, due to the input capacitance here it is it is actually coming
from this Cµ and its value it is only 5 pF.
Now in case if the load capacitance if it is directly connected at this point namely if it is a
100 pF; obviously, then this RS and then this CL it would have created the upper cutoff
frequency much lower than whatever the ⅓ MHz you are getting here, ok. So, let me
take a small break and then we will come back with some more numerical examples.
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Prof. Pradip Mandal
Lecture – 48
Common Collector and Common Drain Amplifiers (Contd.):
Welcome back after the short break. So, we do have here it is the third example. So, it is
you can see that essentially, we are adding one resistance at the emitter instead of having
ideal bias current and also we do have the RS at the base node. We can say the source
resistance. Let you consider this RE 9.8 kΩ. So, let me change this one to 9.8 kΩ and let
us try to analyze the circuit to find the operating point of the transistor.
So, to start with let me draw the DC loop here. So, we do have Vdd which is 6 V and
then we do have the RS, which is 100 k and then we do have the VBE(on) this diode drop
and then we do have the resistance here RE. So, that you consider the current flow here it
is IB. And then of course, we do have the β times of this IB current it is coming from the
collector. So, we can say that this is βIB. So, that is the IC part.
So, the current flowing through this resistor on the other hand it is (1 + β) IB. So, if I
consider that this current it ≈ βIB and then if you analyze this circuit. Namely, if we
consider the potential drop through this loop. So, what we can get it is in this loop. We
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do get 6 V here and then we do have 0.6 V here. So, 6 V equals to we do have IB × 100 k
+ 0.6 V and then roughly you can say that 100IB × RE ok. And RE, we said 9.8. So, what
we are getting here it is IB × 100 k. So, that is 105 and then RE we do have 9.8 k.
So, this is this plus. So, this is 9.8 × 105. So, this = 5.4 V. So, that is 5.4 V is 6 ‒ 0.6. So,
that gives us IB = . So, that gives us 5 µA. So, just a make a note that we have
intentionally have tuned it this resistance. So, that we can get the same value of this IB,
what we have obtained in our previous example of 5 µA.
So, even if this resistance it is something else of course, the circuit it will be working
fine, but it is just for making this circuit comparable with the previous circuit we are
making this RE = 9.8. So, once we obtain this IB of say 5 µA, so, that gives us the IC =
100 × 5 µA. So, then β × this 5 µA so, that = 0.5 mA right.
And then once we have the IC equals to this one, then you can calculate what will be the
voltage here. Similar to the previous case; the voltage here it will be 6 V here minus this
drop, drop across this RS and this that drop it is 0.5. So, we can say the voltage here VB =
6 ‒ 0.5. So, that is 5.5 let me use a different color.
So, the voltage at the base it is 5.5, the voltage coming here it is 5.5 ‒ 0.6. So, the voltage
here it is emitter voltage = 4.9 V. So, that is 5.5 ‒ 0.6 and of course, the collector voltage
here it is 10 V.
So, that gives us the operating point of the circuit. Now using this value of the quotient
currents and voltages we can find the small signal parameter. And since the currents
particularly, the collector current and base current they are same. So, we can see that the
gm value of the gm remains the same. Namely, A/V, and likewise rπ = 5.2 k and then ro
= 100 k right. So, we obtain the small signal parameter. Now then we can find what will
be the voltage gain input impedance output impedance so and so.
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So, let me use the same space and let me clear it and again these we are considering it is
9.8. Sorry for the correction here again and again. But, anyway we do have the voltage
gain you may recall the voltage gain Av, since we do have the RE here earlier in our
analysis we have considered this resistant resistance as RL with that. So, the voltage gain
we obtain it is (gmrπ + 1) (ro ⫽ RE) right.
So, that is because we are having this ro coming here and this RE and ro they are coming
in parallel because this terminal for signal it is AC ground. So, ro and RE they are coming
in parallel. In the denominator on the other hand; we do have (gmrπ + 1) (ro ⫽ RE) + rπ.
So, what are the changes we do have here it is; this is of course, (β + 1). Now ro it is 100
k and RE it is 9.8 k right. So, close to this one, 9.8 k or to be more precise it will be close
to 9.5 or something like that. But whatever it is say we approximate by this RE, it is a 9.8
k. So, likewise in the denominator we do have (β + 1) × 9.8 k and then we do have the rπ.
So, this rπ it is this is 5.2 k. Note that this voltage gain it is from this point to this point.
We do have RS also to be considered, but attenuation for this circuit from this point to
this point, it is expected to be very small even though RS it is 100 k. Mainly, because you
do have the resistance here, input resistance here it is very high. But anyway, we will see
that, but for the time being let you consider voltage gain from precisely at the base
terminal to the emitter terminal and even though this RE it is coming in parallel with ro
because, this we do have (1 + β) getting multiplied.
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So, still this part it is dominating over this part. So, still and hence we can say that this is
approximately 1. So, the voltage gain it is approximately 1. Now let us look into the
input resistance. So, let you consider the input resistance. So, the input resistance on the
other hand it is as we have discussed before. So, this will be rπ + (gmrπ + 1) (ro ⫽ RE).
And again this is the input resistance looking into the base of this one, base of the
transistor without considering this RS.
So, we do have rπ = 5.2 kΩ and then a we do have (β + 1) and then this resistance it is
whatever 100 multiplied by 9.8 divided by 109.8 into 10 to the power 3 kilo right. And
so, this part again either we can approximate by 9.8 or so, we can say that this is close to
9. But, it will be very close to 9 this if you say that this is 10 11. So, that will be close to
this one, but whatever it is. It, we do have so if I approximate this part or this is equal to
very close to 9 kΩ.
So, even then we do have 5.2 kΩ and then we do have 100, one getting multiplied with
and this 9. So, that is giving us 909 kΩ. So, that is equals to 914.2 kΩ that is definitely it
is higher than this resistance. So, the attenuation coming at this point, because the input
resistance here it is given here. Attenuation due to this finite value of RS which is I
should say the voltage here with respect to this one or rather base voltage vb with respect
to vin it is given by . And RS is 100 k, Rin it is close to 900 k. So, accordingly you
can say that this is 914.2 divided by this is 1014.2.
So, it is very close to 0.9. So, even if I consider this finite value of RS then the voltage
gain starting from the primary terminal to this point even though I do have RS is quite
high, still it is around 0.9, considering this RS high value of RS right. So, that is about the
voltage gain remaining close to 1. Output resistance we have discussed before. So, again
we can probably we can go through that the let me clear this and this is 9.8 k as we have
taken.
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So the output impedance it is if I consider this part this is giving us the output impedance
very close to . So, RO it is very close to and then we also have this and RE since
it is quite high compared to . So, this is remaining close to which is 52 Ω.
So, the upper cutoff frequency considering the CL and the output resistance if I consider.
So, this upper cutoff frequency coming from the output node, if I say that fU1. So, that is
equal to . So, this is remaining very close to 30 MHz. And then if I consider the
input capacitance; again Cin it is still we will approximated by Cµ and hence fU2, the
second option for the upper cutoff frequency which is .
So, that part it is I should say I do have the Rin also, but yeah Rin is much higher than RS.
In fact, to be more precise I should rather consider the Rin also. So, we should consider
RS ⫽ Rin and then Cin. And of course, here this resistance it is coming close to and this
close to 100 kΩ. So, again this frequency it is very close to MHz.
So, the conclusion here it is what we can say that even if you consider RE and RS still we
do have the overall performance of the circuit even with RS is very high overall
performance of the circuit or the qualitative performance of the circuit. Namely, the
voltage gain approximately one and then input resistance is very high, output resistance
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is very small, input capacitance is low and then the upper cutoff frequency it remaining
high only right.
Now, if I consider the other resistance also RC then of course, there will be a change. So,
we will see that, but before that let you consider the most counterpart also, namely
common drain amplifier. So, in the next slide we will be going for common drain
amplifier yeah. So, here we do have the common drain amplifier.
Again for this circuit also to find the to find the performance parameters, we need to
follow the same procedure. Namely, we need to find the operating point then we needs to
find the small signal performance then as parameters values and then we can find the
corresponding voltage gain output resistance in then input capacitance in so and so.
So, here of course, the circuit it is different slightly different. So, let us try to see with
this example, how do we find the operating point of the transistor. Remaining things it
will be similar to the common collector circuit. So, let us try to see that. So, to get the
DC operating point, let we consider this circuit. So, what we have here it is in DC
condition; VG if I say that RS it is even though it is say 10 k or 100 k since the current
flow here it is 0, DC wise. So, the drop across this RS is 0. So, we can say that VGG it is
directly coming to the gate node.
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So, if I say that VGG equals to, I do have the VGS of the transistor and then we do have
the current flowing here right. And this current flow of course, it is we do have say 1 mA
of current. So, we are expecting that to find the voltage here which is basically the VGG
minus this 1 sorry, I should say that the VS voltage or Vout voltage it is VGG ‒ VGS.
Now, to find the VGS what you have to do this is now IDS. So, we can say that IDS = IBIAS
equals to the expression of the current which is ( ) . And we may drop this
( ) factor. We can approximate this is may be = 1. So, if I equate this part; what
we can get here it is VGS = Vth + 2 × IBIAS and then divided by and then square root.
So, here we do have Vth of the transistor it is given here which is 1 V + 2 ×IBIAS it is 1
mA and then the device parameter it is given here it is = 2 mA/V. So, 2 mA per, I
should say this is V2. So, what we have here it is this 2 and this 2 it is getting cancelled.
We do have mA it is also getting canceled. So, this part, this part as a result it is we do
you have 1. So, the VGS it is 1 + 1 = 2 V right. So, that is the VGS.
So, from that we can say that the voltage at the source it is 6 ‒ 2, that is 4 V. So, the
voltage here it is 4 V and of course, the drain voltage here it is 10 V and gate voltage
here it is 6 V. So, that gives us the operating point of the transistor of course, it ensures
the transistor it is in saturation region of operation which is of course, required. And then
we can calculate the small signal parameter. So, let us try to see what will be the small
signal parameter values. Let me use this space here.
So, the gm particularly the gm it is × (VGS ‒ Vth). So, what we have it is 2 mA/V2 and
this is 1 V. So, 2 × 1 mA/V, on the other hand the rds which is . Now λ it is given
here it is 0.01 0.01. So, that is 1 divided by 0.01 which is 10‒2 and then IDS it is 1 mA
which is 10‒3.
So, that gives us 105 Ω. So, that is the; that is the impedance we are getting for this rds
and this is the gm part. So, using that we can find now we can find the voltage gain. So,
you can probably for the to calculate the voltage gain, let you try to remember the value
of this VGS and sorry, the gm and the corresponding value of the rds.
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So, again let me use the space and clean it. So, what we are looking for it is the voltage
gain Av.
So, what is the voltage gain of this circuit? The and gm it is 2 m, 2 × 10‒3 and rds
it is 105 Ω. So, likewise here also 2 × 10‒3 and 105 + 1.
So, here in the numerator we do have 200 and in the denominator we do have 201. So,
we can approximate this by 1. So, the voltage gain it is 1. And then the output impedance
if you see the output impedance Rout = . So, what we have here it is it is 2 m, 2
× 10‒3 and then . So, that is 10‒5 right.
So, again this is this part it is dominating over this. So, we can approximate this by so,
which is 500 Ω. Of course, it is not as small as the previous case; namely as small as
Rout of common collector stage, but still it is low and then if you consider we do have the
capacitance coming here of say 100 pF.
So, from that we can calculate the upper cutoff frequency. But before that we can find
what will be the Cin. So, let me use different color for Cin. So, now, we are going to
calculate Cin which is Cgs. So, we do have the Cgs part multiplied by , you may
recall this expression plus Cgd.
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So, this part of course, we do have here it is 201. So, we may drop this part or rather I
should say Cgs we do have the and Cgd it is 2 pF. So, this part we can say it is closed
to we can approximate this 2 by 2 pF only. Because, how much is it, this is 10, 5, 5 and it
is just right. It is it is very small we can ignore this part definitely we can ignore. So, this
is what the input capacitance.
Now, if I say the upper cutoff frequency let me again clear it and use the space here. So,
upper cutoff frequency coming from CL. fU1 = output resistance it is 500 and CL it is
10‒10 Hz.
So, we can multiply this 2 with 500 to get 1000 here. So, what you are getting it is .
So, approximately = MHz or we can say that this is close to 3 MHz of course. And
then the other candidate to define the upper cutoff frequency which is coming from this
RS and Cin. So, fU2 = , we are taking 100 k, 104 and then Cin it is 2 pF so, 2 × 10‒12.
So, this 4 and this minus 12, if you see we do have minus 8 here. So, we can see it is
or we can say this is 25, MHz. Or we can further simplify if I consider this is 3. So,
roughly it is 8 MHz.
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So, that gives us the upper cutoff frequency it is defined by this only. So, that is the
upper cutoff frequency. So, that is how you can analyze this circuit.
So, similarly, if I consider the common drain circuit with say resistance here RL instead
of BIAS, then we can get the similar kind of performance probably you can work it out.
So, let us see what the circuit I do have for you yes is. So, here we do have same
common drain amplifier, but we do have RL having a value of 4 k. RS, we do have same
10 k. So, instead of having ideal BIAS circuit if we put say RL of say 4 k and then VGS of
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say 6 V with whatever the parameter it is given here, then how do you find the operating
point.
So, this part since it is tricky. So, let me explain to you, rest of the things probably you
can do it yourself. So, again if I consider this loop; what we can get here it is the drop
across this RS is 0. So, we can say that gate voltage it is directly coming here DC wise
and then we do have the VGS here and then we do have the IR drop. So, if I call this is VO
output voltage, then VGG, VGG ‒ VO it is essentially VGS of the transistor right.
So, we can say that the voltage here on the other hand, if the current flow here it is say
IDS, the voltage here it is RL × IDS. So, in other words we can say that the VGG ‒ this VGS.
So, that is equal to. So, this voltage that is equal to IDS × RL. Now this VGG if you on the
other hand if I say that VGS and the yeah. So, this is so I can say the other way also say
IDS = ( ) .
And then if I multiply this by RL. So, what we are getting it is RL × IDS, but that is equal
to this one. So, we can say that, this is equal to VGG ‒ VGS right. So, probably, we can try
to see what will be its expression of this IDS from this or from how do we proceed the,
maybe you can try to write. So, this in term of VS and so, this is VS then, so this is VS.
So, from that we can say that VGS = VGG ‒ VS.
Yes. So, now, we can say that VS = this one. On the other hand VGS, we can replace by
this VGG ‒ VS. So, we can let me use different color. So, using this part and this part
along with this one, what we can say that VS = × RL × VGS which is ( ) .
Now, let me put the value of different parameters here. So, we do have RL = 4 k and this
part it is 1 mA/V. So, we can say that VS = 1 mA; 1 × 10‒3. RL = 4 k, 4 × 103 and then we
do have VGG ‒ Vth, that is 6 ‒ 1, so, that is ( ) . Or we can probably you can make it
( ) . So, ( ) × 4 = VS right. Or we can say that we can take this 4 here.
So, we are getting ‒ 10VS + 25. Then = 0. Now if you solve this second order
equation; what will be getting is that one solution you will be getting for VS. So, the
coefficient of VS here it is with a ‒ sign. So, ± √( ) whatever it is.
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So, we do have A × C. So, we do have 4 × 25, so, that is . So, if you take 4 outside
what we will be having here it is 41 divided plus minus. So, here we do have 41 square
and here you do have 16 yes so, 4 square. So, basically you will be getting 81 square root
divided by 4 into 2 8.
So, this gives you this is 9. So, we can say that VS, I am using this space sorry for clumsy
here, clumsy arrangement 41 ± . So, one solution if I consider minus, one solution it is
4 V and the other solution if I consider this is plus that is .
Now, this is not possible that because, the transistor enters into cutoff. So, we are not
considering this one, we need to consider this one. So, if I consider VS the voltage here
actually. So, this is same as the source voltage VS if the VS it is 4 V; we do have 6 V. So,
the voltage drop here it is 2 V.
So, that gives us VGS = 2 V. If the VGS = 2 V, then we can say that the corresponding IDS
= , that is 2 m and then divided by 2 into VGS is 2 V ‒ Vth square so, that gives us 1
mA. So, again we are making this RL = 4 k. So, that the current flow IDS it is consistent
with the previous example right.
So, let you consider that that much of current and it is consistent to the previous case and
once you obtain the value of this IDS. So, then we can find the corresponding value of the
small signal parameters. So, let me calculate the small signal parameter.
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So, I think we already have done that since IDS = 1 mA. The corresponding gm, it was
coming 2 mA/V and of course, the r ds it is same as the previous case; 100 k. And rest of
the parameters you can calculate yourself. So, I am not going to repeat that part now if
you have say rds connected here then what will happen?
So, let me see that part. So, we do have this RD also connected we do have the RD
connected here. So, what we say that we do have RD which is 4 k and then RL also 4 k.
Assuming this transistor it is in saturation earlier we already have analyze that for RL of
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4 k, IDS equals to so, that is equal to 1 mA and if this is RD = 4 k. So, the drop across this
RD is 4 V.
So, we do have 6 V coming here. So, this is 6 V and the source we do have 4 V. So, the
voltage coming here after subtracting 4 V from 10 V, it is 6 V. So, we do have 6 V here,
we do have 6 V here. So, that this transistor it is still in saturation region of operation.
So, that makes the circuit it is still working as a good amplifier. And then you can use the
IDS current and the VGS to calculate the gm and this rds it still remains high namely 100 k.
And so, what will happen is that the impedances; particularly, the output impedance it
will be having little modification gm the voltage gain since the gm it is remaining same
voltage gain again approximately it will be 1, output impedance it will be having slight
change. In fact, if we see the Rout, if you look into this circuit; the Rout it will be .
So, that you can calculate.
So, that is the resistance here and the total resistance looking into the circuit; it will be
this part coming in parallel with RL. Now here if you see the numerical value; this part it
may be dominating over 1 and then rds it is also dominating. So, as a result this part it is
becoming only all practical purposes. And then, RL even though RL it is coming in
parallel. So, it is since it is 500 Ω. So, again this can be well approximated by and
it is 500 Ω.
So, even though we do have RD it is there, but the if you see the output impedance it is
remaining low quote and unquote low. And it is expected that upper cutoff frequency
defined by output resistance and the CL, it is almost remaining the same. Only another
important thing you must be careful that voltage coming from this point to this point it is
also prominent. So, as a result and that not only the Cgd, it will be contributing through
Miller effect, but sorry, Cgs. But Cgd, it is also having Miller affected part. So, what is the
voltage gain coming from the gate to drain that we need to see.
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So, if you see the voltage gain coming from gate to source that is approximately 1, that is
what we said. But in addition to that, if you see the Cgd and the voltage coming here we
call say Vd. So, that is definitely it is nonzero and the voltage coming here it is vin
multiplied by approximately × RD divided by the so, that is × .
So, if I consider this resistance is very high compared to RD. So, that is what I will be
getting and this can be well approximated by with a of course, a ‒ sign. So, now, in
this example since we are taking both of them are equal. So, we can say that the voltage
gain from here to here, it will be close to 1 with a ‒ sign. So, we can see that C in; it is
having primary contributor is Cgd, but it is getting affected by this voltage gain,
and this part it is given here.
So, from this equation if you see this part it is Cgd × 1 and then ‒ 1 is also there. So, it
becomes 1 + . So, I should say that this becomes practically 4 pF. So, what is the
conclusion here it is even though we do have RD here and we do have the signal coming
here since, Cgd it is small and then the input capacitance still it is remaining low.
But, we need to be careful that RD may be allowed to some extent, but if the RD it is
coming more and more then, the contribution of the Cgd to the input capacitance it will be
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large. And as a result the upper cutoff frequency defined by RS and the Cin that may be a
problem.
So, unnecessarily, we should not be putting this RD. So, that is what the conclusion. So,
let us see what is the design guidelines we can follow based on this knowledge? So, let
me I think I do have a slide for that.
So, with here it is the analysis the knowledge of the circuit analysis can be utilized where
in the analysis part; we have started the calculation from top to bottom of this list. While
these parameters it was given to us. So, that was the numerical analysis we have done for
the common collector or common drain circuit.
Now, if we have to make a design, where in fact, these parameters it will be given to us.
Voltage gain should be close to 1, then output impedance it will be given to us, and then
maybe for a given value of the load capacitance; the cutoff frequency may be given to us
from that we need to calculate RO.
So, this output impedance we can find. So, the way we will be preceding while we have
to design the circuit it is basically from bottom to up. And so, from the requirement of
the output impedance which we know that this output impedance is 1 by, roughly and
that gives us the requirement here. So, then once you have the value of the gm, from that
we can calculate what will be the corresponding IDS.
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So, what is the sequence? From RO we calculate gm and then from that we calculate ID or
IDS. And to achieve this IDS, we can find what supposed to be the meaningful DC voltage
and what will be the corresponding meaningful resistance of the source. And better, we
should avoid this resistance and ideally we want this resistance should be 0. So, that
unnecessarily we do not want to complicate the circuit and contribution of the Cgd, we do
not want to take it to the input capacitance otherwise that will affect the upper cutoff
frequency.
So, the summary of the design guidelines is that we start from output resistance
particularly for common drain circuit then we calculate gm, we calculate the required IDS
to achieve the required IDS, then we can find what will be the value of this one and also
the corresponding DC voltage here. In fact, this DC voltage it may be coming from the
previous stage. So, in case if this is given to us; accordingly, then we can calculate the
corresponding RL. So, it boils down to the point that we need to calculate the
corresponding RL of the circuit.
So, similar kind of guidelines it can be followed for the common collector circuit also.
Where, again the information may be given or rather requirement it will be given for the
upper cutoff frequency for a given load capacitance. So, from that we need to calculate
what is the RO. And this RO, since it is predominantly defined by gm from that we can
find what is the corresponding trans conductance and from that we can find what will be
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the corresponding collector current. And if the collector current is known to us, then for a
given value of VBB, we can find what will be the corresponding RE.
So, if VBB, it is given to us then, the last thing it is we need to find the corresponding RE.
But whatever the calculation we will be doing. We are assuming that the remaining
parameters are given to us. Namely, the device parameters particularly the early voltage
and Cπ, Cµ even though we do have so many parameters, but primarily we do have the
main thing is the collector current and gm it is defining the circuit performance of this
voltage buffer.
I think we need to conclude now. So, what we have done today? It is we are we have
concluded with numerical examples and exhaustive numerical examples it is giving us to
understand how we proceed for designing a circuit. So, the design guidelines of the
common collector and common drain, it is also covered and so, that is all about this
second configuration. Now in the next class; we will be going for the other configuration
namely the common base and common gate configuration.
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Prof. Pradip Mandal
Lecture- 49
Common Base and Common Gate Amplifiers: Analysis (Part A)
Yeah. Dear students we will come back to NPTEL online certification course on Analog
Electronic Circuits. Myself, Pradip Mandal from E and EC department of IIT Kharagpur.
So, this is continuation of this course and today’s topic of discussion it is Common Base
and Common Gate Amplifiers.
So, based on our overall plan let us see what our situation is now if we are in week-5 and
we are in the building blocks of analog circuits. And in week-5 we have completed
common collector and common drain.
Today we are going to discuss about the common base and common gate amplifiers.
Under that we will be discussing about basic operation biasing, analysis and design and
numerical examples will be covered will be covering later in the next class. So, whatever
the concepts we are planning to cover today it is the following.
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We shall start with the motivation of going for this new configuration called common
base and common gate amplifiers specifically for BJT and MOS based amplifiers.
Then we will be talking about the basic operation of these two configurations. In fact,
common base and common gate they are I should say similar kind of configuration
common base is used in BJT and on the other hand common gate it is MOSFET
transistors. So, after the basic operation we will be going for a biasing of these two
configurations; then we will go a little detail of small signal analysis to find the
following important performance matrices; namely the voltage gain, input impedance,
output impedance. And then we will also see the current gain.
Now, coming to the motivation of these two new configurations; as we have discussed
already about the common emitter and common source amplifier followed by common
collector and then common drain. Now, we are entering into the third configurations. So,
let us see what the basic motivation is as I said.
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So, this is it is again recapitulation over whatever we have discussed before. To start with
the motivation, you may recall that common emitter and common emitter cascaded it is
having some cascading effect. Namely, the output impedance of the previous stage and
the input impedance of the subsequent stages they are creating you know potential
division.
As a result we already have seen that due to this interaction what you call it is loading
effect. Due to the loading effect it degrades the overall gain starting from the primary
input to primary output if you directly connect this one; it also affects the upper cutoff
frequency or the bandwidth of the circuit.
Mainly because the output impedance of the previous stage and then input capacitance of
the subsequent stage they are forming a pole. So, as a result this additional pole it may
restrict the bandwidth of the amplifier. So, what we have seen in the previous class
particularly for common collector configuration. What we said that if you put a common
collector stage here it helps to improve the circuit performance. In fact, it is similar for
the MOS counterpart namely if we have two common collector sorry common source
amplifier cascaded together.
Here also the loading affect at this point namely the output impedance of the first stage
and the input capacitance of the second stage. In fact, input impedance also they are
creating the loading effect. And again here also the solution it is we have to put a buffer
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and for MOS based circuit or buffer it is common drain and here we say it common
collector. And in these two cases what we have seen here it is the signal here it is in the
form of voltage. So, I should say for voltage mode of operation the buffered
implementation it is either it is done by common collector or common drain.
So, likewise if the signal if we consider here it is in the form of current, then also we will
be seeing that there will be some performance degradation; to overcome the performance
degradation we may require a buffer suitable buffer which is current mode buffer. So,
coming to what may be the implementation of the current mode buffer, it is for BJT it is
common base and for MOS it is common gate. So, I should say that these two circuits
namely the only common base this is working as buffer, buffer for current mode
operation and. So, this is buffer for BJT and this is for the mas based.
So, both the common base and common gate essential requirement is it is working as a
buffer. So, let us see what is the basic property we are looking out of this current mode
buffer or buffered in current mode operation, whether you know the common base and
common gate the configurations are they suitable for those requirements that we will see.
So, what we have summarized here there is in the previous discussion it is summarized
that. For voltage mode operation whatever the buffer we are looking for the basic
property, we have seen that the input resistance or input impedance should be high
output resistance of the buffer should be as small as possible. And the voltage attenuation
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offered by this buffer should be as low as possible or you can say that voltage gain
should not be much lower than one.
And these requirements are getting fulfilled by common collector and common drain
configuration; that we have discussed in our previous years discussion. Now, the counter
part of the amplifier in the current domain. So, that is what we will see that the buffer in
current mode operation, the requirement here it will be complementary in nature. So, let
us see what the requirement there is.
So, this is the current mode buffer requirements it is a listed in this part. So, this is the
current mode buffer, this is for our reference we are keeping the voltage mode. So, this is
I should say voltage mode a buffer and if you see if you compare the features of these
two kinds of buffers; one is voltage mode another is current mode. For voltage mode
buffer output impedance should be as low as possible for current mode output resistance
should be as high as possible.
So, likewise if you see the input impedance the requirements are complementary. So, for
voltage mode the input resistance should be as high as possible whereas, for current
mode buffer the input resistance should be as low as possible. And of course, since it is it
is in voltage mode operation we required the voltage attenuation should be as low as
possible.
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Whereas for this case the current attenuation should be as low as possible. So, this
requirement as I said it is getting fulfilled by common collector and or common drain
configuration likewise this set of requirement it is getting fulfilled by common base or
common gate configuration. Common base is the BJT version and common gate it is the
MOS transistor version.
So, that gives us the motivation while we are going for this new configuration namely
the common base or common gate configuration. So, let us see basic operation next slide.
So, the basic operation it is I am keeping both the common base as well as common gate
simultaneously because they do have a lot of similarities. So, the analysis can be shared
across these two configurations.
So, let us see the basic operation, if I consider the ideal bias situation of course, the input
here it is the emitter. So, this is the input node and the output it is at the we are collecting
from the collector. And for the time being we know that its basic purpose it is buffered in
current mode amplification, but for the time being let we keep our mind flexible this
circuit can also be used for voltage mode operation.
So, we will see that why we are insisting for current mode gain later. But let we start
with our standard discussion namely the voltage mode operation and then input and
output impedance. And then we will be moving towards the current mode gain.
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So, coming to the basic operation with ideal bias at the emitter of this BJT we require
some biasing arrangement. So, that the DC current need to be supported at the base we
require a DC voltage. In fact, we want this node should be the base node should be AC
ground. So, if it is DC voltage it is with a 0 resistance it is fine. In case if it is having
some resistance here thevenin equivalent resistance coming from the bias circuit, then
you may have to add a capacitor here.
But whatever it is signal wise we want the signal at the base should be quote and unquote
0. Now, at the input we can give the signal through a capacitor it may be voltage or
current. So, that the DC operating point or at the emitter node should not get disturbed by
the DC condition of the input signal source.
So, that is the purpose of adding this DC blocking capacitor. So, the emitter we are
giving a signal and as I say that at the output, we are observing the signal either in
voltage or current mode. Now, to keep the collector node at high impedance we require a
good bias here. So, again this bias purpose of this bias it is to provide the DC current.
Now, these two conductance’s finite conductance’s, theoretically we are not looking for
it, but it may be coming from practical implementation. So, I should say ideally this is
good enough and this is good enough and then we are feeding the signal at the source
and then we are observing the output and the collector.
So, if you see the signal at the source I should not say source this emitter rather at the
emitter node if you see the voltage wise with respect to time what we are expecting is
that we are giving a signal like this. And this signal it is such that the voltage base to
emitter voltage it is not taking the transistor into a cutoff region. On the other hand
whenever we are applying the voltage at the emitter what we are expecting at the
collector node it is the signal coming. In fact, the signal it is coming in phase.
So, whenever the input it is rising the corresponding output here also it is rising. So, this
is the output and this is the corresponding input. So, why it is happening? Let us see if
the input at the emitter node the voltage it is rising keeping the base voltage constant DC
then vbe it is reducing. So, the collector current it is getting reduced. So, if the collector
current is getting reduced then drop across this resistance it will decrease. So, the voltage
it will increase.
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So, in terms of voltage if I see input to output voltage it is having a nice linear
relationship and most important thing is that they are in phase hopefully in voltage we
are getting a good amplification. In fact, later we will see that it is having very good gain
this common base configuration particularly in voltage mode of operation.
So, you may be excited by seeing this you may be thinking that then common base why
not it can be used as the voltage amplifier as a voltage amplifier. We will see its
limitation, but yes if we have idealistic situation yes, it can be used as voltage amplifier.
The major problem starts when you consider the finite source resistance Rs and then if I
consider input resistance of this circuit ok. I am just giving the hint of the main problem,
but anyway we will we are going to cover in detail later.
Now, similar thing it is happening for the common gate circuit. So, for common gate
again the we require these two biases current biases they are providing DC support and
the DC current support. And then we are feeding the signal at the source node of the
moss transistor gate node we are keeping at a DC voltage AC wise it is ground and at the
out the output we are collecting at the drain node.
So, since this is common. So, we call it is common gate. So, likewise here also since the
base it is common we call it is common base. So, here again if we feed the signal through
this DC decoupling capacitor at the source, the signal at the source it should be such that
the transistor should not enter into the cutoff region. So, assuming that condition is
getting satisfied the voltage here at the input node or at the source node it is having say
sinusoidal form like this and the corresponding output at the drain node.
So, we are expecting similar to BJT here also we are expecting amplified signal it will be
coming to the drain node why that is, because if the source voltage it is increased by
keeping the gate voltage at DC level the corresponding Vgs here it is dropping.
So, over this period Vgs it is getting reduced compared to it’s the DC condition. So, the
current flowing from drain to source, it is getting reduced and then the drop across this
resistance it is dropping. So, the voltage here since this DC voltage so, this DC voltage
and the voltage coming at the output which is Vdd minus this drop that is getting
increased.
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So, I should say that input to output they are in same phase. So, this is the output and
again similar to common base here the input to output we do get dissent gain voltage
gain it is in fact, it is much higher than 1. So, we will see the issues in case if the signal
source it is having finite source resistance Rs and if we consider input resistance of this
circuit us will see what kind of problem it will be there.
But for the time being let we consider the circuit it will be analyzed for voltage gain
input resistance and output resistance little bit about. So, this is the basic operation little
bit about biasing we can touch upon. So, in the next slide we will be discussing about the
biasing of the common base yeah.
So, biasing of the common base amplifier, here how do you practically make this bias.
Suppose you do have the BJT main BJT is here and here either we can put a put another
transistor say NPN transistor having a meaningful bias at its base.
So, based on the supply voltage here and then RB it produces a base current and then
after multiplying with β of this transistor we are getting the corresponding collector
current. So, this collector current it is working as emitter current of the main transistor
yeah. So, implementation of this circuit it is it may be like this.
In fact, this kind of arrangement it is good because output impedance of this circuit
looking into the collector of the second transistor here it is ro which is quite high. So, this
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is high. So, that gives us a good current source which we are looking for biasing this
transistor at the emitter. So, likewise at the collector side, either maybe we can put PNP
transistor with a meaningful bias here.
So, we can have Vdd here and then we can have another resistor there let me call this is
R2, RB2, RB1 here. So, this transistor again based on its base current and after multiplying
with its own β it provides the collector current, which is useful for this transistor main
transistor for the biasing at the collector terminal. So, ideally speaking, this kind of
biases is desirable, but even if we do not have for this bias circuit even if you have
simple bias. Simple bias in the sense instead of the active device, even if you have say
passive element that may be good enough even here also we can put a passive element
and in between we can have the corresponding main transistor.
So, I should say this is a simple biasing scheme of the common base circuit. Now, at the
base node on the other hand we are looking for a DC voltage here. So, to have a DC
voltage there we require appropriate potential divider which may generate a DC voltage
different from the main supply Vdd to some intermediate voltage. Based on this potential
division here let me call this is RA and RB we can generate a voltage here. So, this
voltage it is Vdd ( ). And then, Thevenin equivalent resistance of this bias circuit if I
consider this the bias circuit. So, if I call this is Thevenin equivalent resistance Rth from
the network analysis you may recall that Thevenin equivalent resistances is RA ⫽ RB.
Now, if we have some finite resistance here it is always better to take this node to AC
ground. So, we can simply put a DC decoupling capacitor or I should say it is a capacitor
which ensures that no signal it is practically no signal it is there. So, here also we can put
a capacitor here. So, similar kind of things we can do here also for the simple biasing
scheme. So, we can have RA and RB. So, whatever we do model wise, if we say that this
is R1 and this is R2. So, directly we can say that this resistance it is R2 and this is R1 and
this current is 0 this current is 0 for this simple biasing scheme.
On the other hand if we have said active biasing scheme namely this one. So, you may
say that this resistance it is r naught of this transistor say Q1 and or rather let me call this
is Q2 and no that will be confusing. So, let me call this is Q1 no problem Q1 then this is
Q2 and so here we may call this is ro1 that is the ro1 of this Q1. And this resistance is ro of
the second transistor and whatever the DC current we do have here without considering
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the early voltage whatever the DC current we do have that gives the nonzero value of
this IBIAS1. So, likewise this DC current it is giving us the IBIAS2 ok.
So, in summary we can we can see that and the practical circuit is given here that can be
translated into this idealistic situation. Whenever we will be talking about the numerical
examples, we will be discussing little more about how to decide the biasing and all. But
for the analysis point of view particularly to find input resistance and output resistance
and voltage gain and current gain, we may use this this biasing scheme simplistic or
model of the biasing scheme. And that may be good enough to get the information about
the characteristic of the common base amplifier.
So, similar to the common base we can have biasing scheme for common gate. And there
also will be having these three the terminal biasing arrangement and of course, after that
we can feed the signal here. The signal can be either in voltage form or current form. So,
that can be that will be discussed later.
So, the biasing scheme of the common gate on the other hand here we are having the
main transistor. So, we do have the main transistor and then at the source side we do
have. So, at the source terminal we need to have a bias here. So, we may say that we can
put a transistor here with a meaningful vgs of this transistor. So, that this with a DC
voltage meaningful DC voltage here this added transistor let me call this his M2. And
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then likewise at the drain side we can add b MOS transistor again here we need to have
meaningful DC voltage at the gate.
So, let me call this is M1 and then the output it is coming from here and then at the gate
of the main transistor we can have a bias DC bias here let you call this is RA and this is
RB. So, that the Vdd here it gives us a DC voltage here which is RB, ( ) and then
Thevenin equivalent resistors looking into this circuit it is RA ⫽ RB.
So, we may add a capacitor here to avoid the consequences of this finite resistance of the
bias here. And here the transistor-2 it provides the good biasing scheme here. So, the DC
current here without considering the lambda effect whatever the DC current we do have
that gives the IBIAS2 and then rds of this transistor rds2; it is giving us the corresponding
finite conductance of this bias circuit.
So, likewise M1; M1 it is giving us the; giving us the bias circuit here or the
corresponding DC current without considering lambda it is given this part. And then r ds
of transistor-1; it is giving this resistance or finite conductance.
So, that is the biasing scheme of the common gate. So, as I said that it while we will be
talking about numerical examples, we will be discussing about how to find the value of
these resistances and so, and so. In fact, you need to be careful here if the current flow
here and current flow here they are not properly matched, then there will be an adverse
consequences. So, we may have to pay very good attention, so that these two currents
they should be quote and unquote equal. And that can be maintained by considering the
individual transistors characteristic and whatever the corresponding voltage we do have
here.
So, matching of this I should say the source bias source terminal bias and drain terminal
bias is very important. On the other hand the simpler version of the biasing scheme
similar to BJT is also applicable here it has in fact, many a times depending on the
situation we may use simple resistor here. And likewise, the at the drain side we may put
simple resistor. Note that we may have different combination namely at the source node
we can have simple bias and at the collector we may have the active bias and vice versa.
So, we do have different possible combination of the biasing scheme.
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And so this resistor we may call this is R1 and this is R2. So, this R2 it is giving this
resistance R2 and this R1 it is given this resistance. And of course, if we have this passive
biasing then this current and this current they are they can be assumed 0.
So, whatever the biasing scheme we do have whether it is with active circuit or whether
it is passive bias that can be or may be combination of them that can be a model by this
schematic. So, for our circuit analysis small signal circuit analyses we may not be going
to you know the detail circuit here. Rather we may use this simplistic biasing scheme and
then will be going for the corresponding analysis.
Only thing is that you have to keep in mind that, we need to consider these two elements
either R1 or rds1 or R2 or rds2; we need to consider finite value of this elements in our
small signal analysis. So, let me take a short break and then, we will come back with a
small signal analysis.
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Prof. Pradip Mandal
Lecture – 50
Common Base and Common Gate Amplifiers: Analysis (Part B)
Yeah. So, welcome back after the short break. So, we are talking about the biasing of
Common Gate and Common Base circuits. Now we are going to discuss about the small
signal analysis.
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So, let me go to the corresponding circuit here yeah. So, we do have common base
circuit here. So, this is the common base amplifier and this is the corresponding small
signal equivalent circuit. For to save some time what I have done is that I have drawn
this circuit, but I will explain that what the things I have done are.
If we see here the bias circuit in the small signal equivalent circuit, we have dropped this
DC current and we consider only the resistance here R1. So, likewise here at the emitter
side, the DC current we have dropped and we have considered only this R2 here. Then
this is the small signal which is getting coupled through the capacitor. So, we simply
have shorted it, signal it is coming to the directly coming to the emitter and then at the
base, we do have DC voltage.
Even if it is having Thevenin equivalent resistance, we assume that that is getting

grounded by grounded by capacitor here. So, even if you are having source Thevenin
equivalent resistance that is ignored and the base terminal, it is grounded.
At the collector side we do have gmvbe that voltage dependent current source flowing
from collector to emitter terminal and then of course, we do have the ro. So, that is the
small signal equivalent circuit. Input we are giving at the emitter and output we are
observing at the collector. In this diagram we are showing that output it is voltage input
is also voltage. Now we are going to analyze these circuits step by step.
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So, by considering this small signal equivalent circuit, let us see what are the now what
are the conditions we are getting. First of all we do have vbe, base node it is grounded and
emitter it is having some signal and that signal is incidentally vin. So, we can say vbe is
essentially 0 ‒ ve. So, and ve it is same as vin. So, in fact, vin is ve.
So, we can say that vbe it is ‒ vin. So, this is the first thing we obtain. The next one it is if
you see at this node the collector node, we do have three current elements. One is one
current is flowing through this ro another current is flowing through on this device and
then also we do have a current flowing through this R1.
So, the current flowing through this R1 it is . So, , it is summation of these two
currents. So, if I consider this is the polarity of the positive direction of the current, then
this current it is and ve it is nothing, but vin. So, the current flow here it is .
On the other hand gmvbe which is now it is gm(‒ vin) and the current flow here it was from
collector to emitter. So, minus sign we can remove and then you can say that the current
flow it is in this direction and it is gmvin.
So, the second term here it is representing this ic current voltage dependent current
source. So, what we have it is this current, it is equal to summation of this two current.
So, by applying the applying KCL at the collector terminal collector node rather we
obtain this equation. So, if you rearrange this equation it is it is having vin and vout only.
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So, we can write the expression of vo in terms of vin. So, with the rearrangement property
rearrangement what we are getting here it is vo = vin ( ).
So, this relationship it is helping us to get the voltage gain expression. So, what we are
getting is that voltage gain of this circuit, it is ( ). In fact, you may
approximate that this 1 it is very small. So, we can simply say that this is gm(ro ⫽ R1) and
further to that if you recall the common emitter amplifier voltage gain, it is similar.
So, and its gain it was gm(ro ⫽ Rc) and Rc it is in fact, Rc and R1 it is in this circuit and
common emitter amplifier their synonym. So, for common emitter amplifier, the voltage
gain it was gm into this one, but of course, with a ‒ sign. So, that is the difference. So, we
can say that if we are if we can successfully feed the signal at the emitter in the voltage
form and if you observe the corresponding output at the collector in the voltage form.
Then the gain of the circuit it is same as whatever the gain we can get from common
emitter except of course, this minus sign which means, that here input and output they
are in same phase; in common emitter the input and output they are in outer phase.
In fact, if you see here if you closely look into this circuit, for common emitter we feed
this signal at the base and emitter it was grounded. So, whatever the vbe it was there it
was producing this active current it was flowing through this Rc and maybe ro in parallel
and it was producing the output voltage. So, here on the other hand for common base
configuration we are feeding the signal here and we are making it ground. So, that is the
only difference how we are feeding the signal whether it is at the base or at the emitter,
other part of the circuit it is identical. So, that is why it is giving us the same level of
voltage gain, but of course, the polarity of the input it was different opposite. So, that is
why here we do not have the ‒ sign.
So, that is about the voltage gain, but we need to be careful here. Here we have assumed
that there is no source resistance.
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And as a result we are saying that entire vin it is coming here and then R2 is not having
any role and then we are really not bothered about the input resistance and so on. But
practically if you see that if we consider source resistance signal source resistance and if
we look into the input resistance of this circuit, then we will be we will be getting a
surprise.
So, to get that surprise, let us look into the expression of the input impedance of the
circuit ok. So, to get the input impedance what we can say?
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If I stimulate the circuit by say vin and then if we observe the corresponding current here
say iin then if I take the ratio of that will be giving us the input resistance. So, if you
see that iin for a given stimulus of vin, it is having three components: one is this current,
another one is this current and the other part it is it is going together; finally, it is going
to that ground and then it is coming back to this ground.
So, the first part or this current of this iin it is . So, voltage at the emitter node we do
have vin here. So, naturally this current it is . So, likewise the second part it is . And
the other part whatever the current is flowing, it is same as whatever the current is
flowing through this R1 and incidentally this current it is .
So, that makes our analysis simple. So, the third part of the current it is and we
already obtained the expression of vo in terms of vin. So, this is the corresponding
expression. So, we can plug in that expression here and we can say that iin it is vin, it is a
function of vin multiplied by and then we do have this part the middle part and the
third part it is we need to consider which in my equation previous equation I have not
considered. So, we can consider this part also.
So, if I take the ratio of this vin and iin to get the input impedance of the circuit, what we
are getting here it is rπ coming in parallel with this impedance namely ( ) right and
then of course, we do have this R2. In fact, if you look into this circuit carefully the input
impedance is having three part; one is this conductance this conductance and the
conductance through the active device.
So, this is the rπ and this is the R2 and the middle portion if you see if you further
simplify, it is ( ). And if you further simplify it, you may say that this part in case if
it is dominating over R1 if I consider this is much higher than R1, then you may
approximate that this is . So, why I am writing like this, because to indicate that the
typical order of magnitude of this input resistance series .
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So, if it is coming in parallel with rπ and R2 this it will be dominating. Typical
value we already have seen before that this may be in the order of say 25 Ω and the on
the other hand rπ maybe in the kΩ. This resistance depending on what kind of biasing
arrangement we are considering here, this may be higher than kΩ. So, we may say that
input impedance it is quite low, it may be in 10s of Ω ok.
So, depending of course, it depends on the DC condition, but important note is that the
resistance is very small and whatever the if I consider the source resistance then this
input resistance and source resistance it will be making this voltage coming to the emitter
of the transistor very weak. So, we will see that what may be the consequence if I
consider source resistance of this circuit.
So, basically we like to say that this voltage gain it will not remain so, nice. In fact,
voltage gain from emitter to output it will be having the same expression, but from the
primary input to the emitter because of Rs and input resistance here there will be a big
attenuation. So, if I call this is vin followed by say resistance of the signal source Rs
followed by the Rin, Rin is the equivalent input resistance we or just now we have
derived.
So, if I see the signal here if the value of this Rs, it is much higher than Rin the signal here
it will be very small. So, as a result we have to consider another attenuating factor. So,
we will see its consequence. Before that let me consider the common gate configuration
because whatever the analysis we have done so far for the BJT version quiet and extent it
is applicable for the common gate amplifier.
So, let me go into the common gate configuration, yes.
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So, in our previous analysis namely for common base, we obtain this relationship vout to
vin and here we do have the common gate configuration. So, this is the main transistor,
signal we are feeding at the source through the capacitor, gate is biased at DC voltage
and then at the drain, we are observed in the corresponding output.
So, here we do have the small signal equivalent circuit. Again same thing, this bias
circuit we have dropped in the small signal equivalent circuit; similarly, this bias circuit
the bias current DC bias current, it is dropped and we are just keeping only R2 and R1
here. The small signal equivalent circuit of the mass transistor it is given here by gmvgs
that is the drain to source signal current and then we also have rds here. Of course, we do
not have rπ here and then voltage here from gate to source it is vgs.
So, instead of vbe in whatever we have seen for common base configuration, we do have
vgs and instead of ro we do have rds, rest of the things is similar. So, whatever the
previous circuits analysis we have done that can be utilized namely to get the voltage
gain of the common gate. So, for common gate configuration, the input to output gain it
is (gmrds instead of ro; I have to consider rds + 1) × ( ). Again this can be we will
approximated by ignoring this one part with respect to gmrds and it can be written as gm
(rds ⫽ R1).
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This is again, it is having the similar gain of common source amplifier where the
expression of the gain it was gm(rds ⫽ RD), but of course, with a ‒ sign here, we do not
have any ‒ sign here rather input and output they are in same phase. Now similar to the
voltage gain the expression of the input impedance of this circuit can be obtained from
the derivation of the common base circuit. So, this is the derivation, we already have out
of the common base circuit, of course, there we are having R2 also.
Now, if I consider common gate: so, common gate circuit configuration. There the input
resistance Rin which is defined by , where vin we are applying here and then the
corresponding current here it is we call this is iin. So, this current this ratio can be
obtained from the same analysis whatever you have done, except we have to make this is
in finite and we have to make this is rds. So, this is rds and this is also rds. So, that gives us
the input resistance expression, it is ( ) ⫽ R2 .
Again here we can we can approximate this input resistance by and even though this
of mass transistor and BJT they are having different order of magnitude, but still it
is quite low. So, since the input resistance it is low, the same problem it will arise if I
consider source resistance signal source resistance Rs and this voltage signal it will be
having difficulty to reach to the common source.
So, if I consider say this Rs here, what kind of voltage gain will you get? So, let us see
what will be the voltage gain if I am having this finite value of the source resistance.
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So, this is the corresponding circuit here the analysis it is very similar for common base
and common gate. So, let us start with the common base. So, this is a corresponding
circuit. We already have discussed this circuit before.
Now, if I consider along with that if I consider it is having a source resistance of Rs and
this circuit it is having input resistance looking into the source node Rin which is we
already have discussed that this is rπ ⫽ R2 ⫽ ( ). So, the attenuation coming from
this network namely this vin part of the vin it is arriving here and the signal coming here.
It is I should say vin ( ). And after that from this point to the output whatever the
gain we are having that remains the same and we know that the gain from source node to
collector node its gain it is given here. So, the overall gain from the primary input to the
primary output it will be this attenuation factor multiplied by this gain.
So, we can say that the overall gain , it is ( ) multiplied by this part, where
this is the Rin this is also Rin. Now it will be having a serious problem and we already
have discussed that this can be well approximated by . So, likewise this is also . And
if this Rs it is significantly large, then we will be having an attenuation here which is
right.
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So, that gives us. So, this is coming . So, there will be huge you know attenuation
depending on the condition if the Rs, yeah if the Rs it is sufficiently large then there will
be large amount of attenuation. As a result the voltage gain this circuit may not be (Refer
Time: 25:13) working as a voltage amplifier. In fact, this is true for the common gate
configuration as well.
So, even if I consider common gate the analysis it will be similar. Only difference is that
we will not be considering this part and then we have to consider we have to consider rds
instead of ro because for common gate this is rds and this is I should say it is infinite. So,
this is rds and so and so.
But the consequence or the overall conclusion remains the same, namely, this circuit
common gate also may not be a good idea to utilize as voltage amplifier ok. So, what
may be then the other alternative? Can I use this circuit as current mode amplifier? First
of all for current mode amplifier what we are looking for it is idealistically the input
resistance should be has small as possible, output resistance should be has high as
possible and we already have seen that this circuit is having input resistance quite low.
So, we already have this property.
Now, we can see that do we have this property. So, in the next slide we can see that,
what is the expression of the output resistance of this circuit.
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So, let us start with the common base configuration and in fact, the analysis it is similar
for common gate also and let you consider finite value of this Rs. So, we are keeping the
source resistance Rs and this is the corresponding small signal equivalent circuit of the
common base amplifier. To find the output resistance what we are doing here, it is we
are stimulating this circuit by a voltage called vy and then we are observing the
corresponding current iy.
And if I know their relationship, then from that if I take the ratio of this that gives us
the output resistance. So, the output resistance it is essentially . Now in this circuit if
you look it look at this circuit carefully, it can be simplified. Say this part it is a parallel
branch to ground whereas, this part it is another branch. So, whatever the resistance we
can get out of this lower part if you if you analyze this part and then if you find its
corresponding resistance and then that resistance if you simply make a parallel
connection of this R1 that gives us the overall resistance.
So, to simplify the analysis probably we can presently, let you drop this part and let me
analyze only this lower part. Further to that this R2, Rs and rπ all are connected to the
emitter node and the other part other end of those resistors are connected to ground. So,
all of them we can say that they are parallely getting connected and equivalently you can
say that from the emitter node we do have a resistance which is Rs ⫽ rπ ⫽ R2.
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So, in summary; if we drop this part and if we club all these three resistors into one then
the corresponding circuit it becomes very simple like this. So, let us analyze this circuit
and then let me consider this is our stimulus and this is the corresponding observation
and then from that whatever there be we will be getting we call this is a R′out.
Then the total resistance here of course, this will be this R′out in parallel with this ignored
part this one. So, let me do this analysis then finally, to write the expression of output
impedance, we will be considering this R1. So, in the next slide we will be analyzing this
circuit.
So, you do have the circuit copied here and this is rπ ⫽ Rs ⫽ R2.
Now, how do we find the relationship of this vy and iy? First of all the voltage here it is at
the emitter it is ve and the current here it was gmvbe and vbe it is essentially ‒ ve. So, we
have dropped the ‒ sign here and we have changed the polarity of the current here. So,
the current flowing from emitter to collector it is gmve and so, here if you see this current
iy it is probably, it is going through this part and this part and finally, it is coming back
here.
So, the current flowing through this total resistance here it is also same as whatever the iy
we do have. So, we can say that the voltage ve it is iy multiplied by this resistance. So,
the first equation we obtain here it is ve = iy × the total resistance; on the other hand if
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you see at this node and this node we do have the different. So, at this node if I apply say
KCL what we are getting here, it is iy it is summation of this current and this current.
So, the current here flowing through ro it is . So, that is this part and then the
current here it is in this direction from emitter to collector it is gmve or you may say that
collector to emitter it is ‒ gmve. So, the iy it is having this expression. So, what do you
have here it is iy it is written in terms of vy and ve, whereas, ve it is written here in terms
of iy. So, if I combine these two equations this equation in this equation what we get here
it is; vy = iy ro + iy × the total resistance here + iy × the total resistance × gmro.
So, if you see that various terms here in fact, the voltage vy if you see here it is having
this drop and also this drop. So, this drop it is straight forward. In fact, if you see here
this is the this part this drop and then if I combine this part and this part that gives us the
drop across this ro because this current is also flowing through this and this current it is
its expression it is gm into this resistance multiplied by this re.
So, that gives an idea that the voltage here it is having this iy multiplied by a big
resistance here. In other words if I take the ratio of what we can what we are getting
here it is having this resistance in series with this big resistance. In fact, compared to this
part it is very small it is rather I should say this is dominating. So, we may approximate
this by (rπ ⫽ Rs ⫽ R2) gmro.
So, if you observe carefully this Rs even if the Rs it is not very big, but whatever the
value it is there that is getting multiplied by gmro. So, even if I say that Rs it is not so, big
and whatever the value we do have since it is getting multiplied by gmro which is intrinsic
gain of the amplifier that gives the output resistance very high, at least from this part the
resistance is very high
So, now to get the output resistance we need to consider the other part, namely, R1 part.
So, that is what we are summarizing in the next slide.
708
So, what we have said is that we already got the expression of . So, it is having the
impedance coming from this part. So, that is the impedance it is given here and then we
do have R1. So, the output impedance of this circuit it is whole thing in parallel with R1.
So, I should say that this common base configuration. This portion it is having very high
resistance. Now if this bias circuit it is also having high resistance by implementing say
by active device then you can say that its output resistance is very high. Now whatever
the analysis we have done that can be utilized to get the output resistance or output
impedance of the common gate configuration also, namely, the mass counterpart and its
output resistance it will be obtained from this expression only by dropping these parts
and replacing this ro by rds.
So, I am just writing that R1. So, this is the output resistance of the common gate
configuration; R1 ⫽ {rds + (Rs ⫽ R2) + (Rs ⫽ R2) gmro} right. So, again the output
resistance here it is high. So, we are convinced that for common base or common gate
the output resistance is very high. So, let us see this circuit either common base or
common gate as current amplifier.
So, we do have the corresponding analysis to find the expression of the current gain.
709
So, here we do have the common base configuration. We do have the corresponding
circuit here and to get the current gain what we have to do? At the output node we have
to make their corresponding terminal unloaded. What do you mean by unloaded? We
have to basically short this node to ac ground and then we have to find how much the
current it is coming from the circuit signal current. We are putting this capacitor, so that
the operating point of the transistor it is not getting affected and at the same time signal
wise we are observing the short circuit output current.
And we know that if the signal it is in current form unloaded condition should be the
corresponding impedance or the terminating impedance should be 0. So, small signal
model if you see the corresponding situation here it is this node the corresponding
collector node it is ground and we are observing the corresponding signal current io, for
their input signal it is iin. In fact, in this case we are stimulating the circuit by signal
current.
Now if you see this circuit again the base node it is grounded, voltage at the emitter we
do have ve. So, the vbe it is vbe it is ‒ ve right and part of the current is also flowing here.
So, we can say that iin, it is having different component; one is this part another is this
part right and then we also have this current and this current.
So, the if you see one by one this current it is gmvbe. So, that is why gmve is the first part
and then the second part here flowing through rπ, it is voltage here . So, there is a
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second part and then we do have this part third part which is and then through this by a
circuit which is . So, in summary we can say that iin it is it can be directly written in
terms of ve.
On the other hand if you see the current at the output terminal here. So, if this is the
current. In fact, this current of course, this node it is grounded. So, the current here it is
actually 0 because this is also ground this is also ground. So, the current here it is 0. So,
the io on the other hand, it is summation of only these two currents we do have this
current and we do have this current. So, io it is ve×gm and then we do have .
So, if I take ratio of this two what we are getting here it is the v this is getting cancelled.
So, the current gain = . In fact, if you see because this gm it is
dominating we may consider rest of the things it is very small. In fact, you may call this
is practically it is . If you want you can probably keep this part or to be more precise it
is we may drop this part. So, we can write this part and we can write this part.
So, it will be . Of course, this R2 can be ignored, definitely it can be ignored with
respect to gm, but whether this is ignore able with respect to rπ, ro that depends on what
kind of biasing arrangement we do have for the emitter terminal. But, whatever it is or
we can write in this form and you can further simplify this as .
In fact, you may recall that is nothing but the β of the transistor. So, this ( ). In
fact, you may recall this is nothing but, α of the transistor that is very obvious. If I ignore
this resistance if I feed a signal current here at the emitter whatever the current will be
getting at the collector side, it depends on how much the current gain we do have from
for this transistor from emitter to collector and that is nothing, but the α of the transistor.
So, we know that this α it is very close to 1. So, we can say that this current gain it is less
than 1, but it is very close to 1. So, that gives us good you know conclusion that this
circuit namely the common base, since its input resistance is low output resistance is
high and the current gain it is it is close to 1. So, it is a good circuit for current mode
buffer.
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The similar kind of analysis it can be done for common gate also. I think you can do
yourself just by dropping this part for that for common gate we simply remove this part
and that gives us the corresponding current gain; = . In fact, for this case it
is if I if I ignore this R2 then it is exactly = 1 that is a very obvious. For BJT we do have
this path which is taking some part of the current, but for most we do not have the get to
source resistance.
So, as a result at the source whatever the current we give the entire current it is arriving
to the drain terminal. I think most of the things we have covered.
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So, what are the things we have covered today? It is we have discussed about the
common base and common gates amplifiers or configurations. It works as a buffer
particularly for current mode amplification. What we have covered today it is the basic
operation of these two configurations and we also have discussed a little bit about the
different biasing schemes. Numerical discussion it will be done later. And then we have
done full set of analysis of the small signal analysis of common base and common gate
configurations to find the gain particularly voltage gain, input impedance and output
impedance and also current gain. So, both voltage as well as the current gain, we have
discussed. Numerical examples on these two configurations will be covering later. I
think that all we need to cover.
Thank you.
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Prof. Pradip Mandal
Lecture – 51
Common Base and Common Gate Amplifiers (Contd.):
Numerical Examples (Part A)
Welcome to this NPTEL online certification course of Analog Electronic Circuits.

Myself Pradip Mandal from E & EC department of IIT Kharagpur. We are continuing
this course for quite some time and today’s topic of discussion it is Common Base
Common Gate Amplifiers. In fact, this is continuation of our previous lecture. So, we
already have discussed about the theoretical aspect, today we will go with more
Numerical Examples.
So, our plan is to cover the following items of this this topic. As I said that we already
have discussed about the motivation of going for this common base and common gate
configuration. We also have discussed about the basic operation and biasing of these two
configurations and also we have talked about small signal analysis for different
performance parameters, namely voltage gain input impedance, output impedance and
current gain.
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Today we will be covering number of numerical examples associated with these 2 basic
configurations and whatever the expression we have obtained in the previous class of
different parameters that will be extensively used here and we will get numerical value
of those parameters. And subsequently once you covered these numerical examples
which are associated with analysis of design circuit.
Once we are comfortable on this numerical examples, then we will be in a position to

discuss about what may be the design guidelines for a given requirement of the circuit
performance. So, today’s discussion here it is number of numerical examples and then
design guidelines of common base and common gate amplifiers.
So, let us go to the numerical example of common base amplifier. What we do have here
it is the basic circuit given here and you can see that we do have ideal bias as well as
more practical bias of the collector terminal. And also at the base node of this circuit we
do have a DC voltage along with Thevenin equivalent resistance of the DC source.
And since it is common base configuration and we want this base node should be AC
ground, to ensure that we are also connecting CB large capacitor there. Input port is at the
emitter and output port is at the collector terminal; input we are giving through a DC
decoupling capacitor. In this case in this example we are showing input signal in the
form of voltage and the signal source it is also having it is source resistance called RS.
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And here we do have different parameter values namely VBE(on) of the BJT it is
approximately 0.6, current gain β of the transistor it is 100. Early voltage of the BJT it is
taken 50 V and then base to emitter small signal capacitance Cπ it is 10 pF and on the
other hand base to collector capacitor Cµ it is having a value of 5 pF.
These are typical numbers and then also we do have the information about the supply
voltage 10 V and then base voltage DC voltage 6 V, thermal equivalent voltage VT it is
26 mV and then also we do have the load capacitance connected at the output node
which is 100 pF. Now, in this bias circuit we do have IBIAS which is given as 1 mA. So,
for the time being in this numerical examples we are considering this emitter bias it is
ideal. So, we do not have any associated conductance of this bias circuit, in later
examples we will be replacing this ideal bias by resistive bias.
And in this numerical example let we consider that the source resistance RS = 0 and also
the Thevenin equivalent resistance for the base bias RB, let we consider this is very
small. So, whether we do have CB or not we can consider that base terminal is AC
ground. At the collector terminal on the other hand we do have practical circuit RC and
let we consider it is value it is 3 kΩ. So, how do we find different performance matrices
of this circuit which are in listed here? Namely voltage gain, input impedance, output
impedance, input capacitance may be upper cutoff frequency of the amplifier. While we
are driving the signal in the form of voltage.
So, how do we proceed? We can start with the operating point of the transistor, to get the
operating point of the transistor we can do the DC analysis and then we will be going to
the calculation of small signal parameter of the transistors. Namely gm and then ro of the
transistor. So, let us let we target at this point and try to find the operating point of the
transistor. So, as I said let us try to find the operating point.
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If we see that this IB it is given as 1 mA and β is 100. So, we may approximate that
collector current IC = IE and which is same as 1 mA, so this is the DC current. And then
the voltage at the base it is given as 6 V and the emitter voltage here it can be obtained
by considering 6 V here and VBE all of 0.6 V.
So, we can say at the emitter node we do have 6 ‒ 0.6 that is 5.4 V. Now, if we have this
1 mA of current at the emitter, approximately the collector current is also said by that,
then the drop across this RC it is 3 k × 1 mA. So, that gives us this voltage it is VRC = 3
V, Vdd on the other hand it is 10 V.
So, the voltage coming at the DC voltage coming at the collector terminal it is 10 ‒ 3 so
that is 7 V. So, if we have 7 V here at the collector and at the base we do have 6 V, the
transistor it is in active region of operation. In fact, to consider this approximation it is
very important to ensure that the transistor it is in active region of operation. So, that is
how we obtained IC. So now, the operating point it is we obtained. In fact, we can find
what is the corresponding VCE voltage which is 7 ‒ 5.4 here.
So, anyway then we come to the calculation of small signal parameters. So, let we
consider small signal parameter calculation namely gm of the transistor which is
and it is given 26 mV. So, we can see this is ℧ and then the
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other parameter it is ro and it is expression is and early voltage it is given
here it is 50 V and IC it is 1 mA. So, that gives us ro = 50 kΩ.
And then rπ which it can be obtained by considering this gm and the value of the β given
here. So, this is can say this is 100 × 26. So, that gives us 2.6 kΩ. So, these are the
small signal parameters we obtain. Now, 3 using those parameters so we can find the
corresponding voltage gain. So, let us see how we do get the voltage gain. So, the
voltage gain starting from the emitter terminal to the collector terminal and if I call that
voltage gain it is AV.
You may recall from our previous days discussion it was ( ). In fact, if you do
if you compare and 1 definitely, we can approximate this by only. So, we
can drop this 1 and we can see that this is ( ), which is actually ro and RC in
parallel. So, the voltage gain now if I plug in this value of this gm and then ro and then RC
of 3 k. What we will get here? It is . So, this is k and this is .
So, I should see this is multiplied by 1000 that gives us a gain. So, this resistance if you
see this resistance let me write that part also separately. So, gm it is and this part it is
2.83 kΩ, in my previous calculation I already have done this one. So, that gives us the
gain which is equal to 100 roughly 100 to be more precise 108.85.
So, that gives us a very decent gain of this circuit. In fact, this this gain it is very close to
the gain of common emitter amplifier having the similar kind of bias level, so that is how
we obtain the voltage gains. Note that in this example we are considering that RS = 0. So,
whatever the input voltage you are applying here, even though this circuit is having very
low input resistance. This since this RS we are considering it is very very small, so we
can say that almost entire signal it is reaching to the emitter.
Assuming of course, this capacitor it is successfully allowing the signal to be coming to

the emitter. So, this gain it is the not only emitter to collector gain, but it is also
representing primary input to the primary output gain. Now, next thing is the input
impedance. So, let us look into the input impedance, let me use different color for that
hopefully I will be able to manage to write that expression here Rin, again you may
718
utilize the previous derivation. So, if I look into the emitter terminal what we have here it
is rπ that is the resistance from emitter to base and the base node it is AC ground.
So, that is coming in parallel with whatever the impedance we do have on out of this
entire circuit, let me use different color yes. So, we do have input resistance looking into
the emitter the input resistance it is expected to be ( ). So, I should say that this is
again it is dominating and not only that if you if you see the value of this ro which
is 50 k and then this RC it is only 3 k. So, we can approximate this by rπ ⫽ .
And again if I compare the value of this rπ and they are they are having a ratio of β.
So, further to that we can simplify or approximate the input resistance by . So, the
summary is that the input resistance of this circuit it is and that is 26 Ω. So, naturally
this input resistance is quite low. So, this input resistance as expected it is quite low 26
Ω.
In fact, if you consider this rπ and Rc also here, it may be slightly different but more or
less it is value it is quite low as low as 26 or 25 Ω. Now, next thing is that we can try to
find the output impedance. So, I think the board is really clumsy, so let me erase. But
you please make a note that gm it is , ro = 50 kΩ, rπ it is 2.6 kΩ.
719
So, we need to calculate the output impedance and as I said that gm = ℧, ro = 50 kΩ
and rπ = 2.6 kΩ. Now, looking at the at this point if I want to know what will be the
corresponding output resistance. So, that output resistance it is resistance of this RC this
path and then the other resistance coming from the active device in parallel. So, that is in
parallel with whatever the impedance will be seen.
Now, if I consider RS = 0 as we have discussed earlier. So, this emitter node it is getting
grounded and the impedance will be seeing here it is only ro. So, the net output resistance
it is RC ⫽ ro. Now, RC it is 3 k and ro it is 50 kΩ. So, earlier we already have calculated
this resistance while we are calculating the voltage gain and that is two point 2.83 kΩ, so
that is the output resistance.
Now, next thing is the Input capacitance. So, if we see the capacitance at this node for
this signal, of course this coupling signal coupling capacitor it is quite large. So,
whenever we are talking about input capacitance it is coming the emitter to whatever the
ground node AC ground node will be considering that is the net capacitance. Now,
emitter to base we do have Cπ and then also base to collector we do have Cµ coming out
of the device.
So, if we look into emitter and since the base node it is AC ground, whatever the input
capacitance we will see here it is only Cµ, Cπ. In fact, to be more precise if I consider this
is our primary input and if I call that this coupling capacitor signal coupling capacitor it
is C1. So, then the input capacitance strictly speaking it should be C1 in series with this
Cπ and whenever 2 capacitors in series their value it is .
Now, this C1 it is typically much higher than Cπ, as a result you can say that since this is
much higher than Cπ. So, you can approximate this by Cπ, so that gives us the input
capacitance. Now next thing is the upper cut off frequency of the circuit and since we are
dealing with the signal in the form of voltage. So, the upper cutoff frequency, of course it
is coming from the output resistance here and the corresponding CL here. So, ω upper
cutoff frequency it is .
So, you can find what may be the value of this one CL it is given here it is 100 pF and
Rout we already have calculated 2.83 kΩ. So, we can find the corresponding value here.
720
So, that is how whenever we do have the common base amplifier circuit, we can analyze
the circuit and as I said that end of this analysis what we obtain that the voltage gain it
was very good 108.8.
Input impedance it is low 26 Ω, output impedance it was it is different it is 2.83 kΩ and

input capacitance on the other hand it is low. So, I should say it is 10 pF only and Cµ it is
not having any effect on Cin. In fact, that is say a good sign if you compare this common
base and common emitter amplifier and if you recall for common emitter amplifiers
input capacitance it was Cπ + miller affected Cµ. So, which is (1 + AV)Cµ and if you have
significant amount of Cµ, since the voltage gain it is high for CE amplifier the input
capacitance it was quite large.
On the other hand for common base amplifier that C mu it is not having any contribution.
So, we can say that if I compare common emitter and common base in terms of input
capacitance common base amplifier it is better. And as what will be the consequence of
that the in case the upper cutoff frequency it is not only defined by the output node, if it
is also defined by the input pole namely if Cin and RS they are defining the upper cutoff
frequency, then we can see this advantage.
So, in this example since we are considering RS = 0 that is that is why the effect of the
Cin is not coming in the frequency response. But if we consider in general so the upper
cutoff frequency defined by RS and Cin, so that is the other candidate of the upper cutoff
frequency that may using this expression. And if we are having RS it can be easily
prominent that the common base circuit. Since it is input capacitance is low it is useful
for some high bandwidth application.
So, now the next thing what we have to see that, even though we have seen that the
voltage gain it is good, but input impedance is not so good. Now, if I compare again the
CE amplifier and CB, then and if I consider practical value of the source resistance
signal source resistance. Because of the input impedance is low we are expecting that
primary input to emitter node there will be large attenuation. Namely if I consider say
this is the input signal vin having a finite value of the source resistance followed by the
input impedance of the amplifier and since this Rin is small so we are expecting there will
be big attenuation.
721
So, in the next example numerical example what we will consider that RS instead of
considering 0 Ω, we will take some practical value rest of the things we will keep as it is.
And then we can see what will be it is consequence particularly on the voltage gain.
So yes, so this is this is what exactly what I was telling, that all the parameters here we
are taking same except the source resistance. So, we are considering the source resistance
it is 10 kΩ. No,w let us see what will be the corresponding voltage gain. So, the voltage
gain from this point to this point namely emitter to collector we already have seen that
voltage gain it is gm(ro ⫽ RC).
And then if I consider from this point to this point primary input to the emitter node it is
having attenuation and that attenuation it is . Now, this part we have calculated as
108.85 and then Rin we obtained this Rin it is only 26 Ω and then RS we are considering
10 k. So, it is 10026, so that gives a big attenuation.
So, the overall gain now with RS = 10 k it is quite small, I mean let me think I did some
calculation on that yes. So, this attenuation factor 108.85 getting multiplied by;
multiplied by this attenuation factor which is 0.0253. I think I am correct and then that
gives us the overall gain it is only 2.758 no surprise, there is a huge attenuation from here
to here of 0.025.
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So, the voltage gain in summary the voltage gains it is very bad particularly if I start
considering practical value of the source impedance. Of course, it depends on the source
impedance. But then even if you consider say 1 k which may be in the many of the
application, then also the this attenuation will be quite big. So, we need to be a little
careful here in I guess I am correct here 10 k. So, that is 26 yeah approximately you can
say that this is . So, that gives us no sorry I will take it back.
In fact, the attenuation it is even more and that is what I was wondering that why the
attenuation is only this much and that gives us very low gain. In fact, the gain it is less
than 1 ok, so it is just 0.27. So, naturally if we consider practical value of this source
resistance we can see the effect. In fact, if I consider RS it is a lower say RS = 1 kΩ, then
also this attenuation it will be quite significant and with this RS of 1 kΩ the overall
voltage gain it is 2.758 yeah. I think I have done this calculation for 1 k and now if it is
10 k the situation is really bad.
Now, what is the effect on the output impedance on the other hand, since we are
considering the finite resistance RS. So, I let me use different color to explain that, output
resistance if I see it is having 2 components one is RC and the resistors coming from the
active part. So, the resistance coming from this active part it is basically it is you may
recall if I call this is R′out, so that is the impedance of the active device. So, that is (rπ ⫽
RS) + ro + (gmro) (rπ ⫽ RS).
And in this case if I consider this 10 k and rπ it was 2.6 k. So, these two in parallel, again
I think I do have the calculation no I do not have that, but whatever it is this part this part
it is 2.6 × 10 k. So, that is , so that is . So, roughly we can say that this is 2 k.
And now if I consider ro which is you may recall this is 50 k and this part it is quite big
and that is gm which is and then we do have 50 k and then we do have roughly 2 k ok.
So, let me use this space here, this part is really becoming clumsy here. So, what we are
getting here it is 100 × 5000 and then we do have this is kilo; this is also kilo; this is Ω,
so × . So, roughly we can see this part and this part close to 4 which means that 4 MΩ
that is quite big; that is quite big. So, by having the source resistance we may get an
advantage that this resistance is quite large. But then overall resistance output resistance
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it is RC ⫽ Rout and R′out rather. So, though this R′out it is quite large of say 4 MΩ of
magnitude.
On the other hand RC it is only 3 kΩ. So, we can say that it is having hardly any
influence on the overall output resistance, because this 3 k it is quite small it is I should
say it is peanuts of that the 4 MΩ. So, the output resistance it is hardly getting affected
by this RS, but we need to be careful that that is mainly because this RC it is small. In
case if we have a have an implementation where this RC it also it is quite large, then only
we can see that output resistance of this entire circuit it is highly dependent on this RS ok.
So, this is the other example, now also the other thing probably we can we can do the we
can observe that output input capacitance and upper cut off frequency. Hardly is it in
particularly input capacitance it is not getting changed, but then output I should not say
output the overall upper cutoff frequency it depends on the RS. So, let me clear this board
and then again rewrite with different color.
What we like to say that input capacitance Cin it is Cπ and this is 10 pF and then this RS
and whatever the capacitance we do have here the other end of this capacitance it is AC
ground.
So, we can say that from primary input to this point we do have one RC circuit defined
by Cin and this RS. So, one candidate of the upper cutoff frequency coming from this RS,
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let me call this is ω′U is and this is one divided by 104 and Cin it is 10 to the power.
So, this is pF, 10 pF so this is ‒ 11. So, that gives us ‒ 7 here, so this = 107 rad/sec.
On the other hand, the upper cutoff frequency defined by the Rout and CL and let me
denote this by ωU which = and Rout it is dominated by RC. So, that is 3 kΩ, 3 × 103
and then we do have the 100 pF, so that is 10‒10. So, that gives us here again 10‒7. So, in
the numerator it becomes so yeah so I should say Mrad/sec and this is 10 Mrad/sec.
Now, incidentally in this numerical example still this is higher than this one. So, I should
say ωU will define the overall upper cutoff frequency, but we need to be careful that RS if
it is higher and higher then this may also create the bandwidth limitation. So, the bottom
line here it is rather I should say the information other way, even though RS it is say 10
kΩ.
Since the input capacitance it is remaining low unlike common emitter amplifier, where
the input capacitance it is large. Since this input capacitance for this circuit it is
remaining low, this upper cutoff frequency it is still going beyond the other candidate of
the upper cutoff frequency here. So, I should say the common base amplifier it is helping
to design relatively wideband amplifier.
So, later we will see that how this information can be utilized. Now, similar kind of
analysis can be done for the most counterparts, namely the common gate amplifier.
Before we go into that let we take a short break and then we will come back to analyze
the common gate amplifier.
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Prof. Pradip Mandal
Lecture – 52
Common Base and Common Gate
Amplifiers (Contd.): Numerical Examples (Part B)
Welcome back after the short break. What we are discussing is Common Base Amplifier
and we will be going for Common Gate amplifier, but before going I have another
example based on the common base where we are talking about practical circuit of this
base bias. Instead of having you know ideal separate voltage source here along with the
Thevenin equivalent resistance RB, practical circuit wise we may have only one supply
voltage and from that we need to generate whatever the voltage we like to generate here.
So, we can have a potential divider constructed by say RA and RB connected to ground
which generates the voltage here and also we may have a situation that instead of having
this ideal current source, we may have some practical component either active device or
passive bias circuit. So, in our next example what we will be concentrating on it is
common base amplifier, but then with more practical bias arrangement.
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So, in the next slide we have the example, here as I said that the voltage for the base we
are generating in this base voltage by Vdd and then the potential divider constructed by
RA and RB and the value of RA and RB are given here. The other information about the
BJT as well as the other parameters are remaining same which are enlisted here the RC
intentionally we are making slightly different value or I should say we have made some
change here and at the emitter instead of having ideal bias, we have RE and its value is
given here close to 10 kΩ. In fact, we are considering 10.3 kΩ so that with a β of 100,
we can get the emitter current or rather collector current very close to 0.5 mA.
And also, we are considering the signal source resistance of 10 kΩ. So, the effect of this
resistance we already have discussed, in this numerical example primarily what you are
focusing on as I said that we have practical bias circuit and in case if we have practical
bias circuit using that how do I find the operating point of the transistor.
Let us try to see the operating point of the transistor by considering RA, RB, and so on.
Now, in this case Vdd also I have changed. So, instead of 10 V it is 12 V and RA and RB
both are 100 kΩ. So, we can say the voltage source coming to the base is 6 V. So, this 6
V is Thevenin equivalent voltage in series with Thevenin equivalent resistance which is
RA ⫽ RB incidentally that is 50 kΩ and then it is going to the base of the BJT.
And then at the emitter DC wise we have RE here and it is 10.306 kΩ and the current
flow. So, we are expecting that there will be a current flow and let me call this current is
727
IB and if the transistor here it is in active region of operation this IB current produces a
current here which is (1 + β)‧IB. Now, base to emitter node we do have VBE(on) of 0.6 V.
So, if I redraw the circuit considering base to emitter voltage.
Then we have 6 V Thevenin equivalent voltage source, 50 kΩ resistance coming from

RA and RB in parallel and then we do have a drop of 0.6 base to emitter voltage and then
we have this current flowing through RE which is 100.306 kΩ and the current flow here
is IB whereas, this current flow since we have the collector current which is β‧IB. So, we
can say this current is (1 + β)‧IB. So, if I consider this loop and if I see the potential drop,
6 ‒ 0.6 = IB × 50 k + 101IB × 10.306 k. So, that gives us IB = .
And that gives us close to 4.95 µA of base current. Now, if we multiply this base current
with β, we can get the collector current and the emitter current is of course, (1 + β)‧IB.
So, that gives us very close to 0.5 mA. In fact, for simplicity collector current also we
can consider this is same as the emitter current. So, we got 0.5 mA current flowing here.
So, the drop across this RC it is 6 kΩ and 0.5. So, that gives us voltage drop across this
RC, VRC it is 3 V and then the collector voltage it is 12 ‒ 3 V. So, that is we have 9 V.
And the voltage coming at the base of course there will be base current flowing here. So,
it is not just entire 6 V it is coming here. In fact, I should consider this drop also and this
current it is as you have seen it is very small close to 5 µA. So, 5 µA × 50 k. So, the drop
across this resistance it is 50 k × (5 close to 4.95). We can say approximately 5 µA, 10‒6.
So, this is 250 × 10‒3 or we can say that this voltage it is 0.25 V. So, the voltage coming
here it is 6 V ‒ 0.25 V. So, the voltage DC voltage coming here it is 5.75 V.
That ensures that device it is in actively general of operation and of course the voltage
coming here it is 5.75 ‒ 0.6. So, that is 5.15 V that is how we can get the operating point
of the transistor. Now, once you obtain the operating point of the transistor, then again
we can go for calculating the value of the small signal parameters namely gm.
728
So, small signal parameters gm = . So, this is = ℧ and then ro it is .
So, this is = 100 kΩ and rπ is = 5.2 kΩ. Once we obtain these small signal
parameters, then rest of the things yourself can do namely you can calculate what will be
the input impedance and so. So, those things I will not be repeating.
The next thing we are going to talk about the output swing on the circuit and as we have
discussed that the supply voltage is 12 V and RA and RB both are equal to 100 kΩ. So,
that gives us the Thevenin equivalent voltage. At the base node it is 6 V and the
Thevenin equivalent resistance is 50 kΩ. Now, the base terminal current of 5 µA as we
have discussed before.
729
So, if we consider the IR drop with respect to Thevenin equivalent voltage, so, at the
base terminal the DC voltage is coming 5.75 V. On the other hand, the collector current
is 0.5 mA. The RC value it is 6 kΩ. So, the drop across this 6 kΩ it is 3 V. So, that gives
us the DC voltage at the output node which is equal to 12 V ‒ 3 V, so that is 9 V.
So, we have the DC voltage, at output node is 9 V and at the base is 5.75 V. So, while we
have the signal riding at the collector terminal. So, with respect to 9 V the instantaneous
collector voltage it can go as low as 5.75 before this base collector junction it is getting
forward bias. That means, the device coming out of the saturation region.
In fact, we can have this junction weakly forward bias by an amount of roughly 0.3 V.
So, we can say that the collector voltage it can go even lower than 5.75 V by an amount
of 0.3 V. So, the amount of signal swing we can have we can tolerate here is 9 V is the
DC minus 5.75 V minus little forward bias we can tolerate it is 0.3 V.
So, that gives us 9 V ‒ 5.45 V = 3.55 V. So, this is output signal swing in the negative
side. So, this is the possible output swing in the negative side till the transistor it is
entering into saturation region. On the other hand, if we consider the positive swing, now
we consider output swing in the positive direction. So, with respect to 9 V here; the
voltage here it can go as high as 12 V.
Even though we know that there, will be significant amount of distortion because of the
exponential IV characteristic of the BJT, but let you consider that is the limiting
situation. So, the corresponding positive swing = 12 V ‒ 9 V = 3 V. Of course, once you
consider the input signal it is sinusoidal. So, we have to consider minimum of these two.
Finally, we can conclude that the signal swing of say sinusoidal signal it can tolerate.
Coming to other aspect that the input impedance of this circuit is expected to be low. If
the source resistance is significant, then the input signal will be experiencing significant
amount of attenuation. In fact, in practical purposes when we consider RS in the range of
kilo ohms or say 10 kΩ, it will be having significant large amount of attenuation. So,
instead of considering the circuit in the form of feeding the signal in the form of voltage
in practical purposes we consider let the signal be feed into the input terminal in the form
of current. So, in other words typically common base amplifier we want to consider as
current amplifier. So, the next item we need to discuss is the current gain of this
amplifier.
730
First of all on the stimulus part we need to replace current source. Signal current source
is iin and it may be having a finite conductance and this is conductance is . Now, this
signal it is going here and again through this capacitor the signal is arriving to the emitter
node. Now, once we have this iin we are feeding at the emitter node and then we like to
see how much the current we will be getting here particularly in unloaded condition.
For unloaded condition we mean that, we have to basically short it to the AC ground and
while we have this iin current what is the corresponding produced output short circuit
current. So, for this current gain you may recall that the current gain is very close to 1. If
I say that we are shorting this node here; the corresponding vo = 0. And if you recall the
small signal model here, we have this ro we have gm × vb and vbe it is ‒ ve and its ‒ sign
can be taken out. So, the small signal model of this circuit can be written like this and
then the output node it is shorted and we are observing the corresponding output current.
At this node we have the signal iin, assuming this part is zero conductance. So, we can
say that iin is entirely flowing through a voltage of ve then we have RE part, also we have
the rπ part and other terminal of the rπ is connected to ground. So, the current flowing
through this RE and rπ can be directly obtained by considering this or and so. So,
whatever we have done in the previous discussion that iin is , and then this divided
by ro and also multiplied by gm. So, on the other hand io it is and gm. So, from that we
731
obtain the current gain AI = . If I consider these two equations what you are getting
here it is 1. So, gm + divided by in the denominator gm + + and then .
Now we can compare each of these terms and you may recall the value of gm; gm is ℧
and rπ is 5.2 kΩ and RE is 10 kΩ. So, 10 kΩ and then we have ro is 100 kΩ. So, by
considering all these practical values of different parameters naturally you may say this
gm will be dominating over in the denominator also this gm will be dominating. So, we
can directly say that this current gain is very close to 1. If you want them to get better
approximation probably you can retain this part and then you can find what will be the
value instead of 1 to be more precise, it will be then ( ). In fact, this is α which means
that if we have this iin it entering at the emitter, the corresponding available current at the
collector it will be α times of this transistor.
So; obviously, this α is very close to 1 depending on the value of the β though
mathematically it is less than 1, but as I said it is very close to 1. This completes the
analysis of the common base amplifier. Now similar kind of analysis can be done for
common gate amplifier. But I must say that for common gate circuit we can consider
ideal bias and we already have done this exercise for common base. So, instead of going
with the ideal bias and then going for the practical circuit, I prefer directly go into a
numerical example where we will be having this kind of biasing arrangement.
732
In the next slide, we have common gate amplifier having be practical bias arrangement.
Now; obviously, finding the operating point of the MOS transistor is slightly different
from BJT and that may be one important exercise we must try to do with this.
Now, we have the different component values are given here namely RA and RB same as
the previous case. So, we can say at the gate node we have 6 V getting generated by this
RA and RB from this 12 V, supply Vdd supply.
So, we have 6 V here and then that is coming in series with the Thevenin equivalent
resistance of RA ⫽ RB which is 50 k. And then, we have the MOS transistor and then we
have RE, I should not say RE, I should say rather different resistance and it is its value it
is 4 kΩ. Now, how do I find the value of IDS from this circuit?
What we can do it is we can make use of the parameter of the device assuming the
transistor is in saturation region. So, if I say that IDS current is flowing and that is
creating a drop here at the gate of course, the current is 0. So, we can say that the 6 V it
is directly coming here. So, VG is 6 V and source voltage it is such that VGS it is
supporting the required current here which is exactly producing this IR drop.
So, we can say that this 6 V ‒ this 4 k × IDS that produces the VGS. So, if I say that IDS
equals to into VGS and VGS is 6 V ‒ Vth of 1 V ‒ this IR drop which is 4 k into IDS
and its square. So, here we do have IDS = 1. So, this part it is . So, that is 10‒3 into
this is 5 V, (5 ‒ 4 k × IDS)2.
Now, we have second order equation and if you solve this second order equation what
we will be getting here it is IDS will be having two values one of them it is the actual one,
other one it is hypothetical one and the correct one you will be getting is 1 mA.
So, we do have this part it is 4 k × IDS. So, we can say this parameter if I multiply here
what I will be getting here it is 4 k, 4 × 103 × IDS = 4 × 103 × 10‒3 × (5 ‒ 4 ×103 × IDS)2.
So, that gives us say this part and we like to calculate this IDS and let you consider this is
equal to x. So, from that you can get an equation which is 4 x2 ‒ 41 x + 100 = 0.
So, from that you can get the value of x and once you get this x you can find the
corresponding value of IDS and one of them it is this IDS. In fact, you will be getting
733
another IDS solution here which is in practical namely that will make this source voltage
it is higher than the required voltage here pushing this transistor into cut off.
So, that solution you can ignore and you can retain this 1 mA of current. In fact, you can
verify this one say if we have 1 mA of current flowing here, the drop here it is 4 V. So, if
I am having 1 mA of current the voltage coming at the source it is 4V, here at the gate
we do have 6 V. So, the VGS is 2 V. So, VGS ‒ Vth is 1 V. So, that gives us IDS = 1 mA.
So, how you can get the IDS and then the drop across this R1 it is 3 kΩ × 1 mA. So, that
gives 3 V here ensuring that this transistor is in saturation region of operation and hence
this circuit is in good condition to amplify the signal.
So, end of it what do you obtain? Here it is IDS = 1 mA and different VDS and the VGS.
We obtain the operating point using that we let us calculate the small signal parameter.
So, IDS as I said equals to 1 mA and hence gm of the transistor which is having an
expression of √ . So, that gives us gm = 2 m/V. The other parameter we are looking
for it is rds small signal parameter rds and this rds it is and λ it is given here it is 0.01
V‒1. So, this is 0.01 × 1 mA. So, that gives us rds = 100 kΩ.
So, we obtain the small signal parameters and then we can proceed for the voltage gain.
So, the voltage gain Av = gm (R1 ⫽ rds). And gm is 2 mA/V and R1 it is 3 k ⫽ 100 k. So,
734
this gives us this is 2 mA/V × 2.91 kΩ. So, that gives us overall gain is 5.82. So, you can
see that the gain here it is very small compared to the common emitter amplifier. This is
expected mainly because value of the gm for MOS transistor it is quite low. So, even
though this R1 and rds in parallel it is having significant amount of resistance, but because
of smaller value of this gm the voltage gain it is quite low.
So, even without considering this RS we have this problem. Now, if I consider this RS.
The gain of course, from source node to drain node. Now, if I want to know what will be
the voltage gain from the primary input to the primary output after considering this RS =
10 kΩ, then we need to calculate what will be the corresponding input impedance. So,
the input impedance of this circuit of course, it is getting dominated by .
So, the Rin is you can well approximate by ⫽ R2 and this gm we already have obtained.
So, that is is 0.5 k ⫽ R2 is 4 k. That gives us 0.444 kΩ. So, the input resistance of this
circuit is not as low as common base circuit where gm it was much higher, but still this
resistance is much lower and if I consider source resistance of say 10 kΩ that further
degrades the signal from primary input to the source node.
If I say overall gain Av-overall. So, that is Av multiplied by this attenuation offered by Rin
and this RS; RS is 10 kΩ. So, that is RS + Rin and this attenuation; Av we already obtained
is 5.82 and then this attenuation it is . And it becomes 0.24. So, what you can see
the gain is much lower than 1. So, this is primarily because this circuit it is having low
gain from here to here. In addition to that, the input resistance is low and we are
considering a practical source resistance that further attenuates the signal before going to
the source node.
So, I should say that the voltage gain is low and the input resistance now we already
have calculated, output impedance it can be calculated in the similar way we already
have done. Input capacitance of this circuit it is similar to the common base namely input
capacitance is Cgs and from that we can say that the we can calculate the upper cut off
frequency define by RS and input capacitance.
So, those things I will not be repeating but I must say about this output swing what we
said here it is the gate voltage is 6 V and the voltage at the drain is 12 V these 3 V drop.
735
So, that is 9 V. So, the DC voltage at the at the drain node is 9 Vand Vth is 1 V. So, this
voltage it can go as low as 6 ‒ 1 that means, it can go to 5 V. So, with respect to 9 V DC
the corresponding swing towards the ‒ve side is 9 V ‒ 5 V that is 4 V. So, we can say
that the ‒ve swing it is a 4 V.
So, what we said here it is 9 V DC, voltage here it is 6 V. So, at the output node we do
have the 9 V here and the voltage here it is 6 V. So, we can have the signal swing like
this, if this is 6 V it can go as low as up to 5 V because threshold voltage is 1 V. So, the
swings here signal swing we can get here it is 9 V ‒ 5 V. So, that is the 4 V ‒ve side.
On the other hand +ve side it can go as high as 12 V theoretically, but of course, the
corresponding signal may get distorted like this. So, the corresponding swings on the +ve
side; however, it is 3 V. So, anyway for this design that is what the operating point and
that is a corresponding signal swing. This information it will be useful whenever we are
going to design a circuit so, that we will be discussing later. Now, next item it is the
current gain of this circuit.
Current gain for this circuit will be . And R2 is we already have discussed is 4 k
and this is definitely quite small compared to the gm. So, again here we can approximate
this by this gm it is getting dominated.
736
So, we can say that the corresponding current gain is approximately 1. In fact, if you
ignored this resistance whatever the current it is entering signal current is entered into the
source, the same current is flowing here approximately. So, that is an indication that the
circuit current gain it is common gate amplifier current gain it is close to 1.
So, that completes the numerical examples whatever thing we have planned, based on
this information. Probably I will cover this one in the next class because if I start
explaining it maybe it will take more time. So, what we have to cover here this numerical
example and in this numerical example. So, in this numerical example what is the
important point here it is in case if we are not using the CB what kind of affect it may
come and this is important for common base amplifier. So, this numerical example it will
take some time. So, let me come back on this example after break.
737
Prof. Pradip Mandal
Lecture – 53
Common Base and Common Gate Amplifiers (Contd.): Numerical Examples (Part
C)
So, dear students welcome back after the break. And before the break we are discussing
about Common Base amplifier and Common Gate Amplifier.
738
So, this is the example of that common base amplifier. In fact, we are covering the
numerical examples and we already have discussed this circuit.
So, likewise we also have discussed common gate amplifier. So, here we do have the
common gate amplifier. And next to this common gate amplifier what we are looking for
it is; we are you might have observed that at the gate we are connecting one capacitor
CG. In fact, if you see the previous circuit.
So, they are also you can see that in common base amplifier in common base amplifier
here also we do have the CB that makes the base node AC ground and with that
assumption we have done the analysis. Now it is very important to keep this capacitor
sufficiently large so, that the base node particularly for the signal it should be working as
a ground. And this is important specifically for common base in fact, this is also
important for common gate.
But it seems the discussion it will be similar, here we are going to talk about
performance of the common base amplifier without this CB without the CB.
739
So, in our next example numerical example that is what we are going to do and we will
see that what are the performance degradations are happening due to eliminating this
capacitor.
So, we can see that the base node we do not have any capacitor and rest of the things it is
very similar to whatever the numerical example we have discuss before. So, you may
recall the voltage gain if we have the CB connected. So, if I say the expression of the
voltage gain with CB it has been enlisted here.
So, this is the voltage gain from the emitter node to collector node and this is the
expression of the input resistance of the main circuit looking into the emitter terminal. In
fact, if you consider RE we should also consider RE coming in parallel, but what is most
important thing is that the main device the we do have the rπ and then we do have the
input impedance coming from the active circuit so, that is it is given here and yeah.
So, that is a small notation correction instead of R1 we should write RC here. So, same
thing this is RC this is RC rest of the things are ok. So, this was this was the expression
whenever we are connecting the CB. Now if I remove the CB what will be the
consequences on these two important parameters namely the input resistance and the
voltage gain and maybe the output impedance also so, that is what we are going to
discuss now.
740
Now let me draw the small signal equivalent circuit, small signal equivalent circuit of
the main amplifier, try to explain that what kind of effects are there.
So, this is RC connected to AC ground. So, this is RC this is also RC this is also RC and
here we do have gmvbe voltage dependent current source and then of course, you do have
the ro and then we do have the RE connected to ground.
And at the emitter node we are feeding the signal through the signal coupling capacitor
and let we have its source resistance is also there see RS. Now what is the so, this
equivalent circuit we already have discussed. In fact, we will also have discussed that the
voltage across this rπ it is vbe. So, this is + and this is ‒.
Now earlier this node it was a c ground but if you look into this circuit we do have RA
and RB they are together namely parallel connection of RA and RB they are forming the
terminal equivalent resistance and for the small signal what we have to do? We have to
consider this RA ⫽ RB. But then definition of the vbe still it is the voltage across this rπ.
Now as I said that if we are considering CB then we do have this expression.
And if you see here the basic difference here the vbe, vbe it is not same as whatever the
emitter voltage we are having. In fact, earlier in presents of CB the emitter voltage it was
same as ‒ vbe. On the other hand the vbe it is of course, it is the function of this emitter
voltage namely vbe = ‒ ve ( ).

⫽
741
In fact, if you if you look at look at this circuit carefully if we have ve here and the
voltage available across this rπ it is nothing, but the potential division of whatever the
emitter voltage you do have. And due to whatever the gmvbe we do have, this part can be
replaced by gm ( ) and then of course, we do have the emitter voltage ve with a

⫽
‒ sign. Earlier whenever we are having a capacitor at this node, we have considered this
RA ⫽ RB it was 0 and then we have considered this current it was ‒ gmve which means ok.
So, this is the output voltage which means that whatever the derivation we do have in
this derivation if we replace this gm if we replace this gm by see gm ( ⫽

), then this
equation itself it can give the voltage gain and same thing for the input resistance also if
we replace this gm by this part namely gm ( ).

⫽
So, if we replace this gm by this equivalent gm, then we can get the expiration on the both
input resistance, then voltage gain and then the output impedance also. So, if we if we
recall see ok. So, let me let me try to erase this board and try to plug in this expression in
the expression of to get the affected voltage gain.
742
So, what we said is this gm will be replacing by ( ). So, from that we can say
⫽
that input resistance Rin if I ignore RE and if I consider . So, directly we can use this
equation and we can see that this is rπ ⫽ R1 is basically RC. So, ( ).

⫽
And also you can see whenever we consider input resistance earlier we are having rπ here
and the base node it was connect to AC ground and that is why we are taking this rπ. So,
now, this rπ instead of rπ we should also replace this rπ by this rπ in series with (RA ⫽ RB).
So, if I replace this replace this rπ by this and then we can get the input resistance. And of
course, this input resistance it does not consider it is not considering this RE. So, if you
consider the effect of RE then both this part this part should be coming in parallel with
R E.
So, the summary is that this input resistance it is getting modified here and also we do
have this RE. Now so, likewise the voltage gain. So, we will see the voltage gain and
since we do have this numerical example, let us try to calculate what is the input
resistance we are getting by considering the value of the gmro and then RC and so, and.
So, you may recall for this circuit whatever the conditions we do have collector current
IC it was 0.5 mA.
And then the gm it is . So, that is more and also the rπ which
is β times . So, if I use this value of the gm we can get rπ = 5.2 kΩ. So, likewise the
other parameters see ro which is . So, the early voltage here it is 50, IC it is 0.5
mA. So, that gives us ro = 100 kΩ and then RA and RB they are 100 k. So, we can say that
RA ⫽ RB so, that is becoming 50 k, 50 kΩ.
Now, if I consider the middle term particularly this term and if you see the corresponding
numerical value. So, what we have here it is RC = 6 k and then ro it is 100 k. So, we do
have in the numerator we do have 106 k, 103 and then in the denominator we do have
gmrπ that is nothing, but β. So, that is 100 multiplied by this ro which is 100 k. So, 105
and in the denominator we do have rπ is 5.2 k and then we do have 50 here.
So, this means that this is 55.2 k plus 1. In fact, you may ignore this one part and then
you can consider only the first part here. So, this is 105. So in fact, I did I have done this
743
calculation. So, let me share you this information. So, we do have this part it is 0.582 kΩ.
So, this part is 0.582 kΩ and then this part after making this replacement we do have 50
and then 5.2. So, that is 55.2 kΩ and then RE it is 10.
So, this one is 10 kΩ. So, we do have this resistance, we do have let me use different
color, we do have 55.2 k here and then we do have 0.582 k here and then RE it is 10 k.
So, finally, what we are getting here it is Rin very close to this 580. In fact, again here
also I have done the calculation for you.
So, this is 0.545 kΩ. So, what is what the outcome here is? If we are not using this CB,
then the input resistance it is quite large now compare to of course, compare to if I use
CB. So, with CB the input resistance Rin it was and that is 52 Ω only. So, if you
compare this one and this value it is almost 10 order. So, it is it is it is getting increased
by a factor of 10.
So, intuitively what it is happening here it is whatever the stimulus you are putting here
voltage only part of the voltage it is appearing across this rπ and major part it is appearing
across RA ⫽ RB. So, if you see the potential division it is happening here and that voltage
it is coming to gmvbe part.
So if you see the potential division we do have here it is rπ = 5.2 k and these two
resistances is together it is 50 k. So, now, it is very obvious that whatever the stimulus
we are putting voltage wise only one tenth it is coming here. So, that gives you an
intuition that the equivalent gm or equivalent input impedance coming from it is
getting changed by a factor of 10.
So, that is how the input resistance it is getting increase. So, the bottom line here it is
even otherwise it is not mention explicitly, we have to keep in mind that at the base node
we should ensure that this is signal wise this is AC ground. So, unless otherwise you do
have a special requirement we must use the CB. In fact, similar kind of conclusion you
can get for the voltage gain also. So, in the next slide let me consider the voltage gain
also.
744
So, here again the if I want to know what will be the affected voltage gain. So, we do
have we do have the affected voltage gain. So, what we can get? In fact, directly we can
use this equation only thing is that we have to replace this gm. So, let me call this is A′v
and the gm if you replace by then we do have + 1 and then R1 is essentially RC.
⫽
So, we can put this RC here and then here we do have RC + ro. So, again here if you put
the numerical value of different parameters. So, what we have here it is . So, that is
β that is 100. So, that is 100 and then we do have ro which is 100 k, 105 and then we do
have ⫽ .
So, that is 55.2 kΩ, 103 and probably we can ignore this one part, then in the
denominator we do have 106 kΩ coming from ro and RC. So, 106 × 103 and then we do
have the RC here and RC it is 6 k, 6 ×103.
So, that gives you a voltage gain in fact, you can calculate this one that gives you a
voltage gain around ten point something. In fact, I again for this also I have done the
calculation for you so in fact, in my calculation it was 10.31. Now of course, this voltage
gain it is from this point to this point. So, without considering RS that is the gain and of
course, if you consider the effect of RS from here to here we have to consider attenuation.
But also you have to keep in mind that attenuation factor it will be getting change
because the input resistance it is not just . But whatever it is the gain of the common
745
base amplifier from emitter to collector it is 10.31 if you recall the corresponding value
of this gain with CB it was 108.
So, if you compare again this and this almost it is a factor of 10. Again this factor of 10 it
is coming due to whatever the voltage you are applying at the emitter almost only one
tenth it is appearing across base to emitter terminal which means that we do have a
reduced version of the voltage appearing from base to emitter which is finally, getting
amplified by this. So, you can almost say that this factor it is getting one tenth and that
gives us the gain of close to 10.
So, that is how intuitively we can get. In fact, again the conclusion is that we should keep
this CB whenever it is possible. So, similar to the input resistance and voltage gain the
output resistance it is also getting affected because the resistance is the emitter it is
getting changed if we remove this CB.
So, yeah so, this is the slide to get the corresponding derivation of the Rout and the output
impedance for this circuit it is this RC I should write here it is RC in parallel with
whatever the resistance we do have. And this is the expression we already have derived
in our previous classes and there we have assume that the base node it was a ground AC
ground and if you if you consider say the same expression we can get the output
impedance only thing is that this rπ we have to replace by rπ in series with RA and RB and
this is true for this rπ this is true for this rπ.
And also this gm this gm part we have to replace by and the logic is same
⫽
namely the voltage appearing across rπ it is a fraction of whatever the voltage we do have
at the emitter node. So, we do have the emitter voltage and then we do have this is the
gmvbe and the vbe it is. So, this is ro and the vbe it is it is a voltage across this rπ and now in
absence of CB we do have RA and RB coming in parallel ok.
So, that is how we can get the corresponding output impedance and. So, this is RC sorry
this is RC in parallel with just now whatever we seen ro + ⫽ in parallel with
in case if we have source resistance we have to consider RS, then in case if you have
emitter resistor basically R2. So, that also you have to consider then we do have this part.
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So, let me write that here we do have rπ + RA, RB in parallel with RS ⫽ RE and then gm
need to be replaced by . So, this is the whole thing that is the expression of this
⫽
output resistance. So, again here also we can see the numerical calculation and I must see
while I am writing this one I must see that due to due to the presents due to the absence
of CB, this part particularly this part the dominant part it is getting affected because of
this factor and this factor we already have discussed that in this example it is one tenth.
So; that means, from here to here this impedance it is getting changed by a factor of a
point 0.1, but then even if it is getting reduced by a factor of 0.1 the still the RC it is
smaller than that. So, the output impedance output in parents; however, still it is
remaining approximately RC. So, internally the output impedance is getting change in
due to due to the absence of CB, but the output impedance it is since it is primarily
getting dominated by RC and that is remaining unchanged. So, the output impedance it is
remaining unchanged.
So, the input impedance and voltage gain they are getting affected by a factor of 10. So,
that is about the common base amplifier and now we will be going for design guidelines.
So, what we have seen here it is the circuit already has been designed and it is given to
us and we need to find the different performance matrices like this. Now in actual
scenario, you may have to rather design this circuit for a given requirement.
So, in the next slide we will be talking about the design guidelines. If the requirement is
given to us then we can see how we can proceed to find the values of different
resistances.
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So, the corresponding the circuit here it is for common gate amplifier and so, likewise we
also have a common base amplifier and here the task is. So, probably we will be having
instead of find probably these values are given.
So, now we do have the complimentary exercise; namely the voltage gain, output
showing input impedance maybe the current gain and output impedance those things are
given to us. And we need to find the corresponding by a circuits and assuming the other
information it is given to us ok. So, let me take a short break and then we will come back
for these design guidelines.
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Prof. Pradip Mandal
Lecture – 54
Common Base and Common Gate Amplifiers (Contd.): Numerical Examples (Part
D)
So, welcome back after the short break. So, we were here we do have the Common Gate
Amplifier and let us assume that the performance requirements are given namely voltage
gain it is given output swing it is given and input impedance is given to us and then, we
need to find the values of different parameters. Now, you must be careful here in our
circuit analysis we already have seen that out of this common gate amplifier, what are
the achievable performance we do have?
So, if the specification the requirement if it is well within that the achievable
performance of the circuit, then only a week this exercise is meaningful. So, for example,
if we have say 12 V supply and if we are looking for output swing ± 12 then this circuit
will not be able to give. So, likewise if this common gate amplifier if you are expecting
that voltage gain it is a 50 or so, it is not possible; whatever the practical value we do
have of this parameter device parameter with that it is not possible, at least in this circuit
configuration it is not possible.
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Then we may have to adopt the circuit namely this resistance may be replaced by maybe
by passive the active circuit and maybe this R2 also need to be replaced by active circuit
and so and so on. But let we assume that in this guidelines, we are not venturing into
modifying the circuit topology; rather we are restricting our discussion on this topology
and we are our task is to find meaningful value of different components passive
components.
So, how do we proceed? First of all we are assuming that the supply voltage is given to
us and then device parameter namely it is given to us, threshold voltage it is also
given to us, maybe Cgs, Cgd they are also given to us, but for mid frequency performance
they are not so important. And also we do have the requirement say voltage gain and
then output swing. So, to start with let me consider that output swing it is see if this is 12
V and the requirement maybe a ± 4 V; which means that the requirement is 8 VP-P. So,
how do you how do you utilize this information?
So, the first step it is that the voltage drop across this resistance, it should be more than 4
V and the so that will ensure the +ve swing of the output voltage it is at least it is 4 V. On
the other hand ‒ve side if you see the gate voltage of this MOS transistor should be
sufficiently low. So, if the output voltage it is changing from it is quiescent voltage by an
amount of say 4 V towards the ‒ve side then we have to ensure that the device it is in
saturation region.
Which means that the DC voltage here at the output it should be such that DC voltage
here and DC voltage at the gate it should be such that the VGD should be at least 3 V.
Why 3 V, because the Vth should have 1 V. So, the drain voltage it can go less than gate
voltage by an amount of 1 V before the device enters into the triad region. So, I should
say that the gate voltage maybe decided after deciding the drain voltage drain DC
voltage to accommodate ± 4 V or 8 VP-P. Let you consider VOUT DC voltage it is say we
consider a drop of 5 V so, 12 ‒ 5 so, that is 7 V.
And so, likewise here also we can keep a margin of 1 V. So, we can say that the gate
voltage it can be the 7 V ‒ 4 so that is a 3 V. And once you have this voltage particularly
the gate voltage is known to us and then 12 V it is the primary supply that gives us the
ratio of RB and RA. So, from this we can say that this or whatever it is. So, we can
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say that this drop it is ah. So, here we do have 3 V remaining 9 V here and there is no
current flowing here. So, we can say drop across RA it is 3 and a drop across a RB it is 1
unit. So, it is basically ⅓.
And now so, we obtained this ratio relative value it is better to also get the absolute
value and since we are not drawing any current here; typically to reduce this DC current
flow here we may consider this is in the order of 10 kΩ so, at least say 10 kΩ. So, either
you may take say a one of the possible value maybe you can say this is 100 k and this
may be a 300 k this is one possible value there are of course, many other possible values
we can consider 10 k, 30 k and so and so but we obtain the required 3 voltage DC here.
And then next thing is that the you must be having the requirement of the input
impedance and the input impedance we know that the it is expression it is and
suppose this is given to us that this is a 250 Ω, which means that gm of the transistor it is
we are looking for more right. And then also we need to see what will be the
corresponding current flow here and then we can get the value of this R1. In fact, if we
have a meaningful range so, we do have say gate voltage here it is 3 V and if we are
having some idea about the range of IDS. So, from that we can say then what maybe the
value of VGS here then to achieve this gm.
In fact, if this is 3 V and if we are looking for a meaningful operation we need at least
some drop across this R2 and the voltage here it will be left behind it is 3 V minus
whatever the drop we do have. Now, if I say that the drop here if we assign it is a 1 V for
simplicity. So, if this is 1 V then corresponding VGS it is 2 V and the corresponding the
gm so, the gm it is. So, we can say that with this DC voltage the VGS is 2 V and gains VGS
‒ Vth is 1 V. Now the expression of the gm we know that this is × (VGS ‒ Vth) and then
that gives us 2 mA/V.
So, if we have this gm the corresponding impedance of course, it is not achievable. So, I
can see here with this value of the (VGS ‒ Vth) it is not feasible ok. So, now, what will be
the corresponding option, probably we kept 1 voltage margin here. So, we may increase
this voltage by say 1 V and then we can get the (VGS ‒ Vth), 2 V. So, let me modify let
me modify this gate voltage to 4 V and the corresponding ratio here it is 1 is to 2 and
then if it is a 100 k this would be a 200 k.
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Now with this modification let us see whether is it achievable to get this gm and hence
the input impedance of 250. So, to get the gm of course, here if we have 4 V and if we are
still keeping this voltage 1 V then VGS is 3 V and (VGS ‒ Vth) it got changed to 2 V. And
with that this gm it becomes 4 mA/V. In fact, that gives us input impedance Rin = it is
just exactly 250 Ω.
So, it is possible to get this input impedance of 250 Ω, but at the cost of the probably the
higher current. So, if we are having (VGS ‒ Vth) of 2 V the corresponding IDS it is higher.
In fact, from here you can calculate what will be the IDS, IDS it is ( ) . So,
here we do have 1 mA per whole square and then we do have (VGS ‒ Vth) is 2 so, that
gives us 4 mA.
So, what we have obtained here it is let me summarize, output DC voltage is 7, VG we

are converging to 4 V instead of 3 V we are converging to 4 V, IDS it is 4 mA and so, that
is helping us to get the Rin = 250 and then of course, we are getting a both output swing
as well as the input resistance.
Now, how about the voltage gain? So, probably the voltage gain may not be having
much option, but let us see. So, if we have this current of 4 mA and if this drop it is a 5
V. So, we do have 12 V here, we do have 7 V here so, R1 basically . So, that is . So,
this is kΩ yeah. So, likewise the since the IDS it is known here and the target drop here
it is 1 V. So, that gives us R2 = .
So, that gives us the corresponding resistance here it is 250 Ω. So, what we obtain here it
is end of this analysis what you obtain here it is the RA = say 200 k and then RB it is 100
k, then R1 it is it is . So, it means 1.25 kΩ and then R2 it is 250 Ω, And then if you want
to know what will be the corresponding gain. So, if you consider the corresponding are
not probably that are not it will be much higher than this R1. So, the voltage gain if I
consider this voltage gain now it is gm(R1 ⫽ ro) and the gm we already have . So, that
is and R1 maybe you can say it is dominating so, that is 1.25 k.
So, that gives us the corresponding gain = 5. So, the achievable gain here it is 5. So, as I
said that if you are if you are having a target arbitrary or you know flexible target it may
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not be possible to provide the performance by this circuit. So, this if you are considering
this output swing an input impedance of this circuit is more important, and then whatever
the voltage you are getting here you should be happy with that. In fact, some extent it is
possible to further improve the gain, but of course, the gain of this voltage gain here it is
not so great and that is of course, obvious it is because of the ah the gm of the MOS
transistor it is a not so good.
The output impedance you can calculate and the current the current it is of course, we do
have 250 Ω here and the input resistance here it is 250. So, whatever the current you are
putting here half of the current actually it is flowing here and remaining half it is going to
the device. So, the while the current gain of the main amplifier from it is source to the
drain node it is 1, but because of the bifurcation of this current here and here we do have
only a current gain of 0.5. So, I should say in this design the current gain it is 0.5 and that
is mainly because the R2 it is it is comparable with a .
In case if you are looking for better current gain then you may have to replace this one in
fact, you should replace this transistor by active device. So, we may replace the transistor
by active device, we still discuss that in our later classes that if we replace this passive
element by active device the corresponding resistance here it will be much higher as a
result the input current most of the input current ah should be entering into the source of
the MOS transistor and then the overall current gain it would be approximately 1. So,
that is about the common gate amplifier.
So, let us see the similar kind of exercise for the common base amplifier namely the
design guidelines of the common base amplifier.
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So, again here we do have the same circuit configuration which we have discussed in our
analysis part and what we are looking for here it is, instead of find we should say it is
given. So, probably what are the things are given, probably this part it is given at least
the voltage swing and the either the voltage gain or most important thing is the input
impedance. So, and we need to find the value of different components here. In fact, all of
these components it will not be there we need to find rather this components.
We do have this other information device related information so given to us and also the
supply voltage is given to us then maybe the load capacitance also. And let to start with
we do have the supply voltage of 12 V and then let you consider again the output swing
it is a ± 4 V which means the peak to peak it is 8 V.
So, the drop across this resistance it will be it should be at least 4 V and let we keep this
voltage 5 V. So, that gives us this DC voltage again 7 V and then to gate the so this gives
us the +ve swing +ve side it is ensured ‒ve side to get the ‒ve side swing the voltage at
the base node of the transistor should be sufficiently low namely the base voltage here it
should be less than (7 V ‒ 4 V) here. So, I should say this voltage should be < 3 V. In
fact, it is not necessary that it should be less than 3 V if I consider the base to collector
junction maybe weakly forwarded, but the value is only 0.3 so, it hardly matters.
So, if we say that this voltage the voltage here it is even if it is a 3 V that may be
considered is good enough to get the ‒ve swing of say 4 V. So, we do let you let you
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proceed with 7 V here and 3 V here and we do have 12 V supply here. So, the
requirement of 3 V here demands that this voltage it should be you know divided by
these 2. So, if I ignore the base current compared to this current, then we may say that
the RA and RB this ratio can be obtained by considering this drop and this drop without
considering the IB, which means that drop here it is 9 V and drop across this RB it is 3 V.
So, we can say this is 3 is to 1 right.
So, I hope in my previous exercise I have done correctly namely the RA and RB for
common base I have done the correct calculation; maybe you can check that, but anyway
let us proceed with this example. So, what we have it is it is 3 : 1 ratio. And in case if
we want to ignore the effect of IB the current flowing through this circuit we can consider
it is almost say 10 times higher than IB at least 10 times higher than IB and typically you
may consider this is a 30 k and this may be 10 k is a meaningful option.
We can have any other combination only thing is that as a if you are increasing the value
of this RA and RB towards higher value maintaining this ratio. Then the moment that you
draw the base current the voltage here it will not remain at 3 V it may drop, but in any
way if this voltage is dropping the output showing it is not getting affected it may affect
something else.
So, let we assume that 3 V it is written by the selection of RA and RB and then the
voltage coming to the emitter after the dirtying of 0.6 VBE from 3 V we do have here it is
2.4 V right. So, we do have 2.4 V here. So, now, we do have the drop here known to us
next thing is that we need to find the corresponding collector current or emitter current.
Now, how do we find? We can make use of particularly this one the input impedance.
So, if the input impedance is given to us then from that we can say that what may be the
corresponding current. So, let you assume that input impedance required input
impedance it is say 13 Ω suppose, which means that it should be it is 13. So, which
is and that is we can approximate ah to this input impedance and this is and this
is say 13 Ω which means that the IC = 2 mA.
So, once we obtain this IC to achieve the input impedance now we obtain IE also and then
IC we are already obtained. So, from that we can calculate RC = 7 V not 7 V, 12 ‒ 7
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rather 5 V, . So, that gives us a 2.5 kΩ. So, likewise RE it is drop across this one is
. So, that gives us 1.2 kΩ. So, we obtain RA, RB and then RC and RE and then
probably you can find what the corresponding gain is.
And you may recall the gain it = gm(RC ⫽ ro). And if you consider 2 mA of current value
of ro = so, that is 25 kΩ. On the other hand RC it is 22.5 kΩ so, we do have gm
here it is and (RC ⫽ ro) which it is which = right. In fact, if you see here it is this
part it is it is . So, it is coming. In fact, this is a 25 k should multiply by 103 and this
calculation it is giving us AV = .
So, I should say 104. So, whatever the value it is coming roughly this may be giving
close to a 100 yeah close to 100 approximately. So, in this case as expected that voltage
gain of this amplifier it is expected to be high. So, we can have a 100 gain roughly, but in
case if we have the source impedance and the input impedance it is a 23 Ω. And if this
RS it is much higher than this input impedance then again it will be having attenuation as
we have discussed earlier.
So, the voltage gain maybe from here to here it is a 100, but then here to here we have to
see how much the attenuation coming due to the potential division happening by RS and
input resistance. So, that gives you an idea that to get a meaningful input impedance and
output swing how we select the value of different passive components. Again note that
the in case if you want to further improve the circuit you may have to replace this
register by active device maybe another NPN transistor. Similarly if you want to improve
the output impedance in this case the output impedance it is dominated by RC show it is
approximately RC so, that is 2.5 k.
Current gain from here to here it is close to 1 in fact, this is α and α it is this is 100
divided by 100 and 1 coming from the device, but then if you consider the potential
division it is happening here and here there will be a certain loss fortunately this RE if we
see this RE it is much higher than. So, this RE it is much higher than input resistance of
the circuit so, most of the current it is entering to this circuit. So, I should say this current
gain for the common base amplifier without replacing this register by active device
current gain it is still approximately 1. So, that is that is the difference compared to this
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common gate and this common base. What I was telling in the previous example now let
me just since we do have maybe 2 minutes of time.
So, if we recall in this circuit what we said is that, the voltage we are targeting here it is 4
V. So, the ratio of RA and RB so, this is 12 V. So, that is , . So, this resistance you may
consider this is 200 say 200 K and this resistance it may be a 100 k or maybe 20 k and 10
k is fine. Now, let us see what we have, I think most of the things I have discussed
whatever we have planned.
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So, in this module what we have done it is we started with motivation of going for this
third configuration namely; common base, common gate configuration. We have
discussed about the basic operation and biasing of this configuration. We have done the
detailed small signal analysis to find voltage gain, input impedance, output impedance
and the current gain and also the cutoff frequency.
And then we have seen a number of numerical examples where we obtain the
performance of designed circuit both common base and common gate. And then we have
discussed about the design guidelines; namely how do we select the value of different
registers in the common base and common gate configuration. I think that is all I do
have.
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Prof. Pradip Mandal
Lecture – 55
Multi – Transistor Amplifiers: Operation and Analysis (Part A)
Yeah, dear students welcome back to the online certification course of Analog Electronic
Circuit. Myself Pradip Mandal from E and EC Department of IIT, Kharagpur, today’s
discussion it is Multi Transistor Amplifiers. So far we have discussed about different
amplifier configurations, so where one transistor primarily you know single transistor it
was doing the amplification and other activities. So, the transistor it was either BJT or
MOS transistor and for different configurations we have seen the merits and demerits of
the different configurations.
Based on that merits and demerits we shall try to combine different configurations
together, so that we can get overall better performance. So, let us see what is the overall
plan in the next slide.
But, before going to the overall plan let me see our alignment with our course layout. We
are in week-6 and we are in between of the block level and module level. In fact, we are
will be moving back and forth here. And, so, philosophically we can say there these are
building blocks or they may be modules and to be precise whatever the topic we will be
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discussing here it is common emitter, common collector cascaded together. Then may be
common source and common drain configurations cascaded together.
Then common collector and common collector cascaded together and so and so. So for
each similarly the Darlington pair and so and so and for each of these configurations you
may say that as they are involved more than one transistor this configurations it may be
named as multi transistor amplifier. And, the purpose of that is of course, getting better
performance compared to whatever we have obtained from single transistor amplifier.
So, the topic we will be covering today it is enlisted here. We shall start with the
motivation of going for mixing different configuration together and then we basically we
will summarize whatever the earlier discussion we are having. Based on that we shall see
that how meaningful mixing it is useful to change the impedance and change the output
impedance and maybe what is the overall circuit performance particularly when you
consider for the bandwidth of the circuit and what will be their influence so and so on.
So, if you see the common emitter followed by a common collector, its purpose it is to
decrease the output impedance. So, we can say that conceptually we can decrease the
output impedance of existing amplifier by simply cascading one common collector stage.
So, when we say that common emitter is the main amplifier followed by the common
collector. So, likewise if we have say common collector amplifier already and then
whatever the output impedance is coming from the given common collector amplifier, If
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you want to further decrease it is output impedance you can cascade with another
common collector stage, so that the overall output impedance it will be even lower than
that.
So, likewise the if we precede if we precede common emitter or common collector stage
by another one common collector configuration we can increase the input impedance ok.
So, conceptually again we can increase the input impedance of an existing amplifier by
connecting one common collector stage at the input side. So, these are the discussion it is
primarily on BJT circuit. In fact, we do also have a special popular configuration called
Darlington pair we shall see. In fact, this is similar to common collector common emitter
configuration, but we will also see what are the difference and pros and cons.
And, then we do have the most counterpart namely we can decrease the output
impedance of say one common source amplifier existing common source amplifier by
cascading; by cascading with a common drain amplifier. So, note that the common
source amplifier since its gate impedance is very high we need not to precede the
common source amplifier by another see common drain configuration which means that
in BJT both we do have scopes to in in change or improve the output impedance as well
as the input impedance.
On the other hand, for most counterparts you know since the input impedance is already
high the improvement here it is only to improve the output impedance rather to be more
precise decreasing the output impedance.
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So, in the next slide what we will be doing is primarily focusing on the motivation of
going for mixing different configuration and here to start with we shall summarize
performances of different configurations. So, so far we have discussed basic three
configurations namely, CE, then CC and then CB configuration. And, we have gone
through different derivations and all.
Now, here what we are trying to highlight is basically we consider say one configuration
and for this configuration these are the circuit configuration we already have discussed
either we may have simple CE amplifier or we can have CE amplifier with emitter
degenerator bypassed with CE and so and so, but both the circuits are having the common
you know performance matrices. What are the performance matrices we are focusing on?
The voltage gain, input resistance, output resistance, input capacitance and then current
gain.
So, as a building block if I consider if we model this circuit or this circuit in the form of
voltage amplifier, its corresponding macro model it is given here this is this was also
discussed that whenever we translate the amplifier in the form of one amplifier
particularly it is voltage amplifier. Then the voltage amplifier we can model by three
important parameters namely voltage gain then input impedance and then output
impedance and its electrical circuit configuration here it is given.
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So, we can say that by looking at the value of these three important parameters we may
certify whether the circuit is good or bad. Say for instance, the of course, the voltage gain
should be high and it is expression it is given and qualitatively you can say that voltage
gain of the CE amplifier it is reasonably good. So, it may be in the order of say 100 or so
or even beyond that ah.
Then input impedance of the amplifier which is given by RB ⫽ rπ; RB it is coming from
the bias circuit and then rπ it is coming from the transistor. And, then we may say that it
is quote and unquote high and qualitatively we can say high, but just to get a feel that
when you say high in this context its value it will be somewhere kΩ maybe 10 maximum
maybe some tens of kΩ.
So, if this resistance if you see in this model and if you see it is input port since we are
feeding the signal here it is in the form of voltage, then higher this input impedance is
better because then in presence of the source impedance RS the signal coming from the
main source it will be able to come arrive to the input port of the amplifier.
On the other hand, if the Rin it is much lower than RS then there will be significant or
may be very very high signal attenuation. So, whenever we are call that some amplifier it
is good we like to see that this input resistance should be as high as possible ok. So, in
case if we have some value and if we want to further improve of this amplifier in terms
of input resistance which means that we like to increase the Rin further.
On the other hand, on the signal coming at the output port it is a voltage and the output
impedance here if it is smaller, then in presence of the load resistance here we can say
that internally developed voltage here which is AVvin it will be primarily the entire
amount it is coming there.
So, I should say smaller this Rout is better. So, I should say smaller is better and input
resistance higher is better. So, based on this understanding we may say that this is good
for voltage amplifier amplification, but this is not so ok. So, that is why I put this in red
color indicating that if you directly you want to use CE amplifier there may be some
application where load resistance if it is relatively small then the value of this Rout it may
create significant amount of attenuation at the output node ok.
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So, on the other hand if you see the input capacitance though the input capacitance it is
not shown here, but if you recall along with the mid frequency performance, we may
have to consider input capacitance because this input capacitance along with RS and may
be combination of RS and Rin they will form one R-C circuit and that R-C circuit it will it
will define the upper cutoff frequency. So, I should say this Cin and RS ⫽ Rin they are
forming R-C circuit. So, the upper cutoff frequency of the frequency response of the
amplifier starting from the primary input to the primary output it may be defined by this
RC time constant.
So, here again Cin; Cin is smaller the better. So, the Cin is smaller. So, I should see smaller
is better. So, if you see the expression of the input capacitance of CE amplifier Cµ which
is base to collector capacitance Cµ that is getting × the voltage gain gm(RC ⫽ ro). So, as a
result we can see that typically it is value it is high ok. Say for instance Cµ it may be in
the order of few pF to maybe 10 pF and if the gain it is 100 so, then it gives us
capacitance here it is in nF and then nF capacitance it may create the bandwidth
limitation of the overall amplifier.
Now, this configuration it may be considered as voltage amplifier or and or current

amplifier and in this circuit particularly in this configuration CE amplifier configuration
input to output current gain it is β of the transistor. It is very straightforward we already
have discussed that and the corresponding model in case if you want to use this CE
amplifier as current amplifier it is given here. So, this is the macro model of that.
So, here also we do have the three important parameters particularly Rin, Rout and then
current gain ,AI and the other parameter of course, you can consider the Cin here and for
this configuration the input port is base and output port it is collector. So, unloaded
current gain of this circuit is β of the transistor.
So, this β typically we know that it will be in the order of 100. So, we can say it is good
it is high. So, higher of this current gain is better. The CE amplifier can also be
considered in other you know mode of amplifier namely trans conductance or trans
impedance amplifier, but again based on the signal type we may say that sometimes this
is in favorable condition or not. Say for example, in this case if I say that Rout it is high
and for voltage mode amplification that is not good.
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On the other hand, if this same Rout if it is high and if we are looking for some
application where output we like to consider as current then of course, higher the value
of this current higher the value of the output resistance is better. So, depending on in
what configuration we are looking for depending on that we may say whether some
parameter high or low is good or bad, it is very subjective.
So, while you will be discussing about the mixing of different configuration we shall
keep the of the main focus on voltage mode amplifier and based on that we may see that
how different configurations are getting mixed up. So, as I said that so far we have
summarized CE amplifier. So, likewise we can also summarize common collector
configuration and then we can see that qualitatively which is in favor of making the or
using that configuration for voltage mode amplifier and or current mode amplifier ok.
So, let we go to the next slide where we are summarizing common collector
configuration. So, we do have common collector configuration it is given here and for
this circuit also we do have detailed derivation of the voltage gain, input impedance, then
output impedance, then input capacitance and of course, the current gain. And, whenever
you are talking about different parameters we do have the corresponding model here
voltage amplifier. So, this is for your reference and then current amplifier.
Now, if we see the expression here; if we see this expression here and if we put the
typical value it can be easily obtained that it is very low. In fact, it may be lower than
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mathematically it is lower than 1, it may be close to 1, but it is less than 1. So, what does
it mean is it CC configuration should not be used as voltage amplifier by this stage itself.
So, as it is not providing voltage gain so, it is main purpose definitely it is not to use for
voltage amplifier without taking any support from other configuration.
On the other hand, if you see it is input resistance. In fact, if you see the expression of
the input resistance since the RL and ro it is getting amplified by (β + 1) which means that
this is very high. In fact, it is much higher than CE stage. So, this is this is writing in blue
color indicating that this is good for voltage amplifier so, this Rin is high. Though the
voltage gain here of this configuration it is not really favoring voltage amplifier
application, but it is input impedance is very high.
And, also if you see the output resistance and its expression here it is given and it is
dominated by and we have seen that the order of magnitude of this gm it is maybe 10
to 20 Ω and that is low very low other and again this Ro since it is low it is in favor of
using this circuit for voltage amplifier. Also, if you see the input capacitance Cin it is
only Cµ.
So, the Cµ is this capacitance without having any amplification. In fact, theoretically Cπ
is not having any contribution as the input to output voltage gain is close to 1 and due to
the Millers theorem or from the Millers theorem you can say that the effect of Cµ, Cπ it is
negligible. So, we do have only Cµ coming to the output node or loading the sorry, input
node.
So, again input capacitance from the input put to ground. So, this Cin it is also in favor of
using this configuration for voltage mode application, but the question mark is that it is
gain it is very low. So, again if I want to use this CC configuration alone we cannot use
it, but then if we take support from other configuration then we may get a better
configuration compared to maybe the other configuration or CC configuration ok.
So, if you want to get everything right, we need to have some mixing. I also must say
that this circuit is having very good current gain (β + 1) and since this is high so,
depending on some application this circuit can be used as current amplifier, but then the
natural question is that whether the input resistance and input resistance and output
resistance are they really supporting for current mode amplifier? If you carefully look at
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this one input resistance is very high and if the input resistance here it is very high, then
whatever the current it is trying to penetrate that may get lot of resistance that may be
having difficulty to enter into that which means that major part of the current it will be
flowing through the source resistance itself.
So, in other words we can say that there will be big amount of attenuation. So, this high
value of Rin definitely it is not in favor of current mode amplifier. Similar thing it is also
can be seen here for Rout, output voltage it is very low. So, if this is low then at the output
port we may not be having good amount of current coming out of the internally
generated current. So, the low value of Ro it is not really in favor of the current mode
amplifier.
So, the summary here it is if we want to use CC for voltage mode amplification, then the
game itself is poor. On the other hand, if you if you want to use this CC configuration for
current mode amplifier then even though it is current are high current gain it is high, but
then it is input and output impedance they are not really supporting it is good
characteristic. So, again we may require support from other configuration.
So, likewise if you go to the third configuration namely the common base configuration
yes, so, in common base configuration here we do have the circuit diagram we do have
the circuit diagram. And, we already have detailed derivation of different performance
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parameters given here and if you recall their values and qualitatively you may say that
the voltage gain is high, but it is subjected to a condition.
If the source resistance; if the source resistance signal source resistance Rs if it is 0, then
only we do get this expression. So, it is in case if you have a special case where the
source resistance is very very small, then we can say that it is gain it is high. But, then if
the source resistance is it is having significant value due to input impedance of this
configuration is low rather very low and the reason is given here the expression is given
here from that we can derive that input resistance it is in fact, in the order of . So, since
it is very low, then we may or may not be able to satisfy this ok.
So, I should say ok. So, let us look into the Ro and its expression it is given here and Ro it
is major contribution coming from the active devices given here and R1 it is; R1 it is
basically the bias circuit. So, if I consider the output resistance coming from the main
configure on the amplifier we can say it is very high that is because this rπ, Rs and R2 in
parallel it is getting amplified by intrinsic gain of the amplifier namely gmro which is
intrinsic gain of the transistor.
So, since this is again very high, and definitely it is not in not in favor of voltage
amplifier so, whenever we like to use this for voltage amplifier since this is low so, since
this is rather very low we will not be able to use this for voltage mode amplification.
Sorry, this is this is very low and this is also very low. So, as a result this common base
configuration better we should not be using as voltage amplifier. In addition to that even
though we are saying the gain is high, but it is only when you consider most of the time
you may see that hypothetical situation where Rs is 0, then only we are getting high.
So, anyway all of the three parameters they are not supporting to use this CB
configuration to be used as voltage amplifier. But, if you see the current mode amplifier
on the other hand, it is having some other interesting information that for current mode
amplification that this Rin in fact, this is in favor on that right and same thing if you if
you see the output resistance very high that is in favor of on the current mode amplifier
where we are looking for Ro should be as high as possible. But unfortunately, it is gain if
you see gain it is α and it is very low which is in fact, it is theoretically it is less than 1
though it is close to 1.
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So, again CB it is input and output impedance they are favoring for current mode
amplifier, but unfortunately because it is current gain is low that makes it is use question
mark. So, probably CB stage can be used for some better configuration or rather we can
mix this CB with other configuration to get overall circuit performance either may be for
voltage or current mode amplifier or may be trans conductance or trans impedance that
we will see.
So, if you put all these three configurations together namely CE, CC and CB and if you
enlist the qualitative parameter you know values or I should say if you consider then
together probably we can make a meaningful decision to see what kind of mixing of
different configurations it will be useful.
So, here we do have the summary yup. So, we do have the CE amplifier it is having good
gain, input resistance is high, this two are in favor, but because of this one it is question
mark. On the other hand, so if so, this is for voltage mode operation, then if you want to
use this as current amplifier so, this is good. In fact, if you see this is this is good for
current amplifier ok, but then input resistance it is not favoring it. In addition to that this
input capacitance it is high. So, for voltage mode amplification that may restrict the
bandwidth.
So, I should say that the intrinsic gain if you see of this configuration as it is having both
voltage gain and current gain so, this circuit may be the heart of either voltage mode
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amplifier or current mode amplifier, but each for each of the cases we requires some
suitable buffers to cascade with the subsequent stage or maybe to feed the signal we can
probably you can precede this stage or in case if you want to connect a load we can put a
buffer and then you connect the load.
So, this is the important remarks that CE amplifier it is a good candidate for voltage
amplifier as well as current amplifier, but it is better to have suitable buffer. When I say
suitable buffer depending on whether it is voltage mode signal or current mode signal at
the two ports, input and output ports you have to put a meaningful other configuration.
So, let us see, what the other configurations we can think of are.
So, if you see the CC stage and for buffer mode configuration what we are looking for is
that the input and output impedance if you see ah. Since the input resistance is very high
and output resistance is very low this is good for voltage mode buffer ok. So, if you want
to use voltage mode buffer definitely then we should be inviting this CC stage. And, also
it can be used for power amplifier mainly because even though the voltage gain it is low,
but since it may be close to 1, in addition to that it is also having a current gain so, these
two together if you put that may be helping us to get a good current gain.
In fact, CE amplifier since it is having both voltage and current gain that can also be used
as a power amplifier, but again that requires some additional buffer. So, which means
that in case if we are constructing say voltage mode amplifier so, this should be the heart
and then CC stage should be used to buffer the stage. So, we can have CE stage at the
center and then we may have CC stage as buffer for the output port and or CC stage as
buffer at the input port also. So, this is for voltage mode amplifier right.
And, on the other hand if you see the third configuration. So, let me use a different color
yeah. So, if you consider say CB change and if you see it is in the Rin and Rout they are in
favor of current mode amplifier. So, in case if you are constructing say CE as current
mode amplifier so, then you can put the common base configuration after the CE stage
and if it requires probably you can put the CB stage before this one, but many a times
this may or may not be required, but this is important; if you put the CB stage you can
get good current mode amplifier.
In fact, we will also see that if you put the CE and CB stage together so, that is another
configuration let me use violet color. So, if we put the other configure if you consider the
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CE stage followed by CB stage interestingly it is not only working as a buffer the CB
stage, but in fact, by this one we can enhance the gain.
So, this is so, if you put the CE stage followed by CB though the CB stage the CB stage
may not be having much current gain, but it is input impedance at the input and output
quite different and whatever the current at the output port you are generating out of the
CE stage if it is arriving to its output port since it is output port impedance of this
amplifier it is on the configuration is very high. So, at this output port you can get very
high voltage.
So, the CB stage apart from using as a buffer for current mode amplifier it can also be
used as voltage gain booster ok. So, in fact, if you put the CE followed by CB something
called cascade configuration that is another configuration we will be discussing soon. So,
that is how we do mix different configuration as we have summarized here we do have
another possible configuration, we do have another possible configuration or you may
consider partially you can have partial mixing namely CE-CC or CC-CE alright and CE-
CB and then of course, CE-CB it is already here.
So, in the next slide we will be talking about this kind of different configurations and we
will see the corresponding the other issues particularly biasing and all ok. So, but before
that let me take a short break and we will come back.
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Prof. Pradip Mandal
Lecture – 56
Multi-Transistor Amplifiers: Operation and Analysis (Part B)
So, we are talking about this different possible configurations meaningful configuration
and let we go one by one how they are helping us to improve the performance.
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So, in the next slide we will be mixing CE and CC. So, for our reference so, we do have
the main table we are keeping it here and we will see that how the CE and CC will be
helping us to improve the performance to start with let you consider CC and CCs
together and then probably we will see the CE and CC.
So, we do have the basic CC configuration and its main characteristic or main rather
from requirement is that input is at the base and output is at the collector. So, if I
consider say one transistor we do have see input here feeding at the base of this transistor
and let me call this is Q1 and then it is output it is going to the second transistor. So, we
do have the second transistor here and let you call this is Q2 and of course, the collector
here and collector here they should be connected to the main supply, better be connected
to main supply.
In fact, we can have some resistance also connected there, but for ideal condition we
want that and if you see they are bias conditions. So, I mean think of that it is having a
DC current here as we can see here and we may or may not require this DC current
depending on the level of the current of the Q1 and Q2. So, if I say that if we do not have
any bias current here this means that the base current of the second strength transistor it
is same as the emitter current of the first transistor. If this is getting satisfied then we do
not require.
Otherwise the additional current; additional current of the emitter in case if it is a emitter
current of the transistor-1 it is higher than the required base current of the second
transistor then we may required this bias circuit. So, that is why I am just putting a dotted
line. So, depending on the situation we may or may not consider, but whatever the
situation it is small signal wise you may say that for ideal current source here we may
think of this is open.
So, if I draw this small signal equivalent circuit and if we are feeding the signal directly
to the base to base of the second transistor, then we can draw the small signal model of
the first transistor and then followed by the second transistor. Let me use that blue color
just for consistency of the other diagram.
So, this is the small signal model of the second transistor Q2 and this node it is connected
to DC voltage which is AC ground and this is also AC ground and of course, we do have
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the input port. So, we may see that the input signal we are feeding here. So, this is the
input signal vs.
Now, if you see that different parameter of the individual transistor we do have rπ1 and
then we do have ro1 likewise for the second transistor we do have rπ2 and then ro2 and this
is the output node. So, primary output port it is given here. Now, what we are looking for
it is basically two things – one is the increasing the input resistance and also it is we are
expecting that this will decrease output resistance. So, let us see how this configuration
on this kind of mixing it is helping to get higher input resistance.
So, Rin if I consider to get the Rin of course, we can whole circuit, we can analyze we can
find what is the corresponding input current going there. And, then if you take the ratio
of this vs and then this iin so, from that you can say what is the expression. Better
approach or qualitative approach it is something like this.
Suppose, if you consider the input resistance of the second stage depending on whatever
the load we do have here say RL, so, we may say that this resistance looking into the base
of transistor-2 it is rπ2 + (1 + β)RL we can ignore this one and so, that is the resistance.
Now, on the other hand, if you are coming to the primary input port and if you try to see
what is the corresponding input resistance you can see that we do have rπ1 + β of the first
transistor (1 + β1), it is amplifying whatever the impedance you do have. So, even if you
are you may consider this one or you can ignore that, but whatever it is. So, (1 + β1) it is
multiplying this ro1 plus whatever the resistance you already have obtained here. So, in
summary so that is in fact, the input resistance of the entire circuit. So, in summary what
we can say of course, this β it is a second transistor β so, we should write β2.
To summarize this input resistance it is rπ1 + (1 + β1) into ok. So, this should not be plus
it should be rather in parallel with whatever you do have. So, that is ro1 in parallel with
this part. And, if you consider the dominant terms of course, this will be dominating (1 +
β1) × ro1 in parallel with this one (1 + β2)RL ok. So, if it is very clumsily for you I am
writing the expression here the final expression (1 + β1){ro1 (1 + β2)RL}.
In fact, if you ignore this part what you can say here it is (1 + β1) and then (1 + β2)RL
which means that whatever the load resistance we are connecting here RL to the circuit
that is seen by the input signal source through this amplification of the impedance of
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each of the stages namely (1 + β1), (1 + β2) are getting amplified. As a result you can get
really high very high input impedance. So, the purpose of CC stage first one it is input
impedance. So, the advantage rather, we are writing here.
So, the advantage here it is the input resistance. So, input resistance is very high very
very high. On the other hand, if you see the output resistance and we are looking for this
output resistance would be as small as possible. So, if you see ok. So, let me clear
otherwise I am not be able to explain to you.
So, the same configuration namely CC followed by CC. So, we do have the CC followed
by CC and so, we do have the Q1 here, we do have the Q2 here and this is connected to
Vdd. The output impedance so, we know that this will be in the order of and in this
case gm of the second transistor. So, now, the gm of course, it is function of the current
ah. So, we do have gm = or rather it is of the second transistor.
And, in this case if you see that of course, it depends on the current. So, higher the value
of this current then we can have better situation namely smaller output resistance, but
then to support this current in case if you are loading the primary port then it may be a
problem.
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But, then since we do have the second transistor here to support this high value of IC2 we
require a smaller version of this same current namely of the second transistor which is
eventually this is equal to IE of the first transistor and to support this we require a base
current here which is very small namely IE1. So, IB equals to this IE ( ).
So, to support this large current we require here it is the required base current is very
small. So, this base current it is coming here after this amplification of (1 + β1) of the
transistor-1 and then we do have this β2 coming from the second transistor. So, what we
are getting here it is the again the output resistance because this IC we can support very
high value and then you can see that the output resistance of CC – CC stage it is very
very low ok. So, that is what that is the advantage of having CC followed by CC.
Now, let us see the other configuration namely CE and CC. So, mixing across different
configuration. So, we do have the CE stage circuit here CE configuration and then also
we do have the CC configuration, and let us see how they can be mixed together to get
the combined circuit. So, we do have the first transistor see we do have Q1 here and its
corresponding RC. For simplicity I am not putting any emitter degenerator, we are using
fixed bias configuration and then we are feeding the signal here.
And, then this output it is going to the CC stage so, that means, different colored here.
So, we do have the CC stage and the collector it is connected to the supply and then we
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may have the corresponding bias circuit or and or the load resistance here. So, this is the
primary output port. So, as we have seen that the CE stage CE stage it is providing good
voltage gain and also it is having decent amount of input resistance and but then output
resistance it is high namely it is dominated by RC.
But, then if we simply cascade it with CC so, we are anticipating that the resistance
coming to the output port without considering this RL if I consider only up to this one
and if I see what is the output resistance. We are expecting that this output resistance
final output resistance it should be much smaller than this one. So, what is the output
resistance?
You may recall. So, this is CC stage. So, naturally its output resistance expression we are
expecting it will be on this transistor. Assuming that whatever the circuit we do have
here it is resistance is 0, but. So, this is true if the resistance of the signal source is 0.
So, if I say that corresponding RS = 0, but if it is not; if it is not then as we have
discussed earlier this gm2 it will be getting attenuated by rπ here and whatever the RS will
be having and incidentally RS is inter close to RC. So, I should say for RS2 = RC what we
have here it is right.
In fact, you can further simplify this expression which is ( ) which is β of the
transistor β2. So, you may say that since this RC it is getting divided by β2, even though
we do have the rπ of the second transistor coming in series, but since it is getting divided
by β2 this is much lower than. So, I should say this is much much lower than RC.
So, what is the conclusion? The main advantage here it is if I am having only CE the Rout
it was RC that is getting changed to ( ) of the second transistor right. So, that
makes much smaller and that is useful for the connecting a load. In fact, the not only it is
just making the output resistance getting smaller and concluding in that form we can
further go and say that what is it is main advantage and motive. By this if the upper
cutoff frequency earlier it was decided by see RC with CL, in case if you are connecting a
load capacitance directly there without considering CC stage then the upper cutoff
frequency it was like this.
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Now, this upper cutoff frequency it is getting changed to 1 by whatever the new output
resistance we do have (rπ2 + RC) × CL and then β2. So, approximately if I drop this part
for just for qualitative comparison we can say that this is β2 times whatever earlier upper
cutoff frequency we are having. So, this is the modified one if I say dash and this is the
original one. So, we can see that the bandwidth of the circuit bandwidth of the amplifier
it is getting extended.
Now, so, that takes care of the output port, similar kind of things it can be done for the
input port also namely, if I precede this CE stage by CC stage then we can get the
enhancement of the input resistance. So, in case even though whatever the input
resistance, so, we do have namely RB and rπ if we are not really happy with that and if
you want to further increase it then we can do that we can mix this CC configuration
before the CE stage.
So, in the next slide what we are going to do we will be having CC followed by CE.
So, here again we do have the individual stages and if we mix them together the circuit
configuration we will be getting is the main transistor CE main transistor it is in CE
configuration. So, we do have the RC and then let me call this is Q1 supply we do have
the Vdd and this is the output port and then we do have the; so, let me call this is Q3
connected to Vdd and so, this is the CC stage and the input we are directly putting here.
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So, either we may have the bias circuit here or depending on the situation we may put
signal with a meaningful DC.
So, of course, if I put bias circuit on the other hand we can put a DC blocking capacitor
and then we can feed the signal whatever it is and then of course, in case the emitter
current here it is entire emitter current DC current if it is not necessary for the base of the
main transistor Q1, then you may put a current sync path. So, the excess current it will be
going here, the other part the base current it will be go into Q1. So, whatever it is the
input resistance of this circuit small signal input resistance that is our primary interest
what is the corresponding expression.
So, if you see the circuit here the impedance coming from the Q1 at the emitter of Q3 it is
we do have the rπ here. So, we can say that we do have the rπ1 and then whatever the
impedance will be seeing here it is this rπ1 and then of course, we do have ro. So, that ro
we can ignore.
So, we can say that at this node we do have essentially rπ1 and then input resistance at
this point it will be rπ3 of coming from transistor 3 + (rπ1 ⫽ ro3) though as I said you may
ignore which is getting multiplied by (1 + β) of transistor 3. So, you can approximate this
by saying that this is rπ1(1 + β3).
So, what is the advantage we are getting here that input resistance this input resistance
initially for this stage it was rπ1 that got enhanced or increased to rπ1(1 + β3). In fact, this
is very common technique it is used for op-amp, we can put this additional transistor
here which enhances the input resistance and this is important for BJT circuit for moss
we know that gate resistance is very high.
So, such kind of enhancement it is not required for moss configuration. But, for BJT
since rπ it is not very high we may require the CC stage to be used to proceed with CE
stage. So, we do have this CE stage input resistance it is getting enhanced by the CC
stage. So, that is the advantage. So, likewise we can go for the other configuration.
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Let me see what the other configurations I do have are.
So, before I go to this composite configuration I must say that so far. So, we are talking
about CC and CE, we also talk about talked about the CC and CC. So, is there any better
way of analyzing this kind of circuit? Just I like to give a little notion of that now we do
have the next discussion something called composite transistor.
So, let us see what it means. Suppose, we do have see one transistor in general say Q1
and then we do have another transistor say Q2. So, whether it is CE – CC or CC – CC
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this kind of configuration we had seen and see emitter of Q1 it is directly internally
getting connected to the transistor-2.
And, as a user or as the complete circuit designer we may not be much interested of
accessing this node, instead we like to access this node to feed the signal probably or we
like to access a this node to observe the signal and or to access this node. And, at the
same time we like to keep the collector of the first transistor to a meaningful voltage
called say Vdd.
So, if we see this configuration then of course, whenever we do have the emitter current
of Q1 coming here either the entire emitter current need to be consumed by base terminal
of Q2 or we should be having some bias bypassing arrangement here. So, I should say if I
am having say this bias Vdd and this one then whole thing so, if these two bias is properly
arranged then whole thing it can be clubbed together and it can be consider one single
transistor where you may call this is the base terminal, this is the collector terminal sorry
this is collector terminal and this is the emitter terminal.
Now, incidentally the collector and emitter terminal of Q2 it is coinciding with this, but
then base terminal of Q2 it is not visible to us or user; on the other hand, base terminal of
Q1 it is defining the base terminal of the transistor or the complete transistor. So, we may
call this as composite transistor and if we consider this is composite transistor for one
transistor we already have seen that three possible configurations are available.
Now, if I call this is base of the composite transistor and if we denote by B(C) this is
collector of the composite transistor denoted by C(C) so, likewise emitter superscript C.
Now, can I use this entire composite transistor in different configuration? So, let us see
suppose if I connect the circuit in say CE configuration.
So, what do I have to do? Let me use some color let me blue color. So, for CE
configuration what I have to do I need to put a bias here and then I need to put the signal
here and then I need to put some bias circuit here through RC and the emitter we can
connect to ground and we call this is the output node. So, what we have done here it is
composite transistor in CE configuration.
Now, if I put this in CE configuration internally what we have obtained here it is actually
this is CC stage and this is CE stage. So, we can say that if the composite transistor it is
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in CE configuration which is making CC followed by CE. So, likewise, if I put the
composite circuit or composite transistor in say CC configuration; so, for CC
configuration what I have to do?
I have to rather instead of connecting this to ground then the supply I should connect to
rather directly to Vdd and instead of calling this as output we will put a resistance here
and then we call this is output and then of course, we will be feeding the signal here.
So, now we obtain by this connection by this connection and this resistance here call RL
we got composite transistor in CC configuration, but then internally if you see that this is
anyway it is CC. So, Q1 it is in CC and then Q2 it is also CC. So, in other words, if the
composite transistor it is in CC configuration eventually we are getting CC – CC
configuration.
So, likewise this composite transistor can be connected. So, in different configuration
and the analysis can be whatever the analysis we have done for CE and CC configuration
that can be utilized to get the overall performance of the CC – CE or CC – CC
configuration ok.
We will continue this one, but let me take a break and then we will get back to it.
Thank you.
782
Prof. Pradip Mandal
Lecture – 57
Multi-Transistor Amplifiers: Operation and Analysis (Part C)
So, dear students welcome back after the break. So we are talking about composite
transistor. And what we said is that if we have amplifier particularly multi configuration
amplifiers where two transistors are having different configuration or maybe the same
configuration. Then the analysis can be done slightly you know smarter way.
And to do that what you can do two transistors together we can consider a single one say
for example, you do have Q1 and Q2 together. Where Q1 it is its collector is connected to
supply Vdd. And its emitter it is directly connected to transistor-2 and then at the emitter
will may or may not be having this bias current. And then the second transistor collector
we can consider it is collector of the composite structure. And then emitter of Q2 it can
be considered as emitter of the composite structure on the other hand base of the Q1
transistor it can be considered base of the composite structure.
So, with that here the whole things, the shaded portion if I consider one transistor and
then if you find its small signal parameter. And then we can use this transistor for two
configuration say common collector configuration and then common emitter
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configuration. So, the moment you make this composite structure in CC configuration
then what will be we getting how CC followed by CC configuration we can get. So,
likewise if the composite structure or composite transistor if you connect in CE
configuration, then we can get CC followed by CE configuration ok. So, let us try to see
that how we are getting it say.
We do have the basic composite structure here whether we do have this bias circuit or
not if we connect the circuit in say CE configuration. So, which means that the emitter
we can connect to ground and at the collector we can put a bias resistor RC connected to
Vdd supply. And so, we can call this is the output port and at the base we can connect
maybe RB providing the bias current for Q1 base bias current for Q1 and then we can feed
the signal there with a meaningful DC.
So, what is this circuit configuration we are getting is that, so what you are doing is that
composite structure we are making in CE configuration. And then internally if you see
that this stage this stage it is coming in CC configuration on the other hand and this stage
this stage it is in CE configuration. So, CE configuration for composite transistor
resulting us CC followed by CE. So, likewise if you consider say the CC configuration,
so now, let me consider CC configuration.
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So, we can connect maybe a bias current here or maybe a resistor and let you call this is
output since this is CC configuration the collector may be connected to supply directly.
And at the base will be giving the signal may be directly or maybe through a capacitor
with bias arrangement. But, whatever it is we do have the input coming to the base of Q1
and output we are observing at the emitter of Q2.
So, that makes the composite transistor in CC configuration and that results into say first
stage it is CC configuration. And then the second stage is also in CC configuration,
which means that if we connect the composite transistor in CC configuration we are
eventually getting CC configuration. Now, how do we then analyze this circuit as I said
that either you can consider the entire circuit and then analyze. And then may be the
better way or smarter way what we can do the entire composite structure you can
translate into single one.
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So, if I say that entire circuit equivalently it is working as one transistor where the
collector we call C(C), emitter it is E(C) and then base is B(C). Then whenever we like to
get see performance of the corresponding amplifier coming out of this composite
transistor first thing we need small signal parameter. So, what are the small signal
parameter? So, β of the transistor then ro collector to emitter resistance. Then trans
conductance and then base to emitter resistor resistance rπ.
And just to consider this is this set is parameters of the composite transistor let you put
the superscript C here for each of the parameter. Then we can find the expression of each
of this parameter in terms of the internal and then parameters of the internal or
constituent transistor namely Q1 and Q2. So, in the next slide we will be having that let us
yeah.
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So, here we are in listing the small signal parameter and they are given in terms of the
small signal parameter of the constituent transistor namely Q1 and Q2. So, how do you
get that if you draw the small signal equivalent circuit of the entire circuit. So, say for Q1
we do have say gmvbe of transistor-1, and then we do have the rπ of transistor-1. So, this
node it is the base of the composite transistor.
Now, here this is connected to DC when you have, so this is connected to AC ground and
we may or may not be considering this ro of transistor-1. So, this is connected to AC
ground and then the, so this is the model of Q1 and then we do have the model of the Q2.
So, Q2 we do have rπ2 and then we do have voltage dependent current source gm2vbe2.
And then we do have the ro of transistor-2 and then finally, we do have the emitter
terminal.
And this is the emitter of the not only Q2, but the composite transistor. And here we do
have the collector of Q2 which is also collector of the composite transistor. So, externally
we do have these three terminals and then internally whatever the components are there.
Now, if I call this entire structure as one transistor then we can translate this entire circuit
into equivalent one transistor. And then whatever the voltage we do have here at VB to
VE that is . And then from the collector to emitter whatever the current is flowing
that is . And then collector to emitter whatever the resistance we do have that is
called .
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So, if I draw the equivalent circuit of the composite transistor. So, we do have
multiplied by the corresponding vbe namely and then we do have . So, this is
emitter and then we do have rπ and this rπ is rπ of the composite transistor. So, here we do
have base and then and you have the collector right. And if I compare see this equivalent
circuit with whatever the circuit is given here. Then first thing is that the resistance from
the collector to emitter it is directly coming from this ro2.
So, that probably we can say that = ro2, so that is the first thing and then, so this is
very straightforward to get. Then next one it is if you see the β of the transistor which
means that the current gain current gain if I consider we do have some base current is
flowing and then whatever the current is going flowing through the collector to emitter
which is β(C)ib. So, that gives the corresponding β of the composite transistor.
Now, if I am having say ib of the composite transistor flowing here ib. So, that is
eventually same as ib of transistor-1. So, the current flowing through this emitter which is
(1 + β1) times this ib and eventually that is that is giving us the base current of the second
transistor. So, this current if I multiply with β of the second transistor then I will be
getting the ic. So, this ic it is (1 + β1)ib1β2 and that is the ic.
So, if I take this ratio of and ib1 whatever we do have which is (1 + β1)×β2 that is
what the β of the composite transistor. So, that is how we are getting the expression of
the β. So, now likewise if I see the base to emitter resistance let me use different color
yeah. So, to get the if you look into this circuit we do have rπ1 coming in series with
this resistance, but then this resistance it is working as emitter de-generator for Q1.
So, whatever the resistance we can see effect of this R2 it is it is (1 + β) times of

transistor-1 multiplied by rπ2. So, the impedance at the base-2 with respect to its emitter it
is rπ1 in series with (1 + β)rπ2. So, that is why we do have = rπ1 + (1 + β1)rπ2. Now,
this part of course, it is not really playing any role to define . And once we have this
next thing it is getting the gm just we have to take ratio of the 2.
So, if I take a ratio of the 2 then we are we are getting the corresponding gm. In fact, the
in gm you can get it through different approach also you will be converging to this only.
So, how do you get the gm alternatively if I consider this is the vbe entire vbe it is from
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here to here. And part of it is appearing here as vbe2 and this vbe2 after multiplying with
gm2 it gives the collector current.
So, effectively I can say that the it is essentially gm2 multiplied by whatever the
fraction of the coming as vbe2. And what is this fraction? We do have impedance
here and also we do have impedance here and this impedance is rπ2. And the, so and the
impedance here if you see this part ignoring this part that you can ignore. So, we can say
that some and that impedance is rπ1 ⫽ .
So, the fraction we are getting here it is rπ2 divided by this resistance plus rπ2. In fact, if
you simplify it if you simplify it you will get the same expression here ok. So, anyway,
so what you can say that from this equation we can say that it is slightly smaller than
gm2 I should say it is slightly if you see the equation. And most important thing is that
this resistance is got increased and also the β of the transistor it is basically product of β
of the 2 transistors.
So, I should say the main advantage of going for this composite structure is basically
improving the β and then increasing the resistance while maintaining the gm almost the
same and maintaining the ro almost the same. So, that is how we can probably you can
consider the you can get the small signal parameter and then utilizing that those small
signal parameter you can find the gain of CE and CC.
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So, in the next slide probably we can discuss that yeah. So, let we let you go one by one,
so let you consider say CC-CE stage which means that this composite structure we can
connect in CE configuration. So, to make this circuit in CE configuration let we connect
RC at here and then to the supply. And the emitter we can make it to ground and then at
the base we can put a bias resistor called RB connected to Vdd and then you can feed the
signal.
So, that gives us the internally that gives us a CC-CE circuit, so we call this is the output.
Now, we know that the circuit it is actually this composite structure it is in, so this is
whole transistor it is in CE configuration. And for CE configuration what are the
expressions of the different parameters or the and the voltage gain namely which is
gm(RC ⫽ ro). And with gm now we have to consider we have to consider of the
composite transistor.
So, likewise RC anyway it is external, so likewise ro it should be ro of the composite

transistor. So, now we do have the expression of the which is ro of transistor-2 and
then we do have the expression of . So, this it can be well approximated by say gm2,
so I should say it is gm2(RC ⫽ ro2). In fact, this is very much of course, with a minus sign
here I sorry I forgot that there is no surprise if you see this circuit the primarily what we
obtain the voltage gain we are getting from the second stage the coming from the Q2.
And Q1 since it is connected in CC configuration its voltage gain it is approximately 1.
So, that is how we can directly get the voltage gain. Now, the input impedance on the
other hand, so for CE configuration input impedance is RB ⫽ rπ. And in this case which rπ
this should be rπ of the composite transistor and expression of the rπ it is given here ok.
So, that is the expression of the , so you can get its value and likewise output RO it is
a output resistance RO it is RC ⫽ ro of the composite transistor and eventually this is same
as ro2. So, we can say that this is RC ⫽ rO2. So, that is how we can get the performance
expression the namely the output voltage and sorry output resistance and input resistance
and the voltage gain of the CC-CE configuration.
So, likewise if you connect the circuit in CC configuration you can find the
corresponding the voltage gain, input resistance, and output resistance. So, let us see how
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we are getting it or probably you can try yourself and you can connect the circuit in CC
configuration.
So, to connect the circuit in CC configuration you can directly connect these to Vdd you
can probably connect a bias circuit here bias current source. And then this is the output
port and then we can connect a bias circuit here RB and then you can feed the signal here
at the base of the composite transistor. And we know the voltage gain it is approximately
1 and then input resistance.
So, in case if we have some RL connected here, then the input resistance of the composite
structure it is RB in parallel with whatever the resistance we do have which is rπ of the
composite transistor. In series with (1 + β) of the composite transistor multiplied by RL.
Now, again we do have the expression of and then β(C) it is given here, so from that
you can find the expression of the input resistance. It may be observed that from this part
impedance of this part it is in fact, it is quite high. And in presence of this RB of course,
this RB it may be dominating that. So, if you are constructing this circuit with this RB you
may not be really seeing much change, but internally the circuit input resistance it is
quite high.
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So, on the other hand output resistance RO we can approximate this by and this is
and this is given by ok, so I should say this is approximation ok. So, that is how we
can analyze the CC-CE and CC-CC configuration using composite transistor concept.
Now, let us move to MOS Tran MOS based circuit in fact, sorry before we go to the
MOS circuit we do have one more information to we like to share.
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We have talked about the CC-CE stage sorry, we have talked about CC-CE stage. And,
so if I if I consider this composite structure and then if I connect this transistor in CE
configuration then we are getting basically the CC-CE configuration. And what is its
main advantage the input resistance it becomes quite high.
Instead of instead of connecting the circuit in this way there is a smarter way where
instead of connecting this Q1 collector of Q1 to Vdd even if you are connecting this to the
output then also we can get the input resistance it is quite high. So, that connection
whatever the connection just now we are showing that gives us different configuration it
is referred as Darlington pair.
So, this Darlington pair I should say it is kind of modified version of CC-CE stage, why I
am I am sharing this information? Because this Darlington pair it is frequently used for
operational amplifier later we will discuss which is commonly known as op-amp. To
increase the input resistance of the input resistance of the op-amp.
So, you may be surprised that then why we do have a special kind of configuration why
not CC-CE configuration. As I said that it is it is on principle they are both the
configurations are same except this connection. So, I should say this is this kind of
modification it gives us the Darlington pair.
Now, let us move to the MOS circuit. Similar to BJT based different basic configuration
we can we can also summarize the performance matrices of the common source,
common drain, and common gate, configuration coming out of MOS transistor. So, these
are the three basic configurations and for each of these configurations we do have we
have been listed qualitatively we have been listed different performance matrices.
Namely voltage gain, input resistance, output resistance, input capacitance, and then
current gain. So, here again it is I should say most of the information it is very similar to
whatever we have seen for BJT. Except this CC stage its input resistance it is very high,
as you know that gate to gate to source connection it is through insulator. So, we can see
that it is almost infinite theoretically.
So, and that is the only difference as a result we may not be requiring any special circuit
to increase the input resistance of the CC’s CS stage. But, then to decrease the output
resistance of CS stage we can use the common drain amplifier to decrease the output
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resistance. Mainly, because if you see here the common source amplifier it is it is a very
good voltage mode amplifier.
But, main concern is that its output resistance is high and of course, its input capacitance
is also high. And this problem the output resistance since it is high that can be avoided or
rather that can be you know managed by using common drain stays cascaded with that.
So, we can say that common source we can connect with common drain to get a better or
I should say lower output resistance.
In fact, that also helps to improve the input capacitance later we will see that. But, so we
should say that this configuration it is very similar to whatever the common emitter
followed by CC stage. So, in the next slide we will be just summarizing its performance,
particularly the common source followed by common drain amplifier yeah.
So, here we do have the common source. So, we do have the common source amplifier
followed by common drain stage. Note that the drain the next stage next stage the second
transistor gate it is directly connected to the drain of transistor-1. That is because it is
very convenient and not only that it first of all we do not require any capacitance here.
Second thing is if you are putting a capacitor here then you need to have separate bias at
the gate. And but then whatever the DC voltage it is available at the gate of transistor-1
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that may be a sufficient to bias the second transistor and hence it is directly getting
sorted.
So, this CC rather CS-CD amplifier if you see its main advantage it is that the output
resistance. So, output impedance it is I should say of the second transistor, and input
resistance of course, here we do not have any the rather this input resistance is infinite.
So, Rin it is eventually coming from the bias circuit only R1 ⫽ R2.
And then we do have of course, the voltage gain which is coming from the CS stage and
that is gm1 × (R3 ⫽ ro1) of transistor-1. And this stage the second stage of course, its gain
it is approximately 1, so its voltage gain it is essentially coming from the first stage yeah.
So, this mixing of the two configurations it is primarily to get the lower output
impedance. In fact, we will we can also have similar kind of mixing namely the CS and
CG as I said that CS and CE they are the heart of the amplifier.
And then to have connection with other circuit we need to take help from buffer. So, we
will be we are in this case we are taking help from common drain to get to reduce the
lower to reduce the output resistance. Likewise, if the common source stage it is
cascaded with common gate we will be getting some other advantage particularly that
helps to boost the gain.
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So, that configuration we can say that common source followed by common gate for this
is for MOS family. And likewise common emitter followed by common base which is
for the BJT family. And both of these two circuits their purpose is primarily to increase
the gain of whatever the gain of the common source or common emitter amplifier we do
have. So, that topic of course, that is also multi configuration mixing multi configuration
that will be discussed in the next class.
So, let me then summarize whatever we have discussed today in 3 parts of this lecture
today. It is first we have started with motivation of mixing different configuration and
then, we have discussed about utilizing the yeah utilizing the CC stage to decrease the
output impedance. And that is done for both cases CE followed by CC and then CC
followed by CC for both the cases output impedance it has been decreased.
Then we also have discussed how to use the CC stage common collector stage to
increase the input impedance. So, here we are the first CC stage it is helping to increase
the impedance of the main one. So, either it may be CC or CE and then also we have
discussed about something called a special configuration Darlington pair which is quite
popular. But, that is I should say on principle it is same as CC followed by CE. And then
also we have just now we are talking about for the decreasing output impedance using
the common drain amplifier for MOS family.
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So, if we have said a common source amplifier we can cascade with that common drain
and that gives us lower output impedance. In fact, here these two and then here all are
pure BJT on the other hand this is pure MOS circuit. There is a possibility of mixing the
MOS and BJT to make the multi transistor configuration. And, so see for example, if we
have common source amplifier we can connect this common source amplifier with
common collector.
So, this is this is MOS, so this is MOS transistor based and then this is on the other hand
BJT right. And the purpose it is seen by now I think you will be able to correctly guess
that CC stage it helps to reduce the output resistance. So, likewise we can connect same
CE stage preceded by or may be followed by common drain to get them. So, this is this
is BJT and this is MOS and like that it can have common emitter preceded with common
drain amplifier.
So, if we do this the input impedance it will be increased by this common drain. So, that
is how we can mix the BJT configuration along with MOS configuration, provided the
situation helps you to do so. We as I said that we had to cover numerical examples either
in the next class or next to next class we will be talking about depending on the situation.
I think that is all we need to cover today.
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Prof. Pradip Mandal
Lecture – 58
Multi-Transistor Amplifiers (Contd.): Numerical Examples (Part A)
Dear students, welcome back to our online certification course on Analog Electronic
Circuits. Myself, Pradip Mandal, from E and EC Department of IIT, Kharagpur. Today’s
topic of discussion it is Multi Stage Amplifiers rather continuation of multi stage
amplifier. And, in the previous three lectures so, what we have seen is the theoretical
aspect of going for multi transistor amplifiers where we do have mixed configurations
namely CE, CC and so and so.
Today, we are going to discuss little more about numerical problems and demonstrating
the same conclusion what we have discussed theoretically.
So, as I said that our according to our over overall plan we are at multi transistor
amplifiers and theoretical parts of CE-CC, then common source-common drain, then
common collector-common collector, Darlington pair. Those configurations it has been
discussed from the circuit analysis point of view and today we are today we are going to
have more numerical problems.
798
So, here again the same summary here the concepts we already have covered particularly
the theoretical aspects of mixing different configurations are covered. And, we are going
to discuss about numerical examples of particularly for CE followed by CC common
collector stage to enhance the bandwidth of the amplifier and. So, similarly for MOS
counterpart common source followed by common drain, it gives the enhancement of the
bandwidth.
So, these two configurations are for bandwidth enhancement and the third example it is
to demonstrate that increase of input resistance Rin. So, compared to CE amplifier
whatever the input resistance we have seen here we will demonstrate that if you precede
this circuit by common collector stage the input resistance it is getting increased.
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So, let us go to the numerical example. So, this slide is a recapitulation of one of our
previous numerical examples where we have discussed about CE amplifier having fixed
bias arrangement and different parameters are given here including the supply voltage of
12 V, then device parameters including β of the transistor, early voltage, then VBE(on) and
then also we do have the bias circuits resistances are given here RB then collector resistor
and so and so.
And, the coupling capacitors information are also given and then the device in intrinsic
capacitances namely Cπ and Cµ are given are here as. So, this is Cπ as and it is value it is
given 10 pF and C mu it is 5 pF. And, based on that information what we have done is
that we obtained operating point. So, just for your information I will repeat some part of
it and then we will see that how enhancement can be made on this one.
So, let us try to see the operating point of the transistor. So, whatever the arrangement we
do have here namely the fixed bias VBE and then VBE at this node essentially the VCC it is
directly coming to the base node through this RB and if I consider the KCL as you may
recall KCL from supply voltage to ground and the drop across this RB then VBE drop we
can get the expression of the IB and then we can get the numerical value of the IB.
So, we can say that VCC ‒ VBE(on). So, that = IB × RB. So, that gives us IB = .
So, it is value it is now . So, that gives us the IB current of 20 µA and
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then using this information and the β information we are getting the collector current
which is equal to 2 mA.
Now, with this information we can find the value of the small signal parameters namely
gm. In fact, let me complete this part and then I will be coming to the small signal
parameter. So, we do have IC = 2 mA then drop across RC = (2 mA × RC it is 3.3).
So, that gives us VCE = (12 V ‒ 3.3 × 2) which is 5.4 V. So, the operating point it has
given here and based on this operating point we can now calculate the small signal
parameters value namely gm = and this is ℧ and then the rπ which is .
So, that = 1.3 kΩ and then ro it is . So, that = , 50 kΩ. And, from that we can get the
voltage gain. So, now, we obtained the small signal parameter now we can get the
voltage gain. So, voltage gain it is gm(RC ⫽ ro). So, the gm we have and RC it is 3.3 k ⫽
50 k. So, probably you can approximate this by 50 or probably you can calculate these
parallel resistances together and then you can find what the output resistance is.
So, that is coming close to 3.1 in my calculation it is 3.1. So, that gives us . So, that is
230, in my calculation it is 238. So, that is the gain we are getting. Now, next thing is
that we can find the lower and upper cutoff frequency.
So, this is the; this is the exact statement of the problem we have address earlier. Now,
for our main focus to demonstrate how the bandwidth it will be extended we can
probably calculate only the upper cutoff frequency using whatever the information we do
have and you may recall the upper cutoff frequency it is considering whatever we do
have here.
So, upper cutoff frequency let me use the space it is expression is then Rout of this
stage multiplied by whatever the CL we may be having and the value of the CL it is given
100 pF. So, that multiplied by CL and this resistance if I call RO, let me call this is ro and
we already have done this calculation on this ro which is 3.3 k ⫽ ro here.
So, the value of this upper cutoff frequency can be obtained by considering that 3.1 k
multiplied by 10 sorry 100 pF which is 10‒10. And, that gives us I have done the
calculation for you. So, this is coming 513 kHz.
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So in summary what we have circuit performance why should you have the circuit gain
is 238 and then the upper cutoff frequencies 513 kHz. Now, the exercise we are going to
do it is that we are going to put in this case instead of putting the capacitor here we can
probably directly put a CC stage here and rest of the things we will be keeping same.
And, then we will see that how this bandwidth particularly bandwidth is getting extended
by putting the CC stage there.
So, in the next slide we do have the a CE followed by CC and the information about all
these biases are maintained namely R1 earlier it was RB and then R2 it is actually the RC
of the first stage and then we do have the CC stage. So, the CC stage it is this has been
added here and the value of this resistance it is bias circuit it is given you as 1.2 kΩ and
the C1 and C2 we are keeping same. C1 and C2 it is 10 µF and then CL instead of
connecting the CL at this node we are connecting the CL after the CC stage.
And, to get the overall gain starting from the primary input to primary output first of all
this part we already have done and we have seen that it is gain it is if I call AV1 it is gain
it is 238 and then it is output resistance if I call RO1 which is 3.1 k and then. So, these
two information are important and then to get the overall circuit performance we need to
see what is the; what is the small signal parameters we do have out of this CC stage. But,
to get the small signal parameter we need the operating point of this Q2, so, how do you
find?
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We know that dc voltage coming here it is 5.4 V in our previous analysis we have done
that. So, if I say that we do have a 5.4 V DC. So, that is 5.4 V along with it is Thevenin
equivalent resistance which is RO1. So, that is 3.1 kΩ that is coming to the base of
transistor-2 and the transistor-2 emitter of transistor-2 it is connected to ground through
this R3 and R3 it is 1.2 kΩ. So, this is our output and this node it is connected to the
supply 12 V.
Now, if I analyze this circuit and again if I consider device parameter same as Q1 namely
VBE, β and early voltage is same and then analyzing this loop what you can get is the
value of the IB value of the IE and so and so on. So, you may ignore the drop across this
resistance due to flow of IB. So, you can see that this 5.4 V it is directly coming into this.
So, we can say that VBE2 it is approximately equal to 5.4 V.
And, then we do have 0.6 voltage based to emitter voltage and then we can see what is
the voltage here coming here it the voltage DC voltage coming here it is 4.8 V. So, that is
the emitter voltage and that gives us the current flow through transistor-2 which is .
So, we can say that the emitter current it is equal to 4 point not 4.2 4.8. . So, that gives
us 4 mA of emitter current and we may approximate that the collector current it is also
equal to emitter current. So, IE2 = 4 mA.
So, using this information what we can get the small signal performance parameter
namely gm2. So, the gm2 it becomes IC divided by thermal equivalent voltage which = ;
that means, and the rπ2. So, that is that is . So, that is equal to 650 Ω ok. So, you
might have observed that the rπ here and rπ here they are different because they are
current levels collector current levels they are different. Now, using this we can find
what will be the gain of the CC stage.
So, what is the expression of the gain of the CC stage? If I call this is AV2 gain voltage
gain of the second stage if of course, it will be very close to one that is the anticipation,
but to get precise value you may recall it is expression it is (1 + β) into the resistance
here in fact, you may ignore ro. So, of course, this ro it is 25 kΩ.
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And, this 25 kΩ you may ignore compared to whatever 1.2 kΩ we do have and then the
expression of the voltage gain it will be (1 + β) multiplied by this R3 in fact, this is in
parallel with ro2 which can be ignored and then (1 + β2)(R3 ⫽ ro2) + rπ2.
So, if I consider we do have a signal at the base and how much the voltage it is coming
here that can be obtained by considering this. You may recall that the this equation in
case if you are unable to really you know intuitively get a feeling of that you can think of
that we do have rπ here and at this point we do have an impedance coming from this
resistance seen from the base. And, this resistance it will be seen at the base after
multiplying with (1 + β) and this resistance of course, we do have ro2 it is coming in
parallel.
So, (β + 1) (R3 ⫽ ro2) is essentially the resistance at this emitter and effect of this emitter
rather seen at the base. So, whatever the impedance we can see here from here to here
effective impedance seen from the base it is (1 + β) times the corresponding resistance.
But anyway you can consider their numerical value and so, this is 101 × 1.2 K and then
we do have 101 × 1.2 K + rπ2 which is 0.65 K. So, that is giving very close to 1. In fact, I
do have the calculation for you it is coming 0.995.
So, we do have the first stage gain here and then we do have the second stage gain. So,
the overall gain. So, we can say the overall gain AV_overall = AV1 × AV2 and also of course,
we will be having some attenuation due to the loading effect coming there. So, we will
see this part. So, what will be this part? It is the impedance at this node essentially it is
loading the first stage. So, this factor whatever the question mark we are seeing here let
us try to see that part.
It is the attenuation coming due to the loading effect and the load here it is the rπ2 + (1 +
β)R3 and that is loading the first stage which means I have to consider output resistance
of the first stage. So, this divided by rπ2 + (1 + β)R3 + RO1. So, this is the attenuation
factor.
So, that factor if you put it here in fact, if you put the value here whatever the value you
will be getting this factor it is approximately coming very close to 1 in my calculation it
came 0.975. So, I should say that the overall gain it is 238 × AV2 which is 0.995 and then
multiplied by 0.975 and that is coming very close to the original gain and it is in my
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calculation it comes 131 ok. So, that is a change, but the change is very small as
anticipated.
Now, next thing is that how the CC stage it is enhancing the bandwidth. So, how do we
calculate the bandwidth first of all we have to see the corresponding gm and then we have
to see what is the corresponding impedance coming there namely we need to calculate
what is the RO coming from the CC stage namely RO2 we need to find and then we can
find what is the corresponding cutoff frequency defined by this RO2 and CL together and
then also we do have another candidate to define the cutoff frequency that whatever the
input capacitance we do have coming from the second stage multiplied by whatever RO1
we do have.
So, to calculate the upper cutoff frequency we have to consider these two time constant
ok. So, I will be using the same slide. So, let me clear whatever the clumsy equation now
we have created.
So, let we consider the output resistance here. So, if I call this is RO2 ideally, if this node
is AC ground then RO2 should be equal to ⫽ R3 ⫽ ro2. So, that we may approximate
by and that is that is 6.5 Ω, but then this is not possible. We cannot do the AC
ground here. So, we have to consider the corresponding resistance here.
805
In fact, for the CC stage we have to consider that the resistance at the base and this
resistance is RO1 right and then we have to see what is the corresponding output
resistance we do have. That can be obtained by considering the considering the drop it
will happen across this rπ in presence of the RO1 while we are see stimulating this circuit
by say vx.
So, I should say if I am applying vx at the emitter then base to emitter voltage it will not
be exactly ‒ vx. As a result whatever the internal current source namely gmvbe; so, this vbe
part it will not be entirely coming from ‒ vx rather this vx it is having some attenuation
here. So, what is the attenuation coming due to this RO1 which is unbypass that is .
And, in this case so, I have to consider rπ2, this rπ2 and then of course, if I multiply with
vx so, that gives us ‒ vbe.
So, whatever the expression we obtained for this RO2 assuming that it is base node it is
properly getting grounded that need to be change. So, what is the changed output
resistance RO2 should be multiplied by this attenuation factor. So, that attenuation
factor it is .
So now we know the value of different parameters. So, we do have this is and then rπ
it is some rπ it is 0.65 k and RO1 it is RO1 earlier we have calculated it has 3.1 K. So, if I
consider that 3.1 K and 0.65 3.1 K and that give us the different value of on this RO2 and
I do have this calculation for you. It is coming 36 36.36 Ω.
So, note that this is different, but still it is quite low and the pole it is getting created by
this RO2 and then the CL. So, that gives us the new upper cutoff frequency. So, if I call
this is f′U and if you find what will be it is value that is .
So, that is so, that is becoming 2π × 36 × 10‒10 F and in my calculation what I was
getting here it is 43.75 MHz. So, now, we may recall this is you can compare this value
and previously obtained upper cutoff frequency, originally it was fU that was 513 kHz if
we consider only this circuit, then if we connect the CL here then the bandwidth the or
the upper cutoff frequency it was this one.
806
But, of course, this is not this is not this is not the only candidate to define the upper
cutoff frequency you also have to see that what is the fU we are getting due to this RO1
and the input capacitance coming from this stage. And, what is the input capacitance we
do have? Cin2 = Cµ and the value of the Cµ it is given here it is 5 pF. So, I should say an
intrinsic or I should say device capacitance of say 5 pF and then RO2 which is a 3.1 K
they are providing the other possible option of the upper cutoff frequency.
In fact, not only you have to consider RO1 you have to consider the input resistance of
this circuit also. So, at this point let me use different color here at this point whatever the
pole we will be getting it is coming from we do have RO1 and then Rin of the second
stage and then we do have the capacitance coming from the second stage which is Cin2.
So, I should say these two resistors they are coming in parallel to define the
corresponding R.
So, the new candidate or the other candidate to define the upper cutoff frequency let we
call it is f′′U and so, this is equal to then 3.1 and we do have the this resistance. Of
course, we the that resistance we have calculated, but somewhere we have we have
missed it and what is it is expression it is rπ2 in series with (1 + β)RO2.
So, you may ignore this part, but even if you consider this the corresponding resistance
here it is coming very close to RO1. So, you can consider this is RO1 multiplied by now it
is 5 pF, instead of having 100 pF of CL now we do have only 5 pF seen by this resistance
and this is 5 × 10‒12 and it is value incidentally it is coming 10.6 MHz.
So, I should say even though we do have now two candidates to define the upper cutoff
frequency one is f′′U and also we do have f′U. So, these two if I compare this is lower. So,
eventually this is defining the upper cutoff frequency, but still if I compare with the
original upper cutoff frequency this adding the CC stage it is helping us to extend the
bandwidth.
So, in summary we can say that if the original CE amplifier it is having a frequency
response like this. So, it is having a gain. So, this is AV1 in dB and this is frequency in Hz
in log scale and this one was 513 kHz was the upper cutoff frequency. Now, by adding
this CC stage what we have here it is the gain got slightly decreased, but then bandwidth
got extended and this bandwidth it is 10 MHz. So, almost 20 times enhancement of the in
807
the bandwidth. And, this is due to so, this is due to the CC stage in fact, CE and CC
together ok.
So, let me take a short break and then we will come back for the mass counterpart and
then we will see that they are also by using common drain stage how it is helping us to
extend the bandwidth ok.
Thank you.
808
Prof. Pradip Mandal
Lecture – 59
Multi-Transistor Amplifiers (Contd.):
Welcome back after the short break. So, we are talking about the CE-CC and now we
will be moving to MOS counterpart.
809
So, in the next slide we will be talking about see common source amplifier again this
numerical exercise we have seen before. So, this is prime and the main common source
amplifier and sorry and then we have the information given here about the device namely
which is 1 mA/V2, threshold voltage it is 1 V, supply voltage it is 12 V and so and
so.
And, we have seen that using this information we obtain VGS = 3 V and then IDS we
obtain it was 2 mA and then corresponding small signal parameter gm it was 2 mA/V. So,
the corresponding voltage gain; voltage gain it was gm into output resistance and you
may ignore the ro or other ro we may consider this is very high assuming λ is very small.
So, the voltage gain it was gmRD and so that becomes 2 m × RD is 3 k; 3 k.
So, the corresponding voltage gain it was only 6. So, whatever it is and then the output
resistance for this case we see it is primarily defined by RD and that is 3 kΩ. So, the
upper cut off frequency for this case fU it was into load capacitance of 100 pF. So, it
was and then 3 k into this one 100 p; that means, 10‒10 yeah. And in fact, if you
calculate it this gives us 530 kHz.
So, the common source amplifier it is primarily it is having a gain of 6 and then upper
cut off frequencies 530 kHz, we are not going to calculate the lower cut off frequency
primarily because our intention here is to see the enhancement of the bandwidth by the
810
use of common drain stage. So, please recall or try to remember this information. In our
next exercise where we will be cascading this CS stage by common drain stage.
So, we do have in the next slide we do have that example here. So, all the information’s
are we are keeping it same we do have additional common drain stage coming out of the
transistor M2 and the its bias circuit R4 and R4 it is given here it is 1.5 kΩ
Note that its biasing it is done directly from the DC voltage available at the drain of
transistor-1. So, the DC voltage coming here if you see the current flow of here it is 2
mA and R3 it is 3 k. So, drop across this 3 k it is 6 V. So, we can say that we do have a
DC voltage of 6 V coming to the gate of transistor-2.
So, we do have R4 here 1.5 k and its drain it is connected to Vdd. Now, how do you find
the corresponding current here IDS? So, there is a method first of all this IDS flowing
through this R4 creating a drop which is defining the source voltage here and then at the
gate we do have 6 V.
And since there is no current flow even if you consider the 3 k resistance here, but still
we can say that gate voltage it is 6 V. So, if I consider the loop here if I consider this
loop and if I consider we do have 6 V coming here. So, we can say that the IDS =
whatever ( ) and then if I multiply with R4.
811
So, if I multiply with R4 here. So, that gives us the source voltage, but then gate voltage
it is 6. So, we can see that V GS; VGS ‒ Vth = 6 V ‒ this Vs ‒Vth is 1 V ok. And so what is
this one we do have 5 here and then Vs we do have this expression which is given here.
So, you can say directly this is 5 ‒ R4 ( ) . So, that is the expression of the
VGS we are getting. So, now, we are we do have one equation here which is in terms of
VGS ‒ Vth. So, if we can find the VGS ‒ Vth, then we can see that we can find the
corresponding current.
Now, since this equation it is coming primarily in terms of VGS ‒ Vth let me consider this
is x. So, we can say that this is x = 5 ‒ R4 it is 1.5 k and it is 1 m. So, we can say k
and m they are getting cancelled and then we do have VGS ‒ Vth, so that is x2 all right
yeah.
So, we do have by 2 also yes. So, now, from this one what we can we can rearrange this
equation. So, that gives us in fact, 3x2 + 4x ‒ 20 = 0. So, if you solve this equation
second order equation what you will get here is one solution it is x = 2, you will get x is
having some other value also, but that value it is impractical.
So, we can see that x = 2 V which gives us VGS = 3 V because x is VGS ‒ Vth. So, this
quantity VGS ‒ Vth we have considered it is x. In fact, if you plug in this VGS value, we
can get the IDS equals to we do have IDS = mA/V2.
So, here. So, that is mA/V2 VGS ‒ Vth and that is 22. So, that gives us 2 mA. So, we do
have a current flow here it is 2 mA. In fact, you can verify that if 2 mA of current is
flowing here from drain to source the drop getting created here it is 3 V and we do have
6 V here.
So, that makes the VGS is also 3 V which is consistent because if I am having VGS 3 V
then only it will support the current of 2 mA of course, assuming this transistor it is in
saturation region of operation. So, that is how you can get the operating point of the
transistor in CC stage and using that you can calculate what will be their corresponding
gm.
812
So, the gm of this transistor it is let me create some space here. So, gm of transistor-2 it is
we do have × (VGS ‒ Vth). So, here also we got gm2 = 2 mA/V and then the output
resistance and of course, since we do not have the equivalent whatever rπ we are having
in BJT.
And so the calculation here it is much simpler and you can approximate that the gain
here Av1, it is very close to 1 and output resistance not Av1, Av2 rather second stage gain
and output resistance of the CC stage it is ⫽ R4 ok. So, it is 0.5 k and R4 it is 1.5
k.
So, that gives us I think 300 something I do have a calculation yeah. So, that gives us
375 Ω. So, since the gain here it is approximately 1, so the overall gain it is primarily
coming from the first stage. So, the overall gain Av_overall it remains 6 only, but then the
upper cut off frequency fU.
Now, if I call it is f′U it is having 2 candidates to define the upper cut off frequency; one
is Ro2. So, this is 2πRo2 and the corresponding load capacitance we do have CL. So, if we
connect the CL here. So, then the upper cut-off frequency it is and yes I do
have calculation here, it is 4.24 MHz.
813
So, you may require you can compare this frequency with respect to whatever the
original pole of this CS stage it was there. So, that was fU it was 530 kHz. Now, also we
have to consider the other candidate of defining the upper cutoff frequency coming from
this point and that is let me denote that by f′′U and its expression is and then Cgd.
So, Cgd it is 5 pF and. So, the value of this this cutoff frequency in fact, since this is 3 k
and this is 5 p earlier we made this calculation and it was 10.6 MHz.
Student: (Refer Time: 15:54).
Now, if I compared these two poles together of course, this is lower. So, the net upper
cutoff frequency it is four point, so 4.24 MHz. So, here also the same conclusion it is
namely originally the CS common source amplifier it was having a gain of 6 and then it
was having a; it was having the upper cutoff frequency it was 580 kHz. Now, we are by
the virtue of the common drain stage along with the CS.
So, this gain it is almost remaining the same and its bandwidth got extended to 4.24 MHz
ok. Now, so that gives us the flavour of why we go for cascading CC and CD. In fact,
you can try out with the other CE amplifier which is cell biased configuration.
So, this exercise we have done before. So, probably you can calculate what is its voltage
gain and the upper cutoff frequency.
814
And then you can compare this with the cell biased CE amplifier sorry cell biased CE
amplifier along with say CC stage. So, we do have the CC stage here and you can find
that again this CC stage it is helping to extend the bandwidth. So, probably you can work
out on this one. I do have another interesting example, but again due to the probably the
shortage of time.
I will just give you some brief and then I will be leaving it to you to solve this problem.
What we have here it is yeah; what do we have here it is this is the CE stage assuming
815
we do have a meaningful DC voltage coming here from the previous circuit and then that
is preceded by CC stage. Note that I am not providing any separate bias here for CC
stage and on the CE stage.
So, we are assuming that whatever the current is coming from Q1, its emitter current it is
getting consumed by the base terminal of Q2. So, I should say that IB2 = IE1 indicating
that the current level here it is much lower than whatever the current level we do have. In
fact, if you consider for both the transistors β is say 100.
So, whatever the current we do have you can imagine that this current it will be 2 order
magnitude lower. So, say for example, if I consider IC2 is 1 mA, then IC1 it is only 10 µA
and the corresponding IB1 it is only 0.1 µA.
So, we require very very small current here as a result the corresponding R2 here; R2 here
we are expecting it will be sorry R1 resistance bias resistance R1 to support this much of
current it should be definitely in maybe 10s or maybe even 100s of MΩ. So, if you put
some value of say even say close to 10 MΩ you will see that the corresponding current
here it will be quite high.
But, whatever the biasing condition you can get with this one probably you can see and
then you can find what is the IC2 and then IC1 and then from that you can calculate what
is the rπ2 and rπ1. From that you can see what is the input resistance it is coming here and
you will see that by adding the CC stage the input resistance it will be quite high.
So, the input resistance expression you may recall it is coming from R1 in parallel with
whatever the input resistance we can see at the base of transistor-1 and that is rπ1 coming
in series with (1 + β1)rπ2 and then if I consider this is ac ground.
So, only this much I will be having. So, you can see that this rπ1 since its current level it
will be quite small this will be quite high and then even though say rπ2 may not be
having. So, high value, but since it is getting multiplied by β1 the corresponding value of
this resistance it will also be quite high as a result this Rin1 it may be in the order of MΩ.
So, if I am having only on the other hand if I consider the input resistance of this stage
only the rπ2, it may be in the range of kilo ohms and the corresponding resistance we are
816
getting here it is getting multiplied by 100. So, I should not say MΩ it will be in the
order of sub MΩ I should say 100s of kΩ.
So, you can solve this problem by considering say R1 is equal to say this MΩ and maybe
you can consider this resistance of 1.2 k sorry you should not take 9.9 MΩ rather 99 MΩ.
You can consider 99 MΩ and then you can calculate what is the corresponding input
resistance here see.
I think let me then summarize most of the things whatever we have planned we have
covered here. So, in this session what we have learned here it is the usefulness of the
common collector and common drain and we have we have demonstrated through
numerical examples.
Basically, by considering CE and CC together and then CS and CD together to enhance

the bandwidth upper cutoff frequency particularly getting increased by a factor of as is
maybe a factor of 10 or more. And, also we have given one framed one example CE if
preceded by CC to (Refer Time: 24:32) increase the input resistance Rin by a factor of
100 ok. I think that is all I need to share.
Thank you for listening this talk.
817
Prof. Pradip Mandal
Lecture – 60
Multi-Transistor Amplifiers (Contd.): Numerical Examples (Part C)
So, now, we do have another example, where we do have the CC followed by CE

amplifier. And what we have here it is, the CC stage it is directly getting coupled to CE
stage. And you can see here the in the CC stage, basically this part is the CC stage and
normally we do have a current sink here for proper biasing; but here we assume that
whatever the emitter current we do have out of Q1 that is entirely getting consumed to
the base or base terminal of Q2. So, now hence we may assume that, this bias circuit is
not required.
On the other hand for Q2 which is forming the CE amplifier, so we do have CE amplifier
here and for the CE amplifier while we are feeding the signal at the base, so along with
the signal we also require meaningful DC voltage at the base of Q2. Now again here we
assume that DC voltage of Q1, it is sufficient to feed the signal at the base of Q2; or you
may say that, whatever the emitter current we do have out of Q1 that is good enough to
make a bias of the Q2. So, in summary what will I like to say that, Q1 is biased by base
terminal of Q2. So, it is biased at its emitter by the base terminal of Q2.
818
On the other hand Q2 is biased at it at its base terminal by emitter current of Q1. So, they
are, I should say they are helping each other to have a mutual bias and hence we can
simplify the biasing arrangements, so that should we do have very simple bias here.
Now, here for comparison with our previous circuits, we are setting the value of this R1
such that the current flowing through this Q2 we are expecting that it will be say 1 mA.
So, if the IC of transistor-2 it is 1 mA and then we like to retain the same DC voltage at
its emitter. So, we are maintaining RE 1.2 k and then now the required current here; since
is its β it is 100, so the required current here it is close to 10 µA. And if I say that this 10
µA current of transistor Q2 based base current of transistor Q2= the emitter current of Q1.
Then again, because the β of Q1 is also 100, the required base current for Q1 it is I should
say . So, that is in the order of sub µA. In fact, so this = 0.1 µA. So, the required
resistance here it need to be very high and I just made some calculation and it is observed
that, if R1 it is say 98 MΩ, then we are getting this current is 1 mA. So, I will show you
the simple calculation to get this the emitter current of Q2 = 1 mA.
819
So, if I start from say 12 V here and then we do have 2 VBE drop here; and if I assume
that these two VBE drops are ≈ 0.6, then the remaining drops namely a 10.4 V it is across
RE and R1. So, I should say that 12 V ‒ 1.2 V due to the 2 VBE = IB1 × R1 + IB1 (1 + β1),
so that gives the base current of Q2. And then if I multiply with (1 + β2), so that gives us
the emitter current here. So, that multiplied by RE is the drop across this RE.
So, here we know β, we know R1 and then RE and from that we can find what will be the
IB. So, this IB1, it becomes. So, this is . So, if we put the value of this
resistors, then what we are getting it is; so 10.8 divided by, we do have 98 MΩ, then (1 +
β1) is 101 multiplied by a 101 multiplied by RE it is 1.2 kΩ.
In fact, that gives us close to 0.1, to be more precise in my calculation it came 0.097 µA.
And from that we can get IE1 equals to. So, if I multiply this by 101, we do get 9.8 maybe
9.85 µA and that gives us the base current IB2 which is IE1 = 9.85 µA, in fact to be more
precise. And then we are getting RE2 which is (1 + β that is 100) × 9.8 µA, so that gives
us 1 mA.
So, now, we have the collector current; so we can say that, IC1 it is approximately equal
to same as this IE, so that is 9.8 µA. And then we also have IC2, we can approximate that
this is by 1 mA. And from that we do get rπ1 and then rπ2; rπ2 it is 2.6 kΩ, earlier we have
done this calculation. And on the other hand rπ1 and its current is quite low; so in my
calculation it was around 265 kΩ, I think around on that.
820
So, if I am having these two resistances are known, and then we can find what will be the
input resistance of this circuit. So, what is the input resistance that is what it is very
important for this circuit, this configuration; because we like to increase the input
resistance by putting this CC stage. So, the input resistance here, Rin it is parallel
connection of R1 and whatever the resistance we do have. So, let me use this space here,
Rin equals to R1 coming in parallel with whatever the resistance we do have. And what
we have, the resistance here it is rπ1 coming in series with (1 + β1)rπ2.
So, we are ignoring this ro here, we consider only this rπ2 and that gives us roughly; so
we can say that, this is 100 and 101 and 2.6 kΩ it is getting multiplied by that factor and
then we do have 265. So, roughly you can say that this is 530, around 530 kΩ in parallel
with R1 which is 98 MΩ, ok.
So, then you may approximate that this is by 530 kΩ. So, if I am having only the CE
stage, the input resistance here it was only 2.6 k; but if I am putting the CC stage in front
of that, the corresponding input resistance it is getting increased. So, that is why for op-
amp whenever we like to increase the input resistance, we put the CC stage in front of
differential pair; whenever we will be talking about differential amplifier, we will discuss
it further. And instead of using this CC stage, in fact people use something called
Darlington pair, so we will see that. But before that, let we see the input capacitance of
this circuit. So, let me clear again to make the space.
821
So, Cin of the circuit it is we do have Cµ of transistor-1. So, we do have Cµ of transistor-1
and this node it is AC ground. On the other hand this Cπ, it is breezing the input base
terminal and emitter terminal of Q1 and its gain it is very close to 1, so we may say that
effect of this Cπ it is negligible. So, this is helping us to reduce this input capacitance.
And you may recall that if you ignore say CC stage and if you are directly considering
this is the primary input, then the input capacitance at this node it was Cµ2 multiplied by
it is gain, the voltage gain; and the voltage gain here it is we know it is quite high and
then also the Cπ2.
So in fact, this is dominating and the Av and Cµ, so Cµ2 × gmRc that is what primarily we
do get, the gain plus 1. So, definitely if you compare this value and this value, this is
much smaller. So, again putting the CC stage, it is helping us to reduce the input
capacitance and to increase the input resistance; that may be useful in case if you are
feeding the signal from a signal source having very high source resistance Rs.
I compare to CC-CE amplifier, there is another configuration something called

Darlington pair and we will see that what the difference basic difference is. In fact, their
configuration wise they are very close; but there is a small difference, in the next slide
we will be discussing about that.
So, here we do have this Darlington pair. So, you can think of this is one transistor; its
base terminal is here and then its collector is here and then emitter it is here. And then if
822
you put this structure or you can say composite pair in CE configuration what we can get
it is, we will be getting the same gain of CE amplifier namely gmRc. But the main
advantage here it is, the input resistance here it will be quite high.
And for our comparison with the previous circuit, where the collector of Q1, it was
connected to supply voltage Vcc; on the other hand here in the Darlington pair, collector
of the first transistor it is connected to collector of the second transistor. In fact, both the
collectors are connected together. Now DC operating point wise, both this circuit and
this circuit are I should say very close to each other; that is because whatever the
collector current we are drawing here, which may be flowing through Rc now, unlike the
previous case, where the collector current of Q1 it was directly coming from Vcc.
But since this current is very small compare to the collector current of Q2; so we can say
that, all practical purposes the operating point of this circuit and this circuit they are
same. But the main difference here it is, in the previous circuit Cµ of transistor-1 it, the
other end of Cµ it was connected to the supply voltage which is AC ground. As a result
the input capacitance here it was only Cµ and that is as is; whereas, for this case the Cµ
here it is connecting the input terminal to the primary output of the circuit.
And we know that from this primary input to this primary output, we do have very good
gain. So, the consequences that, the Cµ of this Q1 it is getting multiplied by Miller’s
factor and that produces big amount of input capacitance. So, the Cin it is Cµ1 (1 + gmRc).
So, I should say that this circuit is definitely better in case if you are looking for an
application where input capacitance is very important; otherwise the other performance
matrices they are identical. So, maybe you can calculate the corresponding gain and all
offline. But so far whatever the things we like to discuss, namely the main purpose of
using CC stage to enhance the performance of CE amplifier that is done.
823
So, in summary what we have covered so far it is that, we have talked about the
usefulness of common collector and common drain stage through numerical examples.
And those examples are primarily CE followed by CC, CS followed by CD, so these two
it was covered before. And just now what we covered it is common collector followed by
CE stage; rather this CE stage it is the main amplifier, which is preceded by the common
collector stage.
Or equivalently you can say that Darlington pair we can put in amplifier configuration
and the then there we have seen that, input resistance it is getting enhanced. This is
helping not only input resistance got increased, but the input capacitance also got
decreased. I think that is all I like to share.
824
Prof. Pradip Mandal
Lecture – 61
Multi-Transistor Amplifiers: Cascode Amplifier (Part A)
Dear, students welcome back to our NPTEL online certification course on Analog
Electronic Circuits, myself Pradip Mandal from E and ECE department of IIT
Kharagpur. And today’s topic of discussion, it is Multi - Transistor Amplifiers in fact,
this is continuation of our previous discussion.
Now the plan overall plan if you see according to our weekly plan so far we have
covered CE – CC; CS - CD and CC - CC; Darlington pair etcetera both theory as well as
numerical examples. And we are going to discuss about Cascode Amplifiers which are
essentially I should say CE this should be CE, CE followed by CB and CS followed by
CG.
So, I should say this is combination of common emitter amplifier with common base. So,
this is BJT version and this one is a MOS version common source followed by common
gate.
825
So, the concepts we will be covering in this lecture is the following. So, we shall start
with CE followed by CB and in fact, with appropriate modification. It gives us a
relatively simple circuit configuration which is commonly known as cascode amplifier
so, that amplifier we will be discussing in depth. And then this is a course with using
BJT. So, likewise we do have cascode amplifier using MOSFET transistor and, but prior
to that since it is essentially coming from a common source followed by common gate.
So, we shall start with common source followed by common gate configuration and then
we will simplify to conclude to cascode amplifier using MOSFET. I like to say that you
might have observed that if we consider simply common emitter amplifier, its gain is
typically quite high more than 100. On the other hand if I consider common source
amplifier it is gain it is not so high. So, we must be having some alternative for
particularly for MOSFET version otherwise that circuit may not be really much of an
use. And this cascode amplifier is one of the configuration in a MOSFET amplifiers
which is essentially helping to get the higher gain.
So, may not be the cascode amplifier may not be very popular in in the in the domain of
BJTs amplifiers, but it is quite popular in the community of MOSFET. So, anyway both
the circuits we will be discussing. So, let us see first the CE and CE followed by CB and
then cascode using BJT.
826
So, to start with you may recall we made a summary that a different performance
matrices of CE amplifier. So this is the basic CE amplifier configuration and then we
also have different performance matrices and their expressions and qualitatively we said
that some of them are high, some of them are not so high or whatever it is and in fact,
even though Ro it is high it is not good for voltage amplifier. So, that kind of discussion
we already made. So, likewise we also have discussion related to a common base,
common collector, this part we already have discussed so we will not be covering now.
So, we need to basically revisit this important property of CE and CB to motivate

ourselves that combining CE and CB it is giving us a better performance. So, this is what
the performance summary of CE amplifier, likewise we do have the performance
summary of a common base amplifier.
827
So, this is the corresponding circuit configuration common base circuit configuration and
you may recall that it is voltage gain it is quite good, but we assume that the signal
source resistance is 0 and then its main property here it is that input resistance it is low,
as a result it is input port it is not really good for voltage feeding. So, we will see that,
but then of course, this property it is helping to make the port suitable for current signal
feeding. On the other hand the output resistance of the amplifier it is very high so, that
also makes the circuit suitable for current mode signal at the output port.
So, then also it is input capacitance its a low namely only the Cπ and the current gain on
the other hand it is not good. In fact, it is theoretically it is less than 1 though it is very
close to 1. So, now, if we put say performances of CE and CB together to construct a
new configuration called CE-CB, then let us see what kind of performance we do expect
yeah.
828
So, this is the summary and as I said that at present we are interested to focus on CE and
CB, this we may not be concentrating. And our main purpose here is of course, CB can
be utilized for current buffer, but today we are going to discuss more like application to
boost the voltage gain. Before I go into that I must say one important point I missed it
whenever we have discussed about the CC amplifier we have seen that its voltage gain it
is slow in fact, it is very close to 1.
And whenever in CC stage whenever we have given the input at the base and we are
observing the output here and we have seen that the gain it is close to 1 and the phase
also it is a phase shift is also 0 degree. So whatever the input signal you are giving at the
base in fact, almost to the same signal it was coming to the emitter. So, that is why this
CC it is having other name which is also quite popular it is referred as emitter follower.
So, which means that emitter node it is following the base node.
So, the CC stage whenever we are using as a voltage buffer it may be referred as emitter
follower. So, likewise when you talk about say common base configuration and their
current gain it is approximately 1. So, whatever the input current we give so, we do have
the CB stage here, whatever the input current we give here almost the same current we
do get at the output.
So, this circuit CB circuit it is the other name of CB circuit it is something called current
conveyor. So, it coveys this current from emitter node to collector node almost with the
829
same magnitude but the base basic purpose here it is that impedance at this port at the
emitter port it is quite low whereas, impedance at the collector port it is high. So, this
current conveyor basic purpose of the current conveyor, it is taking the or rather taking
the receiving the current at the low impedance port and it is delivering the current at the
high impedance port.
On the other hand the complimentary things are happening for voltage follower or I
should not say voltage follower emitter follower, the input voltage it is getting conveyed
from the base terminal to the emitter terminal. And so, here it is while it is conveying it
is input port resistance it is high and then it is delivering the signal at the emitter where
the output port resistance it is quite low. So, these two configurations common collector
and common base they do have their dual property and they are essentially used as
voltage mode and current mode buffer respectively ok.
So, now coming back to whatever we are about to say the application of the common
base to enhance the circuit gain. So, we will be seeing that how this this will be
enhancing the gain.
So, we do have the CE stage here and then we do have the CB stage as the name
suggests that the output of the CE stage we like to feed it here and if we are feeding the
voltage here and there may be a different possibilities, we may remove the capacitors or
830
at least we can say that we can keep only one capacitor. So, if I am putting one capacitor
here, then the corresponding configuration becomes like this.
So the output of the CE stage namely collector or Q1 it is and getting connected to the
emitter of Q2 through a DC blocking capacitor. So, that the operating point of the second
stage it is it should not get affected by this circuit so that is the purpose. Now we will see
that in fact, the condition of the of the DC operating point of CE and the CB stage is in
this connection they are remaining isolated, but then of course, the signal it is going from
the first stage to the to the second stage at its input.
Now we can modify this this connection without really putting this capacitor here, but
then of course, we should be having a meaningful connection. And in the next slide, we
will be discussing about how we can cleverly directly couple these CE and CB together
and that gives us the new configuration called cascode configuration.
So, I should say that cascode circuit, it is essentially CE-CB, but I should say it is
simplified or modified version. So, here we do have the CE-CB amplifier whereas, if you
see here this Q1 in fact, whatever the DC voltage you do have here that may be useful, I
should not say DC voltage rather I should say the current. So, if you see the Q1, it
requires it is collector current and that current it is getting supplied by this R2 and on the
other hand the emitter current, DC current of Q2 need to be consumed by this circuit.
831
So, we can say that basic purpose of having this R2 and this I whatever IBIAS here maybe
along with this R4, it is essentially to bias Q1 and Q2 respectively. Q1 it demand some
current to become entering to it is collector and Q2 it is expecting it is emitter current
need to be consumed by somebody else.
So, what you are doing here it is, if we remove say this part and if you remove this part
and then if you remove the DC blocking capacitor also. Then what you can say that the
emitter current of Q2 can enter into Q1 and; that means, support this bias requirement of
Q1 and that is what exactly it is happening here. So, the emitter current of Q2 it is
entering into Q1 as its collector current. So if here at this node in fact, instead of blocking
their DC current and DC voltage we are directly rather utilizing the opportunity here. So,
that we can get rid off the bias circuits here we can we can get rid of the capacitor, but
then of course, you have to see whether everything is falling in place or not.
So, what we said here it is DC current of Q2 it is supplying require DC current of Q1, on

the other hand we are feeding the signal at the base of Q1 and we are expecting that this
vin signal it will be producing vbe signal that supposed to be producing a current here
signal current and that is gmvbe. So, along with the DC current here of course, we do have
the signal and this this signal should be successfully reaching to the collector or
transistor to which we call it is the primary output port.
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So this current this current source of course, it is having it is own conductance called ro
and then this current supposed to be successfully entering into this circuit. So, we will be
going through detailed analysis for that, but then just I like to say that instead of having
this ideal bias here. Practically we do have a potential divider constructed by R2 and R4
from the main supply Vdd here, which generates a DC voltage. Now it is also having
Thevenin equivalent resistance which is R2 and R4 in parallel and we like to keep the
base node of transistor-2 to AC ground and that is done by this capacitor.
So, in summary we require the gate bias for Q2, we require gate bias DC bias for Q1, but
then emitter bias of a transistor-2 and collector bias of transistor-1 they are eliminated by
making them helping each other right. And of course, at the collector of Q2 we do have
the biasing arrangement IBIAS we do have maybe that bias circuit is having some finite
conductance represented by R3 there ok. So, that is how we got the cascode amplifier and
as I said it is a special kind of amplifier and it is having higher gain and to appreciate or
to really acknowledge that let we do the detail analysis of the cascode amplifier.
So, we do have the yeah. So, here we do have the cascode amplifier and let us see it is
analysis, so, biasing and all we have discussed. So, let me yeah. So, we do have this
biasing and it is operating point of those BJTs it has been discussed. So, what we need to
do here, it is the R1; it is the value should be set such that the IB of transistor-1 it is
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properly set here, which produces it is corresponding collector current IC1 which is βIB1.
And that is eventually gives us the emitter current IE of transistor-2 which is IC1.
Now this current of course, it should be consistent with whatever the current we do have.
So, as long as we make sure that this current, it is consistent with IC1 then we do not have
any problem. But, then if there is any mismatch then of course, the transistors maybe this
transistor or this transistor they may be pushed into a saturated condition and that may
create ill operation of the circuit. So, definitely while we are making this biasing, we
need to be careful about that the current source here must be consistent with whatever the
current we do have here which is set by this R1 ok.
So, here we assume that this balancing of the current source and this current sink defined
by Q1, they are consistent and hence rest of the things are it is I should say it is taken
care. But of course, one minor thing that the base terminal here of Q2 should be set at a
voltage such that after deducting, it is VBE namely around 0.6 whatever the voltage you
do have that should not force Q1 into saturation.
So I should say that it is collector current should be higher than VCE(sat) and then plus 0.6.
So, that is the required voltage here. So, the DC voltage here it should be at least 0.6 +
VCE(sat) maybe whatever 0.3. So, now, this voltage if it is higher than the minimum
required voltage, then we do not have any problem, this both the transistor particularly
Q1 it will be in active region of operation. So, maintaining this voltage on the other hand
to ensure the consistency of the operation of the circuit is not so difficult. So, I think
typically that is not the main concern; the main concern is that as I said that matching
this current with this current is the main concern ok.
Now, coming to the small signal analysis so, now, let us see the small signal analysis and
in in the small signal analysis we do have voltage gain and then output impedance, input
impedance, input capacitances, those things we can compare with what are the
corresponding performance matrices coming out of simple CE amplifier. So, in the next
slide we will be doing the analysis with a small signal equivalent circuit of the cascode
amplifier.
834
So, I think you yourself can try out, but then I have done it for myself. So, here we do
have the small signal equivalent circuit. So we do have the model small signal equivalent
circuit for Q1 and then we do have small signal model for Q2. And the base node of Q2 it
is connected to a ground through this capacitor so, we are saying that this is AC ground.
Then R3 here it is connected to DC supply so that is also connected to ground and at the
input you are feeding the signal maybe the signal source maybe having source resistance.
So, we are feeding the signal here is vin and the source is having source resistance of RS.
So, this is the corresponding model for that.
Now so, we can then of course, this is the primary output so, we will be observing the
output here. So, to get the gain from this primary input to this output we need to analyze
this circuit. So, either we can analyze this entire circuit or probably we can go little
intuitive way to simplify the analysis.
835
So, let us see, what is the simplification we do have for the time being; let me assume
that this Rs equals to it is very small. So, vin it is directly coming here and that makes this
vbe = vin. So, the voltage dependent current source we do have gmvin here. So, this is
gm1vin so; that means, it is expecting that signal current it will be coming through this. In
fact, this current partially it will be coming from upper side as well as it may be coming
from this ro1. So, when I say upper side it is primarily it is coming from rπ2 as well as the
combination of whatever the circuit we do have.
So either you can say that the current here it is signal current is flowing in this direction
or you may say that the signal produced by this circuit it is getting injected here and then
part of this is going here part of this is going here and the rest of the things it is going
here and here. Now depending on the impedance offered by each of these paths, say this
path, this path and this path this current it will be getting segregated.
836
So, if you see the impedance. Now, if you look at the impedance of the main amplifier if
you see this part. So, what is the impedance, impedance of this part it is ( ), on
the other hand this is straight forward this is rπ2. So, if I say that this is the signal current
it is entering and this is the resistance which is quite high compared to rπ and maybe
compared to this. So, we may ignore this path. So, we can say that gmvbe1 is essentially
coming from these 2 paths.
So, then depending on this value of this resistance of course, there will be bifurcation.
So, if I consider say R3 in the order of say ro2 so, if I consider it is value it is in this order
then this resistance; if I call Rin of the common base. So with this Rin_CB it is say ro2 and
in the denominator we may ignore this 1 and we can written only this part so, which is
gm2ro2. So, this is becoming and we know that this is much smaller than rπ2. So, as
long as this R3 it is maybe in this order. So, we can say that major part of the signal it is
entering into this device and then it is whatever the things it will do we will see that part.
So, on the other hand if I say that R3 it is in the order of rπ and then let me call this is rπ2
and then gm2ro2. So if I consider that R3 it is in this order then corresponding Rin of the
common base circuit it is so, compared to ro2 this will be dominating because we do have
this multiplication factor which is rπ2×gm2 that is nothing, but β of the transistor so;
837
obviously, that will be dominating. So, we can say that this is and that becomes
rπ2.
So, if R3 it is in this order which is much higher than the previous case then we may say
that half of the current it is flowing here and remaining half of the current it is entering
there. But even then even then you may say that major part of the signal it is coming here
and once or at least half of the signal it is coming there and once that current is flowing
through this resistance it develops the corresponding voltage here. So, for the two cases
if I consider say this case, then we can say that almost entire current is flowing here and
the corresponding voltage getting developed here.
So, this gives us the output voltage which is R3 multiplied by the signal current which is
gm1vbe1 which is vin. So, we can say that of course, there will be a polarity difference. So,
that gives us the voltage gain = ‒ gm1R3. On the other hand so, you can say that if R3
it is in the order of ro2 so, definitely this gain, it will be quite high depending on the value
of this R3 and the corresponding gm1.
On the other hand if I consider the R3 it is in this order and then only half of the current it
is entering to this circuit and in this case the corresponding vo it will be the ‒ R3gm1 ,
why by 2 that is because half of the current it is entering into this rπ2 which is wastage for
us, but then the corresponding R3 it is quite high. So, which is rπ2gm2, then we do have
× vin. So, that gives this it is quite high.
In fact, if you see here this part it is β so, we can say that the corresponding gain and
if I particularly keep the focus on gain magnitude, then this is β of transistor-2 by 2,

, which means that if I consider simple CE amplifier where the gain may be in this
order where this R3 maybe in the order of ro whereas, for this case the gain, it is higher
than the CE amplifiers gain by a factor of β2. But then that can be obtained by
considering a situation where R3 it is much higher than a standard ro2.
So, we may require additional circuit we may require really a clever circuit here which
offers high value of this R3. Assuming that it is possible to get that then we will be
getting very good gain out of good voltage gain out of this one. So, that is the basis of
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this claim that the cascode amplifier, it provides higher gain much higher gain than the
CE amplifier.
Now let us look into the output impedance.
So, this is the output port and Ro which is R3 coming in parallel with whatever the
resistance coming out of this entire circuit. So, if I want to know what will be the
resistance of this circuit the circle circuit what it can say that this rπ2 and ro1, they are
coming in parallel this one of course, I have to make the signal = 0. So, that makes this =
0. So, this part it is 0. So, we can ignore that part. So, to know this resistance what we
can do? We can draw the rest of the circuit to get the equivalent resistance.
So, we do have ro2 and then we do have gm2vbe2 and at this node at this node we do have
rπ2 connected to ground and also we do have ro1 connected to ground. So, we can say
these two resistances they are coming in parallel and such kind of circuit, we have seen
before the equivalent resistance of this circuit you may recall that Req = (rπ2 ⫽ ro1) + ro2 +
gmro2(rπ2 ⫽ ro1).
In fact if you see here compared to this part and this part; this is quite high. So, we can
approximate that this is gmro2(rπ2 ⫽ ro1), which means that the output resistance coming
here it is quite big and it is expression it is given here. In fact, if you see these two
transistors while these two transistors are connected in series and if the gate of the first
839
transistor, it is connected to AC ground then it is not only it is ro and this ro coming in
series in fact, we do have some nice amplification here ok.
So, this kind of tricks can be utilized to make the impedance here much higher than
normal ro1 which is referred as cascode current source, later we will be talking about that
in detail. So, while you are talking about cascode amplifier, this cascode terms it may be
coming while we will be you know designing this part to achieve high value of this
impedance R3. So, anyway so, that is the output impedance we do have R3 in parallel
with this and then coming to the input impedance. Let me clear the board yeah.
So, the input impedance on the other hand so, if you see this is the input port input
impedance is very straight forward. So, Rin it is same as rπ1, but then input capacitance.
So, this is very important thing. So, input impedance wise if you see hardly there is no
difference compared to input impedance of normal CE amplifier. In fact, we also need to
consider R1 in parallel with that, but. So, this R1 in this model I have not drawn you can
draw that one also. So, typically this R1 it is much higher than rπ1.
So, you may consider this is approximately equal to rπ1 which is same as the input
resistance of normal CE amplifier. So, I should say there is no change in input
impedance; however, in input capacitance if you see the Cµ this Cµ it is which is integral
part of Q1 which is breezing the base and collector terminals of Q1.
840
Now from this node to this node we claim that the gain of the circuit is not very high. So
as a result the miller factor coming for this Cµ1 it may not be very high. So, of course,
you will be getting Cπ1 and then Cµ1 (1 + AV1, gain) and we claim that this AV1 gain, it is
much lower than gm1ro1. So, if we if we agree with this are much lower than gm1ro1.
So, we can say that this capacitance is much smaller than Cin or a standard CE amplifier,
where for standard CE amplifier the corresponding input capacitance is Cπ1 + Cµ1 (1 +
the corresponding voltage gain of CE amplifier). Now to really acknowledge the
improvement of this input capacitance namely reduction of the input capacitance, we
need to establish that this gain the circuit gain here from this point to this point it is much
lower than the voltage gain of CE amplifier.
So let us see how we establish that. So, if you see this circuit if you see this circuit and if
you want to know what will be the gain from here to here, we need to know what is the
corresponding impedance we do have here and we have seen that based on the value of
this R3 this impedance maybe in the order of you know .
So, the voltage gain from here to here it is I should say AV1 if I call it is AV1, ‒ gm1 × (ro1
coming in parallel with whatever the impedance). We are seeing here and that may be in
the order of ok. So, this is approximately and since the current here and current
here they are same, we can say that gm1 and gm2 they are same. So, further we can say
841
that this is approximately minus 1. So, that makes the input capacitance of this circuit it
is Cπ + Cµ (1 + 1) or to be more precise Cπ1 + 2Cµ1.
Here of course, we have assumed that this input impedance the input impedance of the
cascode transistor this is referred as the cascode transistor so, it is in the order of , but
we know that it depends on it highly depends on the value of R3. So, if this R3 on the
other hand if it is very high that may increase the increase this resistance and the
consequence here of course, then the voltage gain here it will increase. So, here to here
the voltage gain if it is increasing, then this factor instead of one that will also increase.
So, but then typically this gain from this point to this point it is, it is quite fair to
approximate that that is gain it will be around 1 or 2 depending on this corresponding
load practical load here. Let me take a short break and I will come back after the break
for the MOS circuit.
842
Prof. Pradip Mandal
Lecture – 62
Multi-Transistor Amplifiers: Cascode Amplifier (Part B)
Start sir.
So, welcome back after the short break. So, now let us move to the cascode configuration
using MOSFET. But as I said, that the cascode configuration it is combination of
common source followed by common gate. And, similar to BJT where we have
discussed about CE followed by CG.
So, here also the basic purpose it is to have that configuration. We need to again
summarize and want to know what is the purpose of this configuration. Particularly,
cascading common source with common gate. Before I go into that, here also I like to
say that when we talked about CE-CC amplifier we said that that circuit it is referred as
emitter follower.
So likewise, when you talk we refer to say common drain stage where input we give at
the gate and then output we observed at the source. And drain node typically it is
843
connected to supply voltage. And we have discussed about its basic purpose and the gain
voltage gain from gate to source, it is approximately 1. And also the phase shift is 0°.
So, if I give a signal at the gate like this, at the source what you observe it is almost
replica of that signal and hence the common drain circuit it is referred as the source
follower. So, source is trying to follow the gate. So, likewise when you talk about the
common gate circuit, and for common gate circuit what we does the signal we feed at the
we feed at the source node.
So, this is the input port and the gate it is connected to a DC voltage which is AC ground.
And then we observe the corresponding signal at the drain terminal. And typically
instead of considering the signal in the form of voltage, here we prefer the signal to be
treated in the form of current both at the input port as well as the output port.
And its current gain ≈ 1. In fact, I should say it is 1. So, the current gain since it is 1, it is
this circuit is referred the common gate circuit is referred as again current conveyor.
So, it conveys the current from the source node to the drain node without any
amplification. But here the purpose here it is to convey the current from low impedance
node, source node to the high impedance node the drain node ok. So, now coming to the
main discussion how the common gate amplifier it can be used as a voltage gain booster
along with the common source amplifier.
So, here we do have the common source stage, followed by the common gate stage.
Similar to CE followed by CB, here also either we can isolate the DC operating point of
the 1st stage and 2nd stage by placing a DC decoupling capacitor there, and only feeding
the signal from 1st stage to the 2nd stage.
The; however, the better version it is that we can probably directly couple the signal
without this capacitor. And whatever the bias requirement for M1 and M2, we can try to
see whether they can complement each other and then they can help us to avoid this bias
circuit and this bias circuit.
So, that gives us the cascode configuration. So, the circuit what we have drawn here
initially it is common source followed by common gate and then if you do this kind of
844
modification that gives us the cascode amplifier in the MOSFET version. So, similar to
BJT, here also it is feasible in the next slide we are discussing that.
So, here we do have the circuit we do have the original common source followed by
common gate. And as I said that if we remove this capacitor, and then what we are
looking for M1. It required some DC current need to be supplied to its drain. And at the
same time M2 needs its source current need to be consumed by some bias circuit.
So, if we directly couple here then what you can do the source terminal current of M2, it
can directly supply the required drain terminal current of M1. So, here what we can see
the current of M1, it is helping to provide the bias for sorry current of M2 it is helping to
provide the bias of M1 and vice or vice versa.
So, here the connection it is direct connection and similar to BJT cascode, here we are
we will be discussing that how the signal it is propagating from this stage; the common
source stage to the common gate stage. So, we can say that M2 it is performing the
common gate configuration. Whereas M1 it is performing the role of common source
configuration.
Now first of all the signal we are giving the giving at the gate of transistor-1 which is
making meaningful vgs here. And this vgs it is producing gmvgs voltage dependent current.
845
And that current we are expecting it is coming from transistor-2 or if I say that we are
producing a signal current in this direction this current it is entering into this one M2.
Now, how much portion of this current it will be entering into M2? That can be; that can
be analyzed by considering small signal equivalent circuit or this cascode amplifier. So,
in the next slide we will be talking about the small signal equivalent circuit of this
cascode amplifier. Maybe you can independently try it out.
So, this is the; this is the cascode amplifier circuit and then the biasing. So, the analysis
part it will be done by considering its small signal equivalent circuit. But just prior to
that, let me put few words about the biasing and operating point of the 2 MOSFET
transistors.
So, what we have here in the biasing side? For M1, we need to provide a voltage here, at
its gate sufficiently high. So that this transistor it will be on and that is done by this
potential divider which is getting constructed by R1, R2 and the supply voltage.
So likewise, at the gate or transistor-2, we are giving a DC voltage which is coming from
this potential divider constructed by R3 and R4. So depending on their ratio we are
generating a voltage here. Likewise, depending on the R1, R2 ratio, we are providing a
voltage here. Now we are feeding the signal at this point, but at this node we want this
signal this node to be AC ground for proper operation.
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So, this node we are at this node we are connecting a large capacitor to ground to make it
really AC ground. Now, while this M1 it is getting its gate voltage and source node it is
connected to ground. So, that gives us VGS for this transistor. And then this VGS and its
dimension it provides an expression of this current. Now this current it is coming from
M2. So M2 is not having any problem.
But then this current whatever the current it is defined by size of M1 and its
corresponding bias it must be consistent with whatever the bias circuit we do have here.
So, similar to BJT counterpart, the matching of the current source here and the DC
current or transistor-1 coming from its bias is very important. If it is not taken care then
probably M2 it will be entering into triode region.
And if it is further mismatch it is there then, maybe M1 also entered, will be entering into
the triode region. Or there is another possibility of course, that it may push this circuit
into malfunction. And as a result the consequence it will be that the amplifier may not
give good performance. So, while we will be designing this circuit, we need to take care
of proper matching of DC current of transistor-1 and whatever the bio-circuit we do
have.
On the other hand, while we are providing the gate bias at the gate of M2. Then, to
support this current it itself adjusts its VGS2. In other words, based on the voltage at this
point minus this VGS or transistor-2 provides the DC voltage here. Which is of course,
the source voltage or transistor-2 which is also equal to drain voltage of transistor-1.
So, we need to maintain this transistor into saturation region; otherwise its output the
drain to source resistance it will be; it will be small, and that may create a problem. So,
for proper operation we will like to keep transistor-1 in saturation region and that should
be done by maintaining at least some minimum voltage here, which is referred as VD(sat)
or transistor-1.
So, this voltage if it is higher than VD(sat), then of course there is no problem. In the in
other words, the voltage here the gate voltage of transistor-2 it should be sufficiently
high compared to minimum required VD(sat) here for transistor-1. Plus, whatever the VGS2
that is necessary to support this current.
847
So, as long as the gate voltage here it is, this gate voltage it is higher than this limit, then
we do not have any problem. So, it may not be very difficult to satisfy this condition, but
unless you pay attention you may miss out this important information; and that may
force the transistor particularly this transistor into triode region.
So, in summary what we, in summary what we like to say here that the gate voltage here
VG2 should be more than or equal to required VGS2 to support this current Plus, VD(sat) or
transistor-1 and VD(sat) of this transistor-1 eventually it is this VGS ‒ Vth.
So, I should say VG2 should be higher than VGS2 + VGS1 ‒ Vth1 ok. So, if you satisfy this
condition then there is no problem, ok. Now, once we get the proper DC operating point,
next thing is that the analysis for voltage gain and output impedance and so and so. And
to do that, we need to draw the small signal equivalent circuit similar to BJT cascode
amplifier. We also have drawn this small signal equivalent circuit here.
848
So, this part it is this part it is for M1. On the other hand, this part it is for M2 and the gate
of M2 it is connected to AC ground here. And at the gate of M1 we are feeding signal.
We are feeding signal vin and the signal source may be having a source resistance of Rs.
And then we do have vgs getting developed, based on the input signal here. So, we can
say that drop across this Rs, it is DC wise it is 0. Even, signal wise you may ignore. So,
we can say that vgs1 it is same as vin. Unless, otherwise we consider the input capacitance
here. Note that here we do not have rπ namely gate two source resistance is infinite.
So, this circuit it is, in fact, simpler than the BJT version. So, now, this input which is
appearing across this gate-2 source of transistor-1, it producing it is producing gmvgs,
here. And, this current you can say that it is coming from this circuit. And of course, this
current part of the current it may be coming from this rds1 also.
But typically, the impedance looking into; looking into this circuit it is much smaller
than whatever the impedance we do have. So, we can say almost this entire current it is
coming through this circuit. And as a result, it is arriving to the output node, and if it is
while it is flowing through this R5 it is producing the corresponding voltage, vout. So, the
vout we can say it is ‒ R5 × gm1vgs1. In fact, part of this current it will be flowing through
this as well as this also.
849
So, I should not say this current it will be flowing only through R5. In fact, I should
consider parallel connection of whatever the equivalent resistance we will be getting
here. In fact, it can be shown that this final vout it is ‒ gm1×vgs1 which is vin. And this
multiplied by R5 ⫽ Req.
In fact, this is the output resistance. So, if we look into this circuit that is the output
resistance. And, we also have discussed about the Req resistance for such kind of circuit.
And this circuit, what is the specialty of this circuit? We do have the active device,
providing voltage dependent current source then ro or rds2.
And this is gm2 into its corresponding vgs2. And then we do have resistance here which is
rds1 connected to ground. So, we can say this Req it is rds1 + rds2 + gm2rds1rds2. That can be
well approximated by the luster namely gm2rds1rds2. So, this resistance it is quite high. So,
that may give very good gain.
So, if I say the voltage gain ; and particularly its magnitude, it is gm1(R5 ⫽ this Req).
And this Req it is quite large. And to get very good gain what you can do we can try to
increase this R5 also in the same order. That can be obtained by considering active
current source there.
Maybe, cascode current source we can put there and then we can get very good gain. So,
that is how we can say that it is helping us to get higher voltage gain. But then of course,
the output impedance here it will be quite high to achieve the gain.
So, if we try to directly sense this voltage through some subsequent circuit which may
offer significant amount of capacitance. So, that may limit the bandwidth. So, that is of
course, is an issue that can that may be addressed by putting a buffer here. Namely,
common drain kind common drain stage which we already have discussed.
But if I focus only on this circuit, I should say it is having potential to increase voltage
gain by increasing the output impedance. Now, input resistance of course, here it is I
should say, this circuit provides input resistance, it is infinite. So, whatever the input
resistance we will see it is coming from R1 ⫽ R2.
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So, Rin of this cascode amplifier it is R1 ⫽ R2. On the other hand, the input capacitance
Cin, it is coming from the Cgs and Cgd or transistor-1. So, let me erase and then make the
space for calculation or expression. Cin it is coming from Cgs.
So, that Cgs is coming as is in parallel with Cgd, but that is affected by Miller factor. So,
Cgd1 multiplied by 1 plus whatever the gain we are getting from this node to this node.
And again, here we may consider that the impedance at this node coming from the upper
circuit, it may be in the order of . So, that gives us the corresponding voltage gain
here it is approximately 1. So, the input capacitance here it is Cgs1 + 2Cgd. On the other
hand, if I consider simple common source amplifier, as we know that for common source
amplifier, the corresponding Cin it is Cgs + Cgd (1 + its voltage gain).
So, because of the reduction of the voltage gain here then input capacitance it is getting
reduced. What is its consequence? In case if the bandwidth of the whole system it is
defined by this Rs and the input capacitance coming at this node, then we can say that if
we can reduce this Cin, that helps us to extend the bandwidth, ok.
So, based on the situation we may say that this is giving us some advantage particularly
in terms of extending the bandwidth. But the assumption of course, here it is we assume
that the system bandwidth starting from this point till the primary output, it is
predominantly defined by this RC time constant. Then only that claim it is valid.
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Otherwise, if the upper cut-off frequency it is defined by say CL and say Rout then of
course, by reducing this input capacitance, it will not be helping to improve the
bandwidth. I think most of the things we have discussed whatever we have planned
today.
So, in conclusion what we have is that, we have continued the multi-configuration

amplifiers. And today, what we have discussed, it is that common emitter amplifier
cascaded with common base and with some modification in the biasing arrangement.
What we obtained it is something called cascode amplifier. Note that this cascode this
word it is not grammatically correct.
But technically, that is the name it is used. Then we have seen the advantage of this
cascode amplifier compared to standard CE amplifier. Namely, the voltage gain it got
increased by a factor of almost β. So, this got increased by a factor of β of cascode
transistor compared to CE amplifier. Also, we have seen that input capacitance it got
decreased.
But then the drawback of course, the output resistance got increased. And that need to be
handled by some means. So, as long as this is allowed we can go for this cascode
amplifier. So, on the other hand for MOS-based circuit, we have seen the common
source followed by common gate. That gives us the with bias modification; biasing
modification we have obtained the cascode amplifier.
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And there also we have seen that the voltage gain. So, voltage gain got increased by a
factor of intrinsic gain of the cascode transistor. Provided the load part it is properly
implemented namely in our example. Assuming this R5 it is in the order of gm .
So, if this is valid then you can say that the gain of the cascode amplifier it is gmro times
whatever the gain we do have on the common source amplifier. AV of common source
amplifier. So, and also we have seen that input capacitance it got decreased.
And because the first stage gain it got decreased. And then, but then the cost is output
resistance got increased. So, this is of course, it is not a good thing, similar to this one.
So, as long as it is allowed to increase the output resistance this may be a good scheme
we yet to cover the numerical examples. Probably in the next class or next to next class
we will be talking about that. I think that is all I do have.
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Prof. Pradip Mandal
Lecture – 63
Multi-Transistor Amplifiers: Cascode Amplifier (Contd.) – Numerical Example
(Part A)
Dear students, welcome back to our online NPTEL certification course on Analog
Electronic Circuit. Myself, Pradip Mandal from E and EC department of IIT Kharagpur.
Today we are going to talk about Multi Transistor Amplifiers; namely, in fact this is
continuation of our previous lectures. So, today we will be talking about Numerical
Examples of Cascode Amplifiers.
So, compared to our overall plan, we are in week 7, 6. And as I said that we already have
discussed about the analysis and construction of cascode amplifiers and today we are
going to detail of some numerical examples.
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So, the coverage of a today’s lecture it is primarily cascode amplifier using BJT and
cascode amplifiers using MOSFET. We do have two very in depth numerical problem
we have said, and most likely we will be discussing on this BJT based on cascode
amplifier. So, that gives you some idea that why we go for this cascode amplifier
compared to a simple CE amplifier.
And the MOSFET counterpart, what I mean is that similar kind of cascode amplifier can
be constructed using MOSFET; and there also we do have very detailed numerical
problem. But based on the time availability, I may be giving you some hint, but you have
to work it out, ok.
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Coming to the cascode amplifier using BJT, so here we do have the numerical problem.
This circuit, the cascode amplifier we already have seen before. And today we are giving
you numerical value of different bias components, supply voltage, and then the device
parameters are given here; similar to whatever the parameter it has been discussed
earlier. Namely, early voltage of both the transistors, we are assuming it would be 100 V;
β or transistor-1, it is 100. Just for a change we are using β of transistor-2, β2 it is 200; on
the other hand VBE of transistor-1 as well as transistor-2 both are approximately 0.6.
Now, the different coupling capacitors, signal coupling capacitors or DC decoupling

capacitors; C1, C2 and then C3 we are assuming all of them are equal, relatively high
around say 10 µF. On the other hand we are assuming that we do have a load capacitance
CL connected at the output port, it is say 100 pF. And for both the transistors Cπ and Cµ
from base to collector are given here; and let me assume that both the transistors Cπ, Cµ
are equal, so we do have Cπ here and then Cµ here, they are given here.
In the bias circuit on the other hand we assume that, the value of this resistance it is 2.8 k
and the bias current here I bias for the first part of the example, let you consider it is 0;
which means that, we do not have this current source, instead we do have a passive
element R3 and it is value it is 2.8 kΩ. Now based on the bias resistors we do have here,
and then the potential divider here constructed by R2 and R4; we do have the other
biasing arrangement. And from that we can find the operating point of the two
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transistors. So, let we first find the operating point of both the transistors and then we
will go for the small signal parameters, ok.
So, to start with let we yeah, let me use different color here. So, to start with we do have
here it is supply voltage is 12 V and then we do have R1 which is 570 kΩ and then we do
have the VBE(on) is approximately 0.6 V drop. So, from that we can calculate what is the
IB1? In fact, IB1 it is 12 V supply minus VBE of 0.6 divided by R1, which is 570 kΩ, so
that gives us 20 µA. And we do have β here which is 100, from that we can get collector
current IC1 = 2 mA.
In fact, same collector current is flowing through emitter of transistor-1 sorry transistor-
2. So, from that we can also say that IC2 is approximately equal to it is emitter current,
which is equal to IC1 and that is 2 mA. So, we can say that this current 2 mA of current, it
is also flowing through R3 and we do not have this current source; as we said that the
bias current we are assuming here it is 0. So, the drop across this R3, it is 2.8 × 2, right.
So, the voltage drop across this R3 = 2.8 k × 2 mA, so that gives us 5.6 V; which implies
that, the voltage at the collector of transistor-2, VC of transistor-2 = 12 ‒ 5.6, so that is
6.4 V.
On the other hand we do have a potential divider constructed by R2, R4 and then 12 V
supply. So, from that we can say, the voltage at the base of transistor-2 ignoring the this
base current compared to whatever the current we do have within this potential divider;
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we can say that, VB2 it is 12 V, that means in the . So, that is 12 × 10, we do
have 10 here and we do have 100 here, so that is giving us 1.2 V.
As I said that we are assuming this IB2 it is very small compared to whatever the current
is flowing through transistor-2 and transistor-4. In other words before we connect the
base terminal, the voltage it was 1.2; obviously once we have this current flowing, this
base voltage it will be slightly dropped. But still we can approximate that the voltage it
will be remaining there; because the drop across this the R2, terminal equivalent
resistance R2 ⫽ R4 due to this IB2 which is in fact, 10 µA.
How do I get 10 µA? Collector current is 2 mA divided by it is β, so that is the IB2 is 10

µA. So, this is very small, very small compared to 1.2 V and hence we are considering
this VB2, it is approximately 1.2 V. So, we do have 1.2 V here, and then the voltage
coming here it is 1.2 ‒ 0.6, so this voltage it is 0.6 V. So, we do have 0.6 V here VB1 and
then we do have 1.2 V here and then we do have 6.4 V here. So, that keeps of course,
this transistor it is in active region, this is also in active region. So, the circuit it is not
having any problem.
Now, so we obtain the operating point or the both the transistors. And let us see what
will be the value of small signal parameters namely gm, then ro and rπ of the two
transistors. So, let me yeah, I do have blue color now. So, we can say that gm1 which is
corresponding . So, this = ℧. So, likewise we can get gm2, it is also same ℧;
because the collector currents they are same, the output resistance ro1 of the transistor Q1,
it is coming from the early voltage here and then 2 mA of current.
So, , so that gives us ro1 = 50 k; in fact ro2 it is also 50 kΩ. And using
this gm1 and gm2 you can say that, rπ of transistor-1 = ; which is equal to 1 by sorry
100 divided by gm, it is , so that gives us 1.3 kΩ. On the other hand rπ2, since β is 200
here; it becomes 2.6 kΩ. So, now, we you obtain the small signal parameter from the DC
operating point and then using that, we can find the voltage gain and then input
capacitance, maybe the upper cutoff frequency which is of course, our interest.
So, what is the voltage gain? So, try to remember these values of the small signal
parameters to get the voltage gain.
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Let me I think I do have, and the next slide I do have the small signal equivalent circuit,
yes. So, we do have the small signal equivalent circuit for Q1 sorry, for Q1 we do have
the small signal model here. So, likewise Q2 the small signal model it is here; and we
know the value of different parameters, so let us try to see what is the voltage gain of this
circuit. And of course, this current it is zero or even if it is DC, the small signal wise will
be ignoring this; R3 on the other hand it is connected to the DC supply voltage here
which is a AC ground.
So, the voltage coming at this output in terms of vin is our main interest. Before we go
into primary input to primary output, let us starts from; start from here and then try to see
what is the gain from base or transistor-1 to the primary output of the amplifier, ok.
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So, what is the voltage gain we get? So, we do have vbe applied here and then we do have
this current is flowing and this current it is partly coming from R1; some part of the
current is coming from rπ2 and then whatever the combined current it is flowing through
this device.
So, these three currents I should say, together it is giving us the total current. And
depending on the value of this resistance, this resistance and whatever the equivalent
resistance we do have; we will be getting the current branch out. And so, whatever the
currents we do have here, they are essentially coming from this R3 and that develops the
corresponding voltage here. So, if I know this current flowing through R3, then if I
multiply with R3 that will be giving us the vo. So, I should say that, vo equals to ‒ R3 into
whatever the current you do have, let me call this is iR3.
So, if you look into this circuit and try to see what the impedance is and in fact, you may
recall; the expression of this impedance of this kind of spatial active circuit it is
( ). So, this is the equivalent resistance looking at the emitter. In addition to that
we also have this resistance. So, these two resistances together, it is giving us the input
resistance of this second transistor or you may call it is common base circuit. So, Rin2 =
rπ2 ⫽ ( ). And then of course, you can see that how much the current is flowing
through this R3 that can be obtained.
860
Now let us see this part numerically and you may recall that this resistance it is 2.6 k.
And now let us try to see, what is the numerical value of this one? We do have R3 which
is 2.8 and ro2 it is 50 k. So, this is ( ). So, what is the gm2? We do have and
then we do have ro2 which is 50 k; 50 × 1000; plus 1 probably we can ignore and so this
is giving us. In fact, I do have the calculation done myself for you; let me see what the
value I got is. So, it is very close to 13. In fact, precisely this is 13.6 Ω only. In fact, if
you compare this part, this is much higher than one; and here also we can say this is
much higher than R3.
So, if I do that approximation, then I will be getting this part = . So, no under gm2 is
and that is why you are getting this resistance is very small. So, since this resistance, this
part it is very small, namely only 13.6 Ω; this resistance on the other hand it is 2.6 k and
this resistance of course, this is 50 k. So, I should say gm1vbe1, it is primarily flowing
through this device. As a result, the current flowing through R3; namely signal current
flowing through R3 which is denoted as iR3. So, this is can be well approximated by
gm1vbe1. So, the output voltage, the output voltage vo = ‒ R3 × gm1vb1. Or we can see that
output voltage vo with respect to base voltage of transistor-1 which is vbe, so that = ‒
R3gm1.
So, that gives us again of, again I do have the calculation 215, so that is the voltage gain.
Now this is the gain from the base terminal or transistor-1 till the output point. Now if I
consider this Rs = 1.3 k. Why did I take 1.33 k? Just for simplicity that, the input
resistance here in this circuit calls Rin which is rπ1 and we know that this is 1.3 k. So, if I
take this Rs = 1.3 k; then you can say voltage coming at the base or transistor-1 is
basically vin multiplied whatever the attenuation offered by Rs and then Rin. And since
both of them are equal; so we can say that vbe, so that gives us vbe of transistor-1 = vin
. So, numerically it is coming .
So, since vbe it is just half of the primary input. So, now, combining this expression or
this value and this equation what we can get that; overall gain Av define as the primary
output divided by primary input, so that is . So, gm, so the overall gain, we are
getting it is 107. Now next thing is that the input capacitance. So, let me clear, but then
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you must remember this values; whatever the values we obtain here, input resistance and
so and so.
And try to then calculate the input capacitance.
So, C in, input capacitance of this entire circuit looking at the base or transistor-1 which,
is equal to we do have the Cπ and then we do have the Cµ. And then Cµ of course, it is
bridging the base and the collector terminal of transistor-1. So, naturally this Cin, it will
be Cπ1 + Cµ1(1 + Av1). So, what is Av1? It is the gain coming out of the transistor-1, while
the load here it is connected. And we know this impedance the load here it is ( ).
And this is of course we already have seen that, this resistance it is 13 Ω. And compared
to this 13 Ω, this is very small; in fact, you can directly see that this is .
Now once we have this gm2, this impedance and then the voltage gain Av1 equals to;
basically the gain starting from the base terminal here, base terminal here to this collector
terminal while it is driving this load of . And it is gain it is gm1 × . In fact, this gm2
it is in parallel with rπ2 and ro1 also; but then these two parts they are very small, so
naturally this is approximately equal to and this is 1, because both the gm’s they are
. And how do we define this gain? This is actually v collector voltage divided by v
base voltage of transistor-1, ok.
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So, since this, this is 1; in fact I should have a ‒ sign here, if I am retaining this ‒ sign.
So, that gives us the input capacitance by considering this value here, we are getting Cπ1
+ Cµ (1 + 1); and Cπ here it is 10 and this is 5, so that gives us 10 + 10 = 20 pF. So, the
input capacitance here it is 20 pF. Now this is of course, one of the important point that,
the gain of this cascode amplifier you may recall if I consider Rs; and then the overall
gain, it was .
So, you may be wondering that this gain it is not much different from normal common
emitter amplifier, so why we go for this cascode amplifier? The answer it is line in this
example also, answer it is having two types of circuits; I should say based on the two
types of circuits, the answer may be 2. One of this answer it is that, in case if this R3 it is
passive and this resistance is relatively small; then we may not get much advantage in
terms of gain. But then if you see the value of the input capacitance, it is quite small; and
so the pole getting created by this Rs and input resistance and then the Cin, that pole it is
getting situated at a very high frequency.
So, if I consider the circuit here along with the Cin; what you are having the circuit
equivalent circuit is, vin followed by Rs. And then we do have the equivalent resistance of
Rin, followed by equivalent capacitance Cin and this is the vin. The voltage here it is the
vb1. So, this circuit it can be redrawn by considering this entire portion as equi Thevenin
equivalent source; and then we do have Thevenin equivalent resistance which is Rs ⫽ Rin
followed by Cin.
So, this resistance and then this Cin, it is forming. So, this is vin , so that is the
Thevenin equivalent voltage source. So, this circuit this Rc circuit is creating a pole; the
pole coming due to that it may eventually limits the bandwidth of the circuit. So, the
corresponding circuit the bandwidth may be defined by this frequency say; fU due to this
Rs and Rin, which is ( )
.
⫽
And if you see that this resistance, numerically this is, in fact this is equal to 650 Ω and
this is we do have 20 pF. So, that gives us a cutoff frequency which is equal to close to
600 or something, this is this is quite high. In fact, this is equal to 12 MHz; which means
that, this pole, this pole defined by Rs ⫽ Rin and Cin it is quite high. And when you say
quite high, we must compare with the other possible candidate defining the upper cutoff
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frequency, which is essentially the output resistance of the circuit. So, output resistance
of this circuit, which is actually defined by this R3; because the resistance coming from
the lower portion it is quite high, so Ro it is primarily R3 and then the CL.
So, what is the value of this the corresponding upper cutoff frequency defined by this Ro
and CL? Did you call this is f′U, which = and R3 it is given here, CL it is also given
here; and if you put the corresponding value, the corresponding cutoff frequency I was
getting 568 kHz. So, if I compare 568 kHz and then to 12 MHz, definitely this defines
the upper cutoff frequency.
So, this is of course you may say that, then upper cutoff frequency it is coming from R3
and CL; so what is the advantage of having this smaller value of this capacitance? Now to
really appreciate this point, what you can do? Let we compare the performance; namely
the voltage gain and the upper cutoff frequency for a standard CE amplifier, where we
can probably, we can eliminate this part and we can directly connect the collector part,
collector of Q1 to R3. And then you see that whatever the simple CE amplifier we get,
what is its corresponding gain. So, in the next slide we will be talking about that.
So, we do have say simple CE amplifier and intentionally I have taken the value of
different bias elements, particularly RB, it is same as the previous case; and also this Rc it
is same as R3, namely 2.8 k. Rest of the things are very similar, namely this the Cπ and
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Cµ. And you may recall that, the same similar kind of analysis can be done and the
corresponding collector current here it is 2 mA, and for this case of course, the
corresponding gm it is , and the voltage gain Av equals to it is gm of the transistor, and
then Rc ⫽ ro; whatever this ro we do have and this is 50 k and this is 2.8 k.
So, this voltage gain is of course, from the base terminal to the output terminal. And here
we are if you put the corresponding value, we are getting ‒ 204, if I consider this one;
otherwise it may be coming close to 215. But whatever it is, if I consider this resistance;
then I will be getting 204. And so, the voltage gain if I consider Rs here, the voltage gain
of the circuit and if I consider this Rs is 1.3 k, which is same as the input resistance Rin
which is essentially this rπ and rπ it is 1.3 k.
So, if I consider Rs is 1.3 k, Rin is also 1.3 k; so the gain or attenuation from this point to
this point it is 0.5, and from here to here we do have the gain of 104. So, the overall gain
vout by the primary input say vs = , this 2 it is due to this attenuation here. So, that
gives us 104. So, still it is ok, the voltage gain of this, this CE amplifier it is same as very
close to whatever you obtained for the cascode amplifier.
Now next point is that, if I consider the effect of input capacitance on the bandwidth;
namely if I consider Cπ and Cµ, then what kind of what kind of upper cutoff frequency
we are getting. Namely if we calculate the Cin which is Cπ + Cµ (1 ‒ this gain), whatever
you say 204 with a ‒ sign. And then we do have here Cπ = 10 pF and then we do have Cµ
= 5 and then we do have 205, right.
So, this is plus. So, that gives us how much, 1035 pF. In contrast to contrast to this value,
the for cascode amplifier; we got Cin, it was 20 pF only. So, now, it is expected that this
large value of this input capacitance, it will affect the upper cutoff frequency due to this
Rs, Rin and then the Cin. So, let us calculate what is the upper cutoff frequency coming
from the Cin and then Rs and Rin?
So, we can say that, the upper cutoff frequency due to, cutoff frequency due to Rs ⫽ Rin
and the input capacitance. So, if I say that this is fU = ; Rs and Rin parallel, so that gives
us 650 Ω × 1035 pF. And I have done the calculation, I got the value here it is. So, I got
the value close to 237 kHz. Now this is very important, earlier we obtained; if I consider
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20 pF, the corresponding cutoff frequency you obtained there it was only, it was rather
12 MHz, now it is becoming 237 kHz.
Now if I consider the other candidate defining the upper cutoff frequency, namely this Rc
and the CL. And we have seen that the corresponding cutoff frequency defined by Rc and
CL, namely it was; in fact, if I consider this Rc ⫽ ro, this was giving us close to
600 kHz. So, if I consider Rc ⫽ ro, which is the output resistance multiplied by the CL in
the denominator. So, this cutoff frequency and if I consider this cutoff frequency,
definitely this will be defining; because this is lower than this one.
To summarize that, if I compare the common emitter amplifier and then cascode
amplifier; we can say that, for both the circuits the gain it is very close to each other.
So, the gain if I say that, for CE amplifier gain may be, overall gain it is 102; if I start
from here till this point considering the source resistance of 1.3 k. And then the upper
cutoff frequency you have obtained here, it was 237 kHz. On the other hand if I consider
cascode amplifier, the gain it was very close slightly higher slightly higher. Note that this
is in ratio we need to convert into dB and then the bandwidth here it was remaining; the
bandwidth it was defined by the corresponding output resistance and the CL. And this
was around 5, something 568 kHz.
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And this difference as I say that, primarily due to difference in Cin for Cin, for cascode it
was 20 pF; whereas, for CE amplifier it was 125 pF, so that gives us the lower
bandwidth, ok. So, let me take a break and then we will come back to similar kind of
comparison again.
867
Prof. Pradip Mandal
Lecture – 64
Multi- Transistor Amplifiers: Cascode Amplifier (Contd.)-Numerical Examples
(Part B)
Welcome back after the short break. Before I going to the next topic I must see here that
this calculation of the Cin I did a small mistake hear, it should be 135 because Cin = Cπ +
Cµ (1 + 204) and so, here we do have 5 and also here we do have 10. So, I miss this 10
part. So, 10 + 1025. So, that gives us 1035 pF capacitance.
So, it should be 1035, this calculation remains the same ok. So, far what we have
discussed that the advantage of cascode amplifier with respect to standard CE amplifier
and namely what you have seen is that in case if you are retaining this passive element
for both the cases, then gain wise we do not get much advantage. But then what we have
seen that in case if we have the input resistance and the source resistance together
forming a significant significantly low frequency pole due to this large value of the Cin,
then we have seen that the cascode amplifier it is giving some advantage.
Now it may be a situation where this resistance it may be small or whatever the cutoff
frequency we are obtaining by this Rs and then Cin and Rin that may be beyond the upper
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cutoff frequency defined by RC and the CL. So, far such case you may say that then what
is the advantage of cascode amplifier. In fact, cascode amplifier it is having two types of
advantages; one is extending the bandwidth as we just now we have discussed
particularly in presents of significantly large value of the source resistance, the other
advantage which is commonly used is that the increasing the gain drastically.
So, to get the higher gain so far whatever the example we have considered RC it was only
2.8 k. So, the increasing the capability of the cascode amplifier to increase the gain, it
has been blocked by the low value of this RC. Namely if you put a cascode amplifier then
its output resistance it is quite high compared to this passive element.
So, to demonstrate the capability of the cascode amplifier to increase the gain first of all
let we consider a different situation instead of having this RC if you put some active
circuit there, probably then the advantage of the cascode amplifier particularly for
enhancing the gain it will be quite prominent.
So, to demonstrate that in the next slide what we are going to do we will be getting
almost the same numerical problem except we do have a change here. Particularly, if you
see the value of this R3 instead of 2.8 k now we are going to take a big value say 10 MΩ.
On the other hand since we have do have 12 V supply here and if we are expecting this
R3 it will be supplying the entire 2 mA of current; obviously, then drop across this
resistance it will be quite high to avoid that problem we consider this IBIAS.
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So, IBIAS it is supporting this 2 mA of current. So, then you may say that why do you
have this resistance at all. Well for all practical purposes while you are implementing this
circuit it may be having finites conductance of the current source and whatever the value
you have taken here it is feasible particularly if you implement this part by something
called cascode current source.
So, later we will be talking about the implementation of the cascode current source for
the time being let you assume that the bias circuit we do have here it is having two parts;
one is 2 mA of ideal current source in parallel with 10 MΩ resistance. And rest of the
things we are keeping same namely R1, R2 and then R4 and so and so and all the bias all
the early device parameters also we are retaining same sorry this should be vbe2.
So, what you are expecting from the lower side as we have discussed based on the
resistance here based on the R2 and R4, the current flow here quiescent current flow here
it is 2 mA, the voltage here it is 0.6 V DC the voltage here it is 1.2 V. So, the voltage
here it is 0.6 V and the voltage coming here of course, we have to see what will be the
corresponding voltage.
In fact, if you see the value of the resistances here and if I say that the current here it is 2
mA it is getting supported by this bias current, then natural question is that if the current
flow through this R3 it is 0 then drop across this one it will be 0. So, naturally the output
voltage it will be 12 V.
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On the other hand if I consider practical circuit and let me use the analysis slight analysis
here. If I consider the resistance of this part in fact, this resistance equivalently you can
see the value of this resistance it will be roughly gm2ro2rπ2. If I ignore say or if I consider
this node it is connected to ground. So, if I calculate this value of course, for DC we
cannot say this is ground, but for the time being let we tolerate such kind of things and if
you do so, the corresponding in fact, this rπ is coming in parallel with ro1.
So, whatever it is the if I consider this resistance here it is gm2ro2rπ2 of transistor-2 plus
may be smaller entities over which this term it is dominating and if you put the
numerical value here particularly if I say this is , this is ro2 it is 50 k then rπ2 it is 2.6 k
that gives us 10 MΩ ok. In fact, this is the reason why we have picked up this 10 MΩ it
is not only feasible, but it is also a meaningful value and if I consider the practical value
of this resistance, then what about the little current it will be flowing here that current we
will also be consumed by the equivalent resistance there.
As a result this R3 and then whatever the resistance we are expecting here since they are
equal. So, that will make this 12 V and the ground here in fact, getting divided by R3 and
this equivalent resistance and hence the voltage DC voltage coming here it is you can
approximate that this will be 6 V.
So, in summary if I consider this is 10 MΩ and the equivalent resistance of this part it is
10 MΩ and the ideal current here it is 2 mA, this is also 2 mA. So, then this voltage it
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will be 6 V. In fact, this 6 V of course, we do have some assumptions. And so, there is
there may be a scope of debate. So, whether those things are correct or not, but whatever
it is we do have this voltage it is maybe in the near vicinity of 6 V keeping transistor-2 as
well as transistor-1 in active region of operation.
So, we can say that for all practical purposes both the devices are in good condition and
hence we can move to small signal equivalent circuit. Now in before we go into the small
signal equivalent circuit, I like to recall that value of gm1 and gm2 both are then ro1 and
ro2 both are 50 k and rπ of transistor-1 it is 1.3 k and rπ2 on the other hand it is 2.6 k right.
So, with that if I try to see what is the voltage it is coming here in the small signal
equivalent circuit. So, suppose we do have vbe voltage here. So, the current flow here it is
gm1vbe now this current it is coming from ro1.
So, part of the current it is coming from ro1, then we do have rπ2 and also we do have this
circuit supplying the current and based on this current here we do have the current
flowing through R3. So, to find the value of this current flowing through R3 we need to
know what will be the relative value of this resistance, we need to find what will be the
resistance coming from this circuit and also this ro1. So, we already have the numerical
value of rπ2 and ro1, but then let us see what is the equivalent resistance coming from this
circuit.
So, this Req as you may recall this is ( ). So, R3 it is quite high compare to ro2 and
this part it is quite high compared to 1. So, we can as well consider this is ( ). In
fact, if you put the value here namely 10 MΩ, 107 divide by gm2 which is and then ro2
it is 50 k, 5 × 104. So, that gives us 2.6 kΩ. In fact, that is how I have picked up the
value. So, this Req it is same as what is a numerical value we do have for this rπ2.
So, compared to these two resistances this resistance and this Req if I ignore if I consider
this resistance is quite high. So, I can see half of this current it is flowing through this
part and the other half the current is flowing through this rπ2 and hence this current flow
through the R3 which is iR3 is equal to half of gm1vbe1. So, that give us the output voltage
vo = ‒ R3 × this iR3 which is × vbe1. In fact, that gives us = ‒ gm1 it is and then
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we do have 2 in the denominator and numerator we do have 107 and in fact, this value if
you see. So, we do have.
So, if you calculate this value, it will be coming roughly ‒ 384615 it is a big number
right. You may recall compared to the normal CE amplifier the gain it was just a 204. So,
compared to that this is very high the basic you know basic philosophy how we get this
gain, it is the even though we do have very high resistance here of say 10 MΩ, we are
able to successfully you know flow this at least half of the current through this resistance
as a result it is developing a large voltage.
So, once we have this voltage gain then of course, the main advantage it is very clear, but
of course, we have to keep in mind that the moment we increase this resistance that also
have increase this resistance namely 2.6 k and incidentally that also has increase the
miller factor coming for the Cµ and what is the consequence? In the corresponding Cin
got increased.
So, this C in got increased because the miller factor of the Cµ got increased now. So, yes
we got the advantage, but we need to really calculate whether we made some significant
amount of damage on the upper cutoff frequency defined by the input capacitance Cin
and Rs and Rin ok.
So, Rs and Rin we are taking same. In fact, Rin it is also defined by rπ1. So, Rs ⫽ Rin same
as earlier case namely 650 Ω, but then we need to see what is the corresponding Cin. So,
to get the Cin we need to know what will be the gain from the base terminal here to the
collector terminal of transistor-1 ok. So, please try to recall all these numbers and I am
going to create the space for that analysis.
873
So, what we have said that this r equivalent coming from this part, it is 2.6 k and also we
do you have 2.6 k here. So, that gives us the total resistance these two together, it is
giving us the total impedance for the lower transistor Q1. So, these two resistances
together it is giving us 2.6 k in parallel with 2.6 k = 1.3 k right. So, if I consider the base
two collector gain which is essentially if I say that = ‒ gm1 × (this resistance 1.3 k ⫽
this ro1 which is 50 k) ok. So, roughly we can see that this gain sorry. So, this gain you
can say that you can drop this part you can retain this one and this gm1 it is , here we
you do have 1300.
So, if I drop this part, the gain it is becoming ‒ 100. So, what is the conclusion here that,
the gain earlier here to here the gain it was just 1 now that gain it got increased to 100
magnitude wise that is mainly because this R3 it got increased from 2.8 kΩ to 10 MΩ
right. So, the input capacitance it is Cπ of transistor-1 + Cµ (1 + this 100 gain).
So, that is becoming this is 5 and this is 10. So, we do have 505 here and then we do
have 10. So, 515 pF. As a result the upper cut off frequency define by Rs and Rin it is
( ⫽ )
and then multiplied by Cin it becomes quite significant.
So, let us I do have the calculation for you. So, we do have and then 515 × 10‒12
and that gives us 475 kHz and earlier we already have said that the pole coming from the
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CL and this RO earlier it was quite small, but of course, now this output resistance it is
also getting increased because the resistance lower side it is 10 M upper side it is 10 M.
So, then total resistance here it is 10 MΩ ⫽ 10 MΩ so, that gives us 5 MΩ.
So, the now the alarming situation we do have here it is 5 M and CL = 100 pF. So, that
defines the upper cutoff frequency. In fact, the corresponding upper cutoff frequency
defined by this load capacitance which is .
So, what we have here it is so; that means, this is roughly 300 Hz only yes. So, the
advantage here what we got namely we got very high gain from this circuit which it was
I think we already have said that 38 the overall gain, it was 384615. In fact, if I
considered this attenuation this divided by 2.
So, that is the gain overall gain, it is very good thing, but unfortunately this output
resistance got increased and the corresponding upper cutoff frequency it is the concern.
But of course, we have to keep in mind that while we have increase this one the gain,
though the miller factor affecting the Cµ increases the Cin, but the corresponding upper
cutoff frequency is the it is not limiting factor for defining the bandwidth of the circuit
rather the problem it is elsewhere and this problem this output resistance it is quite high,
that can be handle differently namely by placing one buffer circuit here which we have
discussed earlier, we can put a buffer circuit here constructed by maybe common
collector stage to address that.
So, I should say the cascode amplifier alone is not the solution, we need to put the CC
stage, but it is important to make a note that cascode amplifier it is having two important
potential it is having the capability to increase the gain by whatever the gain we obtain
there multiply may be square of that almost square of that, also it is having the capability
in case if you are not looking for high gain it is having the capability to decrease the
input capacitance keeping the Miller factor they are small and hence it can be considered
for one candidate to extend the bandwidth. But you need to know the situation of yours
and then only you can deployed.
875
So, for we are talking about cascode amplifier using BJT similar kind of circuit can also
be analyzed. In fact, this is what we were talking. So, in case if you are considering the
CE amplifier sorry this CE amplifier and then if you compare this circuit directly it will
be difficult to compare because this resistance it is high, but then this resistance you
cannot make it so, high in case if you are making this is high of course, then here the
output resistance it will be defined by ro of the lower transistor.
Of course that will also affect the upper cutoff frequency, but the way this circuit has a
affect the upper cutoff frequency, it is quite sever compared to this cutoff frequency.
Namely for this case the upper cutoff frequency it is if I make say this circuit replaced by
this kind of active circuit for fair comparison, then the gain here it is gm1ro1. So, this is
the voltage gain for simple C amplifier and the upper cutoff frequency on the other hand
it is .
( ⫽ )
So, that can be ignored multiplied by CL on the other hand for this circuit the gain we
obtain there it was quite high it was. In fact, gm1 multiplied by this R3 in parallel with
whatever the resistance we obtained here.
So, the resistance there it is gm2ro2 × rπ2. In fact, you can see that gm2 and rπ2 it is nothing,
but the β of the another transistor. So, this is the gain this gain we are talking about the
gain from this point to this point without considering Rs and this is becoming gm1
876
multiplied by R3 in parallel with β of transistor-2 into ro2. So, while this cascode structure
it is helping us to increase the gain to get the advantage of that in the.
So, sorry the cascode structure it is helping us to increase the output resistance by a
factor of β of the cascode transistor to get the advantage of that on the gain if you take
this R3 also in the same order, then only it is meaningful and if I, in this numerical
example we have considered that this resistance it is in this order and hence it is having a
capability of generating a gain which .
So, assuming that this two are equal. So, that is why we do have factor of 2. On the other
hand here the gain it is gmro1. So, the difference if you compare difference of this
equation and this equation if you see here is the factor by which you can enhance the
gain.
So, theoretically you can say that gain of this cascode amplifier compare to similar kind
of CE amplifier it is a factor of . On the other hand of course, the output resistance since
this output resistance got increased its cutoff frequency, it is the corresponding output
resistance it is parallel connection of R3 and β × ro and again if I consider this R3 in the
order of . So, we can see that this is × CL.
Now again if I compare the upper cutoff frequency here and upper cutoff frequency here.
So, we can see that the difference here it is , but in this case cascode circuit it is having
worse performance than the CE amplifier. So, and the the degradation here of course, it
is the same factor by which hear the gain it got increased. So, if I pictorially if I compare
if I am having the CE amplifier gain say like this and then it is having the corresponding
3 dB frequency or the bandwidth defined by the expression there.
So, this is for the CE amplifier on the other hand if I consider the cascode amplifier, we
are the gain it is quite high and then the corresponding cutoff frequency it is lower, but
then if you see that the role of here they are finally, coinciding. So, this pink color it is
the performance of the cascode amplifier.
So, if I consider the output node and the difference here of these two circuit, then for one
case the gain it is increased, but then bandwidth got decreased on the other hand by the
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same factor for normal CE amplifier the gain is lower, but then the corresponding
bandwidth is higher and gain bandwidth product it is remaining same. It is intuitively it
is also clear that by cascode structure we are essentially changing the output resistance
Rout and the consequence of increasing the Rout is that one is increasing the gain and then
with the same factor decreasing the bandwidth as a result the gain bandwidth product for
both the circuits remaining the same.
So, that is about the cascode amplifier. So, depending on our application if you are
looking for very high gain, but then we can if in case if we are we can tolerate with lower
bandwidth, then we will be going for cascode amplifier.
Similar kind of circuit it is also done for the MOS counterpart and the value of different
bias circuits given here device parameters are also given here. So, we do have the device
parameters are given here for both the transistors we consider transconductance factor it
is 1 mA/V2, λ it is 0.01 V‒1, threshold voltage of both the transistor it is 1 V, supply it is
12 V and then R1 and R2 this potential divider it is such that it creates a voltage here it is
3 V from this 12 V.
On the other hand R3 and R4 it is creating 6 V here. So, since the size of both the
transistor they are equal and Vth is also equal. So, we are expecting both the devices they
will be having equal current. So, naturally the VGS here and VGS here we are expecting
they should be equal.
878
So, we do have yes we do have 6 V here, we do have 3 V here and so, this is also 3 V.
So, that gives us this is equal to 3 V. In fact, if you see this node it is 3 V still this device
it is in saturation region because if the gain voltage is 3 V, its drain voltage it can go
lower than its gain voltage by an amount of 1 V. So, the lower limit of the drain voltage
of transistor-1 it is actually 2 V.
So, definitely transistors-1 it is in saturation region. Now to start with of course, if we

have say this VGS it is a 3 V the corresponding current IDS1 = IDS2 = 1 mA per whole
square by 2 into 3 ‒ Vth is 1 square. So, here again it gives us a current of a 2 mA. So,
this 2 mA it is creating a drop across this R5 which is 2 k.
So, this is 4 volt we are assuming that this is 0 and so, if we have this drop 4 V. So, the
voltage coming here it is 12 ‒ 4 so, that is 8 V. Again transistor-2 it is in saturation
region. So, with this of course, we got appropriate operating point of both the transistors,
now small signal parameter wise we can calculate gm1 = gm2 and their values are 2 mA/V,
ro1 = ro2 which is essentially into the corresponding current 2 mA and that gives us
again 50 kΩ.
So, from that probably we can find what will be the corresponding voltage gain. The
analysis small signal analysis here it is very similar to the previous case I should say
rather it is simpler compared to the previous case and by analyzing that you can find the
gain.
879
So, let us see in the next slide about the equivalent circuit here and from our previous
analysis we see that gm1 = gm2 = 2 mA/V and rds1 notation here we are using rds, rds1 = rds2
= 50 k and the of course, we do not have the rπ here.
So, the circuit that is what I said that the circuit is simpler and at this node of course, we
do have the capacitances for gain of course, we can ignore that. So, if we have say vgs
applied here, we do have gm1vgs1 and part of those that current it is flowing through this
and also the other part is flowing through this device and this current it is coming from
this R5. So, the again based on the relative value of this resistance and this resistance we
can say that major part of this current it is coming from here, because in this case the r
equivalent it is essentially rather gm2, which is gm2 it is it is 500 Ω ok.
So, it is of course, significant, but still it is much smaller than this rds1 which is 50 k. So,
we can say that the current flowing through R5 which is denoted as a iR5 ≈ gm1vgs and
then the corresponding output voltage vo = ‒ R5gm1vgs1. So, that gives us the gain starting
from its gate to the output, it is = ‒ gm1R5 and gm1 we have obtained 2 mA. So, 2 mA
× 2 k.
So, that gives a gain of only four as expected MOS transistors they do have 4 gm, so, that
is why we do have low gain. So, in case if you really want to use MOS transistor for
amplification probably we can look for cascode structure and for that we can increase
this resistance. We will see that, but before we go into that let to you also discuss that the
input resistance here since it is infinite, even though in presence of this Rs we can say
that there is no attenuation.
So, whatever this ‒ 4 it is also giving us the overall gain. So in fact, I should say that
it is same as and hence this is also equal to ‒ 4. Now next thing is that what is the
gain what is the sorry what is the input capacitance? So, that you also see the input
capacitance Cin = Cgs. So, Cgs ⫽ Cgd multiplied by whatever the gain we do have.
So, we do have the Cgs1 + Cgd (1 + the gain) coming from gate to drain or transistor-1.
Now here if you see the gain in presence of Req which is and since this gm2 and gm1
they are same we can say that this Av1 = in fact, I should say this is ‒. So, and that
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is ‒1. So, with this the Cin we are getting Cgs + Cgd × 2 and hence again here we are
getting 20 pF capacitance. Now this 20 pF capacitance it may create a pole with this Rs.
So, depending on this value of this Rs it may be having its corresponding pole location.
So, again we will the analysis it will be similar. So, we will not be going into that
discussion, just we like to say that because of the cascode structure since the Cgd here it
is not exposed to the output node and hence the Miller factor for this Cgd it is small. So,
the input capacitance is remaining low.
So, for high bandwidth application of course, this is having some advantage. Now next
thing is that what you are looking for is that if you want to enhance the gain instead of 4
if you want to enhance the again by using this cascode structure, what we have seen for
BJT version that this passive element this passive element probably we can try to replace
by active circuit, where we can try to take high value of this R5 and then the
corresponding IBIAS.
So, I will be going to that discussion, but let me take an again short break and then we
will come back with that numerical problem.
881
Prof. Pradip Mandal
Lecture – 65
Multi-Transistor Amplifiers: Cascode Amplifier (Contd.)-Numerical Examples
(Part C)
Welcome back after the short break. So, we are talking about the Cascode Amplifier
using BJT sorry MOSFET. BJT part we already have completed now come here so, far
we are talking about the passive load namely R5 it was 2 k now we are going to change
this load to active kind of load, where our basic motivation is to for higher gain.
882
So, in the next slide we do have the formulation of the problem ok. This is the standard
common source amplifier for performance comprising, I am not I am just skipping this
part.
So, we do have; so, we do have the cascode amplifier here with active load namely the
IBIAS here it is 2 mA current and this R5 it is 5 I should say 5 MΩ sorry it should not be
kΩ it will be 5 MΩ please read as this R5 as 5 MΩ.
883
So, why did I take this 5 MΩ? It is whatever the parameter we have calculated small
signal parameter based on that the equivalent resistance coming here it is 5 MΩ and for
that I have taken this is also 5 MΩ, this is also 5 MΩ.
So, any way let we go with this 5 MΩ and let see what kind of situation we are arriving
into. So, first of all based on the bias conditions the current IDS1 = IDS2 = 2 mA.
So, the main current it is getting supported by these 2 mA of IBIAS and then we do have
the Req resistance which is matching with this R5 similar to the BJTs circuit
configuration, this 12 V with this is 5 M and the equivalent small signal resistance 5 M,
it is giving us a DC voltage here it is half of that. So, that is also 6 V.
So, this 6 V of course, we do have 6 V here also based on these R3 and R4 we do have 6
V. So, this transistor it is still it is in saturation region. So, then there is no problem the
value of small signal parameters namely gm1 = gm2 = 2 mA/V and rds1 = rds2 they are
equal to 50 kΩ.
Now, with this we need to find what will be the voltage gain. or maybe this voltage.
Now for that we need to know what will be the equivalent resistance coming here and
this equivalent resistance it = ( ). So, this resistance if you put the value here
what will be getting here it is R5 is 5 M. So, this is 5 MΩ.
884
So, 5 × 106 probably you can drop this part and then divided by gm, it is 2 mA multiplied
by we do have 50 kΩ. So, that gives us that is 50 kΩ. So, this is 50 kΩ and this is
also 50 kΩ. So, this half of this gmvgs1 it is coming from rds1 and remaining half it is
coming from this circuit.
So, that gives us the current flowing though R5 namely iR5 = half of this gm1vgs1 and
hence we are getting the output voltage vout = R5 × gm1 and hence equals to of
course, it is ‒ sign.
So, and if we see the value of this R5 it is 5 M and gm1 it is 2 mA/V. So, that
gives us this is 10‒3 and here we do have 5 × 106 that gives us ‒ 5000. So, this big
number big jump compare to when were we have consider passive load and then there
we got the gain of only 4.
So, I should say this voltage gain Av got increase from 4 magnitude wise to should say it
got increase to 5000. In fact, this is I should say it is a big jump and as I said that for
most transistor this cascode structure it is frequently use to enhance the gains and also
similar to BJTs version since we have increase this resistance to increase the gain and it
is also affecting the input capacitance is particularly Miller factor for this Cgd it is getting
increased and that is done by because we do have the Req resistance is high and gain from
gate to drain of transistor-1 it is large.
So, what is the gain here? Let me again erase this part, but then keep in mind that the
gain of the overall circuit it is 5000 all right. So, the input capacitors before we go for a
calculation let me clear the board and then input capacitance yes.
885
So, to get the input capacitance Cin which is Cgs1 + Cgd1 (1 ‒ whatever the gain we do
have from here to here which is let you call this is Av1) and what is the Av1? Av1 = ‒ gm1
multiplied by rds1 in parallel with the equivalent resistance coming from this circuit.
And we made the calculation if this is 5 MΩ, if this is 5 MΩ then the this resistance it is
50 kΩ. So, that gives us these gain of ‒ gm is 2 × 10‒3 and then we do have 50 k and 50 k.
So, that is and so, these 2 are getting cancel, this is also getting cancel that is the
giving us ‒ 50 gain.
So, the gain from this point to this point it is ‒50 and hence the input capacitance with
this value of this Av1 it is Cgs1 it is 10, Cgd it is 5 and then we do have (1 + 50) here and
that gives us 265 pF yes. So, it is increasing the input capacitance, but probably still it is
not so, alarmingly high, maintain this factor it is so, high, but yes depending on the
situation we may or may not be able to accept that.
So, the somebody here it is that by using active device here, we can get higher value of
this R5 and this value of this resistance in this case critically we have taken the resistance
coming from the lower part. So, here it was 5 MΩ and hence we have taken this
resistance.
886
So, to get the maximum advantage what about the resistance we got from this circuit
lower part, if we take the same resistance then we can get the maximum benefit for both
the gain as well as bandwidth consideration.
If you are putting see relativity smaller resistance then of course, that resistance it will be
defining the output resistance while this gain got increased from 4 to 5000 the output
resistance Rout in this circuit is of course, 5 MΩ and 5 M in parallel. So, that gives us 2.5
MΩ and with the CL here with the CL of say I mean 100 pF the upper cutoff frequency
may be the quite look. So, that again we have to see what is the corresponding upper
cutoff frequency define by this R and this C time constant.
So, in summary if I compared this cascode amplifier to boost to the gain and if I compare
the performance of the standard common source amplifier.
Here the common source amplifier may be having very low gain, but then it may be
having very high bandwidth mainly because the output resistance and the CL it is
defining that. But then by the virtual of the cascode structure we can increase the gain by
a big factor, but then the corresponding bandwidth it is getting affected. So, the gain
bandwidth product for both the cascode and the simple common source both may be
having the same gain bandwidth product.
887
It may be it may be important to take a note that the gain calculation can be obtained by
some other means also namely you can say sort this you can sort this output note to and
AC ground and then you can calculate what is the corresponding current is flowing here.
The moment you sort it the resistance looking into this circuit it is just . So, compare
to rds1 this resistance it is quite low. So, you can say that this short circuit current it is
primarily it is this current only. So, we can directly see that this equal to ‒ gm1vgs1.
Now, to get the voltage here once we release this connection, then we need to find what
will be the corresponding equivalent resistance and this resistance it is R5 in parallel with
whatever the resistance we do have here.
So, once we release this and then to get the corresponding output voltage coming here,
what we have to do that this output voltage equals to this current io multiplied by this R5
in parallel with whatever the resistance we do have and that resistance it is gm2rds2 and
then rds1. And that gives us and this part as I say that it is already as having an expression
of gm1vgs1 and then R5 ⫽ gm2rds2rds1 all right.
And hence the voltage gain = ‒ gm1(R5 ⫽ gm2rds2rds1) right. So, this the this is
alternative way of finding the expression of the gain earlier we are calculating based on
the current bifurcation, this may be a simpler method what is the what are the steps it
involve, first of all you make a sort here and then you find what is the expression of this
888
current, primarily this stage the common base what are the common gets stage it is
convening this current to the output which is gm1vgs is coming to the output with the ‒
sign.
And then once you release this connection and then we can find the voltage here just by
multiplying this current with equivalent resistance there. I think we have covered what
are the things we have planned.
So, today we have in fact; cover only two numerical example, but I guess they are very
extensive example to demonstrate the potential of cascode amplifier. First one it is using
BJT and we have seen that, it is having both the capabilities. Of course, not
simultaneously. So, two capabilities one is it is having the capability to reduce the input
capacitance and may be the gain we can maintain same.
On the other hand the other case is that we can make the voltage gain very high may be
the input capacitance it may be in the same order or unchanged. And this is valid for not
only for the cascode amplifier using BJT this is valid for MOSFET. I should say that the
standard CE amplifier namely the simple amplifier using BJT since its gain it is it gain of
it CE amplifier it is significant and it is quite high cascode amplifier may or may not be
require.
889
However, if we consider common source amplifier, this simple amplifier voltage
amplifier using MOSFET. Since its intrinsic gain it is not so, high particularly because of
the gm. So, it is better to go for the cascode amplifier to enhance the gain of the circuit.
So, in VLSI circuit whenever we will be implementing some analog circuit in may be
using MOSFET, then this cascode amplifier it will be frequently used.
I think that is all see.
890
Prof. Pradip Mandal
Lecture – 66
Multi-Transistor Amplifiers:
Amplifier with Active Load (Part A)
Dear students welcome back to NPTEL online certification course on Analog Electronic
Circuit. Myself Pradip Mandal from E and EC department of IIT Kharagpur. So, to
continue this course today’s topic of discussion it is Amplifier with Active Loads. We
may be having multiple amplifiers but, primarily we will be talking about common
emitter and common source amplifier today.
891
Compared to our overall weekly plan we are in week-6, I should say module-6 and we
are. In fact, we already have completed these two sub topics namely Multi Transistor
Amplifiers and then Cascode amplifiers. And today we are going to talk about Amplifier
with active load. In fact, incidentally when we talk about active load, the amplifier it is
having multiple transistors.
So, you may say that this is also a special kind of multi transistor amplifiers. But we like
to explicitly say that it is having unique characteristic, where the passive load it is getting
replaced by a load utilizing MOS transistor or BJT transistor. So, that is why though it is
multi transistor amplifiers, but basically characteristic wise the load part it is getting
replaced by another transistor.
892
Now, today what we are planning to cover it is under this active load amplifiers, we do
have to start with we do have motivation of using this active load. Then, from that we
will we will be talking about basic operation of amplifier having active load and their
corresponding circuit analysis including, small signal model and then finding the gain or
maybe intuitively explaining the gain and so and so.
And then we will be talking about practical circuits having the active load and for both
the basic operation as well as for practical amplifiers. So, we do have two main
amplifiers in our discussion, one is common emitter and common source amplifier.
Numerical examples and design guidelines it will be covered in the next class. So, to
start with let we go for the motivation of going for active load.
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This is a recapitulation or recalling whatever we know about CE amplifier and not only
we will be talking about CE amplifier. But basic operation of the CE amplifier just to see
that, what is it is limitation of the voltage gain.
In fact, if you recall that this is this is the main amplifying transistor and it is at the input
we do have the signal we are feeding along with the along with the DC component. So,
that the transistor it is in active region of operation. In addition to that we also have the
RC connected to the collector to the supply voltage Vcc and the connection of this RC it is
such that the transistor here it is in active region of operation.
So, this RC it is having dual role to play, first of all it provides appropriate region of
operation. And the second one it is it also converts the current into voltage, because
primarily at the output we observe the signal in the form of voltage Vout. So, by applying
a voltage at the input port namely at the base it is given here which is having a DC
voltage along with the signal. We are changing the collector current with respect to it is
quiescent current and that variation or change or the signal part it is getting converted
from current to voltage by this resistor RC.
So, this resistor typically it is referred as load and it is if it is passive component which is
providing linear I-V characteristics. Of course it works fine, but to some extent it is
having limitation to give the voltage gain. I should say rather it is having good gain the
CE amplifier basic CE amplifier it is having good gain. But in case if you want to
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enhance the gain further, then there is a scope of improving the gain and that may be
done by replacing this passive element by it is active equivalent circuit. So, let us see that
where the limitation it is coming from particularly for the voltage gain.
To come to the basic at the base, what we are doing is we are changing the voltage at the
base or either you say base voltage or base to emitter voltage. And if you observe the
based the current flowing through the base terminal say Ib instantaneous current having
both DC as well as the small signal part as function of Vbe, which is also having a DC
part as well as a small signal part. As you know that it is having exponential dependency.
Now, this base current it is getting converted into collector current and that we may call
Ic and this Ic it is flowing through this RC and it is creating a drop across this resistor
called VRC and then we do have the supply Vcc. So, Vcc ‒ VRC that gives us the Vout. So,
this is Vcc ‒ VRC and then this VRC as I said that it is having RC it is expression is RC × Ic.
So, pictorially if you see the output for characteristic, namely if we sketch the Ic versus
Vout. So, you may recall for a given value of current at the base the corresponding
collector current it is having I-V characteristic like this. So, in the active region the
current Ic it is almost independent of Vout. But then if you go very low then of course, the
device enters into saturation region and then there is a significant or I should say sort
dependency of the collector current on Vout or in this case incidentally that is Vce.
895
Now, then if we consider the load line characteristic, as you have discussed load line
characteristic it is given by essentially I-V characteristic of this RC. And we have
discussed that how we obtain this load line characteristic; namely if you plot the voltage
the current through this resistance RC with respect to it is it is voltage across it is VRC.
Actually this load line characteristic is linear.
But then to match the x-axis this VRC instead of writing VRC we prefer to write this as Vcc
‒ Vout. So, to match this x-axis with this the Vout what we have what we have done or we
in fact we have discussed that we do flip this x-axis. So, that the characteristic it becomes
in the second coordinate and then after that we shift it, so that then the load line then we
gets the load line. Where the shift it is Vcc amount.
So, this point it is Vcc and then slope of this original I-V characteristic it was and the
slope of the transformed load line characteristic it is , so that is how we obtain this
load line. So, the slope of this line it is and the amount of shift we have done here to
get rid of this Vcc part to match the Vout axis with this Vout axis, we have shifted this point
here.
So, that gives us this point of the load line characteristic it is Vdd. So, that gives the one
age of the load line Vcc or VDD in this case Vcc and the slope it is that gives the other
end of the load line it = . Now we know that once you have this load line and once we
have the device characteristic intersection of these two characteristic gives us the final
Vout and also of course it is giving the corresponding current call Ic.
So, this Ic and this Vout it is basically the solution point. Now whenever we are giving a
signal as you may recall whenever we are giving the signal with respect to a DC
operating point. So that means, we are changing the device characteristic up and down
with respect to it is actual the exponential relationship, that makes the device
characteristic namely the we call this is pull down element characteristic it goes down or
up.
And as a result the since the operating point it is changing by wearing this voltage and
incidentally that is also changing the changing the Vout namely the output voltage and
that is how we are getting the output signal right. Now if you see that the gain starting
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from the input which is getting converted into current Ib and then through the
multiplication of β then we obtain. So, this Ib it is getting converted into Ic × β and then
again by this load line the signal part it is getting converted back into this voltage.
So, I should say that we do have a voltage here, voltage it is getting converted into
current and then this current it is coming to this y-axis and then this load line
characteristic it is converting back this current into voltage. So, we can see that we do
have two reflectors, one is Ib versus Vbe characteristic reflector multiplied by β and then
we do have the other reflector.
In fact, if you combine this multiplication and then this exponential relationship, namely
if we plot the Ic versus Vbe characteristic curve. Then of course this is also exponential.
But with it is having different scale because of the β.
So, this Ic versus Vbe characteristic curve it gives us one conversion from voltage to
current, so that gives us the current. And then this characteristic curve it is converting
back this current into voltage. So, naturally the gain of this conversion input to output
gain it depends on the conversion rate here and then also it depends on the conversion
rate at the other reflector.
So, if I intuitively if I say that if the slope of this reflector it is very stiff, on the other
hand if the slope of this reflector it is say very small then we can get high gain. So, the
mathematically you can see that gain when you say gain Av = gmRC with a ‒ sign right.
So, since the gain it is gmRC and the slope of this line it is nothing but gm and slope of
this line on the other hand it is .
So, I should say that the gain is essentially slope of this mirror multiplied by reciprocal
of the slope of the other mirror. Why the reciprocal? That is because, this second mirror
it is converting the y-axis into the x-axis. So, that is why we do have the slope it is
getting flipped. So, I should say this is equal to gm ratioed with with a ‒ sign.
So, now in case if we want to really increase the gain, of course it is having a limitation
of the gain will be talking about that also. If you numerically see what is the value here,
if you put the expression of gm into this equation that gives us that is IC quiescent current
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. Because gm into; gm = and it is nothing but this voltage drop DC voltage
drop.
So, and on the other hand the VT it is thermal equivalent voltage. So, we can say that
maximum limit of this gain it is the drop across this RC resistance divided by thermal
equivalent voltage. And if we have the Vcc supply here, obviously this drop across this
RC cannot exceed that. In fact, that should be practically that should be lower than Vcc,
because we require some drop across this device. So, in extreme case even if I
considered and say drop across RC equals to close to Vcc then the gain of the amplifier it
is . So, that is the theoretical limit of the amplifier gain.
So, that is what we see that limitation of the voltage gain, in this circuit because the gm it
is good in this circuit the gain value it is very decent. But in case if you want to further
enhance then we may look for some alternative. Now what may be the alternative? Let
us try to intuitively understand that what may be the scope of improvement of this gain.
So, we the slope of this line it is coming from and suppose this is the equation point
with respect to this quiescent point. If we want to increase the increase the gain naturally
you may be thinking that suppose if I make the load line like this, which means that if I
decrease the slope of the load line. Which means that, if I increase the value of this
resistance RC, then from this analysis what we say it is that voltage gain it is gm which is
the slope of the first mirror and then divided by inverse of rather slope of the second
mirror.
So, if I decrease the slope of the second mirror, since it is coming in the denominator so
we may say that will be increasing the gain. So, this red colored mirror it is supposed to
be increase in the gain. In fact, intuitively it is also clear that for the same kind of
variation if you see for this curve and this curve of that device, the intersection point it is
here and then the other intersection point it is here. So, it is expected that the
corresponding signal it will be getting amplified like this.
But what is what the problem here is, we are looking for a meeting point of the load line
which is much higher than whatever the earlier meeting point and this meeting point it is
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nothing but the Vcc. Now if you are looking for higher value of Vcc which means that I
am looking for higher supply voltage.
Well, theoretically it is that is what it is, but practically if the supply voltage is more
there are two issues, one is power dissipation it will increase for the same coefficient
current. If this voltage it is higher necessarily the power dissipation it will be a problem
and also instantaneously if the output voltage here it is higher, then that may exceed the
breakdown limit of the device, so this may not be allowed.
Some extent it is possible to increase the gain, but then you cannot make this Vcc
arbitrarily high to enhance the gain. So, the natural question or a natural intuition it may
be or rather I should say smarter intuition maybe, that can I can I increase this rather
decrease this slope without changing this voltage? Well, that is also possible maybe we
can keep this point here and then we can try to decrease this and decrease this slope of
the second mirror. But then the corresponding equation point it should be coming down
here, which means that I may be looking for equation point somewhere here instead of
this one.
Where the gm it will drastically drop. So, if I try to decrease this slope without changing
the supply voltage then I have to decrease the gm and anyway the gm it is also coming in
the expression of the gain. So, naturally it is not helping well. Then what may be the
solution? Suppose if I decrease this slope, but then if I do not do not allow this supply
voltage to be increase. So, we can probably you can terminate this characteristic here.
Which means that, in case if we have an option to have I-V characteristic which is not
completely linear, but over this range it is linear and then it is having sharp non-linear to
terminate to the and to the available supply voltage. And then what we are getting by this
blue line blue load line, it is we are decreasing the slope of the second mirror and at the
same time supply voltage we are not changing and also the equation point here we are
not changing.
Which means that without changing the gm here we are able to decrease the slope of the
load line and at the same time since the supply voltage it is remaining same. Then we do
not have any increase of the power dissipation we do not have any fear of whether the
device it will be entering into the breakdown ok. So, that is that is what we replacing this
passive load by active load ok.
899
So, anyway so what we said is that limitation of the voltage gain or the standard CE
amplifier namely CE amplifier with passive load and it is gain it is primarily it is getting
restricted by the voltage drop across this resistance divided by VT. So, I should say
| | it is the voltage drop across this and that can be extended by going for some
alternative of this.
Similarly, if you look into the common source amplifier on the other hand it is
philosophically it is same, only thing is that the I-V characteristic instead of Ic versus
Vbe, now we have to Ids versus Vgs.
So, as I said that for common source amplifier also we do have the similar kind of
problem, to name with that namely the gain voltage gain it will be limited.
And in this case the voltage gain in fact it is much lower than common emitter amplifier.
In fact, we have seen that for in the numerical examples we have seen that common
emitter amplifier it is having a typical gain of say 100 or more. Whereas, for common
source amplifier for practical purposes we have seen that with passive load the gain it is
even less than 10, so that definitely it is a serious matter.
So, whatever the modification we are going to discuss it is more significant for common
source amplifier if not important for common emitted amplifier. So, first of all we do
have Ids versus Vgs characteristic curve and here again if you plot the sorry this is Ids
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versus Vgs characteristic curve and in this case it is not exponential rather it is a square
law right. But then philosophically again it is it is working as a reflector like a mirror,
which converts the Vgs variation Vgs variation it converts into current.
So, it converts into current either you can see this way or this way, but basically it
converts into the corresponding current variation. And then if you see the output voltage
which is supply voltage (VDD ‒ this IR drop). So, which is Ids × RD and mathematically
we can say that Vout it is VDD ‒ RDIds and this Ids it is given here.
And pictorially on the other hand you may see that this is we do have Ids versus Vds
characteristic curve. And if I consider device it is initially in entire region it was like this
and then after that it enters into saturation region at say some operating point. In case if
the Vgs it is lower then the corresponding I-V characteristic it comes down like this. On
the other hand if it is higher, than the corresponding characteristic of the device namely
pull down element it is like that.
And then we do have the load line we do have the load line as you may recall, which is
similar to the CE amplifier and the point here intersection point here it is the supply
voltage. In this case it is VDD and slope of this line it is with a ‒ sign. So, here again
this is working as the load line it is working as reflected and this may be say quiescent
point and in this case the expression of the voltage gain Av which is gm, gm is the slope of
this mirror slope of this I-V characteristic multiplied by or divided by slope of this
characteristic.
So, that is divided by with a ‒ sign or you can say this is ‒ gmRD and this gm if you
recall it is expression this will be ( )

. So, it depends on how we express this gm, but
of course this is one expression. So, this multiplied by RD with a ‒ sign. Again this part if
you see it is nothing, but the drop across this RD and it is its upper limit it is of course the
supply voltage. In fact, practically it is lower and all practical purposes we like to take
this IDS versus RD equals to half of VDD rather than trying to stretch to VDD.
And then depending on this VGS ‒ Vth which is commonly known as overdrive voltage of
the transistor beyond the threshold voltage. So, typically this voltage overdrive voltage
which is VGS ‒ Vth and that is a much higher than thermal equivalent voltage which it
901
was there for BJT. So, as a result in fact VGS ‒ Vth may be in the order of maybe 1 or 2 V
for discrete component. So, if I say that upper limit of IDS × RD is VDD. So, we can see
that this is the upper limit VDD and so this maybe that gives us the max of the voltage
gain max (Av) = ( )
right.
And since this part it is restricted by the supply voltage, then again it is having the
limitation of the voltage gain. Numerically you have seen that if you take this is 12 V
then practically is to take IDS × RD it is 6 V and then 6 × 2 it was that was 12. And the
practical value of this VGS ‒ Vth we have taken say 1 or 2 and that used to give a gain of
only 12.
So, again the conclusion is that with passive load the voltage gain it is really limited and
we are looking for it is corresponding alternative. And of course, this is the
corresponding analysis if it is a passive load, then the corresponding load it was playing
a role to define the gain. So, I will not be going detail of this one, but we may come back
to the small signal analysis when we will be talking about the active load amplifier.
Now, here again we like to replace this load or the load line characteristic, we like to get
something like this. Where the slope of this I-V characteristic it is a small, but then it
should it should converge to this VDD point. So, we are looking for I-V characteristic like
this for this element. So, that the first of all the operating point remains unchanged the
corresponding current it will be the same. So, the gm here it will be the same. On the
other hand slope of this line it is getting decreased. So, if the slope of this line it is
getting decreased then this part part it will be getting increased.
And hence there is a scope of increasing the gain and also without that can be obtained
without changing the supply voltage. So, we will take a short break and then we will be
coming back to discuss about the both the amplifiers with active load.
902
Prof. Pradip Mandal
Lecture – 67
Multi-Transistor Amplifiers: Amplifier with Active Load (Part B)
Yeah. So, welcome back after the short break. And we were discussing about the
limitation of the voltage gain of the common emitter and common source amplifier
particularly if it is having passive load. And intuitively we understand that, how it can be
enhanced. Namely in case if we can get some characteristic load line characteristic like
this, instead of having a linear characteristic. In fact, that is the center point of getting
higher gain of any amplifier using active load.
I must also say in this context that in case if you are putting some arbitrary active load
thinking that that may be improving the gain, but then it may not. Say for example, in
case if you are increasing the slope here, instead of decreasing the slope then it may be
rather the gain it may be lower. So, for example, in case the I-V characteristic it is non-
linear, but in case if it is having say this kind of load line characteristic where the slope
of this load line it got increased. So, naturally it is expected that since the slope of this
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reflected it got increased compared to the passive load. Then the gain instead of
increasing with this pink color load line, it will decrease ok; anyway.
So, let us see what kind of implementation we can think of to get this kind of non-linear
load line, particularly this one which is giving us the gain. So, in the next slide we do
have common source amplifier with active load.
So, here the lower part we are retaining same and same circuit we do have the M1, which
is receiving the signal at its gate along with the DC voltage. But then it is also having the
load, which is instead of having passive load, but it is having a transistor M2. Note that
this transistor M2, this is PMOS transistor right.
And its source it is connected to VDD and the gate it is receiving DC voltage defined by
say VSG with respect to VDD. Theoretically you may say that this gate voltage may be
with respect to ground also, but we prefer to denote the biasing of this transistor M2. In
this way because the VSG of this transistor it is defining it’s current. Now of course, this
transistor-2 based on its DC voltage it may define its own ISD current ISD2; likewise
transistor-1 based on its VGS1 it may define its IDS current.
Now naturally, then who defines this current? For proper operation, we require both the
current should be equal and we need to satisfy some condition to ensure that IDS1 and IDS;
ISD rather ISD2 they should be equal.
904
Well, at this node we do not have any other circuit connected. So, it is very natural to say
that why do we require any condition for this two current to be equal; because it is KCL
as we do not have any other circuit connected here. Then the answer is that we assume
that both the devices are in saturation region and in saturation region their current should
be equal. If you are not paying good attention and if you are simply saying that I do not
have any other circuit connected and the current of the two devices they must be equal.
Then what it may happen that that ah one of these two devices will be forced into
entering into a triode region, the other one may be remaining in saturation region and it
will be having a huge consequence on the gain.
So, I must make you aware that we have to pay additional attention. So, that the both the
devices are in saturation region and of course, their current should be equal. So,
whenever we say that these two are equal what we mean is that, the devices are in
saturation region and in saturation region whatever the current we do have they are
equal.
In other words the ( ) into its corresponding K called K′n of transistor. ×
( ) should be equal to K′p of the second transistor and its corresponding
. So, this is PMOS transistor. So, threshold voltage may be ‒ve.
So, that is why I am putting mod here then ( ). Now, this

condition need to be satisfied to ensure both the devices is in good condition. Now you
may say that this part, we may ignore or you can approximate these two parts they are
equal into one, but then rest of the things this part and this part should be equal. So, for
the time being to appreciate the basic operation of this common source amplifier with
active load; let me assume that this this part. And this part they are equal these two parts
referred as first order part and these two parts on the other hand particularly this
part ( ).
And this ( ) they are referred as the second order part; because they are
influenced on the current as long as the devices are in saturation region is very small.
And these two term on the other hand they do have strong influence on defining the
corresponding current. So, we assume that this part and this part they are equal that is
ensured now assuming that these two are equal let us see its operation.
905
So, again to come back to the basic operation of the device particularly for M1, we do
have Ids versus Vgs characteristic curve and this is beyond threshold this is square law.
And then at I at the output node, if you consider both the pull down element namely Ids
versus Vds characteristic curve and it may be triode region and then saturation region like
this depending on different value of the Vgs and so and so on.
Now this is where we are increasing the Vgs1. Now on the other hand if I consider the I-V
characteristic of this transistor that is very tricky. So, to get the corresponding load line
first of all let me draw the and the current flow here namely ISD2 as function of VSD; for a
given value of the VSG2.
So, as you may recall from our device characteristic, if we plot the ISD2 versus VSD2 and
its characteristic it is like this similar to NMOS transistor. So, now this ISD2 it is not same
as Vout though VDS1 equals to Vout, but this is not Vout. However, this is related to Vout
which is equal to VSD2 = VDD ‒ Vout right. So, the VSD2 equals to this. Now to match this
x-axis or this characteristic curve we need to eliminate this ‒ sign and also we need to
eliminate the VDD. And to get that to do that last time as we have done, we need to flip
this characteristic curve in the second quadrant.
So, which means that if I plot the ISD2 versus ‒VSD2; then I will be getting this
characteristic curve and the moment I put say if I consider ‒ VSD, then this part it
becomes Vout ‒ VDD. Now to get rid of this ‒ VDD part, what you can do here it is, we can
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simply shift this characteristic curve by an amount of VDD. So, this point we shifted to
VDD point which means that, now this new x-axis is this part plus VDD and that is equal
to.
So, this new x-axis it is VDD ‒ VSD2 and that is incidentally equal to Vout and that is
matching. So, this blue characteristic curve if I consider then I do have ISD2 versus Vout
so, that is what you are getting. So, this blue line characteristic curve, now we can
superimpose here. So, we may consider this blue line characteristic curve and how is it
defined? First of all this point it is VDD. And then whatever the slope it was having
original slope it is having this slope got changed, but the magnitude wise this slope
remains the same.
So, this blue line it is working as load line for this common source amplifier having
active load. Now if I compare the slope of this line and then if I compare the slope of this
line. So, that gives us the gain of the circuit. So, intuitively you may say that the voltage
gain Av equals to slope of this line it is gm, divided by slope of this line. And what is the
slope of this line? Minus whatever it is. So, if you consider slope of this line, it is slope
of this line it is change in IDS or ISD with respect to VSD. In fact, this is nothing, but
of transistor-2.
So, since the slope here it got change here so; that means, the slope of this line it is
remaining same magnitude wise and hence slope of this blue line ; it is or whatever
you say essentially both are same. So, slope of this line it is . So, the voltage gain
here it is . In fact, there is a catch that so, so far we used to ignore the slope of the
slope of this I-V characteristic namely for NMOS I-V characteristic. That is because
whenever you are having passive load here compared to the slope of the load line we use
to ignore that.
Now; however, now we do have load line slope and the pull down characteristic slope
they are comparable. So, we should also consider the slope of this line. In fact, if I
consider if I rather ignore this slope or if I say that the device; the pull down device I-V
characteristic it is having almost 0 slope then this is the correct expression of the voltage
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gain. But then if I consider finite slope here then, I need to consider this slope also and it
can be shown that. So, that part it is coming here as gm.
So, if I ignore the slope of the NMOS characteristic, then the expression of the gain it is
gm1 × rds2 on the with a ‒ sign. On the other hand if I consider slope of this line, then
instead of considering rds2 I should also consider rds1 and that is coming in parallel. In
fact, whenever we will be talking about small signal equivalent circuit, this will be very
clear. So, as long as if I say that both the slopes are comparable, I have to consider both
the rds together.
So, in summary what do you obtain here it is that, because the load line slope, it got
changed compared to the earlier slope; earlier slope means the passive load line slope.
For the same operating point if I consider this is the sorry this is the load line for passive
load. And this is the load line for this active load coming from the MOS. So, naturally
the if I am having given variation of the input signal say with respect to quiescent point,
we do have a variation here and here.
And let you consider this variation and this variation are essentially representing this
characteristic curve and this characteristic curve with respect to the quiescent point. Then
with active load what we have here it is, the output it is changing from here to here. So,
so it is a big change versus if I consider on the other hand it is passive load for the same
variation the intersection point of the device characteristic and the passive load line it is
one is here, another is here.
So, if I compare the corresponding output here it will be only this one. So, with passive
load we do have only this much of output; on the other hand if it is active load if it is
active load here, then the output it is much higher. So, intuitively at least it is very clear
that how it is helping to enhance the output signal amplitude for the same variation of the
input signal here. So, this is intuitively and we can also analyze this circuit using its
small signal equivalent circuit.
908
So, in the next slide we do have the we have drawn the small signal equivalent circuit for
the common source amplifier having active load. So, here let us see, what the
information we do have is. First of all transistor-1 its model it is given here by the
voltage dependent current source of gm1vgs1.
In fact, this vgs1 it is defining the small signal current here, which is gm1vgs1 in addition to
that to take care of the finite slope of the MOS. In the NMOS transistor to take care of
this finite slope, which is rds; rds1 we need to consider this also. Likewise if I consider say
PMOS transistor M2 it is having voltage dependent current source and its current is
flowing from drain to source. And then the current is gm2 of this transistor multiplied by
vgs and vgs is this voltage where we are calling this is vgs.
So, the gate voltage it is +ve and then source is ‒ve. But since we do not have any signal
here, this is also DC voltage. So, we can see that this is AC ground and this is also
anyway this is DC voltage so, that is also AC ground. So, we can say for this circuit we
do not have any signal. So, in small signal we consider this is equal to 0. Since this is 0
so, we can say this part is 0. So, we do not have this element. So, that makes the pull up
element or the load part simply getting replaced represented by this corresponding rds2.
So, if I analyze this circuit ignoring this current and then, whatever the voltage will be
getting here due to this signal that is the final signal voltage. So, let me do the simple
analysis.
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So, first of all if I call this is vin; so, we call this is say vin and we are applying this vin
with respect to a DC voltage and in AC signal of course, the DC part it is it is not shown
here; incidentally this vin = vgs1. So, the current flow here it is gm1vgs1 and as I said that
this part it is 0.
So, we do have only this rds. So, this current gm1vgs1 it is flowing through rds1 as well as
rds2. In fact, the other end of rds2 it is connected to AC ground rds1, it is connected to
ground. So, I should say that this current while it is propagating through both the
resistors I can simply combine these two resistors. And then you may say that the simple
circuit it becomes like the 2 rds, they are coming in parallel rds1 and rds2. And the current
flow here it is gm1vgs1 which is incidentally equal to vin.
So, this side it is ground and whatever the voltage you do have here it is the output
voltage. And that is equal to since the current is flowing in this direction that = ‒ gm1vin ×
(rds1 ⫽ rds2). And that gives us the voltage gain = ‒ gm1 (rds1 ⫽ rds2) right. So, that is
what the small signal analysis it is giving us ah. In addition to the gain, we can also see,
what is the corresponding output resistance. And to get the output resistance what you
have to do in the small signal equivalent circuit, we need to stimulate this circuit by
signal source at this point.
And let you call this is vx and let you observe the corresponding current and while we are
doing this exercise, we have to make this is equal to 0. So, if I make this is 0, this is also
910
0. So, this is also getting removed. So, what we have here it is only rds1 and rds2
connected to their corresponding ground. So, naturally if I simplify this circuit with this
stimulus, what we have here it is the stimulus called vx. And then we are observing the
corresponding current here ix. And inside the circuit we do have rds2 and rds1 connected to
their respective ground.
So, it is very trivial now the circuit becomes very trivial. So, we can say that is nothing
but the resistance (rds1 ⫽ rds2) and that is what the output resistance of this circuit. So,
along with the voltage got increased the corresponding resistance also got increased. You
may recall if it is a passive load says RD then the output resistance predominantly it was
defined by the passive load RD. Now this resistance in this active load since it got
increased.
So, the upper cutoff frequency if it is defined by output resistance and the load
capacitance CL, then of course, the corresponding upper cutoff frequency ω or let me
write in terms of Hz. So, upper cutoff frequency fU it is defined by ; then the
corresponding load capacitance and then the resistance which is rds1 ⫽ rds2.
So, with passive load of course, this resistance it was lower and then the bandwidth it
was higher. Whereas, for this case the in the resistance got increased as a result the
corresponding upper cutoff frequency got decreased. So, if I compare common source
amplifier having passive load and active load and then if we see their gain and bandwidth
particularly, what kind of comparison will you get for passive load? Let me use this
space to compare. So, this is the frequency axis and this is the gain in dB.
So, for passive load suppose we do have a gain here and then the corresponding 3 dB
bandwidth for a given CL. And then in active load circuit we do have gain got increase
because the output resistance got increased, but then bandwidth got decreased. And both
of the changes are both of the changes are getting created by the same entity called Rout.
So, as a result this bandwidth here it got decreased by the same factor as the gain got
increased.
And their gain bandwidth product if I say here it is single pole role, then gain bandwidth
product it is remaining same. Similar kind of things you can get for common emitter
amplifier also and let us see the corresponding yeah.
911
So, here we do have the corresponding circuit; namely common emitter amplifier having
active load. So, we do have transistor-1 the main amplifying device here we do have
relatively more practical circuit. The device-1 it is getting biased by its own resistance
RB1.
So, it defines the IB and then it defines the corresponding DC current IC and likewise
transistor-2. So, this is PNP transistor and its current particularly the base current it is
flowing in this direction through RB2. And this IB2 it is also defining the collector current
IC2. Now in this case similar to common source amplifier, we have to pay attention
additional attention. So, that these two currents should be equal of course, again there is
no other DC path we do have. So, natural question is that anyway both the current should
be equal from KCL, but then we also like to keep both the devices in active region of
operation.
So, in active region of operation these two currents IC1 and IC2 must be equal. And IC1 it
is defined by its corresponding (β × its IB). On the other hand the second transistor its
collector current is β its own β and then IB2. And then the base current here it is coming
( )
from its bias circuit namely these RB1. So, we can say that IB1 = . So, this is
( )
what the IB part. So, that should be equal to β2 × .
912
So, if you see here in case β the 2 transistors β’s are different, then you may
appropriately adjust the corresponding bias element. So, that eventually both the devices
currents should be remaining equal if they are even if they are in active region of
operation. So, we need to have appropriate fine tuning of these two resistances to ensure
this condition. Now here for basic operation of this circuit let we assume that this has
been achieved by some means and then we proceed for the subsequent analysis. So, that
is the assumption that proper care has been taken care and that ensures these two currents
are equal. And then the signal point of view.
Now, at the base of transistor-1 we do have the Ib1 versus Vbe1 and this Vbe1 it is at this
point. Of course, it is having a DC voltage without considering the signal part, but the
moment we apply the signal here the voltage here it will be the voltage here it will be the
corresponding DC voltage in addition to that, whatever the signal we do have.
So, we may say that Vbe1 it includes both the DC part plus this signal part and this signal
part we are assuming it is directly coming there. So, the operating point it will be decided
by this RB1, but then with respect to that we do have the small signal also. And then if I
multiply with β, if I consider this current and if I multiply with the current gain of this
transistor-1 so, that gives us so, that gives us Ic let me use different color.
So, that gives us Ic1 with respect to Vbe1 and again here we do have the exponential
relationship. And so, this is the operating point with respect to that would it may be
913
having variation because of the signal we are applying there. And then at the output at
the output port what we have here it is similar to the common source amplifier. Q1 it is
having the characteristic which it is known, initially it is in saturation then after that it
enters into active region and so and so.
So, these are the characteristic curve for the pulldown element namely for Q1. On the
other hand if I considered Q2 it is similar to the PMOS transistor, but we can say that its
ISD rather ISD versus VDS curve we have seen for this case we can see IC2 versus. So, IC
now it is flowing in this direction IC2 versus VCE characteristic. So, this characteristic it is
similar to NPN since we are considering VCE2. So, it is and also the direction of this
current it is from emitter to collector. So, this is also +ve and hence it is coming in the
first quadrant.
Now, if you see this x-axis this is Vce of transistor-1, which is Vout and of course, the y-
axis it is Ic1. Now this Ic1 and Ic2 whether it is DC or small signal wise they should be
equal. And to superimpose this load line characteristic here the corresponding x-axis
should also be equal. Now again similar to MOS transistors circuit this is not equal to
this axis. However, this is equal to Vcc ‒ Vout.
Now again to get rid of this ‒ sign here and then this Vcc part here what we have to do
operation. Namely we have to flip the characteristic curve to get rid of this ‒ sign here.
And then we have to shift the characteristic curve by a VDD amount to get rid of this part.
So, as a result the original red color characteristic curve we are transforming into this
violet color where this point it is Vcc and this entire characteristic curve which is it is
getting flipped here. So, now, we can superimpose this transform characteristic curve and
that characteristic curve it is coming like this.
So, this is the characteristic curve obtained from the PNP transistor Q2 and these are the
characteristic curve of Q1. So, again here since we do have the slope of this active load it
is quite small. So, we are expecting the gain it will be quite high. In fact, this slope if you
see it is of transistor-2. As you have discussed for P-MOSFET similar to that for this
PNP transistor the slope here it is . On the other hand slope of this characteristic
curve, as I said that since these two slopes are comparable we need to consider both the
slopes and this slope it is .
914
So, the overall gain starting from vbe if I call this is the input, if I say that the input we
are applying here. So, if I call this is it is having the DC plus the input part here. So, vin
this vin it is getting reflected by this mirror. In the form of ic this ic, it is coming here and
then it is getting reflected by load line. So, it is getting reflected here and in this form.
So, now, again in comparison with the passive load; if I consider the load line passive
load line, it is going through this operating sorry it is going through the operating point
and the VDD point here or in this case rather VCC point.
So, the slope of this passive load line since it is small. So, expect and earlier the gain it
was lower now that got gain got increased. So, again for this circuit, we can do the small
signal analysis. And then we can find that how the gain as well as the bandwidth it is
getting changed similar to common source amplifier.
So, here we do have the small signal equivalent circuit to do the analysis here, similar to
the previous case. The small signal model of Q1 it is given here consist of gm1vbe1 and
then ro1.
And then rπ in addition to that we do have this bias element; similarly for Q2; we do have
the small signal equivalent circuit given there. And then it is having the bias circuit it is
connected to ground here. Now the emitter node it is connected to VCC. So, that is AC
ground and this end also the other end of RB2 it is also connected to ground. So, as a
915
result there is no signal in this path, which means that this vbe2 = 0; that implies that this
current is also 0.
So, that converts this small signal equivalent circuit, it is much simpler where we do
have only this ro2 we do have ro1 and then gmvbe rπ and since the signal we are directly
given here. So, even though this is connected to ground this RB2, it is not having any role
to play. So, the small signal equivalent circuit what we have it is gm1vbe1. And then we do
have the rπ here rπ1 and the signal we are feeding here, it is vs and the resistance ro1;
connected to ground and eventually this ro2. It is also coming in parallel with that.
So, I should say this resistance it is ro1 and ro2 coming in parallel and this is connected to
ground; vbe1 it is defined here this is + and this is ‒. And then whatever the voltage it is
developing here it is the output voltage vout. So, here again if you see eventually this vbe
it is same as the signal here which we may call it is input signal we are applying here. So,
vbe1 = vin and vout equals to since the current is flowing in this direction it is ‒ gm1vbe1
multiplied by the resistance, which is ro1 ⫽ ro2.
So, this is ‒ gm1(ro1 ⫽ ro2) × vin. Or you may say that if I consider = ‒ gm1(ro1 ⫽ ro2).
So, the gain again it is getting increased because of the slope of the two devices active
device characteristic it is very small rather resistance is high. And also the resistance
output resistance, if you see at this point. So, to get the output resistance the method it is
same we can stimulate this circuit with say signal source of vx and then if you observe
the corresponding current ix keeping this signal equal to 0. So, if this is 0, this is also 0.
So, that makes this portion it = 0 and that gives the output resistance = (ro1 ⫽ ro2).
So; that means, the which is defining the output resistance. So, that is equal to (ro1 ⫽
ro2). So, in summary that we have the output resistance it is getting increased. And the
gain it is also getting increased by the same factor in comparison with earlier what we
have here it is here we are having RD. In case, we are having or RC rather RC in case if
we have say, passive element RC and same thing here also and as a consequence that if.
If you consider the load capacitance equals to CL then the bandwidth in the previous case
it was bandwidth it was defined by this resistance and CL and in this case in the output
resistance it is now (ro1 ⫽ ro2). So, similar to CE amplifier here also with passive load
gain if we plot say gain in dB with respect to frequency in log scale. Then suppose for
916
passive load gives a gain and then corresponding bandwidth here. On the other hand with
active load the gain got increased, but then bandwidth got decreased by the same factor.
And as a result the gain bandwidth product it is remaining same.
So, this is with active load and the other one it is with the passive load ok. So, so far we
are talking about the circuit with maybe a little bit idealistic situation and then also we
say that the two currents and this current and this current quiescent current should be
equal that can be tackled by some practical circuit. So, let me touch upon that practical
circuit.
So, here is a small change now you can see here that the yeah. We do have let me use red
color this RB2 instead of connecting to ground we are intentionally connecting this to the
collector and that gives that creates a feedback. In fact, later we will be discussing this
part.
So, depending on the value of this resistance and the condition of or the DC voltage here,
the current here the IB it will be defined. And whatever the resistance you are taking here
that primarily defines this current. And this transistor it is very now it becomes it is
accommodative to whatever the current it is defined by this Q1; namely if the current
here it is more than this voltage may become lower that makes this IB it is higher that
makes its corresponding IC it is also higher.
917
So, this RB2 as it is giving the information of the output voltage to its base we may say
that it is working in feedback connection. However, you need to be careful that while this
RB2 connected to the output node it is providing a ‒ve feedback to stabilize the operating
point and it ensures that the operating point it is easily achieved. Namely it ensures this
IC1 = IC2 easily, but at the same time there is a chance that this RB2; it may feed the signal
back to this transistor and it may and that may reduce the gain of the circuit. To avoid
that, we put some extra capacitor here.
So, that the vbe voltage or vbe voltage of transistor-2 signal wise it remains 0. At least in
the mid frequency range this additional capacitor; it ensures that this this transistor it is
really working only for giving the support not for any amplification or any feedback
operation in the mid frequency range ok. So, if you consider it is a small signal
equivalent circuit which is shown here in the next slide yeah.
So, this is what the discussion here that if we connect this RB2 here; that means, this RB2
it is connected here it is not connected to ground. So, if we do not put this capacitor here
then naturally then it will be providing one nonzero value of vbe2 as a result this current it
will be flowing as a non-zero entity. And there is a consequence in fact, looking into this
circuit this active device it will provide additional conductance.
So, the output resistance it is not only ro1 and ro2 coming in parallel. In fact, for this
circuit if I do not consider this capacitor and hence if I do not consider this connected to
918
AC ground, then Ro you can find that this is coming in equals to ro1 ⫽ ro2 ⫽ . In
fact, you can simplify it further you can consider this = β. So, that = ro1 ⫽ ro2 ⫽ .
In fact, if I also need to consider this path.
So, it may be even the additional one also. And this is equal and that becomes primarily
dominated by this and it may be reducing the output resistance drastically. And the
consequence is that if the output resistance it is drastically getting reduced from whatever
our original target of ro1 ⫽ ro2 only that will drastically that may affect the gain. In fact,
that will affect the gain drastically.
And that makes the even though the active circuit we may call it is active circuit gain of
the circuit it may go back to the previous circuit. Numerically we will see that how if I
consider practical value of this RB2 and then β then, we will see that gain it may not
change much compared to common emitter amplifier with passive load. So, to overcome
this problem what we are considering now it is, we are putting this circuit here. And the
moment we put the circuit there it is basically we are making this is ground and that
makes this vbe = 0 and that makes this part equal to 0.
And that makes this circuit going back to the previous one except of course, this RB2 it
will be coming in parallel. So, instead of this part if I put the capacitor bypass capacitor
here then the corresponding Ro it will be ro1 ⫽ ro2 ⫽ RB2. Well, even though in this case
this RB2 it is coming in parallel with ro1 and ro2, but we know that the typically value of
this base resistor it is quite high. And all practical purposes it may remain unchanged
almost unchanged and hence the gain of the circuit it will be very good.
919
So, in summary of this modification what we like to say here it is. In this case by making
the connection of this RB2 to the output node, we are making the operating point easily
achievable. And then to avoid it is adverse effect on the gain namely the reduction of the
gain we are putting this extra capacitor which is making the base node of transistor to
ground and hence the corresponding gain it is remaining high. So, numerical value we
will see it later.
So, similar kind of practical circuit can be obtained for common source amplifier also.
920
This is what it is shown here. I will not be going in detail, but just to say that we do have
say one resistor here. We do have another resistor here to define the gate voltage of
transistor-1 and likewise we do have two more resistors here to define the gate voltage of
transistor-2. And then we have to ensure that these two IDS and ISD they should be equal
and both of the transistors should be in saturation region.
Now, to avoid the fine tuning and all or rather to get this condition easily achievable
instead of connecting this to ground we can connect this to output node. But then again
we must be aware that, the moment we connect this resistor to the output node it may
feed the signal back here and that may reduce the gain of the circuit because that reduces
the output resistance. To take care of that you can put here AC grounding capacitor
making the signal coming back here it is bypassed and making the active part of this
device equals to 0.
And then we can get the high gain and for this case if you put this resistor and if I call
this is a RG just RG; then the voltage gain for this case it will be gm1(rds1 ⫽ rds2 ⫽ RG) with
a ‒ sign. And the output resistance it is (rds1 ⫽ rds2 ⫽ RG). In fact, if you if you see the
previous circuit also, now if it is BJT there we have seen similar kind of things namely
this was ro1 this was ro2 and this was RB2 and same thing for this also instead of RG it will
be RB2.
921
So, we need to cover the practical circuits. So, that will be covered in the next class. So,
in conclusion what we have covered today it is, we started with basic motivation of
going into active load. Namely in improving the performance specifically the voltage
gain of common emitter and common source amplifier and then we have discussed about
the basic operation of common source and common emitter amplifier having active load.
And then we have done the analysis to get the expression of voltage gain.
And then output resistance for considering the idealistic bias condition. And then we
have discussed about practical amplifier circuit where the operating point is possible and
achievable with active load. And then we have seen the consequences or at least we have
highlighted the consequences. Namely the gain may get affected by those practical
circuits having feedback. And then we considered bypass capacitor there to avoid the
adverse effect on the gain. And the other two things we yet to cover it as on this topic is
that numerical examples may be little bit on the guidelines, but that will be covered in
the next class.
922
Prof. Pradip Mandal
Lecture – 68
Multi -Transistor Amplifiers: Amplifier with Active Load (Contd.) – Numerical
Examples (Part A)
Dear students, so welcome back to our NPTEL online certification course on Analog
Electronic Circuit, myself Pradip Mandal from E and EC department of IIT Kharagpur.
Today we are going to continue Amplifiers with Active Load we have started this topic
and today primarily we will be discussing about Numerical Examples.
923
So, the plan for today it is Numerical Examples and inherent design guidelines; while we
will be going through the numerical examples we will also be given hint towards how to
design a circuit specifically for CE amplifier having active load and then common source
amplifier having active load. So, this is BJT version and this is MOSFET version.
So, let we directly come to the circuit. So, here we do have one example yesterday we
have in the previous discussion, we already have mentioned that instead of having a
passive load we like to use active load and the purpose of this one we have discussed that
924
to enhance the voltage gain. And here we do have the different parameters of the two
transistors for Q1 β is 100, for Q2 β is 200, just for a change we are taking different value
of β.
And VBE(on) of transistor-1 it is we are approximating it is 0.6 VEB it should be mod

actually VEB of transistor-2 also we are assuming 0.6. The early voltage of transistor-1 it
is 100 V. So, likewise let you consider early voltage for transistor-2 also 100 V and then
the capacitances namely base to emitter Cπ1 for transistor-1 it is 10 pF and likewise for
transistor-2 it is 10 pF and then on the other hand base to collector Cµ it is 5 pF for both
Q1 and Q2.
Then also we do have the information about the supply voltage. So, here we consider this
is 12 V and the bias circuits’ information’s are given here. So, RB1 we have taken 570 kΩ
and then RB2 it is 1.14 MΩ. And we are assuming that in case if we have some load
capacitance and it is value it is given here 100 pF.
So, you may have probably you might have observed that the value of the β of the two
transistors they are different. And then to make a balance of that the collector current of
transistor-1 and collector current of transistor-2 they should be equal and to do so, to get
that what we have done it is that the, base current of transistor-1 and base current of
transistor-2 we are making it different.
In fact, it is just compensating that so, to achieve that the value of this RB2 it is two times
of RB1 just to compensate the β difference. So, end of it what we are getting here it is
collector current of transistor-1 assuming the device it is in active region of operation it
is it is β × IB and IB it is supply voltage minus VBE(on) of transistor-1 divided by RB1 and
that is 100 multiplied by.
So, this is 12, this is 0.6 so, that is 11.4 and then RB it is 570 k. So, that gives us this part
it is 20 µA × 100. So, that gives us 2 mA. Now on the other hand if you see the
transistor-2 it is condition it is to find it is collector current it is equal to it is own β
( )
multiplied by the same supply voltage ‒ VEB, and so, this is β is 200 and
then we do have 11.4 again this part it is the 0.6.
And then in the denominator we do have RB2 which is 1.14 MΩ, 106 and again this part
though it is 10 µA, but after multiplying with it is own β. So, this is giving us 2 mA of
925
current. So, the bias resistors base bias resistors it is such that they are compensating the
β difference and finally, both IC1 and IC2 they are equal.
Note that in this equation we have not considered the effect of early voltage. In fact, we
should what we should do it is IC = βIB and then we should multiply with 1 + (VCE
divided by the corresponding early voltage). So, since this part βIB for both the
transistors they are matched then we should directly compare ( ) of the 2
transistors equal and that eventually gives the output DC voltage here.
So, to get the DC voltage at the output node say VOUT what we can do? we can compare
β1IB1 × ( ) of transistor-1 = β IB of transistor-2 × ( ) of transistor-2. Now
this part and this part we have seen here they are equal. So, now, just by equating this
factor what we can get here it is since the early voltage of the 2 transistors they are equal.
So, that gives us VCE1 = VEC2 and also we know that VCE1 + VEC2 = VCC. So, this is VC of
transistor-2, this is VCE of transistor-1 that is VCC which is 12 V and from that we can say
that both of them are equal and they are equal to 6 V. That gives us this output voltage =
6 V and hence we obtain the operating point of the 2 transistors namely so, let me
summarize the operating point.
926
So, we do have IC1 = IC2 = 2 mA, VCE1 = VEC2 = 6 V. And yeah so, the other things we
already have obtained namely IB1 = 20 µA and IB2 = 10 µA right. So, since this is 6 V
and this is point 6 V, this is supply voltage is 12 V, here the voltage it is 12 ‒ points 0.6.
So, that is 11.4 V. So, that is the operating point.
So, from that we can calculate the small signal parameters of the transistors namely in a
gm say gm of transistor-1 it is thermal equivalent voltage we can consider that is 26
mV. So, this is . So, that is ℧. So, likewise gm2 it is also = ℧, then rπ1 = β of
transistor-1 divided by gm of the transistor.
So, that is equal to 100 × 13 so that = 1.3 kΩ. So, likewise it can also find that rπ2 which
is β 200 and then gm2 it is . So, that = 2.6 KΩ. Then ro, but you have some space here.
So, let me utilize this one ro of transistor-1 which is early voltage of transistor-1 divided
by IC. So, this is 100 divided by 2 m, 10‒3. So, that = 50 kΩ. So, likewise you can also
find that ro2 = 50 kΩ alright.
So, that is how we obtained in the small signal parameter of both the transistors and then
we can try to find what will be the corresponding gain and so on and so. But before that
it is also important to see that if the DC voltage here it is 6 V if the DC voltage here it is
6 V, how much is the signal swing we can expect? From positive from this equation
point towards the positive side the voltage at the collector it can go as close as the supply
voltage in fact, supply voltage ‒ VCE(sat) saturation.
And we can assume that VCE(sat) of both the transistor around say 0.3 VEC of transistor-2
and saturation it = 0.3 V typically that is what it can be taken 0.3 V. So, we do have a 6
V, DC here and then if we consider this is 12 V. So, total here it is 6 V ‒ 0.3. So, the
positive side I should say that output showing in the positive side it is 12 V ‒ 6 V, DC ‒
0.3. So, that = 5.7 V.
So, likewise ‒ve side we can say that here we do have 6 V it can go as low as ground +
0. 3. So, we can say 6 ‒ 0.3. So, that = 5.7 V. So, output swing wise we can say it is ±
5.7 V, which means that the voltage here it can go as high as with respect to 6 V here. It
can go as high as 11.7 V, likewise lower side it can go as low as 0.3 V so, that is the
good swing.
927
Now next thing is that, how do we find the small signal gain and so and so, so in the next
slide what we can do we are going to draw the small signal equivalent circuit, but to
calculate the gain we need to remember these parameters particularly small signal
parameters values. So, you have to keep that in mind and then we will be utilizing this
parameter value in the calculation of small signal gain and so and so.
So, in the yeah so, here we do have the circuit it is for our reference it is shown here and
the corresponding small signal equivalent circuit it is drawn at this at this place. So, for
transistor-1 Q1 we do have the small signal model drawn here. So, likewise for transistor-
2 we do have the small signal model drawn here and then we do have RB1 here, RB2 here
and this node it is AC ground. So, that is why it is connected to ground.
And note that based on this vbe we do have gmvbe flowing here. And incidentally this
node the RB2 it is connected to ground and the other side it is also connected to ground
and hence we can say that this vbe2 = 0 V. So, that gives this portion = 0. So, as a result
we can ignore this part and then you can find what will be the corresponding vout in terms
of this input signal say vs.
Now, since we are ignoring source resistance here so, we can say that vbe1 incidentally
equals to vs assuming that this capacitor it is successfully bypassing the signal to the base
of transistor-1. And then we do have the current flow here gm1vbe1 and that is flowing
through ro2 as well as this ro1. So, the corresponding vout equals to since the current is
928
flowing in this direction and the polarity of this voltage we are defining like this is
positive.
So, the vout it will be minus the current flow gm1vbe1 which is vs then multiplied by the
equivalent resistance of this ro1 and ro2 which are actually in parallel connection. So, after
making the supply node to connected to AC ground these two resistances they are
coming in parallel and if you recall that ok. So, this gives us the that is the voltage
gain Av and it is it is expression is gm1(ro1 ⫽ ro2).
So, we can say that the voltage gain = gm1 it is and then ro1 and ro2 both are 50 k in
parallel. So, they are giving us 25 k. So, this is and that is equal to something like
1900 I made I have done some calculation for you 1923. So, that is this is the gain. Now
we can try to calculate the input resistance based on the information available, but let me
clear the space yeah.
So, input resistance on the other hand it is Rin = rπ1 ⫽ RB1 and you may recall that rπ1 it is
equal to 1.3 k that is in parallel with 570 k. So, you may approximate that this is 1.3 kΩ.
So, we obtain the voltage gain, we obtain the input resistance. So, next thing is so, this
two are done and next thing is that output resistance.
929
So, to find the output resistance what we have to do? We can stimulate this circuit by a
signal called vx and then we can observe the corresponding current here. If the current is
ix then you can say that the output resistance Ro = . So, that is the methodology we
follow to find the port resistance and while we are doing this exercise we have to
consider the other sources signal sources at 0.
So, we can say this is equal to 0. So, that makes vbe also equals to 0. So, that makes this
is also equals to 0 and this source anyway this is 0, we do have ground here, we do have
ground here. So, the vbe2 same as in the previous case it = 0. So, that gives this part also
equals to 0. So, we do have. So, we do not have this part, we do not have this part, only
we do have ro2 connected to ground here and ro1 it is also connected to ground here.
In fact, directly we can say that this Rout = ro1 ⫽ ro2 and both of them are 50 k. So, 50 k
two 50 k is in parallel that gives us 25 kΩ so that is the output resistance. So, next thing
is that the input capacitance. So, while you are talking about the input capacitance we
have to consider the Cπ and so this is Cπ and then this is Cµ. So, we do have Cµ here and
then we do have Cπ here and likewise here also we do have, but that is not really
contributing anything towards the input capacitance and you may recall that Cin it is Cπ
as is and then Cµ of transistor-1 multiplied by (1 + voltage gain magnitude of the circuit)
and this one we already have calculated it was 1923 or something we say.
So, Cπ it is 10 p and then Cµ it is 5 p × 1924. In fact, that gives us something like close to
10 nF. So, that is close to 9.63 nF I think I have done the calculation yes. So, this is
matching with that yeah. So, this is 9.63 nF and from this information 5.93 nF and then
this ok. In case if we have some source resistance then we can calculate the cutoff
frequency coming from the Cin, but since in this exercise we are considering RS source
resistance equals to 0.
So, it is contribution to the cutoff frequency we are not seen ah, instead the upper cutoff
frequency it will be decided by the load capacitance here and it is value it is given here
100 pF and the output resistance ro. So, the upper cutoff frequency = into output
resistance is 25 k, 25 × 103 and then we do have 100 pF which = 10‒10. In fact, if you
calculate this is coming and that is coming close to 63. So, that is 63.63 kHz ok.
930
So, in summary what we can say that the cutoff frequency it is getting reduced gain got
increased and output resistance also got increased of course, the input capacitance also
got increased. So, to summarize the performance of this CE amplifier with active load
probably we can see in the next slide and then we can compare performance of CE
amplifier having passive load. So, in the next slide we can see that.
So, here we do have the table to write different parameters namely yeah. So, we do have
voltage gain in case circuit load CE amplifier load if it is active load voltage gain what
we said is 1923, let me use different colors otherwise it is not visible to you yeah 1923.
Input resistance it remains same 1.3 kΩ, output resistance it was 25, 50 and 50 in
parallel; 25 kΩ. Then input capacitance it got increased 9.63 nF and 3 dB bandwidth if I
say the 3 dB bandwidth or upper cutoff frequency to be more precise ah. So, the upper
cutoff frequency it was 63.63 kHz.
Now if I compare this performance matrices with the performance matrices of CE

amplifier having passive load and here we do have the corresponding circuit and to keep
the 2 circuits comparable what we have done is that. So, we have taken this RB and the
corresponding β it is such that the collector current here it is 2 mA.
So, the corresponding gm and ro they are essentially same. In fact, early voltage we can
consider also VA, for this case it is not so important because we do have the passive load
which is dominating and resistance of that passive load it is given 3 kΩ. So, Ro of this
931
transistor it is 50 kΩ and the output resistance so that gives us output resistance of 3 kΩ
⫽ 50 kΩ. So, that is around 2.8 kΩ.
So, the voltage gain it is gm1 or this gm multiplied by this Ro. So, that = × 2.8 k. So,
that = 218, I have done this calculation for you ah. So, this is 218. On the other hand
input resistance you may say that it is getting dominated by this rπ which is same. So, this
remains 1.3 k and output resistance we already have said that (3 k ⫽ 50 k) for early
voltage of 100 V with collector current of 2 mA. So, this is output resistance is 2.8 k.
And then Cin of course, it depends on the voltage gain. So, since the gain here it is low
so, it is expected that the Cin is also lower. And we have done this calculation for the
same value of this Cπ and Cµ and that it comes 1.16 nF and the corresponding bandwidth
or 3 dB bandwidth here it was 562 kHz.
Now, if you compare these two and try to see the difference basic difference, the gain it
is higher so, almost 10 times higher and the resistance here it is higher. And also the
bandwidth if you see this is also close to 10 times higher. In fact, now the bandwidth of
the passive load corresponding to the circuit corresponding to passive load it is higher.
So, if you if you compare the frequency response for this active load and passive load as
it were anticipated.
So, if I say that the frequency response particularly higher side if you see. So, gain it is
very decent and then it is having 3 dB bandwidth and then for the active load on the
other hand the gain it got increased, but then the bandwidth got decreased. And the
increase here from here to here the increase here whatever the factor we do have that is
primarily coming from this Ro difference and same Ro difference it is also creating the
same effect here So, here it is getting increased.
So, this factor it is basically the factor by which this gain got increased and the
bandwidth got decreased it is same and which is defined by the Ro difference. So, if I
multiply this gain and then bandwidth that remains same and hence the gain bandwidth
product it remains same. In my calculation what I have done is that I simply multiplied
this gain and this bandwidth and it is coming close to 122 MHz for both the cases.
932
So, red one is with active load and the dark one it is with passive load. So, that is the
comparison of the two amplifiers ok. So, let me take a short break and then I will come
back for common source amplifier.
933
Prof. Pradip Mandal
Lecture – 69
Multi-Transistor Amplifiers: Amplifier with Active Load (Contd.) – Numerical
Examples (Part B)
We are talking about CE amplifier with active load and passive load. We discussed and
compared their performance. Before we go to CS amplifier, we must make a note of the
CE amplifier and the circuit we have discussed particularly its stability issue of its
operating point. Next, we will be talking that issue first, then its solution.
934
So, to start with suppose, we do have seen this circuit what we have discussed before.
And in case say the early voltage of the two transistors they are not consistent with
whatever we have planned and or in case if there is any variation of one of these two bias
resistors or maybe β of the 2 transistors if they are changing either with time or whatever
it is may be due to temperature or due to aging effect that it will directly affect the
operating point here.
You may recall whenever we have picked up the value of this RB2, it is picked up based
on the mismatch of this two β, but of course, we are assuming the early voltage of the
two transistors they are equal. So, the RB1 and RB2 difference if you see it is just to
compensate the β difference of the truth of transistor. Now let you imagine a case that is
suppose all the things are same, but then suppose this early voltage it got changed from
say it 100 to maybe 200.
Then this voltage if this is getting changed to 200. Then ( ) = 1 + (VEC of
transistor-2 divided by its early voltage). So, here we have assumed that β difference is
getting compensated by appropriate selection of the RB1 and RB2. So, then by equating
the current here and current here, what do you obtain it is that IC1 = IC2.
So, that gives us this relationship between VEC1 and VEC2. So, from this we can see that
= . And here we said that it got changed from on this particularly, early voltage
of transistor-2 got changed from 100 to 200 and hence it is . So, that gives us VEC2 = 2
VCE1. On the other hand; the summation of the two VCE and VEC = 12 V. So, from that
you can say that it will be converging to a meaningful value, say this is 8 V and this is 4
V satisfying this condition and also summation of this one is 12 V.
So, in case if the early voltage it is getting changed to 200, the voltage DC voltage at the
output node it is getting changed from 6 V to 4 V. Still both the devices are in active
region of operation, but of course the DC voltage got changed and as a result the ‒ve side
swing it is getting affected compared to the +ve side. So, you may still say that both the
devices are in active region of operation and the gain may be very good and so and so.
The problem it will be even more severe particularly, if β is getting changed and rest of
the things are remaining same. Say for example, we anticipated that the β it will be 200
and if this 200 it is getting changed to say maybe 180, then what happens?
935
So, suppose this β is getting changed to 180 and let you assume that rest of the things are
same, namely; VEB2 and VBE1 are remaining same as whatever you have planned and this
is giving us IB2 = 10 µA and this is giving us IB1 = 20 µA. So, what we have then β1
which is 100 × 20 µA × ( ) = 180 × 10 µA × ( ). We can say that
summation of these two VEC2 = VCC.
Now, you are getting here it is 20 × ( ) = 18 × ( ). So, of course, these
two VA ‘s are equal. So that is 2 + 0.2 VCE1 = 0.18 VEC2. So, now by putting the
expression of VCE1 into VEC2 or vice versa. You can get the value of the VCE1. And also
So, VCE1 = 12 V ‒ VEC2 ⇒ 0.2 (12 – VEC2) ‒ 0.18 VEC2 = ‒ 2.
936
Now if we rearrange this equation to find the value of VEC2 = ≈ 11.58 V, which
means that the voltage drop across transistor-2, which is equal to 11.58 V.
This is close to whatever the supply voltage you do have 12 V. That means the transistor-
1 is almost outside of its active region goes towards the saturation. Hence, the output
signal swing towards the negative it is almost close to 0.
So, we can see that yes the circuit is good with active load in terms of gain, but in a
process what we are making this output DC voltage also sensitive to process parameter.
Even a small variation in the β here what we have seen with 10% variation the output
showing it is heavily getting affected. So, we should say this circuit output node is very
unstable. Now to have a solution we like to have a stable bias and here we do have the
corresponding circuit.
If we compare the previous circuit and this circuit, this RB2 instead of connecting to
ground, we are connecting to this output node as a result it is making a negative feedback
ensuring that the output DC voltage it is not so sensitive to process parameter, but we
need to be careful that the signal we like to have good gain.
So, we are placing a capacitor here. Therefore, that the signal is not getting negative
feedback and as a result we can maintain the high gain of the circuit which we obtained
by this active load. So, let us discuss that circuit now.
937
This RB2 instead of connecting to ground, we are connecting into the output node. In case
this β is getting reduced and then what we are expecting is that this voltage may be
getting going towards the ground as you have seen and that makes the corresponding
base current IB instead of a constant current, that is getting increased and then, that is
making the corresponding collector current IC it is getting increased.
So, I should say this arrangement it is having some feedback mechanism which is
helping us to maintain this voltage remaining towards its middle point. But of course, at
the beginning we have to make some sensible calculation and sensible you know
selection of the value of the resistances.
So, if you put say 1.14 MΩ then also it will be, but I suggest that if we have a target at
this node of say 6 V and unlike the previous case where this was connected to ground
and for which we obtained the value of this resistance it was 1.14 MΩ.
Now, instead of ground we have a 6 V target and the RB is connected to this expected to
be connected to 6 V in normal circumstances. So, the selection of this RB2 should be
appropriate namely, instead of 1.14 MΩ, this should be reduced to maybe close to half.
Probably, close to say 570 kΩ. So, with 570 kΩ, it may produce this current close to
whatever 10 µA and then with the β of 200 the collector current it will be to the main
target it was 2 mA. Because the current here is still 2 mA. Then how do you calculate the
corresponding operating point?
938
Suppose, instead of taking this value of this resistance half of it; that means; instead of
taking 570 kΩ. In case if it is changing to this value and then what will be the
consequence at the output voltage or maybe in case if it is say 1 MΩ and in addition to
that suppose this is getting changed then, what happens?
So, in such situation, if you consider the KCL, KVL equation for this loop and then if
you keep this current IC1 which is directly obtained from its own bias and then β then we
can find a compact equation. Suppose, this output voltage is Vout then IB2 =
( )
and so, this is the IB2. So, this is IB2 after multiplying with β of the
transistor, we can get the corresponding collector current.
( )
We can get IC1 = β2 ( ). Before we go into 1 MΩ, let us try to see what
may be a suitable value here. So, since our target here it is 6 V. Let me put the 6 V here
( )
and whatever the β. And, IC1 = 2 mA. So, we are getting is RB2 = β2 ( ).
Note that in this calculation we assume ( ) ≈ 1. So, if you follow this assumption,
then the calculation becomes handy and practical. Therefore, with this equation we get
RB2 = 200 × ( ) = 540 kΩ. That is I was anticipating this resistance would be
coming close to its half value. So, if we target this is 6 V then we can take RB2 = 540 kΩ.
Now if I said this value of say 540 kΩ and then if I say this β is being changed to the
similar quantity maybe, say 180 instead of 200, then what happens?
So, now we are setting this bias resistor 540 kΩ expecting the output voltage will be 6 V.
But in our calculation; we have considered β = 200, but say unfortunately, this β got
changed to 180. Then what happens? So, again we can probably use this equation and
instead of using this is 6, we should use we should use rather we should rather find this
value for this is given as 240 k. So, what is the, how do you find the corresponding
output voltage in case this β is changing from 200 to 180?
939
( )
Let we do this calculation. So, what I said is 2 mA = β2 . Now from
this we need to calculate this VOUT. So, we do have ( ) . So, that is

equal to 2 mA, 2 × 10‒3 × 540 k, 540 × 103/β, β is now 180.
So, this part what we have it is, this is getting cancelled when this 0, 1 this 0 it is getting
cancelled this is 9 and then, so it becomes 6. Then that gives us VOUT = VCC ‒ VEB2. So,
that is 12 V ‒ 0.6 and then you have 6. So, we do have 6 ‒ 0.6, so that = 5.4 V find
forward. So, what is the conclusion here it is that we started with this RB2 = 540
expecting that β it will be 200 and the corresponding VOUT expected VOUT it was 6 V.
Now, the β got changed, this β got changed to 180. So, that is what we have taken here it
is 180 and due to that the corresponding VOUT got changed only to 5.4. So, this is a
demonstration that since this resistance it is connected to the output node it is creating
some feedback mechanism. So, that this output voltage remain insensitive to this bit of
variation right. Now if we put this resistor here connected to the output node, of course it
will be having a consequence on the voltage gain.
To take care of that we can put a capacitor here. So, that for signal this node base node
should not be having any signal. The signal should be getting bypassed by this capacitor.
However, this resistor is connected here that will maintain the operating point stability.
Probably, I have the corresponding calculation for that let me try to see in the next slide.
940
Here we have the circuit with feedback arrangement namely RB got connected to the
output node and also we have this capacitor to make the base node not affected by signal
coming through this resistor. Here we have the small signal equivalent circuit. It is
actually very similar to the previous case except this RB2, it is connected to the output
node. And also this node it is connected to supply voltage. We may say that this is AC
ground or simply you can say this is getting shorted. So, that makes this vbe2 = 0, that
makes this signal is 0. Leaving behind whatever the circuit we have before it is this
circuit is also becoming identical to that except of course this RB2 ⫽ ro2 ⫽ ro1.
And what is this consequence? The voltage gain AV becomes gm1(ro1 ⫽ ro2 ⫽ RB2). And
we have calculated the value of this gm1, ro1 and ro2. There will be some consequence
here since this resistor is getting dominated. In fact, let me do the calculation for you. In
fact, 25 k ⫽ 540 k = = 23.89 kΩ. So, we can say this whole portion it is
becoming 23.89 × = 1838. So, unlike the previous case where it was 1900, something
it was there. It got slightly decreased because you do have this resistance coming in to
the picture and that degrades the gain slightly. But rest of the things remaining almost
same. Of course, since this gain got changed slightly it will be having impact on this
input capacitance upper cut off frequency also it will be having slight change because the
output resistance it is getting changed, but still it will be in the range of say 60 close to
941
say, maybe 70 kHz. So, the upper cut off frequency it will be in this range. So, I think
you can calculate that and now going to the similar kind of exercise for CS amplifier.
So, we have here the CSamplifier circuit and we do have the corresponding bias resistors
and all. So, we do have this resistor it is 9 kΩ, this resistance it is 3 kΩ. So, that gives us
this voltage = 3 V. On the other hand we have 25 kΩ here and we do have 95 kΩ.
In fact, intentionally, I have taken different value of this transconductance factor for
transistor-1 and transistor-2. For transistor-1; we have 1 mA/V2 whereas, for this
transistor; we have 4 mA/V2. Now again for this case it is IDS current of the 2 transistors
should be equal. To compensate this difference we require different value of VGS ‒ Vth
for the 2 transistors. Also I have taken threshold voltage of the 2 transistors different.
One is 1 V here for transistor-1 and then for transistor-2 it is ‒ 1.5 V.
To compensate this trans conductance factor difference, here we like to have different
VGS ‒ Vth. So, you might have noticed that for transistor-1, VGS ‒ Vth = 3 ‒ 1 = 2 V. On
the other hand for transistor-2; (VSG ‒ Vth), I have taken so this is 2.5 ‒ 1.5 = 1 V. So, to
calculate the current which is ( ) .
Since this part, this part it is different for the 2 transistors; they are getting compensated
by this one. And here the difference ratio it is 4. So, the VGS ‒ Vth ratio since it is square,
it is 2. So, that is how it has been picked up the values of these resistors. I am sharing this
942
information so, that is in case if you have to design this circuit namely in case if you
have to find the value of the resistors from this information, then you will be getting a
hint how to calculate or how to get the DC voltage here and then how to get the value of
the resistors.
Note that the value of R22 and R21 it is quite different from R11 and R12, that is again it is
just intentional, but since its gate leakage it is ignorable namely, gate to source resistance
it is you can consider infinite then the value of these resistances are absolute value of the
resistances are not really important, the ratio is important.
We obtain IDS1 = ( ) . So, this is (2 V)2. So, IDS1 = 2 mA. In fact, you
can also find ISD of transistor-2 is also 2 mA. From that you can calculate the small
signal parameter, but before that the output voltage to get the DC output voltage since
these 2 parts of the 2 transistors are equal. To get the DC output voltage, I need to
consider (1 + λVDS) of the 2 transistors and if I equate them namely (1 + λVDS1) and to
VDS and λ2VSD2.
Since both the lambdas are equal. So, that gives us VSD2 = VDS1. However, summation of
these 2 quantities is equal to VDD which is 12 V. So, that gives us both of them are equal
to 6 V. So, that gives us this voltage is 6 V and hence we obtain the corresponding
operating point. Now from that we can say if this is 6 V, we have the voltage at this node
we have 12 V and this drop it is 2.5 V. So, the voltage here it is 9.5 V.
So, +ve side swing wise, +ve side you can say that the signal can go from this 6 V, DC
till 1 this transistor-2 entering into the saturation region, rather going out of the saturation
region. So, what will be the limit the gate voltage it is 9.5 plus its magnitude of this
threshold voltage. So, that is becoming 11 V. So, the upper limit of the output voltage it
is 11 V that we obtained by considering its gate voltage plus magnitude of this 1.5.
On the other hand; lower side we have 3 V here DC and then minus Vth of transistor-1
which is 1 V. So, this voltage it can go as low as 2 V. So, the swing wise; if I say that
+ve side we have output swing +ve side it is 5 V; 11 ‒ 6 = 5 V and then ‒ve side, we
have 6 V ‒ 2 V. So, that is equal to 4 V.
So, this is what the basic difference compared to the BJT version and this MOS version
and then we can go for the small signal parameter calculation. In fact, we have done
943
before. So, if I consider this IDS, then what you obtain it is gm1 = 2 mA/V. On the other
hand gm2 = 4 mA/V and then rds1 = rds2 both of them are equal to 50 k.
Why 50 k? If I consider this λ and the corresponding IDS. So, both of them these resistors
are . So, that gives us 50 kΩ. So, from that we can find gain. In the
next slide we have the gain calculation.
So, we have the small signal equivalent circuit given here. It is very similar to on the BJT
version except of course, we do not have any rπ. So, the calculation here it is I should say
simpler and since this node it is connected to AC ground. So, the voltage here it is 0. So,
that makes this current = 0, leaving behind the circuit is having only rds1 and rds2 in
parallel and then this current incident incidentally vgs1 = vin.
So, the output voltage it is gm1(rds1 ⫽ rds2) with a minus sign and then of course, that is
vgs1 which is vin. So, that gives us the voltage gain = gm1(rds1 ⫽ rds2) = 2 mA/V × 25 kΩ,
so that = 50. Of course, this gain it is not so high. Mainly because its corresponding gm it
is quite low, but at least we can say that the gain got increased.
Likewise you can calculate the input capacitance, Cin = 10 + 5 × (50 + 1) = 265 pF. So,
input resistance of course, it is just parallel connection of this R11 and R12. So, that is
very simple that is coming 3 kΩ ⫽ 9 kΩ and I guess it will be 2.25 kΩ. And the upper
cut off frequency fU, which is this rds1 ⫽ rds2 which is ro × CL, CL it is connected here
944
and the CL it is again 100 pF and this is earlier we have done this calculation. This upper
cut off frequency it is 63.63 kHz. Now, if you compare these performances with the
standard one namely circuit with passive load.
So, in the next slide we have the circuit to compare with. So, what we said for common
source amplifier with active load. The gain was 50, Rin was 2.25kΩ, Ro was 25 kΩ, Cin
was 265 pF and then bandwidth was 63.63 kHz. If you compare the common source
amplifier having passive load and if its bias condition is equivalent namely here we have
taken 9 kΩ and here it is 3 kΩ and the resistance here it is 3 kΩ.
So, that gives us this IDS current of 2 mA and hence the corresponding gm it is also 2
mA/V. Output resistance = (RD ⫽ rds) = (3 k ⫽ 50 k) = 2.83 kΩ. So, that gives us the
voltage gain = 5.66. So, the voltage gain here it is 5.66, input resistance it is parallel
connection of this bias resistors. So, that is remaining 2.25 kΩ. Output resistance as we
have calculated here it is 2.83 kΩ. Cin, on the other hand it is we have 10 here and then 5
× 6.66. So, that is equal to around 43.3 pF.
And the bandwidth if you consider the output resistance of 2.83 kΩ and this 100 pF, it is
coming 562 kHz. So, what we have seen here it is that gain got increased by this active
load. However, the 3 dB bandwidth got decreased and then input capacitance of course,
it got increased. And this increase and this decrease, they are having the same factor
mainly due to the change of this output resistance.
945
So, if I am having say circuit with passive load the gain it is very low and then also it is
having some bandwidth and then with active load the gain got increased, but then
bandwidth got decreased and their gain bandwidth product; however, remaining same.
So, this is the comparison of the common source amplifier having active load versus
passive load.
So, here also similar to the BJT circuit, here also the stability issue is there that can be
handled by the same approach namely connecting this resistor instead of connecting to
ground we can connect these to output resistance. But you have to suitably modify this
resistance earlier it was 95 kΩ, now we have changed this resistor to 35 kΩ.
This voltage with whatever the parameters are given here namely 1 mA/V2 for transistor-
1 and then for transistor-2, this is transconductance factor it is 4 mA/V2 and also
threshold voltage it is we are keeping same with this resistance need to be changed from
95 kΩ to 35 kΩ and with that we do get this output voltage 6 V. This voltage difference
is 2.5 V. So, this voltage it is rather 9.5 V, this is a 3 V.
So, rest of the things of the 2 circuits are remaining same except of course, this resistance
coming in the expression of the AV. So, the AV = gm1(rds1 ⫽ rds2 ⫽ R21). So, there will be
slight decrease of the gain. So, that probably we can calculate this part it is 25 kΩ and
this part it is 35 kΩ. Likewise, the output resistance also is getting changed due to this
RB, RB21 and the expression of Ro it is (rds1 ⫽ rds2 ⫽ RB21).
946
So, you can find this 25 k ⫽ 35 k. So, you can find this value. So, I will not be going in
detail of that. So, the small signal equivalent circuit you can draw.
So, it is very similar, this vgs it is getting changed. So, the vgs it is getting changed to 0
and that makes this portion equals to 0, but then this R21, it is coming in parallel with rds1
and rds2.
So, in summary or in conclusion, what we have done here it is; primarily, numerical
examples we have discussed and numeric today we have extensively discussed about
947
numerical examples that also gives you a slight inside of the design guidelines and what
we have discussed here it is common emitter amplifier with active load and its
performance it has been compared with common emitter amplifier having passive load.
So, we have done the comparative performance comparison to motivate why we go for
active load. You also have discussed about the common name, how do you take care of
the stability issue that may be arising due to the active load making the output voltage a
very sensitive. So, similar to the BJT for MOS transistor also we have seen common
source amplifier with active load and its performance it has been compared with
common source amplifier with passive load. And also here we have discussed about the
stability issue and how to resolve that issue.
948
Prof. Pradip Mandal
Lecture – 70
Single- Ended vs. Differential Signaling and Basic Model of a Differential Amplifier
Yeah dear student, so welcome back to our NPTEL online certification course on Analog
Electronic Circuits. And myself Pradip Mandal from E and EC department of IIT
Kharagpur. Today’s topic of discussion it is Single Ended and Differential signaling and
Basic model of differential amplifier. So, let us see where we stand today compare to our
overall plan.
So, we are in module-7 in fact, we are about to start this module and so the main topic as
I said that we will be discussing about single ended versus differential signaling and the
basic model of differential amplifier. And if you see the overall flow we have completed
components. In fact, we also have completed building blocks in the previous class and
we are just beginning the modules.
So, in fact we may consider this differential amplifier it is one module depending on the
context it may be considered a building block also, but the depth at which will be going
in this course we can consider differential amplifier as a module.
949
So, we are as I said that we are just starting this modules and today’s topic of discussion
it is entering into differential amplifier. So, what are the concepts we will be covering
here? The basic difference between a single ended amplifier and a differential amplifier.
In fact so far whatever the amplifier we have discussed whether it is voltage mode or
current mode primarily it is single ended amplifier. And we are going to start differential
amplifier.
So, naturally we need to understand the basic difference of these two kinds of amplifiers,
and also we need to understand the how we activate the circuit. Particularly if it is single
ended amplifier; the way we feed the signal it is quite different or rather for differential
amplifier I should say the way we feed the signal it is quite different compared to
whatever we have done for single ended amplifier.
So, we need to have fair understanding or we need to be comfortable of discussing about

differential signal pair and then individual signal which we call single ended signal. So,
we will be talking about what are the different two components are there in a differential
signal pair. Namely differential mode signal and then common mode signal and then
when do you call say two single ended signal individual signal they are equivalent to a
pair of signal, namely representing a differential signal.
And then we shall discuss about basic model of differential amplifier and we shall
discuss and introduce basic parameter of a differential amplifier. If time permits then we
950
may also go into numerical examples. So, to start with let we go back to single ended
amplifier and its basic operation.
So, the basic operation of single ended amplifier as I said that we do have the main
amplifier, the circuit it is getting activated by a DC source called Vcc or Vdd. So, with
respect to ground we are putting a DC voltage here and then we do have one more port
where we are feeding signal called vin. The signal need not be always voltage it can be
current also.
So, the signal whatever whether it is voltage or current we do have a different port for
the signal to feed into the circuit. Likewise for signal at the output we do have another
port the output port for the signal. And if you have observed carefully that both this input
as well as this output, if they are voltage we are comparing the signal with respect to the
common terminal called ground.
Now, this Vin it may be having 2 parts namely a sinusoidal part and a meaningful DC. In
fact, if we have the DC power having positive supply and ground then most of the cases
this DC part is essential for proper operation of the electronic circuit here. Now, how do
we feed the signal? We may be having different arrangement namely we can generate
this DC voltage or DC current by some circuit and then we can feed the signal part
through a signal coupling capacitor.
951
As you can see here the CE amplifier we have seen this circuit quite often. And we do
have a DC bias here the DC bias it is coming from RB from the supply and then we do
have the signal source which is getting couple to the input port through this signal
coupling capacitor.
So, in general you may say that at this point we are feeding this signal along with either a
DC voltage you may think of or you may consider it is a current, but whatever it is this is
the signal primarily this signal it is we are giving with respect to common node maybe
having a DC voltage, but the signal it is with respect to common node. And the way we
are giving this signal it is referred as single ended signaling.
So, we do have a signal one terminal of the signal port connected to the input here, the
other terminal of the input port it is connected to DC voltage or you may say that signal
wise it is connected to ground. Now, this amplifier may be having a model in the form of
a voltage amplifier or in the form of current amplifier. So, whatever the discussion will
be having now it is applicable for both current mode signal as well as voltage mode
signal, but then without loss of generality we may focus on voltage mode amplifier.
So, in our subsequent discussions we will be assuming that signal it is in the form of
voltage both at the input port as well as output port. But most of the discussions
subsequent discussions we will be having it is applicable for current mode amplifier also.
So, what we have here as we understand the basic operation wise for single ended
amplifier basic operation wise; we feed the signal at the input port and then we observed
the signal at the output port. And then based on the input to output transfer characteristic
namely, if I plot say Vo with respect to Vin both Vo and Vin is having DC as well as the
signal component.
And suppose it is having say characteristic input to output transfer characteristics is

something like this ok. And then what we are doing is that at the input we are giving a
meaningful DC called says VIN and then with respect to this DC we are applying a
sinusoidal signal or signal; which is changing with time. And the corresponding
observation at the output port we do have maybe a DC voltage which is meaningful DC
voltage and then with respect to that DC we are getting sinusoidal signal. So, we may be
having the signal coming at the output it is like this.
952
So, this part what we call it is vin or it is called small signal input and whatever the signal
we do have with respect to this quotient point we call this is vout. So, in this circuit if we
plot the Vo with respect to Vin we got input to output transfer characteristic. On the other
hand if we keep our operating point fixed, and then if we consider some linear segment
of this transfer characteristic curve and then if you plot the vout namely the output signal
with respect to vin then we do get the input to output characteristic, but now we do have
the signal.
So, we do have only signal into our discussion or in our consideration. So, now, vout
versus vin and it is having a linear segment of this characteristic curve which is coming
here. And then circuit wise what we have seen that to get this relationship input signal to
output signal relationship, what we do; we translate the actual circuit into equivalent
circuit what we call small signal equivalent circuit.
And sometimes we may call it is linearized circuit and then also the DC sources namely
DC voltages, DC currents we do suppress that is because the operating point which is
having non zero value of Vin and Vout that is getting mapped into origin of a this new
transfer characteristic. Which means that we are intentionally dropping the DC part or in
technical terms we may say that, this node it is AC ground and also if this Vin it is having
DC part and the signal part. Then we are keeping only the signal part and then DC part
we are dropping which means that we do have at the input we do have only the signal
part with respect to AC ground
So, the actual circuit we are replacing by a small signal equivalent circuit or we may call
linearized circuit. So, for single ended amplifier we have done this exercise extensively
and for differential amplifier also we will do this exercise. But for our comparison of
basic operation of single ended amplifier and a differential amplifier let we let we
discuss in this domain. What we mean is that a small signal equivalent circuit domain or
linearized domain ok.
953
So, now we do have the small signal equivalent circuit here and here the input signal we
are giving with respect to AC ground and output also we are observing this output
voltage with respect to ground or AC ground. And since the signal at both the terminals
we are comparing with respect to common terminal. So, we can say effectively we do
have the signal terminal is only one. So, that is why it is called single ended signaling
and the corresponding amplifier it is referred as single ended amplifier.
So, whether it is CE amplifier or whether it is common source amplifier whatever the

amplifier we have discussed, so far all of them you can say that they do have a nature of
single ended amplifier. Now, we are going to discuss different types of amplifier called
differential amplifier.
954
So, let us see what is the basic difference of the two kinds of circuit. So, for your
reference we are keeping this; we are keeping this single ended amplifier and the
corresponding small signal model here and now here we do have the differential
amplifier. So, we do have the differential amplifier circuit here. So, the main circuit it is
here and similar to single ended amplifier we are giving the power from a DC source at
the power port.
So, we do have positive supply port and then we do have the common port or ground
port and then we do have the input signal port. So, this is the input signal port, now here
instead of having only one signal we do have two terminals; one is say one terminal is
here to feed a signal called Vin1 and then we do have one more terminal called this is for
signal Vin2. So, at the input port we do have a pair of terminals apart from this ground.
So, individually you may say that individually Vin can be treated as a signal here at
terminal-1 with respect to this common node. So, likewise the other signal Vin2 we are
feeding at terminal-2 with respect to this common terminal. And at the output similarly
for the output signal here also the output port it is having 2 terminals or 2 signals point
apart from the common terminal. So, we do have say terminal-1 at the output port and
then terminal-2.
Now, if you consider the in generalized case both Vin1 and Vin2 maybe having their signal
part or small signal part along with a meaningful DC. Similar, to a single ended amplifier
955
both Vin1 as well as Vin2. So, both of them are accompanying a DC; this DC part typically
for both the signals they are equal, but not necessarily they should be equal.
Now, as I said that will for comparison of this differential amplifier and single ended
amplifier. Let you consider its small signal equivalent circuit or linearized model and
then let you compare with respect to whatever the small signal equivalent circuit or
linearized model we do have for single ended amplifier. So, similar to single ended
amplifier here once we linearize the circuit, we are dropping this DC part namely we are
making this is AC ground. And likewise here also for both the signals we are dropping
this DC part and the signals we are given with respect to ground.
So, both the vin signal at terminal-1 it is given with respect to AC ground likewise vin2 it
is applied at terminal-2 with respect to AC ground. So, signal wise we do have a pair of
signal; one is vin1, another is vin2. So, likewise at the output we do have a pair of signal
one is vo1 and then vo2 both are with respect to the common terminal.
Now, what is the difference then compared to the single ended amplifier and this
differential amplifier? The signal for this differential amplifier when you say signal what
we what we consider as signal it is the difference of the signal we do have ‒ this signal or
to be more precise vin_d which is defined as vin1 ‒ vin2 so this is the input signal.
Unlike the case for single ended amplifier where we consider voltage here with respect
to ground. So, likewise when you consider output we consider difference of these 2
voltages as the main output. So, vo_d differential which is defined as vo1 ‒ vo2 and when I
say this is a differential amplifier having a gain of say Ad; which means that this Ad it is
essentially representing the relationship between this vo_d and vin_d right. It is it is not
really representing the relationship between say vin1 and vo1 in the form of single ended.
Rather it considers the difference of these 2 signals as the main signal. So, likewise for
the output also difference of this vo1 and vo2 it is it is considered as the main signal. And
then ratio of the 2 signals it is defined as the gain of the circuit ok. So, that is the basic
difference.
956
Now, what we have seen that if I again come back and compare whenever we will be
talking about the main differential amplifier its input port it is differential output port it is
differential.
On the other hand for common mode sorry single ended amplifier we do have; we do
have single input and then single output and they are with respect to ground. So, this
kind of signal it is referred as differential signaling versus whatever the signaling we are
doing here it is single ended signaling.
So, we need to we are quite comfortable with single ended signaling and we need to
make our self comfortable with differential signalling. And also we need to say that you
can consider that vin1 and vin2 both are they can be considered as individual signal. So,
whenever we are talking about say differential signaling it is essentially it is having a
differential signal pair right.
So, we do have this signal and this signal together and they together it is representing this
vin_d right. So, it must be having some relationship or meaningful relationship of between
say differential signal pair and 2 single ended signals ok. So, let us see what is the
relationship between these 2 kinds of representation of the signal.
957
So, if you see we will be talking about the relationship, but we need to also understand
that here we do have the small signal; here we do have the small signal equivalent
circuit, coming out of the differential amplifier. And here we do have a pair of signal and
we call it is differential signal pair. And we already have said that vin_d = vin1 ‒ vin2 right.
And also if you see that; if you take the common of this 2 signals so that means,
which you can say average of these 2 signal that is also another signal of course, it is
different from the main signal, but that signal it is considered as the common mode
signal.
So, we can say that whenever we do have a differential signal pair actually it is having 2
components; one is the differential mode component, another one is the common mode
component. In fact, if you see here since it is these two equations are linear equations in
case if we have this information namely; for a differential signal pair if we have the
information of this differential part and the common mode part then we can get the
individual signal.
So in fact, if we have individual signal we can get the differential part and common
mode part. And then alternatively you can represent this signaling in this form and this is
in terms of the common mode component and the differential component. So, let us try
to see that, but before that if I say this equation-1 and equation-2 what we can get it is a
958
vin1 you yourself can find that vin1 it is having 2 parts one is vin_c + . On the other
hand the other part or the other signal vin2 the second signal it is again it is having the
common mode part namely vin_c part and we do have the ‒ .
So, this is mathematically saying that if we have these 2 components given to us from
that we can get the individual signal. So, circuit wise on the other hand you can say that
if we have say vin1 and vin2 we can calculate this vin_d and vin_c. And then we can
represent this signaling in this form, what we have here it is this signal it is vin1. And if
you see this vin1 it is vin_c + so the signal coming here it is matching with this vin1.
On the other hand if you see the other signal the signal at this point and it is supposed to
be representing this vin2 and the signal here it is vin_c which is common and then we do
have ‒ .
So, the signal coming here it is vin_c + that is nothing, but the vin2. So, we can say
that we do have whenever we do have say differential amplifier and then invariably we
will be stimulating the circuit with a differential signal pair may be signal-1 and signal-2
and then these two signal if we can bundle them together and we can represent the
information in the form of differential part and common mode part and circuit wise this
is how we can represent.
In fact, the signal which is going to the positive input or something later we will be
discussing about that the meaning of that. It is referred as noninverting input and this one
is inverting input. The signal we are feeding at the noninverting input it may be
considered as something called true signal and the signal we are feeding at the other
terminal it is called complimentary signal.
So, these are the two terminologies we may frequently use so true signal it is basically
we are representing this vin1 and then complimentary part it is vin2. Now, as I said that if
we have this common mode part and differential part then individual signal we can
translate. So, we can say that if we have one differential signal pair that can be translated
into single ended a paired signal.
959
So the two ways of representation it can go back and forth while will be analysing the
circuit. So, again let we try to make our self comfortable and try to ah understand that
when do we called two single ended signals are together equivalent to a differential
signal pair. So, similar to the previous discussion here we do have two individual signals
or two single ended signals, both of them are with respect to common node and they are
getting represented here by a differential signal pair.
In fact, whenever we will be talking about differential signal pair instead of considering
two single ended signals invariably we will be representing the information in this form.
Namely the it will be having a common part called vin_c or the common mode and then
we will also be having a differential part; half of the differential part it will be going to
the true terminal and ‒ve half of the signal it will be going to the complimentary
terminal.
So, that is that is how we can say that we can always make the equivalence. So,
whenever you are talking about the equivalents for the input port. In fact, this is also
valid for the output port. So, if you see the output port and if I know what is the
differential output signal say vo_d and also if I know the average of these two signals;
average of these two signal and if I say the average of the signal is vo_c then using this
vo_d.
960
And vo_c we can express we can express the individual output signal. Namely vo1 = vo_c +
, the other signal vo2 = vo_c ‒ . Now, the natural question is that suppose we do
have 2 way of representing the signal; one is a pair of two single ended signal another;
one is a differential signal pair namely in the form of common mode component and
differential component. And then which one we should follow which convention we
should follow while we will be discussing the differential amplifier.
Now, the answer to that why we are going for this convention is that this circuit
differential amplifier it its response to vin_d and vin_c it is different. And whatever the
signal we are getting at the output port. In fact, whatever the signal we are getting at the
output port namely vo_d and vo_c; they do have nice linear relationship with vin_d and vin_c,
but not with the individual signal ok.
So, I think it will be clear in the next discussion. So, as the summary of this slide is that
in case if we have two ways of representing the differential signal. Namely one is this
way the other one is this way and if we are dealing with differential amplifier then we
prefer this kind of representation.
In fact, same way whenever we are considering the output before we go into the single
ended information single ended signal pair we will be considering the signal here in
terms of vo_d and vo_c. So, whenever we do have a differential amplifier then at the input
signal wise we will be considering that signal in the form of vin_c and vin_d. Likewise
961
whenever we will be talking about the output port and whenever we will be observing
the signal here the signal will be representing in the form of the common mode part and
the differential part.
And this block the differential amplifier in fact once it is getting linearized. So, if I
consider this linearized model then this circuit it can be characterized by considering
linear relationship among these quantities. Namely if I consider vo_d and vin_d and if I
take the ratio of the two namely, that represents something called differential gain.
So, likewise when you consider the other two quantities namely vo_c and vin_c and if I
take the ratio . So, that is defining another parameter called common mode gain. So,
this gives you an idea that whenever we will be characterizing this circuit in terms of this
two important parameter or called gain of the circuit then it is always better to represent
the signal in the form of vin_d and vin_c.
So, likewise at the output also whenever we will be talking about the signal we prefer to
use this convention rather than individual signal. And once you get this and these two
components namely common mode and differential component, then these two together
we can use to represent vo1 as I said that vo1 it is vo_c + and vo2 = vo_c ‒ all right
ok. So, we will be going further discussion towards that, but let me take a short break
and then we will come back.
962
Prof. Pradip Mandal
Lecture - 71
Single - Ended Vs. Differential Signaling and Basic Model of a Differential
Amplifier (Contd.)
So, welcome back after the short break.
So, we are discussing about the equivalence of the 2 single ended signal and differential
signal pair. Now let me give you some example of that maybe pictorial example of
representing individual signal versus common mode and differential part.
963
Suppose we do have say one signal something like this. See vin1 let me sketch that vin1.
So, we do have one sinusoidal part and on top of that with respect to that we do have
seen vin1, it is sinusoidal with respect to that bigger sinusoidal part right. So, we may say
that this pink colour is vin1 and then if I consider say vin2. So, that is also with respect to
this dotted blue line and that is also sinusoidal, but it is in opposite phase.
So, the pink one you may say it is true signal and the red one it is the complimentary
signal and inside that whatever you see this is the signal and difference of these two it is
basically the differential vin_d. So, vin2 is the as I said it is the red colour one and the then,
if you try to represent say these two signal namely the pink colour and red colour in
terms of say differential and the common mode component. So, let me draw the
differential part, let me use a colour say green. So, here you can see that the signal here it
is large up to this point let me use different colour otherwise you may get confused.
So, here you do have large signal and then here you do have signal going ‒ve, again here
to here we do have +ve and then ‒ve and so on right. So, what would this violet colour
signal? I have drawn namely this signal it is the difference of the 2 signals vin1 ‒ vin2,
which means that this is the differential signal right. So, this signal it is vin_d and then if
you observe carefully that if I take average of these 2 signals namely the common mode
signal is this blue line. So, this is a common part or the common mode signal. So, this
blue signal is vin_c .
964
So in case in case if you have a situation like this. Suppose your main signal is this one
the violet colour one, but then you do have a lot of disturbance getting represented by
this blue signal and in case if you want to really find the find out this signal and if you
extract this remove the noise part, the blue part then you can take help from this
differential amplifier, how will you tell while you are feeding the signal it is having
different response to the differential component and the common mode component.
So, if I say that it is a differential mode gain ad it is said high. So, if this is say high quote
and unquote high and the common mode gain ac if I say it is having low value then at the
output whatever the vo_d you will get vo_d it will be amplified. The amplified version of
this signal and then if it is low common mode gain, it is low then this blue colour part it
will be also coming here as common mode, but its strength it will be less.
Say for example, if I am having say amplitude of say this signal it is say 1. So, which
means that peak to peak it is say 2 V, whereas, a the blue one that you consider blue one
it is having large amplitude say 8 V. So, naturally if I try to amplify this signal both vin1
and vin2 by single ended amplifier then I cannot remove this component, but in case if I
am having a differential amplifier which is having say gain a differential gain of say this
gain it is 10 and say this common mode gain it is a only 0.1 right.
So then at the output what we will get vo_d will be having 2 V × 10 that means, 20 VP-P.
On the other hand the common mode part vo_c at the output port the common mode
signal, it will be 8 V × this 0.1. So, that is only 0.8 VP-P right. So, as a result whatever the
output voltage will be getting, it is primarily this signal it will be dominating. In fact,
pictorially if I try to draw it let me make an attempt to draw the signal whatever the
signal we will be expecting here.
We do have the blue one which is having very small amplitude only 0.8 VP-P and then we
do have this 20, we do have 20 VP-P differential and individually if I see. So, this signal it
will be the signal plus half of this . So, this = vo_c + . So, that means, over this
signal we do have this part which is which is in VP-P. In fact, it goes like this right
something like this and keeps on going like this which means that this pink colour it got
amplified like this and that gives us the vo1 part.
965
On the other hand if I consider the red part which is a vo2 which is vo_c ‒ which
means that it is also having this blue part, but then its peak to peak value it is only 0.8 V
and then also it is having a differential part half of the differential part which is having
10 VP-P. So, that signal it is coming like this right. So, what we have here it is you can
say that if I compare the input situation at the input, where the signal strength it was
almost or I should say it is very small compared to the that disturbance part or noise part
and that noise part if I consider output wise even individual signal if I see that almost
they are giving the good quality signal.
Now, you can imagine that if this am a differential gain it is higher and higher, which
means that this signal the differential output it will be more and if I can make the circuit
is smaller and smaller; obviously, then the blue part it will be getting suppressed. So,
qualitatively I can say that whenever we will be designing one differential amplifier, we
like to have a differential amplifier having differential gain as high as possible and the
common mode gain. On the other hand it should be as small as possible or it should be
having high attenuation and this is the main purpose this is the main objective of going
for differential amplifier.
We will be discussing that some more, but intuitively at least you understand that why
these 2 parameters are important for this differential amplifier. In fact, they are the vital
parameters of characterizing the differential amplifier.
966
So, whenever we do have a differential amplifier we like to have a basic model and the
basic model it is as I said that it should be having 2 important parameters the differential
mode gain which is defined by and then it is also having another important
parameter called common mode gain which is defined by and as I said that this
should be as high as possible, this should be as small as possible and that makes the
circuit more towards the ideal one and then only we can say that this circuit can remove
the average part or the common mode part and it appreciates the differential part.
Now if I write this equation say this equation what we can say that vo_d = Ad × vin_d.
So, likewise if I see this equation, we can see that vo_c = Ac × vin_c which means that if
the circuit it is linearized and if I stimulate the circuit only with this part keeping this = 0
then at the output we will be getting only vo_d and so, on the other hand the
corresponding vo_c it is expected to be 0. So, if I make this = 0. So, we are expecting this
should be 0 on the other hand if I consider say this is non zero. So, if this is this is non
zero and then if I make say the vin_d = 0.
Then what we are expecting is that vo_d should be = 0 and then vo_c maybe not 0, but that
is the idealistic situation which means that the circuit it is only allowing differential
signal in the form of differential signal at the output port and common mode signal at the
input port-2 common mode signal at the output port practically; however, there is a
chance of having a having a cross propagation namely the let me clear the board, yeah
namely this differential part, this differential part it may be appearing at the output in the
form of some part of the common mode signal.
967
So, likewise if I consider a say a common mode signal part that may come here in the
form of some part of the differential. So, we can say that individually then vo_c if I am
stimulating the circuits with both differential and common mode. So, we can see that vo_d
it is Advin_d plus some parameter multiplied by um, some parameter multiplied by vin_c
and this parameter seems it is converting common mode signal in the form of
differential. So, we can see that Ac_d. So, we do have one more parameter.
So, likewise if I consider differential part, sorry the common mode part. Let me use this
colour. So, vo_c ideally we want it should be is Acvin_c, but then practically some part of
the differential signal it may get converted may get converted in the form of common
mode signal and since the differential part it is getting converted into common mode
part. So, the corresponding parameter we can call it is Ad_c. So, apart from apart from Ad
and Ac which we already have defined here we may have 2 more parameters. So, we do
have differential to common mode gain and then common mode to differential mode
gain.
So, yeah. So, ideally as I said that we want this should be as high as possible and this
should be as low as possible. So, likewise here also we like to have both this parameters
should be as small as possible and it need to be observed that the we want both these
parameters should be as small as possible, but making this parameter smaller is
definitely, it is more desirable because it converts the common mode signal in the form
968
of differential. So, if I say that our main purpose of using this differential amplifier is to
eliminate the common mode signal which means that this is the unwanted part correct
and we want this part should be as low as possible and at particularly at the output port
they should not propagate.
So, in case if this part it is say non zero which means that this unwanted part it is getting
converted here in the form of differential signal and once this unwanted part it is sneaks
into the differential signal in the form of differential signal at the output port then we
cannot do anything. On the other hand in case in case say vo_c output common mode
signal if it is still significant then probably this signal we can put it into to the input port
of second differential amplifier, where we can further suppress this unwanted part and
then we can appreciate this part. So, we can try to suppress this part and we can
appreciate this part by putting the signal to another differential amplifier.
But then once we have this unwanted part namely the common mode part if it is getting
converted into the form of differential then by using the second differential amplifier,
there is no use because this differential amplifier it cannot really you know suppress the
unwanted part which already got converted into differential form. So, this circuit will not
be able to really distinguish whether unwanted signal it is getting converted in the form
of differential or the original differential signal it is coming here correct.
So, the summary is that this is most dangerous thing. So, definitely we want both Ac_d
and Ac should be low. So, priority wise; however, this is having highest priority to make
it as small as possible and then probably this one and then the third one is this Ac_d sorry
I will take it back the what I like to say that this part should be as small as possible which
converts common mode signal in the form of a differential. So, highest priority is this
one.
So, we do have highest priority to reduce this signal to as small as possible and um. So,
this parameters should be as small as possible and then the Ac and then Ad_c. So, in case
Ad_c it is non-zero which means that we do have some differential signal that may be
getting converted into common mode part, but anyway by the time we already have
significant amount of differential signal coming out of the differential input. So,
probably that is not so important. So, main thing what I like to say that the Ac_d should be
as small as possible. So, this is the highest priority.
969
And then this is the second highest priority and probably this is the third highest priority
to make all of them low and of course, this Ad should be as high as possible right. So, let
us try to do some numerical example yeah.
So, we do have some numerical example of which we already have discussed probably
with a different quantity and mathematically probably you can try it out differential
mode gain. It is say 20 common mode gain, it is say 1 and both differential to common
mode gain and common mode to differential mode gain they are say 0.
And this is the corresponding circuit and if I say that vin1 = a sin(ω1t) and vin2 = b sin(ω1t)
and then you can find what will be the corresponding vo1 and vo2. So, how do you
proceed? First of all the circuit is already linearized. So, though we are giving the
information in the form of single ended and both of the signals are having the same
frequency, but having different amplitude now if you directly approach using single
ended a signal it is not possible rather it will get complicated.
So, the better option is that let we convert the signal in the form of vin_d and vin_c. So,
what is vin_d here and the difference of these two signals, So, that is (a ‒ b) sin(ω1t) right
and then common mode signal it is ( )sin(ω1t) right. Now this differential part of
course, it will be producing differential output and the corresponding output we can get
by multiplying with Ad. So, we can say that vo_d = 10 rather 20 yeah.
970
So, that is 20 (a ‒ b) sin(ω1t) and then vo_c equals to we do have one common mode gain
it is 1. So, that is ( )sin(ω1t). Now by combining this 2 we can get the individual
signal. So, namely vo1 = vo_c + which means this is ( ) sin(ω1t) + 10 (a ‒ b)
sin(ω1t) right and um. So, if you consider further simplify what you are getting is um
yeah. So, {( ) + 10 (a ‒ b)} sin(ω1t) correct.
So, likewise you can get the vo2 = {( ) ‒ 10 (a ‒ b)} sin(ω1t) right. So, that is how we
can get the individual signal at the output alright probably we can work out on some
more numerical problems, but I think it will be more interesting if you consider say one
of these 2 entities nonzero and. So, let you consider say this is equal to 0 this Ac = 0, but
this is equal to 1.
So, instead of 0 if we consider this as 1 and if I consider on the other hand this is equal to
0 then you can find what will be the corresponding vo1 and vo2 and then the next part.
What you can do? You can consider this is 0 you can consider probably this equal to 0,
but then you may consider this is equal to 1 and this is also equal to 0 and then you can
see what is the corresponding vo1 and vo2 and then from that you can get an idea that
what is the significance and importance of this parameter if they are non-zero what will
what kind of problem we will encounter right.
971
I think that is all we have to cover then we need to conclude here what we have
discussed it is basically the single ended amplifier and differential amplifier. We have
compared in terms of their basic operation and then while we are talking about
differential amplifier, we do have a notion of something called a differential signalling.
So, then once it is coming differential signalling it is essentially a pair of 2 individual
signal, but it is really not a pair of individual signal.
We need to represent that a pair of signal in the form of common mode part and then
differential part. So, that while we will be dealing with a differential amplifier then we
can basically we can simplify the analysis and once we convert the signal in the form of
a differential part and common mode part then only we can make use of whatever the
parameter or the amplifier it has given namely differential mode gain common mode
gain to get the corresponding output whether it is in the form of differential or single
ended and. So, to do that of course, we need to make equivalence basically converting
say two single ended signals in the form of differential signal pair and vice versa once
you want to convert back into the single ended.
We also have discussed about the basic model of a differential amplifier and what are the
basic parameters of the differential amplifier. It is there namely a differential mode gain
common mode gain and then differential to common mode gain and then common mode
to differential gain and also we have considered one numerical simple numerical
example to understand the importance of a differential mode gain and common mode
gain, namely this need to be a high and this need to be low. In fact, both are the other
non-ideal parameters should be low.
In fact, we have said that this part particularly common mode to differential mode gain
should be as small as possible otherwise it may create a problem and of course, the
differential mode gain it should be as high as possible. I think that is all to share.
972
Prof. Pradip Mandal
Lecture – 72
(Contd.)
Dear students, welcome back to our NPTEL online certification course on Analog
Electronic Circuit; myself Pradip Mandal from E and ECE department of IIT Kharagpur.
Today’s topic of discussion, it is Single Ended to Differential Signaling and Basic
Models of Differential Amplifier. In fact, this is continuation of our previous lecture. So,
we are going to continue on the basic model of differential amplifier.
If you see the overall plan; we are in module-7 and we are continuing the first 2 items of
a module-7. And in the overall structure wise we are at the module levels of the circuits.
In fact as I said that it can be considered differential amplifier it can be considered either
block level or module level depending on the perspective and in this course we are
focusing this topic differential amplifier as module level discussion ok.
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Now the concepts we are planning to cover here, it is the following. So, yesterday or in
the previous course, in fact, previous lecture we have discussed about numerical
examples. So, we will continue some more numerical examples and based on the basic
model of differential amplifier to highlights what is the importance of different
performance parameters of the differential amplifier. After that we will be talking about
the motivation of using differential amplifier.
So, we are expecting after the first topic, we are expecting that we will be having fair
understanding of the behaviour of differential amplifier and then we will be talking about
where and when we need to use differential amplifier. Particularly, we already have
discussed about single ended amplifier. So, we have to discuss about the situation where
single ended amplifier may not be the preferred one rather we want differential amplifier.
And then we will be talking about different variants of differential amplifier starting
from the basic one which we have we already have started. And then, we will be talking
about which variants of the amplifier should be used in what condition right. So, coming
to the topic, we have discussed in the previous class namely, the basic model of
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We can consider this is the recapitulation of whatever we have discussed in the previous
lecture. Here we do have the differential amplifier as I said that the input port it is
differential in nature, output port is also differential.
We do have the main supply voltage and then we are feeding the signal at the input port
by say to single ended signal. And then at the output, we are observing the output either
at individual terminal output terminal with respect to ground or more appropriate way to
say that we can observe the signal in the differential form.
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And then as we have discussed in linear single ended amplifiers linearization so, this
differential amplifier can be linearized. And so, we do have the linear model here of the
differential amplifier and then at the input either we can think of that we do have one pair
of single ended signal or we may consider that it is carrying differential signal and
maybe it is having also common mode signal. So, we can represent this pair of signal in
this form, namely in terms of common mode component and the differential component.
And we have discussed that why we prefer this representation of the signal input signal.
Namely, because the behaviour of this amplifier differential amplifier it is it can be well
characterized. If we convert the signal in the form of differential signal and common
mode signal and then we can say what may be the corresponding output we get out of
this circuit.
And also we have discussed about four important performance matrices namely,
differential mode gain common mode gain and then differential to common mode gain
and then common mode to differential mode gain. As you may recall the differential
mode gain, it is defined as output differential by input differential. Assuming that the
common mode signal it is 0; vin_c = 0. So, likewise we can define the common mode gain
which is when differential component of the input namely vin_d = 0.
So, likewise if we consider the other two parameters namely, differential to common
mode gain which is defined as the differential signal is getting convert into common
mode; that means, when we do have the vin_c = 0. So, likewise we can define this
this parameter namely, Ac_d equals to and so, this is converting the common mode signal
in the form of differential. So, this is when we do have a situation where input
differential signal equals to 0.
And as I said that this parameter it is very dangerous thing, particularly we should pay lot
of attention. So, that this parameter should be as small as possible ideally should be 0
that is because it converts common mode signal in the form of differential signal. And
whenever we are talking about differential amplifier its basic purpose here it is to
appreciate the differential signal and also to suppress this common mode part. Now if the
differential signal it is coming as is in the form of differential, then there is no problem.
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If the common mode signals it is coming here, then also it is ok. But then toward this
output we may not be able to really separate this unwanted signal.
So, in summary this parameter which we one this should be as small as possible ideally
should be 0. On the other hand if say Ac or Ad_c if they are nonzero, but then we may say
that we can put one more differential amplifier to further suppress the unwanted part and
we compare to the wanted part, namely differential part or we can say that we can
appreciate the differential part and then we can suppress the common mode part.
So, this is what we have discussed in the in the previous class and let we go for some
numerical example.
So, yeah so, here in this numerical example, we are going to start with the linearized
model. So, we do have the main circuit here and the input we are applying here, which
are given here in terms of see differential part and common mode part. So, if you see
here, both the signals both the signals are having two frequency components.
So, depending on this T so, this part first part it is having a frequency of and its
amplitude it is 50 mV. So, this is of course, unit it is volt. On the other hand if you see
the second part, if you consider the second part it is having a frequency which is and
its amplitude it is 0.5 V; that means, 500 mV. So, on the other hand if you see the second
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frequency of and its amplitude it is 50 mV, but it is having a ‒ sign. And so, if I take
the difference of say vin1 ‒ vin2 to get the differential output vin_d.
So, what we are getting it is 0.1 ( ). So, these two parts the other higher frequency
part this part and this part. Since they do have the same sign once we subtract this two
input they are getting cancelled out. So, we can say that differential input it is having 100
mV amplitude and the frequency of . On the other hand if I take the average of these
two signals; if I take average of these two signals to get the common mode component
namely vin_c. So, that = and this = 0.5 ( ). And its frequency it is of
course, if I call f2 = .
So, this unwanted signal or common mode signals it is having a frequency one-fourth of
whatever they wanted signal or differential signal. Now once we have this signal paired
vin1 and vin2 represented in terms of vin_d and vin_c, then probably we can represent the
stimulus in this form. Where this signal it is submission of vin_c + .
So, this is the vin_c part and then this is the part. And the signal coming at this point
on the other hand, we do have vin_c ‒ . So, this is the common mode part and then we
do have ‒ , it is given here right. So, once we get this information the particularly the
signals are getting represented in the form of differential part and common mode part,
then probably we can look for the signal coming out of the differential amplifier by
considering its corresponding parameters.
So, what are the parameters we do have? We are expecting it will be having a differential
mode gain and then common mode gain and the other two parameters. Now suppose we
will be considering different cases and to start with ideally we want this circuit should be
having differential gain should be as high as possible and then the other parameters
should be as small as possible. So, to start with let we consider say case 0 or ideal case
where differential gain it is 40 and let we assume that the other parameters are 0.
So, if that is the case and we like to know what will be the corresponding output; either
you can think of the output signal in the form of differential part and common mode part
978
or maybe we can think of the individual signal with respect to common node. So, either
it may be in this single ended form or maybe in this differential form ok.
Now we will be talking about that namely once we have this information of say
differential gain 40 so, from that we can see that vo_d = Advin_d right. And that is coming
so, we can multiply this this signal with 40. So, that gives us 4 ( ). So, which
means that at this differential port we obtain a signal having a frequency f1 = and its
amplitude it is it got increased from 100 mV to 4 V right.
And if you see the common mode part on the other hand vo_c, since the Ac is not given to
us. So, we can assume that this is 0 and in fact, we can consider Ad_c = 0 and Ac_d it is
also 0. So, if I consider all of them are 0 then we can say that this is the sole vout and vo_c
of course, it becomes 0.
So, that gives us the individual signal namely, vo1. So, that gives us the vo1, let me use
this space. So, vo1 equals to, now we can convert this this representation of the output
information in terms of a pair of single ended signal namely, vo1 = vo_c + which is
equal to 2 ( ). So, likewise if I consider the other signal namely vo2 so, that is
equal to vo_c ‒ and that = ‒ 2 ( ).
So, this is what the signal we are getting here. So, as I said that this is ideal case. So, we
want this block should be intelligent enough. So, this block should be intelligent enough.
We suppose to appreciate the differential part namely it should amplify the differential
signal and it should completely ignore this common mode signal.
So, pictorially let we see what is it’s you know the corresponding input and output and
how we can further explain that what is the basic motivation of using this differential
amplifier.
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So, here we probably we can. So, we can use this graph. So, I have prepared this graph.
So, that we can probably sketch the waveform say for example, if you want to sketch say
vin1 and vin2. And since we do have this signal which is 10 times higher than this signal
probably the scale we can consider here it is say this is 0 and this is maybe is a 0.5 right.
And the signal here it is having a frequency of . So, we can consider this as the time
period.
So, this we consider 4T, this is 2T, this is T and this is 3T and so and so. Now, if we
consider the common mode part; so, this part which is there for both the signals. So, it
may be having amplitude of this much. So, the signal should be going through this point,
this point, this point, this point and this point. So, let me consider the common mode part
and then if I consider the differential part. So, if I consider only this part and its
amplitude is just to one tenth of this, which means that its amplitude should be only one
of the scales. So, this part so, it is having different frequency sorry, this should be having
a period of T.
So, it should be going like this and it is having in fact, 4 cycles right. So, this is the
differential part I should say rather half of the differential part. And if I consider the
other half of the differential part which is having ‒ sign so, this is just complimentary of
the red colour signal ok. So, we do have the differential part it is represented here and if I
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take the difference of these two signal; difference of these two signal it is essentially the
wanted part which we like to process or amplify.
And on the other hand this blue colour part we like to eliminate. And this is this can be
done by these differential amplifier which is having a gain is 40 and this this is actually
differential gain so, which is amplifying this signal. Now in the yeah so, if I consider the
total signal of course, if I consider this total signal; it is a combination of this blue and
the red. So, let me try to sketch that.
So, if I combine this blue and red and if we see the signal coming like this let me use red
colour just to represent it better right. And then here yeah here we go. So, this red colour
is essentially vin1. On the other hand, if I consider say vin2 let me use pink colour so, if I
consider this part. So, I need to add this pink colour signal with the blue one. So, I do
have the signal going like this.
And so, if I see the individual signal we can see that compared to the blue line the
differential part it is really small and it may be scary how we can really separate it out
this wanted part from the unwanted part right. So, this pink colour is vin2. Now out of this
we also said that we have considered the vout in the particularly differential part which is
( ). So, let us try to sketch that in the next slide yeah.
981
So, we do have the input signal, we are keeping as is and we are trying to sketch them
yeah we are trying to sketch the output. Now when we will be sketching the output we
may recall that vin_d = ( ) and that gives us vo_d = ( ) right. And from
that we obtain vo1, vo1 equals to half of this vo_d which is 2 ( ). And the vo2 = ‒
2 ( ). And let we say use this graph to sketch this two output.
And so, here we do have the time axis and here we do have the output signal can be
plotted along this y-axis. So, if we consider say vo1 and its amplitude it is 2 V. So, in this
graph probably, we can consider this is 2, this is 1, and this is 0. And so, the vo1 which is
having a frequency , let you consider the same timescale.
So, we do have T, 2T, 3T, and 4T. And we do have the signal vo1 which is having
amplitude of 2 and the time period of T. So, which means that vo1, its sketch it is like
this. So, it is having amplitude of 2 V and a frequency of right. On the other hand if I
consider the other output namely, vo2. So, let you consider vo2. So, that signal it is
coming this complimentary of it right.
And now we can see that the signal what about we are looking for that got nicely
amplified. And the unwanted signal unwanted signal it is completely getting removed.
So, if as I said that we are looking for this part or whatever this part shaded part which is
wanted that part it is coming here with nice amplification. Note that this scale and this
scale they are different, in fact, if you are putting in the same scale; obviously, this signal
could have been much bigger.
So, that is the basic purpose of this differential amplifier namely, suppressing the
unwanted part. Suppressing the unwanted part which is probably it is having some
reason somehow it sneaks into the signal and it is trying to corrupt the signal. But then
we do have this magic block called differential amplifier which is helping us to
completely suppress that. Now practically; however, this common mode gain Ac need
not be 0. In fact, the other parameters may also be having some significant value.
So, let us try to see what may be the consequence only you have a situation where a
common mode gain it is nonzero along with the differential gain maybe remaining as
high as 40 ok.
982
So, now here we do have a situation, here we do have a situation sorry, the I am trying to
return this waveform. So, that you can appreciate that what are the things it has happen
in between or earlier what was the situation. Now if you see I have change the condition
namely.
Now, we are considering a second or case 1, we say where it is not ideal situation namely
this is non-zero and since it is nonzero we are expecting that there will be some
difference in this output signal or to be more precise this common mode signal, the blue
colour signal it may be having some influence on this part.
So, in the next exercise what we are going to do it is basically trying to see what will be
the corresponding individual output and then I must say that once you have say clean
nice output, probably one of them is good enough to extract the information. But in case
if we have say common mode gain which is nonzero, then probably the signal coming
here either vo1 or vo2 may not be as clean as what we are plotting here instead, it still may
be having some unwanted signal.
So, let us try to see in this situation what may be the unwanted component ok. So, let me
take a small break and then we will come back.
983
Prof. Pradip Mandal
Lecture – 73
(Contd.)
So, dear students, welcome back after the short break. And we are talking about the
situation where we do have the model of differential amplifier and its parameters are
given, namely differential mode gain it is 40, common mode gain = ‒ 1 and then
differential to common mode gain and common mode to differential gain we are
assuming they are = 0. And, the signal we are feeding here at terminal-1 called vin1.
It is having common mode component and half of the differential part. And likewise at
the other terminal, we are feeding vin2, that is also having common mode component and
half of the differential signal. And this signal pictorially it is shown here. As we have
discussed for the previous case; the signal remains the same at the input port. However,
we like to see what may be the consequence in case if the common mode gain if it is
having some significant value.
And from this information which is given here, we have the differential part of the input
signal it is having an amplitude of 100 mV and the frequency is and the common mode
984
signal its amplitude its 500 mV and the frequency it is . So, now, let us see what will
be the corresponding output. Output at probably in the form of differential and common
mode and then we can see the individual signal.
So, as you know that this differential input it is producing the corresponding differential
output. So, vo_d = this signal × 40. So, that gives us 4 ( ). And the common mode
part it is we need to multiply with ‒ 1. So, we can see that vin_c it is producing vo_c which
= ‒ 0.5 ( ).
Now if I combine this two, we can get the individual signal. Namely vo1, so let me sketch
write the vo1 part first. So, vo1; it is having the common mode part namely, ‒ 0.5 (
) + half of the differential signal, namely ( ).
So, likewise the other signal; namely vo2. So, this is equal to same common mode part ‒
0.5 ( ) and then ‒ ( ). So, we do have 2 outputs here. So, let us try to
sketch that. Now we can see that this red part which is the wanted part or desired part
along with that we do have the unwanted part. So, what we are expecting that, let me use
the same scale namely, we consider this scale it is a 2, 1 this is 0 and so and so.
And so, let me sketch the blue part first having lower frequency. So, time axis it is 0, T,
2T, 3T and 4T. So, same thing here also 0, T, 2T, 3T and 4T here. However, this scale it
was different, this was 0.5, this was 0 and so and so. Now, here the common mode part it
is having a frequency which is , so that means; this is the time period. And its
amplitude it is 0.5 and it is ‒.
So, we can say that the blue part the common mode part it is having this kind of
sinusoidal signal and then on top of that we do have the red colour part. So, if I plot the
first output, I have to consider this signal which is riding over this common mode signal
and its time period it is T and so, the signal what you will be seeing here it is something.
So, it will not reach to 2 V, it may be having slight smaller value compared to 2 V,
because it is having the common mode part it is existing. So, likewise here again this part
it will not be really going to 2 V, so it goes like this.
985
And here; however, it is exceeding 2 V because you do have the common mode part
right. And here it will be less than this ‒ 2 called rather it is having +ve part. So, it is so,
what we can imagine that this is having sinusoidal signal, but it is having slight change
or wavy kind of nature and this wavy part if we see the if you connect the peak points it
is similar to this blue line. Now if you consider the other signal so, this is the out-1. So,
vo1. So, this is the vo1.
So, now if you plot the other output; namely, vo2, it is complementary, but then common
mode part it is remaining the same. Only the differential part it is complementary right
and it goes like this. So, you can see now you can compare the first case namely case-0
and this case what you can see here, here also we are getting nice amplified signal. So, if
I say that differential signal it is getting amplified, but of course, if I take the difference
of this two, then only you can say that the signal got amplified.
If I on the other hand if I compare or if I consider only one of these two signals either vo1
or vo2, then will the signal it is really not pure sinusoidal, it is having some variation,
particularly if you see this variation. And this variation it is due to the presence of the
common mode signal. And why we do have this? Because at the input we do have
significant part of the common mode signal and also in addition to that we do have the
common mode gain Ac, it is also significant.
So, what may be the remedy or from this graph at least intuitively you can say that if we
have Ac smaller, definitely it will be better. But in case, if you consider practical
situation this may be the case and in case if you have to further suppress this unwanted
part. So, this is the unwanted part. If you want to further suppress it probably you can put
one more differential amplifier second differential amplifier.
So, based on the Ad and Ac of the second differential amplifier; this common mode part
or the unwanted part it can be further suppressed and then you will we can get the
individual signal coming out of the second differential amplifier probably hardly it will
be having this unwanted signal. We can get the sinusoidal signal which is primarily out
of the wanted signal or you can say the frequency of that signal it is , only practically
only that signal it will be available.
986
So, that is the basic characteristic what we are expecting out of the differential amplifier.
Namely, this pair of input it is getting converted into this kind of output. Now let you
consider a case where the other 2 parameters may be nonzero and then we can try to see
what will be the corresponding consequences.
So, this plot will not be repeating, but we will try to make a sketch of the corresponding
output. If I consider and see other parameters other performance parameters are nonzero
and we can keep this part = 0.
So, let we have that case-2 or you can say that third case where we do have Ad remaining
40; Ac we are taking 0 and Ad_c we are taking 0, but Ac_d we are taking 0.5. And again
the signal we are giving here they are same. And we like to know what will be the
individual signal.
So, again we can convert this signal pair in the form of differential part and common
mode part and then we can make use of the value of Ad and Ac_d to get the vo_d and vo_c
and from that we can calculate the individual signal ok. So, probably we can say that vind
= 0.1 ( ). vin_c = 0.5 ( ). And from this we can calculate what will be the
corresponding vo_d.
So, first of all vo_d; it is combination of the output coming from the differential input and
also this common mode signal, it is getting converted into differential form because this
987
parameter is nonzero. So, if I multiply this 0.1 ( ) with 40, we do get 4 (
). And then also we do have this part 0.5 into this 0.5. So, that is giving us + 0.25
( ). I should use different colour just to say that this is unwanted part and the
common mode part essentially. So, 0.25 ( ).
So, why do we have this one? That is because we do have the common mode input is non
0 and also the Ac_d this common mode signal it is getting converted into the form of
differential. And since Ac and Ad_c = 0. So, we can say that vo_c = 0. Now from this we
can tell that the individual output vo1 = half of this. So, that is 2 ( ) and then plus
the unwanted part which is I need to consider this divided by 2. So, that 0.125 ( ).
And then the other output vo2 = 2 ( ). And of course, this will be having a ‒ sign
and this part is also having a ‒ sign. 0.125 ( ). Unlike the previous case, where at
the output whenever Ac it was nonzero at the output the unwanted signal it was
appearing as common mode signal.
So, as a result to suppress it further we could have placed one differential amplifier here
and we could have eliminated that. But, unfortunately by placing one differential
amplifier here, it will not help us to remove this unwanted part. That is because the
signal this signal it is appearing at vo1 and vo2 in the form of differential. So, whatever the
differential mode gain will be having for the second differential amplifier that again it
will amplify this unwanted part. So, that is very dangerous thing. So, let me sketch this
signal in the next graph and further try to illustrate that.
988
So, as I said that I am not going to sketch the input signal that we already have done, but
let me write the vo1 and vo2. So, vo1 as you may recall that it is having 2 ( )+
0.125 ( ). Likewise, if we consider vo2. So, that is having ‒ 2 ( ). And
also this part, unwanted part as I said that it is having a ‒ 0.125 ( ). So, this is
this is very important that this is having + sign this is having ‒ sign.
So, this unwanted signal having a frequency of it is appearing as differential signal.
So, if you sketch the signal here first of all let me sketch the unwanted part which is
having a time period of 4T. So, we do have we consider time scale it is 0, T, 2T, 3T and
4T, its the voltage scale let you consider this is 2, 1 and 0, ‒1, ‒2. And its amplitude it is
as I said that 0.125. So, that is really small, but let me try to emphasize that though it is
small, but it is dangerous.
So, we do have very small amplitude here of this signal and then we do have the red
color part. Now to represent this blue signal let me also try to put the image of that blue
signal here all right and likewise here also and sorry, and then let me plot the red colour
along with the blue. So, if I combine this blue part and this red part. So, what we have
here it is vo1 it will be like this right. And, then again here it is coming up, going to this
green line and goes on like this all right. Now if I consider this part, these parts having a
‒ sign.
989
So, which means that we do have similar to blue one, but it is having opposite phase
right. So, we do have this is unwanted low frequency part or unwanted common mode
signal. Now if I put image of this violet colour at the peak concern. So, along with this
green we can see here they are in opposite phase right. And then if I sketch this part. So,
let me use different colour for that, let me use a black one ok. This is also fine ok. So,
here first of all both this part and this part is having opposite phase with respect to the
vo1.
So, we are expecting the vo2, it will be going down like this and then it will be going here
and then it will be here, it will go here and then it will go to the pink one. And sorry, this
is this got exaggerated, but what I like to say here it is yeah so, yeah there you go. So,
what we like to say that if you observe carefully that this signal, the orange signal which
is vo2 and the red one is vo1. So, they are really not differ you know, they are getting
affected by this unwanted signal, namely if you see that this part.
Now, if I take the difference of these two signals. So, you can see that the amplitude at
this point and amplitude at this point, they are different. So, same thing here also
amplitude here it is more like this and amplitude here it is different. So, if I put a
differential amplifier now what this differential amplifier it will do. It will try to amplify
the shaded part and as a result what we are expecting the differential signal nature of the
differential signal it is like this.
This part it is having higher amplitude and then next parts it is having smaller amplitude.
But then time period it is if you see here and here they are same so; obviously, this is
giving us some distorted signal and naturally, the signal what we are getting here it is it
is not purely sinusoidal. It is having distortion coming due to this unwanted signal.
Incidentally, here it is this unwanted signal it is having a frequency which is one fourth
of the desired signal and that is why it looks like some harmonic distortion. But in
general if the unwanted signal it is not really harmonics then you can see a lot of
consequences.
And if this this this Ac_d, it is higher and higher the distortion here what we can see here
it is it will be more and more prominent and most important thing is that by placing one
more differential amplifier, we really cannot eliminate. In fact, whatever the number of
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differential amplifier you like to put you cannot really separate it out from the
differential signal. Because the unwanted signal it is appearing as differential signal.
So, likewise you can probably work out on the other case namely, if I consider the other
parameter it is nonzero. Say in this case, what we have considered it is Ad_c it is nonzero
and Ac = 0 and Ac_d = 0 and then you can see what is the consequences.
So, in this case what we are expecting or let me let me at least give you a hint probably
you can work it out. First of all vin_d = 0.1 ( ). And vin_c = 0.5 ( ). Now,
this common mode sorry, this common mode signal it is really not having any role to
play because both Ac_d and Ac, they are 0, but then this differential signal one part of the
differential signal it is also appearing as common mode output.
But of course, it will also produce significant amount of differential signal. So, what will
be getting here it is vo_d = 4 ( ). And vo_c, it is 2 times of this differential signal
so; that means, this is 0.2 ( ). Now here you can see that both differential part as
well as common mode part, they are having the same frequency right. But then this is
common mode and this is differential.
So, as a result, if you see the individual outputs say vo1. So, vo1; it is half of this
differential 2 ( ) and then + 0.2 ( ). On the other hand the other output vo2
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=‒2 ( ). But then + 0.2 ( ). In fact, you can write since the signals are
same, but the frequency is the same. So, you can simply say that this is ‒ 1.8 ( ).
And the other one this one you can say this is equal to this gives us vo1 = 2.2 ( ).
So, note that here the amplitude here and here they are different of course, it is a ‒ sign.
But then both the signals are the wanted signal namely, whatever they wanted signal we
do we are looking for that signal.
So, in summary, you can say that both this signal as well as this signal they are carrying
only the wanted signal an unwanted signal it is it is completely absent. So, in fact, it is it
is a good thing that both Ac_d and Ac, if they are 0, then even if I consider individual
signal that is good enough get the desired signal. And if you take a difference of these
two of course, this will be nice. So, if you take a if you take the difference of that then
you can get the entire signal.
So, what we like to say that in this situation without using any other differential circuit,
we can as well you can extract the information from any one of them or you may say that
if I put a single ended circuit from that you can get the desired signal. So, in summary,
this circuit it is very nice, just by putting this one differential amplifier having this
important property namely, Ac as well as Ac_d are 0 that completely suppress the
unwanted part.
So, it completely removes in this part. Now in practical cases; however, all of these
parameters may be present.
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So, you can consider yeah you can consider a situation where both I should not say both,
all of them are say non-zero, depending on their corresponding value, they are influences
it will be there and then you can find the individual output and as I said that the this is
very dangerous thing. So, that really creates the problem.
So, practically even though they are non-zero, but in this course of discussion, in this
subject we will assume that these 2 parts; this part and this part they are absent. We
consider Ad_c = 0 and Ac_d is also 0. And, we will try to characterize the circuit by
considering the differential gain and common mode to common mode gain ok. I think,
let me take a break here probably will come back we do have some more things to
discuss. So, for the time being let me take a break.
Thank you.
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Prof. Pradip Mandal
Lecture – 74
Single - Ended Vs. Differential Signaling and Basic Model of a Differential
Amplifier (Contd.)
Yeah. So, dear students welcome back after the break.
So, what we are talking about the basic characteristic of differential amplifier. And what
we said is that its main purpose is to suppress the common mode signal, which is
unwanted quote and unquote unwanted. And then along with that to appreciate the
differential part the differential signal namely if you consider the two input signal.
This is the shaded portion is the differential signal and the blue line here it is the
common mode unwanted signal. And this is what we do expect at the output vo1 and then
vo2. So, vo2 and what we do get is primarily vo1 and vo2; it was almost I should say
amplified version of the individual signal namely the differential part of the individual
signal. And what we said is that the common modes part it got suppressed.
So, the blue part it got suppressed and the differential part it got amplified. So, the and of
course, it depends on the relative value of the differential mode gain and the common
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mode gain and the other parameter. Now next thing is that what we will be looking for is
what may be the basic purpose of using this differential amplifier or what is its need,
what is its application in actual scenario?
So, in the next slide, we will be talking about the basic need of the differential amplifier.
So, suppose we do have single ended amplifier. So, we do have this is one single ended
amplifier. And it is producing a signal vout and since it is single ended this vout it is with
respect to its common node. And let you call this is the transmitting circuit and then we
do have a receiving circuit.
So, we are expecting that this output it is getting connected to the receiver input and
assuming that this connection it is long. So, ideally we whenever we are producing signal
from the transmitting end it produces a voltage with respect to its common node.
Likewise whenever the receiver it is receiving the signal at its input, it is comparing this
voltage with respect to its own ground. And ideally we want these two grounds are same
and if these two grounds are same then this vout of the transmitter say vo_Tx is directly
coming here.
And then we can say that the vin_R is exactly equal to vo_Tx transmitter. So, then the signal
received by the receiver is not having any issue and then of course, based on its own
characteristic it is providing its corresponding output vo_R. Now the problem starts
whenever the spacing between these two blocks; it is quite large. And if there is a chance
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that this ground of the transmitter circuit and ground of the receiver circuit, if they are
not equal maybe average wise they are equal.
But instantaneously if there is any variation, then the received signal by the second unit.
And the transmitted signal from the first unit they will be they will be different. Say for
example, if we have some voltage here. And if we consider the voltage difference
between these two it is a vx; assuming this is + and this is ‒. So, now, if I consider this
line, it is directly carrying the signal and if I consider KVL through this loop.
So, from this you can say that either this way or this way. So, we can say that vin_R = vin.
So, our vo_Tx ‒ this vx. So, this vx entity in case if it is unknown, then we can see that at
the receiving end whatever the signal we are receiving even though the signal it is
coming from here to here without any problem. But then because of this ground and this
ground may be instantaneously they are different.
And if it is having a difference of vx then the difference of the two ground it is appearing
as input signal which means that the receiver it is not only receiving the transmitted
signal, but also it is receiving, the voltage difference it may be referred as ground noise
or ground difference; many a times depending on this length depending on this spacing.
The difference of these two ground voltage may be quite different. And many there may
be even practical cases where this ground difference; it may be comparable with the
transmitted signal if not higher than this. So in fact, there may be a situation, where the
ground difference may be even higher than the signal quantity naturally the received
signal it is we should say it is not only noisy probably.
It the receiver may be having difficulty to properly identify whatever the signal it has
been transmitted from the transmitting end. So, that creates the major problem of course,
in case if we have say same amount of voltage difference in this line also. Then of
course, this this voltage difference and voltage difference may get canceled, but in
general we cannot say that the ground difference and the signal difference they will be
same.
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Then how to solve this problem, instead of sending the single signal instead of sending
say this kind of single signal, what we can do? We can send the signal which is referred
as true signal and its complementary signal.
So, the voltage difference between this two now it may be considered as the main signal.
So, whenever this transmitter it is produced a signal, it is the signal it is essentially the
difference of this two terminal voltage. Or I should say that vo1 ‒ vo2 is the main signal.
And at the other end whenever the receiver it is trying to pick up the signal and trying to
detect the signal, it considers that voltage difference at this terminal with respect to the
complimentary line is treated as a received signal. Now in case if this ground and this
ground it is having a difference then you may say that vo1 and vo2 may be having
different voltages with respect to this ground. In other words this line and this line, may
be having not only this signal volt differential signal, but whatever the common
difference we do have called vx that may be appearing at this terminal; terminal-1 as well
as terminal-2. And since both the terminals are experiencing the same vx in same phase,
we can say that the receiver it will be seeing this vx as common mode signal.
So, the signal received at this point, if I call say vinR_1. So, that = vo1 ‒ vx; vx is the
voltage here that is the ground difference. So, likewise if you consider the voltage here
this is vinR_2. So, that is equal to vo2 ‒ vx. Now whenever this receiver it is trying to detect
the signal, it takes the difference of vinR_1 and vinR_2.
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And the differential voltage here which is referred as a vinR_d, which is the difference of
vinR_1 ‒ vinR_2; that is vo1 ‒ vo2. So, if this receiver it is essentially amplifying or sensing
the differential input, then this receiver it will not be getting disturbed by this common
voltage difference between the two grounds. So, of course, this is possible only when the
receiver it is having capability to completely suppress this common part. Namely ‒ vx
part, then only we can say that the output of the receiver it is completely independent of
this vx.
And that can be achieved by considering common mode gain Ac = 0 and also common
mode to differential gain is also equal to 0. And then this differential part probably, we
can amplify by considering a good differential gain Ad. So, we can say that this Ad if it is
much higher than 1, then we can say that the received signal is getting amplified. Or
even if it is a comparable with 1, at least we can say that unwanted signal it is
suppressed; and then differential signal which is the transmitted signal coming from the
other end it is properly getting received.
So, this is what the basic motivation of going for differential amplifier. And the kind of
signal coupling in this case it is referred as differential signaling versus whatever the
signal coupling we have done here it is referred as single ended signaling. So, many of
the high-speed application, where this transmitted signal due to various reasons, this
transmitted signal it is typically it is very small its voltage showing it is very small. And
in that case the ground difference may be quite significant it may be even higher than the
signal here.
And for such situation this mechanism called differential signaling it is very essential for
proper communication of the signal from one end to the other end. And in nowadays for
many of our devices attached with computer we might have seen that the cables are
differential in nature. So, the transmitter one end device of this cable is transmitter which
sends the signal in differential form and the other end we do have the receiver that
receives the signal in differential form. And the whenever we say differential signal it is
essentially it is having two signal lines; one is true signal another one is the
complementary signal.
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So, that gives you the motivation of going for differential amplifier. Apart from this of
course, common very common application of differential amplifier and age-old
application of differential amplifier I should say is op amp operational amplifier.
So, let us see why we require differential amplifier for this op-amp implementation.
Suppose here we do have say op amp having a gain of say A or in fact, strictly speaking
it is a differential gain Ad. And it is defined by its output vo divided by this differential
input vin_d.
So, for vin_d this is plus and this is minus. So, I should say that gain of the op-amp Ad it is
defined by . You might have observed that its input port it is differential, but then
output port it is single ended. We will come back to this kind of configuration, but at
least let me try to appreciate that its input port it is differential in nature and why we look
for such kind of things.
Now, if the op-amp gain A it is very high. So, if I say that this is very high quote and
unquote very high, and then what you can say for finite value of vout the vin_d it is very
small. And we can see that this vin_d approaches to 0 for finite vout right. And of course,
this is this is possible if the feedback in this circuit it is having a negative feedback, then
only it is possible. So, later we will be talking about the importance of having negative
feedback and the polarity of inverting and non-inverting terminal. But for the time being
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let me consider that since this differential mode gain it is very high that makes this vin_d
approaching to 0; making the two inputs; one is here, another is here two input terminal
of the different the op-amp.
It is virtually equal or I should say they are close to each other very close to each other
and you may say that they are virtually following each other. So, if the voltage here it is
vin controlled by this vin then if we consider this is vin and also if I consider input current
is 0 ; from that we can say that vout = ( ) vin.
I suppose you may know this relationship and here the basic assumption is that the gain
is very high and the differential input here it is approaching to 0 ok that is fine. And
based on this equation we can consider this circuit is an amplifier. So, whatever the
voltage you are applying here, amplified version of the voltage it is coming to the output
and so and so on. But you might have observed that this circuit this op amp, it is
receiving a signal here of course, and it is having differential input though it is expected
to be very small.
But that is the signal after multiplying with Ad it is producing vout right ; because the
definition of Ad is given here and from that we can say that vout = Advin_d right and so, I
should say that it is amplifying differential input and then it is producing the
corresponding output.
In addition, if you observe say voltage at this terminal which is referred as non-inverting
input so, this terminal with respect to ground of course, it is having a voltage vin. So,
likewise if you observe this voltage this voltage is also very close to this vin. So, if you
consider the voltage at this point called say V1 and then this is V2 and then also we do
have vin. So, if we are applying say vin with respect to time of course, vin and V1 they are
same. So, I can say V1 it is also same as vin; then the V2, it is very close to that.
So, V2 it is very close to that, but of course, there may be a small difference, but that
small difference is good enough; because once we multiply that signal with an Ad
differential gain. So, this differential part little difference that difference is essentially the
vin_d. So, after that is getting multiplied by Ad it produces the corresponding output right
and this is this is the final output this is vout. So, we can say that vin, we are applying here
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and then we are getting the red color one. And also because of the negative feedback the
black one this black one is essentially this voltage.
So, if I see this circuit independently. So, we can say that op-amp, it is receiving two
signals; one at its non-inverting input another one it is at the inverting input and these
two signals they are very close to each other. So, we do have V2 here and then we do
have V1 here and these two voltages they are very close to each other. And then this
output of course, we are expecting this output primarily it is amplified version on this
differential. And with progress of time of course, if you see this voltage and this voltage
they do have a big common signal. If you see here, if I take average of these two signals,
it is having a big common mode signal.
So, with respect to ground both V1 and V2 they do have very big common mode signal
which is almost equal to whatever vin we are applying. So, this amplifier it is facing its
vin_c, it is very close to whatever the input voltage you are applying. And this input
voltage this common mode input voltage we are expecting that it should not really affect
the output; rather this output should be coming only from the difference of the two signal
right.
So, this circuit we also look for you know one apart from the differential mode gain it
should be high we also look for another parameter called common mode gain. It should
be as small as possible; otherwise this red colored signal it will not be solely dependent
on vin_d it may also be getting affected by vin_c.
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So, to summarize within the within the op-amp within the op-amp at least it is having a
circuit that is the first part the port if you see it is differential. In fact, if you see inside of
this, it may be having multiple stages and the first stage it is differential amplifier.
Second stage may be having similar to differential amplifier, but it is I should say special
or some variants of differential amplifier and so and so. So, this is also another very
common application of differential amplifier where it receives the signal in the form of
differential signal it produces a differential output. So, we should say that we need to
have good understanding of this differential amplifier and its corresponding
implementation.
Now, there may be different variants of differential amplifier. So, in the next slide let we
see different variants of different amplifier. So, we already have discussed about the fully
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So, here this is the circuit or block diagram of that, here we do have the corresponding
linearized model. And here we do have different representation or different way of
representing its input signal; namely in terms of the common mode part and the
differential part.
Likewise we also are quite familiar with single ended to single ended amplifier. So, here
we do have the main circuit and here we do have the corresponding linearized model.
The input it is input signal it is with respect to common node ground and output also it is
with respect to ground. Now apart from this two we do have one more variants of
amplifier you might have seen for this circuit both the input port and output port they are
differential.
So, that is why this circuit actually it is referred as fully differential whereas, for this case
both input and output their single ended. So, it is it is referred as single ended amplifier.
The third possibility is that the input can be differential and the output can be single
ended which is referred as differential to single ended. So, in fact, whenever we talk
about say op amp op amp it is also one kind of differential to single ended amplifier right
What is the other possibility? The other possibility is that there may be the input port
may be single ended and then output port it can be differential in nature. So, this is
referred as single ended to differential amplifier; where this is the true signal and this is
the complimentary signal input it is with respect to ground. This output it may be with
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respect to ground common ground, but we do have a pair of signal where difference of
these two voltages is carrying the main information.
So, this is a special kind of circuit in this course we will not be discussing about single
ended to differential amplifier, but definitely we will be frequently talking about
differential to single ended amplifier. So, it is better to better to see the difference of the
difference of this this differential to single ended amplifier with respect to fully
So, in the next slide we are going to give a little hint how this differential to single ended
amplifier it is really different. So, if I consider fully differential amplifier, here as I said
that there are four basic performance matrices; namely differential mode gain common
mode gain and then common mode to differential gain and then differential to common
mode gain.
So, these are the four basic performance parameters for fully differential amplifier. Now
if you see on the other hand whenever you are talking about differential to single ended
amplifier; since the output port since this is single ended. So, the signal here it is with
respect to ground. So, then the signal it is a signal there is no you know separation of this
the common mode and differential part of the signal. So, naturally whenever we will be
talking about gain of this circuit it may be differential input to output gain.
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And then the other one is that the common mode input to output gain. So, it is having
essentially two parameters Ad and Ac and for this case Ad and Ac, they are defined as Ad
it is and the corresponding the other one is common mode gain which is . So,
you might have observed that at the input since it is differential signaling differential
port, we do have differential part and the common mode part we can treat them
separately.
But at the output it is single ended signal. So, we do have only one signal. So, whenever
we are defining this Ad we are assuming that the vin_c = 0. So, likewise whenever we are
talking about Ac we are assuming that the corresponding differential part at the input a
vin_d = 0. So, of course, the other basic characteristic namely for proper operation of this
circuit, we want this differential mode gain it should be as high as possible. And for good
differential amplifier differential to single ended amplifier we want this should be as
small as possible.
So, ideally we want Ac should be 0 and this should be as high as possible ok. So, these
are the three variants of amplifiers. And as I said that while our discussion it is with
voltage amplifier similar kind of you know variants are also possible, if we consider the
signal in the form of current. In fact, the signal can be mixed namely at the inputs say
signal may be voltage at the output the signal can be current and so and so.
But whatever the circuit we considered, everywhere we do have the possibilities of this
kind of different variants of the amplifier. So, whether it is current mode or voltage mode
or mixed mode and of course, apart from this three the other variant; namely single
ended to differential amplifier we are not going to discuss in this course right. So, now,
when and where to use this different kind of circuit? So, let us try to see where we
considered which circuit and keeping in mind that the basic purpose of differential
amplifier is to suppress the unwanted part namely the common mode part.
1005
So, if you see this chain, we do have we do have say fully differential amplifier. So, this
is fully differential amplifier, followed by differential to single ended amplifier. So, its
input port it is differential, but then its output port it is single ended and then followed by
single ended to single ended amplifier. In fact, if you see this circuit as you can guess
that since the input it is single ended, among these three this is the simplest one in in
realization. And this is most complex one this is in between.
So, if we have some task, which can be performed by the simplest version then
unnecessarily will not be going for a differential circuit. On the other hand if it is really
not possible to perform some task by single ended to single ended amplifier, then we do
invite either fully differential or differential to single ended.
So, unless otherwise it is needed we will not be going for fully differential. So, the
natural question is that when do we look for this differential amplifier? In case if we
have say one system, if we have a system and we do have say different blocks of some
system; from outside we are receiving a signal from another probably another system.
Then; obviously, this connection in this connection there is a scope of getting the signal
interfered by some other environments. Or we may say that the signal may get affected
by some other interferer called noise.
So, for such cases whenever the signal it is coming with some interference and if this
noise is really alarming. So, then we prefer to use differential signaling here having a
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true signal. Having a true signal path and along with that we do have a complimentary
signal. Now how it helps in case we do have this some noise unwanted noise is coming
there. And this noise it may be interfering the true signal path as well as the
complimentary signal path in same way which means that whatever the noise this noise it
is coming in the true signal as and complimentary signal in the same way.
So, the received signal if you see here, the noise can be received as like a common mode
signal. And the difference of these two signal these two line voltages that can be treated
as the main signal which is differential. So, whenever we do have some block here which
is first interfacing with the external world we like to keep particularly whenever we are
receiving sensitive signal. And in case if it is getting affected by noise then we like to
keep the first block at least its port is differential in nature.
And if this block it is getting realized by say fully differential, probably that may give
signal where this noise part it may get significantly suppressed. Of course, it depends on
what is the differential mode gain and the common mode gain of this this circuit. But
whenever we are seeing the output probably the quality of the signal here, it will be
much better compared to the signal here because here the noise is getting suppressed.
And if we are happy with the quality probably you can subsequent block we can put as
single ended.
So, probably then we can convert this differential into single ended and then the
subsequent block it can be single ended. So, as you can anticipate that whenever we are
receiving signal from outside, we do consider it is fully differential signaling. And then
once it is going inside the system we do convert into single ended and subsequently we
can keep the signal in single ended form. So, this is the boundary of the system and this
is the inside of the system.
So, as you are going inside the system for simplicity, we keep the single ended blocks
more and more there and only at the interface we keep the port as differential. So, that
gives you some idea that where and when we should use what kind of amplifier what
kind of configuration.
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In fact, if you see the op amp there also in op amp also if you see its input port where we
do have the inverting terminal and non-inverting terminal.
So, we are expecting that whatever the signal it will be received by this block, it will be
having significant amount of common mode. In fact, that the common mode signal; it
can be even higher than the differential signal. So, naturally the first block if you see this
first block it is differential to differential and then one say the common mode part it is
getting suppressed. Then probably the next block it converts the differential signal into
single ended signal and then subsequent blocks are a single ended.
So, we can say that this chain this kind of chain it is quite common in this kind of circuit
called op amp operational amplifier.
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I think that is all we like to cover and so, let me conclude whatever whatever the topics
we have covered today in. So, first of all we started with numerical examples, numerical
examples on basic model of differential amplifier. And then there what we have
discussed is that significance or importance of different performance parameter; namely
differential mode gain, common mode gain, then common mode to differential gain and
then differential to common mode gain. And what we have said is that this is this is
definitely we want it should be as high as possible.
But most vital thing is that this parameter should be as low as possible. And so, this is
the having this is having the highest priority and then in addition to that to improve the
signal quality we have also want it should be low. And probably we want this should also
be low, but definitely these two parts, which are essential parameter indicating that how
much the elimination of unwanted signals are performed by differential amplifier. So,
that needs to be taken care. So, we want these two parameters should be as low as
possible.
So, whenever we will be implementing a differential amplifier we have to pay good at

good attention to achieve this. And then, we also have then discussed about the
motivation of using differential amplifier we are all we do use. Particularly whenever we
like to send very sensitive signal from one device to another device they are far apart.
And in case if their grounds are not really maintained equal. And or in case if some
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possibilities of having noise corrupting the signal; then we do go for differential
signaling namely sending both true signal and complementary signal. And that says that
we require a differential circuit here and differential circuit here.
So, while we have discussed we with the basic discussion we started with fully
differential amplifier, we also have introduced something called differential to single
ended amplifier. So, that as you are progressing towards the system that signal seen, it is
getting converted from differential to single ended and subsequently it remains single
ended. So, this single ended is important because that simplifies the circuit, but then we
require this basic chain to convert the differential signal into single ended form.
So, we do have fully differential amplifier, we do have then differential to single ended
amplifier and then we do have the subsequent stages are single ended to single ended
amplifier. We also have just touched upon that when to use what variants of amplifiers;
namely if I consider this three variants of amplifiers. We have discussed about when to
use which block. I think now we are well set to go for implementation of differential
amplifier. So, in our next class, we will be talking about implementation of differential
amplifier. So, that is all to share in this lecture.
1010
Prof. Pradip Mandal
Lecture – 75
Differential Amplifier: Basic Structure and Principle of Operation
Dear students, welcome back to our NPTEL online certification course on Analog
Electronic Circuit; myself Pradip Mandal from E and EC department of IIT, Kharagpur.
Today’s topic of discussion is Differential Amplifier and we will be talking primarily the
Basic Structure and Operating Principle.
So, in our overall flow where we stand, we are in module-7 and we are talking about
different circuit modules and this module particularly in our discussion today it is
differential amplifier. We have given basic motivation of going for differential amplifier
and today we will be talking about the basic structure, how the construction of the
differential amplifier it is there and it is operating principle.
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So, the concepts covered in this talk, in this lecture are the following. So, we are going to
start with basic operation and then we will be going to discuss detail of characterization
of differential amplifier. Namely, how we find the basic parameter values particularly,
differential mode gain and common mode gain and so and so, from a given circuit.
And then we will be talking about realization of differential amplifier at transistor level.
So, transistor maybe BJT or MOSFET. So, we will start with very basic structure and
then we may discuss about different variants of differential amplifier, particularly the
code differential amplifier. And then we will talk about operating principle of a realized
structure.
So, we may consider two structures namely, one is using BJT and other one it is using
MOSFET. So, let us discuss about the basic operation and characterization of differential
amplifier.
1012
So, to recapitulate whatever we have discussed in our previous lecture we do have say
this is a main differential amplifier. Where we have the power supply DC supply and
ground and then at the input we do have the differential input port having two terminals
1 and 2 and at this input we are given signal or I should say voltage signal and it is
having a DC part meaningful DC part and on top of that we do have two signals. One is
vin1 and vin2.
So, these are the two signals, but we must be careful that while you are feeding the signal
the voltage DC voltage at this point and DC voltage at this point should be appropriate.
So, that this differential amplifier should be working properly. Since in this connection
supply connection we do have only one supply namely, Vcc and the common terminal is
ground here invariably we need a +ve DC voltage at both terminal-1 and terminal-2.
So, unless other unless otherwise it is stated we assume that the DC voltage at terminal-1
and terminal-2, they are equal and we refer this DC voltage at input common mode DC
voltage VINC. Now if we concentrate on linearized circuit. So, here we do have the
linearized circuit, once we are sure that all the transistors are in proper region of
operation, then we may focus on linearized circuit or something called small signal
equivalent circuit. And they are what they do the DC parts we will be considering it is 0.
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So, we do have this terminal supply terminal it is ground and whatever the input signal
we are given it is with respect to AC ground. And then this is the differential signal
coming to the circuit and then the corresponding output we are observing at either
terminal output terminal-1 and output terminal-2 or maybe we can compare this to
voltage and then we call this is the differential output.
So, if you see the voltage at this point it may be having say with respect to time it may be
having a DC voltage, it may be having a DC voltage and this DC voltage it is VINC and
then on top of that we do have say this signal this signal vin1.
So, let you consider this is one signal on the other hand if I consider the second terminal
there we do have same DC voltage on top of that we do have the complimentary signal,
so this signal is this one. Now so, these are the two inputs, vin2 and then vin1. And the
corresponding output what we are expecting at terminal-1 of the output port and
terminal-2 of the output port namely, Vo1 and Vo2 respectively.
So, we are expecting that here we do have say Vo1, it may be having it is DC voltage
level and on top of that it may be having the corresponding signal. So, we are expecting
that it will be amplified version of whatever the signal we are applying and at the other
output probably, it will be having the same DC level and then on top of that it will be
having complimentary signal.
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Now, whenever we are talking about the DC level at the output and the DC level at the
input, they may be having some relationship, but that relationship cannot be expressed by
the two parameter what we have discussed is Ad and Ac. Ad and Ac they are essentially
representing small signal relationship.
This DC voltage relationship can be obtained by considering non-linear characteristic of

the entire circuit. So, whenever we will be talking about actual realization we may
discuss about the relationship of this DC voltage level and to whatever the DC voltage
level at the output.
This DC voltage level we may call it is VO_C, output common mode DC voltage level.
And then whenever we are at say small signal equivalent circuit we are primarily
focusing on the signal and we need to adjust this DC level to ground level ok. So, same
thing here also.
So, in this circuit, whenever we will be talking about it is corresponding input and output
what we will be talking is the input it is with respect to ground. So, this is one input and
the corresponding complimentary input is like this.
So, this is 0 levels, this is vin2 and the blue one it is vin1. So, likewise when you when you
see the output signal. So, there also we will be discussing only the signal part not the DC
part. And so, whenever we are focusing on signal, we are assuming that this DC level is
aligned with 0 and we are focusing on the signal part right.
And now it is it is very important that though the focus is here, but it is also very
important to properly adjust this input DC voltage level and also it is important to get
this meaningful DC voltage level. So, that the signal swing undistorted signal swing it is
very good and this DC level should be such that the entire circuit is properly operating.
So, as I said that whenever we will be talking about actual circuit we will be talking
about this level and this DC level and their implication, but for the time being we are in
this small signal equivalent circuit.
1015
Now once we are in small signal equivalent circuit, then it is basic parameters are
differential mode gain and common mode gain as you can see here and we say that
ideally we want this differential mode gain it should be as high as possible and this
common mode gain on the other hand it should be as small as possible.
Apart from that, you also have two more parameters namely, common mode to
differential gain and differential to common mode gain. But unless other unless
otherwise it is stated we assume that both of them are equal to 0. So, henceforward we
will be assuming that this two are 0. Later we will be talking about how to achieve this
property in the actual realization.
Now, to see the output in terms of whatever the input we are applying here and in case if
we have say these two parameters namely the common mode gain and differential mode
gain. We need to translate this if this pair of signals in the form of common mode
component and differential component.
So, this circuit it is equivalent only thing is that it is it is a representation of the input
stimulus it is different. In fact, in actual circuit when you see, we may consider the
similar kind of arrangement namely a common mode signal going to both the circuits
and then we do have say two half’s of the differential signal as you can see here.
1016
So, we do have +ve half it is going to say terminal-1 and ‒ve half it is going to terminal-
2. And then, the common mode signal it is going to both terminal-1 as well as terminal-2.
And then we do see the signal here. So, that is what we have discussed in our previous
lecture, now next thing is that further to that.
Suppose, we do have a circuit whether in this form or in the model form then, how do we
find the value of this differential mode gain and common mode gain? For say analysis of
a circuit or maybe in actual hardware, how do we how do you find this parameter? So,
which is referred as characterization of the existing circuit to find the value of
differential mode gain and common mode gain; so, in the next slide we are going to
discuss about that.
So, the basic operation and most important thing is that characterization of a differential
amplifier.
So, this is what we have discussed and this is what the corresponding small signal
equivalent circuit and it is stimulus which is having combination of the common mode
part and the differential parts. Now to find Ad differential mode gain of this circuit, what
we do we take this circuit and then we consider that this part = 0.
So, then the corresponding stimulus what you can see here it is common mode signal it is
0, we do have only the differential signal coming to the circuit. So, this kind of stimulus
1017
it is referred as differential mode of stimulus which means that the common mode
component it is completely 0 and the signal coming here and here, they are perfectly
complimentary to each other.
So, you may say that one of them it is it true signal and this is complimentary signal and
there is no common mode component and in case if we have say Ac_d = 0 and since in
this case vin_c = 0, which implies that vo_d = Advin_d and vo_c, even though it is Ac may be
nonzero, but since vin_c in this stimulus in this stimulus it is 0, so that is why this = 0.
As a result if we see the individual output see vo1 is ‧vin_d on the other hand vo2 = ‒
‧vin_d. So, what we can see here it is that these two outputs they are perfectly
complimentary to each other.
So, we may say that this is true output and this is the corresponding complimentary
output. Now in this arrangement if you simply observe this signal namely this signal and
then if we know what is the vin_d. So, from that you can calculate what is the Ad. Namely,
Ad it is given by vo1 divided by maybe one of these two signals.
So, that is equal to so, so, that 2 it is coming here and that is how we can get the
value or expression of the differential mode gain ok. So, likewise in case if you want to
know what will be the common mode gain Ac, then you can consider say this circuit.
And in this circuit what you do we are making this two differential halfs equal to 0
namely, differential part = 0. So, we can see that this differential part is equal to 0 and
both terminal-1 and terminal-2 are getting common mode signal.
1018
So, in this the second circuit, in the second circuit to find the common mode gain we are
making these differential particles to 0. So, naturally, the vo_c = Acvin_c whatever the vin_c
we are applying and vo_d on the other hand Advin_d. Now vin_d = 0, so, that gives us vo_d =
0. And hence the corresponding output vo1 it is just vo_c and vo2, it is also vo_c.
So, that is why we are writing that both this output and this output they are same because
this signal it is 0. So, here again by considering say this equation say this equation and if
you consider this = Acvin_c. So, just by observing one of them maybe say this signal and
then if you take the ratio of this signal with respect to vin_c, then you can find
corresponding Ac.
Namely, the Ac equals to by observing one of them either . So, that is how we
characterize a given circuit to find these two important parameter, differential mode gain
and common mode gain right. Now of course, again we like to say that while we will do
this operation in actual circuit we have to retain this DC voltage and then, we can see
what kind of signal we can apply here to get this differential mode of stimulus and then
common mode of stimulus. So, now let us see the realization of this circuit.
1019
So, how do we realize this differential amplifier. There may be different possible
realization of differential amplifier, but here we do have a very basic realization of
differential amplifier I should say it is basic, but still it is it is I should say practical
circuit.
Many of times it is also used in actual circuit and whatever the concepts we will be
discussing related to differential amplifier for that this circuits are good enough to
discuss that. So, here we are showing that the realization of this differential amplifier.
So, like so, this is BJT version and here it is MOSFET version.
Now, here I like to tell you one important point here if we consider say this is one
terminal input terminal, this is the other input terminal in-1 and in-2 and then if I
consider the corresponding output, output at this point; it is in phase with this input and
hence instead of calling this is vo1, we are calling this is vo1 ok.
Just to say that if this is +ve side of the signal and this is ‒ve side of the signal, the
corresponding output will be having this side is this terminal showing the +ve side of the
output and on the other hand this terminal will be showing the ‒ve side of the output. Or
we may say that if I am applying say vin_d having say +ve side here and ‒ve side here.
So, ‒ve side we are giving to terminal-1 and +ve side at terminal sorry, ‒ve side at
terminal-2 and +ve side it is going to terminal-1.
1020
Then whatever the voltage we are observing here at the output. So, for this output, this is
+ and this is ‒ and we call this is the differential output. Now, in and this is true for the
other realization also, we call this is vo1 and this is vo2. So, that the polarity of this
terminal and this terminal they are same ok.
Now coming to the other information which is also very important, that you might have
seen that we do have this circuit is having two parts structurally they are identical. In
fact, this Rc1 and Rc2 we want they should be equal, Rc1 we want Rc2 should also be
identical.
So, likewise Q1 and Q2 are identical right. So, once we have these two halfs they are
identical not only in schematic, but their actual value then only we can see that whatever
the parameters other parameters we have ignored namely, Ac_d = 0 and Ad_c = 0.
Which means that whenever we are applying say differential signal at the input the
corresponding output it is perfectly differential and whenever we are applying say input
signal in the form of common mode, perfectly common mode which means differential
component is 0 then you can say that at the output whatever the signal we are getting
signal at terminal-1 and terminal-2 they are identical and hence differential output is 0.
So, these two matching as I said that these two matching’s are very important to achieve
this other parameter to remain silent they need to be equal to 0. So, same thing here also,
1021
we want RD1 and RD2 they should be equal and these two should be identical, M1 and M2
should be identical.
Now, the natural question is that in practical realization if they are they are not possible
to achieve whatever the little variation is there. So, same thing it may happen for Q1 and
Q2, then their consequences it will be if they are not and if are not identical then these
two parameter we cannot consider they are 0 and we have seen their consequences.
Particularly Ac_d it is very dangerous. So, we prefer to avoid such kind of situation ok.
Now next thing is that here of course, there are different possible realizations and as I
said that these two realizations are very basic and very fundamental.
Now, what are the different variants we do have? First of all we have seen that for
common emitter amplifier instead of having passive resistored we can have active
device. So, we can probably replace this passive element by 2 identical PNP transistor.
So, here and here. So, as I said that they should be identical. So, and by doing that we
can get higher differential gain.
So, by doing this we can increase the differential mode gain ok. In fact, same thing it is
also applicable if we replace this RD1 and RD2 by their corresponding counterpart in
transistor realization namely p-MOSFET. So, same thing here also identical PMOS
transistor with of course, meaningful bias here.
1022
So, if we replace this resistor and this resistor by their corresponding active devices. So,
here also the differential mode gain it increases. So, so that is how we can get different
variants. On the other hand if we consider this resistor it is role is to play to decrease the
common mode gain this RT it decreases not only it is working as bias circuit, but it helps
to decrease the common mode gain.
We will see how it is getting achieved, but higher the value of this RT, we can get smaller
the value the corresponding common mode gain. So, naturally if we replace this resistor
by one active device say one NPN transistor. So, if you replace this one so, that will help
us to decrease this. So, that that helps to decrease the common mode gain. So, by
replacing this resistor by active device, it helps to decrease this one. So, same thing here
also, if you want to decrease the common mode gain then you can replace this resistor by
corresponding NMOS transistor.
So, we may say that if we have a circuit like this, if we have a circuit where the load part
it is active it may be having meaningful bias here and here and then of course, the main
differential pair this Q1 and Q2 normally it is referred as in differential pair. So, same
thing M1 and M2 it is also referred as differential pair. So, if you if you have this kind of
circuit of course, again with a meaningful bias here and then if you consider this is the
output and this is the other output terminal.
So, this is Vo1 and this is Vo2 and so and so. And again we consider Q1, Q2 their identical
likewise Q3 and Q4 should be identical. So, that Ac_d and Ad_c should be maintained 0 and
then you do have the Q5 here. So, by doing this we can we can get one enhanced version
of whatever the basic differential amplifier we have discussed where of course, the
differential mode gain it is much higher and then common mode again it is much lower.
So, same thing you can get the active version for both load as well as the and the lower
till resistor. So, we do have the differential pair here and then we do have the tail
transistor by the way this Rt it is referred as tail element it is referred as tail transistor.
So, we do have M1 and M2 identical and then M3 and M4, they are identical of course,
here we should be having meaningful bias here. So, same thing here also these are
PMOS transistors and then you can get one output here another output here and this is in1
and this is in2. And again this circuit will be having better Ad and lower Ac. So, that is
1023
how you can you can derive different variants. In fact, I also must say that there are other
possible way of getting other variants of differential amplifier.
Particularly, if you consider this basic structure; here we have used Q1 and Q2 to really
amplify the signal and these transistors are NPN and here we do have NMOS device.
So, you can develop one complimentary circuit where PNP transistor can be used to
amplify the circuit. In other words, the differential pair it can be PNP so, we do have say
now we call this is Q1 and Q2 and as I said that this would be identical then, we can have
say passive resistors called Rc1 and Rc2 and they may be connected to ground and then
the tail resistor RT now it is connected to the supply Vcc.
So, we may call this is input-1 and this is input terminal-2 and we may call this is Vo1
and this is a Vo2. So, here again the operation of the circuit using PNP differential pair it
is very similar to on this circuit only thing is that while we will be applying the bias we
need to be careful that we need to have meaningful DC voltage here and here so that,
devices are in active region of operation.
But, then once you go in small signal equivalent circuit this terminal it is AC ground, this
terminal it is AC ground, this is actual ground and then the equivalent circuit of this part
and this part I should say it is essentially same. In fact, same thing you can do for the
1024
MOS version also we can put a tail resistor and then we do have the differential pair
using PMOS transistor and then we do have two passive loads.
We do have RD1 and RD2 and then we do have M1 and M2 right and this is we do have the
supply. This is one output and this is the other output, this is input-1 and this is input-2.
And of course, again if you want to enhance this circuit performance you can replace
these resistors by active device to enhance the differential mode gain and likewise you
can replace this tail resistor by PNP transistor to decrease the common mode gain.
So, this transistor helping to decrease the common mode gain whereas, these two
transistors they are helping to increase the differential mode gained. Now I think it is
very logical you can, so, similar thing you can do for the MOS version also. So, at least
we understand that it is not just only these two are the realizations of differential
amplifier, there are many possible variants, but then their basic structure can be
understand by considering this simple structure.
And in our subsequent discussion, we will be talking about these two circuits only ok.
So, let me take a short break and then we will come back.
1025
Prof. Pradip Mandal
Lecture – 76
Differential Amplifier: Basic Structure and Principle of Operation (Contd.)
Yeah, welcome back after the short break.
So, what we are talking about different realizations and different variants of Differential
Amplifier and primarily in our next discussion, we will be talking about this circuit and
this circuit as representing basic structure. Now, if you want to see the basic working
principle of this circuit particularly, this circuit or this circuit, we need to convert this
circuit into one of its equivalent.
1026
So, let us see in the next slide, what equivalent circuit we are talking about. So, here this
is the basic differential amplifier using BJT and here we do have tail resistor called RT.
So, this kind of circuit so far we have not analyzed, but at least to we have analyze
something similar particularly, if I consider only half of this circuit something like this
and if we feed a signal at the base and if you observe the corresponding output at the
collector, we know that this is CE kind of circuit.
So, we also have seen resistor the emitter node need not be connected to ground, even if
it is connected through a resistor still we call this is CE amplifier considering this is input
and this is the output right. So, since we know the analysis of this circuit, I think it is
better we you know go inside this circuit rather convert this circuit in this kind of form
and then try to analyze the circuit.
In fact, in case if we are observing the output at this node and if it is remaining as input
even though, we do have say resistor connected here and if I call it this is our new output
then we call this is a common collector circuit.
So, even in this case also it is better, we convert the differential amplifier in terms of this
kind of structure. Now in this original structure this RT it is connected to Q1 and Q2
together, but we also know that Q1 and Q2 and then Rc1 and Rc2 they are respectively
identical. So, if we split this circuit, if we modify this circuit in some way so that we can
have two identical halves probably then our analysis it will be simpler. So, instead of
1027
using only one RT let me consider that 2 RT s are parallelly connected to realize this RT.
So, we are keeping this node connected.
So, this circuit as long as this is connected this circuit and this circuit they are same. So,
in our subsequent analysis instead of really going into this circuit, we will be talking
about the analysis of this circuit for simplicity. Namely, if I split the circuit into two
identical half then probably if we feed a signal at the base then, we can see what kind of
signal we do expect at this terminal and this terminal. So, same thing for the MOSFET
version instead of analyzing this circuit directly, let we split this resistor into two
identical parts each one of them is 2 RT.
So, that we can prepare this circuit such that, whenever it requires we can split the circuit
into two identical halves and that is the corresponding circuit. So, in our next analysis
instead of using this circuit and this circuit rather, we will be considering this modified
circuit. I should not say modified, but it is a structurally it is different, but they are
actually same circuit. So, in the next item what we have is analysis of this circuit rather
this circuit and try to see its operation basic operation.
So, here is the circuit. Before, we really go into the analysis what we have done here it is,
we have simply disconnected this two terminal then naturally this circuit and this circuit
they are not same.
1028
So, of course, this is different, but then depending on the situation probably, we can
makes the left half and right half separate. Now while we will be applying the signal at
the input like this namely at this point we do have one signal called Vin1 which is riding
on a DC voltage called VIN_C; that means, DC and then the signal we are feeding here it
is Vin2 which is also on the same DC voltage VIN_C. So, same thing in the modified
circuit here also, we consider that we are applying signal here Vin1 and Vin2 and both of
them are they are on the same DC voltage called VIN_C.
So, by doing this what we can see that, whenever we are applying a signal here and here
probably since we are familiar with this circuit and of course, this circuit then, we can
see what kind of signal we are getting at this point and this point and also we can analyze
the circuit to really understand that what kind of DC voltage you require here for proper
operation of this transistor and the circuit. So, let we consider this half. So, one of this
half and try to understand that what kind of signal we do get. In fact, we already have
seen this kind of circuit before, but it is more like a recapitulating whatever we already
know it ok.
So, let me redraw again clear and redraw the circuit, let you consider we are applying a
signal here on a meaningful DC voltage and when we say meaningful DC voltage this
DC voltage should be sufficiently high. So, that transistor-1 it is remaining in active
region of operation. Now for a meaningful collected current, we need this voltage DC
1029
voltage should be at least 0.6 with respect to this ground. So, we are assuming that this
VIN_C it is higher than VBE(on) say 0.6 V. And then based on that based on how much this
voltage it is higher the corresponding emitter voltage it will be higher than the ground
and then it will be having a current flow. And let we call this current flow it is ok.
Later I will discuss about why we consider , but let you consider this is whatever the
current is flowing this is that is also setting the corresponding collector current. We
can approximate that this IC collector current = . So, that sets the proper region of
operation of transistor-1 and hence, we can probably calculate its corresponding gm and
then rπ and then ro based on whatever the condition you are putting. Now if you see this
circuit and if I feed the signal at the base, then at the collector what you are observing
this Vo2.
And since this emitter node it is degenerated by this resistor, we know that the signal will
be getting here say vo2 equals to if I call this is vin1. So, vo2 it will be ‒ gm of this
transistor called . In fact, this expression we obtained by considering
something called common emitter amplifier, where emitter it is getting degenerated by
2RT right. And you may approximate that this = ‒ or further to that you simply
remove this gm.
So, we do have the essentially ‒ . So, that is that is the signal that kind of signal, we
are expecting sorry I forgot to write the signal part this is multiplied by vin1. So, we can
say that = ok. So, depending on this ratio, we are expecting some signal here. So,
if I observed the signal here see it is having a DC voltage defined by VIN_C and this is a
corresponding signal. So, this is Vin1 and this part is the signal here.
So, the corresponding output, what do you get here it is, it is having its own DC level.
Now, of course, this DC level it can be obtained by considering (Vcc ‒ this IR drop)
across this resistance due to this quiescent current IC flowing through it. So, this voltage
we know how to get it and on top of this one, we do have this signal just now we have
derived is its expression it is having a ‒ sign and probably it is having some amplified
version. And this amplification with respect to this input it depends on this ratio right.
1030
So, it may be amplification or attenuation of course, it depends on the relative value of
Rc1 and then 2RT. Now, if I consider the other node at this node and if I call this the
emitter signal at transistor-1 called say ve1. So, now, the circuit it is basically it is
working as common collector circuit or something called emitter follower emitter
follower. What does it mean is that the signal we are expecting here it will be almost
same as whatever the signal you do have.
So, you may approximate this is equal to vin1 and it is in the same phase. In fact, it is its
supposed to be slightly less than vin1 because we do have some signal between base to
emitter and that how we are getting the current here it is having signal and hence we
obtain the signal, but the signal here at the emitter node at this node v1 it is very close to
this signal and they are in phase. Now, if you also look into the emitter terminal we can
find its corresponding resistance. In fact, if you look into its emitter terminal, what we do
expect that it is having a signal.
And this signal it is ve1 which we claim that it is very close to vin1 and then it is having its
own Thevenin equivalent resistance and that Thevenin equivalent resistance we know
this is common collector stage. So, that is rπ ⫽ and then it is connected to 2RT. So,
that is what we see here at this point and you can probably approximate that this it is
much smaller than rπ1. So, you may consider approximately this resistance = and then
this resistance is typically a it is much higher than .
So, we can further approximate that this is equal to ve1 and this resistance it is . So, I
should say this kind of Thevenin equivalent signal source, we can see here right. Now.
1031
So, now let me let me again summarize what we said here, it is that if we feed a signal at
this point called vin1 on top of a meaningful DC voltage. Let we call VIN_C. So, that this
meaningful voltage it is ensuring that this transistor it is in active reason of operation.
Then the signal we observe at the output terminal, it is vin1 × .
That is because of the circuit it is working as common emitter with emitter de generator
of course, we do have a ‒ sign here there will be phase shift. On the other hand, if you if
you look at the emitter terminal what we can get that if I call this ve1 this is the signal of
course, it is having a DC voltage, but signal wise v1 ≈ vin1 without any phase shift and
also its resistance Thevenin equivalent resistance it is very close to .
So, looking into the emitter node of transistor-1 what we can see here it is a voltage
signal source having strength of ve1 which is very close to vin1 and then the
corresponding resistance of gm1. Now, if I apply signal here call vin2 on the same DC
voltage level same DC voltage level ok. This is very important that VIN_C it is also
coming here. So, this voltage and this voltage they are same and then we do have the
signal here. So, now, if I analyze the right half the signal will be getting at this point it is
‒ vin2 × . And in the same way as we have discussed for the left half if I look into its
emitter. So, here also you will be seeing that a signal source called ve2 and having
1032
Thevenin equivalent resistance which is ok. Now the moment we are keeping these
two are disconnected then we do have the signal here.
Now, let us see what happens for two cases namely if I say that, the circuit it is stimulus
in differential mode of operation namely vin1 and vin2 they are identical in terms of
magnitude, but they do have opposite phase. So, then what happens? So, if I assume that
this = + and then this also this if I consider = ‒ ok. So, this is one case. So, we
consider that both the circuits are we are preparing in such a way. So, that the stimulus it
is perfectly in differential form which means that this signal.
So, this part it is ‒ . So, as a result this part it becomes ‒ is getting +. So, we do have
and then . On the other hand the corresponding output here at this point, we do
have a ‒ sign here we do have a + here. So, here to here we do have ‒. So, ‒ it is getting
+ and a here, we do have + and this is ‒. So, this is a ‒ × . Now, if I assume that
this Rc and this Rc they are same. So, we can say that the signal here and the signal here
they are identical in terms of magnitude, but they do opposite phase.
Now still it is um. So, if I if I try to plot these two signal namely vo2 and vo1. So, what
we are getting it is see vo1, if I plot vo1 in blue color something like this and. So, this is
vo1 and then vo2 in red color which is similar or I should say amplitude wise it is
identical, but it is having opposite phase. So, this is vo2 and the difference of course, if I
if I say that vo1 ‒ vo2. So, that is essentially coming as two times of this amplitude. So,
this is I should say now vo_d differential. On the other hand if you see the signal at the
emitter at this point.
Let me sketch the two signals at the emitter, we do have signal at the emitter which is in
phase in phase with the red color of course, I am considering a differential input it is in
this form. So, this is the signal and of course, the signal here it is this signal it is in
opposite phase. So, this signal it is vin2 and this signal on the other hand it is vin1. So, the
differential signal we are applying here it is the shaded part and the corresponding output
here we are getting which is the differential output. Now, what you are talking about the
emitter signal at this point and if you see that this is almost equal to vin1. So, we are
expecting that ve1 it will be like this.
1033
And the ve2 it is following vin2 magnitude wise is it same. Now it is now it is very
interesting thing it is going to happen is that to get this circuit same as this circuit I need
to make a connection here. So, from here to here I need to connect. The moment you will
be connecting these two you know nodes together which is having completely identical
signal with opposite phase. So, this signal and this signal they cancels each other and it is
making it 0. Primarily because, they are corresponding Thevenin equivalent resistance
they are equal. So, the moment we make these two signals are getting shorted.
So, that makes this node and this node as single node and making the corresponding
output = 0. And hence we are expecting the signal at this point it will be 0. Now, all of a
sudden if we do this operation all of a sudden what we are expecting that, the signal at
this node it will get amplified. Why? That is because this node earlier it was having a
signal because of this emitter degenerator of 2 RT, but because of the connection of the
other half which is having identical signal, but the signal having in opposite phase
making this voltage it is signal wise it is 0. So, I can say that after making this
connection this node becomes AC ground or I should say this is virtual ground which
means that this RE it is getting completely shunted by this AC ground.
So, then this 2 RT is not having any meaning. In fact, if this is if we are saying that by
some means we are making it to ground either by a bypass capacitor or this kind of
arrangement then this circuit it becomes simply CE amplifier without having any
degenerator. So, as a result this gain instead of it becomes gm1Rc1 and of course, this
is much higher than . So, the consequence of this modification, whenever we are
making this connection the red signal the signal at vo2 it just gets amplified like this with
a very big amplitude. In fact, same thing it is happening for this also because now, this
node it is becoming AC ground.
So, the gain of this circuit it is instead of this gain it becomes gm2Rc2. So, the
corresponding output it will be × gm2Rc2. So, this blue color it got extended like this
and it is also having very big amplitude. And the corresponding output the net output the
differential output; obviously, which is the difference of this extended blue color and
your local golden color. So, the corresponding output it got amplified like this.
1034
So, in summary I should say that in case if we are making this connection to get this
actual signal actual circuit or equivalence of that actual circuit and if we stimulate this
signal the circuit with perfectly differential kind of a signal namely, with + sign as
vin1 and ‒ with at say the other terminal for vin2. Then the signal coming at this point
at this point it is ‒ × gm1Rc1 and the signal here it is a + × gm2Rc2 and this node
it is becoming grown. So, if I see the corresponding output here differential output
Now if I take difference of this and this, where if I take this as +ve side and this has a ‒
ve side then the corresponding vo_d it becomes which is defined as vo1 ‒ vo2 it becomes a
gmRc assuming that this gm and this gm they are same. So, gm1 = gm2 = gm, same thing Rc1
and Rc2 they are equal and they are Rc this × . So, this is what we do get as
differential gain which means that if I take the sorry this 2 it is getting cancelled because,
we do have half signal here and another half signal we do have. Now, if I take the ratio
of the differential output divided by this vin_d then the corresponding gain of the circuit it
is gmRc.
So, what we are getting here it is = gmRc. In fact, this gain it is same as common
emitter amplifier gain of course, the ‒ sign is not here because, we have excess this
terminal for vo1 on vo2 otherwise magnitude wise gain of CE amplifier and this circuit it
is same. So, the I should say that differential mode gain Ad = same as a gain of a CE
amplifier constructed by only one half of it right. Now next thing is that how this circuit
works for a common mode right.
1035
So, let us see for common mode operation. Again coming back to the same circuit, we
are applying say vin1 here and vin2 here. So, vin1; however, of course, both of them with
DC voltage VIN_C and; however, in this case we consider signal here equals to vin and
also the signal here it is vin_c which means that it is a stimulus in perfectly in common
mode operation in other words, we are assuming that a differential input vin_d = 0.
So, with this operation before we make this connection again, we can analyze the circuit
and then we can see that the signal coming at this node it is ‒ vin_c × . So, likewise at
this point at this point this signal it is ‒ vin_c × . Now, both this signal and this signal
they are identical, but of course, they do have a different magnitude and the signal
coming at the at this point. So, signal coming at this point it is same as the vin1 and it is
an impedance it is .
So, we can say that the signal will be getting at the emitter of Q1 call say ve1 which is
equal to very close to vin_c and it is having a Thevenin equivalent resistance of . On
the other hand, if you consider the other side this side emitter node of transistor-2. So,
here also you will be having the signal ve2 that is very close to vin_c and the Thevenin
equivalent resistance it is . Now if I if I see here both this signal and this signal they
1036
are same. So, even if I now, if I make this connection if I make this connection then there
will not is any changing because both the signals are same.
So, even if I make this connection the signal coming here it will this or this whatever you
say which is vin_c. So, even after making this change or a making this connection there is
no change of the signal here and here. As a result these two signals are also demeaning
same. Now, if I say that a individual signal this signal and this signal they are identical.
So, if I take the average called vo_c.
Let me use different color it is not so, visible. So, vo_c = which is same as an
individual namely ‒ vin_c × assuming Rc1 and Rc2 they are same and from this one we
can say that =‒ , but this is the definition of the common mode gain.
So, we can say that the common mode gain of the circuit it is it is primarily depends on
Rc and RT all right. So, by making these two modes of operation we obtain these two
parameters.
So, the summary of that what do you see, that once you make this connection this circuit
and this circuit they are equal and by considering a differential mode of operation, we
obtained the expression of Ad which is equal to gm whether it is gm1 or gm2; gm × Rc1 and
1037
the common mode gain on the other hand common mode gain = ‒ . In fact, to be
more precise this expression it is ‒ right.
So, the and now, we can we may recall that we want ideally this gain should be as high
as possible and this common mode gain on the other hand this should be as low as
possible. Now, you can see that what are the elements we supposed to be changing say
for example, to increase this gain, we can replace these two resistors by active device
which may be having equivalent circuit like this having very high resistance coming
from the active device and that may that may replace this Rc by this ro and hence that will
increase the differential mode gain.
On the other hand if you replace this part by active device having a very small
conductance or very high resistance, if I call say RT and by making this RT higher and
higher we can make the corresponding common mode gain lower and lower.
So, that makes sense that if you replace these two resistors by active device and if you
replace this till resistor by active device performance of the circuit it is getting enhanced.
Similar kind of analysis it can be done for the MOSFET version and the circuit it is very
similar. So, you can see the circuit is very similar. So, I am not going to repeat this part,
but basically, what you can say that you consider two modes of operation differential
1038
mode of operation and common mode of operation and then you make the connection
from that you can get here also the differential mode gain it is ‒ gmRD and then common
mode gain Ac equals to sorry it is not ‒ based on the definition we are defining the
differential mode output.
So, this ‒ is not there, we are considering this is + and this is ‒. On the other hand the
common mode gain it is having a ‒ right. And again to enhance the circuit
performance, we like to replace these two resistors giving us higher differential mode
gain and replacing on the other hand replacing the tail transistor or tail element by active
device that makes this common mode gain going lower and lower. Now, for our analysis,
we have split this resistor, but in actual circuit, we will be having only one element. I
think most of the things we have covered what we planned.
So, the conclusion wise, we can say that we started with basic operation; basic operation
of the differential amplifier rather it we started with recapitulation of basic operation and
also we said that how to characterize a differential amplifier and particularly how do you
get the differential mode gain and common mode gain. And then we talked about
realization of different differential amplifier using transistor, I should say transistor level
realization of differential amplifier.
1039
And though the circuit represented circuit it is I should say simple enough, but that
represents most of the cases and that helps to understand the basic operation of
differential amplifier. You also have given hint of how to get the different variants of
different differential amplifier with respect to the basic structure we have discussed.
And then, we have discussed about the operating principle of the simple differential
amplifier particularly with BJT we have gone in detail how we obtain the expression of
differential mode gain intuitively and also the common mode gain by using the common
emitter and common collector operation common emitter and common collector
operation.
So, at least we understand that how the basic structure it works and in the, we also obtain
the corresponding expression of the differential mode gain and common mode gain
through this analysis and intuition. In the next class, we will be talking about small signal
equivalent circuit and arriving at the same expression of the differential mode gain and
common mode using the small signal equivalent circuit of the differential amplifier. I
think that is all to cover.
1040
Prof. Pradip Mandal
Lecture – 77
Differential Amplifier: Analysis and Numerical Examples
So, dear students welcome back to our NPTEL online certification course on Analog
Electronic Circuit myself Pradip Mandal from E and EC department of IIT Kharagpur.
Today’s topic of discussion it is: Differential Amplifier and in fact, today we are
continuing differential amplifier, but today we will be primarily focusing on Circuit
Analysis and maybe towards the Numerical examples.
So, in overall plan we are in module-7 and; under the module-7 we do have the plan of
going for Differential Amplifier. So, in our previous lecture we have talked about basic
structure and working principle of differential amplifier, prior to that we have discussed
about single ended signaling versus differential signaling, they are part of the differential
amplifier background. And today we are going to discuss more on analysis of differential
amplifier.
Specifically, for two modes of operation differential mode and common mode operation
and their corresponding gain. And, then we will also talk about large signal analysis from
where we can get the signal swing possible output signal swing and the range of DC
1041
voltage which is referred as Input Common Mode Range. So, that is the overall plan, so,
the concepts we are going to covers are the following.
So, we shall start with small signal equivalent circuit of differential amplifier both;
implemented by BJT as well as MOSFET. And, then we shall talk about small signal
analysis. Specifically, for Differential mode of stimulus or Differential mode of
operation then, Common mode stimulus or Common mode operation and then combined
one which is referred as generalized stimulus and then we may have a special case which
is referred as pseudo differential stimulus.
And then we will be going for Large signal analysis to start with, we shall discuss about
DC operating point analysis and then we shall talk about; the input DC voltage range
over which devices are in proper region of operation which is commonly known as Input
common mode range and then, we shall talk about the possible signal swing for a given
circuit which referred as output signal swing.
Numerical examples it will be followed after that, but I am not sure whether we will be
able to cover today, but yes, this is the overall flow. Now coming to small signal
equivalent circuit of differential amplifier. So, here we do have the basic; the overall
model namely, we do have a differential amplifier and then we do have the input port
which is differential in nature and the signaling we do it is in the form of differential.
1042
Likewise, at the output whenever we are observing the signal the signal we are receiving
in the form of differential. So, both input as well as the output port they are differential in
nature; which is referred as fully differential amplifier. And, then here is the one possible
implementation the basic implementation of the differential amplifier; by BJT Bipolar
Transistor and then we like to go for its analysis particularly small signal analysis.
So, for small signal analysis we require small signal equivalent circuit. So, for this circuit
we need to have equivalent circuit where, we can drop the DC part and components of
this current as well as the voltage and then the linearized circuit which is referred as a
small signal equivalent circuit and then there, we can stimulate the circuit. So, before we
go for small signal analysis, we need to get the small signal equivalent circuit of this
Now, in our previous lecture we have discussed for better understanding of the circuit
operation. We do have here we do have equivalent circuit. In fact, if you see this circuit
it is essentially same except this resistor it is it has been splitted into two parts; one is
2RT connected to transistor-1 and then, second one is 2RT connected to transistor-2 and
we are keeping they are disconnected.
If we connect the two emitters then of course, this is same as this circuit. So, in our small
signal equivalent circuit though we will be drawing the small signal equivalent circuit of
this circuit, but once we connect it, we know that we are going back to this circuit. So,
1043
then I must say that in literature this is the circuit it is referred as differential circuit, but
for our internal analysis we are going to analyze the circuit in this form ok.
So, let us try to see the small signal equivalent circuit of this one. First of all, transistor-1
we can replace by its equivalent model; namely gm1vbe1 and so, this current is between its
collector and emitter. And then, we may consider the ro collector to emitter resistance ro1
and then, we do have rπ call rπ1 and the voltage across this rπ it is vbe1.
So, this is for transistor 1 so, likewise for transistor-2 we do have ro2 then, we do have
gm2 multiplied by its corresponding vbe2 this is the voltage dependent current source and
then we do have rπ of transistor-2, rπ2 and then we do have the input terminal here. So,
we call this is In2 and this is In1.
These two emitter node they are connected together, but in our analysis we like to keep
this resistor splitted into two parts; one is 2RT connected to the emitter of transistor-1, the
other one it is 2RT connected to the emitter of transistor-2. And, then we do have RC1 the
load resistor here and then we do have RC2 which is the load resistor here.
And, then we do have output at this node and then also we do have the output at this
point; you might have observed that naming convention wise even though we are calling
this is this is Q1 and this is Q2, but whenever we have called this node, we call this is vo2.
So, we may say that the output one of the output we are observing here, which is named
as vo2.
On the other hand, the output at this node at the collector of transistor-2 we call this is vo1
and of course, this node it is AC ground so, that is the DC node. Now why do you call
this is vo1 and vo2? That is just to take care of the polarity of the signal in differential
mode. So, if I consider this input it is the non-inverting input and this is the inverting
input and then, the corresponding output if we say that this is the true signal and this is
the complimentary signal and the difference of these two voltages we call say vo_d.
Then with this convention we do get Ad differential mode gain defined as vo1 ‒ vo2
divided by voltage here called vin1 ‒ vin2. So, this becomes +ve. So, we had just like to
have this Ad +ve. It is just a convention in many of the textbook we do we have seen that
this voltage it is considered as the non-inverting output and this is considered as
inverting output; and kinds in in that convention of course, Ad it will be ‒ve.
1044
So, it is not so important it is just a convention that is all. So, with this convention
namely if I consider this is the vo1 and this is vo2 then we are getting Ad is +ve. So, now,
with this model; with this model; what we can do? We can put stimulus and then we can
get the subsequent analysis to find the expression of at differential mode gain ok.
So, this is what the small signal equivalent circuit of differential amplifier realized by
BJT and here we will be; we will be giving the signal namely we will be applying the
signal here this may be called vin1. And, the signal here it is vin2 right ok. So, in summary
we have drawn the clean small signal equivalent circuit here.
So, just now what we discussed it is shown here. So, what we have it is out of Q1 we
have drawn the small signal equivalent circuit here. So, this is for Q1. So, likewise we do
have the small signal equivalent circuit for Q2 and then the 2 RT. So, till resistors and
then the load resistors are here RC1 and RC2.
And as I said that; this side we like to call vout1 out-1 and the voltage here it is vo1 on the
other hand, voltage at this node at the collector of transistor-1 we call it is out-2 and the
voltage here it is vo2. Note that this node this node it is AC ground. So, the voltage here
we are considering the voltage here with respect to this AC ground itself. In fact, we may
consider with respect to the common ground, but anyway for small signal analysis both
this node and this node they are equal.
1045
So, they are essentially same; and then we do have the gmvbe of transistor-1 and the vbe it
is the voltage across this rπ1. So, likewise we do have here vbe2. So, that is the small
signal equivalent circuit and likewise if we consider differential amplifier realized by
MOSFET transistor then we will be getting the similar kind of circuit.
So, in the next slide here we do have the differential amplifier differential amplifier we
may consider this one or the customized one here after splitting the tail resistor into
identical elements. And, here again we call this is the +ve side of the input namely; non-
inverting input and this side this node into it is we consider ‒ve side of the input. And,
with this we like to declare this is +ve side of the output and on the other hand this is ‒ve
side of the output.
So, that we do get the differential mode gain is whatever it is +ve. Now let us draw the
small signal equivalent circuit of the differential amplifier. In fact, I already have drawn
in the next slide. So, let me directly go there yeah. So, here we do have the small signal
equivalent circuit for transistor-1 M1. So, likewise for transistor-2 we do have the small
signal equivalent circuit and then we do have RD1 here RD2 here.
1046
And the two tail resistors split tail resistors are there; and then this node it is AC ground
and then this side the drain node of transistor-2, we call it is Out-1 on the other hand
drain node of transistor 1 we call it is Out-2. Accordingly, we are declaring this is vo1 and
this is vo2 and the output we considered particularly the differential output we are
defining by considering vo1 ‒ vo2 and vin_d it is vin1 ‒ vin2.
And, with this definition of output polarity output and input polarity and this convention
Ad we are getting +ve. So, now, we like to stimulate this circuit in two modes of
operation and we like to get the expression of differential mode gain and the common
mode gain for the two small signal equivalent circuits one for BJT another is for
MOSFET.
1047
So, you may recapitulate that whenever we do have differential amplifier so, we do have
main differential amplifier containing DC sources and DC bias condition; we like to
convert into small signal equivalent circuit. So, by now we do have small signal
equivalent circuit for differential amplifier and then we like to stimulate it at the input in
this convention. And it is having two modes of operation; one is differential modes of
operation or differential stimulus that is that will help us to get the parameter Ad or
expression of Ad in this case.
And, then we do have another mode of operation called Common mode operation where,
at both the inputs we are giving the same signal vin_c making the differential = 0, for this
case common mode we are making it 0. So, if we make the differential = 0 and whatever
the differential output, we are expecting it should be 0 assuming of course, Ac_d = 0.
And, whatever the voltage you will be getting at both the outputs are essentially the
common mode output and they are identical. So, now, what we will be doing is that let
us start with differential mode of stimulus for the small signal equivalent circuit obtained
out of BJT’s implementation. So, we do have here the small signal equivalent circuit and
we like to put the differential mode of stimulus as we can see here.
1048
So, we like to put the signal let me use a different color. So, we like to put differential
signal here perfectly differential; which means that, here we like to put and here +
and both of them are with respect to a DC voltage. And, once we get the small
signal equivalent circuit, once we get the small signal equivalent circuit of course, we
will be dropping this part and then we will be considering this is AC ground.
So, that is what we do have here and so, in the small signal equivalent circuit at this input
we are applying see vin1 = + . So, likewise at the other input we are applying vin2 = ‒
and in our intuitive analysis what we have said is that if I consider see the two
halves of the circuit, if I say that the emitter nodes here and emitter nodes there
disconnected.
So, we can then split the circuit into two parts then we can observe what the signal we
are getting at this node is and we can observe the signal at this node. So, if you see this
circuit the expected signal coming at this point it is ‒ into the gain of this circuit
which is . So, this is what we are expecting at vo2.
So, it is having a ‒ sign and then we do have this gain. In fact, we can drop this one and
we can as well approximate this by × . So, likewise when you consider this node
1049
and at this point whatever vout1, we are getting vo1 equals to ‒ and ‒ we do have both the
‒es together. So, we do have .
So, this ‒ and the ‒ here polarity of this amplifier it is getting cancelled and. So, this is
. And, the signal coming at the emitter here it is approximately equal to the signal we
are applying at the base, because it is working as in fact, it is working as the emitter
follower.
And so, the voltage signal we are getting here it is ve1 approximately equal to whatever
the voltage we are applying there; namely and then its Thevenin equivalent
resistance it is multiplied in parallel with 2 RT right. In fact, I should say that let me
go step by step. So, if I consider only this part and if I consider this resistance RC1 ≪ ro1
which is typically the case, then we do get this relationship and also, we assume that the
β is very high.
So, we consider β is very high. So, with this approximation we obtain the ve1 = and
then Thevenin equivalent resistance it is and then we do have the 2 RT. So, we do
have this 2 RT and again if I consider this resistance it is very small compare to 2 RT.
So, that is getting translated into Thevenin equivalent voltage source it is almost
remaining the same and Thevenin equivalent resistance it is .
So, the signal we are getting here it is with a + sign. So, likewise if you consider the
other emitter, transistor-2 the corresponding signal source, we will be getting a signal
which = with a ‒ sign and the impedance here it ≈ .
So, in this mode of operation in this differential mode of operation namely if the input-2
and input-1, if they are complementary to each other then at this point and this point the
two signals you are getting they are complementary, their impedances Thevenin
equivalent impedances are also equal.
So, if we connect it ok. If we connect it then the signal here it will be getting 0 as a
result; as a result here, we can consider this is ground. In fact, before we make this
connection the signal if I draw. So, before you make this connection signal here it was
1050
like this and on the other hand signal at this node it was having the same strength, but
having opposite phase ok.
So, this is the signal and this signal it is shown here and the corresponding output what
we have observed at this point we do have signal which is in phase with the In1 and it is
having some decent amplification. So, we can say this is vout1. On the other hand, signal
at this point it is similar, but having opposite phase. So, this is vo2. Now so, this was the
case before we made this connection now the moment, we make this connection ok.
Before we make the connection why the signal here it was low? That is because emitter
of transistor-1 it was getting degenerated by 2 RT. So, only a small part of the applied
signal it was appearing across this vbe even though we said that this voltage and this
voltage they are equal, but actually this voltage it was slightly smaller than this one and
that it was the vbe.
Now and since this vbe it is only a small fraction of this applied input voltage and hence
the obtained signal at the collector it was only; I should say it was having amplification,
but the corresponding amplification it was not really big it depends on the ratio of RC1
and 2 RT. So, same thing it was the case here at the other output.
Now, the moment we make this connection that makes this signal and this signal they are
cancelling each other and particularly since their phases it was opposite, amplitude it was
equal and also their Thevenin equivalent resistances, they are equal. So, the moment we
make this connection the signal here it was it completely got vanished. So, the emitter
node the combined emitter node it becomes 0.
So, the moment we make this is in fact, connected it may be having only a DC voltage,
but you will not be finding any signal. So, equivalently you can see that after making this
connection it becomes AC ground right. And, once it is AC ground then the available vbe
it becomes = . So, the voltage appearing across this rπ1 it becomes = and once it
is getting the full signal the corresponding current here voltage dependent current source
that also got increased.
As a result the corresponding signal here it got changed it becomes now; so instead of
this or this it got changed to vo2 = ‒ × gm1RC1. Why? That is because now, if this
1051
node it is ground. So, this circuit it becomes like same as common emitter amplifier and
we know common emitters, common emitter amplifiers gain it is gmRC, RC is a load.
So, with this connection now, vo2 it got changed and changes in magnitude of the output.
So, same thing or equivalent things it happened in at the other end namely once you
make this connection this voltage it got increased. Because, this vbe2 now it becomes
equal to entire with a ‒ sign. As a result, the corresponding output here, it got
increased and this output now it is; so, this output it becomes × gm2RC2.
So, in let me clear and again summarize; what we said is that the moment we. So, we do
have the signal here with a +ve sign polarity and here we do have the
complementary part namely; ‒ . And, the moment we are making this connection to
get this circuit same as the original one, then the signal here it is 0, it is 0 here that
means, this is AC ground. On the other hand, the signal coming at this point it is
amplified one, but having opposite phase.
So, this is vo2 and this vo2 = ‒ × gm1RC1 likewise if you see the other side; we do
have vo1 which is in phase with the differential input and the signal here it is vo1 = ×
gm2RC2. So, the differential output vo_d which is defined as vo1 ‒ vo2. So, it becomes
× gmRC × 2 and here we have assume that gm1 = gm2 = gm and RC1 = RC2 = RC.
1052
So, that gives us so, this 2 and this 2 they are getting cancelled. So, that gives us the
differential mode gain expression is equal to which is defined as = gmRC right. Note,
that our polarity convention helps us to avoid this ‒ sign otherwise it is its gain it is same
as common emitter amplifier.
Now, similar to this circuit then similar to the differential amplifier using BJT if you
consider the differential amplifier realized by MOSFET transistor we can do similar kind
of analysis. So, in the next slide we do have the small signal equivalent circuit. So, we do
have the small signal equivalent circuit of the differential amplifier.
And, the actual circuit of course, will be getting when we are making this connection and
here also if we stimulate the circuit in perfectly in differential mode of operation namely;
vin1 = and the signal here it is vin2 = ‒ . Then, before we make this connection
we are having signal here and here, but the two signals it was in opposite phase and the
gain here we obtained, it was only , but the moment we make this connection to get
the actual differential amplifier, then the corresponding output we obtain here it is
amplified version with 180° phase shift.
And the corresponding output vo2 = ‒ × gm1RD1. So, we do have gm1 here and then
we do have RD1. And likewise, if I consider this output and the corresponding output it is
1053
similar, but 180° phase shift. So, this is vo2 and vo2 = × gm2RD2. So, again for this
case the differential mode gain Ad defined as = .
So, it becomes gmRD where gm is we are assuming gm1 = gm2 = gm and RD1 = RD2 = RD. In
fact, lot of common things is there across these two differential amplifiers. So, we can
use the same concept in this differential amplifier to understand so, that is why I did not
go in detail of this circuit.
So, now, we can go for so, we have covered the differential mode of operation and we
obtain the differential mode gain of the circuit. And, next thing is that we can go for
common mode stimulus and then we can find the corresponding gain of the circuit called
AC and to start with let me go with the MOSFET version first right and then we will be
doing the analysis ok. Before we go into that let me take a short break and then we will
come back.
1054
Prof. Pradip Mandal
Lecture – 78
Differential Amplifier: Analysis and Numerical Examples (Contd.)
Yeah. So, welcome back after the short break. So, we are talking about the common
mode stimulus. And let us see what happens to the circuit, when we stimulate the circuit
with identical signal at the 2 inputs. And so, here we do have the small signal equivalent
circuit and here, we like to feed the signal small signal. So, vin1 = vin_c. So, same thing
same signal we are feeding here at the other input.
So, vin2 = vin_c. Now for our understanding of the circuit, again we are keeping the circuit
disconnected here. And we like to see what kind of signal we do get with this stimulus.
So, if we are keeping this is disconnected and if you refer to the circuit here, at the
transistor level, this is common source amplifier with degenerator, source degenerator.
So, this is the source degenerator and we know its consequence namely the signal
coming at its output.
It will be vo2 = the input vin_c; with a ‒ sign here and then . Or you can
approximate this by ‒ vin_c gm1RD1. In fact, this one part you can remove. So, we can
1055
simply consider gm1 and 2 RT so, this gm and this gm this getting cancelled. So, same
thing for the other output, namely vo1 = again ‒ sign, the corresponding input × RD.
So, this is RD1, this is RD2 and then 2 RT. So, note that the signal here and the signal here
they are identical. Now if I consider on the other hand the signal at the emitter, if I
consider the signal at the emitter it is working as similar to our previous discussion.
Before we connect the resistor and these two resistors; we do have signal coming here
very close to the applied input voltage, which is vin_c and then thevenin equivalent
resistance it is approximately .
So, likewise if I consider the other side, this side and what we get it is similar kind of
equivalent circuit. Namely, the signal source, which is close to vin_c and then, thevenin
equivalent resistance of and note that unlike for differential case since these two
signals the applied signal at the 2 inputs they are in phase then this signal and this signal
they are in phase.
Now, even if we make this connection since these two signals they are identical there
will not be any change. So, the signal coming at this point it will be vin_c. So, before we
make this connection whatever the signal we are having here and here they are remaining
same even if you make this connection. And that is mainly because the input signal it is
the applied input signal they are identical and they are in phase. So, I should say that the
common mode output if I say, if I take average of vo2 and this vo1.
So, that gives us the common mode output vo_c. So, that is . So, that is remaining
same as individual one namely vin_c × . In fact, that gives us the common mode gain
common mode gain Ac defined as of course, with a ‒ sign do you have a ‒ sign here. So,
Ac is which is defined as =‒ ok.
So, that is that is the common mode gain. In fact, similar thing you can get for the other
differential amplifier realized by BJT.
1056
So, in the next slide we do have the corresponding circuit and here again even though we
do have small change small difference, in the circuit namely we do have rπ and rπ here.
But all practical purposes when you stimulate the circuit with identical signal here vin_c at
input-1 and input-2.
Then the signal coming here and here they are identical. And the signal at then vo2 = ‒
× vin_c. And same thing we will be getting here also namely vo1 = ‒
× vin_c. Now since the signal here and here they are in phase even if we make
this connection the signal coming here it will be remaining unchanged.
Namely this will be approximately equal to vin_c and as a result these two outputs after
even after making this connection they are remaining unchanged. And hence vo_c ≈
× vin_c with a ‒ sign. So, you may ignore this one and then you can remove
this gm part. So, that will be = ‒ × vin_c. In fact, that gives us the same expression of
common mode gain = ‒ right.
So, in summary we got the expression of the common mode gain and differential mode
gain, whenever we will be going into numerical circuit then we will see their
corresponding values. Now so, far we are talking about the small signal situation. Now
1057
you may recall that while we are applying the signal at the input definitely we are also
applying a meaningful DC.
So, now next question is that what may be the meaningful DC quote and unquote
meaningful DC? That can be that can be analyzed by considering large signal behavior
of this entire circuit. In fact, not only this voltage, but also we like to know what may be
the DC voltage coming at the 2 outputs. And we like to see whether the two transistors
really in good condition or not. So, to understand that, we need to have large signal
analysis ok.
So, before we go into the large signal analysis of course, so, I need to say one more thing
that. So, far we are we are talking about small signal one at a time, namely differential
part and then the common mode part. But then in case you have say both the signals
coming together namely if vin_c and the differential part namely + and ‒ .
If they are coming together, then what happens? So, naturally before we make this
connection the situation it was something, but again instead of repeating that I may
directly get into this connection. And then we like to see what may be the condition here
and here. So, before you go for large signal analysis, let me do one more small signal
analysis, where we are considering both the common mode and differential mode signal
together. And we like to see the corresponding output.
1058
So, in the next slide we do have the generalized mode of stimulus. So, as I said that at the
input we like to give both differential and common mode part together. And probably we
can make this connection we can make this connection. Now let us see if we apply a
differential part here . So, here we do have and then we do have on the common
mode part, let me use blue color. So, vin_c, which is going to both the inputs.
So, it is going here as well as here. Now let us see once we make this connection then
what may be the signal here what may be the signal here and what may be the signal
here. Now due to due to this is perfect differential; that means, we do have a ‒ sign here.
So, these two differential signals are not having any influence; in fact, for differential
component this is this supposed to be ground, but then we do have the common mode
component.
So, the signal coming here it is only vin_c; I should say very close to vin_c it is slightly
less, but it is very close to that. And then what happens to this output, we do have we do
have this signal it is coming in amplified form. So, this differential part it is it is showing
its effect it is in opposite phase. So, likewise here we do have the effect of differential
part, which is which is in phase of the differential input ok.
And then we do have the effect of the common mode part which is of course, having
smaller amplitude and. So, here we do have the common mode input which is again
getting flipped. Note that for our simplicity we have considered both the signals are
1059
having the same frequency. So, and then if that is the case then at the 2 outputs what will
get in the combined effect of these two it may be something like this.
So, this is the net output we do get at this point. And if I consider the other input it will
be having the corresponding signal like this. So, you can see that this amplitude it is
slightly higher, because of the common mode component is coming there and this signal
it is slightly less than the red colour. So, we can say that at the output we do have both
differential as well as common mode part they are present.
So, vo_d if I take the difference of these two signals will be getting gm1 or gm I should say
gmRC × vin_d. And if I take average of these two signals average of say this signal and this
signal then what will be getting is only this part; because they are getting added up and
the red portion it is getting cancelled out. So, we can say that vo_c if I take average of the
two signals then vo_c = gmRC × vin_c.
So, that is how the circuit it operates; now as a special case if you consider that let you
consider a special case where you like to give a 0 signal here; that means, if I apply say
vin_c = . So, what happens? So, in this case, this part if it is and then, we do have
‒ ; so, together that gives us a 0 signal here on the other hand if I am having this
signal = . So, this and this together it gives us vin_d.
So, the signal at this point with respect to ground it is . So, such kind of stimulus
namely if we have a signal only at one side and then other side it is say ground, it is
referred as pseudo differential stimulus. Many times suppose you do have an amplifier
like this we like to give signal only at one end and then of course, along with the DC.
While at the other input we like to give only this DC and the signal here it is whatever
the complete signal you may say that this vin incidentally that is this vin_d.
For such case; obviously, you will be getting a signal here which is vin_c and this signal it
is if you see here it is . And the corresponding signal here because the common mode
gain and differential mode gain they are quite different sorry, I have committed a mistake
here. vo_c it will be vin_c × yeah. So, since this gain is low that is why we are
getting smaller signal. So, now, in this pseudo differential case, whenever we are
considering, this common mode signal it is half of the differential signal.
1060
Then since this signal it is small the in even in this case the net voltage which is this vo2
and the net voltage here. So, this net voltage here which is vo1; since these part it is very
small. So, we can approximate that this output and this output they are almost like a
differential. So, based on the logic if the common mode gain this Ac it is very small
compared to this Ad.
Then you can say that even if we stimulate the circuit in this pseudo differential form, the
corresponding output there very close to like a differential operation. And that is why it
is referred as pseudo differential mode of operation right. And now, we are in a position
to go for the large signal analysis.
So, in the next slide we are going to talk about large signal analysis and we like to see
the DC operating point of the amplifier.
So, again going back to the circuit here, the basic model here, where we do have the
differential amplifier; which is getting stimulated by a pair of signal accompanying same
amount of DC voltage. And here we do have the corresponding implementation. Now we
are going to talk about what is the role of this DC voltage and what may be the range of
this DC voltage and if we vary this DC voltage what may be the situation at the output.
Now, since this DC voltage it is applied to both the input terminal, to understand this
circuit operation we do not require to split this circuit. In fact, we can keep the circuit
1061
like this. And at the two inputs so, at both the inputs we shall apply a DC voltage called
VIN_C and then we will we can observe the corresponding DC voltage here and DC
voltage here. So, we can vary this voltage and then we can see what it may happen to DC
voltage here as well as here.
Now, we have, so, we do not require this kind of split. So, we are considering this is
connected and hence our subsequent discussion it will be with this circuit we may not be
going back to the split one. Now coming back to what we said is that, if I vary this
voltage and then if we observe the voltage at the two outputs, definitely they are also
defining the condition of transistor-1 and transistor-2. And for good operation of the
circuit we want both the transistor should be in active region of operation.
So, the range of this voltage it should be such that both the transistor should be in active
region of operation. Now we also have said that to make Ac_d and Ad_c to 0 we say that
Q1 and Q2 are identical and RC1 = RC2 right. And since they are identical probably, we
can consider the entire circuit together. And in fact, since these two are identical and
these two are identical, we can say that voltage here and voltage here they will be same.
So, we can simply consider it is a folded circuit where Q1 and Q2 we can overlap
together and then we do have RT here. So, likewise we do have RC1 and RC2 they are
coming in parallel. And here you do have Q1 and Q2 they are coming in parallel. And the
voltage you are applying here it is this VIN_C input common mode voltage. Now, if you if
you analyze this circuit of course, depending on this voltage will be getting a voltage
here and then that will define this current and that current it is flowing here.
So, we do have a DC supply voltage VC. So, we can make a drop of this voltage and that
gives us the corresponding collector voltage. In fact, if you if you go step by step to that
for a given VIN_C so, what is the emitter voltage. So, emitter voltage at this node or in this
where you say merged circuit the emitter voltage equals to VIN_C ‒ VBE(on). So, it may be
around 0.6 or 0.3 depending on the transistors material.
So, that gives us the voltage here and hence the current flowing through this RT =
. In fact, this current it is flowing through both Q1 and Q2. So, here also we
can say this is IRT which is summation of the two emitter currents and if I say that both of
1062
the transistors are identical. So, we can say that half of this current is emitter current and
practically they are defining the corresponding collector current.
So, the voltage at the two output nodes, if I say that VO_DC = VCC ‒ IRC; RC1 or RC2 both
are same this multiplied by . So, that gives us the corresponding collector voltage and
we do have the emitter voltage. So, now, we have to apply a meaningful voltage here.
So, that both the transistors should be in active region of operation, not only they should
be in active region of operation it should be having sufficient the voltage here should be
having sufficient room for the signal.
So, that we can have good amount of signal amplitude it should be able to accommodate.
So, the range over which this resists this voltage it is allowed, it is referred as common
mode range. And in this case of course, it depends on the corresponding value of RT and
RC. So, whenever we will be talking about numerical examples, where we will be having
value of this RT and RC. And the supply voltage there we shall see the upper limit and
lower limit of this input common mode voltage.
Only thing is that qualitatively. So, these are the expressions, but qualitatively I must say
that it is having a good range. So, it is not necessary that we need to have very precise
DC voltage here for proper operation, it will be having a good range over which the
circuit it will be working fine. Only thing is that depending on this value of this VIN_C the
corresponding collector current it may vary.
So, I should say that collector current is strong function of VIN_C and hence all the small
signal parameters namely gm and ro and so and so, they are strong function of this
voltage. But as long as the devices are in active region of operation typically they do not
have any problem for proper functionality of the differential amplifier. Now once you get
the DC operating point next thing is that what may be the possible signal swing.
1063
So, let us see in the next slide yeah. So, input in fact, we already have discuss this point;
the input common mode range. So, the range over which this common DC voltage it is
allow to vary. Now next thing is that once we have this VIN_C and then what may be the
range of this voltage over which the transistor both the transistors they are remaining in
active region of operation.
So, if you see the range, pictorially suppose we do have the total voltage range. So, this
is VC and this is ground and suppose this input common mode voltage it should be higher
than 0.6 or VBE1. So, that at least we will be getting a meaningful voltage here.
So, VIN_C it should be higher than say 0.6 and above. So, that is the lower limit of this
and then for a given VIN_C, we do have some current flow here and then of course, there
will be some higher drop. So, the corresponding DC voltage here it may be somewhere
here. Now this is VO_DC now this DC voltage it can go as high as or it may go close to the
VC. On the other hand it can go as low as suppose we do have some VIN_C given to us.
So, VIN_C we are expecting this should be higher than this lower limit.
So, suppose this VIN_C it is given to us then the VO individual output VO1 and VO2 with
respect to this DC it can go as high as towards the VC or it can go as low as towards the
VIN_C; maybe with a margin of 0.2 or 0.3. So, whatever the range we are talking here,
this side and this side. So, that is referred as the possible signal swing. Now for a given
input DC voltage, we want this DC voltage should be towards the middle of it. So, that
1064
the +ve swing of the output signal and negatives swing of the output signal they should
be equal.
So, that gives us the maximum possible not only maximum possible peak to peak
voltage, but also that will be helping us to get the maximum amplitude of the sinusoidal
signal right. So, again as I said that whenever will be going through some numerical
examples, we shall explain little detail of how to pick the right value of the resistant says
and this resistor. So, similar to BJT for MOSFET circuit also we do have similar kind of
situation.
Namely the DC operating point, it is a strong function of the input common mode
voltage.
So, suppose we do have input common mode voltage coming to the gate or transistor-1
and transistor-2 and that essentially so, this is VIN_C. So, that defines the gate voltage
here now again here also we are assuming these two transistors they are identical and
these two resistors they are identical. And since both the gate nodes they are getting the
same voltage probably we can fold it and we can equivalently say that we do have a
single chain. Where we do have M1 and M2 they are connected in parallel way and then
here we do have VIN_C.
1065
And then we do have we do have RT here and then we do have 2 RD are in parallel. In
fact, if they are equal you may say that simply . And then here we do have the VDD.
Now for this circuit, if you may recall if we analyze this loop; then if the parameter of
the transistors are given namely threshold voltage and transconductance factor. So, from
that we can find what will be the corresponding current flow here.
For a given value of this voltage, so, if you analyze this circuit what we can say that
suppose this circuit the combined resistors they do have transconductance factor of say
it is given to us. Then it is having VGS and then also if its threshold voltage is given
to us. Then we can say that VIN_C = VGS of transistor-1 or 2 plus the total current. So, if I
say this is the current is say IRT.
So, IRT multiplied by RT. So, this is one equation another equation we can get is that IRT
should be equal to this this is combined transistors M1 + M2 together multiplied by
half and then the corresponding vgs of transistor-1 or 2 ‒ Vth square. So, we are dropping
part. So, if you solve say if you consider this equation and this equation and if
you solve, then you can find the value of this current flow through this RT.
And then you can say half of this IRT it is flowing through this resistor and this resistor
from that you can find what will be the corresponding drop. And that gives us the DC
voltage common DC voltage VO_DC = VDD ‒ RD ‧ right. So, that is how we can get the
output DC voltage. In fact, either you consider this circuit where the drop here it is ×
IRT or if you consider half of this circuit where current is half and the resistance is RD
whatever it is. So, we got the expression of output voltage DC output voltage for a given
input voltage.
Now, again this voltage it may be having a range and this voltage definitely it should be
higher than threshold voltage of the transistor. So, that we can get a positive voltage am
hence rather it will be having some current flow here. And that current flow it will be
flowing through this resistor keeping these two devices and active condition and
preferably the drain voltage and gate voltage should be such that both the transistors
should be in saturation region. And not only they should be in saturation region if we
have a DC voltage here and DC voltage here it should be such that signal should be
having some headroom.
1066
So, the again this is also important aspect, but unless we do have numerical values of the
supply voltage and resistors, probably it will be little too hypothetical to analyse. So,
once will be going through numerical examples, then we will be talking about the
calculation of input common mode range and DC operating point and then the
corresponding output signal swing. Now at the input at the input.
Now, if we apply voltage. So, far we are talking about small signal; now in case if we
apply say large signal keeping this voltage constant.
Then what happens? So, if I say that it is perfectly differential namely this is and
this is ‒ . So, if I make these two signals 0; obviously, voltage here and voltage here
they are same; namely VO_DC and this is of course, VIN_C. Assuming that vin_c it is having
a value which is within its acceptable range and then output voltage it is also having
meaningful value. Now if I if I increase this voltage subsequently, if I am also increasing
this voltage with this ‒ sign. So, what we are expecting here it is this voltage it is it will
increase with respect to its DC.
And this voltage will decrease with respect to the DC. So, if we plot the difference of
these two voltages called vo_d with increase of this vin_d. Then what we can get here it is,
input to output transfer characteristic, but then input it is in differential form so, is the
corresponding output. So, if the input is very small the behaviour here to here it was
1067
quite linear. So, this may be linear, but as you are increasing this input voltage beyond
some limit then what will happen is, this may enter into non-linear characteristic.
Likewise this side also it will be entering into non-linear characteristic.
And this Vo_d it is defined as VO1 ‒ VO2; note that this VO1 and VO2 they are representing
large signal voltage both of them are having the same DC voltage of VO_DC. But then
once we subtract it that got removed. So, range of this Vo_d it is in fact, +ve and ‒ve this
is 0 level and this is +ve and this is ‒ve.
So, same thing for Vin if I am making these two voltages together, but if we are making
this voltage it is higher and higher. Then we mean define this, Vin_d as Vin1 ‒ Vin2.
And both of them they are having this VIN_C DC. So, voltage here it is Vin1 and voltage
here it is Vin2 and both of them are having the common DC and then differential part.
Now whenever you are talking about small signal, what we have essentially considered it
is that range of this input voltage it is small enough. So, that we are talking in the small
range and slope of slope of this characteristic curve it is the gain small signal gain as we
increase this voltage beyond certain range.
Then it may enter into the saturated condition. So, whenever we are talking about
differential amplifier and if we are restricting the operation within this linear range, then
it is it can be treated as a good amplifier having good linearity between input to output.
But once you go for and some other application, where circuit is entering into the
saturated situation then also it is having some application. But the circuit will not be
called it is a linear circuit. In fact, then circuit it becomes like a comparator.
So, the basic differential amplifier structure can be used for both for amplification
purpose for analog application as well as it can be used for comparator. So, later I
whenever from the situation permit, we may elaborate on that. But just I like to say that
differential amplifier whatever the amplifier we have discussed it is having a specific
application not only for analog, but it is also having some application called mixed signal
where the output it may be more like a logic signal high or low.
1068
I think yeah that is all we do have. So, to conclude to summarize what we have discussed
today. We started with small signal equivalent circuit for differential amplifier realized in
either in BJT or MOSFET version. And then we have talked about small signal analysis
for differential amplifier specifically for three different modes of operation extensively
for differential mode and common mode.
And then also we have talked about generalized stimulous and pseudo differential is a
special operation. Then we have talked about the large signal analysis, where we mention
about the importance of DC operating point and the DC operating point it is a strong
function of the input common mode voltage. VIN_C which also defines the output
difference DC voltage and both this input common mode voltage and output DC voltage.
And the range of operation of the transistor they are defining the output swing. So, we
did not get a chance to elaborate on these two topics particularly input common mode
range and output swing; because it may be difficult to appreciate without any numerical
value. So, whenever we will be talking about numerical examples, we shall further
elaborate on these parameters. And so, our next discussion it will be numerical examples
on differential amplifier will to be covered in the next lecture. I think that is all.
1069
Prof. Pradip Mandal
Lecture – 79
Differential Amplifier: Analysis and Numerical Examples (Contd.)
So dear students, welcome back to our NPTEL online certification course on Analog
Electronic Circuits. Myself Pradip Mandal from E and EC Department of IIT,
Kharagpur. Today’s topic of discussion it is continuation of Differential Amplifier.
In the previous lecture, we have completed analysis and today we will be talking about
numerical examples. So, the concepts we are planning to cover it is the following.
1070
As I said that, the analysis part it is done in the previous 2 lectures, and we are going to
talk about numerical examples, and we do have primarily differential amplifier using
BJT then we do have differential amplifier using MOSFET and then also we do have
another example where we do have the differential amplifier, we do have both types of
transistor MOSFET as well as BJT.
So, this differential amplifier having BJT’s it will be having different perspective;
namely, the DC operating point and then small signal parameters, then differential mode
gain, common mode gain and then going to the input range and output swing.
So, almost every aspect it will be covered with this example. Similarly, here also, we will
be covering most of the aspects and then in the third example, we shall try to see that
how the performance can be enhanced by replacing one of the passive element namely,
the tail resistor by active device to enhance the performance ok.
1071
So, we do have differential amplifier realized by BJT. So, this is the circuit we have
discussed before and you may recall that in our most of our analysis we used to split this
resistor RT into two identical elements in parallel. And the intention of that was to get
more insight of the circuits particularly, to see how the differential signal and common
mode signal they are getting propagated from primary input port to the primary output
port.
Now, but then actual circuit of course, we do have only one tail resistor. So, the analysis
we have done there where this RT it was split into 2 identical part and then if you connect
the emitter of the 2 transistors together, then this circuit and that circuit they are
essentially same.
So in our discussion now, most of the time we will be using this tail resistor it is
connected together. So, here how we do have the different device parameters namely, for
BJT’s we do have β. In this case, this β may not be having much of use, but for the sake
of completeness we are keeping the parameter.
And then we do have the VBE(on) of both the transistors 0.6. In fact, we are considering Q1
and Q2, they are identical and then we also have the early voltage of the 2 transistors =
100 V. And then we do have the supply voltage = 12 V and then the loads RC1 and RC2,
both are equal; and they = 5.2 kΩ and the tail resistor it is 1 kΩ.
1072
Then, load capacitance for this example it is not mandatory, but just to say that we may
consider high frequency signal also and then we can consider that the load is also
balanced namely the load here CL1 and CL2 they are in this case they are both are equal to
100 pF.
Now to start with, we do have this DC voltage given to us which is 2.6. In fact, this DC
voltage should be sufficiently high, so that Q1 and Q2 should be in active region. And on
the other hand this DC voltage should not be too high otherwise, Q1 and Q2 may enter
into saturation region.
So, here we have picked up the value of this DC voltage well within its range, allowable
range. So, with this 2.6 of VINC, let us try to find the operating point of the transistors.
And of course, we have considered Q1 and Q2, they are identical. So, how do you
proceed? First of all, for DC analysis we can ignore the AC signal part and then we may
say that we do have 2.6 V here and also 2.6 V here at both the base terminal of Q1 and
Q2.
Now, if I consider VBE(on) drop of 0.6, then we do have the emitter voltage DC wise it is
2 V. Now RT = 1 kΩ. So, the current flow here it is , so that is 2 mA. And under
quotient condition, in absence of the small signal, this 2 mA current it is equally getting
divided into 2 halves, one for the left branch and another one is for the right branch. So,
1 mA current it is flowing through Q1 likewise, for the Q2.
Now, we assume that of course, this is the emitter current 1 mA. So, we assume that the
base current is very small. So, we can say that the collector current of transistor 1 as well
as transistor 2 both of them we can well approximate by 1 mA. Now we do have 6 V
here sorry, we do have 2.6 V here we do have 2 V here, and now we do have 1 mA
current is flowing through this resistor which is having a value up to 5.2 kΩ.
So, the drop across this resistor it is 5.2 V. So, the voltage at the collector DC voltage at
the collector it is 12 V ‒ 5.2. So, that = 6.8. So, we can say that now we obtain the
operating point and then also we obtain the DC voltage. DC voltage it is same here also
6.8 V ok.
1073
So, to summarize the DC operating point, we do have 2.6 V is the base voltage and then
at the emitter. So here also, it is 2.6 V and at the emitter we do have 2 V. Then, voltage
here it is 6.8 V and here also it is 6.8 V and the collector current in both the transistors
they are equal and they are 1 mA right.
So, that gives us the operating point of both the devices. In fact, you can calculate what
is the VCE and ensure that Q1 and Q2 both are in active region of operation. In fact, we do
have sufficient headroom.
So, in case if you have say VCE is at is 0.3 V. So, this voltage it can come down as low as
2 point; so, this voltage it can go as low as 2.3. So likewise, so we do have a swing here
with respect to DC voltage it is 6.8 ‒ 2.3. So, that = 4.5. So, the ‒ve side swing it is 4.5.
So, the output showing; so, ‒ve side it is 6.8 ‒ 2.3 V, alright. So, that is considering VCE
voltage = 0.3 and that = 4.5 V. So, likewise for +ve side for +ve side the voltage here it
can go towards the supply voltage. So, here we do have 12 V DC and then the DC
voltage at the output it is 6.8.
So, the +ve side on the other hand it is 12 ‒ 6.8. So, that = 5.2 V. So, we do have fairly
good swing. So, which means that whatever the DC voltage we do have, over that DC
voltage we can have very nice signal swing. So, the circuit operating point it is very
good. So, 6.8 V is the DC level.
1074
So, now we obtain the output swing. So, we obtain operating point, we obtain the DC
voltage; now, next thing is the small signal parameter of transistors. So, we do have the
collector current IC = 1 mA, and that gives us gm = , if I consider thermal equivalent
voltage, it is 26 mV.
So, that = ℧ and then rπ = . So, that is 100 × 26; so, that = 2.6 kΩ. And then output
resistance ro, so, that = . So, this = . So, that is giving us 100 kΩ.
So, we assume that this 100 kΩ it is much higher than this passive load RC1 and RC2. So,
that gives us the small signal parameter. In fact, for the other transistor parameters are
also same corresponding to whatever the parameter we obtain for Q1. So, now we obtain
the small signal parameters of both the transistors. Next thing is we need to find the
small signal gain namely, a differential mode gain and common mode gain.
So, the differential mode gain Ad = gmRC and this is equal to RC it is 5.2 and gm = and
this is of course, it is kΩ. So into 103 so, that is equal to 200 and the common mode gain
on the other hand it is alright .
And so, in the numerator we do have 200, just now we have calculated and then we do
have a 1 + . So, this is equal to how much? ; I do have calculator for me. So,
= 77; + 1 and the denominator and so that, reciprocal of that, multiplied by 200 is giving
me 2.566 and so and so.
In fact, if you ignore this 1, you will be getting this = 2.6. Of course, it is having a ‒ sign,
alright. So, we do have the differential mode gain of 200 and then we do have the
common mode gain; common mode gain is basically approximately it is ‒ 2.6.
So, now next thing is that once we feed the signal, once we feed the small signal namely,
vin1 and then vin2 based on this differential mode gain and common mode gain, we will be
getting the signal at this point namely, at vo2 and then vo1. And to get the individual
signal first of all, based on this Ad and Ac as you have done for the macro model based
numerical example.
1075
To get the individual signal first thing is that, we need to see what is the differential
input, and then what is the common mode input, and then we multiply this differential
and common mode component of the input by their respective gain to get the vo_d and
vo_c, and from that we can find what will be the individual signal. So, keeping the
operating point same, let we find what will be the corresponding output for a given set of
vin1 and vin2.
So, in the next slide what we have it is, so, we are keeping the operating point same.
Namely, we do have VINC = 2.6 V and that gives the whatever the operating point we
obtain and we know that DC voltage wise VO_DC = 12 ‒ 5.2, so, that is 6.8, right.
And also, we have calculated the Ad = 200 and Ac on the other hand, it is ‒ 2.6 now here
we do have the vin1 and vin2 and if you see here, the this part similar to our numerical
examples associated with the macro model vin.
So, this 2 if I consider, so, this is giving us vin_d = vin1 ‒ vin2 = 0.02 ( ). On the
other hand, if I consider the common part namely, if I take the average of the 2 inputs; so
that gives us the common mode input vin_c = = 0.2 ( ).
So, we do have the common mode component and we do have the differential mode
component here and we do have the differential mode gain and common mode gain. So,
1076
from that we can get vo_d = 200 × 0.02. So, that gives us 200 × 0.02 ( ) =4
( ). So, that is the differential output.
So likewise, we can calculate the common mode common mode output vo_c = ‒ 2.6 × this
common mode part 0.2 ( ), it is having different frequency. So, this is equal to
how much? This is 0.52 ( ) of course, with a ‒ sign.
So, now we have obtained the differential and common mode component. So, the
individual signal now, we can say that say Vo1, it is having the DC part 6.8 V, DC and
then, we do have the common mode part. So, that is ‒ 0.52 ( ) and then it is also
having half of the differential part. So, that = +2 ( ).
So likewise, if you see the other output Vo2; so, that is also having DC of 6.8 and then the
common mode part ‒ 0.52 ( ) and then ‒ 2 ( ). So, that gives us the
complete output. So, we can see here; this is the common mode part. So, this part and
this part they are common mode and then we do have the differential part, here and here.
And if you compare if you compare the common mode part and differential part, it is
almost that differential part if I see, individual signal-wise and if you take the particularly
the differential output, at differential part it is quite large. In fact, almost 8 times higher.
So, this part it is almost 8 times higher than the common mode part.
However, if you see at the input if you compare the differential part which is 0.2 and
then common 0.02 rather and common mode part it is 0.2. So, here on the other hand, the
common mode part it was 10 times higher.
Which indicates that the whatever the signal we are receiving here, that may be getting
affected by significantly I should say affected by unwanted signal having an amplitude
which is 10 times higher than the desired signal, differential signal.
And through this differential amplifier which is having differential mode gain, it is much
higher than the common mode gain and that is why at the output we are getting the
desired signal almost having 8 times higher amplitude than the unwanted component
1077
unwanted component is this common mode component, right. So, that is the basic
motivation.
Now, next thing is that how do we see the signal? Particularly, if I consider how the
common mode and differential mode signal it is getting propagated.
Particularly, you may recall in the analysis we used to split this resistor into 2 parts, and
we use to claim that this 2 RT and this 2 RT we used to split them and then we used to see
that the signal here and signal here it was propagating differently for common mode part
and differential part.
And now here, at the input the stimulus it is having both differential as well as the
common mode part.
1078
So, in case if you in this actual circuit if you split these 2 resistors and we like to see
what other things are happening, namely, with this kind of signal what is the signal
amplitude you are getting at the emitter and the output. So again, we are keeping the
same operating point, only thing is that the RT it has been split into 2 parts, identical
parts 2 RT and also here we have opened it, here we have opened it.
Now in this case, if we open it and if we are keeping the same stimulus namely, vin1 and
vin2 then what happens? First of all, if you see once you do have a split here, identical
split here and then even though we are applying the same 2.6 V here, the operating point
it is remaining same, but left and right half they are completely isolated.
So here again, if you see the operating point here, the DC voltage it 2.6 and the voltage
coming here it is 2 V and now 2RT having RT = 1 k, this current it is 1 mA. So, that gives
us the emitter current 1 mA and then the collector current is also very close to 1 mA.
So, we can say that 1 mA it is flowing through RC1 creating a drop of 5.2 V since its
value it is 5.2 k. So, the voltage here again it is 6.8. So, with this spilt of course, the as
expected the operating point is not getting changed.
So, the corresponding small signal parameter namely gm1 and gm2, they remain same and
both of them are equal to ℧ and rπ of the 2 resistors transistors they are remaining 2.6
k and then ro1 = ro2 they = 100 k.
1079
Now, if I am having this parameter and then I do have a signal v in1 coming here. So,
what do you expect? That the left half it is completely isolated. So, just by analyzing this
left part we can calculate what may be the signal coming here and the signal coming
here, ok. So, let me clear the board and then let me write those signals expression.
So, the gain of this transistor Q1 and its corresponding associated bias we can say that its
voltage gain = of course, with a ‒ sign. So, what is the value? Here, we have
calculated this = 200 and this is 1 + close to 77 and this = ‒ 2.56 or I should say, ≈ ‒ 2.6.
So, if I ignore this 1, then you then that gives us 2.6.
So, that is the gain from this point to this point. This means that for this input, the output
signal we are getting namely, vo2 what we are expecting here it is ‒ 2.6 × vin1, alright.
And then we do have 2 components and if you see here so, the first component it is ‒
0.026 ( ) and then we also have to multiply this 0.2 and 2.6 for this component.
So, that is equal to ‒ 0.52 ( ). You might have observed that since this circuit,
left part it is completely isolated from the right part. So, this circuit of course, it is
working as common emitter amplifier having a degenerator of 2RT.
1080
So, this circuit of course, it cannot distinguish which is common mode part and the
differential part. So, the differential part as well as the common mode part it will amplify
and whatever the signal it is coming here it is given here.
And also, if you see the signal at this point and so, if I call that signal it is ve1. So, what
kind of signal do I get? Before we can consider this RT, we are getting almost the vin here
and then we do have the output impedance which is .
And then we are connecting 2 RT. Note that this vin1 it is not this vin1, it is the signal
coming at this point which is very close to this signal, alright. And so, before we
consider this resistance the signal here, if I consider it is having say infinite resistance
then at this point the signal it will be same as whatever the signal we are applying here.
So, that is why you are calling it is voltage it is getting translated to emitter or emitter is
following the base terminal. And then we do have this resistance which is . So, once
this Thevenin equivalent voltage source it is getting loaded by 2 RT then, whatever the
voltage we do get here it is nothing, but this RE1.
So, this voltage it is vin1, the reflected signal coming to the emitter multiplied by 2 RT
that is because, divided by 2RT + . That is because, this signal it is getting divided
across this and 2RT to create this voltage called ve1.
So, this is the; this is the signal we are getting at this point before connecting the load, it
was like this and then once we connect this 2 RT then, whatever the voltage we are
getting here. So, if I calculate this one, it is coming vin1 multiplied by this is 2 k. So, 2000
and this is 2000, this is that is 26 so, 2026. In fact, this part it becomes very close to
1 this = 0.987, I think that was my calculation 0.987 multiplied by this vin1.
Which means that, I do have this signal = ‒ so, no I do not have the ‒ sign here, I do have
the signal coming in phase. So, I do have 0.01 × 0.987; so, I do have 0.00987 ( ).
And then we do have this part that is also getting multiplied by this one so, that = + we
do have 0.1974 ( ). So, that is corresponding to this part. So, this is the signal
coming at emitter here.
1081
In fact, similar kind of things you will be getting at the other side namely, at this point
and likewise, here also we will be getting the signal. So, the signal coming here it will be
similar to whatever we obtained namely, the gain of this transistor along with its bias
arrangement it will be having the same gain of ‒ 2.6.
So, we can say that vo1, this vo1 signal wise, it = this is having ‒ gain is ‒ 2.6 and this
signal it is ‒. So, I do have + 0.026 ( ) and then we do have this part. So, it is
having a ‒ and then we do have 0.52 ( ).
So, we do have the 2 frequencies again, this amplifier it does not really understand the
common mode part and differential part. So, both of these parts are getting amplified by
the same gain. So, if I see individual signal, if I see the see individual signal this and this
of course, it is having both the frequency component and if you are keeping this node
still open and if you consider the differential output say vo_d is vo1 ‒ vo2 by definition.
And, so if I take the difference of this signal and this signal then, obviously, this part it is
getting removed, leaving behind this part and this part multiplied by 2; because they do
have opposite sign. So, what we are getting there, it is 0.052 ( ), and this part as I
said, that they are getting removed.
On the other hand, if I take the average of the 2 signals; so, if I take average of this signal
and this signal that gives us the output common mode. And so, if I take average of vo1
and vo2, in fact, in that case this part and this part they are getting cancelled leaving
behind this part and this part.
So, that = ‒ 0.52 ( ). So now if you see, that this part even if you are keeping this
is open, the common mode part common mode part it is same as the case when we have
connected it or in the previous circuit.
But then, the differential part if you see it is quite small. In fact, if you connect it to get
the original circuit, then what we have obtained it is that corresponding differential
output; it was having an amplitude it was 4 V if you recall right, and so, now if I make a
connection, what we are expecting that the emitter voltage at this at the emitter of
transistor-2 it is also having similar kind of signal as you can see here similar kind.
1082
So, what will be the difference? This part it will be same, but this part it will be having
opposite sign. So, if I observe the voltage at this point, before we make the connection
and we call this is say ve2. So, that is equal to this part and the first part it is having a ‒
sign, ‒ 0.00987 then whatever, × ( ).
And then this part on the other hand, it will be having + sign, + exactly this one 0.1974
then whatever it is. So, the moment we make this connection, this part and this part they
are getting cancelled out, and also at the output this part and this part they got amplified
and both of them this part it was it is getting converted into ‒ 2 ( ) with this
connection, if you make this connection.
Same thing this part is also getting increased to + 2 ( ) and naturally, the
amplitude of the differential part it got changed to 4 ( ). So, this got changed to 2
and this is also 2. So, that gives us the amplitude of 4, alright.
So in fact, in hardware you can make this experiment namely, you can construct this
circuit and then if you keep it open and then if you observe the signal here and here, what
you will be seeing here, mostly the common mode signal it will be dominating hardly
you will be seeing the information out of the differential part because, at the input the
strength of the differential signal is very small.
1083
And then, the moment you make this connection all of a sudden, then you will see that
the differential part it will be appreciated and then common mode component; however,
it will be remaining same.
So in fact, you can do this experiment in the lab, lab setup and you can get a feel of it
alright. So next thing is that we will see what will be the suitable range of this input
common mode voltage? And so, we have taken a meaningful voltage here, but we like to
see what may be its meaningful range namely, lower limit and upper limit. But then let
me take a short break and then we will come back.
1084
Professor Pradip Mandal
Lecture 80: Differential Amplifier: Analysis and Numerical examples (contd.)
Part-B
So, we are talking about the Differential Amplifier and we assume that we do have
meaningful value of this DC voltage. So, our next exercise is to find what may be the
range, suitable range of this common mode voltage.
1085
So, here we are having some value of VINC which is just 0.8 V. In fact we need this
voltage to be at least 0.6 V because to make Q1 and Q2 ON, we need the VBE voltage
sufficiently high. So, here just we are taking 0.8 V so that the drop across this resistance
it is only 0.2 V. So, if the voltage here it is only 0.2 V and RT it is 1 kΩ and the DC
voltage here it is 0.8 V which is given here. So, the current flow here it is .
So, that is 0.2 mA. Of course, strictly speaking if we have say 0.2 mA current and if we
have a split of this current and the emitter current it is say 0.1 mA, then VBE it will not
remain at 0.6 V, it may be definitely lower than 0.6 V, maybe around 0.5 V. But just to
say that even if it is a 0.5 V the value of this current it is quite low compared to our
previous case where we considered current it was 1 mA.
So, instead of going into the detail of what exactly be this current, but see this DC voltage
here it is low enough making this current it is small and we like to see what is its
consequence. So, if the IC current and IE current it is 0.1 mA and hence we can
approximate that IC1 = 0.1 mA. So, same thing for IC2 as well. And then the drop across
this resistor 5.2 kΩ is only 0.52 V.
So, the DC voltage here and here it is 12 V ‒ 0.52 V, so that is 11.48 V. So, this voltage it
is quite high. So you may feel that once this DC voltage is closer to this supply voltage,
1086
the signal swing towards the +ve side it is very limited, it will be only theoretically only
0.52 V. On the other hand ‒ve side we do have very good swing. It can go as low as 0.2
V here and VCE(sat), so that is 0.3 V. So the lower limit here it is 0.5 V.
So, if it is 0.5 V here the minimum value of the output voltage then we do have a very
good swing of 11 V, close to 11 V. So, ‒ve side swing is not a problem but the +ve side
swing it is very small 0.52 V so, that is the first problem. The second problem it is with
this value of IC, gm1 and gm2, they are now = ℧. So, of course, the resistance ro
they are also quite high.
So, ro1 = ro2 both of them are = 1 MΩ, but it is not having any influence on the gain
because the output resistance it is dominated by this passive resistance. So the differential
mode gain Ad, which is gmRC = . So, that is equal to only 20. So, the gain you may
recall the previous case when the current here it was 1 mA, the gain it was 200, now it
comes to 20.
So, necessarily the signal, expected signal at the output it will be quite small. So, what we
are expecting that vo_d = 20 × vin_d, and vin_d is 0.02 ( ) V. So, vo_d = 0.4
( ) V. So, the amplitude here instead of 4 V now it becomes only 0.4 V. Also if
you see the common mode gain, AC = ‒ .
And the gm we say that ℧. So, the numerator it becomes 20 which we already have
calculated, and here we do have ( ). So, I do have the common mode gain, it is
not having much change, in fact it is only ‒ 2.3 instead of ‒ 2.6.
So, the common mode gain you did not change much but then differential mode gain it
has significantly changed. So, then now if you see the, so due to this one, vo_c it can be
obtained by multiplying this 0.2 with 2.3. So that gives us ‒ 0.46 ( ) V. So that is
1087
the vo_c and then this is the vo_d and the DC voltage it is given here. So, from that you can
find the individual signal namely say vo1.
So, this is having a DC voltage of 11.48 V. And then we do have this signal minus so,
there is a common mode signal, ‒ 0.46 ( ) V. And then half of this signal it is +
0.2 ( ) V. Now, if you see the magnitude for some time instants, the magnitude it
will be 11.48 plus for some time instants you will be having 0.46. So, that gives almost
close to 12 V. And then we do have 0.2.
So in fact, if you add this amplitude, this amplitude and this one it is exceeding this 12 V
which is impractical. So, what does it mean is that at this point and this point the signal
combination of this common mode and differential in fact they are getting distorted,
because the voltage here it cannot exceed this 12 V, indicating that the DC operating
point it is too high. In fact, you may recall the positioning the operating point with respect
to the load line.
So, suppose this is the load line defined by the corresponding RC that we have discussed
for common emitter amplifier, and if the circuit is in good condition then pull down
element should be such that the operating point should be middle of this range. Now, in
this case since the current here it is too small the corresponding characteristic curve of the
transistor actually it is here. So, due to the small current, the operating point it is very
close to that VCC supply.
As a result even if you do have a small signal, the signal it is getting distorted there, so
we need to be careful there. So, indicating that this voltage probably it is quite low and it
is alarmingly low and the gain here it is very small particularly the value of the gm it is
small and that is coming from the device it is almost in the, I should say towards the
cutoff. So, definitely lower this VINC it will be having even more severe problem. On the
other hand let us try to see what may be the upper limit of on this VINC.
1088
So, this is the exercise we can try, what maybe the maximum value of this VINC keeping
both Q1 and Q2 in active region of operation, which means that we like to get a limiting
case, namely if I increase this voltage then what will happen is, this voltage it will follow
the base voltage ‒ 0.6 V and hence this current IRT increases. And if the IRT it is
increasing, then drop across this RC call VRC1 that also increases.
And since we do have fixed 12 V and if this drop it is increasing so, that will make this
voltage decreasing. So, which means that if I increase the voltage here the base voltage of
1089
transistor-1 it is going higher and higher, on the other hand the collector voltage it is
coming lower and lower. And there may be a situation where these two voltage
difference it will be such that the base collector junction it may get forward biased.
In fact, if it is weakly forward biased then we may say that device it is entering into the
saturation and if it is strongly getting forward biased, then deep into the transistor it will
be deep into the saturation region. So, to calculate the limit of this DC voltage where this
transistor it is just entering to the saturation, what we can do either we can compare this
voltage and this voltage or the better approach is that if we have the base voltage, and
then we take, take out 0.6 V to get the emitter voltage here.
And then we add VCE(sat) of 0.3 V. So, then we can say that this is the limit of the
collector voltage. Namely, if I consider the this path in the limiting case, whatever the
voltage you do have ‒ 0.6 V, so VINC(max) ‒ VBE1 of say 0.6 V then + VCE is at of 0.3 V.
So, that is equal to the collector voltage, and then if I add this voltage, this voltage, so
that is RC into whatever the IC called say IC(max) so, that is equal to 12 V.
In fact, if you consider this voltage in the limiting case, this is equal to the emitter
maximum voltage and this voltage it is RT × 2 times of whatever the collector current we
do have approximate in that collector current and the emitter current they are equal. So, if
I rewrite this equation what we are getting here it is 2RT × IC(max) + RC1 × IC(max) = 12 V ‒
0.3 V. And as I say that this 0.6 V it is VBE1 and this 0.3 V it is VCE saturation limit.
So, we know the value of this RT, we know the value of this RC1 and so we can calculate
what is the maximum value of IC called IC(max) = so this much of mA. And this
gives us, IC(max) it was 1.625 mA. And this current it is creating a drop here which is 2
times of this current multiplied by this 1 k. So, the corresponding drop here or the emitter
voltage here it will be 3.26 V.
Now, if I add this 0.6 V here, to get the corresponding maximum voltage of VINC(max) so,
that becomes equal to 0.6 V and 3.26 V so, that is 3.86 V. So, this is indicating that if I
put this limiting case and again if we recall the load line and the operating point concept,
1090
ideally we like to keep the device in this region and the operating point should be almost
at the middle of the possible range.
And in this case if I consider VINC(max) the corresponding device characteristic it is going
towards the extreme, namely it is going somewhere here. And keeping the device it is just
at the saturation limit. So, this is corresponding to VINC(max) and this is the maybe some
nominal case. And other case we already have discussed that if on the other hand VINC it
is approaching towards 0.6 V then the characteristic curve it will be like this.
So, that gives us the range of VINC. So, while we will be designing this circuit we have to
keep that in mind. And since we do have passive resistor here, so the operating point it is
very much dependent on this VINC. If we do have active device probably then dependency
of this current it will, it is not so much on VINC, but again VINC definitely it will be having
a suitable range. So, once we see some numerical example, there probably we can discuss
the range of the VINC.
1091
Now, coming to differential amplifier realized by MOSFET and going back to the similar
exercise. So here we do have differential amplifier realized by MOSFET, it is very
similar to BJT but of course, the I-V characteristic here they are different. So, again let
me consider a meaningful value of the input DC voltage of 4 V and different parameters
are given, both the transistors are identical having transconductance factor of 2 mA/V2,
threshold voltage of both the transistors are 1 V, λ’s are given here.
And then RD1 and RD2 they are identical and both of them are equal to 4 kΩ, supply
voltage it is 12 V and again RT we are considering 1 kΩ and this load capacitances in this
example it is not really having much significance. Now, coming to how we find the
differential mode gain and common mode gain, first of all we need to start with the
operating point of the transistor. So, we do have a DC voltage at the gate which is equal
to 4 V.
Now if we have a 4 V then it is, probably it is having some VGS here whatever you say
VGS1 or VGS2 and here also of course we do have 4 V and the voltage here of course,
depending on this DC voltage divided by this RT it produces a current of IRT. And again
because of identical transistors M1 and M2 and RD1 and RD2, and the currents are getting
equally split into two branches. So, this is and so and so.
1092
So if I consider this loop and if this voltage is given to us, from that we can find what will
be this current or we can see what will be the corresponding IDS current of transistor-1.
And so, let us try to see the, for this voltage what is the corresponding IDS. First of all this
IDS = , whether it is for transistor-1 or transistor-2 they are equal. So, we
are ignoring this part.
So we consider ≈ 1. So, here we do have the second-order equation and also

the current flow here it is 2 times of IDS. So, we can say that VINC ‒ VGS whether you call
VGS1 or VGS2, so that is equal to 2 IDS × RT. And then expression of IDS it is given here.
So what you can do here it is we can write this × RT.
Now, we would have VGS1 here but we do have . So, we can probably
directly we can try to solve and try to see what is the VGS1 or maybe a better way to
convert this VGS1 in the form of (VGS ‒ Vth), what we can do, we can take (VINC ‒ Vth1) ‒
(VGS1 ‒ Vth1) = × RT.
Now, this equation here if you see, this term particularly VGS1 it is not known to us. So,
we can say that these two terms we can say x. Rest of the things are known to us. So, this
is 4 V ‒ 1 V, Vth is 1 V and let you call this is x equals to this is given us 2 mA/V2. So,
this is x2, unit of x is volts, and then RT it is 1 kΩ. So, that gives us 2x2 + x ‒ 3 = 0.
√
And from that you can get x = = . Obviously x = ‒ 1.5 V we will not
be considering because that is not the practical value so, we will take x = 1 V. So,
actually x = 1 V.
So, that gives us the, VGS ‒ Vth is 1 V and hence VGS = 2 V. And in fact from that here we
can say that, IDS equals to this part it is 2 mA/V2, this part is 1 and this is 2. So, that gives
us IDS1 = 1 mA. So, we got this IDS = 1 mA. So, the current flow here it is 2 mA. So, that
gives a drop here it is 4 kΩ × 1 mA, so that is the 4 V drop.
So, we do have 12 V supply ‒ 4 V. So that gives the DC voltage, here it is 8 V, and this is
also DC voltage of 8 V. Now, you can see that we do have at the gate, we do have 4 V
1093
and at the drain we do have 8 V, so that is good for this transistor, the transistor it is well
within its saturation region of operation. So far we obtain the operating point and then
DC voltage you also obtain. Now, we can calculate gm.
So, gm1 it is for a given value of the VGS1 = 2 V. So, from here we can calculate gm1 =
× (VGS ‒ Vth) = 2 mA/V. Same thing gm2 also. And, both rds1 and rds2 that is equal to
= in fact, that gives us 100 kΩ. So, that is how we obtain the small signal
parameter of the transistors.
On the other hand swing wise if we have 8 V DC and then, +ve side we do have 4 V
swing and ‒ve side on the other hand if the gate voltage it is 4 V and threshold voltage it
is 1 V, so the minimum voltage at the drain it is 4 ‒ 1 that is the 3 V. So, lower limit it is
3 V. So, the possible swing here it is 8 V ‒ 3 V, so that is the 5 V; ‒ve swing.
So, the +ve swing it is 4 V and ‒ve swing it is 5 V. So, it is having very decent amount of
signal swing. Now coming to the gain, gm it is 2 mA/V. So, that gives us the differential
mode gain Ad = gm1 × RD. So, this is 2 m × 4 k = 8.
So, the common mode gain so, what we say that Ad we obtain equals to 8 and Ac = ‒
= . So, that gives us ‒ . So, the differential mode gain it is 8 and
common mode gain it is ‒ .
So, as anticipated that the differential mode gain it is not so high because of the most
transistors, they do have a relatively lower value of gm but whatever it is. Now, let us see
that what kind of signal we do get at the output. So, again let me consider these two
signals and let you consider it is mixed mode of operation, namely at the input we do
have both, differential as well as common mode signal.
1094
So, we do have vin1 and vin2. Again here it is having the differential signal and the
corresponding common mode signal. And you may recall that the Ad = 8 and Ac = ‒ .
Now for, for simplicity of calculation let me consider this common mode part it is 0.5
instead of 0.3, as the common mode gain it is ‒ .
So, the differential signal, at the input vin_d = 0.5 ( ) V. And on the other hand the
common mode vin_c = 0.5 ( ) V. Note that since the gain differential mode gain
here it is low, intentionally we are taking relatively higher value of the differential input
compared to the case when you talked about differential amplifier using BJT.
So, both differential part and common mode part, they have equal amplitude. Now, using
this information we can say that vo_d = 8 × 0.5 ( )V=4 ( ) V. And the
common mode output vo_c = ‒ × 0.5 ( ) V= ‒ 0.8 ( ) V. So, if I combine
this two we can get the individual signal and as I said that individual signal they do have
a DC voltage of 8 V, so Vo1 it is having a DC part of 8 V and then plus common mode
part, it is ‒ 0.8 ( ) V. And then half of the differential part, so that is plus in phase
with this differential, so that is plus 2 ( ) V.
1095
So, likewise the other output Vo2, it is having a DC part of 8 V and then it is having the
common mode part of ‒ 0.8 ( ) V and then ‒ 2 ( ) V. Now, again since
the differential mode gain and common mode gain they are different. In fact, common
mode gain it is one fifth of the differential mode gain.
So, as anticipated that the signal at the output if I consider difference of this two it is
having a differential mode signal of 4 V amplitude and common mode part unwanted part
it is having 0.8. Of course, it is getting reduced but still it is not clean, the differential part
it is still it may get affected by this common mode component.
So, we need to do some modification of this circuit, either we can try to increase this
voltage gain or differential mode gain, or we can try to decrease this common mode gain
or maybe combination of both, we can try both increasing the differential mode gain and
decreasing the common mode gain. In fact, if you see the expression of the common
mode gain this RT or 2RT is having important role to play.
So, to decrease this resistance what we can do, we can replace this resistor by say active
device so, in our example what we will be doing, we will replace this resistor by an active
device and then we will see what may be its corresponding consequence. And in case if
you want to increase this gain, we can replace this to passive resistor by active load. So
that example probably some other day we will see, but today definitely we will be
replacing this passive element by active element.
1096
So, before we go into that, we can also like to see what may be the suitable range of this
input common mode voltage. In fact, if you consider threshold voltage of the devices it is
1 V. So, definitely the theoretical limit of VINC it is lower limit is 1 V, but to have some
current, the voltage here should be beyond that. So, let you consider the voltage here it is
say 1.12 V and try to see what is the corresponding current.
1097
So, in the next slide what we are considering that VINC it is, it is 1.12 V. And if you
consider this is 1.12 and the method we have followed to find the corresponding current it
can be followed and it can be shown that the current here it is 0.1 mA. So, these two
currents are 0.1 and 0.1. So, that gives us the voltage here it is 0.2 V and no this is 1.2. So
sorry, this would be VINC = 1.21 V. So, if I take 1.21, we will be getting a meaningful
value here, yes. And then VGS ‒ Vth, I think the numerical value we have taken here it is
not so accurate to get a round of current.
1098
But just I like to say that in this case, again here we do have a meaningful range of VINC,
so if we do have higher and higher voltage then that may increase this current, and that
may that may increase the voltage drop here and hence it may push this transistor M1 into
triode region. So, we can probably find what may be the corresponding upper limit so;
upper limit is very important for this case.
Lower limit definitely we do not want to keep the transistor more towards the sub
threshold region, definitely not, but we should be aware about the upper limit. So, due to
this, this question it will maybe or this numerical problem it will be similar to the
previous one, we will skip that part and in the next problem what we will do, we will
replace this resistance by active device and try to see what maybe its corresponding
consequence on the common mode gain and differential mode gain.
1099
1100
So we do have a differential amplifier and also I must say that in this circuit this is the
first time we are trying to combine both MOSFET and BJTs together within one
amplifier, and this is of course intentional just to give you a confidence that you can mix
BJT as well as MOS in a, in your circuit. As long as you are following the fundamental
basic guidelines, then you can mix it properly.
So, here as I said that this RT, earlier we used to use RT, that has been replaced by this
device. In fact, if you see the device characteristic you may see that it is almost working
as one ideal current source but it may be having some finite conductance. And this
conductance sorry inverse of this conductance is basically ro1. Now, what is this current?
This DC current can be obtained by considering its base bias.
At the base we do have RB1 and that is connected to 12 V supply. And RB1 its value it is
given it is 570 kΩ. And if I consider VBE = 0.6 V then from that we can get, so IB1 =
= = 20 µA and then we do have β = 100. So, the corresponding
current here it is 2 mA.
Now since, the left branch and right branch they are identical and we do have equal DC
voltage coming there VINC, so we can say that in both the transistors IDS = 1 mA. And
again, this biasing condition it is such that we are retaining the output DC voltage, so we
do have 4 V drop across RD1 and RD2 and then we do have DC voltage of 8 V. So, we do
1101
have 4 V here. And now this current, this current is in fact it is more dependent on the
lower transistor rather than this voltage.
In fact it can be shown that even if say this voltage it is rising and hence this voltage it
may be rising, but since this transistor it is in active region of operation, its current it is
predominantly defined by its base current and the β. So, the tail current it is remaining
same as 2 mA. So, I should say the DC operating point here it is not really much
dependent on this voltage, unless we are making this voltage it is very small and forcing
the source node very low, pushing this transistor Q1 into saturation.
So, as long as that is, that is ensured, and then you can say that both this current and this
current they are remaining 1 mA. And to get that we can say that VINC if it is higher than,
let me clear to the board, so, we can say that the if VINC it is higher than the required 2 V
here and VCE is at 0.3 V, then we can say that the current here it will be 2 mA and current
here it will be 1 mA.
So, as long as VINC is higher than required 2 V to support 1 mA of current plus 0.3 V the
VCE(sat). So this is VCE(sat) and this is the required VGS to support IDS = 1 mA. Now, if this
VINC as I said it is higher and higher it will not create any problem. In fact, if this voltage
it is rising the voltage here it is still remaining at 8 V.
Of course, this is the lower limit of VINC, so likewise if this is 8 V the upper limit of VINC
on the other hand it can be obtained by considering the limiting case when transistor-1 it
is just entering into the triode region. So, when will it be in triode region? VINC(max) once
it is reaching to a value where this transistor it is entering into triode region from
saturation and that time this is 8 V and the corresponding voltage here it will be 1 V
higher than 8 V, that means this is 9 V.
So, VINC(max) it is 9 V. So, in summary what we can say that VINC, VINC it is having a nice
range, the upper limit it is 9 V and lower limit it is 2.3 V. Of course, this upper and lower
limit they depends on how we are setting this current and what is the value of this
resistance is and of course, to support this current what is the required VGS basically this
1102
part. So now, in this circuit at least we do have better definition of input common mode
range or better limit, strict limit of the input common mode voltage.
Now if we are keeping this VINC within this range as I said that the current is not
changing and so is the DC voltage it is not changing and also since the current flow here
it is remaining 1 mA the corresponding gm, gm it is also remaining very close to 2 mA/V,
and the corresponding gain it is remaining close to this 8. And in case if you are placing a
resistor here of course, the corresponding current depends on the VINC and hence, the
corresponding gm will also be changed and then of course, the corresponding differential
mode gain.
So, that is the advantage of having this active tail resistor, the biggest advantage of
having this tail resistor it is we yet to discuss is that the corresponding common mode
gain. In fact, let us try to see what the corresponding common mode gain is. So, to
calculate the common mode gain we know that the in the expression of common mode
gain we do have gm×RD and in the denominator we do have (1+2gmRT).
Now, while we do have this active device instead of passive element, what about the ro
we do have, that is playing the role of RT. Because if I consider its small signal equivalent
circuit out of this still current source, where this part is the DC and for DC of course, we
have to remove this part and then we will be having this ro1 it is left behind in the small
So, ro1 it is essentially playing the role of RT. So, it is now, it is now intuitive that
common mode gained it becomes ‒ gmRD, gm1 or gm2 both are same RD1 and RD2 they are
also same. And in the denominator we do have (1+2gmro1). And if you see its magnitude
ro1, so ro1 if I consider its early voltage of say 100 V and its current flow it is 2 mA, so
that gives us its ro1 = = 50 kΩ.
So, the value of this common mode gain it is equal to numerator part it is we already have
calculated 8 and the denominator part we do have (1 + 2 × (2 m) × 50 k). So, that is equal
to ‒ . So, we may approximate this by 200 so that is equal to, so that ≈ = ,
1103
which means that if we apply same signal, this differential and whatever the common
mode signal you do have as we have discussed earlier.
Let me consider this is 0.5 and 0.5 and there what we have seen is that the common mode
signal it was quite prominent, it may not be higher or equal to the differential part but at
least it was quite prominent. But by replacing this passive element by this active device
since, now we are getting common mode gain it is , so that gives us the voc = ‒
( ) V= ‒ 0.02 ( ) V.
On the other hand the differential part since, the differential mode gain it is remaining 8.
So Ad = gmRD so, that remains 8. So this differential part on the other hand it remains
same as what we have seen it is 4 V.
So, the differential part, vo_d on the other hand it is 8 × 0.5 ( ) V. So, then if I
combine and say this differential signal and common mode signal, since the common
mode signal it is very small compared to differential part then individual signal they will
be very close to fully complementary to each other.
So, we can say that vo1 ≈ 2 ( ) V. And vo2 ≈ ‒ 2 ( ) V. So, to summarize,
replacing this tail it is also helping to suppress this common mode part and still
maintaining the differential signal quite prominent, particularly if you observe the output
the, the signals there it is almost like complementary to each other.
1104
(Refer Slide Time: 1:00:45)
I think we do have covered whatever we have planned today. So as I say that the small
signal equivalent circuit and analysis those things it has been done in our previous
lectures and in today's lecture primarily we have focused on numerical examples, mainly
with extensive calculation on differential amplifier using BJT, for calculation of the
operating point then differential mode gain, common mode gain, then range of the VINC,
output showing and also we have seen that what are the different outputs are there and
same thing we have done quite an extent for the differential amplifier having MOSFET.
And then we also have discussed about the differential amplifier having both MOS and
BJT. Particularly what we have seen is that even though this differential amplifier its gain
it is not so high, differential gain it was only 8 in our example, but by replacing the tail
resistor RT by active device 1 NPN transistor, that helps us to really suppress the
unwanted common mode signal quite an extent, and ensuring that at the output we are
getting almost complementary signal. I think that is all to share. Thank you for listening.
1105
Prof. Pradip Mandal
Lecture-81
Current Mirror Circuits (Part- A)
So, dear students welcome back to our online certification course on an Analog
Electronic Circuits. Myself Pradip Mandal from E and EC Department of IIT Kharagpur
today’s topic of discussion it is Current Mirror Circuits.
So, according to our overall flow let we see where we are. In fact, we are in module 8.
So, we are in module-8 and presently we are in week-9. We are going to talk about
current mirror. In fact, this topic it is both it can be considered as building blocks in to be
more precise it is bias circuit.
And later on we will see that this building block it well be used in a circuit model. So, we
should see this topic it is starting with building blocks, but it is also having a scope to
enter into modules. Anyway, so, we are going to talk about the operating principles and
analysis of current meter. In the next lectures will be talking about application of current
mirror; specifically for amplifier and signal mirroring. So, the concepts will be going to
cover here it is.
1106
So, here we do have the enlisted items for today’s lecture. We shall start with motivation
and a need of current mirror. So, we shall start with whatever the circuit we have studied
where we have seen that current biasing elements it helps to improve circuit
performance.
And then we shall talk about what are the basic characteristic of a current biasing
element, then will be moving to another small discussion highlighting that what is the
need of current mirror. In fact, current mirror circuit not only it is useful for using as
biasing element, but it also can considered as a buffer circuit in current mode amplifier.
And then after that well be talking about basic structure of a current mirror. In fact,
before we entered into the basic structure, we shall talk about the evolution of the current
biasing element. And there will see that the evolution leads to current mirror circuit. And
then we shall learn on this current mirror. In fact, the current biasing element it consists
of a mirror pair and a current reference.
And subsequently well be talking about analysis of current mirror. And it is having
basically multiple items here; one is expression, deriving expression of current output
current of a current mirror. In terms it’s input current or reference current and also the
mirroring ratio. And we shall also talk about the output impedance of the current mirror
and we sell cover both BJT as well as MOSFET versions.
1107
And after talking about the basic current mirror circuit and its analysis, we shall talk
about the improvement of the basic current mirror to enhance performance. Specifically
for improvement of output resistance of the current mirror and there also we shall talk
about both BJT and MOS implementation.
We shall also talk about small signal model of current mirror and this is important to
when will be going for utilization or current mirror in current amplifier circuit. So, that is
the plan. Now, let us a go back and recapitulation what are the circuit, we have studied to
motivate ourselves that why we look for current by a single limit.
So, here we do have different amplifiers you can see, we do have a common source
amplifier, it is constructed by MOS transistor along with its bias resistor RD connected to
the supply voltage VDD. And this circuit it is having a gain small signal gain of gmRD if I
see the magnitude. So, that is the voltage gain and this gain it is not very high
particularly since the gm of the transistor it is not so high.
And this gain can be increased by increasing this resistance, but we cannot simply
increase this resistance. Instead what we have given a hint that, if we replace this passive
element by as an active device M2, which is offering say much higher resistance looking
into its gain. And as a result the voltage gain Av gets increased to gm(rds1 ⫽ rds2). So, that
gives us gm × .
1108
So, if we can replace this transistor this resistored by a transistor then we can get higher
gain. However, if you see we do have this transistor it is having a bias and instead of
having this bias, if we use current mirror that makes the circuits more practical more
robust against process variation or supply variation. So, that gives us an indication that if
we use some current mirror circuit here, then we can enhance the gain. And instead of
having single transistor here we can use a current mirror along with it current reference
circuit.
Now, a similar to the common source amplifier here we do have common emitter
amplifier here again the load resistance RC; it restricts the gain to gmRC and so, that is the
voltage gain. So, this gain again it can be enhanced by replacing the passive element by
one active element here. So, though in this circuit this transistor-2, it is having a typical
bias current bias, but of course, this circuit it is sensitive to temperature and β variation.
So, in terms of getting the bias point stability of this circuit, it may be recommended to
use a current mirror instead of having simple Q2 here.
So, likewise if you consider a say a common collector stage CC-stage or say common
drain stage, where at the for common collector stage at the emitter we prefer to use one
current source. And we want this current source it should be almost independent of this
output voltage. So, if it is independent of this out voltage output voltage then the
performance of this circuit is more towards ideal one.
1109
In other words, this RL if it is higher that gives us the circuit performance better; same
thing for a common drain amplifier. So, if this RL it is higher that gives the performance
of the circuit more towards the ideal situation. So, here once again if we have some
implementation of this by a circuit, definitely we can get performance of both common
collector and common drain more towards its ideal performance.
So, here again we are landing into a situation that we need the biasing element should be
preferably it should be a current source or we can say that it is a current biasing
eliminate. So, here we are looking for current biasing element, here also we are looking
for current biasing element similarly for these two circuits also.
So, likewise if you consider differential amplifier differential amplifier, here again there
is a need of there is a need of biasing element here. If you put a passive resistor here, that
makes the common mode gain magnitude of the common mode gain equals to RC. In this
case , we want this gain should be as small as possible ideally it should be going to 0.
Now, here again this equation suggest that if this RT it is higher then we can make it
better circuit; namely the common mode gain we can make it lower. But, then if you
increase this RT to support required equation current, you may require much higher drop
across these resistrants. So, just by replacing this passive element by one high resistive
elements or high resistrants, it will not solve the problem. Instead if you replace this
element by a current source like this, then definitely this resistance we can make it a high
on the other hand this DC current it may support the required equation current in the
circuit.
So, same thing this true for this different cell amplifier also they are also the current
common mode gain can be increased. And for this case the common mode gain it is a
. So, if we replace this element by bias circuit and if we make these resistrants higher
and higher, then definitely we can improve the circuit performance.
In fact, in this circuit we can improve the circuit performance by replacing its load also.
So, we same thing here also because the different cell mode gain it is gm into that load
resistance. So, similar to common emitter or common source amplifier, we are as we are
replacing this passive element by active element to increase the gain.
1110
So, for this different cell amplifier also if we replace these load resistors by current
source, then we can improve the different cell mode gain which is having an expiration
of gmRD. So, gmRD in this case and in this in the BJT version it is different cell mode gain
it is gmRC ok.
So, at least we understand that there is a need of current biasing element, across different
amplifier and then of course, whenever you are talking about of current biasing element.
Let us try to see what are the basic characteristics we are looking for this bias current
biasing element.
So, here we are highlighting what are the basic characteristics required for current
biasing element. First of all the output impedance should be high what does it mean is
that, suppose we have say this element whatever the current biasing element and it is
having a current flow and then, we do have some application circuit. So, we call this is
current biasing elements and this is the application circuit.
Now, we want this current should be well defined by this biasing element; see let we call
this is IBias. And we want this IBias should be as independent as possible on the voltage
across this we may call this is VBias. So, that is what we want to say that if this IBias it is
independent of this voltage, which means that if we plot the I-V characteristic of this
biasing element IBias versus VBias. And we want theoretically it should be independent
which means it is horizontal line.
1111
In other words, we may say that the slope of this line slope of this line it is zero slope is
quote and unquote 0. Or we want resistance you can see output resistance is quote and
unquote ∞; practically we want it should be as high as possible. So, if we can achieve
what we will get it is that, in case these applications circuit it is defining the voltage at
this point.
So, then even though this voltage it may vary based on the application circuit
requirement. But if we ensure that this IBias it is independent of this VBias then we can say
that this bias current of the application circuit it is not getting changed by this voltage
variation. So, that is one of the basic requirements. So, this is the first characteristic we
will be looking for. So, while will be implementing the biasing element we have to pay
good attention to that.
Then second characteristic we are looking for it is the current should be well defined. So,
this IBias should be flowing through this current biasing element, should be well defined;
namely IBias should be easy to implement. And important thing is that variation its
variation with respect to whatever the design value. We do have should be as small as
possible not only its static value, but even say instant inverse value should be as less
dependent on any other variation namely temperature variation or supply variation.
So, we want this current should be a well defined along with this characteristic, the
variation should be less or uncertainty of this current bias should be as small as possible.
Then the third characteristic we are looking for it is that this circuit should be operating
with available supply voltage, which means that suppose we do have supply voltage here
it is say VDD and then we do have ground here.
So, we want this circuit the bias circuit should not be taking too much of this supply reel
keeping behind large amount of voltage drop for the application circuit. So, we want this
current bias circuit should be operating with a less amount of voltage VBias across it. So,
that is what we said that minimum required voltage across this bias circuit should be as
small as possible ok. So, while will be implementing this current bias circuit, we have to
pay to this three basic requirements.
1112
Now, let us see that the basic ok. So, this is the additional information I like to mention
that, this current mirror can also be used for current mode amplifier. In fact, this is also
recapitulation for us that we have seen if we require one circuit basically one current
mode amplifier. If we want to cascade it with another current mode amplifier and the
impedance of the previous stage and the next stage if they are not well match. And then
if the moment we cascade it may create some loading effect and that may degrade the
overall performance of the circuit.
So, what we may require we can place one circuit in between, which supposed to be
working as a buffer and this is the model of that buffer. So, this is the model of the buffer
here we do have and the input current it is iin_buffer. So, this is the internal circuit of on
that buffer.
So, it is having input signal it is iin_buffer and then output signal here it is primarily iout or
iout_buffer. And this iout_buffer ideally it should be equal to a gain times whatever the input
current we do have. And we want the input impedance of this circuit, it should be as low
as possible on the other hand the output resistance which is Ro_buffer it should be as high
as possible.
So, for current mode buffer we are looking for this input resistance should be as low as
possible and output resistance should be as high as possible. So, that the buffer output
current it hardly depends on the output voltage; likewise if the input resistance it is input
1113
resistance here it is small. Then while we are feeding the current while we are feeding
the signal here it should not really depends on whatever the source resistance we do
have. So, if this resistance is small, then entire current it will be getting into the buffer.
And the current gain we may not require much, but at least we should say that
attenuation should not be very high. So, even if it is a approximately one that was ok.
And this three basic characteristic for current mode buffer leads to the spatial
configurations called common base and common gate configuration, based on whether it
is implemented in BJT or MOSFET.
So, this is what we have discussed earlier in one of our lecture. And what we are why we
are talking this information here is that, current mirror the circuit will be going to discuss
today. The current mirror circuit can also work as current mode buffer, which means that
the current mirror it is having input impedance low. And also the output resistance it is
high and the current gain not only it will be one. In fact, the current gain it can be even
higher than 1 ok. So, that is why I said that, in the second item is that the current mirror it
also works as current amplifier.
So, this is an indication that current mirror circuits it is having important role to play,
even for current mode amplifier particularly current mode buffer and as current amplifier
right. So, that is the motivation of going for this current mirror and current biasing
element.
1114
So, let us see the implementation what are the possible implementation we do have. First
of all before we talk about the implementation we need to recall the basic characteristic
required for this current biasing element. So, here we are enlisting different versions of
current mirror or other current biasing element I should not say current mirror it is
current biasing element. So, 1st versions, 2nd versions and then we also have 3rd versions.
So first one it is the simple resistor. So, simple resistor and this bubble indicate that we
do have the application circuit connected here. So, we do have the application circuits
and, we want the current here it should be well defined. And we also want as we said that
it should be well defined the output resistance here it should be high and also we want
and that drop across this resistance should be as low as possible.
Now, if you see this basic requirement wise this version it is not. So, good first of all
output resistance it is defined by this resistance itself. And the drop across this resistance
if we want it should be as small as possible, and then this requirement and this
requirement they are conflicting. But based on some restricted application, if we have
sufficient amount of headroom across this biasing element available probably we can use
this circuit also; but I should say that if we have better option we may go for that.
Now, if you consider the 2nd version, we do have a say one BJT or maybe a MOS
transistor in MOS transistor, having a meaningful bias here as VBE or VGS. And suppose
this transistor it is in active region of operation or if this is the MOS transistor if it is in
saturation region. And then if we have the application circuit connected. So, we do have
the application circuit here connected, same thing here also we do have the application
circuit connected and suppose this application circuit they are defining this voltage and
this voltage.
Now, the current flow through this transistor, if it is in active region we know that it is
having very low dependency on the VCE voltage. Same thing for this transistor also the
IDS current here, it is having very low dependency on the voltage across this element
namely VDS.
So, if I plot this IC versus VCE or if I plot the IDS or ID versus VDS. If they are in
appropriate region of operation we know that the character characteristic it will be quite
horizontal or flat. Indicating that it is having good high output impedance. And the
1115
minimum required voltage for this case it is VCE(sat) and for this case it is VD(sat) typically
VCE(sat), it is quite low it is around 0.2 or 0.3 V.
On the other hand VD(sat) it depends on the VGS. So, that is VGS ‒ Vth. So, it depends on
what is the VGS we are applying. But we can see that the minimum voltage we require
across this transistor. To keep the transistor in appropriate region of operation it is much
lower than what we are expecting for simple resistor.
So, definitely then the second version is better or I should say superior uh, but still there
is a possibility of improvement. Say for example, if you are in this case if you really have
to make a precision voltage here to make well defined collector current it may be
impractical.
In fact even if you are considering that this VBE it is not or well defined. But based on the
temperature variation characteristic of this transistor it may vary. And due to that we may
have altogether lot of uncertainties in the collector current. So, I should say the second
version, it is satisfying first and third requirement, but not the second one. Second
requirement where we are looking for uncertainty in the current value it should be as
small as possible.
So, we do have now 3rd version or 3rd generation. Here instead of having DC voltage we
can put some bias resistor connected to supply voltage. And then we can have the
application circuit that may also be connected to the same supply voltage. So, based on
this RB and VCC and VBE we do have IB flowing and this IB in turn it is defining the IC
which βIB right.
So, the current flow here of course, it can be well defined by this resistor. So, it is in fact,
it is much better to define this current, but still it is a strong function of this parameters
particularly the βof the transistor. So, even if say IB it is remaining constant, but if the β
is changing whether due to replacement of transistor or due to temperature variation
then; obviously, this current it will be getting change.
So, likewise here we do have the MOSFET version which is of course, at the gate we do
have voltage bias. And we do have potential divider R1, R2 which is generating gate
voltage from DC supply VDD. And then it is producing a current here based on whatever
the VGS we are applying and whatever the dimension we do have and whatever the K′n
1116
we do have right. Keeping the transistor in saturation we can get this current it is
( ) ( ).
Assuming this ( ) part it is very small similar to in this case if you consider early
voltage it is high. So, in this case we can say that current is well defined, but again as I
said that for this circuit also the current it is definitely, it depends on the device
parameter it also depends on threshold voltage of the device. So, that makes
uncertainty of this current also significant.
So, I should say that third version definitely it is much better than the previous two, but
still there is a scope to improve the current bias element. Namely to make the current
more independent of the you know process variation or supply variation or temperature
variation. In fact, that leads to the requirement of current mirror. So, the fourth version or
fourth generation of current biasing element is basically a current reference along with a
current mirror.
So, here is the basic structure of the fourth version of the current biasing circuit. Now,
suppose we do have say two transistors; transistor-1 and transistor-2 and the transistor-1,
it is say diode connected, namely its gate it is connected to drain. And let we flow one
current call say I reference maybe that is coming from the supply voltage. And let you
assume that this current reference is given to us and try to see how this current mirror
1117
constructed by M1 and M2; it is helping us to define this current here which is a primarily
function of this current or this reference current.
Here of course, we do have the application circuit and that application circuit it is
connected to VDD. And here we do have the voltage across this transistor we may call
this is VDS2. So, as long as this transistor-2 it is in a saturation region, then we can say
that IDS it is which is IDS of transistor-2 in this case that is I2 which is in fact, the bias
current for the application circuit, which is quote and unquote independent of VDS.
So, as long as the device it is in saturation region depending on the value of λ, we can
say that the dependency of this current is very small. Of course, if the VDS is very small
going beyond the pushing the transistor beyond saturation region then there will be lot of
dependency.
So, as long as the VDS is higher than this VD(sat) then we can say that it is a good current
biasing element. So, how it what is the. So, this is the structure and how it works? Based
on this current and based on its dimension, it produces a voltage called VGS1 and the
same VGS we are deploying to transistor-2. So, instead of having independent potential
divider. We are generating a voltage at this point for transistor-2 or gate bias of
transistor-2, which is also having a term this VGS1, it is having a term called Vth plus
some additional element called Δ VGS.
So, this voltage since it is having Vth inherent within it then whatever the on the voltage
we are generating here it is having this Vth. So, if I take VGS2 ‒ Vth definitely this Vth and
VGS2 it is VGS1, which is again it is having Vth term plus Δ VGS1 and then we do have the
second Vth.
So, this Vth and this Vth it is getting cancel making this current mirror making this the
current flow through transistor-2. It is independent quote and unquote independent of the
threshold voltage of the invertor. Of course, here we are assuming that this Vth1. So, this
is for transistor-1 and this is for transistor-2.
So we are assuming Vth of the both the transistor they are equal. So, that we have to that
we can we can assume that. And in fact, that is a fair assumption particularly for
integrated circuit that is it is not so difficult we achieve. On the other hand, whatever the
1118
voltage you do have here, it is also having one term , which is of course, it is so, of
transistor-1.
And so, likewise here whenever we do have the expiration of this current in terms of W
and L. So, they are also will be having and then . So, this part we do have . In
fact, this part it is having in the denominator and that and this they do get cancel
each other.
So, that makes these current not only independent of threshold voltage, but also
independent of the process parameter. So, if I assume again this it is a of
transistor-1 and this it is of transistor-2. So, again we are assuming of both the
devices are identical and that is again it is not difficult to achieve. And that makes this
current that makes this current mirror a very suitable candidate to make the biasing
elements satisfying this particularly the second condition.
And transistor-2 anyway it is satisfying the first and the third condition, we have seen in
the third generation of the biasing circuit. So, in summary I should say this is a good
current biasing element. But the natural question is that we are looking for of course, we
have to have this current reference to make this circuit working.
But I must say for all practical purposes this reference current need not be a very very
fancy or very idealistic current references.
1119
Even if you have a primitive current source, say for example, if you have a simple
resistor connected that will also serve the purpose. Because in this case drop across this
transistor it is not so big living behind a big amount of a voltage drop available across
this resistrants.
So, though the application circuit is sitting here and that may require a much higher
voltage drop across it; but the drop across this resistance we do it is not getting affected
by whatever the requirement of this voltage you do have. So, even a simple resistor it
may work for providing this I reference. So, I can say that this circuit it is 4th generation
of current biasing element which is utilizing 1st generation or 1st version of the current
reference.
So, by combining this 1st version and this 4th version and namely the current mirror we
are getting a good current biasing element. In case if we have a better option we can go
for a current reference. In fact, why we go for current reference.
And then we generate another current reference, the logic is if you have only one current
reference, which is generating 1 voltage here for transistor-2, that can also be reused to
make another current bias. Say you do have transistor-3, that may be connected to
another application circuit. So, this application circuit it is different from this one. So,
this is application circuit-2 this is application circuit-1.
1120
So, this application and this application circuit all together they are different. But as long
as we ensure that M2, M3 and M1 they are similar in nature, then we can say that this
current I3 it is also satisfying all these conditions and so, this I3 it can be obtained from
the same reference current. In fact, you can generate n number of such kind of current
reference.
So, if you have one good current reference from that you can have many more current
references you can generate right. So, that is why; that is why we are using current
mirror. So, we do have one current mirror here we do have these two together making
another current mirror and so and so.
So, this is MOSFET version current mirror. And we can have a BJT counterpart. So, in
the next slide we are having the current reference here. So, you can see here it is very
similar this circuit is very similar only thing is that we do have Q1 and Q2 instead of M1
and M2. The here also the collector and base they are connected to make transistor-1
diode connected. And rest of the thing it is very similar and this circuit. Of course, it
offers this basic characteristic.
We will be discussing about its analyzes, but before that let me take a short break.
Thank you.
1121
Prof. Pradip Mandal
Lecture – 82
Current Mirror Circuits (Part-B)
So dear students, so welcome back after the break. So, we are talking about the basic
structure of current mirror both BJT and MOSFET versions. And now we are going to
discuss more detail about the expression of the output current and output resistance of
those current mirrors.
1122
So, to start with the analysis of current mirror we do have here, the circuit which is, as I
said that it is having a reference current, Iref and then we do have transistor-1 here which
is diode connected and it develops a voltage VGS which is supplied to the get to source or
transistor-2.
And then transistor-2, it is connected to the application here. So, this is the application
circuit and we like to get the expression of the current I2. In terms of the reference
current or you can say this I1 and then the size ratio of M1 and M2. Now to start with, we
do have the expression of the current I1.
1123
So expression of this current I1 which is given here. Incidentally, that is also equals to Iref
and expression of this current assuming transistor it is in saturation. In fact, this transistor
it is in saturation because its drain and gate they are connected together.
And its expression is given here, of the transistor and typically, in text book it is
referred as ; so, that is the eternals conductance parameter. And then that multiplied by
VGS ‒ Vth of the transistor square and then we do have ( ) of the transistor.
So likewise, we also have the expression of current for the transistor-2. So we do have
current here, it is also having very similar expression and because of the connection here,
we do have both the VGS’s, they are equal namely VGS1 and VGS2, they are equal.
And also, we do have the threshold voltage here and here if we consider they are equal
namely, Vth1 = Vth2. Then, by taking ratio of these 2 currents what we are getting is the
expression of the current I2 in terms of the reference current and then .
So that is the ratio of aspect ratio of the 2 transistors. And then we also have
( )
( )
.
Now, we can approximate this part; in terms of ( ) difference assuming, λ1 = λ2.

And also, we are ignoring the term associated with λ2. So, if you consider λ1 = λ2 = λ,
1124
and if we ignore the second-order term associated with this λ. So if we drop this term,
then we do get this approximated expression of current flowing through transistor-2.
Incidentally, that is also defining the current through the application circuit. Now, this
part it is defined by the aspect ratio of the 2 transistors and also the reference current.
And let me denote that by , just to indicate that is the main part or nominal part of this
I2 current. And then we also have the additional term λ( ).
So, we can write this expression in this form, + . Where rds this rds2, it is
defined as . In fact, this is the rds of this transistor.
So, we can say that if the voltage here and voltage here namely, the drain voltage of the
two transistors they are equal. So, that makes this part equal to 0 and hence, the I2 it is
nothing but .
So, we can say that is it is the current of transistor-2 when the 2 drain voltages they are
equal. Now in case, as I said that the voltage here it will be defined by the application.
And in case, if this voltage or drain voltage of transistor-2 it is different from drain
voltage of transistor-1, then we will be getting this additional part of this current.
In fact, if you plot the IDS2 or you can say I2 versus VDS2 and if VDS = VDS1; VDS2 = VDS1,
at this point whatever the current we are getting that is . And then if VDS2, it is different
from VDS1, say this is higher, so based on the resistance, the current it will be having
additional component.
So, we can say that finite dependency of the I2 current on VDS2 is getting captured by the
second term. In fact, that is well characterized by this rds. So this additional part whatever
the additional current we do have, that is getting represented by the second term. In fact,
this VDS2 it can be even lower than VDS1 by almost threshold amount. So, we will discuss
that in the next slide.
1125
So, in summary what you are saying is that the expression of the expression of the
application circuit current or I2 it is given by its nominal value multiplied by a plus the
additional component which is defined by the rds. In fact, if you see this expression this
part is the . So, this = {1+ λ ( )}.
So the expression of this current, based on our situation either we may consider this
expression this expression whole expression or it may be in this form. So in this form, if
you see here, in this form we do have nominal current plus the additional current.
Whereas, in this form we do have the nominal current multiplied by a factor this is
referred as non-ideality factor.
So whenever, we will be talking about non-ideality factor is essentially that is 1 plus this
additional component. Of course, this VDS2 if it is higher than VDS1 then this will be +ve;
otherwise, it will be ‒ve. So that is the expression of the output current. If I say that this
is the output of the current mirror.
And of course, it depends on the condition of this transistor. Particularly, the VDS of this
transistor. If this VDS it is sufficiently high, keeping this transistor-2 it is in saturation,
then only we can get this non-ideality factor it will be small. So, it can be and as long as
it is in saturation, its dependency as I said that it can be characterized by this rds which is
also referred as output resistance Rout.
1126
So the expression of Rout, of this current mirror is which is same as in this case
incidentally, this is same as rds2 and that = . So, we get this resistance it is high only
when as I said that transistor it is in saturation and to do so, we require the VDS to be
sufficiently high. Namely, it should be higher than its VGS2 and VGS1 both are same ‒ Vth.
So as long as we do satisfy this condition, then we are getting this output resistance. So,
we need to maintain this minimum voltage across this element to get this advantage
namely, this resistance it is high and if this resistance it is high, this part it will be small
or you can say that non-ideality factor it will be small. So, similar to this current mirror,
similar to the current mirror using MOSFET, let me consider the current mirror using
BJT transistor.
So there also, so, here is the circuit. So there also we can first we can derive the
expression of the output current namely, this current, I2 current. In fact, I2 it is the
collector current of transistor-2 IC2. And also, here we do have collector current IC1. And
then this IC1 and Iref they do have a dependent relationship. But, we need to say that this
IC1 it is not exactly equal to Iref because we do have some base current is flowing for
transistor-2 as well as transistor-1.
1127
So, we do have IB1 and IB2. But before that if you write the expression of the collector
current of transistor-1 and transistor-2 in terms of VBE the common VBE voltage and the
corresponding VCE, VCE1 here and then here we do have VCE2.
Assuming that both the devices are in active region of operation we do get similar kind
of expression for IC1 which is saturation current or reverse saturation current ×

( ) of the transistor.
So same thing, we do have the expression of collector current for transistor-2. Now as I
said that if I consider this both the VBE’s are same and non-ideality factors are = 1 or
maybe even equal, then we can take the ratio of this current and this current where this
VBE part or part is getting cancelled. And that gives us the expression of IC2 in terms
of IC1 and also in terms of the reverse saturation current of the 2nd transistor; .
And in addition to that, depending on the VCE voltage, we do have this factor in the
numerator and also in the denominator. Similar to the previous current mirror, here this
factor it can be approximated assuming that of course, VA1 = VA2. And if we consider, if
we denote that as VA then we can write in this form, assuming then here also this
approximation involves that term we have dropped.
So, if I consider, if we ignore the second order terms of then, we do get this
approximation. And in this approximation what we have it is this factor, the main factor
multiplied by 1 plus sorry this should be VCE. VCE2 ‒ VCE1. So, in case if this VCE of the 2
transistors they are equal, again this part it will be = 0.
But if they are different then we will get a value and this additional component of course,
it depends on the value of this early voltage. Typically, this early voltage it is very high
and we may assume that the IC2, it is approximately equal to this one.
So, dropping this part dropping even part. So, we can say that IC2 ≈ × IC1. Now, if
you see here, the expression of this current it is primarily depends on (whatever the
collector current we do have here) × (the ratio of their reverse saturation current).
1128
So we can say that whatever the current we do have, it seems that is getting reflected
here or getting mirrored there by the mirror ratio of . In fact, in the previous current
mirror the mirroring ratio it was .
So, that was the mirroring ratio for MOSFET current mirror. Whereas, for this case the
ratio mirroring ratio of the BJT was version it is defined by the reverse saturation
current. In fact, geometrically if we see the or dependency of this IS on the geometry of
the transistor, this ratio it is I should say emitter to base junction area ratio. Anyway,
since this current it is getting mirrored here, that is why the name suggests that it is
mirroring the current based on their aspect ratio or emitter area in ratio.
Now this in this circuit, as I say that the IC1 ≠ Iref because we do have we do have the 2
base currents IB1 and IB2. So, let us try to write the expression of IC1 in terms of Iref. This
is VCE2 and this is VCE1, as I said.
So, now if I at this node if I consider the KCL, we do have Iref = (the collector current of
transistor-1 + 2 base currents). So now, these 2 base currents again, it can we say this
current it can be expressed in terms of its collector current namely, of the transistor.
So, same thing for the second transistor of the transistor.
1129
And then if I consider this relationship, IC2 can be well approximated by this × IC1. So,
from that if we replace this IC2 in terms of IC1, then we do get relationship between Iref
and then IC’s. So, we can say that Iref = IC1 { }.
So now, we do have the so far we do have I2; IC2 expression in terms of IC1 and then
expression of IC1 can be placed here namely, Iref divided by this factor to get the current
final current in terms of the reference current. So, in the next slide we will be doing that.
So here, what we said is that the expression of IC2, it is primarily we do have this factor
and then we do have whatever, non-ideality factor and then Iref and IC1 is having this
relationship. So, by plugging in the expression of IC1 into this equation what you are
getting is, the final expression of IC2 which is the ratio of the reverse saturation current
multiplied by this reference current multiplied by 1 divided by this factor, and also we do
have this factor.
Again, I have repeated this mistake sorry for that. This should be IC2 sorry, VCE2 ‒ VCE1.
So same thing here also this is VCE2 ‒ VCE1. So now, if the situation it is ideal namely, if
the β is very high say this β and this β if they are very high and also, if this early voltage
it is very high then we can say that IC2, it is well approximated by × Iref.
1130
So, the rest of the part of the expression this part we can say, it is non-ideality factors. It
is having 2 factor, one is due to the early voltage, another one is due to the finite value of
the β or whatever you say the current loss here due to the base bias. Now this similar to
the previous current meter, we can also write this dependency part as in terms of output
resistance and this part we can say that loss due to β.
We can say that in case, if we get higher output resistance or higher value of this early
voltage then this factor it will be getting improvised or this factor it will be going
towards 1. On the other hand, but then this factor it will be still it whatever its value it is
there it is in fact, less than 1 whereas, this factor it is mostly it is more than 1.
Now, this factor can be taken care differently. So, we may have 2 possible options to
improve this circuit. One is to increase the output resistance or increasing this factor:
non-ideality factor, other one it is improving this factor. Now, coming to this factor or
the effect due to the output resistance, this output resistance can be expressed. In fact, we
can rewrite this equation in terms of output resistance.
Probably, in the next slide I do have that, let me see. So here we can rewrite the
expression, we can rewrite the expression of I2; IC2. So, we can say that this part let me
consider this part it is .
1131
So, if I say that this is then, we do have here multiplied by this factor. Again, I
have repeated this mistake, sorry for that; VCE2 ‒ VCE1. Now this part can be expressed in
terms of this where this ro2 = . In fact, that is the collector to emitter
resistance of the transistor-2. So, I should say this is collector to emitter resistance of Q2.
So if this output resistance it is higher, maybe that can be obtained by a higher value of
this early voltage, then you can say that this non-ideal part, it will be smaller. So, we may
wish to keep the transistor in active region so that we can get the output resistance high.
And as I said that this output resistance it is essentially ro2. So, we can say this Rout = this
ro2 which is having this expression.
Now, we can get high value of this output resistance which we are looking for only if we
assume that the transistor it is in active region of operation. And to get that, we require
minimum voltage across this transistor. So, that is the VCE. So, we can say that the
VCE_min we require it should be higher than VCE(sat). And that is the voltage here, voltage
across this element we call it is maybe V2.
So, this is the voltage here. So, we can see the voltage across this current mirror, it
should be at least this VCE(sat). Typically, its value it is 0.3 V. So, that may not be a
difficult one. So, the application circuit after deducting this minimum VCE(sat), application
circuit it will be having a very good possible range for its own operation. So, that way
you can say that this circuit is good.
1132
Now for both the current mirrors as I said that there are non-ideality factors and let us try
to see how those factors can be reduced or how we can enhance the circuit performance.
So if I consider say, a simple current mirror as it is given here and we like to enhance the
circuit performance; when I say enhance, we like to increase the circuit by increasing its
output resistance.
So, to increase the output resistance what you can do we can place one transistor at this
point, to get the modified circuit like this. So, M1 and its connection remaining the same,
we do have Iref here, connected to supply voltage and then we can have M2. And then we
do have the application circuit here, but in between we like to place one transistor.
Keeping of course, both the transistors if I call say transistor-3, and this is M2 and we
like to keep a meaningful DC voltage here so that this transistor; when I say meaningful,
DC voltage it is such that this transistor this voltage it is sufficiently high, keeping
transistor-2 in saturation. And of course, on top of this, we do have the application
circuit. So whatever the application circuit we do have, we do have the circuit.
Now, by adding this transistor what we can say intuitively, even if say, this voltage in
this case it is changing, if I call now say VO even if I change this voltage, maybe that is
done by this application circuit, this voltage hardly it varies. Of course, I am assuming
that all the devices are in saturation region.
1133
So, based on the gate bias, VBias and the current flow here and the size here the VGS of
this transistor-3 it is set there. So, the voltage coming here, it is essentially VBias ‒ VGS of
transistor-3. And this VGS of Transistor-3, it hardly depends on the output voltage.
As a result, even if say this voltage it is changing, even if this voltage it is changing, as
long as transistor-3, it is in saturation this voltage it is not changing. So, we can say it is
remaining almost constant. As a result, we can say that VDS of this transistor, it is
independent of I should say quote and unquote of the output voltage.
( )
So, that makes the expression whatever, I2 which is . Now, this
( )
expression of course, remaining same, but then by adding this transistor compared to the
simple current mirror. What we are doing is, even if you vary this output voltage the
VDS2 it is quote and unquote unchanged.
Or you can say that this current it is it hardly depends on this voltage here. So pictorially,
if I compare the 2 cases, the simple current mirror based on probably finite λ, we do have
this output current and the voltage dependency it is having a slope. So, let you call this is
output current. So, this is the output current and the voltage drop across this one is say
VO output voltage.
Now, if I consider on the other hand, on this circuit where we do have transistor-3, it is
protecting this source voltage from the variation from the output voltage and for that, we
do have the corresponding current it is almost remaining flat. So, this is with transistor-3.
And on the other hand, this is simple one without M3.
So in fact, if you see the waveform, you can see that this is giving us higher output
resistance or less dependency of the current on output voltage. So, indicating that Rout is
very high. And at least compared to this one it is very high. So, let us try to see why we
call it is very high?
In fact, if you see the output resistance looking into the output port here, the output
resistance it is basically it is a cascode structure and we have derived the output
resistance of the cascode structure which is giving us say Rout = rds2 + rds3 + gm3rds2rds3.
So, because of this additional this factor, this output resistance it is much higher than this
case where this case the output resistance it is it was. So, this is much much higher than
1134
rds2, which is Rout of the simple one, simple current mirror. And this is the output
resistance of the modified one. Since you are placing this transistor in the form of
cascode, this circuit is referred as cascode current mirror.
And as I said that main advantage here it is that we are getting output resistance it is very
high. As a result, the output current it hardly depends on the output voltage here or
whatever the application circuit current it can be well defined by this ratio. Basically,
from this one we can get the current which is independent of this output voltage.
The practical circuit, it is having slight modification instead of having independent bias
here, we prefer to have that bias free so we can place one more transistor in diode
connected form in the left branch to create a bias for transistor-3. So, we can have the left
branch like this. So, this is M1 which is biasing M2 here and then we do have M3 here,
M3 it is getting biased from this fourth transistor which is also diode connected. And of
course, on top of this one we do have the application circuit.
So, this is rather very common circuit. Only advantage only disadvantage of this circuit
over the simple current mirror is apart from requiring more transistor, the minimum
required voltage over which we can maintain this constant current it will be higher for
the for the cascade cascode current mirror, compared to minimum required voltage for
the simple current mirror.
1135
So, in the same way if you consider the BJT version, so there also we do have the
possibility of improving the output impedance by the means of cascode structure; and
here again, the purpose to a have cascode it is to improve the output resistance and as
you can guess, that we do add one extra transistor on top of this Q2. So, let you call this
is Q3.
We may have a meaningful voltage here, when I say meaningful voltage, it is basically
what you are saying is that the voltage here it should be such that transistor-2 it is in
active region of operation. We do have Iref then, this is connected to Vdd and then we do
have the application circuit here.
So, this is the application circuit and this is the output voltage, this is the current flowing
through this circuit. So, for this circuit again, if you analyze it can be said that this output
voltage it is having hardly any influence on this voltage or it is having hardly any
influence on the VCE2 voltage.
As a result, the current flow through this transistor or the final current, it hardly depends
on this output voltage or you can say that the output resistance it is in this case, output
resistance looking into the collector, it is much higher than the output resistance of this
circuit. In fact, if I consider this structure which is referred as the cascode current mirror,
as you can guess this output resistance of the cascode circuit, it = ro2 ⫽ rpi3.
And then we do have ro3 + gm3ro3(ro2⫽rπ3). In fact, this can be well approximated by this
rπ3 here. And so, we can say this is ro3 + (ro2⫽rπ3).
And this part gm and this one we can see it is β3ro3. This is much much higher than ro2,
which is the output resistance of the simple current mirror. So compared to simple
current mirror, the corresponding output resistance it is much higher.
And if you observe the variation or dependency of the output current for the 2 cases
namely, a simple current mirror and cascode current mirror, on the output voltage VO.
For simple current mirror, based on the early voltage, it may be having significant
dependency, whereas, for this case for this case the dependency it will be much smaller.
So, this is with Q3 and this is without Q3. And the practical circuit practical circuit for
this cascode current mirror similar to BJT, here we use one more transistor in the left
1136
branch to create a bias for transistor-3. And then of course, we do have the below
transistor and then we do have the Q2. This is Q1, this is Q3, this is Q4 and then we do
have the reference current here. And of course, we do have the application circuit, it is
here.
Now, this is this is I should say more practical circuit. Now if I compare the 2 circuits,
definitely I am getting higher resistance in this case. But the only drawback here it is the
minimum required voltage to get this benefit it is higher namely, for this case we require
one VCE or rather VCE(sat).
So, minimum required voltage = VCE(sat) here or transistor-3 plus this voltage. And in
fact, that voltage if I go through this loop, it can be shown that this voltage and this
voltage they are equal. So, that is one VBE(on). Whereas for this simple current mirror, the
minimum required voltage here it was only VCE(sat). So, that is the only you know
limitation. So, we do have a requirement here it is VCE(sat) + VBE(on).
Whereas, for the other circuit for this circuit we require only VCE(sat), VCE(sat) of
transistor-2. So, that is how we can increase the output resistance and we can get the less
dependency of the output current on the output voltage.
So the other factor, other non-ideality factor, namely, dependency on β you may recall
that in the expression of the final current, particularly, for the BJT based circuit there are
1137
some loss of the reference current because, it is supplying the IB here and IB here and the
relationship of Iref with IC1, it was Iref = IC1 { }. This is the case for the
simple current mirror.
Now, to avoid this loss or to reduce this loss, what we can do? We can place one
transistor here, we can place one transistor here, which may work as current amplifier
which is referred as Beta-helper circuit. So, the circuit is like this. We do have the
reference current then we do have lower one, the Q1 and also the Q2.
Similar to the previous case Q1 and Q2, but in addition to that, we do have one extra
transistor which is increasing this current here. So, if the base current here it is say, IB1
and this is IB2 which is emitter current of this transistor. So, let me call this is transistor-5
and IE of transistor-5, it is summation of this 2 current.
So, the current at the base of this transistor it is ah, I can say this is IB5. And IB5 = .
So, we can say that by adding this extra transistor, the loss of this current loss of this
reference current; if I say that is the loss, then that is getting reduced by this factor. As a
result, the relationship between Iref and IC1, instead of this equation, in this part, you will
get a factor which is (1 + β5).
So, this is the corresponding relationship. Iref = IC1 multiplied by this factor and then this
part. So, what is its consequence? The final expression of this I2 or IC2, if I say this is the
IC2 and then we do have the application circuit here. And so, it is having × Iref and
then this factor, we can see it is getting improvised by adding this (1 + β5). And this part
however, it is remaining as is once again, sorry, this would be VCE2 ‒ VCE1.
So this part, we already have discussed to improve this one we can put the cascode
structure. In addition, we can put this transistor to make this non-ideality factor very very
close to 1. So, this is referred as Beta-helper circuit by the β of this transistor we are
making this factor more towards the ideal one. So, that is why it is referred as Beta-
helper circuit.
So, that is the expression of the final current, whatever you see, IO or I2. I think these are
the two possible way of improving the circuit and by doing this, as I said that non-
1138
ideality factor it is going close to 1. In other words, Beta-helper circuit it increases the
accuracy of the current.
Now to summarize, what are the things we have discussed in this lecture, we have started
with motivation of going for current mirror namely, to implement current biasing
element in amplifier, we require the current mirror. And we also have discussed about
basic characteristic namely, output impedance of the current bias element or current
biasing element should be as high as possible.
And in addition to that, the current mirror also works as signal mirroring circuit. Later,
we will be talking about how it is really doing that. But just to give a hint, that it also has
good application in current mode amplifier to mirrored signal; not only mirroring signal,
it also helps to amplify current mode signal.
Then we have talked about the basic structure of current mirror and to get the basic
structure, we have discussed about various versions of current biasing elements, namely
simply registered and then leading to active device, and then we are we have discussed
about the final version which is current mirror.
And the structurally, current mirror it is having a current reference followed by a mirror
pair transistor. And then after the break, we have discussed more detail about the
expression of the output current. So, we have gone through detailed circuit analysis and
1139
we have derived the expression of output current of a current mirror in terms of reference
current, and then aspect ratio or the reverse saturation current ratio.
Then we also have talked about the output resistance and then finally, we have talked
about advancement of current mirror namely, cascode current mirror and also, so, this is
for both BJT and MOS and then also we have talked about Beta-helper. So, Beta-helper,
it improves the non-ideality factor. Second, non-ideality factor of BJT current mirror due
to whatever the loss it was having in the base bias.
So, I think that is all we have discussed, we yet to discuss 1 more item small-signal
model of current mirror. That it will be discussed in the next lecture along with other
topic.
1140
Prof. Pradip Mandal
Lecture – 83
Usage of Current Mirror (Part-A)
Dear students welcome back to our online certification course on Analog Electronic
Circuits, myself, Pradip Mandal from E and EC department of IIT Kharagpur. Today’s
topic of discussion is Usage of Current Mirror. So, we have started the current mirror
circuit and today we will be talking about its application.
So, according to our overall plan we are in week-9. In fact, this is course module-8. We
have talked about current mirror, its operating principle and analysis in the previous
lecture. Today we are going to discuss more detail of the current mirror specifically its
application and we do have different applications for this current mirror. One is in
common emitter and common source amplifier based on whether it is BJT or MOSFET
based implementation. Likewise, in common collector and common drain and common
base and common gate and also in differential amplifier.
So, in this lecture in fact, we can also see the usage of current mirror in signal mirroring
particularly within the differential amplifier, we will be talking about its application as
current mirroring circuit.
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So, what are the concepts we are planning to cover or what are the sub topic we are
going to cover today is the following. To understand or to appreciate the effect of
common current mirror in amplifier standard amplifier where, we normally talk about the
linearize circuit whether it is common emitter or common source or common collector or
common drain or for that matter even for differential amplifier.
We need to understand the small signal model of current mirror and to go into the small
signal model we do have two possible situation. One is the current mirror may not be
carrying any signal namely under DC condition what is the small signal equivalent
circuit and then we do have the second possible situation where the current mirror may
carry signal in the form of current. And we will be talking about both BJT and MOSFET
version of the use the small signal model. So, let me talk about the small signal model of
current mirror implemented by MOSFET.
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So, here we do have the current mirror circuit, we do have transistor-1 it is diode
connected and the we do have reference current DC current that is getting mirrored into
this branch through this transistor-2 and here we do have the application circuit.
So, we do have the application circuit which is connected to the power supply and the
current flow here as we have discussed that this current flow here it is defined by
whatever the current we do have here. Now, if you want to have said small signal model
of this entire circuit along with the application circuit, we need to know what will be the
small signal model of the current mirror.
So, here we do have the small signal model for transistor-1, it is having gm1vgs1 that is the
current flow voltage dependent current flow and vgs it is here. So; that means, whatever
the voltage you do have here it is the vgs1 and then we do have from drain to ground we
do have the resistance. Earlier we is to call this is rds; rds1, for fair comparison with BJT
version here we are instead of writing rds1 here we are writing ro1.
So, I should say this is synonymous situation. So, let me stick to this notation. So, we do
have voltage here which is vds as well as vgs, so we can say that this is the voltage. Now,
for small signal model this is DC current so; obviously, we have to make the current here
it is since it is 0. So, we can say it is this circuit is open.
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So, we do have open circuit here and then if this portion it is open. Then if we if we have
this small signal equivalent circuit what we can see here the solution of this voltage vgs
voltage it should be 0. That is because if I consider say this loop and this is having a
solution only when the vgs1 = 0 and mainly because this side as well as this side they are
connected to ground.
So, that makes the vgs1 = 0 and incidentally vgs1 and vgs2 they are equal. So, that makes
vgs2 also = 0. On the other hand the small signal model for transistor-2 M2, we do have
gm2vgs2 and vgs2 as I said that it is same as vgs1.
And also it is having drain to source resistance either we call this is rds2 or in this
discussion we are calling this is say ro2 and then we do have the application circuit. So,
now, this is the actual application circuit and here this is the small signal equivalent
circuit of the application circuit. So, this is small signal equivalent circuit of the
application module and then whatever the voltage we do have we do have this voltage.
Now, since vgs2 = 0, so we can say this part it = 0.
So, as a result what we have it is small signal model, we do have only this part left
behind. Which means that if we do have this reference current is having only DC
component and then suppose in the application circuit we do have some analog signal
coming and then probably we like to know what will be its corresponding transfer
function. Then to get the linearized circuit of the entire portion we need to draw the small
signal circuit here and out of this entire current mirror what we will be having it is only
ro2 left behind.
So, I should say the small signal equivalent circuit whenever we do have a current
mirror, then it will be very simple we do have the small signal equivalent circuit of the;
small signal equivalent circuit equivalent of application and then we do have simply this
resistance ro2 and then of course, in this node it is connected to AC ground ok. So,
likewise whenever we do have a current mirror having getting implemented by a BJT
instead of MOS, then also we will be getting similar kind of circuit.
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So, let us see that. So, here we do have; here we do have the current mirror and again we
do have a reference current is only DC, here we do have the application circuit or
application module and we like to draw the small signal equivalent circuit here. So, this
is the Vcc and to draw the small signal equivalent circuit what we have for transistor-1 we
do have ro1 from its collector to emitter. So, this is the I should say collector node as well
as the base node and base node as base node and collector nodes they are connected
together.
And then we do have gmvbe1. And what is the vbe1? This is the voltage we do have the vbe1
this should be vbe1. And we do have a course rπ unlike BJT MOSFET, here we do have
rπ1 and then we do have rπ2. So, these two resistors they are coming in parallel and then
whatever the voltage you do have here it is vbe1. In fact, the voltage across this vbe1 it is
the voltage here and that vbe1 incidentally it is same as vbe2 or rather vbe2 it = vbe1.
And again since it is a DC current for small signal equivalent circuit this is open and in
this network, particularly in this network if you see here we do have ground connection
here also we do have the ground connection and the only solution for this vbe = 0. So,
that makes vbe2 also = 0. So, this current flow here voltage dependent current flow it is
gmvbe2 and since this is 0 this part it is also becoming 0. And here we do have the small
signal equivalent circuit of the application module, equivalent circuit of the application
module.
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And so now, whenever we are feeding signal to this application circuit and we like to
know what is its corresponding transfer function, then this portion entire portion we can
completely omit we can just consider this ro2. As a result the corresponding small signal
equivalent circuit it becomes likes this. So, this is the small signal equivalent circuit of
the application module and then only ro2 it is there.
So, that is how we consider the small signal equivalent circuit for a situation where the
current mirror it is not carrying any signal current or rather whenever the reference
current is DC. Situation when may arise when this reference current may have a signal
part namely say iin.
And in that case; obviously, this will; this will not be 0 and this may carry some signal to
this voltage dependent current source. So, let us see that situation.
So, in the next slide we do have this situation, yes. Here we do have the basic current
mirror and now the difference here it is along with the DC reference current it is also
having signal current iin. So, this signal current it is again it is coming from either DC
you are whatever it is, but finally, at the collect the drain node of the MOSFET it is
arriving and it may be producing a voltage here.
So, this vgs1 is now it is function of iin and it is nonzero. So, here we do have the small
signal equivalent circuit drawn here for transistor-1 we do have voltage dependent
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current source which is gm1vgs1. So, this is vgs1 and vgs and vds they are equal. So, vgs1 it is
here. So, from drain to source we do have rds1 or ro1 along with this voltage dependent
current source gm1vgs that is the circuit. Now, here we do have the input signal current.
So, whenever we are drawing the small signal equivalent circuit we have to make this is
AC ground and this part will be eliminating DC part, but then we have to consider the
small signal part.
Now, if you analyze this circuit to find what will be the corresponding voltage which is
also equal to vgs2, we can consider iin that at this node we can apply KCL. So, iin = gm1vgs1
+ . So, that gives us; that gives us the expression of . So, that = and vgs2
and vgs1 they are same. So, this is vgs2 = vgs1 and its expiration is given here.
So, vgs; vgs2 = . So, that makes this current gm2vgs2 it is nonzero and as a result
whenever we will be drawing the small signal equivalent circuit of this entire part. So,
we do have the small signal circuit here; small signal equivalent circuit of the application
module and along with that we have to consider this. So, after multiplying with gm2 this
current source which is gm2vgs2 it is having this expression namely, .
In fact, this can be well approximated by by ignoring . So, this is × iin and of
course, here we do have the application circuit. So, in this case we can say that whatever
the current we do have if it is signal current. So, its effect in this application circuit can
be considered by considering this voltage dependent current source which is the input
signal here multiplied by . Now, this part depending on the ratio aspect ratio of these
two transistors it may provide again or it may be = 1 or it may be sometimes depending

on the situation it may be even less than 1.
So, that is how we consider the small signal equivalent circuit when the current mirror it
is carrying a signal current. So, that is what we said that if the current mirror it is having
AC current signal entering into it. So, it is conveying the current to the other side. So,
here you can see that this is the input to the current mirror and this is the corresponding
output and its gain we can say that .
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So, similar to this MOSFET version if you consider BJT there also will be getting similar
kind of expression only thing is that here will be having rπ also. So, let me quickly go
into that yeah.
So, here we do have the circuit yeah. So, this is the current mirror where we do have
current is having DC part along with that we do have the signal current. So, this DC part
in the small signal equivalent circuit that can be removed, but we have to keep this small
signal part. So, this iin we have to keep it sorry this polarity it should be in this direction
iin based on this convention. And then we do have the small signal model of Q1 which is
which is having the collector to emitter resistance which is ro1 and then we do have the
gm1vbe1 and then we do have rπ of transistor-1 along with rπ or transistor-2 in parallel.
So, we can directly see that we do have one more resistance and it produces whatever the
voltage here we may call this is vbe1 = vbe2 incidentally and that you may also call this is
vbe combined vbe1. So, the other side the small signal equivalent circuit for Q2, we do
have voltage dependent current source. So, this is dependent current source we can say
this is gm2vbe and then its collector to emitter resistor ro2 and then we do have the small
signal equivalent circuit of the application circuit and then this Vcc, now it is connected
to ground.
In the small signal equivalent circuit now if you analyze this circuit again similar to the
previous case namely MOSFET based current mirror you can get the expression of vbe in
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terms of iin. So, if you if you consider this iin and if you equate it to all the current
components which are essentially function of vbe. So, vbe × ( ). So, from
that we can say that expression of vbe, vbe1 or vbe2. So, that = .
( )
And this vbe it is same as the vbe of transistor-2. So, as a result this voltage dependent
current source it can be written in this form. So, we can say that it becomes after
multiplying with gm2, we do have this current it is shown here. So, .

( )
So, let me rewrite whatever it is given here it is having multiple mistakes. So, it is
. So, that is the expression for this current. In fact, similar to the
( )
previous case this part you may ignore. So, in the denominator you do have effectively
gm1.
So, this equivalent circuit may be written in this form. So, the current source here
dependent current source here which is ro2 and then of course, we do have the
application circuits small signal equivalent circuit of the application module which is
connected to AC ground.
So, now, we have covered this small signal equivalent circuit of current mirror for
different cases namely if it if the current mirror is not having any signal current, then it is
the equivalent circuit is very straightforward. Whereas, if the current mirror it is having
input current then of course, that current it is coming to the application circuit. Now, let
us try to see the application or usage of current mirror in different circuits.
1149
So, to start with let me consider common emitter or common source amplifier let me see
which one I do have yeah and to start with I do have common emitter amplifier with
active load. So, this is this is the main circuit where transistor-1 it is working as
amplifying device, input signal we are feeding through the coupling capacitor and then
R1 it is providing bias current IB. So, this is more like a fixed bias common emitter
amplifier. At the collector instead of connecting the passive load here we do have Q4
which is working as active load.
In fact, we have discussed about the active load circuit considering an independent bias
here, but instead of having a bias this may be better one particularly if we have say 2
NPN transistors they are identical. Then what we can do? We can place say R2 here
which is equal to R1 this R1. So, that provides the base current here which is say IB2
which is equal to IB1 assuming these two transistors they are identical that provides this
current and this current identical. So, I can say this is IC1 and this IC2; IC2 becomes equal
to IC1 assuming that transistor-2 and transistor-1 they are identical.
Now, by the virtue of this current mirror and if I assume that this Q3 and Q4 they are
identical then this current IC2 it is getting mirrored here. So, the current flowing through
transistor-4 which is also equals to IC2. I should say approximately equal to because as
you may recall that because of the base current loss there will be a small difference
between this current and this current. And if I assume that this is very close to this IC2
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and then IC2 and IC1 they are equal that makes this current and this current are getting
matched which we are looking for.
And not only they are matched the both the transistors transistor-4 and transistor-1 are in
active region of operation right. Here you might have observed one important changes in
the current mirror, if you see this Q3 and Q4 they are forming a current mirror, but type
of transistors here we have used it is PNP. So, we do have PNP transistor, we do have a
current flow here in this case Iref = IC of transistor-2. So, this Q3 and Q4 which are
together connected to supply voltage and then we do have a current mirror getting form.
So, this current mirror it is very similar to NPN transistor based current mirror. So,
whatever the discussion we had before namely the expression of this current in terms of
IS ratio of the two transistors multiplied by this current multiplied by non ideality factors.
One it is due to the base current loss another one it is due to early voltage finite early
voltage that can be considered. So, so the expression of IC4 = × IC2 and then we do
have two non ideality factors coming there. One is due to β loss or IB current and other
one it is due to the finite value of early voltage ok.
Now, here the as I say that the requirement here it is these two transistors they are
identical that makes probably many a times it is not so difficult to achieve that, but in
integrated circuit. But for discrete component based circuit still there may be an issue of
getting two transistors having identical situation.
So, I should say theoretically it is fine, but practically you may have to in case if you
want to make this circuit working you may have to tune this resistor to ensure that this
two currents under active region of operation they are equal ok. So, once we have these
two currents are equal, then to get the gain you can. So, the voltage gain which is defined
by . So, that can be obtained by considering its small signal equivalent circuit.
So, if you consider this part small signal equivalent circuit where this capacitor it is
working as a short. So, we do have directly vin coming here. So, we do have the vin
coming to the base let me use a different color otherwise you may get confused in yeah.
So, we do have vin here and then we do have rπ and then we do have. So, this voltage is
vbe incidentally that = vin as we have discussed earlier.
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So, we do have gmvin is the voltage dependent current source and then for transistor-1 its
collector to emitter we do have a resistor ro1. On the other hand for transistor-4, we do
have ro4 and we do have supply voltage which is AC ground. Now, the voltage coming
here it is the output voltage and this output voltage if we analyze this circuit this output
voltage is equal to ‒ gm1vin × (two resistors in parallel).
So, we do have ro1 ro4. In fact, so this is the expression this should be ro4 instead of ro2,
it is ro4. So, that is how we can say that we can use the current mirror in common emitter
amplifier. So, likewise we can use common emitter current mirror in common source
amplifier also.
So, in the next slide we do have the corresponding circuit. So, as you can see here
transistor-1 it is working as amplifying circuit it is having its bias to get a meaningful
voltage here we do have Vdd supply along with that R11 and R12 are informing the
potential divider to get VG1. So, likewise here we do have a potential divider consists of
R21 and R22 along with the supply voltage to generate a gate voltage VG2. Now, if we
consider these two transistors M1 and M2 they are identical, then if this potential divider
here and potential divider here they are identical providing equal gate voltage, then we
can say IDS or transistor-1 = IDS of transistor-2.
So, we can say this IDS2 = IDS1 assuming that DC wise this part and this part are identical
and then we do have current mirror form by M3 and M3 this is a current mirror
1152
constructed using PMOS transistor. So, here we are assuming that M3 and M4 are
identical. So, if they are identical then whatever the current it is flowing namely IDS2 it is
nicely getting mirrored here. So, we can say that ISD4 = IDS2 or to be more precise it is it
is having a ratio aspect ratio relationship.
So, we considered then multiplied by whatever non ideality factor and if I assume
that this = 1 which means that transistor-3 and transistor-4 their identical that makes ISD4
= IDS2 and then at the lower side we do have transistor-1 which is having IDS1. So, that
makes and the current here it = 1 assuming this IDS2 = IDS1.
So, with this assumption it may not be very difficult to match the current of the
amplifying device and the active load device and many a times in integrated circuit
particularly integrated circuit matching getting the matched characteristic of 2 transistor
it is not so difficult and this circuit it is hence quite frequently used in integrated circuit.
After getting the DC operating point correct we can probably try to get the gain of the
circuit and the gain it is defined by the voltage coming here . So, to get the
relationship between this output signal and input signal we can draw the small signal
equivalent circuit.
So, here we do have the small signal equivalent circuit let me clear the board and yeah.
So, yeah some part of the small signal equivalent circuit is missing.
1153
So, let me draw that part particularly this part we do have the input directly coming here
to the gate node of transistor-1 and that produces vgs1 and incidentally this vgs1 = vin. So,
we can see that voltage dependent current source it is gm1vin and at the output side we do
have this rds1 which we are denoting now by ro1. So, we do have ro1 likewise we do have
rds4 which we are denoting by ro4. So, we do have ro4.
And this is of course, it is AC ground and the output signal it is coming at this node.
Now, analyzing this circuit we what we can get it is vout equals to the current flow with a
‒ sign of course, with this convention of this current; current direction. So, this is gm1vin
× (ro1 ro4) and yeah. So, I should say yeah I should have multiplied by vin. So, that
gives us the voltage gain Av = = ‒ gm1(ro1 ro4) right.
So, likewise this current mirror it is also having application in differential amplifier. So,
this usage of current mirror is also there in differential amplifier an in differential
amplifier the current mirror not only it can be used as biasing element, but also it is used
as current carrying element. So, the discussion there it will be quite involved. So, we will
be discussing that, but let me take a break and then we will be talking about usage of
current mirror in differential amplifier. So, we will be coming back after the break.
Thank you.
1154
Prof. Pradip Mandal
Lecture – 84
Usage of Current Mirror (Part B)
So, dear students welcome back after the break. So, before the break we are talking about
usage of current mirror for CE amplifier, and also CS amplifier. Now we also can see
that usage of current mirror for Common Collector amplifier as well. So, here we do
have the transistor level circuit transistor-1 it is the main amplifying transistor input port
is here.
And then the output port it is here and earlier what we said is that the current of this
transistor it can be set by one reference current. So, instead of having reference current
this is what we do have the implementation of the current source. In fact, if you see that
it consists of a bias resistor RB maybe you can see bias. So, VCC to collector of transistor-
3 we do have this RBias and based on the value of this RBias we can get a current here and
( )
we call this is IREF the reference current and expression of IREF = .
So, that is the reference current and we do have the current mirror getting constructed by
transistor-3 and transistor-2. And if we ignore on the current the early voltage effect and
1155
the beta - loss. So, we can say that the collector current of transistor-2 IC2 it is well
approximated by × IC3.
So, this is the exact equation assuming transistor-2 and transistor-3 they are identical and
then this may be well approximated by × IREF. Strictly speaking this approximation it
is associated with the drop of the 2 non-ideal factors; namely ( ).
And in the denominator we do have non ideality factor which is which is
and so, and so. Here we assume that this non ideality factor it ≈ 1 and hence, we do we
can approximate this collector current equals to this reference current multiplied by the
reverse saturation current ratio of the transistor-2 and transistor-3.
And the IREF current is given. So, that sets the emitter current of transistor-1. So, IE1 it =
IC2. Now, once we get the DC operating point then to find the gain from input to primary
input to primary output we can draw the small signal equivalent circuit and since the
current mirror here it is not carrying any signal. So, the equivalent circuit small signal
equivalent circuit coming out of the current mirror it is only ro of transistor-2.
So, that is what we do have here this is the; this the model of transistor-1 and collector is
connected to VCC which is AC ground and at the emitter we do have ro2 and rest of the
things in terms of signal it is not carrying any signal so that can be a dropped and again
you can analyze this circuit to find what will be the corresponding gain. So, AV = and
that we have discussed that it is gain it is .
So, similar to common collector amplifier the current mirror can also be used for
common drain amplifier which is the MOSFET counterpart of this circuit.
1156
So, in the next slide we will see the circuit here we do have the main circuit. Transistor-1
it is M1 it is primarily the main circuit the amplifier circuit, which is connected in
common drain configuration this is the input port and this is the output port and here we
do have the bias circuit we do have say resistor RBias and this RBias it is connected
between the supply voltage and the diode connected transistor M3.
So, we can say that VDD = IREF × RBias + VGS3. And on the other hand and this reference
current IREF = IDS3 which is of course, ( ) . So, we may drop the ( )
part. And so, equating see or utilizing say these 2 equations we can get the IREF current
and that reference current; IREF reference that defines the IDS2 current.
⁄
So, IDS2 = × IREF. In fact, this strictly speaking it should be × ( );
⁄
ΔVDS2-3 = VDS2 ‒ VDS3.
So, by dropping this part by dropping this part or approximately making this part = 1. So,
we can get the expression of the current here which defines the current of transistor-1.
Again by once you get the DC operating point then to get the input to output relationship,
you can draw the small signal equivalent circuit. Similar to the previous circuit here
since the current mirror is not carrying any signal current.
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So, it is a small signal equivalent circuit out of the current mirror it is only the rds of
transistor-2 we are denoting this by ro2 and then by analyzing this circuit we can get the
voltage gain = = this we already have derived before.
So, that is how we can find the gain and that is how we can get the corresponding
operating point for the common drain amplifier. Now of course, since this both the
resistors are very high you can well approximate this by 1. Now, next thing is that the
current mirror can also be used our rather frequently used for differential amplifier. So,
our next topic or next subtopic it is how current mirror can be used for differential
amplifier.
So in fact, there are different possible applications and the applications of the current
mirror on differential amplifier it is having 3 folds. One is for replacing this tail resistor;
and if you replace this tail resistor that will improve the common mode gain. And then
you can replace the these 2 loads by active load and the active load can be biased using
current mirror and then in addition to that instead of having the active load bias from
external current reference or DC current reference we may replace this by something
called current mirror load.
So, this current flowing through this left half can be mirrored into the right half and that
mirroring it is different from normal DC mirror. Because, this left arm it also carries
1158
some signal and once you make the current mirror here; obviously, the signal also
propagates from left to right through that current mirroring and it is consequence it is that
it improves both the differential mode gain as well as the common mode gain; which
means that the active current mirror load it improves the differential mode gain and
decreases the common mode gain.
So, let us see one by one how the replacement or utilization of current mirror can be
deployed to improve the performance of differential amplifier. So, in this circuit what we
are what we mentioned here it is essentially this RT we are replacing by a current mirror
here.
And this current mirror it is of course, it is current it is said by the DC supply voltage and
then RBIAS and whatever it is dimension we do have. In fact, similar to the previous case
here again if I say that this is the reference current IREF; then you can say VDD = IREF ×
RBIAS + VGS4. On the other hand IREF = IDS4 and we know this IDS and VGS it is having
known relationship.
So, ( ) . We can drop the ( ) part and again utilizing these 2
equations we can find the reference current as we have discussed earlier. So, once you
get this reference current from that you can find what will be the corresponding current
flowing through transistor-3.
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So, in fact, that gives us IDS3 or tail transistor current; it is primarily defined by this IREF ×
⁄
because of the current mirror property. And then we can also consider ( )
⁄
or probably you can drop this part λ (VDS3 ‒ VDS4).
So, assuming Vth of these 2 transistors they are equal and their corresponding K
parameter equal and assuming λ of the 2 transistors are also equal we do obtain this
current equation.
And note that incident this ratio it is also there in case if this ratio aspect ratio of
transistor-3 and transistor-4 are same; then again this part it will be 1 and then this
current it will be IREF. Otherwise if the this ratio it is having some other value then we
can get this value different from IREF, but nevertheless this IREF current it is defining the
tail transistor current.
Now, in contrast to this circuit which you have discussed before, if you change the DC
voltage or common mode DC voltage in the circuit coming here and here if you vary this
DC current this node voltage the source node voltage also changes. And if we have
simple tail resistor if this voltage it is changing then the corresponding tail current also
changes; and the corresponding DC voltage as a result at the output DC voltage that is
that also changes.
Now in comparison with this if you consider this circuit having the tail current mirror
suppose we do have a common DC voltage at both the inputs again if we vary this
common DC voltage then the voltage here it will vary. But then this current since it is
having very weak dependency on VDS through λ. Then hardly these current changes
depending on the depending on the value of λ or you can say equivalent resistance the
variation here it will be very small.
So, we may say that as long as this voltage it is such that transistor-3 it is in saturation
region. Then the quotient current here it hardly depends on this common mode voltage
whatever we have said that this is V common and if this input common rather input
common mode voltage. So, if this current is not changing then of course, DC voltage
here and here they are also not changing.
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In fact, in case if we have common mode signal then also we can say that the
corresponding common mode signal coming at the 2 outputs it is it hardly depends on the
common mode input.
In other words, if you see the common mode gain; common mode gain of say this circuit
which is as you have discussed ‒ . On the other hand, if you consider say this
circuit the common mode gain it is ‒ .
Now, if you compare this part and this part in fact, we can well approximate this by
dropping this 1 and then the expression becomes . Whereas, for this case the previous
circuit this is becoming of course, with a ‒ sign.
So, if we compare this 2 expression since ro3 it is the output resistance of transistor-3 in
saturation region we know that ro3 it is much higher than the passive resistor RT for same
for equal tail current tail current; I should say DC tail current all right. And since this is
much higher then we can say that this common the common mode gain of this circuit
having this active device at the tail it is having much lower common mode gain.
So, if I call say this is A′c and this is Ac. So, we can say that this A′c it is much smaller
than Ac. So, that is why we say that it improves the common mode gain of the
differential amplifier. So, now, if you replace the load part by active current mirror then
what will be getting is the improvement of common mode and differential mode gain.
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So, in fact, here we do have the small signal equivalent circuit and using this small signal
equivalent circuit again you can derive the expression. And so, what we said is you
already have compared so probably we can skip this part; and we can directly go to the
differential mode gain improvement by replacing the load part.
Now, here we already have replace the tail transistor, but then we do have the passive
load. Now, these 2 passive loads it can be replaced by active device as shown here.
1162
So, RD1 it is getting replaced by transistor-7 and RD2 it is getting replaced by transistor-8
and they are getting biased from this is current and this is of course, a current mirror. So,
we do have 2 transistors M6a and then M6b both are diode connected and they are
connected together and suppose we do have some reference current.
So, this is M6a, this is M6b and then we are mirroring this current to say transistor-7. So,
this is transistor-7 and then we do have some circuit connected here ok. Now if I say that
let me call this is I′REF and since by the virtue of current mirror; if I consider this
transistor and this transistor they are identical then the current flow here if I call this is
⁄
ID7 can be given as .
⁄
Now since these 2 transistors they are identical we may say that W6 is essentially
summation of the 2 W’s; Wa + Wb. So, ⁄ is essentially summation of these 2 W’s
divided by the corresponding L and L they are same either we may say that La or Lb. And
so, this is getting multiplied by I′REF. Now if I say all the transistors are identical;
obviously, this part it becomes 0.5 IREF which means that only half of this reference
current is flowing through transistor-7.
So, likewise transistor-8 and M6 it is forming current mirror. So, the current flow here it
is again half of this I′REF. So, now we do have the reference circuit which and it is having
its reference current say IREF and this reference current it is getting mirror to transistor-3.
⁄
So, if I call this is ID3 = IREF × .
⁄
So, that is. So, we do obtain the current here in terms of IREF. Likewise, here also we can
⁄
get the current relationship namely I′REF it becomes IREF × by dropping ( )
⁄
part. So, what you can say that this reference current if say transistor-4 and 5 and 3 are
identical; then we can say this is equal to IREF this is also equal to IREF and the current
flowing through this transistor and this transistor they are .
So, this is also and why? So, half of these 2 IREF together it is giving the total IREF
here. So, that makes the current source coming from transistor-7 and 8. It is well
balanced with the capability of transistor-3 which is working as current sink.
1163
So, let me summarize here what I would like to say on this slide. If I assume that the this
transistor this transistor and transistor-3 they are identical then if I say this is IREF, that
makes this current is IREF and also this current is IREF. On the other hand if I assume that
all 4 transistors they are identical that makes this current = likewise, this also .
So, that is how we can say that DC current wise. So, if and of course, this IREF current it
is in case if we have same DC voltage applied here and if I consider M1 and M2 they are
identical. So, that makes this IREF current it is getting splitted into 2 parts or equal parts
are coming from 1 and 2 and that makes everything is getting well balanced.
And in fact, this is very common particularly for integrated circuit we want to keep
transistor-1, 2 anyway they should be matched and likewise, transistor-7 and 8 they
should be matched and in addition to that whatever the bias circuit we do have or bias
arrangement we do have.
So, here also we want this 3 transistors and transistors they should be identical likewise
not only this 2 PMOS transistor, but also the 2 bias transistors namely M6a and M6b they
should also be identical. And for integrated circuit that is not very difficult to achieve
and that is frequently getting used. In fact, this arrangement as expected since we are
replacing the resistors here by active devices the corresponding resistances offered by
this active resistance or active devices namely ro8 and ro7 they are much higher than the
RD we are we do have here.
1164
And we know we know that the differential mode gain = gmRD and since we are
replacing this RD by these active devices. So, we are expecting the gain should be higher.
We can draw this small signal equivalent circuit here and as you can see the transistor-1;
model of this transistor-1 it is given here. So, we do have ro1 and then gm1vgs1; vgs1 it is
given here, coming from primary input and whatever the source node voltage you do
have likewise.
We do have transistor-2 a model of transistor-2 here; which consists of ro2 and gm2vgs2
and vgs2 it is the gate 2 source voltage of transistor-2. So, this is the vgs2 that is coming
from in to and whatever the source voltage you do have. And then transistor-7 and
transistor-8 they are giving ro7 and ro8 and then if you analyze this circuit what we can
find that the common mode gain to get the common mode gain we have to make vin1 =
vin2 = vin_c.
And in that case both the voltage here and here they are same and left half and right half
assuming these 2 resistors are identical the left and right half are identical. So, probably
we can split this resistor into 2 equal parts, as we have discussed before namely; 2ro3 here
and then we can remove this part and then this voltage of course, this is vin_c this is also
vin_c and then from that you can find the both vo1 = vo2 = vin_c × gm1(or)2 × ro7(or)8 divided
by (1 + this degenerator).
1165
So, that is gm1,2 × 2ro3 and so, this is the both the outputs are same. So, we can say that
this is the common output voltage for common mode operation. And we can so likewise,
so you can get the corresponding common mode gain it is of course, it is having a ‒ sign.
So, that gives us common mode gain = right. So, for differential mode of
operation. So, by replacing these 2 transistors what we are getting is the common mode
gain of course, it got increased compared to the original circuit. But the differential mode
gain it is also getting increase. So, this increase of the common mode gain it may not be
having any drastic effect as the differential mode gain is also getting increased.
Now, for differential mode gain what you can do in this circuit for a differential mode
gain we can make vin1 = and vin2 = with a ‒ sign and we do have all these
elements ro7, ro8 then this is gmvgs1; gmvgs2. And so, this is with a + sign and this = ‒
and as we have said earlier that makes this node virtual ground.
So, we can simply then split this part and then we can find the expression of vo2. So,
since this is AC ground. So, this = gm(ro7 ⫽ ro1) × (the half of the differential input) and
with a ‒ sign. So, likewise if you consider vo1. So, that is equal to ‒ gm of course, this is 1
and this is 2. So, we may drop that subscript 1 or 2 assuming there I equal.
1166
So, this is multiplied by (ro8 ⫽ ro2) × with a ‒ sign here. So, this ‒ and this ‒ they are
getting cancelled. So, we can remove that. So, from that we can see the differential
output vo_d = vo1 ‒ vo2. So, that is equal to gm(ro7 ⫽ ro1) assuming the respective terms are
equal. So, this multiplied by vin_d and from that we can get from this you can get the
differential mode gain = gm(ro7 ⫽ ro1).
So, now the differential mode gain got increased from the previous value in the original
circuit it was Ad it was gmRD though these 2 resistors they are coming in parallel, but you
may recall this RD it was in parallel with ro1 and definitely this is much higher than this
one as a result this new Ad if I call this is A′d it is much higher than previous Ad. So, we
can say that, that is how the circuit gain it is getting changed by deploying the current
mirror in differential amplifier.
So, we have discussed about the MOSFET differential amplifier the situation it is very
similar if you consider BJT version. Let me take a break and then again we will be
coming back.
1167
Prof. Pradip Mandal
Lecture – 85
Usage of Current Mirror (Part-C)
Welcome back after the break. So, we are talking about the differential amplifier
particularly constructed by MOSFET. Now we are going to see the differential amplifier
using BJT, where we will be deploying the current mirror, corresponding current mirror
using BJT and will see the similar kind of situation there.
So, I may not repeat, but just for completeness we shall visit to those circuits which let
me go to the next slide to start with replacement of the tail resistor.
1168
So, here we do have the differential amplifier which is having till resistor is passive
element and also the load part it is passive. Now, here instead of RT, what we are using is
transistor-3 which is getting a bias from transistor-4 and the RBIAS circuit.
In fact, similar to the previous case, you can see that this is the current mirror circuit
which is helping us to set the tail current here. Now in this case the reference current
( )
IREF, it is coming from VCC. So, .
And this reference current based on the reverse saturation current ratio or transistor -3
and transistor-4, we do get current here which is IC3 of transistor-3 = × IREF of course,
multiplied by two nonideality factor; one is due to early voltage and another one is due to
β-loss or base-bias loss.
So, we may draw off this nonideality factor considering this ≈ 1. Then we do get the
current here said by this IREF current. And once you get the reference current here or the
tail current here said by the reference current, then we can analyse this circuit by
considering it is small signal model.
1169
So, as we have done for MOS circuit. So, here also we can draw this small signal
equivalent circuit compared to the MOS circuit the difference here of course, we do have
rπ. So, here also we do have rπ and the voltage here it is vbe, vbe2 here and we do have Rc1
and Rc2.
Now again similar to the previous case here if you analyse we can find the common
mode gain. and that can be well approximated by .

( )
Now similar to the previous case, this this part can also be replaced by active load and
that load current of course, should be consistent with whatever the current we do have
flowing through transistor-3 and to make it consistent the mirroring circuit should also
get current from here as we have seen for MOSFET version. The corresponding circuit is
given in the next slide yeah.
1170
So, here we do have that modified circuit. So, the modified circuit is given here and this
was the previous circuit where load it was passive, but till tail element it was bias by
current mirror. Here we do have both the tail part it is coming from this current mirror
and the load part.
So, this load part it is having these current mirror and it is reference current of course,
this reference current it is also getting from the same common reference current. And as
a as a result we can maintain the good balance of this current and this current together
with whatever the current is flowing through transistor-3. Namely, if I say that similar to
the previous case if I say this is IREF, assuming transistor-4 and transistor-5 they are
identical.
So, this current it is also ≈ IREF and then we do have two transistors identical transistor to
transistor-7 and 8 which is mirroring and since we do have two transistors diode
connected I have connected, this is connected. So, the current here it is same thing
here also it is . And here on the other side at the tail we do have this current it is IREF.
So, whenever we are applying a common DC voltage and if transistor-1 and transistor-2,
they are identical then you can see half of these two currents together they are
converging to IREF without any problem maintaining their corresponding VBE equal. So,
that is how the load part it is getting replaced by active device, but as I said that this
1171
proper matching of the active load current with the tail current it is essential otherwise
the DC voltage it may having some issue.
Now here, similar to the common mode gain for differential mode gain we can we can
draw the small signal equivalent circuit and then we can analyse the circuit to get the
differential mode gain.
So, in the next slide we do have the corresponding small signal equivalent circuit, it is in
fact, we do have rπ here and rπ here and this resistor it is ro7 and this is ro8; gm2vbe2, gm1vbe1
and vbe1 it is given here. So, likewise here also we can get the vbe2.
And, then we do have the corresponding output and for differential mode of operation;
we can say this is half of the differential input is coming as vin1 with maybe +ve polarity
and here it is remaining half namely , but with a ‒ sign. And since left and right parts
they are identical. So, again we can split this resistor, in fact, it is not necessary to split
for differential amplifier rather this node it becomes AC ground or a virtual ground.
That makes this part, left part and right part we can consider independently without
considering this ro3 and by analysing this circuit we can find the corresponding
differential mode gain say A′d which is defined by and vo_d it is vo1 ‒ vo2. As you
have discussed earlier in other examples it will be easy to find that this = gm1(or)2 × (ro7 ⫽
ro1).
1172
In comparison with this modified gain, if you recall the previous circuit; differential
mode gain it was gm1(or)2 × (RD ⫽ ro1). So, definitely this is having much higher gain. In
fact, this circuit since the active load the here you are using active load with respect to
passive load. The common mode gain of course, got increased, but since differential
mode gain also got increased it is not an issue.
So, just for completeness modified common mode gain it becomes with a ‒
( )
sign and this ≈ . So, this is in comparison with the previous circuit gain, common
mode gain, it was ‒ .
So, here of course, the common mode gain it got increased with respect to RD, here we
do have ro7 which is much higher, but if I consider the ratio differential mode gain
divided by common mode gain that is remaining unchanged. In fact, the ratio is
important which is referred as common mode rejection ratio. So, to summarize we have
replaced both the active load part and the tail part it is getting in fact, current mirror. So,
that makes the differential mode gain and common mode gain getting improvised.
Now instead of having say this kind of load which is not having any signal propagating
we may have some better arrangement particularly, because if you see this transistor
current and this transistor current DC current wise they are same. So, we may be having
some attempt to or tendency to use current mirror here.
So, in the next slide what we will see that there will be an there will be one modification
of replacing this active load by active current mirror load.
1173
So, here we do have the active load circuit sorry, here we do have the active load circuit.
On the other hand, if you see the transistor-7 and transistor-8, both are having equal DC
current. So, why not making this transistor like a diode connected transistor if it is having
say half of the current flowing here then that half current or , that can be that can be
mirrored into transistor-8.
So, if this is so, these two currents together it is giving IREF and that makes definitely
the circuit simpler. So, what we are looking for here it is we do have simple only this
portion it is having a current mirror bias and in addition to that we also have a current
mirror load. So, this kind of load it is referred as current mirror load. Note that, here also
we do have a current mirror, but we do not consider this as current mirror load. Namely,
because this current mirror though we do have current mirror circuit, but it is just getting
only DC bias.
In contrast to that in this case whenever we will be applying a signal, transistor-1, it is

having say current signal and that signal it is also getting mirrored into transistor-8. And
there will be it is direct impact or consequence on the differential mode gain on and
current mode gain or to be specific the signal here it is a function of this one.
1174
Also since this transistor-7 it is diode connected. It is expected that a signal at this node it
will be getting affected because the impedance of transistor-7 which is diode connected.
So, that impedance it will be much smaller in fact, this will be approximately .
So, as a result at this node the signal it will be less. But, but we have to keep in mind that
because of the signal it is getting mirrored from transistor-7 to 8. The signal on the other
side namely at Vo1, it is getting enhanced and the signal here it is getting doubled. So, if I
take difference of this two and if I say that is the differential output signal, then we will
not be seeing any change on differential signal.
So, that is how it is done. In fact, that it makes the circuit much simpler as you can see.
In fact, it is not just only for simplicity this circuit is popular, in addition it is also used to
make the circuit differential to single ended.
So, here we do have most of the signal whereas, at this node we do have hardly any
signal. So, while we are stimulating this circuit by say external whatever the signal
coming here which is signal it may be coming in the form of differential and common
mode component. But, then the differential part it is getting combined and it is coming in
the form of single ended and whatever the circuit you will be connecting here in case if
the common mode part it is nicely rejected by this circuit at this point then rest of this
1175
circuit, rest of the circuit we can use in the form of single ended architecture, single
ended amplifier architecture.
So, from this point onwards it will be single ended amplified. So, similar to this BJT we
also have the MOSFET version where we can replace the active load by active current
mirror load.
So, in the next slide we are having that circuit. So, as you can see here transistor-7 and
transistor-8, they are forming a current mirror and again similar to the previous BJT
version. So, sorry this should be MOSFET. So, here the not only of course, from DC
point of view, the current here it is getting mirrored here and we know for DC operating
point current flow through transistor one and transistor two they should be equal.
So, whatever the reference current we do have, we do expect half of this reference
current it will be coming from transistor-1 and that half of the reference current it is
getting nicely mirrored here which is eventually coming back to transistor-2. So, that
makes the entire circuit well balanced.
So, and as I said that it is not only making this circuit much simpler compare to compare
to this circuit it also improves or modifies the differential mode gain and common mode
gain. In fact, if we see the differential mode gain it hardly gets change, but the in
common mode gain it is getting drastically dropped. So, in the next slide we will be
1176
talking about the common mode gain and differential mode gain by drawing it is small
So, DC point of view also we have to keep one thing one important thing here that since
this transistor yeah since transistor-7 it is diode connected voltage here it is pretty well
defined. In fact, whatever the half of this reference current is flowing here along with the
VGS of this transistor it defines the corresponding voltage here. So, if I draw the left part,
we do have transistor-7 diode connected.
At the source we do have VDD and the current flow here it is . So, by considering it is
dimension and the K factor, we can find and of course, the threshold voltage we can find
what is the corresponding VSG of this transistor. So, the voltage here it is DC voltage
here it is VDD ‒ this VSG. So, this node since it is diode connected you may say that DC
wise it is very well defined and small signal wise you may say that impedance of this
circuit, small signal impedance it is much smaller namely .
So, based on the reference current you can find the corresponding DC voltage here and
this DC voltage eventually if this 7 and 8, they are well matched. It can be shown that
DC voltage on the left side it is also equal to DC voltage on the right side. So, let me try
to explain why the DC voltage here and DC voltage on the right side they are equal.
1177
Suppose, if I consider ( ) part also for all the transistors particularly all the 4
transistors. And then if I say that DC at this point it is say V2 and DC here at this side it
is V1. So, if I consider V2 it is a higher than V1 and let we assume that we do have same
DC voltage connected at the both the inputs and assuming transistor-1 and transistor-2,
they are identical.
So, since we do have same common mode voltage, it is coming to the input. So, we may
say that we are expecting that these two currents should be same because the VGS here
and the VGS here they are equal and transistors are identical.
But if I consider ( ) part then definitely the they may be slightly different. So, if I
consider V2 it is higher than V1, which means that VDS of transistor-1 it is higher than
VDS of transistor-2 and that gives us IDS of transistor-1, it is higher than IDS of transistor-
2. And this this difference is primarily by considering ( ) and then if I consider
this condition on the upper side and if I consider transistor-7 and 8 they are identical.
So, that makes VSD of transistor-7 it is less than VSD of transistor-8. In fact, that gives us
though these two transistors are identical and then they are VSD, they are identical, but
because of (1 + λVDS) you may say that ISD of transistor-7 it is less than ISD of transistor-
8. But then since it is DC connection in the there is no current flow here it is capacitive
connection the ISD of transistor-7 and IDS of transistor-1, they are equal.
So, if these two are equal and also this two are equal, but then their relative value it is
having opposite condition. So, that makes this condition not possible. So, similarly, it
can be shown that V2 cannot be less than strictly cannot be less than V1. So, by
considering this we may say that V1 should be equal to V2. So, DC wise you may say
that this node and this node they are identical.
So, you may say that they are virtually getting short and not only this is for DC, even if
you have say is some small signal here even for the small signal whatever the signal you
will be getting here, the same signal it will be coming here. So, if I know what will be
the voltage coming here for common mode input vin_c whatever the voltage we are
getting here we can directly say that the corresponding voltage it is coming to the other
input. So, to get the common mode gain of this circuit, we can simply consider left up
and then you can what will be the corresponding right of voltage.
1178
Even though this is not directly connected and we are expecting that M8 and M2, they are
in saturation region and hence the output impedance should be very high, but because by
the virtue of this current mirror particularly for common mode operation, the left of left
side output and right side output they are identical. So, to get the small signal common
mode gain, what we can do probably we can draw the small signal equivalent circuit and
then there we can analyse the circuit to get the common mode gain. So, in the next slide
we will be having that analysis yeah.
So, we do have the small signal equivalent circuit most of it only thing I have to add here
it is gmvgs. So, an vgs1, it is here this is MOSFET. So, likewise here we do have vgs2 and
this is vgs2. Here we do have transistor-8 and here we do have. So, this is ro8 and also we
do have ro7. In addition to that we do have this transistor diode connected.
So, what we are expecting? Either we draw the voltage dependent current source or
simply you can since it is diode connected you may say that it is having is the
equivalent resistance. Also this node it is going to the gate of transistor-8. So, in case if
we have a signal here at say vo2, that signal it will also provide a current here and this
current it is gm8vo2 right.
So, now if you see two cases particularly for common mode operation and differential
mode operation. Let me to start with let me consider vin1 = with a + sign here and
1179
this = ‒ . Even though this circuit and left circuit and right circuit they are not
perfectly well balanced, but still approximately you can consider that this is AC ground.
So, this is for differential mode of operation you may consider this is AC ground. And
the voltage coming here at vo2 it can be written as gm1vgs1 × (ro7 ⫽ ro1 ⫽ ). Now vgs1 =
vgs. So, this is gm1vgs1 it is essentially and this part it ≈ . So, this . So, that
gives us the output voltage here.
Now, if I consider on the other hand if I consider the voltage here vo1. So, the vo1, it is
this is equal to the current here we do have gm2vgs2; vgs2 = ‒ . So, this ‒ and that ‒ is
getting cancelled. So, you can say simply multiplied by the resistance here, but also
we do have this current which is equal to gm8 into this voltage and this voltage it is ×
and this multiplied by the resistance here. So, the resistance of course, here it is (ro8
⫽ ro2).
So, if let me use the other space to write this vo1 equals two if I considered gm8 and gm7
they are equal. So, I can cross it and then we do have gm1 here and gm, gm2 and gm1 they
are same both are getting multiplied by vin_d. So, we can see that this is gm1(or)2 × ×
(ro8 ⫽ ro2). So, this is having two times; one is coming from say gm2 part another is
coming from the current mirror part. So, this 2 and this 2, they are getting cancelled and
that gives us gm1(or)2 × (ro8 ⫽ ro2) vin_d.
So, this is very interesting that signal here, signal here compared to the previous case got
doubled. Earlier we obtained the signal here and signal here they are having equal
amplitude, but of course, in opposite phase on the other hand now the signal here is this
is much smaller. If you see the gain here it is approximately equal to say maybe 1, if say
gm1 and gm7 they are equal. But the signal on the other hand here it is much higher or it is
getting doubled.
So, I should say if I observe the signal here and signal here at this side we may have very
small signal almost in the same order of this one. So, the signal here and signal here they
are having similar amplitude of course, they are in opposite phase. On the other hand, if
you see at vo1, at this point the signal here it is having much bigger amplitude.
1180
So, we may simply consider this node as the primary output and then we may say that
this circuit it is having from this point onwards this is carrying the quote and unquote
entire signal. And this port or this node it is having hardly any signal or rather this signal
it is amplitude it is in the same order of magnitude of the primary input.
So, to summarize what I like to say here it is. If I consider say this is not connected rather
if this node it is coming from independent bias then the voltage here and voltage here
under differential mode of operation they were having equal magnitude something like
this.
So, here it was signal it was having equal amplitude, but opposite phase right. And now
if I make this diode connection, if I make this diode connection instead of giving
independent bias now if I give the bias getting generated from here. So, that makes this
signal is getting much weaker because of this diode connected transistor it is resistrants it
becomes 1 by approximately .
On the other hand, this signal got amplified, it got doubled. So, this is vo1 and this is vo2.
So, for diode connected transistor-7, we can say this is the main output and this is I
should say secondary output also you have to keep in mind that voltage DC voltage here
and DC voltage here they do have the same level. As I said that voltage here and voltage
1181
here cannot be different for common mode operation. So, now we can talk about the
common mode gain.
So, let we talk about the common mode gain. For common mode operation this is vin_c
this is also vin_c and; however, this resistance this is approximately this is ro8, but it is
also having voltage dependent current source which = gm8vgs which is same as vo2. Now
this is gmvgs1 and this is into vgs2 and this is the corresponding vgs2 and this is the
corresponding vgs1.
Now, under this common mode operation we are applying same signal here as well as
here and as a result we may say that we can probably since left and right half they are
having similar kind of situation. We can split this resistor into two identical parts; this is
also 2ro3. Now as I said that this voltage and this voltage under strictly common mode
operation whether for DC voltage or even for common mode condition, since these two
voltages is they are equal.
So, we may say that this node and this node they are virtually short. In fact, if you short
it then this voltage dependent current source can be replaced by one resistor which is
same as . So, that makes the left and right part they are identical and hence you can
split the circuit without any effect. So, you can replace this one, this resistor by these two
identical resistors. And then to find the voltage at this node vo2, we can simply analyse
1182
this part and if we analyse this circuit it becomes like a common source amplifier, where
the load it is diode connected.
So, the circuit becomes like this. We do have gm1, we do have gm7 connected to VDD and
then this transistor half of the transistor we may call say M3 by 2. It is just a just a matter
of representation and at this point we are giving the small signal along with the DC. Of
course, this node it is getting the bias similar to this point and we like to know what will
be the corresponding output here due to the small signal and this small signal it is vin_c.
Now, if you analyse this circuit or if you draw the small signal equivalent circuit, you
can find that the voltage here vo2 = ‒ gm1 × . So, this into whatever input
( )
signal we are applying vin_c. In fact, as I said the voltage here also it will be same.
So, we may say that vo1 under common mode operation is also = vo2 and that gives us
vo_c = vo common mode. And hence the corresponding common mode gain if I say A′′C
which is defined by = ‒ gm1 × .

( )
Now, again you can see here because the resistance now it is getting changed . So,
this AC it is much smaller than the previous common mode gain. So, to summarize what
we can see the advantage of having this current mirror in the load part.
1183
What do we obtain it is the common mode gain got drastically decreased and it = ‒
divided by 1 plus sorry, one part we can remove so, × 2ro3. So, that = ‒ .
So, this is one consequence of having this active current mirror load and the gain at this
point, gain at this point if I say that . So, that is becoming gm1 ( ). In fact, you may
say gm1 or gm2 both are same. So, we can say that differential input to single ended output
gain it is same as whatever the gain earlier you obtained.
So, that is why this circuit it is very popular to convert differential signal in the form of
common mode signal in addition to that since the DC voltage here it is same for the two
nodes the DC voltage here it can be directly obtained from this node and since this DC
voltage it is with respect to VDD or to be more precise it is VDD ‒ VSG7. So, we can say
that DC voltage here it is VDD ‒ VSG7 and hence this voltage can directly be used to bias
PMOS transistor in the subsequent stage.
So, we can have this is VDD and let you call this is transistor-9 and this 9 transistor-9, it is
having a very meaningful DC voltage received from on the previous drain node of
transistor-8 and of course, it is also receiving the signal which is coming through this vo1.
I think most of the things I have covered.
1184
Let me summarize the presentation in these 3 parts of this lecture what we have done it is
we have started with a small signal small signal model of current mirror particularly,
under DC condition as well as whenever it is carrying the signal current for both BJT and
MOSFET versions.
And then after that we have talked about usage of current mirror particularly as bias
elements for common emitter amplifier and common source amplifier particularly for the
load part and we have seen that it enhance the gain of the both the amplifiers. And then
also we have discussed about the usage of current mirror as a biasing element for
common collector and common drain amplifier. And then finally, we have talked about
usage of current mirror in differential amplifier.
And it is having two kinds of application, one is for biasing element and we have seen
that it improves the common mode gain and differential mode gain. In addition to that
finally, we have talked about the usage of the current mirror as active mirror load. This
helps to convert the output port in the form of single ended and in addition it also
decrease the common mode gain what we said is A′′C very low it is in fact, it is
magnitude it is gm7ro3, this is very very small.
So, this helps to improve the common mode rejection drastically. I think that is all to
cover. In the next class we will be talking about numerical examples.
1185
Prof. Pradip Mandal
Lecture - 86
Numerical Examples on Current Mirror and its Applications (Part-A)
So dear students, so, welcome back to our online certification course on Analog
Electronic Circuits. Myself, Pradip Mandal from E and EC Department of IIT,
Kharagpur. Today’s topic of discussion it is Numerical Examples on Current Mirror and
some Application Circuits, where we are using current mirror. So, primarily we will be
talking about numerical examples, to complement whatever the theory you have learnt
on current mirror and its application circuit.
Now according to our plan, we are in week-9 and in fact, that is the course module-8 and
we have discussed about the theoretical aspect of current mirror and different application
circuits. And as I said that today we will be covering numerical examples extensively, on
current mirror and different types of current mirrors including simple one and then
advanced one.
1186
So, the coverage of today’s presentation is enlisted here. So, we shall start with
numerical examples of simple current mirror. We may start with current mirror having
MOSFET transistor and then we can go for current mirror using BJT and then we will be
moving to numerical examples on improvised current mirror or more precision current
mirror.
And there also we will be having 2 types of circuits: namely one using BJT’s and then
other one is MOSFET. And subsequently, we will be talking about numerical examples
on amplifiers which are using current mirror. So, our main focus is on the current mirror.
So, we may not be going into the aspect of the amplifiers, but primarily what are the
advantages we can get using current mirror and what is the corresponding calculation we
do? That will be highlighted by considering 2 specific types of examples, one is single-
ended amplifier namely, common emitter and common source amplifier and then
differential amplifier. Now, coming to a current mirror, simple current mirror
constructed by MOSFET, here we do have the example.
1187
So, here we do have the example circuit where M1 and M2 are forming current mirror.
We do have a reference current here and then we do have the application circuit here. So
in this example, the of transistor-1 and transistor-2 along with the K factor, it is given.
For transistor-1, we do have 1 mA/V2. For transistor-2, we do have 4 mA/V2.
And let me assume that both the transistors are having equal threshold voltage of 1.5 and
then we do have the reference current = 0.5 mA, and then supply voltage it is 12 V. To
start with, let we go simpler version, ignoring lambda effect considering both the λ’s are
very small and let we try to find the values of VGS1 and IDS2.
Of course, IDS1 it is same as IREF current namely, 0.5 mA. But then, VGS1, it is setting
VGS2 and since the K of the 2 transistors, they are different, we are expecting the
current here to be different. So, let me start with the calculation of VGS1 or for IREF = 0.5
mA so, that is the IDS = its corresponding K which is 1 mA/V2 by 2 × ( ) .
So note that for this calculation, we are ignoring ( ). Even if the λ is given, we
normally ignore that. And if you see here, this equation it is giving us VGS1 = Vth1 + 1 =
2.5 V. So, this 2.5 V it is coming to the VGS of transistor-2 and the corresponding current
here, it is either we can use this information of 2.5 VGS and then again, you can use the
similar kind of equation. Or directly, we can use the expression of you know this IDS2
current.
1188
⁄
In terms of IDS1 × . So, from this we can say that the IDS1 it is 1.5 mA and if you take
⁄
the ratio of K , and K here. In fact, we do have Kn in here and Kn in here. So, they
are getting cancelled and then ratios are coming . So, that gives us IDS2 = 2 mA. So,
current flow here it is 2 mA.
Now we can find next part it is that we need to find what is the minimum value of this
VDS of transistor-2, particularly for transistor-2 for proper operation of the circuit.
Namely, the current mirror current output current can be well defined by this equation
only when transistor-2 also in saturation.
So to keep this transistor in saturation, we know that the drain voltage it should be higher
than the gate voltage minus Vth and gate voltage we know, it is 2.5 V. So, the VDS(min) =
VDS(min)2 = 2.5 V is the gate voltage ‒ Vth which is 1.5 V. So, that gives us minimum
requirement of this voltage it is 1 V.
Now, let us consider the next part of the same question in the next slide. So, that will be
continuation of this problem. But probably, we can consider some finite value of from
this λ’s.
So, in the next slide we do have, so, what we have here it is all the other parameters
remaining same. In fact, it is continuation of the same example, but we are considering λ
1189
= 0.01 V‒1. And then again, we can try to find what is the corresponding value of this
current. And particularly for 2 cases, if VDS2 here that is 2.5 and 5.5.
Now, you may recall from our previous calculation, the voltage here it is 2.5 VGS, we
already have calculated = 2.5 and so that is also VDS of transistor-1.
And then for the first case if VDS = 2.5 and if you consider this λ, then you can get the
⁄ ( )
current of IDS2 which is having this equation × IREF. And then we do have ( )
.
⁄
Now for this case, VDS2 = 2.5, both this VDS and this VDS they are same. So, and also the
lambdas are equal. So, we can say that this part of this equation it is becoming 1 for 2.5.
As a result, the corresponding current here it is coming. So, this ratio it is 4 and IREF as I
said it is 0.5. So, that gives us 2 mA. And this is for VDS2 = 2.5 V. And let us try to
calculate the IDS2 for the other value namely the VDS = 5.5.
So for that, if I say VDS2 = 5.5, for this, IDS2 it is equal to so, this part it is remaining
same. So, we can directly write that part which is 2 mA × this non-ideality factor,
( )
( )
. In fact, this part you can approximate well, approximate by considering this
denominator factor into the numerator factor. And then if we ignore λ2 term, and since
( )
both the λ’s are equal, so, we can say that this is ( )
.
So, what we are getting here it is 2 mA multiplied by so, VDS2 ‒ VDS1. So, VDS2 it is 5.5
and VDS1 it is 2.5. So, this part it becomes so, this part it becomes 3 and λ is 0.01, so that
gives us 1.03 is the non-ideality factor. And that gives us the current = 2.06 mA. So, we
can say that for these 2 different VDS values we do have different current; one is 2 mA
here, another is 2.06 mA.
So pictorially, we may say that if we vary the VDS of transistor-2, the current here it is
having a finite slope. So, this is IDS2 and we do have one value here 2 for 2.5 V the
corresponding current is 2 mA. On the other hand, for 5.5 we do have so, this current is
2.06 mA. And from the slope of this line from the slope of this line, we can calculate the
output resistance or we can strictly speaking, it is small signal output resistance.
So, to calculate the small signal output resistance what we can see here it is we can get
the calculate the slope of this line and reciprocal of that is the small signal output
1190
resistance. So, small signal output resistance at the output of the current mirror Rout. So,
that is the voltage difference and we know that ΔV it is 3 V and the corresponding
variation of this ΔI it is 0.06 mA.
And so, this is giving us how much? × 105 Ω, right. Or you can say this is 50 kΩ. So
that is the small signal output resistance of 50 kΩ, right. So, now, if we continue this
exercise for say, other condition. So, let we see in the next slide the third part of this, no
now we are going to BJT. So, we have considered this simple current mirror. So, similar
kind of circuit can be constructed by BJT.
So, in the next slide will be going for simple current mirror constructed by BJT’s and it
will be having similar kind of exercise. But of course, the corresponding parameter of the
BJT’s is different. So, let us see in the next example how we calculate for current mirror
circuit constructed by BJT.
1191
Now, in this example we do have Q1 and Q2. Now it is forming the current mirror and in
this case, just for a change, instead of giving a reference current, we are giving a resistor
here, supply voltage it is given to us 12 V. This RBIAS resistor in resistance it is 22.8 kΩ
and then we can assume that VBE(on) voltage for both the transistors are approximately
0.6 V. In addition to that, we also have the information about reverse saturation current
of the 2 transistors.
So, Q1 it is having reverse saturation current of 9.5 × 10‒14 A. On the other hand, for Q2
we do have reverse saturation current which is 2.85 × 10‒-13 A. In fact, if you see
carefully, this is = 3. So, that is how I have picked up the number here.
So with this, what we can probably we can see the mirroring ratio it will be 1∶3 if it is, if
we approximate that early voltage and then β-loss or the base current loss it is ignorable,
then we can say this current mirror is essentially 1∶3 ratio current mirror. But before that
we need to find what is the reference current itself I reference.
( )
To get thus this IREF current, so we need to find what will be the IREF? IREF =
= = = 0.5 mA. Now, if I consider a simple situation considering this both
the β’s are very high, early voltages they are also very high which means that non-
ideality factor we can we are ≈ 1.
1192
So, the current flow here IC2 is given by × IREF. And then we do have the 2 non-
ideality factors. One may be due to early voltage another one may be due to the base
current loss or due to finite β. And for this part, both these non-ideality factors = 1. So,
this = 1; this is also = 1.
So, that gives us the current IC2 = which is 3 and then IREF we have calculated is 0.5.
So, that gives us the output current = 1.5 mA.
Now, let we consider the effect of β namely, the current loss due to whatever the currents
are flowing here. So that means, this is no more = 1 and to get this non-ideality factor
you may recall that this part = . So, this is the non-ideality factor and the
values of β1 and β2 are given. This is also the , it is also known that is why this is 3.
So, we can see that let me use this space. So, this non-ideality factor it becomes 1
divided by . Then we do have 3 here and then 150 in the denominator. So, that gives
us = 0.02. So, that gives us , ok.
So with this factor, for this case, to calculate this current we need to multiply by this non-
ideality factor of 1.03. In fact, if you calculate it what we are getting here it is =
1.456 mA. So, this part it is coming 1.456 mA.
So if I consider finite β of course, this current is getting smaller because this non-ideality
factor < 1. On the other hand, if I consider say early voltage if this voltage and this
voltage they are not equal, then again we will be getting non-ideal adding the second
non-ideality factor. So, if this voltage it is higher than the VCE1, so, in that case this non
ideal non second non-ideality factor it may be higher than 1. So, to consider that let we
go for the third part of this example.
1193
So, in the next slide it is continuation of the same numerical problem. So as you can see
here, we do have all the parameters we are keeping same. Except, we do have early
voltage of the 2 transistors are given here and intentionally, we are using different values
of early voltage. And we already have obtained the effect of β, right.
So, we already got IC2 = 1.5 × which in fact so, this is equal to 1.456 mA, without
considering this early voltage. Now, if we consider this early voltage and if you observe
the VCE voltage difference, then we have we can calculate that factor.
So, let me consider V2, this V2 = 0.6 V and we know that this is VCE1, VCE1 = 0.6 V. So,
( )
if I consider this V2 = 0.6 V then that non- ideality factor, I am going to . And for
( )
this case, both this part is 0.6 and also this part is 0.6.
However, this early voltage we are keeping it is same. So, it is not getting cancelled, it is
rather we do have 1 + 0.006 in the numerator and in the denominator, we do have
( ). So, = 0.12, ok.
So, this non-ideality factor it is . So, this is 0.994. So, we need to consider this factor
of 0.994 and so that gives us the current equals to 1.447 mA. This is the case with V2 =
1194
0.6. Now if I consider say V2 = 5.6 so, in that case what are the changes do we expect?
This part this part it will be different, namely, and that part it will be .
So, that it becomes 0.056. In fact, this factor then it will be . So, that = 1.0435
instead of 0.994, we need to replace this by 1.0435, and the corresponding current here
instead of 1.447, we do have 1.456 × this factor = 1.519 mA. So, for this voltage we do
have 1.519 mA.
Again to you can use this to data point to calculate the slope of the IC versus VCE. So, at
this point of 0.6 V VCE2, we do have the current that current it was this was point 1.447.
On the other hand, at this point we do have current which is for 5.6 V VCE2 and this
voltage this current it is 1.519 mA. So again, by considering reciprocal of this slope we
can calculate the output resistance offered by this current mirror at its output.
So, Rout so, that is equal to ΔV voltage change divided by the corresponding current
change. And voltage change it is 5 V; 5.6 ‒ 0.6 so, that is 5 V divided by this current
difference. So, that is equal to 1.519 ‒ 1.447. So, that is 0.072 m. So that means, it is 103
Ω or you can say that this = 69.4 kΩ.
So, the small signal output resistance it is 69.4 kΩ. So now, here we have considered, so
far we have considered simple current mirror. Now we can go for more precision current
mirror and as we can see here, if I consider finite values of β’s and then early voltage, the
ratio instead of 1∶3, it is becoming different, slightly different though. There may be
some precision cases, precision applications where this much of difference may not be
still acceptable.
And then we can go for betterment of the circuit. So, for current mirror constructed by
BJT’s we do have 2 types of improvement one is to take care of the non-ideality due to
the early voltage another one it is to take care of the non-idealities factor due to the base
current loss. So to take care of the base current loss, as we have said that we can have a
Beta-helper circuit here, so that the current loss to the base of this third transistor which
is much smaller than whatever the base current is going to Q1and Q2 which is referred as
Beta-helper.
1195
So, continuation of this new this numerical example, to go for that Beta-helper, let we go
to a next slide.
So it is, I should say it is more like a continuation of the previous problem. Namely, we
are retaining the parameters here. So, the current flow here it is 0.5 mA and we have we
have calculated the base current the non-ideality factor due to the base current loss. Now
we can improvise the circuit by using Beta-helper here.
So, let you call this is transistor-3. So, we are adding this Beta-helper and this Beta-
helper its β it is 99 and then once we add this transistor, we need to readjust this resistor
because once you add this transistor, since the collector and base voltage they are not
same, in fact, if you observe carefully, this is one VBE this is another VBE.
So, if I approximate that this VBE it is also 0.6, then the DC voltage coming here it is 1.2
V, ok. Now since you are trying to keep the focus only on the non-ideality factor coming
due to the base current loss, we are suppressing the other information namely, in this
example, we are considering early voltage it is a very high. And we are primarily
focusing on this base current loss. So, in the next slide we do have the Beta-helper
circuit.
1196
So, here we do have the Beta-helper circuit drawn for you. We do have Q3 here and as I
said there this is approximately 0.6 and here also, it is approximately 0.6. So, we do have
1.2 V. So what we are doing here, to retain this current of 0.5 mA in this numerical
example, we are readjusting this RBIAS to 21.6 kΩ. And that gives us the IREF current, it is
same as 0.5.
So, let us see that our IREF = = = = 0.5 mA. So for our
comparison, better comparison we are keeping this reference current same as the
previous case. And then we can calculate the corresponding non-ideality factor.
So, you may recall the non-ideality factor in presence of the β the Beta-helper is. So,
non-ideality factor it becomes . And earlier, we have calculated in
( )
( )
absence of this one. Now, we do have 1 plus so, this part 99 + 1. So, this is 100.
So, that gives us a factor here 0.01 getting multiplied with β1 it is 100. So, it 0.01 +
this β2 is 150. So, = 0.02, right. = 0.03. So, that is equal to non-
ideality factor. So, it becomes and this is very very small compared to 1.
So, we can approximate that this = 1. In fact, how much is it coming? This is 1.0003
reciprocal so, that is equal to in fact, 0.9997. So, that is how this Beta-helper is helping
1197
us to maintain this ratio here, it is very close to 1∶3. So, similar to so, this circuit as I said
that it is improvised current mirror. Similar to this improvisation, we do have different
improvisation by adding something called cascode transistor to make the non-ideality
factor due to early voltage it will be very small.
So, we will be discussing that circuit, but before that let we take a break and we will
come back.
Thank you.
1198
Prof. Pradip Mandal
Lecture - 87
Numerical Examples on Current Mirror and its Applications (Part-B)
So dear students welcome back after the break. So, before the break we are talking about
the numerical examples of the current mirror. As you can see here, and there we have
used Beta-helper to improve the non-ideality factor coming due to the base current loss
namely, this base current loss. So in the next example, what we will see that
improvisation of the numeric current mirror circuit to take care of the non-ideality factor
due to early voltage.
To be more precise, we like to place one cascode transistor here and that improves the
output resistance of the current mirror.
1199
So in the next example, we are starting with MOSFET version and then after that we will
go to the BJT version. And so, here transistor-3 it has been added on the main current
mirror. So, the main current mirror it is constructed by M1 and M2 and whatever the
reference current it is coming, it is mirroring here.
And then we do have this transistor M3, to have meaningful operation of this circuit, we
require its gate voltage VBIAS, denoted here. VBIAS it should be sufficiently high. So, that
transistor-2 and maybe 3 also are in saturation region of operation.
1200
Now coming to the different sizes of different transistors given here, we do have for
transistor-1, we do have the it is 1 mA/V2. On the other hand for transistor-2 and
transistor-3, we do have = 4 mA/V2. This is just for a change, we are using different
values of the aspect ratio. Threshold voltage on the other hand, we are keeping it same
for simplicity of the calculation and also the λ of all the transistor it is not only for
transistor-2, but for all transistors.
Let we consider this = 0.01 V‒1 and then we do have the bias resistor which is 19 kΩ and
then VBIAS, it is 5 V. Here, it is 5 V and supply. This should be VDD. So, this is 12 V.
Now we need to find the value of this VGS1 and the current flowing here from whatever
the voltage 12 V it is given to us and then RBIAS, it is given there.
So to calculate that, in some of our previous examples we have done that this current
which is IDS1, it is also creating a drop here and after subtracting this drop, say
from 12 V supply, it is giving us the VGS. So, VGS1 = VDD ‒ IDS × RBIAS. And on the other
hand, we know that expression of IDS = of transistor-1 and then ( ) .
Of course, by dropping the rest of the part, so if I drop this part and what we have we do
have the expression of IDS here. So, we can put the expression of IDS here and then we
can make probably we can take the VDD on the other side. So, we can say that VDD ‒
VGS1 = RBIAS × IDS, an IDS expression it is given to us which is ( ) .
Now, we do have VGS need also need to be find out. So, what we can do for simplicity,
we let we consider we add Vth1 here, so that we can write this is ‒ with VGS1, but then
since we are adding it, we also have to subtract here the same Vth. So, we do have VDD ‒
Vth equals to this part and again, VGS ‒ Vth is also appearing here, in the second order
form.
So, if I consider VGS1 ‒ Vth = say x then, we can rewrite this VDD ‒ Vth. So, this part it is
12 V ‒ Vth it is given to us 1.5. So, that is 10.5 ‒ x ‒ RBIAS it is 19 and this part it is
here. So, we can and also we do have kΩ here and this is in mA.
So, again that is getting cancelled. So, we do have × x2. So, we can rearrange this
equation, we can write in the form of 19 x2 + 2 x ‒ 21 = 0. In fact, that gives us solution
1201
of this x which = ‒ 2. We have to consider only + term because, we are considering VGS
‒ Vth should be +ve.
In fact, that gives us solution x = 1. So that means, the so, this is equal to 1. So, that gives
us VGS1 = Vth + 1. So, this is equal to 1 + Vth is 1.5. So, that is equal to 2.5. So, we got
the voltage here it is 2.5 and the corresponding current if we put the value of this x = 1
here, then we do get IDS1 = 0.5 mA alright.
Now we need to find what will be the value of V2. V2 is the voltage coming here and
here we assume that both this transistor and this transistor, they do have which is 4
times than this one. Which means that the current flow here it is 4 times of this current
which is 0.5 here. And so that gives us IDS2 = 4 × 0.5 that is 2 mA.
So, if we do have this 2 mA current is flowing and the same current is flowing here also
and the VGS here it is same since dimensions of transistor-2 and transistor-3 they are
equal and if I assume transistor-3 it is in saturation region then the corresponding VGS
here it will be same as whatever the voltage you do have namely. 2.5.
So, if the VGS3 it is 2.5 then voltage coming here which is V2. So that is equal to VBIAS =
5 V ‒ VGS3 = 2.5. So, we do have DC voltage here it is 2.5. In fact, this the hint it is
given that we can consider both the transistors are in saturation and if we assume that
VDS of the 2 transistors that ensures that VGS3 = VGS2 because we do have same
transconductance of the 2 transistors.
Now so now we obtain, we have solved this part. Next thing is that for V3, if it is say 5 V
then what do you do expect? Here we do have 2.5 So, VDS3 So, V3 = 5 V that makes VDS3
it is also 2.5 right. And with this voltage, we can try to find what will be the
corresponding value of the output resistance Rout small signal output resistance.
So, I am going to erase this board to create some space for next calculation, but you
please keep in mind that the current flow in this branch it is 0.5 current flow here it is 4
times of that 2 mA.
1202
So, we need to find what will be the small signal output resistance. And Rout is gm3ro3ro2 +
ro3 + ro2. Note that ro and rds we are considering they are synonymous. Now ro2 in fact, all
the transistors we assume that λ = 0.01. So, ro2 it is = . And that gives us
the resistance equals to 50 kΩ. So same thing, ro3 = 50 kΩ.
And on the other hand, g m3 and as I said that the current flow here it is 2 mA and the
VGS DC voltage here it is 2.5 or VGS ‒ Vth is 1 V. So, that gives us the gm3 which is by
utilizing say, K value here of 4. So, we can say 4 mA/V. And hence the Rout we are
getting here it is 4 m × 50 k × 50 k + 50 k + 50 k.
In fact, this is becoming 10.1 MΩ resistance ok. So, that is the small signal output
resistance. Now utilizing this information, can we calculate what will be the current flow
in this branch IDS3 or you may call IDS2 also for V3 = 8 V? So, how do you calculate? We
can use this information we can use the information of the current at 5 V.
So we know that if V3 = 5 V, the corresponding current it was the corresponding current

here it was 2 mA and then if we increase this V3 from 5 V to 8 V due to output
resistance, it is having some slope here and we know that inverse of this slope which is
the output resistance it is given here. So, using that slope and this voltage change which
is 3 V we can find what the additional current here is. So, you may call this is delta of
this current. So, Δ of this current it will be = 3 × 10‒7 A.
1203
So, the corresponding current here at this point it is 2 mA + 3 × 10‒7 A. So, we can say
that this current = 2.0003 mA ok, now how do you get this voltage? Or so, this is this
circuit it is fine, we are getting very small change of this current because of this cascode
transistor. So, even though the voltage at this point V3 it is going from 5 V to 8 V.
Still we can see that the variation here the current variation it is very small and hence, it
is meaningful to add this cascode transistor. But then it is little inconvenient to get this
voltage and to overcome this problem, what we can do we can put a transistor here which
is also diode connected and that produces a voltage and that is normally that is what it is
getting applied.
So in the next slide, we do have that example. So, we are adding here transistor-4 to
generate this bias here ok. But of course, the voltage coming here it is now different from
whatever the voltage you do have. So for the same condition here namely, sizes of
transistor-1, now I have probably I have changed, yes. I have changed here just for a
change, we consider of transistor-1 and of transistor-4 they are = 2 mA/V.
On the other hand, for transistor-2 and transistor-3, we are retaining this to be 4 mA. Vth
we are keeping it as same and all the λ′s are 0.01 V‒1, supply voltage it is 12 V. So, we
can try to calculate what may be this bias resistor so that the current flow here it is 1 mA.
1204
So, how do you find that? If I know this current is 1 mA, probably from this dimension,
we can find what is the corresponding VGS1 required and the VGS4 required. And then
from that you can find what will be the voltage here and then we can see what the drop
here is and from that we can calculate R BIAS.
So, 1 mA of IDS1 equals to its corresponding K which is mA/V2 × (VGS ‒ Vth)2. Again
we are dropping ( ) part. So, this is giving us VGS1 ‒ Vth = 1 V. And hence, VGS1
= 1 + 1.5 that is 2.5 V, and this is also giving us VGS2 = 2.5 V.
So, that gives us the voltage here it is 2.5 and 2.5, so that is 5 V. In fact this 5 V, it is
nicely getting generated for making a suitable bias for transistor-3 and RBIAS = ,
right. So, that is giving us 7 kΩ.
So that is how we can set this resistor. So that the current here in the left branch it is 1
mA. Now, we can try to find the value of this IDS3 in same way and here now the ratio
aspect ratio of transistor-3 channel and transistor-1 channel it is 2. So, the IDS2 = (IREF 1
⁄
mA) × .
⁄
So, that is 2. So that is giving us 2 mA. So now we obtain this part and this part we can
calculate the small signal output resistance similar to whatever the way we have done.
So, output resistance here it will be in fact, since the current here it is remaining same
and this is also remaining same. So, we are expecting that output resistance Rout.
So, here also it will be 10.1 MΩ. So, next question is that what is the minimum value of
this voltage here voltage here, so that we can enjoy this high output resistance. In other
words, what should be the minimum value of this voltage so, that transistor-3 it is
remaining in saturation region of operation?
So, we know that the voltage here it is 5 V. So, the minimum voltage here we required it
is 5 V ‒Vth. So, the minimum voltage here it will be, 5 V is the gate voltage here, Vth is
1.5 V. So, that is equal to 3.5 V. So, as long as this voltage it is higher than 3.5 V then
we do get output resistance, it is very high. So that is how we can make the output
current very less sensitive to the voltage for improved current mirror or which is referred
as cascode commonly known as cascode current mirror. And similar thing it can be done
for BJT also. So in the next slide, in the next example-6, we will see that.
1205
So here as we have done before, we have added transistor, transistor Q3 to get higher
resistance here and making this current insensitive to the output voltage variation. And
instead of giving a bias here, independent bias here, similar to the previous circuit
example, in MOSFET, we have added transistor-4 in diode connected form so that we
can internally generate a voltage here, suitable voltage here. Now here the dimensions,
the information of different transistors are given; namely, we consider these 2 transistors
are identical having reverse saturation current of 9.5 × 10‒14 A.
On the other hand transistor-2 and transistor-3, they are identical having the reverse
saturation current which is 19 × 10‒13 A which is just 2 times of this current. So, we can
say that the reverse saturation current ratio here it is 1∶2. Supply voltage it is 12 V. So,
the 1st part we need to find what will be the bias resistor. So, the current here it is 1 mA.
Now, here for BJT getting the voltage here it is much simpler, we can always
approximate that VBE(on) is very close to 0.6. So if this is 0.6 and then we do have one
more 0.6. So the voltage here it is 1.2 V. So, that gives us the RBIAS = .
So this is equal to 10.8 kΩ. So, for the subsequent part we can use the same RBIAS to
maintain this current 1 mA. Next thing is that we need to find what will be the; what will
be the small signal output resistance and then we can calculate what will be the
corresponding current here for V3 = 1.2 V and 5.2 V.
1206
So for if I consider say, V3 = 1.2 V, this is also 1.2 V. So that makes VCE here and VCE
here, they are similar. So what we can see that both transistor-3 and transistor-2 they are
in active region of operation and that makes the corresponding current particularly,
whenever this is 1.2 V and voltage here and voltage here making 2 VCE voltages equal.
So, that gives us IC3 particularly for this case equals to just IS ratio × (IREF is 1 mA).
And hence this is since the IS ratio it is 2. So, we can see it = 2 mA. Now once we have 2
mA of current, probably we can get the value of the Rout and the corresponding
particularly ro and then gm and then we can find what is the corresponding output
resistance of the current mirror.
So, to calculate let we consider ro2 = . So, that gives us 25 k. In fact, this is
true for ro3 also. So that is equal to 25 k. On the other hand, gm of transistor-3. So, this is
equal to , thermal equivalent voltage we can consider this is 26 mV, VT.
So, we can say this = ℧. In fact, that gives us the output resistance Rout = gm3ro2ro3 +
ro2 + ro3. In fact, what we can get here it is ok, let me use this space here. So, gm3 it is
and then we do have 25 k × 25 k. So, this is this much of MΩ plus we do have

summation of this 2, 25 k’s. So, that is 50 k probably that you can ignore.
In fact, you may calculate this one, but I think I do have some calculated value for you.
So, this is becoming 48.127 MΩ. Note that here I have ignored the rπ here, otherwise, I
should have to consider instead of only this one. I should have to consider ro2 ⫽ rπ2, but
this node it is not ground. In fact from here to here I do have and also we do have .
So, I should have considered rπ3 in series with + , instead of this one. But since
we have considered β is very high, we may say that this is infinite and as a result, I have
dropped this part and that gives us much higher of resistance. Practically, you have to
consider this rπ, and its value it may be much lower than this resistance. It may be in the
range of say 1 k to 2 k.
In fact, if I multiply this rπ3 with gm3 so that gives us the β of the transistor and the
corresponding resistance it may vary, but even then this resistance it may be in the order
1207
of few MΩ. So anyway, for this numerical example since the output resistance it is here,
using this output resistance information, we can calculate the variation of this current. If
we vary this V3 from 1.2 V to 5.2 V; that means, a voltage variation of 4 V.
So for this voltage, for this voltage of V3 we can calculate the corresponding IC3 = 2 mA
+ (Δ V which is 4 V)/48 MΩ. So, . And in fact, again I have done the calculation
for you and this is coming 2.00008 mA. That is again very close to whatever you do
have.
So, that indicates that by adding this cascode transistor since the output resistance is very
high, the variation here it is very small. So, this is again it is called the cascode current
mirror and by adding this transistor, we are getting the advantage. Now coming to other
kind of example instead of considering only the current mirror, if we consider some
circuit where we have used the current mirror namely, in common source amplifier as
well as in common emitter amplifier where we have use the current mirror to create the
active load.
So in the next example, we do have common source amplifier I guess, yes we do have
common source amplifier where we have the load part it is active load here, input we are
feeding to transistor-1. So, transistor-1 it is working as the main amplifier and then
transistor-4 it is working as an active load. But then this active load it is getting biased
from or through this current mirror.
1208
And our calculation of this numerical example is to find that how do you set the different
meaningful value of these resistors and then current mirror. So, to start with, we do have
the value of of different transistors namely, transistor-1 and transistor-2. So we do
have transistor-1 and transistor-2, we are assuming they are identical. And on the other
hand, transistor-3 and transistor-4, they are PMOS transistors.
They do have different value of this transconductance factor, but they are same, they are
this transistor-3 and transistor-4, both of them are having this factor = 0.5 mA/V2.
Let we consider Vth for all the transistors. So whether it is NMOS or PMOS, it is 1.5 and
λ for all the transistors = 0.01 V‒1, supply voltage it is to 12 V. So, the first part we need
to find what is the ratio this potential divider so, that it creates a voltage here, such that
the current flow here it is 1 mA. So, how do you find? We need to calculate what is the
VGS required here to get 1 mA of current flow.
So again, if you use this information and the 1 mA of current requirement, you can find
that VGS ‒ Vth = 1 V and that gives us VGS1 = 2.5 and that gives us the ratio of =
= or we can say this is .
So, if we use this ratio for this part also, and that also sets this current = 1 mA ok. So, we
are using the same value of this ratio and for the subsequent part, let we consider this
ratio. Now we need to find next step it is we need to find the small signal output
resistance and the voltage gain. So, we are expecting this will be setting the current here
right, which is 1 mA keeping both transistor-1 and transistor-4 in saturation region of
operation.
So, the ro of transistor-1 = = 100 kΩ. Likewise, ro4 it is also 100 kΩ and that
gives us the output resistance of the amplifier = (ro1 ⫽ ro4) = 50 kΩ.
Now to get the voltage gain, we need to calculate g m of transistor-1 and again, by
utilizing this information and VGS we do get this is equal to 2 mA/V and that gives us the
voltage gain AV = ‒ (2 mA/V) × this Rout which is 50 k and that gives us a gain of 100.
So, we got the voltage gain, we got the output resistance.
1209
Next thing is that what is the DC voltage? We know that these 2 currents, they are equal.
But both of them are having very high resistance, but we need to know what may be the
precise value of this voltage. Will it be 6 V? Which is half of this voltage or something
else? We can keep that in mind that the current flow here it is 1 mA. There we have
ignored ( ) part and to define this voltage, we need to consider this ( )
part to get the precise voltage.
In fact if you see it carefully, the current flow through this transistor and this transistor
they will be equal if their corresponding VDS they are equal, right. But then VDS of these
2 transistors if we see, VDS of this one output node voltage since it is very sensitive and
its output resistance is very high. It may be difficult to get, but then voltage getting at this
point is not so difficult because this transistor-3, it is diode connected.
In fact, if you calculate what may be the VSG of this transistor by considering its size here
and the corresponding current here, you can find that (VSG of transistor-3 ‒ Vth of
transistor-3) since it is PMOS we should consider magnitude. In fact, this is equal to
since the current is 1 mA, but then it is 0.5; (VGS ‒ Vth)2 = 4 and VGS ‒ Vth, is
becoming 2.
So that gives us I should say VSG because it is PMOS. So, VSG3 = 2 + the threshold
voltage 1.5. So, that gives us 3.5 V. So that sets this voltage here, 12 ‒ 3.5 and this
voltage it is 8.5 V. In fact, if this voltage it is 8.5 and this is also 8.5, then only this 2
current they will be equal.
In other words, this current flow of this transistor and current of this transistor they are
matched whenever these 2 voltages they are 8.5 and transistor-3 and transistor-4 they are
also nicely supporting this conclusion that output voltage if it is 8.5 then the currents are
equal.
So, from that argument we can say that DC voltage, output DC voltage instead of 6 V it
is rather 8.5 V. It is not 6 point right. So, similar kind of exercise we can do for the
common emitter amplifier.
1210
So in the next slide we will be having this common emitter amplifier, but then again, we
need to take a break. So, after the break we will come back.
Thank you.
1211
Prof. Pradip Mandal
Lecture – 88
Numerical Examples on Current Mirror and its Application (Part-C)
Dear students, welcome back after the break. So, we are going through different
numerical examples and now we are going to talk about one common emitter amplifier
which is using current mirror and particularly to bias the active load say Q4. We are
using current mirror and transistor-1; it is the amplifying device then we are assuming
that Q1 and Q2 they are identical and also we are assuming that whatever this Q3 and Q4
are also identical.
So, to get the IC current of transistor-1 and collector current or transistor-4 equal. We
want the current flow through transistor-2 should be equal to current flow through
transistor-1. And since, Q1 and Q2 are identical having the same β value of 100. So, then
the value of this resistance bias resistance, based biased resistance R1 should be identical
to this transistor the resistor R2.
So, that the base current here and base current here, DC base current they should be
equal. So, also we do have othered information namely all the devices are having early
1212
voltage 100 V and with this information let we try to find what will be the value of this
resistance to get the collector current IC1 = 2 mA.
So, since the β is 100 so, the IB it is should be = 20 µA. So, to get the value of this R1 to
get 20 µA, the R1 should be = = . So, this is . So, that = you know
570 kΩ. So, the value of this resistance as well as this resistance they are = 570 kΩ.
So, with that we do have this current is also 2 mA and if we assume that the base current
loss it is ignorable, then you can say that collector current of transistor-3 it is also 2 mA
which is getting mirrored to transistor-4, so, that is making this current also 2 mA. So,
that is how these 2 currents; currents of transistor-1 and transistor-4 they are getting
matched.
Now, with this information let us try to find the small signal output resistance and
voltage gain of the amplifier. So, we are assuming both the devices are in active region.
So, the output resistance Rout = ro1 ⫽ ro4. Whereas, this ro1, ro1 = = . So, that is
giving us 50 kΩ.
So, same thing we can get for transistor-4, ro4 = 50 kΩ and that gives us 25 kΩ. So, the
output resistance it is 25 k. Now we like to get what will be the gain of this amplifier. So,
the gain of the amplifier of course, the voltage gain of this amplifier it is gm1Rout with a ‒
sign. So, what is the value of the gm1?
So, that is , that is the VT given there. So, this = ℧. So, the voltage gain so, the
voltage gain it is , it is close to 2000 rather yeah.
So, the gain it is coming 1923. So, that is the voltage gain we are getting. So, as it is
expected that since we do have active load. So, the gain it is expected to be very high and
the output resistance is also high. Now, next part of this question it is to find DC output
voltage we need to consider this VA, the early voltage very carefully ok. Now let me
clear the board and then again we will talk about the DC voltage.
1213
As I said that the current flow current flow here and here should be equal and if you see
it carefully the DC voltage here it is defined by this Vcc ‒ VBE drop. So, I should say the
voltage here it is. So, this is 12 V. So, the voltage here it is 12 ‒ 0.6 so, that is 11.4 V.
Now, with this 11.4 V here we can say that whatever the current we do have. So, that
may be 2 m which is of course, 1 approximation that we are assuming ( )=1
please stop here.
So, the current flow here it is to be more precise it is 2 mA×( ) = 2 mA×( ).
So, whatever the current. Now if you see this current is getting mirrored here ignoring
the base current loss here, because for transistor-3 and transistor-4, we have considered
their β’s are very high.
So, they are identical, this information it is also given. So, we can assume that the
collector current of transistor-4 it is same as collector current of transistor-3. So, IC4 =
IC3. So, this IC3 as I said that this current is also equal to this and on the other hand this
current the collector current of transistor-1 it is also 2 mA × this kind of factor ( ).
So, if this voltage here it is say 11.4, then you can say that this current and this current
they are becoming equal. In in intuitively also you can say that if this voltage it is 11.4.
So, that makes the current here and current here, they are equal and also the current flow
in transistor-3 and transistor-4 they are equal. So, that makes everything is consistent.
1214
So, that gives us the DC output voltage VOUT = 11.4 V right. But of course, if the values
of early voltage or in case we cannot ignore say this base current and then of course, the
corresponding the current here and here there will be a mismatch and the DC voltage
here it will deviate from here. So, in the next numerical example it is continuation of this,
the same example, but considering finite value of this β of transistor-3 and 4 will be
giving us a situation where we need to consider mismatch of the 2 current and then we
can try to find what will be the change of this output voltage right.
So, in the next slide we are going to talk about that yeah. So, as I said that the problem
here it is very similar, except that transistor-3 and transistor-4 they do have β = 250.
Now, here we can try to find what will be the current IC1 and IC2 at VCE = 11.4. Why
11.4? As I say that is the voltage here it is 11.4 and supposes if we make this voltage also
11.4, then we know this current and this current they will be equal. And just now we
have calculated that IC1 = 2 mA. In fact, that is the base current 20 µA × β that is 100 ×
( ).
In fact, if you do the calculation here what you will get it is the 2 ×1.114. In other words,
this is 2.228 mA. In fact, this is same for IC2 also. So, IC2 also = 2.228. Assuming that
VCE2 it is 11.4 V. We can also try to find what will be the corresponding current here in
transistor-3 and a transistor-4. If we ignore the base current loss, then we are expecting
that this current and this current it will be same. But we do have some loss here so, to get
1215
the IC3 what you can say that IC2 now it is working as the reference current for this
current mirror IREF.
So, IREF = IC1 and it is value it is given here. So, IC3 = IREF × . So, we do have
2.228 × yeah. So, this is becoming = 2.210 mA.
Now, the same current, same current it is also flowing through transistor-4 as they are
identical. So, now, you can see that if we try to hold this voltage at 11.4, then the current
flow here it is 2.228. On the other hand, the current coming from transistor-4 it is 2 on
the other it is 2.210. So, we do have some excess current requirement and so, that current
it is point so, we do have additional requirement here. So, that current is 2.228 ‒ 2.21.
So, additional 0.018 mA of current we are looking from this node.
Now where this current it will be coming from. So, of course, we do have in the small
signal equivalent circuit we do have ro4 which is connected to the supply. And then also
we do have ro1. In fact, these 2 together you may say that it is providing ROUT and the
other end of the ROUT, it is connected to 11.4 V. So, as we are looking for this excess
current, there will be a change of this voltage with respect to 11.4 V by an amount of so,
if I say ΔVOUT. So, this ΔVOUT it will be 0.018 mA multiplied by whatever the output
resistance.
We have calculated the output resistance it was 25 k. That gives us a voltage difference
or voltage variation which = 25 k × 0.018 mA = 0.45 V. So, the voltage here at the
output the DC voltage = VOUT = 11.4 ‒ 0.45 = 10.95 V. Why it is ‒? That is because we
are demanding more current here so, naturally the voltage it will be coming down.
In case if this current it is higher than the current flow through transistor-1 for 11.4 V
DC, then the corresponding voltage here it would be higher +ve. So, in this case since the
current flow here it is more. So, we do have reduction of the voltage and it is finally,
going to this one. So, yeah so, we have calculated these 2 currents and then also we have
calculated this non ideality factor. In fact, this is the non-ideality factor is . And then
the corresponding DC voltage it is given here yeah. So, that is how you can approach.
So, here what we have seen that precision level or these 2 currents are important,
otherwise this voltage it may be having a big change. See suppose this the early voltage
1216
here and early voltage of the other transistor if they are having mismatch then also it is
expected to have mismatch of these 2 current leading to significant amount of variation
of this output voltage.
This may be a case when the output node it is high impedance node. So, even a small
mismatch of the current may lead to significant amount of voltage variation. In this case
though this variation it is not much, but there may be a situation in practical situations
this difference it may be so large, probably 1 of the transistor may be pushed towards the
saturated condition or saturation region of operation. So, we need to be little careful.
Now let us go into different types of examples or application circuit of current mirror
namely. Differential amplifier. So, in the next example, example-9; we will be talking
about differential amplifier where we are using current mirror yeah.
So, here is the circuit first of all we do have the main differential amplifier and then we
do have the bias circuit here. In fact, if you see here the bias circuit it is having number
of current mirror. So, Q4 and Q5 they are forming a current mirror, Q4 and Q3 they are
also forming a current mirror and whatever the current is flowing here that is again
getting mirror to transistor-7 as well as transistor 8 and the corresponding diode
connector transistors Q6a and Q6b together it is mirroring the current. In fact, this circuit
we have discussed in a while we have analyzed the circuit. Now let we go into it is
numerical calculation. What we have the information given here it is transistor yeah.
1217
So, transistor-1 and 2, they are well matched. So, since it is differential amplifier so, we
are looking for that. And then Q3, Q4 and Q5 they are also identical. So, they are also
matched NPN transistor. On the other hand Q7, Q8, they need to be identical for
differential amplifier of performance point of view. In addition to that Q6a and Q6b
individually they are also identical to Q7 and Q8. So, I should say all the 4 transistors
they are identical.
Now, the moment we make transistor-6; 6a and 6b parallelly connected, namely they are
collectors they are connected together emitters are connected together and base also they
are connected together. So, you may equivalently say that we do have 1 transistor which
is say Q6 which is similar to or it is identical to a parallel connection of this transistor,
assuming that the IS of this transistor it is 2 IS of individual Q6a and Q6b.
So, we may say that this current mirror it is mirroring the current with a ratio of 2∶1
rather whatever the current we do have here IREF. So, half of that current it will be
flowing here and another half it will be flowing there. So, that is that is what we have to
keep in mind.
Now, here in this circuit the bias resistored it is given to us that is 11.4 k and then supply
voltage of course, this is 12 V and thermal equivalent voltage it is 26 mV and VBE1 as
usual we are taking 0.6, early voltage it is 100 V and let me assume that β of all
transistors they are quite high. So, we can ignore the base current loss.
1218
In fact, many of the bias circuits we may not be looking for precision level of the current
we like to get nominal value of the current and to get that we can many a times we do
ignore the effect of β. Anyway, so, this is given to us and let we calculate the reference
current here and then let we calculate the current through all the other transistors. So,
how do we proceed? First of all, the current flow through this RBIAS.
( )
So, RBIAS it is we may call IREF, IREF = = = 1 mA. For simplicity that
why I have picked up the value here. So, that the reference current here it is 1 mA. Now
we do have transistor-5 and transistor-3 they are well matched with transistor-4. So, we
can see that this current is 1 mA same thing here also.
Now, you may consider this early voltage and then you can precisely get the value of this
current, but many a times we may rather ignore that precision level. So, we can consider
this nominal current of 1 mA it is flowing through both these transistors. And as I said
that this diode connected transistor it is mirroring the current in the ratio of 2∶1. So, half
of this 1 mA. So, that is 0.5 mA. It is flowing through transistor-7 and likewise 0.5 mA
current is flowing through transistor-8. Now if I say that we do have meaningful DC
voltage here and here. So, that is what we said meaningful input common mode bias you
do have then current flow here and current flow here they are identical. So, I should say
half of this current is coming through transistor-1 and the other half it is coming through
transistor-2.
1219
So, current flow here it is 0.5 and here also it is 0.5 mA. In fact, this 0.5 mA it is
consistent with the current flow through-7 and 8 respectively. So, that makes the current
flow through transistor-5 and transistor-3 = 1 mA. On the other hand current flow
through transistor-7 then IC8 = IC1 = IC2, all of them are approximately 0.5 mA.
In fact, current flow through transistor-6a and 6b, they are also = 0.5 mA. With this
information now we can try to say that we can calculate what will be the gain and since
the nominal currents they are consistent we can assume that all the transistors namely Q1,
Q2, Q7, Q8 and Q3 are in active region of operation. So, in the main circuit, we are
keeping all the devices in proper region of operation then we can calculate the small
signal gain.
So, in the in the next slide as you have done before, once you know the operating point
then we can calculate the small signal gain. So, this part we already have done. So, in the
second part; we need to find the differential mode gain and common mode gain. Here we
do have the small signal equivalent circuit where we do have of course, we are not
showing this rπ1 and rπ2 and transistor-7 and 8, they are giving ro7 and ro8.
We do have ro1 and ro2 and a current flow here it is gm1vbe1 and gm2vbe2 here. And then
transistor-3, it is having resistance of ro3 and as we have discussed before for this circuit
the voltage differential mode gain Ad = gm1(ro1 ⫽ ro7). And gm1 it is Ic so, that is 0.5 mA
divided by 26 mV multiplied by these 2 resistances. So, what is the value of this
1220
resistance ro1? ro1 = = 200 k. So, likewise ro7. So, this 2 together it is
giving 100 k. So, the gain here it is.
So, if it is close to 2 or 1.9 something, 1.9 × 103. So, that is the gain, differential mode
gain. On the other hand the common mode gain it is the expression it is and ro7, it is
200 k on the other hand ro3 it is = 100 k. So, that gives us = 1 of
course, with a ‒ sign. So, that is how we can get the common mode gain and differential
mode gain of this circuit. We can also work out on differential amplifier having current
mirrored using MOSFET, probably I do have that in the next slide.
But before that instead of using the load connected through a current mirror, we may
have current mirror load within the circuit itself. Namely, M7 can be made diode
connected and it is corresponding current it may be coming to the output. So, in the next
example, what we have it is the circuit where transistor-7, it is diode connected and that
current it is getting mirrored to transistor-8.
So, yeah so, here it is the circuit. Let me take a short break and then again will be
resuming here.
1221
Prof. Pradip Mandal
Lecture – 89
Numerical Examples on Current Mirror and its applications (Part-D)
Yeah. Welcome back to our next example. So here we do have the differential amplifier
and the load of course, it is active load, but internally we do have current mirror. So,
what we are expecting here it is transistor-7 DC wise it will be mirroring its own DC
current into transistor-8 and that is good. In fact, we want this current should also be
same as this 1 from balance point of view. So, we do not have to put any external circuit
to bias here and in addition to that this transistor-7 it may also mirror signal current, in
case if we have say gmvbe current it is coming here at the collector.
So, that current is also getting mirrored here. So it is expected it is expected that the
signal it is whatever the differential signal or common mode signal, it will be arriving to
this output through this transistor-2 as well as through transistor-1 and then through the
current mirror. So, we will see the consequence in this numerical example I hope you
recall the analysis we have done for this circuit.
So, in the numerical examples we will be reestablishing the same thing, to start with we
do have to find the DC currents through all the transistors.
1222
Again the value of this resistor it is 11.4 k, so that makes this current = 1 mA. So, the
current flow here it is also 1 mA and if we are applying meaningful input common mode
DC then half of the current is flowing here and remaining half it is here. So, each one of
them it is 0.5 mA so this 0.5 mA it is getting mirrored here. So, the current flow here it is
0.5 through transistor-7 as well as transistor-8.
Now yeah so it is now it is pretty straight forward so if you if you ignore this early
voltage to calculate the nominal quiescent current, namely ( ) if you consider it ≈
1 for DC condition DC current. Then the circuit analysis it becomes really simple and
also we like to say that since this is transistor-7 it is diode connected.
So, the voltage here it is decided by the 12 V ‒ 0.6 V so the voltage here it is 11.4 V. In
fact, it can be shown that the DC voltage at this point assuming Q1, Q2 identical Q7, Q8
identical it is also 11.4 V. So, I should say DC voltage at output-1 and output-2 both are
11.4 V, now with this information let we calculate the small signal gain namely
differential mode gain and common mode gain in the next slide.
1223
So, yeah so now our next calculation it is we need to find differential mode gain and
common mode gain. And here we do have most of the small signal model this part of
course, we are in the small signal model we are removing we are keeping only ro3 and on
the other hand for transistor-8 we do have ro8 and then ro7. In fact, since it is diode
connected we should also give this ro7 ⫽ .
So, the voltage coming here vo2 it is predominantly it will be defined by and
whatever the signal current is flowing through this. So, approximately we can say that
this resistor it is , so then whatever the voltage it is producing here that voltage it is
also deciding the vbe voltage of transistor-8.
So, through the transistor-8 there will be a current flow, signal current flow and this
signal current flow. Of course, it will be it will be corresponding gm8 × vbe here which is
it is basically this is vo2 because this node it is ground.
So, the voltage vbe voltage it is gm8vo2, so in in summary now to analyze this circuit we
can just simplify and saying that this resistance it is this is ro8.
1224
But in addition to that we do have a current flow here which is gm8vo2 and then we do
have ro1, ro2 then we do have gm1vbe1, so this is vbe1 across this rπ so vbe1 here.
So, likewise here we do have vbe2 so vbe2 gm2 it is giving the current here. And to get the
differential mode gain what we can say we can make this voltage = and this voltage
on the other hand it is ‒ . And in fact, this is common node this is common node the
impedance looking into this device and this device. If I ignore this part strictly speaking
they are not same, the impedance looking into the source of transistor-1.
It is smaller primarily because at its collector we do have a smaller resistance compared

to whatever the resistance we do have. In fact, there may be a detailed calculation by
which you can find that this voltage it is tilted towards Vdd, compared to ‒ . If
the 2 resistances they are equal then only you can say this is AC ground, but whatever it
is we may say that it is having vs voltage that makes this vbe voltage which is this ‒
vs.
On the other hand the voltage here it is ‒ and then ‒ this vs and then that produces
this current. And this current it is producing a voltage compared to this impedance we
may ignore this ro1 even though it is connected to this node which is having the signal,
1225
but as the signal here it is very small. We may see that output voltage vo2 it is well
approximated by gm1 × .
So, that is the impedance at this node and then minus I should not say s let it be ve
because this is common emitter voltage. So, that is the voltage you do have here so the
current flow at this node on the other hand it will be gm8 multiplied by this voltage which
is with a ‒ sign multiplied by ‒ ve. So, this is the current at this point in addition
to that we do have this current also, so we do have gm2 and then we do have ‒ ‒ ve.
So, this is the total current and if I multiply this current by the impedance at this node
which is practically it is ro8 ⫽ ro2, so that gives us the output voltage vo1. In fact, if you
see here gm7 and gm8 we may cancel it out and if I consider gm1 and gm2 they are equal
then this we do have a ‒ sign here and ‒ sign here that makes it is plus and here you have
‒ sign so we can say even this part is also getting removed. So, with this approximation
what you are getting here it is gm1 so we do have gm1 here and then of course, with a ‒
sign here because the current is departing this node.
So, we will be having a ‒ sign so this ‒ sign and this ‒ sign and this ‒ sign they are
getting converted into +. So, eventually gm1 or gm2 × vin_d, multiplied by this net output
resistance which is practically ro8 and ro2 in parallel. So, if I say that final output voltage
if I call this is the net output voltage vo1 by differential input here which is equal to
gm1(or)2 × (ro8 ⫽ ro2) on the other hand the voltage at this node vo2.
So, vo2 on the other hand so this is equal to it is very small so whatever the voltage you
do have that is getting multiplied by gm1, but then that is again multiplied by . So, this
is ‒ ve, but whatever it is these two gm′s in the same order of magnitude as a result
you may say that this voltage it is very small compared to vo1. And if I say that output
voltage differential output voltage vo_d defined as vo1 ‒ vo2.
So, all practical purposes it = vo1 and then the expression of vo1 it is given here to find the
gain differential mode gain Ad. So, that is equal to that is defined as and that is
given by gm1(ro8 ⫽ ro2). So, numerical value to calculate numerical value let we consider
let we calculate gm1 and ro8 and ro2.
1226
In fact, we already have done this calculation gm1 = . And so this is this much of more
and ro2 = 200 k also ro8 = 200 k and that gives us the differential mode gain = 0.5 × ×
103 = 1923 to be more precise.
So, that is the differential mode gain, on the other hand the common mode gain. So, the
common mode gain it is essentially it is a bit tricky.
1227
Here we do have this resistor it is practically , and if we apply same voltage here and
same voltage here namely vin_c. So, that makes this voltage and this voltage to be equal
so, even though we do have ro8 connected here. But we do have voltage dependent
current source which depends on this voltage, making this node very insensitive or a
smarter way to calculate their common mode voltage we can say that common mode
gain.
Essentially, it is and in this circuit since we are applying same voltage here and here
vin_c with same polarity. In that case this node of course, it is remaining high impedance
or rather I should say degenerated node. So, we do have this resistored remaining there
and it is degenerating the circuit and this gain as you have discussed before it will be the
gain of this circuit which is getting degenerated by ro3 or if I split the circuit it will be
rather 2 ro3.
So, the corresponding gain here it is gm1 × so that is the impedance here divided by 1
+ gm1(2ro3). In fact, after removing this 1 you can remove this gm1 also, so that gives us a
common mode gain = . In fact, gm7 it is given to us and also yeah so it is
becoming this is .
So, that gives us how much 26 × 10‒5. So, the common mode gain it is really very small,
so that makes this circuit it is having differential mode gain it is good and then common
mode gain it is quite low, the similar kind of circuit can also be constructed using
MOSFET.
1228
So, in the next slide we will be talking about that so here again we are assuming that
these two transistors, these two transistors they are identical, these two transistors they
are identical here and the load part also it is active current mirror load and they are also
identical. And the supply voltage it is 12 V, bias resistor it is 9.5 k and let we consider all
the λ′s are 0.01 V‒1. Threshold voltage of all the transistors it is equal to 1.5 the analysis
part it will be very similar to the other circuit.
We just now we have discussed having BJT implementation, but probably the DC
operating point may be little different. So, let we calculate the DC operating point we do
have 12 V supply here and we do have the size of transistor-4, it is given here rather
transconductance factor it is 4 mA/V2. If we calculate it carefully what you can get here
it is the current flow it is actually it is equal to 1 mA.
So, 4 is it 1 mA this is 3 and 4 they are equal that is fine let me calculate this one. So, we
do have the VDD ‒ VGS4 and so that = RBIAS × IREF.
So, this IREF on the other hand it can be defined by this transistor so we do have RBIAS ×
×( ) . And so here what we can do we can yeah so we can add one Vth and
then subtract one Vth. So, we can say VDD ‒ Vth ‒ (VGS4 ‒ Vth) = 19 ( ).
So, from that we can find what will be the corresponding x so we do have 19 x2 + x ‒
10.5 = 0. So, from that we can find what is x and then you can consider this two are
1229
having current mirror so; obviously, then you can find what will be the current flow here.
And then half of the current it is flowing here, so then here also the corresponding
current it will be half of that.
So, that is how we can precede probably you can work it out and once you get the
operating point then you can find the differential mode gain. Which is again gm1(ro2 ⫽
ro8) and the common mode gain on the other hand it is Ac = ‒ . Probably you can
( )
work it out so since it is similar kind of example so I will skip that part.
So, yeah so this is and then you can probably you can find what will be the numerical
value.
1230
Now, coming to the conclusion of this entire session it is what we have talked about
basically we started with numerical examples of simple current mirror. And we have
calculated the different transistor current there and then we have talked about numerical
examples of improvised current mirror namely the beta helper and then cascade current
mirror.
And then we have talked about different numerical examples on amplifier starting with
common emitter and common source amplifier, having current mirror as its load. And
then we have talked about differential amplifier implemented by BJT as well as the
MOSFET. And then there we have considered how to calculate the quiescent current of
all the transistors and then we have calculated the differential mode gain and common
mode gain, I think that is all to share with you thank you for listening.
1231
Prof. Pradip Mandal
Lecture – 90
Feedback System (Part–A)
So, students welcome back to our online certification course on Analog Electronic
Circuits. Myself Pradip Mandal from E and EC department of IIT, Kharagpur. Today’s
topic of discussion it is Feedback System. So, we shall start with basics and then
gradually, we will be moving to practical circuit.
So, the based on our plan overall plan, we are in modules in fact, whatever the concepts
we will be talking it is primarily on analog modules and today we are starting this week-
10. In fact, it is module-9 and as I said that we are going to talk about feedback system.
We are going to start with basic feedback theory. And then today, we will be able to
cover four different basic configurations of feedback system. In fact, four different basic
configurations of feedback systems we will be discussing.
And these four basic configurations are generic enough; it can be deployed in other
configurations as well.
1232
So, the concepts we are planning to cover today, it is the we shall starts from basics of
feedback system. And then, we shall talk about types of feedback systems, basic types of
feedback system and then we shall derive transfer characteristic of feedback system. And
then we will be focusing on four different distinct configurations of feedback systems.
To start with the basic concept of feedback system so, far we are talking about
amplifiers.
1233
In fact, different amplifier configurations and those amplifiers are essentially linear
circuit. So, we can say that at the input, we are applying input signal either it may be in
the form of voltage or current. On the other hand at the output, we are observing the
corresponding amplified version of the input signal and this A represents the
amplification factor.
So, this is I should say basic model of whatever the amplifier we have discussed. This
input need not be single ended, it can be even differential and we know the signal it is
propagating from left to right from the input port to the output port. Whenever you are
talking about the feedback system, what we are trying to do, we are essentially sampling
this signal and part of it we are taking back and we are given to the input.
In fact, while we are taking this feedback signal from the output, we also have to retain
the corresponding input port primary port for feeding the signal. So, whatever the
feedback signal, we have to generating here, let we call it is say signal-f and the primary
input we do have say maybe S. So, this signal S and this signal need to be combined
together to generate this input signal for the amplifier.
So, if you see the model we use, it is given here from this point to the primary output, we
do have the forward amplifier take which is taking the signal from left to right and then
part of this signal or maybe this entire signal we are sampling. And then we are
generating a part of this signal by this circuit called feedback path or feedback network
to generate the feedback signal.
And this feedback signal, we are combining with the primary input signal to generate the
input signal of the forward amplifier. So, we required some mixer here to mix this signal
and this signal and while you are mixing the signal, we want to retain the linearity only
option we are keeping here it is the signal may be coming from this port to this port
either in same phase or opposite phase; likewise this signal while it is coming to the
input it may have its ±.
So, we can say that this mixer predominantly it is not amplifying or attenuating, it is
rather either multiplying with + 1 or ‒ 1 and then combining the primary input signal and
the feedback signal to generate the input signal for the amplifier. So, that is the basic
model of feedback system; this feedback system we will be coming back again and
again.
1234
So, if you see this in this feedback system what are the basic modules we do have first of
all we do have forward amplifier. So, this is called forward amplifier which is taking the
signal from left to right and then we also have feedback path. So, we do have the
feedback path here through which, we are taking the primary output and bringing the
signal back to the input port of the amplifier. So, we do have the feedback path and its
transfer function it is β for forward amplifier the transfer function it is A.
And then also we do have signal sampler. So, whenever we are tapping this signal, we
are calling this is sampler signal sampler and then also we do have signal mixer. So, here
we do have the mixer which is mixing the feedback signal along with the primary input
to generate the input signal for the amplifier ok.
So, let us talk about more about this feedback system and how we are primarily mixing
based on that and also the polarity of the transfer function of the forward amplifier and
feedback path. The system can be classified primarily into two types; one is ‒ve
feedback system and +ve feedback system.
1235
So, what we said is that, the basic types of feedback system it is, we make say it is ‒ve
feedback system or +ve feedback system. So, when we call it is ‒ve feedback system?
Suppose, in first of all it is having a feedback, whether we call it is +ve or ‒ve.
So, the signal it is looping around this path which is going through this forward amplifier
and also it is going through the feedback path and of course, we do have sampler and
mixer. Now, based on the feedback signal coming back, we may call either it is ‒ve or
+ve and if you see here, when you call it is ‒ve feedback system it is essentially for
exchange at a point in the feedback system or circuit.
If the created effect coming backed coming back to the original point through the
feedback path. If it negates the original change then the feedback system it is called ‒ve
feedback system. Say for example, if I consider say suppose this signal it is getting
increased or say this signal at this point it is getting increased. Now, if I assume that A is
+ve.
So, it is expected that this signal we will also be increasing. If I consider β it is also +ve,
then since So it is increasing. So, this feedback signal it is also increasing. Now, while it
is going through this mixer and if I say that this block this mixer block, it may create +ve
or ‒ve coefficient. So, suppose this is ‒ve, then whatever the feedback effect we are
getting here due to this change and because of this ‒ sign which is coming back here, it is
going in other direction because of this ‒ve sign.
1236
So, since the this effect coming back which is this blue color which is opposing the pink
color or negating the original change and hence we call it is ‒ve feedback system. And in
fact, this change it may happen at any point in this system need not be only at this point;
it may be here or it may be here whatever it is. We can start from a point and then we can
see follow the feedback path.
And then we can see whether the feedback signal coming back to the point through the
feedback and feedback path and forward amplifier it is negating or not. On the other
hand in case if the; signal it is if the change if the created effect due to a change coming
back through the feedback path, if it is aggravating the original change; that means, if it
is in the same phase. Then we call the feedback system it is +ve feedback system.
Note that it is it is very important that in along according to this definition, the polarity of
this signal coming to this amplifier it is immaterial. In many of the textbook you might
have seen that invariably, we say this is + and this is ‒ and this + and ‒ this sign it may
be defining ‒ve feedback system. But that is a wrong concept you need to be careful, it is
immaterial of this polarity of the primary signal going to the amplifier.
What it is important is that, if you go through this loop and if you follow whatever the
signal it is original signal coming back through this feedback loop if it is negating the
original change then we call it is ‒ve feedback system. In fact, based on the possible sign
here or in fact, based on the sign of A and β we may have +ve and ‒ve feedback systems.
So, we will be discussing that in the next slide of different examples, but before that let
me summarize what I said is.
In case any change say for example, in case if you have a change here, if it is say if the
change is +ve and the corresponding effect here it is +ve assuming both are + and then
this change it in case if it is having a ‒ sign in the mixture. So, this is creating a change
here in the opposite direction and since A is +ve. This blue effect the feedback effect it is
countering the original and hence, we call it is ‒ve feedback system.
1237
On the other hand, if I if I consider say the same original change here and then the
corresponding effect if it is coming back here. And if I say this is + sign which means
that Sf and Sin they do have the same phase so, which means that the corresponding
effect coming back here it is in the same direction and so, the effect coming back through
this feedback path it is in the same direction which means that it aggravates the original
change and hence because of this + sign here. Assuming this is also +ve the system
becomes +ve feedback system.
So, as I said that let me consider different cases. So, not only we will be having this sign
but also we can think of the flexibility of A can be ‒ve or β can be ‒ve. So, a various
combination and based on the polarity here and here to generate this input signal, we
may say that we do have different expressions of the Sin which is function of Ss and Sf.
So, suppose we do have Sin = Ss ‒ Sf, which means that we do have a + sign here and we
do have ‒ sign here.
On the other hand in case if we do have S in equals to Ss + Sf then we can say this is +ve
and also this is +ve. Likewise, in case if I have a situation where Sin = ‒ Ss ‒ Sf which
means that both this polarity of this input and polarity of this input of the mixture. This is
‒ this is also ‒.
So, then we can say that Sin = ‒ Ss ‒ Sf. So, likewise based on the polarity, if we define
the relationship among Sin and Sf and Ss from that we can say what may be the nature of
the feedback system. Also as I say that A and β can be +ve or ‒ve ok.
1238
So, let us see, what are the different possible options, it is not all exhaustive options but
just to tell you some of the examples to clear your concept. Let you consider a situation I
where Sin = Ss + Sf which means that I do have + sign here and + sign here. So, that gives
us Sin = Ss + Sf. And if I consider both A and β they are +ve and then as I said that if I am
having this situation, if I consider any change within this loop suppose, this is increasing
and because of + sign this is increasing and again this is + sign or β is +ve. So, this Sf it
is increasing.
Now, I do have + sign here or I do have + sign here in the expression of Sin. So, the
effect coming back here due to this change it is in the same direction. So, that means, the
feedback system here it is +ve. On the other hand, if I consider situation-II. So, I do have
say situation-II, where Sin = Ss and Sf; that means, we are retaining this one, but if I
consider A is ‒ve. So, if I consider this A it is ‒ve.
Then, you can easily see that the original change here, if this is the original change
because this is ‒ve. So, instead of going +ve direction this will be in the ‒ve direction
since β is +ve. So, now, it will be ‒ve and I do have a + sign here. So, on this change it is
coming back here in this direction. So, since the original change and the feedbacks effect
they are opposing each other or the feedback signal it is negating the original change.
And hence the feedback system it is ‒ve feedback system. So, likewise if I having say
this situation, where Sin it is Ss ‒ Sf. So, instead of saying that this is Ss + Sf let me say
1239
this is Ss ‒ Sf and if I consider both of them are +ve. So, this is +ve this is also +ve and
you yourself can find that since this is ‒ sign here while the signal it is going through this
loop from here to here they are in phase again here to here they are in phase.
But whenever the signal is going from this port to this port because of this ‒ sign it will
be creating an effect which is countering the original change and hence this is ‒ve
feedback system. So, likewise you can see the situation-IV where we are retaining this
same expression, but then this is ‒ve and this is +ve. So, you yourself can find that this is
+ve feedback.
So, likewise if I consider situation-V where the expression of Sin it is different and this is
‒ve and this is +ve. And it can be again it can be shown that I do have ‒ sign here, but I
do not have ‒ sign here this is + sign. So, this is again ‒ve note that here I do have ‒
sign, but it is not having any impact on the definition of ‒ve feedback system. So,
likewise you do you also have the other case in this situation and you yourself can find
then this is ‒ve mainly because we do have ‒ sign here.
So, likewise we do have many other situations and you yourself can find when the
system it is +ve feedback or ‒ve feedback. Note that while we are making this change
original change and, we are trying to see the effect, we are giving sufficient time to see
the corresponding steady state change. So, this definition of this +ve and ‒ve feedback
system it is primarily based on observation of steady state response.
So, on the other hand instantaneous response it may vary, but then without having any
ambiguity, we prefer to use this steady state change to define whether the system it is
+ve feedback or ‒ve feedback. So, what I like to say that whatever the ‒ve feedback
system we are talking about say here or here or maybe here, this does not give any
guarantee that the system it will remain a remain ‒ve feedback for all possible transient
situation.
So, anyway we will be discussing that later, we will we will come back, but right now at
least it is clear that what is called +ve feedback system and ‒ve feedback system. Now,
instead of considering all possible situation without loss of generality, we may consider
say this situation and we will continue our discussion, which means that as I said that we
will continue with this situation namely this is the ‒ and this is + which means that Sin =
Ss ‒ Sf
1240
And unless otherwise it is stated, we assume that both are +. And hence this is ‒ve
feedback system, but of course, this polarity we may not change, but we have to keep in
mind depending on the situation we may change it. So, in our further discussion, we may
consider Sin = Ss ‒ Sf.
And then, we will be moving for further analysis particularly input to output transfer
function.
1241
So, in the next slide, we are going to talk about transfer characteristic of the feedback
system. So, as I said that we may have different situation, but without loss of generality,
let we consider that primary port, it is having + sign at the mixer terminal and the
feedback signal terminal it is having ‒ sign which means that this Sin = Ss ‒ Sf.
On the other hand since, it is forward amplifier and we know its transfer function it is A.
So, we can say that So so, this So = A Sin. Likewise, when you consider say signal
whatever the signal we do have So, it is generating Sf and we do have a transfer function
of the feedback path it is β which means that Sf = β So.
So, we do have three equations here and here. And if I consider that this is my primary
input port and this is the primary output port. And I like to know what will be the transfer
function of this entire system, starting from this primary input to the primary output. So,
input to output transfer characteristic if I say, which means that . So, what is the
transfer function when we do have the feedback system in place and assuming that the
polarity of this terminal it is +ve and here it is ‒ve.
So, if you consider say this equation this equation and this equation, we can get the
expression of . So, to start with we do have a Sin is this one. So, Sin it is given here. So,
we can say that So = ASin and Sin is Ss ‒ Sf and then Sf = So β. So, we can see that this is
Sf = A (Ss ‒ β So). Since, we need to find this ratio. So, we are getting relationship
between Ss and So. So, we can further expand it. So, this is Ao or other A Ss ‒ β A So and
then this So part we can bring it on the left side. So, we can get So (1 + β A) = A Ss.
In fact, that gives us the required input to output transfer characteristic = . So, that
is the input to output transfer characteristic of the feedback system. This expression we
will be frequently using and this is defined as input to output transfer characteristic of the
feedback system. So, that is what I have written here. So, likewise you can also find the
other important transfer characteristic I should say internal transfer characteristic which
is referred as loop gain.
If you see it carefully and if you go through this loop, it is having its own gain. So, if I
start from any point in this loop and if I try to find what will be the net transfer function
and so, if say for example, if I start from here and if I go from this point to this point I do
1242
have a transfer function of A and then through this path I do have β. So, from here to
here I do have transfer function Aβ.
And then again going from this point to this point here to here I do have a ‒ sign. So, we
can say that this loop gain; this loop gain of the feedback system it is Aβ and also we do
have a ‒ sign. So, the loop gain of the system it is ‒ Aβ. In fact, Af if you see here you
may write this one as . So, if you see it here carefully that apart from this loop
gain also there is another important factor called desensitization factor.
What is what does it mean is that, if you look into this transfer function of the feedback
system and on the other hand, if you see the transfer function of the forward amplifier
ok. Let me clear the board and then I will explain. So, what I said is that, if I do not have
this feedback path if I remove this one and if I consider this is the primary input and this
is the primary output.
So, from here to here the transfer function it is we do have + here. So, if I remove this Sf,
and hence So = ASin incidentally that is same Ss. So, the forward path amplifier gain it is
A. Now, if I if I incorporate this feedback, you now if I incorporate this feedback
whatever the transfer function I am getting it is Af. So, the gain of the system it is getting
changed from A to .
1243
In other words we can say that, the system gain it is getting reduced by this factor or we
may say that circuit is getting desensitized by this factor. So, this factor it is referred as
desensitivity factor of this ‒ve feedback system. In fact, here we said it is the feedback
system gain it is changing by A factor of (1 + βA).
Later we will see that this factor it is not only changing the gain by this factor but, also it
is changing the input resistance output resistance for that matter sensitivity of the circuit
it is getting change by this factor. And hence in general this (1 + βA) it is referred as
desensitivity factor D ok.
So, whenever we will be talking about any ‒ve feedback system, we may always refer to
this four important parameter; one is forward amplifier gain, another one it is the loop
gain then de sensitivity factor and of course, the gain of the entire feedback system.
Now we need to be careful in this model that what are the assumptions we are doing and
also we need to be aware that this analysis of this feedback system or I should say this
model it is very generic it can be deployed in different systems. So, first let us try to see
what is the applicability of this analysis namely, Af = .
And then we will be talking about what are the assumptions, we are making here and
when those assumptions are you know practically valid or not.
1244
So, the as I said that applicability of this this model this model and whatever we see Af =
. In fact, whatever we have discussed it is valid for the signal in time domain.
So, for time domain analysis, we may use this model and we can make use of this
formula. This is also valid for frequency domain analysis. So, as long as in the system it
is linear and time invariant, we can make use of this formula. So, as I said that this is
very generic, but of course, if the system it is non-linear we cannot deploy directly then
we have to see up to what extent it is useful.
But then as I said that we need to be very careful of what are the assumptions we are
making. We need to be whenever we will be deploying this model in a practical circuit,
we need to be aware of that. First of all the forward amplifier and feedback path they are
unidirectional which means that we assume that signal it is propagating from left to right
through this forward amplifier.
And the through the feedback path on the other hand the signal it is going from right to
left. So, in case the signal it is also propagating in this direction then we have to make
the corresponding correction. So, likewise in case if the signal some part of the signal if
it is having a chance to propagate from right to left through this amplifier then also we
have to take the necessary correction.
So, in this the formula, we have assumed that both the amplifier forward amplifier and
then feedback path they are unidirectional. The second assumption we need to be careful
it is the loading effects. So, we are considering that loading effects either ignorable or
probably they are considered in the transfer function. What do I mean by that is that.
Whenever we say sampling the signal from this point and we are feeding the signal to
this feedback network naturally, this output port it is getting loaded by input impedance
or input condition of the feedback network. So, we are probably ignoring this loading
effect or we have to capture that loading effect in this formula. So, likewise, whenever
we do have the feedback network having a transfer function of β from here to here.
And then once you are connecting this output to the input port along with the primary
source, whatever the loading effect it may be coming from the input characteristic of the
amplifier and or the impedance of the signal source, we are assuming that is already
considered. Unless that is properly taken care you may get erroneous result. So, if I
1245
typically what it is done here is instead of calling this is A, we may call it is A′ and we
assume that A′ represents the forward amplifier gain after considering the loading effect
from the feedback network.
So, we call instead of A, we call it is a dash. Likewise, β the feedback path or feedback
networks transfer function β instead of β we consider β′ which incorporates the loading
effect. So, if you take care of those loading effects of course, then this equation it will be
getting change in this form, where A need to be replaced by A′ and β need to be replaced
by β′.
Likewise the loop gain we do have ‒ sign and then β′ and A′ and then also the de
sensitivity factor which is (1 + β′A′) right. So, while we will be deploying this as I said
while we will be deploying this formula, we need to be careful now next thing is that
whatever the signal we are talking about signal at this point signal at say this point.
So, far we are talking about their signal. Now, this signals they can be voltage current or
for that matter any other say for example, temperature pressure whatever it is. So, this
model it is in fact, generic enough to capture various situations as long as we map our
original system or practical system into this model. Then we can make use of whatever
the formula we will be, we have derived as well as we will be discussing.
1246
But, first of all we need to be careful that the in our discussion of this analog electronics,
we will be considering this signals this signal this signal having two types either they can
be voltage or current.
So, that is the assumption and it is not mandatory that the signal here and here should be
of same type say for example, this may be voltage this may be current and so and so. So,
we do have four different possible situation; leading to four basic configurations. So,
depending on the signal type here and signal type here, we will be having four basic
configurations out of this this model.
And only thing is we need to be careful that if we, if we define say this signal nature,
then that should be supported by the amplifier and also whatever the signal it is coming
to this mixer need to be consistent with that signal time. Same thing whenever, we are
talking about the signal here we should be careful that the this block as well as this block
it is they are characterized based on the signal type.
So, if I say this is voltage and if I say this is also voltage. So, A is the voltage gain and
this is expecting to generate voltage. So, this is also converting voltage to voltage. On the
other hand, in case if say this is voltage, but say this is current. So, then this this block it
is converting voltage to current which means this should be transconductance. So, then A
should be transconductance which receives a voltage and converts the signal in the form
of current.
Now, if you consider here, it takes the signal in the form of current and it is it is
supposed to produce a voltage here. So, that the mixer will be having appropriate
conversion there, without really transferring it. So, if this is transconductance then this β
should be impedance or resistance. And if this is voltage this is voltage this should also
be voltage. So, then only this two voltage you can mix.
So, based on the situation based on different types of signals the unit of the transfer
function should; should be appropriately modified. So, it may be unitless or it may be
transconductance or transimpedance or vice versa. So, we will be talking about four
basic configurations, but before that let me take a short break and then we will be coming
back.
1247
Prof. Pradip Mandal
Lecture – 91
Feedback System (Part B)
Welcome back after the short break. So we are talking about different possible
configurations. So, in the next slide we are going to see one of those 4 configurations.
1248
So, here we do have so, this is the basic model and here is the corresponding detailed
model. In this case as I said that the input signal and output signal are say voltages.
So, here we consider it is voltage here also it is voltage, so the signal here it is voltage
and this is also voltage. Now, since here the signal it is voltage as you can see that the
sampler whenever we are sampling the signal, it should be parallel connection. So, we do
have this is the output signal in fact, that is So to sense this voltage the input port of the
feedback network it should be parallelly connected.
So, that is why we say that voltage sampler at the output port it is having a parallel port.
So, we do have parallel port. On the other hand if you see signal here they are voltages,
so our intention is to use these two voltages to generate this Sin or vin. So, this is Sin and
this is Ss it is in the form of voltage and this is Sf.
So, this signal and this signal we are mixing together to generate a voltage here which is
if you see here if you consider this loop. So, if I say that this is vin this is + and this is ‒.
So, vin = vs ‒ vf. So, if you see carefully the polarity indicates that vin = vs ‒ vf. In fact,
that is what we are looking for Sin = Ss ‒ Sf.
So, that is the; that is the situation and while we are mixing to generate this input voltage
from vs and vf, these two signal sources they are connecting in they are connected in
series. So, the voltage mixer at the input port it is a series mixer. So, we are connecting
the two voltage sources in series. And also in this ideal model while you are say tapping
or sampling the signal from the output port we assume that there is no loading effect,
same thing here also we are assuming it is loading effect.
So, to create that situation we have considered this ideal situation namely the resistance
here it is ∞. So, I am keeping this is open so, Rin it is ∞. On the other hand output
resistance here Ro, so that is equal to 0. So, output resistance here it is 0.
So, the since the resistance here it is 0. So, whenever we are trying to tap the signal for
the feedback network, so then it is not creating any loading effect. In fact, we do have a
double precaution Ro or Rout it is 0 and also here the input resistance of this feedback
network in fact, this is R′in_β. So, it is not Rin_β it is R′in_β.
1249
So, this R′in_β; that means, input resistance of the feedback path that is also ∞. So, by this
arrangement; by this arrangement, we said that the A is remaining A, we do not have to
consider A′. On the other hand, Rout of this feedback network which is R′out_β which is we
are assuming it is 0 and also in combination of this resistance is infinite.
So, whatever the input we are or the feedback signal vf we are producing here that is
directly coming there. And this voltage of course, it is coming from whatever the voltage
we are sensing, if I call this voltage it is vx. So, the internally developed voltage it is βvx.
So, I should say vf = βvx and incidentally this vx and vo they are same. So, we may say
that this is βvo. So, whatever the desired equation we are expecting? Namely vf it will be
βvo that we obtain and here we got vin = vs ‒ vf.
And also here we do have the output voltage which is Avvin. So, I should say this Av
representing voltage gain, so Ain our formula we need to replace by this Av. So, if you
see here the primary input to primary output transfer characteristic. Namely, if I call
voltage gain of the feedback system in this situation it is .
Now, also you might have observed that since the signal here it is voltage and here also it
is voltage. So, this A it is unit less and β is also unit less both of them are converting
voltage to voltage. So, this is one possible configuration out of the 4 configurations.
And how do we name this configuration? As you can see here we are summarizing the
naming conventions again it may vary from textbook to textbook; but you should not get
confused with different naming. If you see here the feedback signal it is going through
this path.
So, whenever you will be naming you should say this type of the mixture and sorry type
of the sampler and type of the mixer. So, in this case what you are having it is voltage
sampling and voltage mixing feedback system. Since this voltage sampling it is what you
are doing is basically a shunt connection. So, we may say shunt sampling and voltage
mixing it is actually series mixing.
So, we may say that shunt sampling and series mixing. To compress it typically we use
this word and this word. So, alternatively this configuration it can be named as shunt
series feedback system or you may say that here the signal it was voltage, so we can say
1250
that voltage series feedback. So, this voltage it is coming from coming from here and this
series it is coming from here.
So, in summary this configuration typically or most of the time we refer as shunt series
feedback. So, this is shunt and this is where series; shunt-series feedback or you may say
that this is voltage and then series feedback. So, likewise if you consider other situation
to get the 2nd configuration where probably one of the signal type we can change. So, let
me see what I do have in the next slide, yes.
So, in fact we have changed both we have changed from voltage to current. So, what we
said is that input as well as output both are current. So, here it is current and here also it
is current. Of course, then this is unit less and you may say this is current gain.
And likewise β is also unit less because it is converting current to current. And then this
signal primary port signal should also be current, so that the mixer will be able to mix the
feedback signal and the primary signal to generate Sin. So, now the sampler current
sampler so, whatever the sampler we will be using at the output port it should be in
series.
So, if you see here, and if you recall the previous configuration there it was shunt
connection; but in this case we do have output signal say io and this io need to be flowing
through this path right. So, to have this current flowing through this input port.
1251
So, this port and this port they should be in series. So, the sampler these sampler it is
actually series type of sampler. On the other hand if you consider the input port. Since,
we do have the feedback signal which is in the form of current and then primary signal it
is also in the form of current; and if you want to mix two currents we have to make a
parallel connection. So, the mixer it is a parallel mixer.
So, in summary what we have here it is series and here it is parallel compared to the
previous case here the situation got changed. Also, if I consider ideal model to avoid the
loading effects, the situation here for the input; and output resistance of forward
amplifier and the feedback path need to be appropriately changed.
So, what we have here it is to avoid the loading effect here the input resistance it is 0.
And the output conductance here it is 0 or output resistance is ∞ ok. So, if I am having
conductance then definitely internally generated current it may get reduced. So, to avoid
that situation or to avoid the loading effect, we are considering the output resistance of
the forward amplifier it is ∞ and input resistance it is 0.
So, on the other hand if you consider the feedback network again to avoid loading effect
we want its input resistance should be 0. So, that it can nicely sense the signal input
signal vx. So, Rin_β that is the input resistance of the feedback network, we want this
should be 0. And the output conductance of this current source of the Norton equivalent
model this should be 0, or we can see output resistance is ∞. So, this is what the ideal
situation.
1252
And if you see here the polarity of the signals particularly at the input port you need to
be very careful. We call this is the +ve direction of the current; we call this is the +ve
direction of the convention. And this is also +ve direction of the current.
So, if I consider say this net and if I consider the KCL at that node, so we can easily see
that iin = is ‒ if. In fact, that is what we are looking for, Sin = Ss ‒ Sf. So, this ‒ ensures
that we are satisfying this ‒ sign. And also if you see the at the output port this is the +ive
direction of the output signal.
So, the internally generated current it is consistent with that, and we are assuming this AI
current gain it is +ve, so which means that this is also +ve. And if the current is flowing
in this direction it is producing a current in this direction which is aligned with if. And
then we can say that for a +ve current of ix it is producing a +ve current of βix which is
consistent with if.
So, that again ensures that in this configuration β is also +ve. So, we do have this is +ve,
this is +ve and this is ‒ sign and hence, the system it is ‒ve feedback system. So, if you
make any changes here then there is a chance of your ‒ve feedback system may get
converted into +ve feedback system.
So, if you also have observed that A needs to be replaced by AI and β of course, β is
remaining same. And AI it is converting current to current so, it is unit less β is also unit
1253
less. And hence, we can say that the overall system gain AI_f = which is defined as
which = . And of course, the loop gain as you can see here loop gain it is ‒ βAI.
So, this second case this configuration it is having different naming based on this
connection and this connection. As you can see that this current sampler it is if you see
here it is a current sampler, and current mixer. Current sampler it is a series kind of
connection, or a series sampling. So, that the output current should be flowing through
this input port of the on the feedback network. And also whenever we are mixing if you
see here it is a shunt connection.
So, the naming of this configuration it can be said that it is series sampling, shunt
mixing, ‒ve feedback system. Alternatively, we can probably consider series, and shunt.
And as I said that the feedback it is in this direction. So, we should start from sampler
and then going to the mixer. So, we do have series is the sampler and then shunt is the
mixture. Alternatively we may say that we are sampling the current and then we are
feeding back to the input port and there the connection it is shunt connection.
So, this current again it is coming from this name and this shunt it is coming from this
one ok. So, that is see that is about the naming of this feedback system. So, now we can
consider the other situation other rather two more situations where one of them it is
voltage; another one is current.
1254
Let me see what I do have in my next slide, say in the third case. In third case what we
have it is input it is voltage. So, here we consider the signal it is in the form of voltage.
And the signal here it is in the form of current.
So, now you need to be a little alert that this is of course, it is converting voltage into
current. So, this should be transconductance which is taking the voltage at the input and
it is giving the current at the output that is why trans, and since its unit is more so it is
conductance.
So, in the model here if you see I do have instead of A here I do have Gm representing m
represents trance and G represents conductance. And it is taking the voltage from the
input port and it is generating a current here. And on the other hand if you consider the
feedback path β here the signal it is in the form of voltage and here of course, it is
current. So, it is converting current into voltage.
So, now this β actually its unit it is ohm. So, you can say it is trans impedance kind of
network and. So, if you see the nature of the sampler and mixer at the output port we are
sampling current so, definitely this will be series. So, series sampler and on the other
hand at the input port we are mixing two voltages vf and vs to generate this vin and since
we are mixing voltage they are getting mixed by the series connection. So, mixer is
series; so, series mixer. So, if you see here for avoiding loading effect again the input and
output impedance of these two blocks need to be appropriately consistent.
So, if you see here the signal it is voltage to avoid loading effect input resistance should
be as high as possible. On the other hand at the output to avoid loading effect we want
conductance to be 0. Since, it is not only k equivalent conductance we want to be 0 for
avoiding loading effect. So, the Rout is infinite and on the other hand the feedback path it
is sensing the current and to avoid the loading effect as I say that we are trying to be
doubly sure that loading effect is not there.
So, the input resistance here if I call Rin_β should be as small as possible ideally 0. And at
the output port of the feedback network since, we are generating voltage again to avoid
the loading effect, the corresponding output resistance here Rout_β should be 0.
So, to create a situation to avoid loading effect this is what it is assumed. And hence we
considered A is A and of course, A need to be replaced by transconductance Gm. And β
1255
we are using same β, but of course, its unit it is Ω and unit of this is ℧. Now, in this
situation of course, input primary input to primary output transfer function, it is we can
say Gm_f, or you may say that this is what Af.
So, that is equal to A which is . And loading f that the loop gain on the other hand
equals to ‒ βGm of course, this part it is the desensitivity factor. So, you can probably
you can see yourself that this loop gain of course, you are retaining ‒ sign; but most
important thing is that unit of Gm and unit of β they are complementing each other.
So, that it becomes unit less, that is very obvious that if I start from a point and then we
are converting voltage into current and then current it is getting converted back into
voltage. So, if we really go through this loop the signal here it is of the same type. So, the
complete transfer function going through this loop should be unit less. So, that is
consistent with this case that loop gain it is of course, it is unit less.
Now, about the naming of this feedback system it is as you can see that how we do have
current sampling. So this is the current sampling and the voltage mixing. So, either we
may say that this feedback configuration it is current sampling and voltage mixing, or
while you are sampling it is basically the connection it is series. And voltage mixing it is
also series, so we can say series sampling series mixing or to abbreviate it alternatively
you can say that series connection.
So, this series is in the first one and then this was the second one. The other possible
option you might have you may get in the literature is that instead of calling this series,
we may use this term and we call current series feedback. So, we are sampling current,
and then we are feeding back here in the form of series network. So, likewise the fourth
possible configuration where we can say this is current and this is voltage.
1256
So, in the next slide we will be seeing that. So, the here input is current and output is
voltage. So, we are expecting this is current and here the signal it is voltage and we one
the feedback signal should be consistent with this current. So, this is also current and the
signal source also needs to be current. You might have observed that based on the
situation in the signal source we are appropriately modifying. And also we are making
ideal signal source without considering its Thevenin equivalent resistance, or Norton
equivalent conductance.
So, that the loading effect it is ignorable. Later we will be coming back to the loading
effect so, but anyway so, this configuration at the output port we do have voltage
sampler. So, we are having signal in the form of voltage. So, the input port of the
feedback network should be parallel connected. So, as you can see here it is a parallel
connection, or shunt connection. And also the input mixer side. So, mixer it is of course
here the signals are in the form of current.
So, the while you are mixing the signals in the form of current it should be a parallel
connection, or shunt connection. So, that is what we do have here it is parallel and here
also it is parallel, this is for voltage sampling and this is for current mixing. And again to
create the ideal situation the since the signal here it is current, we want input resistance
should be as small as possible ideally 0. And, the corresponding conductance here it is 0,
or the output resistance of the feedback network it is 0.
1257
So, these two is creating this loading effect it is ignorable. So, we can consider only β not
β′. And also we are considering 0 conductance for the signal source. On the other hand at
the output port to avoid the loading effect the resistance here Ro, Rout we are taking 0.
And the input resistance on the other hand we are considering it is ∞, so that we have to
consider A not A′. Now, here the signal it is current and this is voltage which means that
this forward amplifier it is converting current into voltage.
So, naturally its unit it is Ω and we call this parameter it is transimpedance. So, instead
of A we write this is Zm, m stands for mutual or trans and Z stands for the impedance.
So, the voltage getting generated here it is Zm multiplied by input signal which is iin.
On the other hand in the feedback path it is sampling the output signal in the form of
voltage let me call it as vx and based on this vx it produces a current which is βvx. And
again the polarity convention if you see here we do have + sign here and this ‒ sign here
which is consistent with this + and this ‒.
And this vx +ve, vx it is producing a current in this direction which is consistent with the
direction of this if. And the +ve direction convention of if; and is and iin it is such that iin =
is ‒ if. So, that gives us Sin = Ss ‒ Sf and hence it supports this ‒ sign. And the polarity
here, and the +ve direction of this current insists that this Zm it is +ve.
So, that means this A is +ve so, likewise here also the output current and input voltage
they are consistent for the +ve sign. So, the β is also +ve. So, that makes again this is ‒ve
feedback system; because of this ‒ sign, and this both are a +ve. Now, with this we can
say that A should be in this case A should be replaced by transconductance theorem. And
the overall feedback system transfer function from is to vo which is Af. So, in fact, we
may write this is Zm of the feedback system which = .
And the loop gain as you can guess that loop gain equals to ‒ βZm here also we can see
that unit of Zm it is Ω and unit of β on the other hand which converts voltage to current it
is ℧. So, together it is unitless so, as I said that loop gain should be better being unit less.
And coming to the naming convention of this feedback system, it is the sampling it is
happening in the form of voltage or we are sampling voltage at the output port. And then
we are mixing the signal in the form of current.
1258
So, we can say that this feedback configuration it is having a voltage sampling, and
current mixing, or we can say that voltage whenever you are sampling signal in the form
of voltage it is we can say it is shunt sampling and current mixing is shunt mixing. So,
we can say this is shunt-shunt feedback configuration, or we can say voltage-shunt
feedback configuration ok.
So far we have talked about the ideal situation. Now, of course the situation whenever
we consider practical examples there we will see that we will not be having any
guarantee to have this situation or maybe the other situation.
So, in case say we do have finite value of resistance so, in case this is nonzero likewise
in case if we do have output resistance which is nonzero and still if I say that this is
infinite and this resistance is 0 this is having 0 conductance. So, even in this situation
since we are not having any load here. So, we consider load resistances in finite. So,
even then in this case the loading effect is 0.
So, we need not to consider A′ rather A′ it is same as A and likewise β′ right. But then in
case if it is not so, in case if we have say finite value of say finite value of say RL, then
naturally the voltage coming here it will not be same as whatever the voltage we are
generating here. So, in that case instead of Zm we have to consider the corresponding Z′m,
or in that case I need to consider A′ which is Z′m. And in that case; obviously, this is not
same as Zm, or A.
1259
So, if we have a practical load then we have to consider that situation. And also you have
to keep in mind that whenever I do have nonzero value of input resistance. Then if you
look into this port; if you look into this port the input resistance of the feedback system it
will not be same as whatever Rin in fact this Rin.
Of course, the input resistance of the feedback system I can call this is Rin_f. So, Rin_f it is
not same as Rin because we do have another path parallel path we do have active path
that we do have. So, we need to find what may be the corresponding relationship. So,
likewise when you consider this Rout and if I look into this circuit. And if I want to know
what will be the corresponding Rout of the feedback system and if I call this is Rout_f.
So, this is not same as this Rout because we do have a parallel connection here which
generates internal signal and it is making some internal voltage there. So, in case if I
consider this practical situation then we will see that not only A it is input to output gain
A it is desensitized by a factor of (1 + βA). But, also this input resistance of the feedback
system and output resistance of the feedback system they are also getting changed by the
same factor.
So, in our next analysis what we will be doing is so, what will be doing it is we will
consider this is non zero; this is non zero. So, that we can find what will be the Rin_f and
Rout_f, but for all practical purposes we may continue the ideal situation of the feedback
network.
1260
And also we considered all practical purposes it is unidirectional. In fact, this is what I
said for only Case-IV namely; this shunt-shunt configuration, it is valid for the other
configuration for example, if we go back.
So, if you consider this case and if I say that to support the ideal situation we have
considered this, but in case if I am having some finite resistance here. So, suppose this is
non-infinite, so if I am having Rin and say this is also not ∞.
So, we do have some internal conductance or we may call Rout. And then if we want to
know what will be the corresponding input resistance Rin of the feedback system. And
likewise, Rout of the feedback system then we need to again analyze the circuit. So, but
then to simplify the analysis even though we may consider this non ideal situation for the
amplifier, but we may continue to consider this ideal situation. And then we will see
what is the expression of Rin_f in terms of Rin.
In fact, what we will see here since it is series connection it is expected to be this
resistance you will get increased, and this increasing factor it is the desensitization factor
(1 + βA) and in this case A is Gm. Likewise, Rout it is Rout_f = Rout × (1 + βGm). So, if I
consider this 4th case and if I consider that these are nonzero.
1261
And if I want to know what will be this Rin_f which is equal to Rin and since it is parallel
connection we are expecting that input resistance. So, Rin and if I know what will be the
corresponding feedback system input resistance this Rin it is getting decreased, or
desensitized by the same desensitization factor which is (1 + βA) and A it is Zm.
So, likewise if I consider Rout_f equals to if I consider the finite Rout here which is
nonzero. So, that will be . So, we are going to discuss that, but again please let me
take a break and then we will come back.
Thank you.
1262
Prof. Pradip Mandal
Lecture – 92
Feedback System (Part-C)
Yeah. So, dear students, so, welcome back after the break and before the break we were
talking about 4 basic configurations of a ‒ve feedback system and we have seen the
change of the system gain due to the ‒ve feedback and we have talked about the
desensitization factor. Now we are going to talk about the effect of the feedback system
on input resistance and output resistance as I have given a hint in the previous part of this
lecture.
1263
So, in the next slide we do have the corresponding circuit diagram here and to start with
let we consider a voltage amplifier and its feedback connection it is shunt-series or you
can see voltage-series feedback; which means that this port it is shunt and here we do
have a series connection here.
So, if you see here at this port we do have the input port and a primary port and feedback
port they are connected in series. So, here of course, while you like to see the change in
input resistance and output resistance of the amplifier we have to keep this in mind that
we have to consider finite value of this input resistance and the corresponding output
resistance.
However, to start with for feedback network let we consider it is ideal situation namely;
it is input resistance it is infinite and the corresponding output resistance here it is 0. So,
here we do have open and here we do have 0 resistance and we will see that the input
resistance of the feedback system initially it was Rin and now due to this series
connection of the feedback network we will see the corresponding change and we call
the changed input resistance in Rin_f.
Now, to get this derivation of this input resistance of the feedback system let we consider
that we are stimulating the circuit with a signal source called vs and we are observing the
corresponding current entering into the port and let we call this as is. And then the input
1264
resistance of the feedback system are in f it is defined by . To get this ratio let we
consider the input port and then let we get the corresponding relationship.
So, if you consider say this port and if we are applying say vs here and if you consider vs
actually it is equal to summation of vin and then corresponding feedback voltage vf. So,
we can say vs = vin + vf which is of course, vin plus the internally developed voltage
which is βvx. In fact, vx it is same as this voltage vo.
So, we can say this is vin + βvo on the other hand if I consider that this port it is open and
here also it is open then the voltage getting developed here vo even though we do have
Rout the voltage here it is same as internally developed voltage namely Avvin. So, we can
further consider this expression of vs as vin + βAvvin right.
On the other hand, if I say that is current is flowing and it is entering to the circuit and we
do have a resistance of Rin and across this resistance Rin we do have vin it is getting
developed. So, we can say that vin = isRin. In other words we can say that vs equals to if I
take vin common and then we do have (1 + βAv) and that = isRin (1 + βAv).
And that gives us the feedback systems input resistance Rin_f = and using this
relationship we can see that this is Rin(1 + βAv). So, that is why the feedback system
input resistance it is having this expression in terms of the input resistance of the forward
amplifier and also the corresponding voltage gain and also the transfer function of the
1265
feedback network. And of course, here we have assumed there the feedback circuit it is
ideal one.
So, we have considered input resistance of the feedback network it is ∞, output

resistance of the feedback network it is 0 and also it is load we considered this is ∞. So,
we consider load of the circuit it is ∞.
Now, let we consider that in practical situation where definitely there may be a finite
load RL and due to which the voltage available here at this port it may not be same as
internally developed voltage and in that situation what maybe the corresponding change.
So, to start with let we consider RL it is finite.
So, if we put say RL here and then the voltage here vo. In fact, this is same as vx also. So,
vx = vo = Avvin × right.
Or we can rearrange this equation and we may see that this is equal to A′vvin where A′v is
Av . Or we can say this is load affected gain of the amplifier Av and rest of the
analysis it is remaining same namely, if you consider vs which is summation of vin + vf

which is βvx and then expression of the vx it is given here and from that we can see this is
equal to vin + βA′vvin and of course, you know we also have relationship between vin and
is. So, vin = isRin.
1266
So, using this relationship and this relationship we can find that the corresponding input
resistance of this circuit we call the say Rin_f and. So, it is remaining very similar to this
equation except this Av need to be changed by A′v. So, we can say that we are finding
this new expression of the input resistance where A′v it is defined here.
So, likewise if I consider say resistance here also in case, if I consider finite resistance of
the feedback network. So, if I say that this is having some finite value call Rin_β then the
corresponding voltage here getting developed here across this RL and Rin_β they are
coming in parallel.
So, then the voltage here instead of Avvin × RL it will be (RL ⫽ Rin_β). So, likewise here
also we will be having Rin_β ⫽ RL and of course, we do have this Rout in series. So, we
may say that the corresponding expression of vx it will be say .
So, let me write the expression of in presence of Rin_β and RL it is equal to internal
⫽
voltage gain Av × ⫽
. So, again the relationship here between input resistance
of the feedback system and without feedback it is remaining similar except this Av need
to be replaced by and its expression it is given here.
On the other hand if I consider the output resistance of the feedback network also
namely, if I say that Rout of β network it is non-zero. So, if I consider this resistance and
if I say that this is Rout_β in that case whatever the relationship we said here it will be very
similar, but of course, then this Rout it is coming into picture and the voltage coming here
vin it will not be same as whatever the voltage you do have.
So, what we will be getting here it is this β part it is also getting a load affected. Namely,
the voltage here it is not only say this voltage rather of course, this voltage will be there,
but also we have to consider this drop. So, the β is also getting affected and the
corresponding β need to be changed by considering this load and so then the
corresponding β here need to be a changed and. In fact, we also have this is coming in
the series.
So, we have to consider this Rout_β also in the series. So, if I consider both this and this
are having say practical value then the expression of the input resistance of the feedback
system it is coming in this form where it is the expression includes Rin(1 + β′ ) + Rout_β.
1267
so here what we have seen that the series connection the series connection it is making
the input resistance getting increased by whatever the desensitization factor; either we
consider in this case, or this case, or this case. And also you mean you might have
observed that it is independent of this port situation.
So, in case if we have a circuit where see this part the mixer part it is series, but then if
this port it is different namely series; that means, if it is current sampling and then series
feedback then also we will be getting we are expecting that input resistance it will be
increased by so called desensitivity factor. So, let us look into the corresponding circuit
there ok.
So, here we do have a trans conductance amplifier and what do we have what we have
here it is input it is of course, in the form of voltage and since it is trans conductance here
the signal output signal it is current. And of course, the amplifier gain need to be
replaced by transconductance amplification and the feedback system of course, it should
be appropriately modified signal here we are sensing is current and then here of course,
mixing in series.
So, the feedback system it is current series feedback, or we can say it is series feedback.
Here again to start with we consider practical value of Rin and Rout, but we are keeping
the feedback network ports are I should say ideal namely the input resistance here it is 0
and the on the other hand output resistance it is also remaining 0.
1268
And why it is this input port is 0, but that is because now the signal here it is in the form
of current. So, to avoid loading effect namely to absorb the maximum current within this
circuit to sense it we have to make the input resistance to be 0. Also you might have
observed that since the signal here it is in the form of current and to avoid loading effect
we are considering the output resistance it is 0.
So, if this is 0 resistance and this is also 0 resistance we can see that whatever the current
we do have internally developed current that is entirely flowing through this because the
drop across this Rout is a 0. So, if I say that drop across this Rout since it is 0.
So, that gives us iout = Gmvin. So, that you have to keep in mind. So, we are receiving the
maximum current and hence we can see that this is providing unloaded situation. And
then to start with to find the relationship between this vs and is to give the expression of
Rin_f the input resistance of the feedback system which is defined by we start with this
relationship of say vs = vin + vm.
So, we can see vs = vin + vf, but we do have the expression of vf = βix. So, this is vin + βix.
And in fact ix it is same as io. So, we can see that this is vin + βio and the expression of io
in terms of vin it is Gmvin.
So, then vs = vin +βGmvin and. So, that gives us vs = vin (1 + βGm) and if the vs it is
flowing through this Rin we have as we have done last time in the previous slide the vin
equals to Rinis.
So, we can write this is as isRin(1 + βGm). So, from that we can find the expression of
input resistance of the feedback system. So, this is becoming Rin(1 + βGm). So, that is the
expression of the input resistance again input resistance it is getting amplified by this
desentization factor. However, the difference here it is instead of Av we do have Gm here
and also we thought we are writing this is β, but you have to be careful that or you
should be aware that this β converts got into voltage which means that this β it is not unit
less rather it is unit it is Ω.
And unit of the Gm is ℧. So, these two together it is giving unit less factor. So, that is
how here the input resistance it is getting amplified by this feedback mechanism. Now if
I consider the these two are having some practical value then say for example, if I
1269
consider the we do have some resistance here and if I call this is Rin_β and if I say this is
non zero.
So, then it is expected that some part of this current internally developed current it will
be flowing through this circuit and part of the current it will be flowing through this
circuit. So, likewise in case if I consider RL here.
So, again part of the current. So, if this RL it is non-zero. So, that will enforce some
additional some current it will be flowing through this Rout and only part of the current
will be flowing through this the output port. So, just to start with if I consider say RL is
non-zero, but say Rin_β is 0 and then we will consider the other case. So, if I consider this
case then io it is Gmvin × . And again you may say that this is equal to G′m load
affected Gmvin where G′m = Gm× .
So now we are we are having this relationship between this io and vin and we know that
this ix it is same as this io. So, we can say that vf = βix and ix it is io and that = βG′mvin.
Now using this equation we can go back to this input port to get the expression of vs = vin
+ vf and vf it is βG′mvin. So, that gives us vs in terms of vin and (1 + βG′m).
So, vin = isRin. So, if I put the expression of iin here and then you can find Rin_f which is
defined by and that is becoming Rin (1 + βG′m).
1270
So, if we have this load practical load then the corresponding input resistance it is also
having the similar kind of expression as we have seen before only difference is that we
have to consider load affected gain G′m. Now if we have say along with RL non-zero, if
you also have Rin_β a non-zero in that case you have to consider these two components
together.
So, to find the io now instead of considering this io expression only Rout and RL you also
have to consider along with this RL you also want to have to consider Rin_β in series right.
And if I consider that; so since we do have some more modification. So, we can say that
is G′m where = Gm right.
And then in the in the expression of Rin_f what we will be getting here it is Rin(1 + β ).
Now if I consider that this is also non-zero so; obviously, at the input port we do have
some effect. So, the voltage coming here it will not be a really same as this voltage and
this voltage we do have some drop across this Rout_β also and if I consider that. So, either
we may say that β is getting affected or we may consider this is coming in series.
In fact, is it is flowing through this also and then you may see that this Rout_β it is coming
in the series with whatever the resistance we do have right. So, that is giving us the
change of input resistance and again since it is a series connection here; series
connection of the feedbacks circuit at the in the mixer.
So, we may say there the input resistance it is getting increased by this factor
desensitization factor now let me consider the other situation namely if the mixture it is
having a parallel connection which means that signal here instead of voltage if it is
current then we can see what kind of changes we do have. So, probably we can start with
say current amplifier. So, in the next slide we can see the change of input resistance of a
current amplifier having feedback.
1271
So, we do have a current amplifier and again we are we have to see what is the
corresponding resistance here called Rin_f and in the amplifier you can see that input
resistance it is having finite value output conductance it is having finite resistance. So,
we are of course, here the signal it is current and here also the signal it is current. So, the
feedback network on the other hand to start with we are considering ideal one. So, if it is
current here signal it is current here to have 0 loading effect we want the input resistance
should be 0.
Of course the load resistance to start with without having any loading effect we consider
RL also = 0 and here the signal it is current. So, we are considering 0 conductance or we
can say that the output resistance of the feedback network Rout_β it is ∞. So, what I like to
say here to summarize that we are considering Rin and Rout of the forward amplifier, but
we are still keeping the feedback network in ideal situation and to start with we are also
considering load resistance equals to 0.
Now to find the in input resistance probably we can stimulate this port by voltage, but it
is since we are considering this is ideal a source we need to stimulate this port by say
current; or I should say it is rather more convenient to get the derivation. If you want you
can stimulate this input port by a voltage source and then you can observe the
corresponding current as you have done for the previous two examples, but i think this
may be having a relatively simpler derivation.
1272
So, at the input port we are stimulating this port by is and we are observing the
corresponding developed voltage called vs and then the input resistance of the feedback
system it is the developed voltage divided by the stimulating current is. Now to find this
ratio we need to find the corresponding relationship and again what we will be
considering here it is you consider the voltage here and then we can see the voltage here
it is a summation of these two or we can say that is it is summation of this current and
this current ok.
So, either way it is possible, but let me just start with say is = iin + if the feedback current
and that feedback current it is βix. So, we can see this is iin + βix and ix it is same as
whatever the current we do have because we do not have any resistance here and we do
not have any resistance here. In fact, both of them are equal to internally developed
current.
So, ix = iin + βix; ix it is AI the current gain of the current amplifier × iin. So, that is giving
us is = iin (1 + βAI). Now if you see the voltage vs and this iin and Rin. So, since it is a
parallel connection the voltage getting developed across this Rin it is the as this vs. So, we
can see that this vs = iin × Rin or we may say that iin = . So, then is = (1 + βAI). In
fact, from here we can get the feedback system resistance which is defined by = .
So, that is the expression of the input resistance of the feedback system.
1273
Now, a similar to the previous example you let you consider the loading effect and to
start with if I consider we do have RL here, if I say that this is non-zero. So, naturally the
io and ix both ix = io both of them it will be AI reduced version of the internally developed
current AIiin × .
So, similar to the previous case here let we consider this factor it is part of the load
affected current gain A′Iiin. Where A′I = AI × . Now following the same procedure
we can get the expression of Rin_f in terms of Rin and the desensitization factor. So,
where A′I it is given here.
So, in case if we have RL it is non-zero. So, that is the expression of the input resistance
we will be getting. Now if I consider say this input resistance of the feedback network it
is non-zero and if I see this is Rin_β which is non-zero then the current here current
expression of ix and io it will be similar only thing is that along with RL I have to
consider this Rin_β also because that is coming in series with RL. So, I have to consider
this Rin_β and let me call them this is . Where the expression of it is AI × ;
and so that is how the expression of the whole system it is getting changed so you can
get this expression.
1274
Now if I consider this part it is finite which means that if I consider it as having some
finite resistance getting connected. So, what will be its consequence that this resistance it
is coming in parallel. So, we can say that input resistance here, it is whatever the
resistance it was there and then we do have this resistance coming in parallel.
So, if I call this is Rout_β then the complete resistance Rin_f it will be ⫽ Rout_β. So,
again for this case you might have observed that because of the shunt connection the
input resistance input resistance got decreased and the decreased the factor it is this
desensitization factor (1 + β × whether we call A or A′ or A′′) and also in case if you
have Rout_β then also you have to consider that as well.
Now, here the signal it is of course, it is in the form of current the situation it will be very
similar in case if we have the signal here it is voltage and of course, if it is voltage and
then if the input signal it is remaining current then the corresponding amplifier it will be
different, then feedback connection it will be different. But there also we will see that
input resistance it will be getting decreased by desensitization factor because of the
parallel connection.
However, the corresponding loop gain it will be different its expression it will be
different. Note that both AI in this case in the present case where signal here and signal
here both are current both AI and β they are unit less once we go to the other amplifier
where input is current and output it is voltage; obviously, then the amplifier gain which
is converting current into voltage it is essentially trans impedance.
1275
So, the corresponding circuit it is given in the next slide. So, here we do have the
transimpedance amplifier. So, in the circuit. So, this is a transimpedance amplifier and it
is corresponding feedback it is of course, it is sampling voltage and then mixing in the
form of current.
So, this feedback system it is voltages and feedback or we may say this shunt feedback in
this case again to start with we consider in input resistance and output resistance of the
transconductance amplifier. However, we are starting with ideal feedback network
namely its input condition and output port condition it is avoiding helping to avoid
loading effect. Namely, the input resistance it is in finite and the output conductance is 0
or output resistance is ∞. And here of course, since the signal it is in the form of voltage
to avoid loading affect we consider RL it is ∞.
So, if I consider this RL it is infinite then at this port whatever the voltage you will be
getting. Sorry I will I will make a correction here I have committed a mistake since this
is Thevinin equivalent model please consider this resistance coming in series with this.
1276
So, let me correct it instead of having this resistance what I mean it is the resistance it is
here Rout ok. So, since I consider RL it is ∞. So, we can see that vo it is same as internally
developed voltage namely, Zmiin and that is also equal to vx and if I consider on the other
side the input port to get the expression this current the total current is = iin + if and if =
βvx; is = iin + βvx and expression of vx it is given there.
So, we can see this is iin + βZmiin. So, is = iin (1 + βZm). On the other hand, here
relationship among vs, Rin and iin it is given by; let me write here vs = iinRin or iin = .
So, this is (1 + βZm).
Now again the definition of the input resistance of the feedback system it is ratio of =
and similar to the previous case if we start considering the loading affect namely,
if I consider this RL it is finite.
And then if I consider this resistance also and then if I consider the internal conductance
here namely both of them are finite RL it is also finite then we can get the derivation of
input resistance going to . Where, Zm it is taking care of the loading affect due to
finite RL. So, let me consider that the expression of ok.
1277
Again I have to make this correction and then if I consider this RL it is finite. Then the
input resistance of the feedback system it will be given by this where Z′m it is load
affected trans impedance and look when I say load affected it is basically whatever the
attenuation factor we do have here that we need to consider along with the original Zm.
So, Z′m it will be Zm × . On the other hand, if I consider if I consider this
resistance also it is finite. So, if I consider that then the corresponding Zm need to be
⫽
replaced by and its expression it is Zm × ⫽
.
So, why we have to consider these are in parallel that is because this resistance and this
resistance they are coming in parallel. So, the voltage getting developed here which is vo
which is of course, reduced version of internally developed voltage. So, the vo it is Zm ×
⫽
iin × ⫽
and the corresponding input resistance it will be this one. Now if I
consider this also which means if I consider this resistance also then that resistance also
coming in parallel. So, I think that is how we can calculate the corresponding input
resistance of the feedback system. So, if we consider the previous cases probably I yeah,
I can see one small mistake I have done.
1278
Yeah in this case when I explained that the we do have RL here we do have this
resistance and this resistance then the input resistance of the feedback system it is (1 +
β ) + Rout_β this β of course, it is remain should remain unchanged it should not be β′
because effect of this one I have already considered here.
On the other hand, affect of Rin_β and these RL they are considered in this where it
⫽
is Av × ⫽
yeah the mistake I have committed before it is that I said it is β′, but
actually it is not β′.
I think that is all we have to discuss, but of course then we have to consider the other
feedback rather all this feedback circuit to find what will be the consequences in the
output resistance. So, so far we are talking about input resistance, now we can also see
the change in the output resistance before we go into this please let me take a break and
then we will see how to derive the corresponding output resistance.
1279
And sorry I do not want to conclude I let me cover that and then we will conclude. So,
we will cover we will discuss this one and then we will conclude.
Thank you.
1280
Prof. Pradip Mandal
Lecture – 93
Feedback System (Part-D)
So, yeah dear students, so welcome back after the short break and before the break we
are talking about the change of input resistance of the different configuration. And
whereas, we are going to talk about change in output resistance to start with let we
consider it is a voltage amplifier and we want to see the change due to feedback
connection.
And since it is voltage amplifier as we have discussed, the circuit is given here. The
configuration here it is referred as shunt series feedback or voltage series Feedback
circuit. And to start with let we consider the feedback network it is ideal namely its input
resistance, it is infinite and the output resistance as it is producing voltage, output
resistance it is 0. However, for the forward amplifier we are considering finite input
resistance and finite output resistance.
We do have the voltage dependent voltage source Avvin, vin it is appearing at the input of
the forward amplifier. Now, to know the output resistance what we can do? We can
stimulate this output port by say voltage source vy and then we observe the
1281
corresponding current say iy and the then port impedance or port resistance it is defined
by . So, that is what we need to find which is Rout of the feedback circuit called Rout_f.
So, while we are doing this exercise we have to keep the input port appropriate. So, that
it will support the feedback connection, namely we in this case the signal here it is
voltage and so, we do have the ideal signal voltage source connected. However, we have
to keep its magnitude, signal magnitude should be 0. Which means that we are
essentially shorting this input port while we are doing this exercise to find the output
resistance. Now, that is the condition and let we derive the expression of this Rout_f in
terms of Rout and probably Av and β. So, let me clear yeah.
So, if you see if I consider this is short, then if I consider KCL in this mixer what we are
getting it is vin, input voltage of the amplifier it is ‒ vf. But then vf it is same as βvx; vx is
the voltage appearing at the input port of the feedback circuit and vx in this case the
moment we connect vy here it is vx it is same as vy. So, we can say that vin = ‒ βvy.
On the other hand if you want to know what will be the corresponding current here, if we
know the internal voltage which is Avvin and here we are applying vy and this is open.
So, the iy it is essentially flowing through this Rout.
1282
So, we can say that iy = and vs this case signal source it is 0 here. So, vin it is ‒
βvy. So, we can see that iy = . So, that is the relationship between iy and vy, so
from that we can see = .
So, this is what the expression of the output resistance of the feedback system due to the
feedback connection. And this is what we have talked about it is the ideal condition. Let
we consider non ideal situations to start with let we consider that we do have a source
resistance called Rs. So, let me create the space, let me erase it.
So, to get the output resistance; to get the output resistance Rout_f in presence of a series
resistance called source series resistance called Rs and of course, we have to keep the
signal here it is 0, so; that means, it is getting shorted like this.
Now, in this condition; vin, the input voltage at this port it can be written in terms of βvx.
In fact, it is ‒ βvx and then the voltage appearing here it is a part of this voltage and the
fraction it is decided by the potential division getting created by Rin and Rs. So, we need
to multiply this by . So, vx again it is same as vy. So, we can replace this and β
into this factor we may call it is a β′.
1283
So, β′vy, where β′ = β × . So, whatever the previous discussion we already have
namely iy = that is valid in this case also and then if we replace this vin terms of
β′vy from that we can get iy = .
And that gives us = . So, that is the output resistance under this condition, in
presence of this Rs, where β′ it is given. In fact, this is a type so, it should be β′ not A′ so,
it is Av. So, we do have Av here. Now, if we also have to consider say finite value of this
resistance, so if I include say this resistance as well.
So, if I consider Rout of the β network, Rout_β, then this relationship it will be getting
changed and the change it will be Rin it will be there and then Rs and Rout_β it will be
coming in series. So, along with this we need to put plus Rout_β and the corresponding β
we can call it is β′′ where β′′ expression it is β × . And again this equation it is
remaining same and this equation it becomes β′′ here and rest of the things it will be
same. And here it will be double dash where β′′ it is β × .
So, that is what we will get the output resistance in this form again I made this
typographic error, so double dash it will be on β. Now in addition to that if we have this
resistance it is also finite, so if I consider this is also finite. So, I need to put this
resistance and if there is resistance it is say some Rin_β, then the situation here it will be
and the output resistance it will be, whatever the situation earlier it was there and then I
have to consider this additional resistance there.
So, that resistance it is coming in parallel to whatever the resistance we just now we have
considered. So, if we consider this is non-zero, this is finite, this is also non-zero, then
the output resistance expression it is given here.
Now, this situation the expression of Rout it will be similar for the configuration where
the voltage here it is or the signal here it is voltage and in case this mixer this port it is
getting changed to current then also the expression it will be similar., it will not be same,
but it will be similar. And in that situation since the signal here it is voltage and here it is
current of course, it will not be voltage gain amplifier, it will be rather the current is
getting converted into voltage; that means, it will be trans-impedance amplifier.
1284
So, in the next slide we will be talking about change of output resistance of a trans-
impedance amplifier due to the feedback connection.
So, here we do have the circuit. So, the this configuration is given here, it is at the
sample side we do have shunt connection and also at the mixer we do have shunt and
hence it is called shunt feedback configuration or we may say that here we do have the
signal in the form of voltage and the signal here it is in the form of current. So, we are
having this voltage shunt-shunt feedback system.
Now, in this system to get the output resistance, the you know we are stimulating this
output port by vy as we have done before and we like to observe the corresponding
current entering to the circuit and then we have to take the ratio of this . But while we
are doing this exercise we have to keep in mind that input port; input port should be
supportive for this exercise namely we have to take the signal here it is 0 and in ideal
condition it is it is having 0 conductance of this not on equivalent representation of the
signal source.
So, if is = 0, here this port it is remaining open. So, with this condition we need to find
what will be the expression here. Now, if you and also we to start with we are
considering ideal feedback network, namely its input resistance it is ∞ and since it is a
1285
current source. So, we are considering output conductance is 0 or output resistance it is
∞.
So, with this what we are having it is the expression of the current iin. So, iin, if you see
here iin if this is 0 it will be = ‒ if the feedback current and this feedback current it is βvx.
So, iin = ‒ βvx and this vx it is incidentally same as vy. So, we can see this is equal to ‒
βvy and then also if I consider say this network to find the output current iy. We do have
the voltage source here we do have internal voltage source here and then we do have the
resistance Rout; this circuit is open.
So, we can say iy = . And iin its expression is given here. So, we can say this is
vy ‒ and ‒ is getting +. So, this is we do have . So, we can rearrange this
equation to get the expression of = .
So, this is the expression of this Rout, it is given here. So, you might have observed that
the unit here it is ohm and though we are using the same notation β here for the feedback
network, but then it converts voltage into current. So, its unit it is or ℧. So, after
making this multiplication this part it is it should be unit less. So, that is what we do have
β it is of course, it is having unit of .
Now, let we consider non idealistic situation one at a time or let we introduce one by
one. To start with if we consider that signal source it is having finite conductance; that
means, if I consider say some finite Rs. So, if I consider this is finite, then whatever the
current iin will be having it is not same as βvx, but it will be having a current division.
Part of this current it is coming through this circuit and remaining part it is coming
through this circuit.
So, we can say there is this iin, it is not entirely if we need to have some whatever the
fraction to be multiplied that fraction it is getting created by this Rs and Rin. So, to write
that let me again clear the board.
1286
So, we can say that iin = if which is of course, ‒ if. So, ‒ βvx multiplied by if I am having
say finite resistance Rs then the current flow here it will be , that we know from
network theory. So, we can and vx incidentally it is same as vy. So, again we can say this
is ‒ β′vy, where β′ now this β′ and the previous β′ they are different, this β′ it is β ×
And on the other hand the expression of this current iy = . So, this equation it
becomes vy ‒ and ‒ is getting +. So, we do have now . So, if we simplify it
then we can get = . So, that is the expression it is given here.
Now, again in addition to this if I consider that this circuit is also having some finite
conductance. So, if I consider this is a finite; that means, we do have Rout_β. So, this
current it will be having further division so, the current flowing through this one it will
be further getting reduced. In fact, these two resistances they are coming in parallel. So,
what we can say that this Rs and Rout of β-network it is coming in parallel. So, likewise
here also Rout_β ⫽ Rs.
⫽
So, let we call this is β′′. So, β′′ = β × . Rest of the derivation it will be
⫽
same except this β′ need to be changed to β′′ and expression of β′′ it is given.
1287
So, come end of it the output resistance it is getting changed to and where β′′
expression it is given here. Now, if I also consider that input resistance, this is also finite.
So, if I consider some finite resistance here, then we have to consider that resistance
effect also. So, whatever the previous Rout was there. So, we can consider this is also
coming in parallel.
So, the net resistance here it will be if I consider all the three non ideal factors, then I will
be getting the Rout_f it is having expression of ⫽ Rin_β. So, that is the change of
the output resistance particularly when output port it is having signal in the form of
voltage. Now, if we consider other two configurations where the signal at the output port
it may be current whereas, at the input port the signal may be current or voltage.
So, we can think of either it will be current amplifier or it will be trans-conductance

amplifier. So, in the next slide we will be talking about Rout_f, output resistance of the
feedback circuit for the current amplifier and trans-conductance amplifier.
So, we do have on this current amplifier it is given here. So, we do have current
amplifier along with its feedback and here as we have discussed the sampler it is series
and mixer it is shunt. So, the feedback it is series shunt or I can say current sample and
shunt feedback. So, it is current-shunt feedback.
1288
And to get the output resistance, to get the output resistance again we are stimulating the
output port by a voltage source and we are observing the corresponding current. In fact,
we can do it to the other way also, we can stimulate this output port by a current source
and then we can observe the corresponding developed voltage. And while we are doing
this exercise, we have to keep in mind that the signal here we have to make it 0, but then
port we have to keep it in such a way, so that it is supports whatever the feedback
connection we are making.
So, in ideal situation if I consider it is having 0 conductance or say source resistance it is

0 and if I consider the feedback network it is also ideal namely its input resistance it is 0
and so, this is 0, so that it will not create any problem while the current it is getting sense
and at the output conductance it is 0. So, this conductance it is 0 means the output
resistance of the feedback network it is ∞.
So, with this condition, we need to find what will be the expression of right. And to
get that again we can start from here and we can see iy or other iin = ‒ if = ‒ βix and this ix
it is incidentally = iy. Because, whatever the iy it is this current is flowing whether
through the internal current source or through this resistance finally, they are combined,
getting combined together and the return current should be consistent way this iy. So,
which means that ix = iy.
So, this ix = iy, so that gives us the expression of iin = ‒ βiy. On the other hand, if I want
to know what will be the corresponding current iy here, we do have two current
components. One is internal current AIiin and then current flow through this resistance
Rout and the voltage drop across this resistance is vy. So, since here we do have short
circuit.
So, we can see entire vy it is appearing across Rout. So, the corresponding current it
is . And expression of iin it is already given here so, we can say iy = ‒ βAIiy. So,
left side we do have iy and right side we do have this term. So, we can bring them
together to get iy + βAIiy.
So, we can take this iy common to get iy(1 + βAI) = . And from that we can get =
Rout(1 + βAI). So, this is the expression of the output resistance of this system and this is
1289
of course, under ideal condition. Ideal condition means the source resistance it is 0 and
then feedback networks impedances are supporting the ideal condition.
Now, again similar to the previous exercise, let we consider those non ideal factors one
introduce those non ideal factors one at a time and let us see the corresponding
cumulative effect. So, let me clear again clear the board and let we continue the
discussion.
So, the iin = ‒ βix × this so, what I want to say it is finite Rs is finite, it is non infinite. So,
it is we do have some finite resistance Rs. So, the current going through this main input
port of the forward amplifier iin is a fraction of this current in absence of the signal
source, it will be this current multiplied by the fraction getting created by Rs and Rin.
And this fraction it is from the current division we can get alright.
And this ix it is incidentally same as iy = ‒ β′iy where β′ = β × . And the other
equation at the output port it is remaining same namely iy = + AIiin and iin it is β′iy
with a ‒ sign, so that, we can take at the left side.
So, again we are getting the relationship between iy and vy in this form iy(1 + β′AI) =
. We can get which is given here. So, that is the Rout_f = Rout(1 + β′AI).
1290
So, likewise, if we consider finite conductance here as well, namely, Rout of feedback
network β. So, then the derivation it will be very similar except this Rs it is coming in
parallel with Rout_β. So, we do have Rout_β here and then we call this is β′′ and its
⫽
expression it is β × .
⫽
So, this derivation it is remaining same except this β′ it is getting replaced by β′′ and then
the output resistance it is finally, it is coming like Rout(1 + β′′AI). Now, the last item it is
if we consider this is also finite. So, if we have some finite resistance here. So, what will
be having it is that, that will be contributing to this output resistance and its contribution
it is that this Rin_β it is coming in series with whatever the previous resistance it was
there. So, we can say this resistance it is coming in series with that.
So, you might have observed that this element, presence of this element it is really not
disturbing. In fact, you can whenever you are putting this resistance we can think of that
we do have a series resistance getting added here. So, this resistance probably either you
can shift it here or here.
So, up to this one whatever the resistance you are getting it is given here and then we do
have this resistance coming here that is how we can visualize. And also we have seen
that the input resistor the output resistance it is getting increased because of this series
connection here and the increased it is essentially this desensitization factor it is helping
us to increase this output resistance or we can say that output conductance it is getting
reduced by this factor. And we need to be very careful while we are considering this load
affected β.
So, the fourth configuration where the signal here it is current and on the other hand
signal here it is voltage namely, the trans-conductance amplifier. So, we are going to
discuss about the output resistance change in trans-conductance amplifier in the next
slide yeah. So, here we do have the circuit, so, the, we do have the sorry yeah.
1291
So, we do have the trans-conductance amplifier here and the forward amplifier it is you
can see here the signal it is current and the signal here it is voltage. So, the mixing here it
is series and sampling here it is also series. So, this is series connection or current
sampling series mixing feedback network.
Here also it will be very similar to our previous discussion as we said that to get the
output resistance. So, we need to stimulate this circuit by one voltage source and then we
can observe the corresponding current here. Keeping the input port condition it is
supporting the feedback network namely we are keeping the source with a source signal
of 0 and for ideal condition to start with we are considering source term in equivalence
equivalent source resistance = 0. So, from that we can say vin = ‒ vf.
So, we have analysed lot of similar kind of circuit, almost similar kind of circuit
probably you yourself can now be comfortable to derive that vin = ‒ vf = ‒ βix and this ix
it is incidentally = iy. So, this is ‒ βiy and at the output port we can get the expression of
an iy = Gmvin and yeah. So, vin we do have in terms of iy ok.
So, we also have one more component + or we can say that iy = + Gmvin which
is we can say ‒ βGmiy. And from that we can get iy(1 + βGm) = and from that we can
get the output resistance of the feedback network defined by = Rout(1 + βGm).
1292
Now, again similar to the previous case, if we consider non ideal factors namely if I
consider this is nonzero, then I have to consider the corresponding β′. And the expression
of the final output resistance as we have discussed earlier which it will be Rout(1 + β′Gm)
where this β′ in presence of this resistance it is coming due to the potential division
happening between this Rin and Rs.
So, we can say β′ = β × , rest of the things it will be very similar. And now in
addition to that if I consider the output resistance of the feedback network, namely if I
consider this is non-zero Rout_β. So, if I consider Rout_β then I need to consider different
node affected β called say β′′ and its expression it is given by β′′ = β × .
So, with this expression of this β′′, the output resistance it becomes Rout(1 + β′′Gm) and
then, the last non ideal item if we considered it is having some input resistance which is
nonzero say Rin_β and if I consider this circuit again this resistance contribution of this
resistance it is simply getting added. In fact, this resistance as I was discuss in previously
we can think of it is getting shifted here without hampering any arrangement here.
So, the resistance here it will be whatever the resistance we do have without considering
this resistance in series with this resistance. So, that is why you can think of the total
resistance, it will be the main feedback circuit resistance in series with the input
resistance of the feedback network that completes all four possible configurations. Now
whatever the discussion we do have related to change in gain input resistance and output
resistance probably that will be clearer if we consider some numerical examples.
1293
So, we do have some interesting numerical examples also to have seen starting example
it is a voltage amplifier, we do have a voltage amplifier here. So, this is the forward
amplifier and the feedback along with its feedback connection of course, the feedback it
is shunt here and series here; that means, voltage-series feedback connection.
The given parameters are here, input resistance it is 1 k, output resistance it is 4 k, Av the
gain of the forward amplifier in ideal condition it is 200. On the other hand for the
feedback circuit the β = 0.095 of course, this is converting voltage to voltage. So, it is
unit less.
And also we do have say signal source vs having say 0 source resistance and vs = 100
mV. We need to find the value of the voltage gain from the primary input to the primary
output defined as denoted by Av_f and defined by . So, we need to find what will be this
ratio. We also need to find what is the input resistance of the feedback network and also
we need to find what will be the corresponding output resistance of the and the circuit
and Rin_f here.
And also what may be the corresponding voltage and that we need to find for two cases.
Case-I; when you consider feedback network it is ideal one and case-II where feedback
network it is having finite input resistance and also it is having finite output resistance.
So, rather nonzero output resistance. So, this part probably it will be straightforward, but
1294
this part it is very tricky. So, before we go into that let me take a short break and then we
will come back.
1295
Prof. Pradip Mandal
Lecture - 94
Feedback System (Part- E)
So, welcome back after the break. So here we do have numerical example and what is our
objective here? It is that we need to find the voltage gain of the feedback system, input
resistance, output resistance of the feedback system and the output voltage for an input
voltage or the signal voltage of 100 mV.
And the parameters of the feedback systems are given here input resistance and output
resistance of the forward amplifier and the gain of the forward amplifier it is 200 feedback
network, the feedback factor it is 0.095. So to start with, let me consider this relatively
simpler case, case-1 where we consider ideal feedback network having the input resistance
it is infinite and its output resistance on the other hand it is 0 as we are generating voltage.
So 0 output resistance it creates the ideal Thevenin equivalent voltage. So let me clear the
board, yes. So to start with, let we have the derivation of this Av rather A′v or rather Av of
the feedback system Av_f.
1296
As we know that this Av_f it is the forward amplifier gain . So the Av it is given 200
and on the other hand, feedback factor it is 0.095 and Av it is 200.
In fact, we have picked up these numbers such that we do have in the denominator this part
it is becoming twin 19 and then we do have 1 here. So that is giving us in the denominator
it is 20. So the gain of the feedback system it is 10. Now, to find the value of the input
resistance Rin_f. As you can now guess that since we do have series connection here Rin_f, it
is getting amplified by the desensitization factor.
So that should be Rin(1 + βAv). And Rin it is 1 k × 20 and that gives us 20 kΩ.
So note that just by this feedback network the input resistance it is getting increased by a
factor of 20 which means that if the main amplifier input resistance it was 1 k, the feedback
system input resistance it is becoming 20 k. Rin_f it is 20 k. So whenever for some
application, we have to increase the input resistance we should consider the series mixer
and then we can enhance the input resistance.
Now, we need to calculate the output resistance Rout_f. So, now here we do have shunt
connection. So the shunt connection it is reducing the resistance which means that the
output resistance it will be = = 200 Ω.
1297
So now we obtained input resistance of the feedback system, output resistance of the
feedback system and next thing is that what is the output voltage? It is very straight
forward. From here to here, the gain we obtain it is Av_f. So, here to here the gain it is 10.
So it is giving us very simple situation. So the output voltage vo it is 10vs. So that is giving
us 10 × 100 mV = 1 V.
So the case-1, it is relatively straightforward, we have used the whatever the formula we
have obtained namely, the gain got decreased then and the voltage gain got decreased,
input resistance got increased and then output resistance and got decreased. Now if I
consider the 2nd case, I should not say it is ideal. So this part may be ideal, but with finite
resistance. In fact, we are considering relatively low input resistance.
So we are considering non-ideal rather non-ideal feedback, and input resistance it is 200
and output resistance coming in series. So, that is 1 kΩ. With that we need to find the
corresponding feedback system gain input resistance and output resistance.
So, before we start. So this should be non-ideal, I should have said it is non-ideal.
Before we start, let we consider since we do have since we do have finite input resistance
and output resistance of the feedback network, the input resistance here it is affecting the
output port. So the voltage will be getting here, it is not same as this internal voltage.
1298
Rather, we may say that load affected voltage, let me use different color here. So we need
to be careful that Av it is giving us 200, but A′v it is different.
So, how do we find this A′v? So the way we define this A′v it is Av multiplied by whatever
the load we do have here, it may be external or it may be internal part of the feedback
network. So in this case, Rin_β it is loading. So, the loading factor it is = 200 ×
that gives us .
So, I have some calculation for you. So this is 9.523. So we have to keep this in mind.
Likewise, when we see the feedback network, since we do have output resistance of 1 k.
So whatever the voltage we are developing here, βvx it is not directly coming there. In fact,
if I consider Rs = 0, the corresponding load affected β called β′ = β × . So this is
1 k this is also 1 k.
So, that gives us this part it is 0.5. So we can say this = . So a priori we should keep
these 2 parts, load affected A and load affected β ready for our consideration. Now if we
have to find what the corresponding gain is, voltages gain of the entire network. So, Av_f
we can say load affected Av divided by 1 plus load affected β and then load affected Av.
So we do have here it is . In fact, again I have done this calculation. In fact,
in this case the desensitization factor this part it has drastically changed. So if you consider
its value here and here the value here it is 1.45238. So the value here for this Av_f it is
= 6.5573. So earlier the gain from here to here the gain it was 10.
So if we are applying say there is 100 mV. So what we are expecting this voltage the
corresponding voltage here it will be 655.73 mV. As the gain of this entire circuit for this
case it is 6.557. So, this is also obtained. So next thing it is that, what is the input resistance
and output resistance of the feedback system? Again we have to keep this in mind that A′v
it is 9.5238 and β′ it is this one and the desensitization factor corresponding desensitization
factor is given there.
1299
Let me also keep A′v which just now we have obtained it is 9.5238 and β′ it is and
also (1 + β′A′v) it is what we say, it is desensitization factor it was 1.45238. So, we need to
find what will be the Rin_f. So we are knowing that the input resistance it will be getting
increased. But should we consider Rin(1 + β′A′v). Should I be getting this value correct?
Now this Rin, it is representing only this resistance. In fact, there it is having 2 alternate
approaches. So definitely this is not correct. We should consider what is the corresponding
R′in. And what do we mean by R′in? It is we have to consider this Rout_β also along with this
Rin. So the R′in. In fact, this R′in, if I put R′in then it is of course, it is correct. Where these
R′in is equal to the input resistance of this circuit in absence of this feedback signal.
So if I say this signal it is 0, the input resistance it is Rin and Rout_β is in series. So, R′in = Rin
+ Rout_β = 2 kΩ. So, we do have 1 k here and another 1 k here. So it is basically 2000 Ω. So
the input resistance it will be 2000 here multiplied by (1 + β′A′v).
So, we do have this number 0.45238 and that is giving us a value which is 2.9047 kΩ. So
earlier the input resistance it was 20 kΩ. Now that got drastically reduced to 2.9 kΩ only.
In fact, whenever and also we already have obtained Av_f. So, its value it was 6.5579.
So, for both this Rin_f and Av_f it is having alternate way of calculating say to explain say
this part, the let me use the alternate expression Rin_f can also be considered as a Rin(1 + β
A′v) in series with Rout_β.
1300
In fact, both of them are same first of all here we consider Rin only without dashed. So,
here we do have 1 k and then here we do not have β′. So we do have one plus 0.095 only,
but then A already got affected by whatever the resistance we do have. So that is A′v we
have to consider A′v. So that is multiplied by 9.5238 in series with 1 k. So if you calculate
here, what we will be getting it is this part it is coming 1 k multiplied by 1 point.
In fact, I do have the calculation for you. This will be 1.9047 k + 1 k. So that gives us
2.9047 k. It is same as whatever you do have. So we do have this alternate approach. In
fact, same way you can find for this Av_f also. In fact, we have used this expression of Av_f
where we consider .
So the alternate approach to calculate this Av let me use this space it is we can consider
Av_f = × ok.
So, this calculation I will be showing you once we get this Rout_f. So let me find this Rout_f
first and then we will be discussing about the alternate approach of finding this Av_f.
Similar to Rin_f. So to, now next thing is that we are going to calculate Rout_f for this case.
But before that, let me clear the board. Please keep the information in mind that A′v and β′
and those things.
1301
So to get the Rout_f what is the formula we can use? There are 2 formulas, one is we can
consider all are load affected. So, where this R′out it is the Rout here and if we have
this Rin_β whatever the net output resistance we will be getting without considering this
feedback network. So that is the Rout.
And if I consider this R′out, it is essentially Rout ⫽ Rin_β = 4 k ⫽ 0.2 k = right. I
have some calculation for you; I was having 190.47 Ω only. As you can see that this
resistance it is quite small. So that is dominating and so, this resistance it is very small.
So, the β′ and A′v we already have calculated before. So A′v it is 9.5238 and β′ it is
and this factor it is 1.4 something right 4 5. So that gives us Rout_f = . In fact, this is
equal to around 131 Ω only. So similar to Rin_f for Rout also we do have alternate
expression. So what is the corresponding expression? This Rout_f we can say this is
ok. So this is without considering this resistance.
Now all of a sudden if we say that this is appearing. So we need to consider then Rin_β in
parallel but while you are doing this, you need to be careful that not only this Rout we are
considering the inherent Rout there. But also this Av it is not load affected ok. And in fact, it
can be shown that this is this part it is coming 10.5. So, this is Rout it is 4 k divided by this
is 10.5 because the Av it is 200 so that is why it is 10.5. This is in parallel with 0.2 k and in
fact, this is also becoming 131 Ω.
So we do have this equation, this equation as well as this equation. Again, I like to; suggest
you that these 2 expression difference are here we do have R dashed, but here we do not
have any R dashed. Also here, we do have A′v, but this Av is not having any dashed this is
Rin_β is already it has been captured here and here. So, we do not consider this Rin_β here,
but in this case on the other hand Rin_β it was completely ignored; now we can incorporate
that.
But while we are doing this exercise the β however, it is remaining load affected. So when
the conclusion is that whenever we are trying to see the output resistance, either we can
incorporate this resistance as part integral part of the amplifier and accordingly, we modify
this Rout to R′out and also this Av to A′v and then you can use this equation. Or the alternate
1302
approach is that we can keep this part aside thinking that this resistance it is here and here
the resistance it is infinite it has been shifted there.
And then we do calculate whatever the resistance we do have by this formula where both
Rout it is inherent Rout, Av it is also inherent Av and then we consider this Rin_β into
consideration by considering its parallel connection. So now we do have the value of this
Rout if whether we do have this equation or this equation. In fact, if you consider this part
this part without considering this we obtain.
So, we may say that this is also some form of the Rout_f without considering Rin_β. So, as I
was telling that Av, Av_f it is having two approaches one approach you already have
discussed by considering this A′v and β′ together. The second approach now we are going
to talk it is the following.
So, if we have say, we need to find what will be the Av_f? What we can say that let we
postpone the effect of Rin_β. So this effect of this Rin_β will be postponing. So instead of
putting it here, if we connect it here and first we calculate what is the corresponding Av
here and then we can consider this part.
So the without considering this the Av internal Av it is or internal Av_f or intermediate Av_f
it is multiplied by whatever the loading effect it will coming due to this β in Rin_β.
1303
So, that is that factor it is Rin_β divided by Rout of this intermediate resistance. So let me call
this is say + Rin_β where is essentially .
So that means, the whatever the in output resistance we are having without considering
this Rin_β. And if you do the calculation here Av of course, we do have 200 and this is
. And then we do have this resistance it is right.
So this is this resistance plus Rin_β that is 200. In fact, this part it is 10.5. So that gives us
× . In fact, this is also coming equal to 6.557. In fact, this is same as whatever
earlier we obtained the value of this Av_f.
So, we do have alternate approaches to find this Av. So either we consider this resistance as
internal part of it or we can postpone its consideration. But of course, we have to keep in
mind that β we need to consider here. So that is how we can get the value of this the
voltage gain input resistance output resistance and output voltage in terms of whatever the
forward amplifier parameters and feedback networks parameters are given to you.
So similar kind of exercise you can do for other configurations. So right now it is voltage
amplifier and the in the next slide we do have another numerical examples.
1304
It is very similar. However, in this case, the circuit is trans-conductance amplifier and so
the signal here it is current. So, the sampler it is series and it is sampling current and the
mixer it is series as the signal here it is voltage. So here again, the gain of this circuit it is
Gm it is given to us which is 100 mA/V, input resistance remains 1 k output resistance here.
Of course, this is in the form of conductance. So, that resistance it is coming it is 4 k. β, on
the other hand it is 90 Ω.
You might have observed that since this Gm its unit it is the expected unit of β it is it
should be Ω and the value here it is 90, the input voltage we are feeding here it is 100 mV
and you need to find what will be the output current? Also you need to find what will be
the overall transfer function? Namely, overall Trans-conductance Gm of the feedback
system Gm_f.
Then input resistance of this circuit and then and the output resistance particularly,
whatever the output conductance we will see. So whatever the output conductance we will
see that is . So that also you can find. Now, to start with, we can consider the ideal
feedback network and then after that we can consider non-ideal situation. So in the ideal
situation of course, it is pretty straight forward. So both Gm and β they are not affected by
load.
So to avoid the loading effect, we do have 0 load resistance. Here, the resistance is 0 and
here the resistance 0. So, there is no loading effect. So directly we can use this Gm and this
β. So the desensitization factor = (1 + βGm) = (1+ ).
So what we have here it is desensitization factor it is 10. So for this case this case at least
we can say. So, right now we are considering the first case Gm_f. So, Gm_f = =10
mA/V. In fact, from that directly you can say that this io it will be 100 mV × 10 mA/V. So,
that gives us 1000 µ or 1 mA for this signal.
So likewise, we can calculate the input resistance. So, Rin_f as you can anticipate the input
resistance it will be increased. So, original input resistance Rin it is 1 k × the desensitization
factor 1 + βGm.
1305
So, this is we do have 1 k × 10. So, that is equal to 10 kΩ. Similarly, if I consider output
resistance Rout, here also since it is series connection. So we are expecting that Rout will
also be getting increased by this desensitization factor namely, 1 + βGm.
So we do have original resistance for the forward amplifier it is 4 k × desensitization factor

of 10. So that gives us 40 kΩ. So, that is how we can calculate for the case-1. So likewise,
you can make an attempt to consider the second part.
So, I may not be going all the solution for that, but I am going to give you hint for this
non-ideal situation, where the input resistance it is 100 Ω and the output resistance of this
circuit it is say 4 kΩ. So to start with, we need to find what is the corresponding G′m and β′.
So from that, probably we can get a hint of how to calculate Gm_f. Gm whenever we are
saying that G′m which means that what may be the current in presence of this resistance? If
this is having 0 resistances this entire current it was flowing through this circuit. So, the io
it was simply Gmvin.
Now in presence of this resistance, this current it is getting segregated; 1 part it is flowing
through this the other part it is flowing through this one and whatever the part it is flowing
through this that gives us this io. So to get this io in presence of this resistance, we need to
consider this factor and that is .
1306
So, we can say this is the G′mvin where G′m = Gm. Gm it is 100 m × = mA/V =
97.56 mA/V. So likewise, you can also calculate the corresponding β′.
And this β′ it is of course, here it is the signal it is we are mixing in the form of voltage, and
the β′ it is the original β multiplied by whatever the potential division it is happening due to
this 4 k resistance here along with this input resistance Rin and its expression it is β ×
.
So that is β it is 90 and Rin it is 1 k and this is 4 k. So, this is . So that gives us β′ = 18. So,
that is how we can calculate G′m and the β′. So likewise, you can find what will be the R′out;
that means, the output resistance in presence of this 100 Ω.
So, definitely this resistance it is in fact, if you see here, this resistance it is coming in
series. So, this will be 4.1 kΩ and likewise, R′in we should consider. So in absence of this
part R′in it is 1 k + 4 k that is the 5 k. So now we obtain the load affected, all these load
affected parameters and from that you can calculate what will be the Gm_f and then Rin_f
and Rout_f and so and so on for this case.
So what is the Gm_f? You may recall similar to whatever we have done for the previous
case, it should be . We do have alternate expression also. But let we consider this.
So likewise, when you consider Rin of the feedback circuit. So, what should we consider?
We should consider Rin load affected and we know that input resistance it is getting
increased by a factor of (1 + β′Gm).
Sorry G′m and likewise, whenever we are talking about Rout, Rout of the feedback system
here the output resistance it is getting increased compared to its R′out. R′out we already have
4.1 k (1 + β′G′m) and G′m it is given here and β′ it is 18, so, we can find what will be the
corresponding factor. So I think you yourself can calculate this one it is now it is a matter
of using your calculator.
1307
So, to summarize all these 4 sub-lectures, what we have discussed in this topic of feedback
system. So, far we have talked about basic concepts of the feedback system, there we have
introduced how we define the feedback system and then we have talked about 2 basic
types of feedback mechanism or feedback system namely, +ve feedback type and ‒ve
feedback types feedback system.
And subsequent discussion it is mostly related to ‒ve feedback system. So then, we have
talked about transfer characteristic of feedback system namely, feedback system transfer
characteristic Af = . So also, we have talked about loop gain = ‒ βA then,
desensitivity factor, D = (1 + βA).
Then we have talked about 4 basic configurations which normally it is common in

electronic circuit and we have discussed about their characteristic. So these are the enlisted
4 basic configurations we have discussed about how the gain it is getting changed.
And also we have talked about how the input resistance and output resistance of the system
it is getting changed by the desensitization factor. And then we have discussed about 2
numerical examples associated with 2 feedback configure different types of configuration
starting with ideal situation and then also we have moved to non-ideal situation. I think
that is all we need to cover.
1308
Prof. Pradip Mandal
Lecture – 95
Effect of Feedback on Frequency Response (Part – A)
Dear students and participants, welcome back to our NPTEL online certification course
on Analog Electronic Circuits myself Pradip Mandal from E and EC department of IIT
Kharagpur. Today’s topic of discussion it is; it is continuation of feedback circuit and
what we will see that the Effect of Feedback network on Frequency Response of the
forward amplifier. So, if we recall the our overall plan.
So, we are according to our schedule we are in week-10 and it is module-9. And at
present we are system and subsystem level of electronics analog electronic circuits. And
as I said that we already have started feedback system and four different configurations
we have seen. And today what we will see that change of frequency response of an
amplifier due to the presence of feedback network.
In general, we can say that it is valid for even other linear circuit, but our specific focus it
will be on amplifier. And also the when you say frequency response, it is primarily our
focus it will be on gain of the amplifier, but that is also applicable for impedance. In fact,
that is applicable for with other gains also current gain, transconductance,
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transimpedance and so and so. So, our discussion today it is relatively generic and we
will see that how the frequency response changes due to the presence of feedback circuit.
The concepts we will be covering today it is primarily how the locations of the poles are
getting changed, in the feedback system and that is due to the location of the amplifiers
poles and also the poles of the feedback network. We shall focus on the situation where
the amplifier may be having one pole or maybe it is having two poles or maybe three
poles. And also, we will be considering cases where feedback network may not be
having any pole only the amplifier maybe having pole or maybe the amplifier as well as
the feedback network may be having poles.
1310
Now, let us come to the first case before we go into the first case again we like to
recapitulate what we have discussed. In fact, we have discussed this kind of situation
where this is the forward amplifier, this is the feedback network and then, we do have
signal mixture and then we do have signal sampler.
And the forward amplifier gain it is A and the primary input to primary output gain what
we call feedback system gain Af and as we know that this feedback system gain it is
. In fact, this equation is very powerful it is applicable not only in time domain; it is
also applicable in frequency domain. So, today’s discussion it is primarily in Laplace

domain, in the frequency domain.
And this equation in Laplace domain also it is valid. So, if we concentrate the feedback
system in Laplace domain, then each of these say transfer function particularly A and β
is having frequency dependency and the transfer function now it is getting represented by
A(s) and β(s) and likewise the signal may be having frequency dependency and so and
so. But then even in this situation the feedback system transfer function defined by
primary output to primary input it is and you may also recall that ‒ of A and β it is
loop gain.
Namely once you go through this loop whatever the transfer function it will be
experienced by the signal, Aβ and a ‒ sign here maybe we do have a ‒ve terminal here.
1311
So, the loop gain what we are discussing it is it is also having a direct dependency on
whatever the poles we do have in the A. So, the effectiveness of this feedback network or
the loop gain to change this transfer function of the feedback system is also, it also
depends on the location of the poles and of course, we do have the desensitization factor.
Now, in our foregoing discussion we shall assume that this system it is ‒ve feedback
system which means that here to here we the signal it is experiencing 180° phase shift
and also we are assuming that A at s = 0 frequency, it is +ve. And likewise β at s = 0, it is
also +ve and this ‒ve sign indicates that under DC condition which means that s = 0
under DC condition the system it is ‒ve feedback system and the system is stable.
So, we will be discussing about amplifier which is linear circuit and in presence of ‒ve
feedback the linear system remains linear. But of course, depending on the situation
location of the pole may create some issues which it will be discuss later, but let us try to
see one by one. Suppose this A is having one pole then what is its influence on the
location of the pole of the feedback system?
So, to start with let you consider case I, what we have in this situation it is yeah. So,
when you say case I we assume that β it is independent of frequency. So, we can say that
β is remaining constant and in the system, it is ‒ve feedback system in DC condition and
let you consider that forward amplifier it is having a transfer function which is having
only one pole. Which means that A(s) can be written in this form, Ao is the low
1312
frequency gain or you can say almost in the DC condition, what is the gain and then it is
having a pole at s = p rather s = ‒ p.
So, this pole it is left off pole and of course, the system is stable. Now, if you recall that
the feedback system transfer function assuming it is having a minus sign here it is
and A(s) it is given here and β is independent of frequency.
So, if you write the expression of this A(s) here what we are getting in the numerator it is
and in the denominator we do have 1 + β × . Now, this factor we can take it

( ) ( )
here and so this factor it will be coming in the denominator of denominator. So, that part
it is getting cancelled here. So, what we will be having here in the numerator it is Ao.
And in the denominator we do have ( ) + βAo. Now, further if we rearrange this
equation what we can do here it is the constant part we can take it aside. So, namely in
the numerator we do have Ao and in the denominator we do have 1 + βAo + . Now, if I
take this part this part it is a constant part outside, so what we can get it is in the
numerator again Ao and in the denominator with if I take (1 + βA) as a common factor.
What will we be having here it is 1 and then we do have right.
And then what you can say that this part it is independent of frequency and let you call
this is the gain of this feedback system at low frequency and let we denote this by say
Ao_f. And this part on the other hand if you see here this part we may say that this is the
new pole and we may denote this by say p′. So, what we can get here it is that transfer
function of the feedback system, it is having low frequency gain Ao_f were, Ao_f it is
defined here divided by ( ).
So, this p′ is the location of the pole of the feedback system which is of course, it is
function of p × (1 + βA). So, this is this is what we do get that the location of the pole of
this feedback system starting from primary input to primary output, it is a function of the
location of the pole here and also getting multiplied by (1 + βAo).
So, as I say that in this case this is and this is independent of frequency, this is also
independent of frequency which means that the location of the p′ it is clearly it is a
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shifted version of this p ok. So, if you look into the bode plot of the feedback system
namely if we sketch the gain and phase of this Af and along with probably the gain and
phase of A and the loop gain you can find very interesting correlation.
So, in the next slide let we continue on that. So, let we try to make a plot of this A for a
location of pole-p. So, first of all we are going to plot gain. So, the y-axis it is we are
considering it is in dB scale linear scale, but it is data is getting converted in the form of
decibel and x-axis it is ω in rad/sec and in log scale. So, if I consider this plot for say to
start with let you consider A.
So, A is having a low frequency gain Ao of course, it is converted into decibel dB and
then it is having a pole and beyond that it is having a role of like this. So, we do have a
pole here p and this is 20 log(Ao) or simply you can say that Ao converted in dB and so
this is the plot of the gain plot of A. Where, of course, s we are replacing by jω and then
we are considering magnitude of A and then we are taking 20 | | for different
values of ω. So, this is what we are plotting here.
So, likewise if you consider the loop gain or ‒ loop gain assuming we do have a ‒ sign
here, what we are expecting is that this location of the pole of A it is directly getting
reflected in the loop gain. So, if I sketch the loop gain here, so β < 1. So, we are
assuming this is β < 1 which is of course, this is that is the typical case.
1314
And it is having the same pole and then it is having role of 20 dB/dec. So, this is β now
sorry the loop gain magnitude of the loop gain and this is A. And then if you consider Af
on the other hand what we are getting here it is Af in the low frequency region we do
have a gain which is given here which is , you may say that this is approximately .
So, if β < 1 which means > 1. So, if I say this is 0 dB level, so the β is it will be like
this.
So, this is Af, but of course, we consider the magnitude of Af and the value here what we
can see here it is 20 ( ). And then what will happen here? If you see this
equation, so this it is getting desensitized by this factor. So, as long as this part it is quite
prominent namely the loop gain part, then we can say that it is approximately . So, it
will continue to remain constant till this part it is coming less than 1.
So, this is the frequency where loop gain it is crossing 0 dB which means that beyond
that this part it is very small compare to 1 that is what you can approximate and by the
way we are drawing asymptotic gain plot, the actual one of course, it will be deviating.
So, almost at this point or beyond this point this Af, it will meet the gain plot of A and
beyond this point Af it is trying to continue or rather it is following A.
So, why is it so? Because from this frequency onwards this part it is getting very small.
So, if I ignore this part compared to 1, then what I have it is Af = A(s) = = A(jω).
So, we can say from this point onwards Af it is following A in other words we can say
that it is having a bend and this bend it is imposing a pole incidentally that is what this p′
and this p′ it is p(1 + βAo). So, in in conclusion what we can say that in the forward
amplifier we do have a pole here p that pole it is getting shifted to p′.
So, apart from the amplifier gain it is dropping from this level to this level, it is also
having a consequence that the pole it is getting shifted from p to p′. And incidentally in
this case the reduction of this gain it is happening by this factor (1 + βA) and the increase
of this pole location or the pole it is getting shifted by the same factor (1 + βA).
And finally, the gain bandwidth product or unit gain frequency this is remaining same for
A and Af right. So, this is what we are expecting that if there is any pole in A, the
1315
corresponding pole of Af it will be getting shifted by this factor (1 + βA). Now, let me try
to plot the phase also yeah. So gain we have ok. So, we do have gain plot, no ok. So, let
me clear this board and then come back to the gain and phase yes.
So, if I consider gain and phase together as we said earlier. So, let me quickly redraw the
gain part. So, A it was like this and then loop gain it was βA with a ‒ sign and so this is
the loop gain part and then this is the location of the pole. So, this is loop gain, this is
corresponding to A and then you also have sketched Af and what we said is that beyond
this point Af it is continuing or rather following A. And we can say that the
corresponding pole p′ is p(1 + βAo).
Now, if we are plotting the phase for Af what we can say that let me plot the; phase angle
of Af. So, if you see here till this frequency the phase it is almost 0 and then once it is
approaching to pole, it will be getting shifted to ‒ 90°. So, it is going from 0° to ‒ 90°
and at the location of the pole it is ‒ 45°.
If you compare the original phase or rather phase of the mean forward amplifier, its pole
it was at p and its phase it was rolling at p and of course, it was going towards 90°. So,
this is the phase for A and the blue color it is the phase of Af. In fact, this phase it is same
for the loop gain also; however, if you put say loop gain with this ‒ sign instead of
starting from 0° it will it is supposed to start from ‒ 180° or 180°. So, that is the change
of the phase and gain plot.
1316
Now, if we consider a situation where suppose this a it is having two poles namely say p1
and maybe one more pole p2 and then we can try to see what may be the situation. So,
that we call it is case-II and to get a better picture let me start with a situation where p1
and p2 they are really wide apart and if I consider p2 it is much higher than p1, then we
can get a clear picture how the poles are getting shifted ok.
So, in the next case let me try to consider A is having two poles namely p1 and p2 and
then we can see what is the corresponding location of the pole of the feedback system.
So, here again in this case we consider it is ‒ve feedback system in DC condition β also
remaining independent of frequency and the forward amplifier it is having two poles p1
and p2. And the this location of the p2 it is not only much higher than p1 magnitude wise,
but let we consider p1(1 + βAo) is also lower than p2; which means, that we are expecting
this p1 it will be getting shifted by this factor and probably this will be the shifted version
of p1.
And then we like to consider this case where p2 it is even beyond this location of the
pole, then it whatever then we can try to see what may be the situation for p2 ok. To start
with again let we consider Af and the expression of Af it is and now we do have A it
is given here.
1317
So, let me put the expression of A here. So, what we are expecting in the numerator it is
; divided by ( ). Now, this part if I put it here, so then from

( )( ) ( )( )
this denominator this factor and this factor they are getting cancelled here. So, what we
can get in the numerator it is Ao and in the denominator what we get ( )( )
So, if you expand this part what we can get it is one second order polynomial which is
having . So, that is the corresponding denominator we will be
getting.
Now, this part as you have done before this part and this part they are independent of
frequency, so we can club them together and then we can take this factor outside. So,
what we will get? In the denominator we will get a factor of (1 + βAo) like this and in the
numerator we do have Ao. So, this entire part it is independent of frequency and then
remaining portion what will get here it is similar to this part, but we do have (1 + βAo)
factor. So, that is what we do have here.
So, the expression of Af it is × , so and so and finally, what I will like to say
that we do have the second order polynomial. Now, let us try to put some approximation
to get a meaningful conclusion here.
1318
So, first of all this part as you have done before let you consider it is independent of
frequency and let you call this is Ao_f, so this is the Ao_f. And then as you can see here
this second order term let we try to retain as is and this condition indicates that this part it
is dominating. So, we are keeping this dominant part, so the linear term we are keeping
unchanged at least this part.
And then quadratic part or a second order part we are keeping unchanged, but then this
part we are intentionally trying to make some approximation instead of considering this
part let you consider and that is allowed because compare to this linear term this linear
term of course, it is very small under this condition. And why we do this, we are
retaining this part that is because if I now, multiply this part and this part together I can
get this term.
So, this instead of having this factor if I consider and if I ensure that product of this
part and this part it is matching with the quadratic term that helps me to do the
factorization. So, what we can say here it is numerator is Ao_f and the denominator it is
( )( ).
So, note that we are getting this approximation under this condition. So, now, we can say
that this is this is the updated pole and this is also updated pole and interestingly this is
we call say p′1 which is which is the case similar to a single pole situation.
And then p2 you may say that now this is a pole second pole of the Af which is again
approximately equal to p2.
So, in summary we can say that Af it is having two poles, but one of the these two poles
it is almost remaining same as the location of the pole of A; but then the other pole p′1 it
is getting shifted by a factor of with respect to original p1.
1319
So, the conclusion here it is in the next slide it is what just now we said it is yeah. So, we
do have this Af and this is what the approximation we do have and this is helping us for
the factorization and as I said that this p′1 it is and p′2 ≈ p2. Why this
approximation? In fact, I should say this approximation is basically leading to this
approximation. In fact, we may say this is also approximation, but it is a fairly a good
approximation. Now, if you see the bode plot for this situation namely the gain of Af and
A and of course, the loop gain under this condition we can find some conclusion for
some information.
1320
So, in the next slide let we try to make the gain plot. So, if I consider a yeah, so let me
start with A and this is ω in log scale and this is gain in dB. So, to start with if I consider
this A, we do have a pole here at p1 and then we assume that and the corresponding
second pole it is sufficiently high or located at very high frequency. So, it is having a
pole here say p2 and here it is p1.
And it is such that we assume that once this p1 it is getting shifted by this factor we are
assuming that p2 it is even beyond that. So, now, if I plot the loop gain, so if I consider
this ‒ loop gain βA and again β it is less than one and it is independent of frequency. So,
what we can say that the pole of the loop gain it is essentially pole of A itself and then it
is going down like this.
So, this is the minus of loop gain plot and this is A, this is gain in dB as you have discuss
before. Now if I consider Af and what you are expecting depending on this value of β
which is less than 1. So, the feedback system gain ≈ which is more than 1 which is
above this 0 dB. And it is again it is continuing to this value till it is hitting the A and
beyond this point it is continuing to be A or rather it is following A and then of course,
we do have the second pole here.
So, we can say that this corner it is representing the first pole of Af which we call say p′1
= and beyond this one of course, we do have the p2. So, we do have we call
it is p′2 which is very close to this p2 ok. And if you consider the corresponding phase
what we can see here if I start with A phase it is starting with.
So, this is phase of A say. So, at this point we do have the phase getting rolled off to 90°
and then again we do have the second pole. So, while it is approaching to the second pole
it is going one more step to ‒ 180°. So, this is ‒ 90° this is ‒ 45° this is ‒ 135° starting
with 0°.
Now, if I consider Af on the other hand, so this is the gain of Af in dB and its pole it is
here. So; obviously, its phase it is continuing till it is approaching to p′1 and here you can
see that it will be having a step here and then probably it will be having the other one.
So, depending on the spacing or separation of this p′1 and p′2, it is having essentially
either two steps or maybe these two steps may be very close to each other.
1321
So, this is the phase of the feedback system Af right. So, that is how the poles of A it is
influencing the pole of the feedback system. Now, the natural question is that suppose
this one p′1, which is say if it is comparable with the original p2, then what
kind of things we do expect here?
So, we will be talking about similar kind of case we call case II-B and case II-A we are
considering p2 it is beyond this one. Whereas, case II-B we will consider this p′1 it may
be comparable with p2 or it may be beyond that. And then what happens whether this
pole it will be remaining there or whether there will be some other changes that we like
to see. But before that let me take a short break and then we will come back.
1322
Prof. Pradip Mandal
Lecture – 96
Effect of Feedback on Frequency Response (Part-B)
Welcome back after the short break. So before the break, we are talking about the
location of the pole of the feedback system. And as you can see here, the condition and
in fact, I should have taken this p2 even beyond this location of p′1 for a clearer picture.
So, if I consider say, p2 it is even beyond this point, something like this and then if it is
having p2 ok.
So, if I consider this is the p2 then the corresponding phase it could have been like this.
For a and then p′2 on the other hand, it is instead of here, this is p′2 and which is same as
p2 then this blue line, the phase here for Af we could we can say that the phase it is
having very clean step like this one.
Now if this p2 it is in the near vicinity of p′1, then what will happen? That is what we
need to investigate in our next discussion. And we consider that case, it is case II-B there
also we consider 2 poles for A, but the conditions the condition is different. So let me
clear the board and let me go to that case yeah.
1323
So here we do have that situation. So first of all, forward amplifier it is having 2 poles; p1
and p2, β is independent of frequency and the system of course, it is ‒ve feedback
system. And we consider p1; it is lower frequency than p2 which means that p1 is referred
as dominant pole.
But the anticipated shifted version of this p1 namely p′1, if it is comparable will with p2,
then what happens? So if I again if I come back to the feedback system gain Af which is
having an expression of and then we obtain this expression. Now while we will be
doing the approximation of this equation, we can consider this case.
And we may say that instead of really considering this part, let we completely ignore this
part to have a meaningful conclusion. So what we are doing is, we are retaining this part
and we are keeping this part here, but this part since it is very small compared to this
one, we may drop this part.
So with this approximation, what we are getting here it is we do have only these 3 terms
and this is of course, valid because as I say that p2 it is much higher than p1. So if I
multiply both these poles by (1 + βAo), then this condition remain same which means
that this part it is very very large compared to this part.
And the reciprocal wise, if I see then I can say this is dominant term compared to this
one. And hence, we can do this approximation, we can eliminate this part or we can drop
1324
this part. Now after dropping this part, what do we have? We do have of course, the
second order equation and from this second order equation, if I say that these 2 are
comparable, then a factorization of this pa equation may or may not be having
meaningful factorization.
Or rather, I should say that we can do factorization, but while we will be doing the
factorization the co-efficient need not be real. Forget about the integer, but the co-
efficient what we will what we will be getting it may not be real, rather it may be even
complex. So depending on the coefficient of s square, here and s and their relative value,
we may get expression of the poles it will be complex. So in the next slide, we can do
you know, derivation of the location of the pole.
So if you yeah, so here we do have the expression of Af it is having in the numerator, we
do have Ao_f and Ao_f it is defined here . And then this part if you see based on this
co-efficient, we can write in this form.
However, this p′1 and p′2, they are they need not be real number. In fact, if you consider
the second order equation and then if you write the corresponding routes, what will be
finding is that the routes are or other location of the pole p′1 and p′2, it is
* √* ( )++.
1325
So this is one possible route. The other one it is same except this sign instead of ‒, it will
be +. So we can say that now based on the relative value of this p2, and (
). So based on their relative value, you may get this part either real or it may be
imaginary depending on the relative value of the +ve part and ‒ve part.
So, if I say that if p2 > ( ), then we can get this part it is real. On the other
hand if it is less, then this part it will be imaginary. And then what we will be getting is
that both p1 and p2, they are complex and incidentally, they are complex conjugate also.
So the real part it will be , in that case and then imaginary part it is ±. In fact for p1 and
p2, we do have + and ‒. And then the imaginary part, then we have to find what will be
the value here. So this condition it is finally, telling us that whether these 2 poles they are
really real poles remaining as real pole or they are becoming complex conjugate.
So depending on this value, as I said that the location of the pole of Af it will be
different. So the corresponding Bode plot if you try to sketch what you will be getting
here it is yeah.
So I, let me try to sketch the Bode plot of A, Af and maybe the loop gain also.
So let me start with A. So if I consider this A in dB and then if we plot against ω in log
scale again. So what we are expecting here it is we do have a pole here, p1 and then we
1326
do have the second pole here maybe, in the near vicinity of the anticipated pole p′1 which
is p1(1 + βAo).
So, this is A this is in dB scale and then β we do have I should not say β, rather loop gain
‒ of loop gain. So we do have loop gain, it is having the same poles namely, p1 and p2
same as A. So this is gain plot of the loop gain and then we do have the Af. So Af it is
above 0 d B.
So what we are expecting here, it is remaining there to the value here or rather if I
convert this into dB so that will be the level here, for Af in the low frequency region.
And then it is it is expected to be heating this A and we are expecting that there will be
sharp corner. Why is it sharp? Because it is from the flat line it is getting converted into ‒
40 dB/dec.
So as if it is having 2 combined poles are there. In fact this pole they are not really they
are real and in fact, they are imaginary. As a result in the Bode plot, because of the
imaginary rather, I should not say imaginary, it is complex pole rather complex
conjugate pole. And because of the complex conjugate poles in the gain what we can see
here it is it will be having a kind of overshoot kink kind of things.
So strictly speaking, this Af it will be having a kink now. So the overshoot of this kink it
is directly proportional or rather directly depends on the magnitude of the imaginary part
here and the real part here. So if the imaginary part it is getting higher and higher so then
we are expecting, this will be having higher kink.
On the other hand, if these 2 poles are distinct pole of course, then or rather if these 2
poles are real poles; namely, whatever we see here if it is also a real entity or if it is
higher than the remaining part here. Of course, this p′1 and p′2, they will be distinct real
poles and in that case, this overshoot it will not be there.
Now if I consider the corresponding phase, probably we can try to go to the phase plot
also yeah. So we can try to make a phase plot here, I am just retaining the gain plot. So
that I do not have to redraw it and so the phase plot for A it is having a step here and then
it is having another step here like this.
1327
But if I consider so, this is the phase plot of A and now if I consider phase plot of Af, it is
remaining here and then all of a sudden, it will get a short change of the phase starting
from 0° to ‒ 180°. So this is the phase of the feedback system transfer function. And
higher this overshoot, this phase roll-off it will be faster or rather rapid.
So based on the again relative position of this p1 and p2, this pole of Af it can be distinct
pole or it can be the 2 poles can be distinct real poles or they can be complex conjugate
pair. Now if I try to compare the location of poles for these 2 cases, case II-A and case
II-B, you can probably try to correlate the location of poles particularly for the forward
amplifier poles location and then probably the pole location of the feedback system.
So, in the next slide we are going to compare the location of poles. So we like to
compare location of poles for these two cases. So let me try to see here this A(s), the
forward amplifier circuit it is having 2 poles p1 and p2. So it is let me consider this case
first. So this is the A(s) plane, this is σ and this is jω and both p1 and p2, they are
representing left half plane poles.
So, this is a p1 and this is a p2, it is quite far apart. So let you consider p2 it is quite far
apart. Now if I consider the corresponding Af assuming that these 2 poles are really wide
apart and if I try to see their location of poles particularly p′1 and p′2.
1328
So, p′1 what we are expecting here it is it got shifted to higher frequency, p′1 and p′2 on
the other hand, it is almost remaining to this place, ok. So the blue colour indicates the
location of the pole of a and red colour indicates the location of the pole of Af. Now and
this is the situation for case II-A. Now let us consider case II-B.
So, we do have situation for case II-B and here again, this is the real part of the s and this
is the imaginary part of s and in this case, what we said is p1 it is say let me again use the
blue colour for A(s). So we do have p1 here, but then p2 it is quite close. So we do have
p2 here. In this case, what we are expecting is that this p′1, it may be in the near vicinity.
So this is p′1 and since it is very close to this p2, it will interfere with that and p2 will also
be changing and the corresponding p2 it will be coming in the near vicinity.
And if I further try to push this pole, this pole closer. So then what you are expecting is
that this p′1 and p′2, they will collide and then they will create complex conjugate pole
pair. So we can say that this is maybe p′1, it is having ‒ sign here. So, I am considering
this is p′1 and this is p′2. So, if we take this p1 and p2 closer and closer, then bifurcation of
this complex conjugate pole pair, it will be more. Note that p1 and p2, they are the real
part it is half of p2 alright half of p2.
While they are getting bifurcated as complex pole, the real part it is half of p2. So if I
take this second pole closer towards p1, then real part it is also getting changed and the
imaginary part on the other hand, it is overshooting. So however, of course, both p′1 and
p′2 both are remaining on the left half plane. As a result, these 2 poles since they are
remaining on the left half plane, the system Af or the feedback system remains stable.
But then since these poles are complex conjugate pole, they will be having very strange
behaviour in step response. So that part we will be talking later, but this is just to tell you
that yes the position of p1 and p2, the relative position of p1 and p2. They are very
important for a well-behaved feedback system. And in fact, we prefer this condition
rather than this condition. Now suppose, we do have a case where A is having only one
pole and suppose, the feedback network β is having another pole and then what it may
happen?
1329
Here what we have it is of course, again we are considering it is ‒ve feedback system in
DC condition. Then we are considering β is having a pole called pb and forward
amplifier it is having a pole called pa.
So the β and forward amplifier gain or transfer function both are having 1, 1 pole each.
So if I consider of course, the loop gain then this part βA it is having both these poles
appearing, right. But then if I consider Af, the feedback system of course, it will be
having 2 poles that is what we are anticipating, but also it will be having a 0. In fact, if
you if you write this here, the expression of A in the in the expression of Af. So, we have
in the numerator it is and in the denominator we do have .

( ) ( )( )
So, here we do have only one factor ( ) in that denominator part, but then in the
denominator, we do have these 2 parts. So if I take these 2 here we will be getting almost
the similar situation as we have worked in before, but this factor this factor it is
remaining it is remaining there. As a result, what we can get this Af, the constant part it is
of course, and in the denominator we do have the second order polynomial.
In addition to that, we do have one factor in the numerator that represents a 0. So these 2
depending on of course, the location of pa and pb what we have discussed for case II-A
and II-B they may create real poles or may be complex conjugate poles. In addition to
1330
that, we do have 0 here. So I can say that Af, it is having frequency independent part, it is
having this factor representing a 0 at pb and then it is having 2 poles called p′1 and p′2.
And p′1 and p′2 it is as I said that it is it can be obtained by the same method what we got
for case II-A and II-B. So I am not going to repeat that. So that part we can see here.
Now if I consider the Bode plot of Af and A and also the β you will be finding very some
similarities are there, but of course, it is having some differences also compared to the
previous case.
So let me try to sketch that for you. You know what? It may be the situation for a
situation where in case if this pole this pole it is dominant pole over this pa. So in the
next slide let me try to sketch that, yeah.
So here I do assume here I do assume that pb it is much smaller than pa and under this
condition, if I try to sketch the bode plot of say, A since it is A has only 1 pole since A
has only 1 pole, so it is having say Ao gain and then it is having pole pa, but because of
this condition, we are assuming that pa it is quite far and then we do have a this pole pa.
So this is pa on the other hand, if I consider β, β is having low frequency gain of βo. Say
like this and then it is having a pole called pb. So it is having a so this is β this is pb.
So if I combine this 2 to get the loop gain, what we can get here it is loop gain it is
having this pole pb and then after that it is continuing and then it is hitting this pa. This is
1331
having steeper slope here. So this is the loop gain. And now if I try to plot say Af you
will be finding very interesting information that Af it is approximately if I consider in the
low frequency region, it is approximately .
So it is continuing here and then it is having a 0 here. So because of this 0, it will

increase. So this is Af and then it is having a pole and then it is having the next pole. So
we can say that this pole it is p′1 = pb(1 + βoAo) and then it is having a 0 here which is
equal to pb. And then of course, it is having the other pole p′2 which is we can say that it
is well approximated by this pa.
So for Af what I said is that low frequency gain here it is approximately , then it is
having a 0 here, and then it is having a pole and then you do have another pole and so
and so. And of course beyond this point it is in fact, so in the sketch I do have it is not
very neat. In fact, this point and this point supposed to be almost close to each other. In
fact, it should have gone like this and then like this.
But anyway, so what I like to say that this Af it is having a additional 0. So depending on
the location of the pole of the feedback network, it may be having in the situation like
this. And as this p′1 and its expression is given here, if it is approaching to this p′2 or pa,
then they these 2 poles may get combined and it may creates the complex conjugate pole
pa.
Probably you can try to sketch the location of the poles for different cases; particularly,
when you consider both A and β they do have the pole. And if they are approaching each
other, what may be the situation? What may be the location of the 0 poles of this one,
you can try yourself and convince yourself that yes; Af it is having one 0 and 2 poles.
Now this is the case when we do have loop gain it is having 2 poles. It may have a
situation where loop gain may have 3 poles or even more than that. So suppose, if I
consider the next case, case-4 where A is having 3 poles, β may not be having a pole, ok.
1332
So in the next slide, we do have this situation where this A is having is having 3 poles
and if I consider p1 it is dominant pole. Not only it is dominant pole, even after if I
consider it is getting shifted by a factor of (1 + βAo) even in this case, if I assume that
this is less than p2 and p3, then what we can say that Af we can we can extrapolate our
previous analysis. That Af it is having low frequency gain defined by this equation .
And then it is having 3 poles namely p′1, p′2 and p′3. p′1 it is shifted version of p1 by a
factor of (1 + βAo). p′2 on the other hand, yeah so, p′2 and p3 they are approximately
remaining to the same position of p2 and p3 only p′1, it is getting shifted by this factor ok.
So that is how we can you can analyse a circuit. In fact if you consider its bode plot
probably you yourself can find what will happen. And of course, if this condition it is
getting violated namely, if these 2 are becoming comparable, then this 2 may be getting
mixed up and as a result then p1 and p′1 and p′2 they may be appearing as complex
conjugate pole.
And then also we do have the third pole. If the third pole it is also coming into a picture
then of course, then we will be having still 2 complex conjugate pole pair and one real
pole. And then all the 3 poles will be having the contribution to define the location of the
of the poles of the Af. So if I try to plot the gain for Af and A for this condition, probably
you yourself can find out, but let me help you to elaborate on that, ok.
1333
So if I try to make a sketch of it namely, if I try to make the gain and particularly gain
plot let me restrict the discussion here, we will be covering the phase plot later.
So what we said is that if I consider this is the condition. Namely, p1 it is dominating and
then p2 it is there, but p2 it is really far then maybe p3 also alright. So we do have p3 here
you do have p2 here and then we do have p1 here. So this is the plot of A and this is low
frequency gain on this A and we consider β it is independent of independent of
frequency, but then it is less than 1.
So the corresponding βAf, if I plot the loop gain. So this is the loop gain and it is having
the first pole and then it is having the second pole and then third pole and then if I plot
the feedback system transfer function namely, Af. So what we are expecting here it is, it
is having low frequency gain which is and it is continuing till it is hitting A.
And this is the point where it is hitting A and beyond this point, it will it is following A.
So we can say that it creates a pole here which is p′1. This is p′1 = p1(1 + βAo). And then
of course, the corresponding pole here and here they are remaining same. So we can say
that p′2 and here we do have p′3.
One important point, you we have simply missed it if you see this corner point and the
frequency at which the loop gain it is becoming crossing 0 dB level. So this is 0 dB level,
1334
they do have well you know coincidence. They are very close to each other which
indicate that if I consider Af which is .
In fact, if you see here in the low frequency situation where this part it is dominating. So
in low frequency, we can approximate this by . But if you go to higher frequency,
particularly beyond this frequency where this part it is less than 1, beyond that frequency
then this is this Af need to be approximated by A. So this frequency which is the UGF of
loop gain it is very vital point.
So later, we will say that this Af its behaviour or rather we can make a we can make 2
segments of Af over the frequency range, below this UGF and beyond that. So below the
UGF the feedback system gain, it is . On the other hand, if it is beyond this UGF, Af ≈
A. For ω > UGF and this is for ω < UGF.
In fact, importance of this UGF it will be discussed later in our in our stability analysis
system. Probably, that will be discussed in the next week. So let me wind up whatever
the discussion, we do have today. Primarily, change of frequency response of the
amplifier due to feedback connection.
1335
We have discussed about the location of poles of a feedback system. And it is their
dependencies on the location of pole of the forward amplifier and also the location of the
pole of the feedback network.
And what we have done is that we have considered 4 cases in fact where the loop gain it
is having only 1 pole, then loop gain it is having 2 poles, it is having 3 possible deviation
where A is having 2 poles and then A is having 1 pole and β is having 1 pole.
And then we have considered a situation where A is having 3 poles, ok. So, this gives
you fair idea that how the poles locations are getting changed. And what we have seen is
that the dominant pole p1, it is getting shifted. Dominant pole of the loop gain, it is
getting shifted to p1 in the form of p′1 which is p1(1 + βA).
And relative position of this p′1 and the second pole and third pole they are creating a
situation whether the shifted version poles are having clear radial value or are they
complex conjugate. I think that is all. In the next class, we will be talking about some
numerical examples.
Thank you.
1336
Prof. Pradip Mandal
Lecture – 97
Applications of Feedback in Amplifier Circuits (Part-A)
Dear participants, so, welcome back to our online certification course on Analog
Electronic Circuit. Myself Pradip Mandal from E and EC department of IIT Kharagpur.
Today’s topic of discussion it is Feedback it is rather continuation of feedback system.
And specifically we are going to talk about Application of Feedback circuit in amplifier.
So, on the amplifier may have transistor level circuit as well as op-amp based circuit.
According, to our overall flow we are in a week-10 and we are in module-9. And we
have discussed about basic four configurations feedback configurations and their
characteristic we also have discussed about effect of feedback on a frequency response of
an amplifier. And today’s discussion it is more like continuation of the basic four
configurations and specifically how those configurations can be deployed on practical
circuits. The practical circuit can be either transistor level the example. So, we will be
talking about is primarily BJT. And then also we will be talking about deployment of
feedback system on op-amp circuit.
So, we can say that we are at module levels as well as at subsystem levels.
1337
So, the concept, so, we are planning to cover today it is listed here. So, we shall see how
we can deploy or how do we decide different feedback configuration in BJT circuits BJT
amplifiers. And there we will be talking about specifically three different configurations,
which you will be giving us fair idea how to deploy the feedback configuration these are
the three possible configurations we are talking about of course, one more configuration
it is skipped due to the shortage of time.
So, we will be talking about voltage sampling and shunt feedback referred as shunt-shunt
feedback. And then current sampling and a series mixing referred as series-series
feedback and then the third one it is voltage series feedback or shunt-series feedback.
And then we shall also talk about a little bit extension of the basic feedback models,
which we need to, discuss before we go into the feedback circuit using op-amp. And for
feedback configuration around op-amp we do have different possible examples; namely
inverting amplifier, then integrator and differentiator and then, non inverting amplifier.
And then also we can discuss about a circuit which is having two feedback loops.
So, these are the enlisted items we do have for this lecture. So, to start with we let us
summarize whatever the things we have discussed in our basic four configurations.
1338
So, here we have four different configurations, so the names of those configurations are
given here; namely voltage-shunt, current-shunt, voltage-series and current-series or you
may say shunt-shunt, series-shunt and then shunt-series and series-series.
So, you may recall that now, depending on these configurations we also can say what
type of signals we do have at the input. And also we can see what type of signals we do
have at the output of the system. Here we do have the basic model of the feedback
system ‒ve feedback system. The input either we may call this is the primary input or
just by observing this input we can tell that what kind of amplifier we do have or rather
this the input type and the output signal type it will decide what kind of amplifier we do
have and that also decides that what kind of feedback we do have or feedback network
we do have.
Say for example, if we consider the first one it is the signal here it is current and signal
here it is voltage. So, the amplifier the forward amplifier it is essentially trans-impedance
amplifier or we can say that A is Zm. So, then of course, we know that once we are
deploying the ‒ve feedback system, according to this formula the main the forward
amplifier gain A it is getting reduced by this factor, which is referred as a desensitizing
factor (1 + βA). Where this β is the feedback factor here and A depending on the type of
signal it may vary from Zm then AI the current gain voltage gain and trans-conductance
Gm.
1339
So, whatever the configuration we do consider essentially this is the formula by which
we can say that A it is getting reduced. So, the arrow we are putting here indicating that
the feedback effect of the ‒ve feedback it is reducing this A by a factor desensitization
factor of the circuit. So, if I on the other hand, if I if I consider say this configuration
then the input is current output is also current and A is current gain. And once we have
the proper feedback connection, we are expecting that this current game it will get
reduced.
So, likewise if we consider the third configuration the voltage gain it will be getting
reduced, likewise the fourth one trans-conductance it will be getting reduced. So,
whatever the configuration we do have if based on that configuration once we know that
what is A and then we can say the corresponding A it is getting reduced by this factor.
And the factor here what is the basic purpose of reducing this A what you can say that if
I assume that βA it is much higher than 1.
Then we can approximate this Af feedback system gain Af = β, which means that the
system transfer function or primary input to primary output it can be decided by the
feedback network. So, if we want to stabilize the specific parameters say Zm then we
should be selecting the first configuration. On the other hand if we say wan to stabilize
say voltage gain. So, if we want to stabilize the voltage gain, then we should be selecting
the corresponding configuration here. So, then we can say that Av that corresponding Av
of the feedback system if I call Av_f. So, this Av_f it is getting converted into . And
again if I consider this is much higher than 1. So, this can be well approximated by .
So, the basic objective of having this ‒ve feedback system it is to stabilize this A whether
it is Zm, AI, Av or Gm. And it should be stabilized to a value which is defined by the
feedback network, which can be decided by a designer based on the requirement. So, for
every configuration while A is getting reduced the resistance input resistance and the
output resistance, on the other hand they may have a different changes. Say for example,
if I consider shunt-shunt configuration then input resistance it is expected to decrease by
the same desensitization factor and also the output resistance it is it is getting decreased
by the same factor.
1340
So, while we are trying to stabilize this Zm, you we should be aware that the
corresponding input and output resistance they are also getting decreased. So, there may
be different objective to follow this configuration or to get this configuration one of them
it is of course, to stabilize the Zm. The other objective on the other hand it can be
reducing the input resistance and or reducing the output resistance.
So, this combination; however, this combination is fixed reducing Zm and then reducing
Rin and Rout it is fixed. And if we are reassured that we are looking for this characteristic
then we can add the ‒ve feedback system in this shunt-shunt configuration. And so,
likewise if you if you are very clear that which parameter you liked to stabilize, namely
defined by the parameter or the feedback network based on that you can select the
corresponding circuit configuration. And also, you should be aware that what maybe its
corresponding consequences. And the consequences as I said that for this case both Rin
and Rout they are getting reduced.
On the other hand, for the second case for the second case the Rin it is getting reduced,
but then Rout it is getting increased. So, likewise if I consider the third case excuse me,
likewise if I consider the third case, we do have the third case here and for this third case
the input resistance it is getting increased and output resistance on the other hand it is
getting decreased.
So, likewise the final one the for series-series configuration feedback configuration both
Rin and Rout they are getting increased. So, this table this summary it is very handy and
this will be helping us to decide which configuration we are looking for to achieve some
requirement. Namely to change the input and our output resistance or probably either
current gain, voltage gain, trans-impedance or trans-conductance we like to stabilize
defined by the feedback network. And while we do have the A it is having different
possibilities, the corresponding feedback factor βFB we are calling this β as βFB to avoid
confusion with the β of BJT transistor.
So, if A it is say Zm the unit of βFB it is more. And on the other hand, if the A it is trans-
conductance or the unit of β if it is Ω. And on the other hand, if A is either current gain
or voltage gain then βFB it is unit less. So, now, we should also be aware that suppose if I
decide one specific configuration and we know that the corresponding changes are
1341
happening then we should also be aware that what will be its consequences namely what
will be the variations on the on the other parameter.
So, in the next slide we are also having one important table along with this table, which
tells us that what may be the corresponding consequences on the other parameter.
So, here we do have the same table, which will be helping us to decide basic
configuration. And then, we do have the other table here which it will be helping us to
understand that what may be the consequences on the other parameter. So, say for
instance if I consider this configuration and I know that Zm got reduced by the
desensitization factor like this (1 + βA) or whatever you say βFBA. And Rin also is getting
reduced by the same factor same thing for the Rout.
Now, suppose we like to know what maybe what kind of changes are happening on the
other parameter; namely current gain, voltage gain or trans-conductance for this
configuration. Then we need to know that how do we express those parameters in terms
of this Zm and Rin and Rout. Here we do have a table which is representing the other
parameters say current gain in terms of Zm and Rin and Rout.
So, if I if I see this this column that gives an indication that the current gain of this circuit
this configuration which is . So, we can say that this is indicating that current gain of
1342
the circuit AI = . And this table suggests that both Zm as well as this Rout they are
getting reduced by the same factor. So, we can say that this AI the current gain will not
be having any change. So, we can say that it will be having no change.
Now, we can also work out on the other parameter say for example, if I consider the
voltage gain. And the voltage gain its expression it can be given by this factor multiplied
by Zm. So, we can say that this Av = . And again both the Zm and Rin are getting
reduced by the same factor desensitization factor and as a result here also there will not
be any change. So, I should say here also we do not have any change.
On the other hand, if I consider say trans-conductance. So, the trans-conductance of the
circuit under this configuration we can say that it can be expressed by in terms of Zm and
Rin and Rout by this or we can say that trans conductance of the circuit Gm = . And
as this table suggests that both Rin and Rout are getting reduced by the same factor and of
course, Zm is also getting reduced, but since we in the denominator we do have two
factors.
So, we can say that the net effect here the denominator is getting reduced; that means, it
is getting increased by the desensitization factor. So, I should say that by looking into by
combining this table and combining this table we can also see the changes in the other
parameter by considering the corresponding parameter here. Now, let you consider other
example say let me clear it. Let you consider say the circuit in this configuration voltage-
series or shunt-series configuration, which indicates that Av it is getting stabilized or
reduced by the desensitization factor.
1343
So, we can say that this A it is Av and appropriately you have to see what is the
corresponding β of course, it will be unitless and this is also Av. And we suggest that
after having the ‒ve feedback configuration the system gain voltage gain it will be
reduced by this factor. And while we are making this configuration as this table also
suggests that the input resistance is getting increased by the desensitization factor. And
the output resistance on the other hand it is getting decreased by that factor.
So, we are clear that this configuration it is having impact on voltage gain input
resistance and output resistance. So, we can say that Av we know for this configuration
now we like to know what will be its effect on the current gain. So, to look at the effect
on the current gain now, we will see this column which represents that the expression of
all the parameters in terms of Av and input resistance and output resistance.
So, if I see the current gain which is Av . Let me, write here AI = Av . And as this
table suggests that Av it is getting reduced Rin on the other hand it is getting increased
and Rout on the other hand it is getting decreased. So, in effect this AI it is getting
increased by this factor desensitization factor because this decrease and this increase they
are getting canceled we do have the denominator is getting reduced and hence the net
effect it is the AI it is getting increased.
1344
So, I should say that before we make the feedback connection whatever AI we are having
that AI after making the feedback connection is getting increased by this desensitization
factor. So, likewise if I consider say Gm. So, if I consider Gm here for this configuration
and the Gm it is its expression in terms of Av it is given here. Gm = and as this table
suggests that both Av and Rout are getting decreased and hence this Gm it is not having
any change.
So, G m remains unchanged. And then if you look into the trans-impedance Zm. So, if
you look into Zm. So, Zm it is AvRin. And this Av it is getting decreased and Rin it is
getting increased. So, again here also this Zm is not having any change. So, both Gm and
Zm are not having any changes, but the AI it is getting increased and Av of course, it is
getting decreased.
So, like that you can look into the other configurations namely series-shunt and maybe
series-series and you can see what kind of changes is happening in the main parameters.
And what kind of corresponding effect it is falling on the other parameters by looking
into either the first column for the series-shunt connection or for series-series connection
you can look into say third column to see what kind of changes are happening in other
parameter.
So, I think this summary table it is very useful to deploy the feedback configuration and
deciding what configuration you are looking for to achieve some objective and also it
will it is giving us the information about the changes or consequences on the other
parameter. Now, let us look into more towards the actual circuit then.
1345
So, what we will be looking for it is. In fact, let me also summarize some other aspect
namely. So, we do have the table we do have table, which gives us the information about
how to select the configuration after that what you do?
So, rather what maybe the overall procedure to incorporate feedback loop in an
amplifier. So, here we do have the list of the activities we have to do first thing is that we
have to select the right circuit configuration. And also we need to be aware about the
consequences what are the changes are happening, not only in input and output
resistances, but also in other parameter such as transconductance or voltage gain and so
and so.
And the third one is very important that, if we consider the practical application. And if
you really want to make use of this feedback connection to create some effect. And if
you really want to know what is the effect and intuitively if you want to calculate what is
the corresponding changes, then definitely we need to have a fair understanding of a
suitable range of the parameters or rather feedback resistance or feedback network.
So, here we do have some guidelines which helps us to make the loop really effective
according to this formula also we can intuitively say that what kind of changes are
happening. So, what are the guidelines we do have? The first thing is that whenever we
are considering say this feedback system model we assume that in case if there is any
load and the effect of the load it has been considered in A which means that we need to
1346
consider A′ instead of A or at least we make sure that the effect of the external load it has
been taken care if it is possible, to do so.
And then next important thing is that we need to find the meaningful feedback network
or other feedback factor βFB. So, that the loading effect of this feedback network on A.
And loading effect of the mixer circuit on feedback network you can say it is it can be
ignorable. Or we can say that this A′′ it should be approximately equal to A′ is the load
external load effected gain. And also the β′FB should be approximately equal to βFB. And
if we follow this follow this appropriate range of βFB to satisfy these two conditions then
you can intuitively say that what kind of changes it is going to happen in the circuit.
Now, in case if you if these two approximations are still not valid, then also the circuit it
will be working, but whatever the simplified expression whatever the equation it is
giving us in intuition that what kind of changes it will happen that may not be really
effective. And they are maybe a significant amount of deviation from the simplified
theory the apart from this two approximation we also need to say that βA or we can say
that A′βFB if it is much higher than 1, then only we can say that this is approximately .
And then only you can say that the feedback system characteristic it is solely or
predominantly defined by the feedback networks parameter.
So, to achieve this property namely the Af solely defined by the feedback network we
need to have meaningful selection of this βFB. And then only whatever the changes we
are we have summarized in this table, namely increase or decrease of the resistances
defined by this desensitization factor it is directly applicable.
But of course, even if you are not satisfying these conditions then also the Rin and Rout
will increase or decrease the according to this table for this different configuration. Only
thing is that their increase and decrease may not be defined by this same desensitization
factor, we have to consider the corresponding deviation to get the more accurates change
in the input and output resistance and also the change in A.
So, for practical circuit as I said it is better to have a meaningful range of on this βFB. So,
in the next slide let me discuss about what is the guidelines to really get a range of βFB
rather going little detail of whatever the guidelines we are discussing now.
1347
So, yeah so, to make the loop really effective and intuitive, first thing is that let you
consider the loading effect on A. So, we should say that instead of A, it is better to
consider A′ after considering the external load effect.
So, in case if you have external load RL and if you consider that RL on the circuit. Then
we can get load effected A and then we can proceed further. Namely we can try to
calculate what may be the Af in terms of this .
Now, next thing is that we need to find the suitable range of the βFB of course, based on
the nature of AβFB it is complimentary in nature. So, that this product it becomes unitless
rather you may say that loop gain ‒ of loop gain it becomes unitless. And that is once
you once you know that what maybe the nature of this βFB next thing is that what the
meaningful value of it is.
And to get that to get a suitable range we do have two things to satisfy as just now I was
talking about. A′′ it is approximately A′. And what is A′′? It is the loading effect of the
input resistance of the feedback network say Rin_β, if it is much higher than the Rout of the
amplifier particularly for voltage sampling then we can say that this A′′ ≈ A′.
So, if I if I ensure that this condition is getting satisfied, then you can say that loading
effect of the feedback network on the forward amplifier it can be ignored. So, pictorially
you may say that suppose this is the amplifier and it is having Rout and suppose we are
1348
making a voltage sampling, which means it is a parallel connection and we do have the
input resistance of the feedback network which is Rin_β. And so, this Rin_β if this Rin_β it is
a much higher than this resistance then you can say that the loading effect on the
amplifier or this output voltage hardly changes even if I consider this Rin_β.
So, this is specifically true for voltage sampling and of course, for current sampling the
condition it will be the other way. On the other hand if I consider the input resistance of
the amplifier Rin and then, we do have say current mixing. So, if we have a current
mixing here. So, this is shunt configuration and then we do have Rout_β. So, if I consider
this shunt mixing or current mixing then if we satisfy this condition.
If I say that this Rout_β it is much higher than this input resistance here. Then we can say
that the loading effect on the feedback network from the input resistance of the amplifier
it is ignorable. And hence, if I satisfy this condition then we can say that this β′FB ≈ βFB.
So, this is giving us a good range of or it is helping us to define what may be the suitable
value of Rin of the feedback network Rin_β and Rout_β. And then also if you consider that
this equation, if it is giving us giving us the expression of Af in terms of βFB to get this
we want this part should be much higher than 1. So, we can say that A′βFB it should be
much higher than 1 and this gives us the βFB it is much higher than .
So, this two condition here along with this condition, it will be helping us to find what is
the suitable range of for the feedback network circuit components and that will be
helping us to get very effective feedback connection. I think this will be very clear once
you consider one practical circuit. Probably, I do have the practical circuit in the next
slide yeah.
1349
So, here we do have one application circuit shown here, which is a common emitter
amplifier. So, we do have common emitter amplifier. In fact, this is fixed by us common
emitter amplifier. And we will be talking about its feedback connection and our main
target it is that we want a stable Zm defined by the feedback network. So, this is our main
objective. And then we will be discussing how to decide the configuration and then how
to select the component value; but before that let me take a short break and then I will
come back.
1350
Prof. Pradip Mandal
Lecture – 98
Applications of Feedback in Amplifier Circuits (Part-B)
Welcome back after short the break. So, what we are talking about the common emitter
amplifier and what we are looking for is that Zm trans-impendence of the amplifier we
like to stabilize define, it should be defined by the feedback network element. So, as this
table suggest that if we are looking for this Zm to be stabilized by the ‒ve feedback then
A should be Zm.
So, this is the configuration we have to use, where we need to sample the signal in the
voltage form. And we have to mix the signal at the input in the shunt configuration or we
can see that the currents fall or we can say it is shunt-shunt configuration. And so, that
based on this table and the requirement, the feedback configuration it is voltage-shunt or
shunt-shunt feedback configuration. And this is the corresponding model of the
configuration, where this is the amplifier forward amplifier and this is the feedback
network.
And here we do have the sampling of the output voltage and here we do have the mixing
of the primary input and the feedback current to get the input current for the amplifier.
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So, we can say that in this circuit input signal it is current and the output signal it is
voltage. So, the forward amplifier it is its gain it is Zm.
So, its it is unit it is Ω and then the unit of the feedback networks transfer function βFB it
is a ℧. And the input now, next thing is that we need to find what is the corresponding
input resistance and output resistance of the actual circuit. Namely, if I consider this
circuit what is the corresponding input resistance and the output resistance of the circuit.
So, in the next slide what we can do? First of all we have to sample this voltage and then
we have to make a connection here, probably we can make a make a bridging element
from output to input. And this unit supposed to sends this voltage here at the output and
it supposed to produce the current at the input port.
So, here we do have the common emitter amplifier along with its feedback arrangement
and we are also adding one capacitor. So, that the DC operating point of the common
amplifier it is not getting disturbed by presence of this Rf. So, this Rf it is sensing a
voltage here and it is providing a current here.
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So, if you consider the idealistic situation, then if I say that if this point if it is connected
to say ground the current flow here it is vo if I call this is . So, that is the feedback
current. So, if = . So, from that we can see that this if = . So, from that we can say that
βFB = . So, if there is no load at this output port of the feedback network namely if I
connect 0 resistance to ground, then whatever the current we are getting that is the if and
that gives us the and using this equation we are getting the βFB which is unloaded.
So, we can say a βFB of this feedback network it is ; in this circuit of course, primary
input it is is note that this resistance here bias resistance RB it is quite high compared to
the other circuit. So, we may ignore this resistance for our linearized analysis or AC
analysis and then of course, we have to consider this is AC ground and the output node
here which is the collector terminal. So, this is the collector node and then we do have
the emitter node here. So, that is this node is the emitter node. So, let me use this point
here which is of course, connected to ground.
So, this is of course, it is connected to the actual ground. On the other hand at the base
this base terminal it is the input terminal. So, this is the base terminal and the ‒ve side of
the input port it is connected to the ground. So, this is the corresponding emitter terminal
or the ‒ve side of the input port or ‒ve terminal of the input port. And this emitter it is
connected to again ground and the register Rf it is connected between the collector and
1353
the base through this capacitor and for signal we can assume that this capacitor it is
working as a short.
So, we can see that this Rf it is bridging this collector terminal and the base terminal for
the signal. So, that is how this Rf it is shown here in this equivalent circuit. Now, base to
emitter we do have rπ. And then collector to emitter what we have it is we do have
internal voltage internal signal voltage, which is βroiin. In fact, this voltage we need to
write in terms of the input signal which is current; because our main focus is to define
this circuit rather Zm.
So, originally or most of the time what we use the internal circuit it is not an equivalent
circuit where we do have the internal current source which is β(ib or iin) in parallel with ro
which is the conductance here.
Now, this ib it is same as iin. So, probably you can write this is iin and this circuit not only
equivalent circuit we are writing here in this form which is Thevenin equivalent. So, in
summary we can say that the internally developed voltage here it is βroiin of course, this
polarity of this current +ve current is from collector to emitter. So, that is why we do
have ‒ sign here and + sign here and this ro it is directly providing the Thevenin
equivalent resistance.
So, in summary this is the small signal equivalent circuit of the amplifier; considering a
Rf in to the picture and of course, ignoring the base bias resistance. And at the input we
do have expecting the signal should be current. So, this is the corresponding input
stimulus ideal stimulus is. So, in the feedback circuit the primary input Ss it is there is is.
And on the other hand output it is the voltage here vo. So, we can see that vo is the
corresponding voltage. Also we can see that this RC it is connected between collector and
Vdd. And Vdd it is AC ground. So, this RC you can connect from collector to the AC
ground which is also for AC model you can or AC or small signal equivalent circuit we
can see that this is also connected to ground.
So, that is how we can see that the transistor level circuit it is getting translated into the
desired model and the model it is it consists of the different elements that the feedback
network work as well as the main amplifier. So, let me clear up the diagram here again.
So, what we have here it is output to input this Rf it is working as feedback network.
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So, we can say that βFB it is input resistance of the circuit it is rπ and output resistance
in this case it is ro which is also getting loaded with RC and typically this RC << ro.
So, it is better to internalize this RC with this amplifier. So, once you modify this circuit
or rather once you take this load within this, then the internal voltage it need to be
changed in this form where you can see that the voltage available here it is. Once we
have the RC the corresponding voltage vo it is equal to internal voltage βroiin × or
you can say that β(ro ⫽ RC)iin.
So, this whole circuit can be represented by Thevenin equivalent voltage source, where
the voltage it is the Thevenin equivalent voltage is given here and the Thevenin
equivalent resistance Rth is ro ⫽ RC. So, the whole circuit it is getting reflected here in
this form. So, the RC it has been consumed now the circuit it is unloaded. So, with this
modification you may say that this Rout instead of ro it is ro ⫽ RC. And in this model the
corresponding A which is of course, this this is Zm in this model it was βro.
But once we take this RC within the circuit, then the corresponding Zm or we can say that
Z′m = β(ro⫽RC). So, that is the A the forward amplifier gain considering the load the
other things of course, it is as I said that the output resistance got changed. So, either you
may say this is R′out which is (ro ⫽ RC). And this can be well approximated by RC for all
practical purposes likewise this also can be well approximated by βRC.
1355
And then if you look into the feedback network. And if you try to see what is the
corresponding input resistance here of the feedback network what we say it is Rin_β. If I
consider the other side it is not loaded; that means, it is shunted to ground then it is equal
to Rf. Likewise, if I consider the output port and if I say that the output resistance of the
feedback network Rout_β that is which is given by a good voltage source.
So, if it is if I consider it is a good voltage source then it is in ideal condition this is also
Rf. So, along with the input resistance of the forward amplifier and output resistance of
the forward amplifier, we also have input resistance of the feedback network which is
equal to Rf. In fact, Rout_β it is also Rf.
So, with this setup information we are now in position to make use of the equation
particularly what will be the feedback system trans-impedance Zm_f. But then we have to
consider that once you have this Rin_β connected here we should consider its loading
effect on the circuit it is negligible. So, likewise the loading effect of this input resistance
here on the feedback network should also be considered as negligible.
So, that gives us an idea that what may be the meaningful range of this Rf or what maybe
the meaningful range of this βFB. That is very vital to construct a practical feedback
circuit where we can directly use the equation to find what are the changes are happening
namely what is the value of the Zm_f and what is the value of Rin and Rout ok.
1356
So far what I said is Zm it was βro, but more important thing is that Z′m ≈ βRC and R′out it
is RC, Rin it is rπ, βFB it is . And then next thing as I said that we need to find what is the
suitable range of this Rf. And to get that since we are sensing the signal here the voltage.
So, one condition it is that Rin_β it should be much higher than Rout here or R′out. Likewise
to avoid the loading effect here or to ignore the loading effect here the Rout_β it is it
should be much higher than Rin. And Rin it is rπ and R′out it is RC; which gives us that Rf
should be much higher than rπ and this also RC ok.
And whenever do we say it is much higher than this, all practical purposes what we can
do we can see that Rf ≥ 10rπ or 10RC. So, that gives us the lower limit of Rf; on the other
hand if I consider the other condition namely A′βFB should be much higher than 1. And
A′ it is βRC.
So, we can say that βRC and βFB on the other hand it is it is we want this should be
much higher than 1 or we can say that Rf it is much lower than βRC.
So, if I combined say this lower limit and upper limit of Rf to really make this feedback
system effective we can get a suitable range of Rf. And once you get that and once you
make sure that both these conditions were satisfying then we can say Zm_f = .
And that can be well approximated by considering by ignoring this 1 with respect to this.
So, we can say this is approximately = . So, it is giving us Rf.
So, Zm_f = Rf. So, we can see that in this circuit Zm of the feedback system = Rf; which
means that Zm_f equals to all practical purposes equal to Rf. And the input resistance on
the other hand as you can anticipate that input resistance it is getting reduced because of
the shunt connection.
So, we can see this is equal to rπ original Rin getting reduced by (1 + βFBZ′m). In fact, this
is also coming in parallel with Rf, but if you see this part first. So, this is rπ divided by if I
say that this part it is dominating over 1. So, we do have βFB it is and then we do have
βRC. So, that is equal to so, rπ here and within the β we do have Gm and rπ so, that rπ you
1357
can cancel. So, this is coming . So, the initial resistance here it was rπ now that is
becoming .
On the other hand, if I consider the output resistance. So, let me use this space here and
use a different colour. So, this resistance it is an output resistance it is RC and so that is
the and it is expression it is β . So, this is it can be well approximated by .
So, both Rin and Rout they are getting reduced by the same factor. And so, in this circuit
we can see that output resistance it is even after considering this RC within the circuit it is
and input resistance here it is of course, we have ignored this resistance and that
should not be a problem because the typical value here it is much smaller than this RB.
In fact, RB it is much higher than rπ itself and this feedback resistance it is a reduced
version of this input resistance. So, naturally it should not be having any problem. So,
now, next thing that lets also look into the consequences on the other parameter. So, here
what we said is Zm it is getting defined this Zm rather Zm it is changing from βRC to this
Rf. And we like to see what other changes are also happening on the other parameter
namely voltage gain and then current gain and then trans-conductance ok.
So, in the next slide again we will be using the overall consolidated table to check what
are the changes are happening there in other parameter yes.
1358
So, this ‒ve the feedback system here it is of course, we are expecting that there will be
changes on the other parameter, but if you see the configuration here we do have this
configuration where the main parameter it is Zm. And so, we already have seen what kind
of changes are happening in Zm. And we like to see what are the changes happening in
the other parameter and to get the information we need to see this column.
So, as I said that this circuit it is having the current gain AI. AI if I consider this equation
it is giving us an expression AI = . So, since this AI it is having an expression of
whether their load affected or not both of them are getting reduced this as well as this by
the same desensitization factor and hence no changes. So, likewise if I consider the
voltage gain which can be obtained from this entity; namely voltage gain it is .
So, this is equal to and both Zm and Rin are dropping by the same factor and hence no
changes. On the other hand, if you see the trans-conductance Gm and if you look into this
entity. So, that gives us Gm = and both Rin and Rout getting reduced by the same factor
Zm also getting reduced by the same factor.
So, we are expecting that this whole entity it is getting increased by desensitization factor
D which means that Gm_f it is getting increased this is getting increased by (1 + βFBZ′m).
And for this circuit this Gm it is gm of the transistor and this entity we already have
discussed. So, that is we can say it is much higher than 1 and it is expression it is βRC
and βFB it is . So, that gives us Gm_f = gm× .
So, this is the quantity it is saying that gm it is getting increased by this factor with
respect to its original value or gm. Now, let us look into a numerical example associated
with this application circuit to get a feel of the value of different term parameters or
particularly how to get the value of this you know Rf.
1359
So, in the next slide we do have the same example having a specific value of different
bias elements as well as the device parameters. So, in this circuit the value of this RC it is
given here it is 5 kΩ, RB it is 940 kΩ and supply voltage it is 10 V.
And let you consider VBE(on) ≈ 0.6 V; early voltage of the device it is let say it is 100 V, β
of the transistor current gain it is a 100. Now, with this information quickly we can say
that the DC current here it is 10 µA and the β is a 100. So, we can say that the collector
current it is 1 mA. And so, that gives us the rπ and gm and so and so. So, we can see that
rπ the input resistance rπ here it is . And the gm it is = ℧.
So, rπ = 2.6 kΩ. So, that is the input resistance of the main circuit the output resistance if
I consider load affected. So, that is and in fact, with this value of early voltage we can
say that ro intrinsic output resistance it is = 100 kΩ.
And R′out = ro ⫽ RC and RC it is 5 kΩ. So, we can say that 5 kΩ it is dominating. So, we
do have the input resistance we do have the output resistance and also the Zm or other let
us let you consider directly Z′m it is βRC = 100 × 5 kΩ = 500 kΩ.
Now, using this information let us try to see what is the suitable range of this βFB or a
suitable range of Rf. So, first thing is that a Rf which is also equals to Rin_β and Rout_β and
by considering the situation such that the loading effect of the Rin_β on the amplifier if we
have to ignore it then you can see that the Rin_β it should be much higher much higher
1360
than output resistance R′out. So, that is equal to R′out = RC and this is of course, Rf on the
other hand the other condition it is Rout_β is much higher than input resistance rπ. So,
combining these two we can see that and this is also Rf.
So, Rf should be higher than much higher than rπ which is 2.6 kΩ and also it should be
higher than much higher than this R′out which is 5 kΩ. Now, if I say that these two are
and in fact, this is defining the lower limit on the other hand if I consider βFBZ′m >> 1
which is giving us >> 1. So, this is giving us that Rf should be much smaller than
500 kΩ.
So, by combining these two limits the upper limit and the lower limit. So, we do have the
upper limit and the lower limit we can see that Rf it is having a meaningful range and its
lower limit it is 5 kΩ and upper limit it is 500 kΩ. And let you consider one example and
so, we can consider from say Rf = say 50 kΩ which is definitely helping us to satisfy
both upper and lower limit.
And if I consider Rf = 50 kΩ then βFBZ′m it is we do have Z′m it is 500 kΩ and βFB is

. So, βFBZ′m = 10 we can say that this is much higher than 1.
So, we are satisfying this condition and then we can say that desensitization factor
actually it is to be more precise it is 11 or rather we can say that this is 10. So, we can
say that Zm_f it is ≈ = 50 kΩ which is same as the value of this Rf. And the input
resistance on the other hand it is of the feedback system which is so, either you can
consider D = 11 or D ≈ 10.
So, we can see if I consider D ≈ 10. So, Rin_f becomes 0.26 kΩ or you may say 260 Ω;
the output resistance on the other hand it is = . So, that gives us a value of 500 Ω.
So, in summary what we can say that if we put this to resistance Rf = 50 kΩ. So, that
gives us the output resistance here which is 500 Ω, input resistance to this circuit it is
260 Ω, of course these are approximation. In fact, they are even lower than that which
means that the input and output resistance it is getting decreased by this shunt-shunt
configuration.
1361
And Zm we said it is getting decreased and the Zm = 50 kΩ. Now, you can find what will
be its effect on Av and voltage gain and current gain by considering that consolidated
table and also Zm. So, we already have discussed that this will not be having any change
this will be having a change and that gets increased by a factor of D which is
approximately 10. So, this gm it will get increased by 10 and then voltage gain and
current gain approximately remaining unchanged.
So, that is about the numerical examples to say that by connecting this feedback circuit
what kind of changes we do have.
So, likewise we can go for other examples. So, here we do have another circuit which is
again common emitter amplifier, but here the objective is it is different namely we want
a stable gm. And in case if you are looking for stable Gm and then the corresponding
configuration here as this table suggests that it should be current sensing and series
mixing or we can say series-series configuration. So, we will be discussing this one in
the probably in the next lecture. So, let we break here and then we will continue this
topic of discussion.
Thank you.
1362
Prof. Pradip Mandal
Lecture – 99
Applications of Feedback in Amplifier Circuits (Part-C)
Welcome back after the break into our Analog Electronic Circuits NPTEL course. So, we
are talking about Application of Feedback Circuit and in the circuit-1 we have seen
voltage shunt feedback and now we do have the second example and we do have the
circuit given here.
So, the main circuit it is given here and the along with this we do have an intention to get
Gm trans-conductance of the circuit defined by feedback network. So, if I consider this
Gm, if we see the Gm in this summary table of feedback effect, what we can see here it is
suggests that we need to have current-series feedback or series-series feedback. And for
series-series feedback, what we have the input signal, it is voltage and the output signal it
is current.
So, we can say that input signal it is voltage and then output signal it is current and then
forward amplifier gain it is trans-conductance amplifier. So, I should say A = Gm and the
transfer function of the feedback network βFB which converts the output signal into input
signal of voltage which means that it is unit it is Ω.
1363
So, here also from the table we can see that unit of the feedback network it is Ω and what
we can say that while we are making this circuit, it is anticipated that the input resistance
it will increase and also the output resistance it will increase. And here we do have the
model of the on a feedback circuit where we can see that at the sampling point we do
have series connection and the mixing point also we do have the voltage mixing in
series. And this is the primary input and the primary output here it is the current through
the circuit which is we may call it is io.
Now, while we do have the main amplifier where RB it is the providing the base bias
arrangement and then the resistor here at the emitter. So, this is RE and then we do have
the collector resistors RC along with the supply voltage and here we do have the
provision of the feeding the signal, but we like to keep the signal of course, it will be in
voltage, but then while we are feeding the signal it should be through coupling capacitor.
So, the DC operating point of the amplifier should not get disturbed by the DC voltage at
the input.
And while we will be observing the output, output it is as I said that it is in the form of
current. So, to get a current here what we can say it is we can connect a capacitor to
ground and then we can see how much the current it is flowing through this circuit which
is referred as io. Now while we are planning for current series feedback so, we want this
io should be flowing through a resistor and that resistor supposed to develop a voltage
and that voltage it should be coming to the input port along with the main source here vs.
So, if you look into this model given here, the developed vf voltage which is equal to the
output current. In fact, io it is same as ix while it is flowing through this feedback network
it is developing a voltage here and that voltage need to be mixed here.
So, if I correlate the input port of the model here we do have +ve side. So, this is the +ve
side here of the input voltage, ‒ve side we do have at the emitter. So, we do have the ‒ve
side and then we do have the voltage coming here with respect to the ‒ve terminal of the
source voltage; which means that we like to give a signal here with respect to this
ground.
So, we like to have a signal here. So, what we can do? This emitter resistor total emitter
resistor you can split into two elements; so, one is RE1 and then rest of the things it is
here which is RE ‒ RE1 and then instead of connecting this CE bypass capacitor at the
1364
emitter we can connect it here. So, instead of connecting the CE here you can connect at
the middle of this resistor keeping RE1 and bypassed and then rest of the things which is
RE ‒ RE1 bypassed.
So, for small signal model we can say that this unbypassed resistor, it is developing a
signal voltage across it while the io current it is flowing through collector to emitter and
eventually it is flowing through RE also. So, the developed voltage here let me use
different colour here. So, the developed voltage here you may call it is vf.
So, this is the vf voltage we may say that this is + side and this is ‒ side. So, this vf it is
getting mixed with vs to produce the input voltage vin here. So, let me clear and then
again summarize it.
So, what we said is we do have primary input signal here, we call it is vs and then the
voltage getting developed here across this RE1 called vf particularly if we connect the
bypass capacitor here instead of this node and of course, this will be AC ground and. So,
this is the vf part and then from base to a emitter we do have the input voltage vin.
Eventually this is vbe of the transistor, but here in terms of a model we can say that this is
input voltage going to the amplifier. So, this vs and vf it is developing the or generating
the vin or preparing this vin for the amplifier to get the signal.
1365
So, to implement the corresponding feedback here the series-series feedback here what
we have to simply do it is that you have to partially bypassed this RE only RE1 it will
rather only RE ‒ RE1 it will be bypassed and RE1 it will be working as feedback a
network. So, in in a next slide, we will continue with this circuit and then we will go for
the corresponding analysis.
So, here we do have the circuit given we do have the circuit given here and what we have
as I said that out of this total RE this part it is getting bypassed by CE and the remaining
portion this RE1 it is working as feedback element developing a voltage vf and of course,
we are going to feed the signal here vs and this is the voltage we can say this is the input
voltage going to the circuit.
So, this is the corresponding model of this circuit and as you can see it is having series
sampling and then series mixing circuit and then also we do have the amplifier circuit
here and it is parameters are given in terms of a small signal parameter of the transistor.
So, let me explain that how we obtain this model.
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So, if I consider this transistor and if I draw the small signal model, what we have it is
gmvbe and this vbe it is eventually vin. So, this is vin along with that we do have the resistor
ro and this is the output node, the collector node it is the output node. So, we can see that
this node it is collector which is eventually the +ve side of the output port.
And then we do have the RC the bias resistor RC it is connected to DC voltage which is
for signal wise it is AC ground. So, the other end of the RC it is connected here which is,
we should say it is ground and. So, this not an equivalent circuit it is given here gmvin is
the current source voltage dependent current source and ro is the resistance inherent
resistance of the transistor and then from base to emitter.
So, base to emitter we do have rπ here. So, this is base terminal and this is emitter
terminal this is of course, this is emitter terminal if I look into the device so in fact, this
node and this node they are same and at the emitter terminal we do have RE1 and through
which the current is flowing. So, from emitter to ground or this AC ground here so, this
AC ground node it is shown here. So, for small signal this is ground, this is also ground.
So, this is the ground or the signal source or ‒ve terminal of the signal source.
So, we do have this ground, this ground and this ground, they are a shown here. Now this
the RE1 it is as I said that it is generating a voltage which we call it is vf. So, the output
current it is flowing. So, let me use different colour here to miss show you the flow of
the current.
1367
So, the current it is essentially flowing through this circuit and that current is flowing
here and this is ground and again it is going back. So, we can see that in the model we
can see that the flow of the current it is in this direction. And the voltage drop across this
one it is vf it is getting mixed with vs to develop this vin. So, now, I think we can fairly
correlate the actual circuit and the corresponding feedback circuit a model or the model
of the specific configuration.
Now the primary input in this case Ss is vs here and So in this model it is output current io
and the A the circuit gain it is basically in this case it is Gm. And Gm if you see it is
eventually this is same as gm of the transistor trans-conductance of the transistor. Ideally,
we want this port should be unloaded and since the signal here it is current, it supposed
to be theoretically should be short. In fact, here also we need to be having a short, but we
do have practically we do have RC and RE1.
So, now, if you if you see the output internal resistance ro it is much higher than RC and
this RE together. So, as a result you can all practical purposes if the internal resistance is
ro you may say that the circuit is really not getting loaded. In other words if I consider the
loading effect and if I say that what may be the expression of G′m; that means, what may
be the current here in terms of vin to get the corresponding G′m it can be easily shown that
this is the inherent gm multiplied by the factor which is coming due to the current
bifurcation.
And this current bifurcation is expression of the attenuation factor due to the current
bifurcation it can be expressed in terms of ok. So, assuming that this input
resistance we are not considering, but once you consider that resistance of course, that
resistance it will come in parallel with RE1 also. But, anyway this resistance it is much
higher than rest of the things. So, you can approximate this by again gm.
So, in summary we can say that G′m it is also it can be well approximated by gm. Input
resistance of the circuit it is of course, rπ of the transistor and then Rout of the circuit main
amplifier it is ro. And then, what is the feedback factor? It converts the signal the current
signal into voltage it is it is equal to RE1, the unbypassed part of the RE. So, with this
information now we can go for finding appropriate value or range of this RE1. So, that
probably we can intuitively explain the effectiveness of the feedback circuit.
1368
So, in the next slide, we are going to see what may be the guidelines to find the range of
this RE1 or rather the portion of RE which need to be unbypassed show that the feedback
configuration it is really working as a series-series feedback and it is formula can be
utilized.
So, in the next slide we are going to discuss about the range. So, quickly we can say that
this Gm it was gm of the transistor. In fact, G′m also we said it is well approximated by gm
of the transistor and Rin it is rπ, Rout it is ro. And of course, βFB it is RE1. Now to find the
suitable range of RE1, we need to consider this three conditions which gives us that the
magnitude of the loop gain it is much higher than 1 and then here the loading effect of
the input resistance of the feedback network, output resistance of the feedback network
we can compare with input resistance of the circuit and on the to avoid the loading effect
of the input resistance on the feedback network.
On the other hand if I consider this condition it is it is suggesting that if you follow this
one then loading effect of Rin of the feedback network, Rin_β it can be ignored. So, and of
course, this is Rout_β and if you look into say this network and it is very simple network.
So, it is easy to see that Rin_β it is nothing but RE1. In fact, Rout_β = RE1.
In fact, so, whenever we look into the output port of the feedback network it works as a
voltage source and this voltage source it is having a Thevenin equivalent resistance and
this resistance it is RE1 and that is what the output resistance of the feedback network.
1369
So, if I know this Rin_β and Rout_β they are approximately equal to RE1. And in addition to
that if I know the Rin it is rπ and Rout it is ro. So, from that we can say that RE1 should be
much less than minimum of the two; rπ and ro. So, these two conditions it is giving us
upper limit of RE1. On the other hand if I consider this condition which is giving me that.
So, it is A′, it is G′m and this is RE1.
So, this need to be much higher than 1 and so, this gives me RE1 need to be higher than
much higher than . So, in summary we can say that in summary we can say that this is
giving me lower limit of RE1 and this is giving me the upper limit of RE1.
So, from these two we can say that if we set the RE1 satisfying both the conditions then,
we can directly use the feedback formula namely, Af which is Gm of the feedback system
= ≈ = .
So, and also then input resistance we can see that this is input resistance it is getting
increased original input resistance it is rπ. So, that is getting increased by the
desensitization factor which is (1 + A′β). So, this is equal to gmRE1. In fact, this is of
course, it is good approximation strictly speaking the actual expression of Rin f you if
you directly analyse this circuit we do get an expression which is very close to this. In
fact, that is having also one more term plus RE1.
But all practical purposes you may ignore this part and so, this part it is giving rπ + β RE1,
if we ignore this part. And if you consider this part, then of course, we will be having one
more small entity and hence if you are constructing this circuit namely if you keep this
portion unbypassed the input resistance of the main circuit excluding of course, the bias
circuit the input resistance it will be rπ + (1 + β)RE1.
So, this is very much consistent to with whatever we know. So, we can correlate the
direct analysis and the feedback circuit analysis. Now on the other hand output resistance
of the feedback system since it is a series connection it is expected that the output
resistance we will also increase by this factor. So, let me use different colour here I do
have this option. So, Rout_f = ro (1 + Aβ) = ro(1 + gmRE1).
So, this also I know the we know that the output resistance looking into this circuit it is
quite high and this can be well approximated by this rogm that is the intrinsic gain of the
1370
transistor multiplied by the unbypassed RE. So, that again correlates that if you directly
analyse this circuit whatever the output resistance you do get it is consistent with the
feedback theory.
So, now let us look into we can use this circuit and then we can go for a numerical
example, but before that while we are making this connection we know that Gm got
decreased and the corresponding Gm it is becoming along with this we also like to
know the information about the other parameter or we can say the change in other
parameters namely, the voltage gain, current gain and also maybe trans impedance of the
circuit.
So, in the next slide what we can do, we can look back the summary table as we have
discussed in our previous lecture. So, let we let we discuss about what kind of effect do
we expect here, but then you have to keep in mind that in this feedback both or rather all
of them rather Af or Gm f it is getting decreased and both input resistance and output
resistance are getting increased by the common factor desensitization factor.
So, with this information let us I will see you what kind of changes do you use observe in
voltage gain and current gain and trans-impedance.
So, here we do have the table and so, this table it is it will be helping us to see what kind
of changes so we do get. In fact, we are making this Gm getting reduced by a factor of
1371
that desensitization. So, this is getting decreased D = (1 + G′mβFB) and it is (1 + gmRE1).
And also we know that input resistance getting increased by this factor, output resistance
it is also getting increased by the same factor D.
Now if I want to see what kind of changes do you expect or do you see for a current gain
then, we have to look into the expression of the current gain in terms of Gm. And this
column gives us the corresponding expression. So, AI it is GmRin. So, we can say that the
current gain it is GmRin. And note that this is true for the circuit before and after the
feedback connection and we know that Gm it got decreased and Rin it got increased by the
same factor.
So, as a result if I combine these two effects, then we can see that there will not be any
change. So, no change due to feedback all right. Likewise, if I consider the if I consider
the voltage gain and if I see the expression of the voltage gain from here which is Gm
times Rout. So, Av = GmRout and here again Gm it is decreased by desensitization factor on
the other hand output resistance got increased by the same factor D. So, altogether they
are getting cancelled and hence no change.
On the other hand, if I consider Zm and it is expression can be obtained from this column;
namely, it is Gm; so, Zm = trans-impedance = GmRinRout. And due to the feedback
connection Gm got decreased Rin got increased and Rout also got increase.
So, altogether we can see whole thing it is getting increased by a factor of

desensitization. So, we can say that Zm it is getting increased. So, that gives us the
overall consequences of the different parameters due to the feedback connection. Now let
we go into a numerical example.
1372
So, here we do have the numerical example, what we have here it is the circuit is given
here and value of different bias circuits are enlisted; namely, RC it is 5 kΩ, RB it is 840
kΩ, supply voltage it is 10 V, RE the total resistor it is 1 kΩ, base to emitter on voltage it
is 0.6 V and β is 100. So, if you consider this parameters we can say that the bias current
here it is 10 µA.
And because of the β, 100 the corresponding collector current it is 1 mA. So, the drop
across this one it is 1 V and drop across this RC it is 5 V so, we do have 4 V. So, the
device it is in active region of operation. So, it is really working as a good amplifier.
Now, with 1 mA of current gm of the transistor it is ℧ and rπ on the other hand which
is = 2.6 kΩ and then ro it is so, that gives us 100 kΩ.
So, with this information we can directly say that Gm or G′m ≈ ℧, Rin it is 2.6 kΩ, Rout
it is 100 kΩ and the feedback factor RE1 we need to find. So, to get this value here again
we may recall that different conditions and what are the conditions we do have? The
Rin_β which is also equal to Rout_β need to be much less than minimum of this two; so, this
should be much less than 2.6 kΩ and so, these two are essentially RE1.
And the on the other hand the lower limit for RE1 it is coming from A′ βFB should be
much higher than 1, which means that this βFB = RE1. So, this βFB should be much higher
1373
than which is and this is = 26 Ω. So, in summary we can say that the suitable
range of RE1 it is it should be well within 26 Ω to 2.6 kΩ.
Now, whenever we do have this requirement much less or much greater then at least we
can say it is better to have one order of magnitude lower or higher. So, based on these
two conditions; we may say that we can select say RE1 = 260 Ω, satisfying both these two
conditions.
And if you take this RE1 = 260 Ω, then Gm_f it can be well approximated by = . In
fact, if you see the desensitization factor D which is (1 + AβFB) and if I put the value of
this βFB of say 260 Ω. So, D = 11, you may say that D ≈ 10.
So, we can see that Gm, Gm of this one it is getting reduced by a factor of 10. Likewise
the input resistance it is getting increased. So, Rin_f = 2.6 k × this desensitization factor
approximately 10. So, Rin_f ≈ 26 kΩ to be more precise it should be multiplied by 11. So,
instead of 26 kΩ to be more precise we can say that 28.6 kΩ.
And then the output resistance on the other hand it is approximately so, Rout_f is 100 k ×
desensitisation factor. So, that gives us 1 MΩ or if I put the D = 11. So, that gives us 1.1
MΩ. So, in summary what we can say here it is due to the feedback connection, trans-
conductance it is instead of . Input resistance it got increased to 26 kΩ from 2.6 kΩ
and Rout rather output resistance instead of 100 kΩ it is now it is 1 MΩ.
So, you might have observed one thing that while we are doing this analysis we are
keeping this RC outside of this circuit and that is very obvious that if you really want to
take this RC to be inside the circuit the other end here it need to be connected here then
only you can consider RC it is part of the current source.
So, in this configuration; we have to keep the RC outside of the amplifier otherwise the
analysis it will be it is possible, but it will get really fairly complicated. Now coming to
what are the consequences on the other parameter namely the voltage gain and current
gain and trans-impedance as we have discussed that we are anticipating that the voltage
gain and current gain will not be having change. And, however; trans-impedance will be
having a change rather trans-impedance it will increase. But we like to add something to
that. So, let us go into the next slide to discuss the one very important point.
1374
So, again we can to understand what kind of changes it will be there in voltage gain and
the current gain and the trans-impedance. We refer back to this relationship table, the let
me change the colour of this. So, we do have as I said that we are anticipating that the
voltage gain and current gain will not be having any change and this will be getting
increased by desensitisation factor D.
And trans-impedance if you see. So, if you see this column . So, trans-impedance of
course, it is Gm. So, Zm initially it was GmRinRout and Gm with the feedback connection
this Gm it is that circuit Gm I should write. So, circuit Gm it got decreased, this got
increased and this got increased. So, as a results the whole thing namely Zm got increased
by a factor of D = 11 or D ≈ 10.
And this is this result or this observation definitely you will be able to see only when you
consider this RC it remaining outside. We can say that if I consider this is remaining
outside or if I consider it is external load then you will be getting this situation.
Now, if I consider this is part of the amplifier and then if I try to see what kind of
changes do you expect in the voltage gain particularly what you will be getting here
before we make the feedback connection, the voltage gain it is equal to gmro, if I consider
magnitude of the voltage gain gmro multiplied by the loading effect which is equal to
loading effect due to RC . And so, the loading effect or factor it is .
1375
So, this is the expression of the voltage gain before we connect the circuit in feedback
configuration. In fact, this can be written in this form gm(ro⫽RC) and all practical
purposes you can approximate this by gmRC. As you can see that numerical value wise
RC it is 5 kΩ and ro it is on the other hand 100 kΩ. So, definitely this is what you can
expect.
Now this is before we connect feedback connection. Now after we make the feedback
connection what do we expect it is the following. So, the Gm it got changed. So, also the
output resistance got changed. So, if I say that Rout in this case it is approximately RC on
the other hand with feedback this is equal to ro got increased by the desensitization
factor.
Now along with this Rout of the feedback system if I consider RC coming into the loading
then the corresponding Rout we can say R′out_f = (ro × D) ⫽ RC. So, if I consider this
resistance in parallel with RC, this can be well approximated by RC.
So, what we can say that if I include this RC within the circuit to get the voltage gain not
for gm, but for voltage gain. What we can see that this Rout initially it was rather R′out,
R′out it was initially RC and R′out_f it is also remaining RC, which means that the Rout if I
considered this RC within the circuit rather R′out it is not really changing, it is remaining
to RC.
As a result if I see the voltage gain and it is expression it is Gm and then if I consider RC
into it so, R′out. So, this is equal to gmRC. And after the feedback connection then we do
have Gm_f then R′out_f = × RC. So, as a result what we can see here; interestingly, what
we can observe here is that the voltage gain it is actually it is getting changed from gm ×
RC to gm × .
So, this is this is the situation when you consider RC into the picture which means that
the gain it is voltage gain it is dropping to this. In fact, this is what we know it is
all right. So, this is what we know.
So, if I do not consider RC into the circuit then we claim that the voltage gain it was not
changing, but we know that the voltage gain of the common emitter amplifier it is it is
1376
dropping particularly in presence of unbypassed RE1. In fact, similar kind of conclusion
you can also find for Zm , but so, as I said that expression of the Zm it is it is GmRinRout.
Now if I consider RC into the consideration then we have to consider R′out. And what I
said is that Gm it is getting decreased by the feedback circuit Rin got increased, but then
R′out it is not changing. So, overall the Zm, if I consider RC into the consideration it is not
having any change.
So, in summary let me clear and then let me write this summary if I consider this RC.
Then we can say that the voltage gain it is getting reduced by D all practical purposes
that short it will happen, mainly because R′out it is approximately RC, R′out_f it is also
equal to RC. On the other hand Zm it is remaining unchanged, no change and on the other
hand of course, the current gain it is not having any change, similar to whatever we have
seen here. So, let me take again short break and then we will come back to another
example and there we will see how we can handle multiple loops in a circuit.
1377
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PH : (044) 2257 5905/08 nptel.ac.in swayam.gov.in

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INDEX

(Refer Slide Time: 01:52)

(Refer Slide Time: 02:58)

(Refer Slide Time: 04:46)

(Refer Slide Time: 10:13)

(Refer Slide Time: 11:45)

(Refer Slide Time: 30:53)

(Refer Slide Time: 30:31)

(Refer Slide Time: 47:34)

(Refer Slide Time: 01:25)

(Refer Slide Time: 03:15)

(Refer Slide Time: 12:50)

(Refer Slide Time: 12:56)

(Refer Slide Time: 27:26)

(Refer Slide Time: 29:59)

(Refer Slide Time: 36:01)

(Refer Slide Time: 37:33)

(Refer Slide Time: 39:21)

(Refer Slide Time: 01:05)

(Refer Slide Time: 03:14)

(Refer Slide Time: 15:58)

(Refer Slide Time: 24:04)

(Refer Slide Time: 27:23)

So, suppose we do have R1 and R2 connected to ground. This node it is connected to a DC

(Refer Slide Time: 34:46)

(Refer Slide Time: 00:57)

And, thermal equivalent voltage VT = . Here, k is Boltzmann constant; T is absolute

resistance of the diode. In fact, this ron it is reciprocal of this slope.

(Refer Slide Time: 09:45)

(Refer Slide Time: 10:58)

through this circuit it will be .

(Refer Slide Time: 15:38)

(Refer Slide Time: 26:46)

(Refer Slide Time: 01:11)

Essentially, in small signal equivalent circuit what we do is we do linearize non-linear

(Refer Slide Time: 03:56)

(Refer Slide Time: 05:06)

(Refer Slide Time: 12:53)

because the axis got changed.

subsequently you can go to the third step.

(Refer Slide Time: 32:06)

(Refer Slide Time: 33:17)

we are concentrating on the magnitude.

(Refer Slide Time: 00:57)

(Refer Slide Time: 07:59)

to Vd what will be getting is will be practically getting .

it is in this case right.

(Refer Slide Time: 12:09)

current will be getting here, say * + .

(Refer Slide Time: 21:51)

(Refer Slide Time: 27:49)

(Refer Slide Time: 33:17)

(Refer Slide Time: 01:48)

(Refer Slide Time: 03:11)

So, in normal circumstances, particularly for analog operation unless otherwise it is

(Refer Slide Time: 11:20)

similar. In fact, this part again you may replace by ( ) .

and then of course, this part it is dropped.

(Refer Slide Time: 32:50)

this becomes 1, so becomes 1. So, we do have only this part.

(Refer Slide Time: 39:50)

(Refer Slide Time: 42:13)

So, expression of current carried by electron equals to ‧npo ( ) , and as

getting along with Dp will be having Lp in the denominator because we do have we