decoder_2x4

module decoder_2x4(a,b,d);
input a,b;
output [3:0]d;
assign d[0] = ~a & ~b;
assign d[1] = ~a & b;
assign d[2] = a & ~b;
assign d[3] = a & b;
endmodule

Test Bench

module decoder_2x4_tb;
reg a,b;
wire [3:0] d;

decoder_2x4 d4(a,b, d);

initial begin
// Initialize Inputs
#20 a=0;b=0 ;
#20 a=0;b=1 ;
#20 a=1;b=0 ;
#20 a=1;b=1 ;
#50 $stop;
end
endmodule
decoder_3x8

module decoder_3x8(a,b,c,d);
input a,b,c;
output [7:0]d;

assign d[0] = ~a & ~b & ~c;

assign d[1] = ~a & ~b & c;
assign d[2] = ~a & b & ~c;
assign d[3] = ~a & b & c;
assign d[4] = a & ~b & ~c;
assign d[5] = a & ~b & c;
assign d[6] = a & b & ~c;
assign d[7] = a & b & c;

endmodule

Test Bench

module decoder_3x8_tb;
reg a,b,c;
wire [7:0]d;
decoder_3x8 d4(a,b,c,d);
initial begin
// Initialize Inputs
#20 a=0;b=0;c=0;
#20 a=0;b=0;c=1;
#20 a=0;b=1;c=0;
 #20 a=0;b=1;c=1;
#20 a=1;b=0;c=0;
#20 a=1;b=0;c=1;
#20 a=1;b=1;c=0;
#20 a=1;b=1;c=1;
#50 $stop;
end
endmodule

decoder_3x8 with enable

module decoder_3x8en(a,b,c,en,d);
input a,b,c,en;
output [7:0]d;

assign d[0] = en & ~a & ~b & ~c;

assign d[1] = en &~a & ~b & c;
assign d[2] = en &~a & b & ~c;
assign d[3] = en &~a & b & c;
assign d[4] = en &a & ~b & ~c;
assign d[5] = en &a & ~b & c;
assign d[6] = en &a & b & ~c;
assign d[7] = en &a & b & c;

endmodule

Test Bench
module decoder_3x8en_tb;
 reg a,b,c,en;
wire [7:0]d;
decoder_3x8en d4(a,b,c,en,d);
initial begin
// Initialize Inputs
#20 en=1;a=0;b=0;c=0;
#20 en=1;a=0;b=0;c=1;
#20 en=1;a=0;b=1;c=0;
#20 en=1;a=0;b=1;c=1;
#20 en=1;a=1;b=0;c=0;
#20 en=1;a=1;b=0;c=1;
#20 en=1;a=1;b=1;c=0;
#20 en=1;a=1;b=1;c=1;
#50 $stop;
end
endmodule

decoder 4x16 using two 3x8 with enable

module decoder4x16u3x8en(a,b,c,en,d);
input a,b,c,en;
output [16:0]d;
wire nen;
assign nen=~en;
decoder_3x8en d1(a,b,c,nen,d[7:0]);
decoder_3x8en d2(a,b,c,en,d[15:8]);
endmodule
 Test Bench
module decoder4x16u3x8en_tb;
reg a,b,c,en;
wire [15:0]d;
decoder4x16u3x8en d4(a,b,c,en,d);
initial begin
// Initialize Inputs
#20 en=0;a=0;b=0;c=0;
#20 en=0;a=0;b=0;c=1;
#20 en=0;a=0;b=1;c=0;
#20 en=0;a=0;b=1;c=1;
#20 en=0;a=1;b=0;c=0;
#20 en=0;a=1;b=0;c=1;
#20 en=0;a=1;b=1;c=0;
#20 en=0;a=1;b=1;c=1;
#20 en=1;a=0;b=0;c=0;
#20 en=1;a=0;b=0;c=1;
#20 en=1;a=0;b=1;c=0;
#20 en=1;a=0;b=1;c=1;
#20 en=1;a=1;b=0;c=0;
#20 en=1;a=1;b=0;c=1;
#20 en=1;a=1;b=1;c=0;
#20 en=1;a=1;b=1;c=1;
#50 $stop;
end
endmodule
Full adder using 3x8 decoder
module fa_decoder_3x8(a,b,c,sum,carry);
input a,b,c;
output sum,carry;
wire [7:0]d;
decoder_3x8 d1(a,b,c,d);
assign sum= d[1] | d[2] | d[4]| d[7];
assign carry= d[3] | d[5] | d[6]| d[7];

endmodule

Test Bench
module fa_decoder_3x8_tb;
reg a,b,c,en;
wire [7:0]d;
fa_decoder_3x8 d4(a,b,c,sum,carry);
initial begin
// Initialize Inputs
#20 a=0;b=0;c=0;
#20 a=0;b=0;c=1;
#20 a=0;b=1;c=0;
#20 a=0;b=1;c=1;
#20 a=1;b=0;c=0;
#20 a=1;b=0;c=1;
#20 a=1;b=1;c=0;
#20 a=1;b=1;c=1;
 #50 $stop;
end
endmodule