STA508

Datasheet

40 V, 4.5 A quad power half bridge

Features
• Multipower BCD technology
• Minimum input output pulse width distortion
• 200 mΩ RdsON complementary DMOS output stage
• CMOS compatible logic input
• Thermal protection
PowerSO-36
with exposed pad up • Thermal warning output
• Undervoltage protection

Description
STA508 is a monolithic quad half bridge stage in Multipower BCD technology. The
device can be used as dual bridge or reconfigured, by connecting CONFIG pin to
Vdd pin, as single bridge with double current capability, and as half bridge (Binary
mode) with half current capability.
The device is particularly designed to make the output stage of a stereo all-digital
high efficiency (DDX™) amplifier capable to deliver 80 + 80 W @ THD = 10 % at VCC
= 35 V output power on 8 Ω load.
In single BTL configuration is also capable to deliver a peak of 160 W @ THD = 10
% at VCC = 35 V on 4 Ω load. The input pins have threshold proportional to VL pin
voltage.

Maturity status link

STA508

Device summary

Order code STA50813TR

Package PowerSO-36 (EPU)

DS3503 - Rev 6 - November 2020 www.st.com

For further information contact your local STMicroelectronics sales office.
 STA508
Diagram

1 Diagram

Figure 1. Block diagram

VCC1A +VCC

15
IN1A 29 M3 C30 C55
IN1A 1µF 1000µF
17 L18 22µH
VL 23
+3.3V OUT1A
CONFIG 24 16 C20
100nF
OUT1A
PWRDN PWRDN 25 M2 C52
14 GND1A 330pF R98 C99
PROTECTIONS 6 100nF
R57 R59 FAULT 27 & C23 8Ω
10K 10K LOGIC
26 12 VCC1B 470nF
R63 R100 C101
TRI-STATE
C58 M5 C31 20 6 100nF
100nF 11 1µF
C21
TH_WAR 28 OUT1B 100nF
TH_WAR 10
IN1B 30 OUT1B L19 22µH
IN1B
M4
VDD 21 13 GND1B
VDD 22
VSS 33 REGULATORS
7 VCC2A
VSS 34
M17 C32
C58 C53 1µF
100nF 100nF VCCSIGN 8 L113 22µH
35
OUT2A
C60 9 C110
100nF VCCSIGN 100nF
36 OUT2A
M15 C109
IN2A 6 GND2A 330pF R103 C107
IN2A 31 6 100nF
GND-Reg C108 8Ω
20 4 VCC2B 470nF
R104 R102
GND-Clean C106
C33 20 6
19 M16 100nF
3 1µF
C111
OUT2B 100nF
IN2B 2
IN2B 32
OUT2B L112 22µH
GNDSUB M14
1 5 GND2B

DS3503 - Rev 6 page 2/19

 STA508
Pin configuration

2 Pin configuration

Figure 2. Pin connection (top view)

VCCSign 36 1 GND-SUB
VCCSign 35 2 OUT2B
VSS 34 3 OUT2B
VSS 33 4 VCC2B
IN2B 32 5 GND2B
IN2A 31 6 GND2A
IN1B 30 7 VCC2A
IN1A 29 8 OUT2A
TH_WAR 28 9 OUT2A
FAULT 27 10 OUT1B
TRI-STATE 26 11 OUT1B
PWRDN 25 12 VCC1B
CONFIG 24 13 GND1B
VL 23 14 GND1A
VDD 22 15 VCC1A
VDD 21 16 OUT1A
GND-Reg 20 17 OUT1A
GND-Clean 19 18 N.C.

Table 1. Pin description

Pin N° Name Description

1 GND-SUB Substrate ground

2, 3 OUT2B Output half bridge 2B

4 VCC 2B Positive supply

5 GND2B Negative supply

6 GND2A Negative supply

7 VCC 2A Positive supply

8, 9 OUT2A Output half bridge 2A

10, 11 OUT1B Output half bridge 1B

12 VCC 1B Positive supply

13 GND1B Negative supply

14 GND1A Negative supply

15 VCC 1A Positive supply

16, 17 OUT1A Output half bridge 1A

18 NC Not connected
19 GND-clean Logical ground

20 GND-Reg Ground for regulator Vdd

DS3503 - Rev 6 page 3/19

 STA508
Pin configuration

Pin N° Name Description

21, 22 Vdd 5 V Regulator referred to Ground

23 VL High logical state setting voltage

24 CONFIG Configuration pin

25 PWRDN Stand-by pin
26 TRI-STATE Hi-Z pin
27 FAULT Fault pin advisor
28 TH-WAR Thermal warning advisor
29 IN1A Input of half bridge 1A
30 IN1B Input of half bridge 1B
31 IN2A Input of half bridge 2A
32 IN2B Input of half bridge 2B

33, 34 VSS 5 V regulator referred to + VCC

35, 36 VCC Sign Signal positive supply

Table 2. Functional pin status

Pin name Logical value IC-STATUS

FAULT 0 Fault detected (Short circuit, or Thermal ..)

FAULT (1) 1 Normal operation

TRI-STATE 0 Allpowers in Hi-Z state

TRI-STATE 1 Normal operation
PWRDN 0 Low absorbion
PWRDN 1 Normal operation
THWAR 0 Temperature of the IC = 130 °C

THWAR (1) 1 Normal operation

CONFIG 0 Normal Operation

CONFIG (2) 1 OUT1A = OUT1B; OUT2A=OUT2B (If IN1A = IN1B; IN2A = IN2B)

1. The pin is open collector. To have the high logic value, it needs to be pulled up by a resistor.
2. To put CONFIG = 1 means connect Pin 24 (CONFIG) to Pins 21, 22 (Vdd).

DS3503 - Rev 6 page 4/19

 STA508
Maximum ratings

3 Maximum ratings

Table 3. Absolute maximum ratings

Symbol Parameter Value Unit

VCC DC supply voltage (Pin 4, 7, 12, 15) 40 V

Vmax Maximum voltage on pins 23 to 32 5.5 V

Ptot Power dissipation (Tcase = 70 °C) 50 W

Top Operating temperature range - 40 to 90 °C

Tstg Storage temperature

- 40 to 150 °C
Tj Junction temperature

Table 4. Thermal data

Symbol Description Value Unit

Rthj-case Thermal resistance junction-case max 1.5 °C/W

DS3503 - Rev 6 page 5/19

 STA508
Electrical characteristics

4 Electrical characteristics

Table 5. Electrical characteristics VL = 3.3 V; VCC = 30 V; Tamb = 25 °C ; fsw = 384 kHz unless otherwise
specified.

Symbol Parameter Test conditions Min. Typ. Max. Unit

Power P-channel/N-channel
RdsON Id = 1 A 200 270 mΩ
MOSFET RdsON

Power P-channel/N-channel
Idss VCC = 35 V 50 µA
leakage Idss

gN Power P-channel RdsON matching Id = 1 A 95 %

gP Power N-channel RdsON matching Id = 1 A 95 %

Dt_s Low current dead time (static) See Figure 5 10 20 ns

L = 22 µH; C = 470 nF;
Dt_d High current dead time (dinamic) RL = 8 Ω 50 ns
Id = 3.5 A; see Figure 5

td ON Turn-on delay time Resistive load 100 ns

td OFF Turn-off delay time Resistive load 100 ns

tr Rise time Resistive load; as Figure 3 25 ns

tf Fall time Resistive load; as Figure 3 25 ns

VCC Supply voltage operating voltage 10 36 V

VL/2
VIN-High High level input voltage V
+300 mV
VL/2-300
VIN-Low Low level input voltage V
mV
IIN-High High level input current Pin voltage = VL 1 µA

IIN-Low Low level input current Pin voltage = 0.3 V 1 µA

IPWRDN-H High level PWRDN pin input current VL = 3.3 V 35 µA

Low logical state voltage VL (pin

VL VL = 3.3 V 0.8 V
PWRDN, TRISTATE) (1)
High logical state voltage VH (pin
VH VL = 3.3 V 1.7 V
PWRDN, TRISTATE) (1)
Supply CURRENT from VCC in
IVCC- PWRDN PWRDN = 0 3 mA
Power Down
Output current pins Fault -th-warn
IFAULT Vpin = 3.3 V 1 mA
when Fault conditions
IVCC-hiz Supply current from VCC in Tri-state VCC = 30 V; Tri-state = 0 22 mA

VCC= 30 V;

Supply current from VCC in Input pulse width = 50%

IVCC duty; 50 mA
operation both channel switching)
Switching frequency = 384
kHz; No LC filters

IVCC-q Isc (short circuit current limit) .(2) 4.5 6 9 A

VUV Undervoltage protection threshold 7 V

DS3503 - Rev 6 page 6/19

 STA508
Electrical characteristics

Symbol Parameter Test conditions Min. Typ. Max. Unit

tpw-min Output minimum pulse width No load 70 150 ns

1. See Table 6. VLow, VHigh variation with VL.

2. See relevant Application Note AN1994

Table 6. VLow, VHigh variation with VL

VL VLow min VHigh max Unit

2.7 0.7 1.5 V

3.3 0.8 1.7 V
5 0.85 1.85 V

Table 7. Logic truth table (see fig. 5)

Tri-state INxA INxB Q1 Q2 Q3 Q4 Output mode

0 x x OFF OFF OFF OFF Hi-Z

1 0 0 OFF OFF ON ON DUMP
1 0 1 OFF ON ON OFF NEGATIVE
1 1 0 ON OFF OFF ON POSITIVE
1 1 1 ON ON OFF OFF Not used

DS3503 - Rev 6 page 7/19

 STA508
Test circuits and typical application diagrams

5 Test circuits and typical application diagrams

Figure 3. Test circuit 1

OUTxY
Vcc

(3/4)Vcc
Low current dead time = MAX (DTr, DTf)
(1/2)Vcc

(1/4)Vcc
+Vcc

t
Duty cycle = 50% DTr DTf
M58
OUTxY R 8Ω
INxY

M57 +
-
V67 =
vdc = Vcc/2
gnd

Figure 4. Test circuit 2

+VCC

Q1 Q2
OUTxA OUTxB
INxA INxB

Q3 Q4

GND

Figure 5. Test circuit 3

High Current Dead time for Bridge application = ABS [DTout(A) - DTin(A)] + ABS [DTOUT(B) - DTin(B)]

+VCC

Duty cycle = A Duty cycle = B

DTout(A)

M58 Q1 Q2 M64
DTin(A) DTout(B) DTin(B)
OUTA Rload = 8 Ω OUTB
INA INB
L67 22 µ L68 22 µ
Iout = 4 A Iout = 4 A
M57 Q3 C69 C70 Q4 M63
470 nF C71 470 nF 470 nF

Duty cycle A and B: Fixed to have DC output current of 4 A in the direction shown in figure

DS3503 - Rev 6 page 8/19

 STA508
Test circuits and typical application diagrams

Figure 6. Typical single BTL configuration

VL
+3.3V 23 18 N.C.
100nF 10µH
GND-Clean 17
19 OUT1A
16 100nF
GND-Reg OUT1A FILM
20
10K 100nF 11
OUT1B 22Ω 6.2 100nF
X7R VDD 10 X7R
1/2W 1/2W
21 OUT1B
VDD 470nF 4Ω
22 OUT2A FILM
CONFIG 9 6.2
24 OUT2A 330pF 100nF
1/2W
8 X7R
TH_WAR
TH_WAR 28 OUT2B 100nF
3 FILM
PWRDN OUT2B
nPWRDN 25 2
10µH
10K FAULT
27 VCC1A
15 32V
26
TRI-STATE 1µF 2200µF
100nF X7R 63V
IN1A VCC1B
29 12
IN1B
IN1A 30
IN2A VCC2A
31 7 32V
IN2B
IN1B 32 1µF
X7R
VSS VCC2B
33 4
VSS
34 GND1A
100nF 14
X7R VCCSIGN GND1B
35 13

100nF VCCSIGN GND2A

X7R 36 6
Add. GNDSUB GND2B
1 5

Figure 7. Typical quad half bridge configuration

VCC1P +VCC

15
IN1A 29 M3 R61 C21
IN1A 5K C31 820µF 2200µF
17 L11 22µH
VL 23
+3.3V OUTPL
CONFIG 24 16 R41 C71
20 100nF
OUTPL C91 4Ω
PWRDN PWRDN 25 M2 1µF
14 PGND1P R51 C81 R62
PROTECTIONS C41 100nF
6 5K
R57 R59 FAULT 27 & 330pF
10K 10K LOGIC
26 12 VCC1N
TRI-STATE
C58 M5 C51 C61
100nF 11 1µF 100nF
R63
TH_WAR 28 OUTNL 5K C32 820µF
TH_WAR 10 L12 22µH
IN1B 30 OUTNL
IN1B R42 C72
M4 20 100nF
VDD 21 13 PGND1N C92 4Ω
1µF
VDD 22 R52 C82 R64
C42 100nF
6 5K
VSS 33 REGULATORS 330pF
7 VCC2P
VSS 34
M17 R65
C58 C53 C33 820µF
L13 22µH 5K
100nF 100nF VCCSIGN 8
35
OUTPR
C60 9 R43 C73
100nF VCCSIGN 20 100nF
36 OUTPR C93 4Ω
M15 1µF
IN2A 6 PGND2P R53 C83 R66
IN2A 31 C43 100nF
6 5K
330pF
GND-Reg
20 4 VCC2N
GND-Clean
19 M16 C52 C62
3 1µF 100nF
R67
OUTNR 5K C34 820µF
IN2B 2 L14 22µH
IN2B 32
OUTNR
R44 C74
GNDSUB M14 20 100nF
1 5 PGND2N C94 4Ω
1µF
R54 C84 R68
C44 100nF
6 5K
330pF

For more information refer to the application note AN1661.

DS3503 - Rev 6 page 9/19

 STA508
Package information

6 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.

DS3503 - Rev 6 page 10/19

 STA508
PowerSO-36 exposed pad up package information

6.1 PowerSO-36 exposed pad up package information

Figure 8. PowerSO-36 exposed pad up package outline

BOTTOM VIEW

TOP VIEW

DS3503 - Rev 6 page 11/19

 STA508
PowerSO-36 exposed pad up package information

Figure 9. PowerSO-36 section A-A and B-B package outline

SECTION A-A
NOT TO SCALE

SECTION B-B
NOT TO SCALE

DS3503 - Rev 6 page 12/19

 STA508
PowerSO-36 exposed pad up package information

Table 8. PowerSO-36 package mechanical data

mm
Dim.
Min. Typ. Max.

Ɵ 0° - 8°
Ɵ1 5° - 10°
Ɵ2 0° - -
A - - 3.41
A1 0.30 - -0.40
A2 3.10 3.14 3.18
A3 - 0.2 -
A4 0.80 - 1.00
b 0.22 - 0.41
b1 0.22 - 0.38
c 0.23 - 0.32
c1 0.23 0.25 0.29
D 15.90 BSC
D1 VARIATION
D2 - 1.00
D3 - 5.00 -
e 0.65 BSC
E 14.20 BSC
E1 11.00 BSC
E2 VARIATION
E3 - - 2.90
h - - 1.10
L 0.80 - 1.10
L1 1.60 REF
L2 0.35 BSC
N 36
R 0.20 - -
R1 0.20 - -
s 0.25 - -

DS3503 - Rev 6 page 13/19

 STA508
PowerSO-36 exposed pad up package information

Table 9. Tolerance of form and position

Symbol Databook

aaa 0.10
bbb 0.30
ccc 0.075
ddd 0.25
eee 0.10
ggg 0.25
Note 1.2

Table 10. Variations

Databook
Symbol Opt.
Min. Typ. Max.

D1 9.40 - 9.80
A
E2 5.80 - 6.20

DS3503 - Rev 6 page 14/19

 STA508

Revision history

Table 11. Document revision history

Date Revision Changes

Sep 1994 1 Initial release.

Jun 2004 2 Note 2: See relevant Application Note AN1994

Nov 2004 3 Changed VCC from 9 min to 10 min

Feb 2006 4 Changed Top value on Table 5.

01-Sep-2020 5 Updated order code in device summary on the cover page.

Updated package name, Figure 2 and Section 6.1 PowerSO-36
19-Nov-2020 6
exposed pad up package information.

DS3503 - Rev 6 page 15/19

 STA508
Contents

Contents
1 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
4 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5 Test circuits and typical application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
6.1 PowerSO36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

DS3503 - Rev 6 page 16/19

 STA508
List of tables

List of tables
Table 1. Pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Table 2. Functional pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 5. Electrical characteristics VL = 3.3 V; VCC = 30 V; Tamb = 25 °C ; fsw = 384 kHz unless otherwise specified. . . . . . . 6
Table 6. VLow, VHigh variation with VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 7. Logic truth table (see fig. 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 8. PowerSO-36 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 9. Tolerance of form and position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 10. Variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 11. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

DS3503 - Rev 6 page 17/19

 STA508
List of figures

List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 2. Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 3. Test circuit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Test circuit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. Test circuit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 6. Typical single BTL configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. Typical quad half bridge configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 8. PowerSO-36 exposed pad up package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 9. PowerSO-36 section A-A and B-B package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

DS3503 - Rev 6 page 18/19

 STA508

IMPORTANT NOTICE – PLEASE READ CAREFULLY

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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2020 STMicroelectronics – All rights reserved

DS3503 - Rev 6 page 19/19