Superior University Lahore

Faculty of Computer Science & Information Technology

Course Outline
Course Course Title Computer System Architecture
Information Course ID CS2403 Course Type Computing Core
Credit hours 3 Hours per week (C-L) 3-0
Programs BS (CS) Preferred Semester 3
Date 2018-11-31 Version 1.0
Instructor Mahrukh Batool TA / Lab Engineer Nil
Course This course is designed to give introduction to computer organization & architecture, CPU structure & functions,
Description buses, memory, input/output, instruction sets etc. By the end of the course, the students should understand the
major architectural styles and appreciate the compromises that they encapsulate. It includes the following major
topics;
- register transfer and micro operation
- control logic inside central computing unit
- data flow and pipeline
- instruction set architecture
Course The objective of this course is to enable students;
Objectives No. Objective Relation with
Program
Objectives
1. To understand the basics of computer hardware and how software PLO2
interacts with computer hardware
2. Depth Knowledge to analyze and evaluate computer performance PLO5
3. Ability to understand how computers represent and manipulate data PLO10
4. To understand computer arithmetic and convert between different PLO1
number systems
Course At the end of this course students will be able to demonstrate;
Learning No. Outcome Relation with
Outcomes PLO
(CLO) 1. Understand Computer architecture and component like processor, memory and I/O PLO1
2. Understand and compare different processors and instruction set, arithmetic PLO6
function and overall functionality and usability
3. Knowledge of terminologies and key concepts in computer architecture for PLO1
advanced studies
4. Evaluate the performance of CPU, memory and I/O operations and give solutions PLO3
related to their problems.
Lecture type
Prerequisite Digital Logic and Design
s
Follow up Operating Systems
Courses
Course
Software
or Tool
Textbook Title Edition Authors Publisher Year ISBN
Computer Organisation and 9th William Stallings Pearson 2012 978-0132936330
Architecture
References Computer System Architecture 3rd M. Morris Mano Pearson 1992 978-0131755635
Computer Architecture: A 5th David A. Morgan 2011 2011 978-
Quantitative Approach Patterson Kauffman 0123838728
Assessment Assessment Weight Used to attain CLO Assessment Weight Used to attain CLO
Criteria Assignment 10% 1,2,3,4 Quiz 10% 1,2,3,4
(100%) Lab 0% Project / Presentation 10%
Attendance 0% Participation 5%

Page 1 of 5
 Mid Term 25% 1,2,3,4 Final 40% 1,2,3,4
Methods of
Evaluation
Notes

Week Lecture Relation with

Topic Lecture Contents
No. No. CLO
Introduction to computer
Organization and Architecture
Function & Structure
Von Neuman Architecture
L1.
Processor
Memory
Introduction &
W1. Input Out Devices CLO1
Background

History of Computers
The First Generation: Vacuum Tubes
L2. The Second Generation: Transistors
The Third Generation: Integrated Circuits

Later Generations
The Evolution of the Intel x86 Architecture
L3.
ARM Evolution

W2. History  CLO1 ,

Microprocessor Speed
Performance Balance
L4.
Improvements in Chip Organization and Architecture

Computer Components
L5. Instruction Fetch and Execute

Components of
W3. Interrupts  CLO2,CLO4
Computer
I/O Function
L6.
Interconnection Structures

Bus Structure
Multiple-Bus Hierarchies
L7. Elements of Bus Design
Bus Structure
Components of
W4. CLO1, CLO3
Computer
PCI Commands
Data Transfers
L8.
Arbitration

Semiconductor Main Memory CLO1,CLO3, CLO

W5. Memory L9.
Organization 4
 DRAM and SRAM
Types of ROM
Chip Logic
PROM, EPROM, EEPROM,ECC,

Synchronous DRAM
Rambus DRAM
DDR SDRAM
L10.
Cache DRAM
SRAM, DRAM,

Cache Memory
L11. Principles

Elements of Cache Design

Memory(Cache Cache Addresses
W6. CLO2, CLO4
) Cache Size
L12. Mapping Function
Replacement Algorithms
Write Policy

Line Size
Number of Caches
L13.
Practice Question
Memory(Cache
W7. CLO2, CLO4
) Associative mapping
Set Associative Mapping
L14.
Practice Question

Summary of components, Memory and Cache

Presentations
L15.
Revision

MID Term
W8. CLO1
Week

L16. MID TERM

Magnetic Disk
L17. Raid
External
W9.  CLO4
Memory
Optical Memory
L18. Magnetic Tape

I/O Modules CLO1,CLO2, CLO

W10. Input/Output L19.
Module 4
 Programmed I/O
Interrupt-Driven I/O

Direct Memory Access

L20. I/O Channels and Processors

Integer Representation
L21. Arithmetic operation
Computer
W11.  CLO2
Arithmetic Floating point numbers
L22. Floating-Point Representation

Elements of a Machine Instruction

Instruction Representation
Instruction Types
L23.
Number of Addresses
Instruction Set Design

Machine
W12. Types of Operands  CLO2
Instruction Sets
Intel x86 and ARM Data Types
Pentium Data Types
L24. Types of Operation, Data Transfer, Arithmetic,
Logical, Conversion, I/O,
System Control, Transfer of Control
Instruction Formats
Immediate Addressing
Direct Addressing
Indirect Addressing
Register Addressing
L25.
Addressing Register Indirect Addressing
W13. Modes & Displacement Addressing CLO2
Processor Stack Addressing

CPU Structure
L26. Processor organization

Registers, User Visible Registers,

General Purpose Registers,
L27.
Processor Condition Code Registers, Control & Status Registers
W14. Structure & CLO2,CLO4
function Instruction Cycle, Indirect Cycle,
L28. Instruction Cycle with Indirect

Pipelining Strategy
L29. Pipeline Performance
W15. Pipelining  CLO4

L30. Pipeline Hazards

 Dealing with Branches
Intel 80486 Pipelinin

Parallel Computer Memory Architectures

Intro to Quantum Computing
Parallel 31
W16. Memory architecture of GPUS  CLO3
processing
Intro to CUDA
32 Revision