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- Adsorption and Diffusion of Aluminum on -
Ga2O3(010) Surfaces
Mengen Wang et al
- R. Singh et al
β-(AlxGa1%x)2O3/β-Ga2O3 heterostructures were grown via plasma-assisted molecular beam epitaxy. The β-(AlxGa1%x)2O3 barrier was partially
doped by Ge to achieve a two-dimensional electron gas (2DEG) in Ga2O3. The formation of the 2DEG was confirmed by capacitance–voltage
measurements. The impact of Ga-polishing on both the surface morphology and the reduction of the unintentionally incorporated Si at the growth
interface was investigated using atomic force microscopy and secondary-ion mass spectrometry. Modulation doped field-effect transistors were
fabricated. A maximum current density of 20 mA/mm with a pinch-off voltage of %6 V was achieved on a sample with a 2DEG sheet charge density
of 1.2 ' 1013 cm%2. © 2017 The Japan Society of Applied Physics
Fig. 1. Schematic of the β-(AlxGa1−x)2O3–Ga2O3 heterostructure, showing Fig. 2. XRD 2θ–ω profile along the 020 direction showing a similar Al2O3
the epi-stack grown via PAMBE, along with the fabricated transistor. On the mole fraction of ∼8% for all three samples.
samples A1 and A2, x1 and x2 are 16 nm and 27 nm thick. While on sample
B, x1 and x2 are 7 and 36 nm thick, respectively. The space between the
source and drain (LSD) is 10 µm.
Fig. 3. 5 × 5-µm2 AFM images of samples (a) A1, (b) A2, and (c) B, showing rms surface-roughness values of 0.40, 5.10, and 0.37 nm, respectively.
(primarily Si and O) at the interface and form a semi- growth temperature (600 °C) was used in this work to
insulating (SI) buffer layer.18) However, in this work, we facilitate the Ge incorporation into the film.
employed an alternative method. The effect of Ga-polishing Next, circular capacitors 50 µm in diameter and transistor
on cleaning the growth surface was investigated. For this patterns were fabricated on the samples. Inductively coupled
purpose, we exposed the substrate to a Ga beam equivalent plasma etching was performed for 1 h using BCl3 to achieve
pressure (BEP) of 1.1 × 107 Torr for 30 min at a substrate mesa isolation.20) Ti=Au (20=100 nm) ohmic contacts were
temperature of 800 °C prior to the growth. deposited via e-beam evaporation and annealed at 500 °C
To study the effect of Ga-polishing on the surface in N2 for 1 min. Then, 5 nm of Al2O3 was deposited using
morphology and the unintentional incorporated Si at the atomic layer deposition as the gate dielectric, followed by the
growth interface, identical structures were grown on the two deposition of 30=500-nm-thick Ti=Au via e-beam evapora-
samples A1 and A2. Samples A1 and B were subject to a tion for the gate metal.
Ga-polishing step prior to growth, whereas for A2, this step The Al content in the (AlxGa1−x)2O3 barrier for all three
was skipped. For sample A2, the growth was initiated by an samples was measured to be ∼8% using the XRD ω–2θ
activated oxygen flux treatment to polish the surface as triple-axis profile along the 020 direction, as shown in Fig. 2.
explained in our previous work.18) For samples A1 and B, The AFM image of the samples shown in Fig. 3 reveals
the O2-polishing was performed after the Ga-polishing step. that for samples A1 and B, where the growth was initiated
After the pre-treatments, the substrate temperature was by Ga-polishing, the surface was smooth, with root-mean-
decreased to 600 °C for all three samples, and a 300-nm- square (rms) surface-roughness values of 0.4 and 0.37 nm,
thick Ga2O3 film was grown in the slightly Ga-rich growth respectively. In contrast, for sample B, the Ga-polishing was
regime (as explained elsewhere17)) using an oxygen foreline skipped, and the surface appeared very rough (rms roughness
pressure of 60 Torr and an RF plasma power of 200 W. This of >5 nm), with large surface defects. Furthermore, the SIMS
was followed by the deposition of a 7-nm-thick undoped profiles for these samples (Fig. 4) show that the Ga-polishing
(AlxGa1−x)2O3 film on all the samples using an Al BEP of was very effective, reducing the unintentionally incorporated
7 × 10−9 Torr. As previously mentioned, samples A1 and A2 Si and Ge at the growth interface by a factor of 5. We predict
had identical epi-structures, with a 16-nm-thick Ge-doped that it is possible to entirely eliminate these impurities at
(AlxGa1−x)2O3 layer (x1) and a 27-nm-thick unintentionally the interface by optimizing the Ga-pretreatment conditions.
doped (UID) (AlxGa1−x)2O3 cap layer (x2). For sample B, According to our previous work (unpublished), we believe
x1 = 7 nm, and x2 = 36 nm. The Ge concentration was chosen that the exposure of the β-Ga2O3 substrate to Ga flux in the
to be 1 × 1019 cm−3 for all three samples. The total thickness absence of activated O results in the etching of the film,
of the (AlxGa1−x)2O3 layer was 50 nm for all three samples. reducing the accumulated Si at the growth interface. The
Notably, although the optimized growth temperature for exact etch rate for this specific conditions is currently under
(AlxGa1−x)2O3 was between 650 and 700 °C,15) a lower investigation and will be reported in a separate paper.
071101-2 © 2017 The Japan Society of Applied Physics
Appl. Phys. Express 10, 071101 (2017) E. Ahmadi et al.
(a)
Fig. 6. DC output (ID vs VDS) and transfer (ID and gm vs VGS) characteristics of samples (a) A1, (b) A2, and (c) B.
Table I. Summary of epi-structures and transistor characteristics of Facilities Network, under Award No. DMR 1121053. A portion of this work was
samples A1, A2, and B. performed in the UCSB Nanofabrication Facility, which is part of the NSF-funded
National Nanotechnology Infrastructure Network.
Barrier structure VP ID,max Gm,max
Sample Ga-polishing
(nm) (V) (mA=mm) (mS=mm)
A1 x1 = 16, x2 = 27 Yes −6 20 4
1) M. Higashiwaki, K. Sasaki, A. Kuramata, T. Masui, and S. Yamakoshi,
A2 x1 = 16, x2 = 27 No −10 10 1 Appl. Phys. Lett. 100, 013504 (2012).
B x1 = 7, x2 = 36 Yes −2.5 1.4 0.7 2) M. Higashiwaki, K. Konishi, K. Sasaki, K. Goto, K. Nomura, Q. T. Thieu,
R. Togashi, H. Murakami, Y. Kumagai, B. Monemar, A. Koukitu, A.
Kuramata, and S. Yamakoshi, Appl. Phys. Lett. 108, 133503 (2016).
3) M. Higashiwaki, K. Sasaki, T. Kamimura, M. H. Wong, D. Krishnamurthy,
plotted as a function of the drain voltage (VD) on a linear A. Kuramata, T. Masui, and S. Yamakoshi, Appl. Phys. Lett. 103, 123511
scale for all three samples. A maximum ID and Gm of 20 (2013).
4) M. Mohamed, K. Irmscher, C. Janowitz, Z. Galazka, R. Manzke, and R.
mA=mm and 5 mS=mm, respectively, were measured for
Fornari, Appl. Phys. Lett. 101, 132106 (2012).
sample A1. The transistor characteristics were limited by the 5) M. Higashiwaki, K. Sasaki, H. Murakami, Y. Kumagai, A. Koukitu, A.
ohmic contacts, which were by no means optimized in these Kuramata, T. Masui, and S. Yamakoshi, Semicond. Sci. Technol. 31,
devices. Thus, the extraction of the sheet resistance and the 034001 (2016).
6) H. Aida, K. Nishiguchi, H. Takeda, N. Aota, K. Sunakawa, and Y. Yaguchi,
electron mobility from the transmission line method (TLM) Jpn. J. Appl. Phys. 47, 8506 (2008).
measurement was not possible. We are currently improving 7) N. Ueda, H. Hosono, R. Waseda, and H. Kawazoe, Appl. Phys. Lett. 70,
our ohmic-contact process to achieve far higher output 3561 (1997).
currents. This is part of our ongoing studies. 8) Y. Tomm, P. Reiche, D. Klimm, and T. Fukuda, J. Cryst. Growth 220, 510
(2000).
A very low gate leakage due to the insulated gate approach 9) M. H. Wong, K. Sasaki, A. Kuramata, S. Yamakoshi, and M. Higashiwaki,
allowed us to measure the current at the forward gate IEEE Electron Device Lett. 37, 212 (2016).
voltages. An ION=IOFF ratio of >9 orders of magnitude 10) M. Higashiwaki, K. Sasaki, K. Goto, K. Nomura, Q. T. Thieu, R. Togashi,
was measured on all the samples. Pinch-off voltages of −6, H. Murakami, Y. Kumagai, B. Monemar, A. Koukitu, A. Kuramata, and S.
Yamakoshi, IEEE 73rd Annu. Device Research Conf., 2015, p. 29.
−10, and −2.5 V were measured on samples A1, A2, and B, 11) K. D. Chabak, N. Moser, A. J. Green, D. E. Walker, S. E. Tetlak, E. Heller,
respectively. The larger pinch-off voltage for sample A2 A. Crespo, R. Fitch, J. P. McCandless, K. Leedy, M. Baldini, G. Wagner,
compared with sample A1 was most probably due to the Z. Galazka, X. Li, and G. Jessen, Appl. Phys. Lett. 109, 213501 (2016).
larger Si concentration at the growth interface on this sample. 12) M. H. Wong, Y. Nakata, A. Kuramata, S. Yamakoshi, and M. Higashiwaki,
Appl. Phys. Express 10, 041101 (2017).
A summary of the epi-structures and transistor character- 13) R. Dingle, H. L. Störmer, A. C. Gossard, and W. Wiegmann, Appl. Phys.
izations are reported in Table I for all three samples. Lett. 33, 665 (1978).
In summary, modulation doping field-effect transistors 14) T. Oshima, Y. Kato, N. Kawano, A. Kuramata, S. Yamakoshi, S. Fujita, T.
Oishi, and M. Kasu, Appl. Phys. Express 10, 035701 (2017).
were fabricated on β-(AlxGa1−x)2O3=β-Ga2O3(010) hetero-
15) S. W. Kaun, F. Wu, and J. S. Speck, J. Vac. Sci. Technol. A 33, 041508
structures grown via PAMBE using Ge as an n-type dopant. (2015).
A maximum current of 20 mA=mm was achieved with a 16) Y. Oshima, E. Ahmadi, S. C. Badescu, F. Wu, and J. S. Speck, Appl. Phys.
pinch-off voltage of −6 V. Ga-polishing was demonstrated Express 9, 061102 (2016).
17) E. Ahmadi, Y. Oshima, F. Wu, and J. S. Speck, Semicond. Sci. Technol. 32,
to be an effective approach for reducing the Si incorporation 035004 (2017).
at the growth interface by at least a factor of 5. 18) E. Ahmadi, O. S. Koksaldi, S. W. Kaun, Y. Oshima, D. B. Short, U. K.
Acknowledgments The authors thank Dr. Gregg Jessen for providing the Mishra, and J. S. Speck, Appl. Phys. Express 10, 041102 (2017).
β-Ga2O3 substrates. This work was supported by the Air Force Office of Scientific 19) M. H. Wong, K. Sasaki, A. Kuramata, S. Yamakoshi, and M. Higashiwaki,
Research (AFOSR, Program Manager Dr Ali Sayir) through grant number Jpn. J. Appl. Phys. 55, 1202B9 (2016).
FA9550-14-1-0112. This study made use of the central facilities supported by the 20) J. E. Hogan, S. W. Kaun, E. Ahmadi, Y. Oshima, and J. S. Speck,
NSF MRSEC Program, which is a member of the NSF-funded Materials Research Semicond. Sci. Technol. 31, 065006 (2016).