Online Extra Concepts Reading:

A set of Verilog statements are usually executed sequentially in a simulation. These statements
are placed inside a procedural block. There are mainly two types of procedural blocks in Verilog
- initial and always.

An initial block is not synthesizable and hence cannot be converted into a hardware schematic
with digital elements. Hence initial blocks do not serve much purpose than to be used in
simulations. These blocks are primarily used to initialize variables and drive design ports with
specific values.

All initial block runs in parallel.

$finish is used to kill current simulation.

Each initial block executed once per simulation. While always block run continuously during
simulation (always clk=! clk; //It is an infinite loop.)

Always block is synthesizable except in following situation:

 For example, mixed sensitive list of signals and edges is not synthesizable, because a
flip-flop cannot be edge-tiggered and level-triggered at the same time.

 More than two clocks are not synthesizable.

 Embedded always blocks are not synthesizable.

 Adding timing delays would not be synthesisable, but often used in verification. Also
some tools will complain if you try to synthesise display statements.

Port Mapping for Module Instantiation in Verilog

Order of ports in instantiation of DFF1 and DFF2 is same as order of ports in DFF.
Order of ports in instantiation of DFF1 and DFF2 is different from order of ports in DFF.

Lecture 1:

Resources:

https://verificationguide.com/

https://www.chipverify.com/

http://verificationexcellence.in/online-courses/

http://www.sunburst-design.com/papers/
X in IF statement will always consider as false, hence output will be Inpu2; other than X and 0 all
will be true in IF statement.

In ternary operator, it will look at both inputs, if both the inputs are different than X will be
output, if both the inputs are same than output will be same as input.
Negate (!): 01 is considered as true, hence ! 01 will be false.

Invert (~): But invert 01 , invert each bit, hence ~ 01 will be 10, which is 2 i.e true.

Order also affect synthesis. (blocking also synthesized to a flop)

The Clk is available than do rst it is synchronous rst. Synchronous

Latch -> Level sensitive

Flip Flop -> Edge triggered.
Modeling latch, make d part of sensitivity list so any change in d will become output when clk is
high, hence a latch is modeled.
Four state values mean 0,1,x,z.

0->Z considered as posedge as Z may settle in 0 or 1, if settle to zero than no change, if settle to
1 than it is posedge, this is how logically language define posedge and negedge.
Lecture 2:

 The int type was introduced as a part of the SystemVerilog extension. However, the key
difference between the integer and int types is that the int type uses only 2 states (o/1).
Verilog has two data type.

Net: Nets are used to connect between hardware entities like logic gates and
hence do not store any value on its own.
e.g. wire .

Variable: It can store the value. e.g. reg, integer, bit.

Continuous assignment (RHS continuously evaluated and value assigned to LHS.)

not allowed on variable type in Verilog. i.e left cannot be variable type it need to
be net type. While in SV it is not compilation error.

***Reg is procedurally assigned (assignment inside initial/always block.).

***Net means continuously driven.

*Logic in SV act as variable and wire.

 In the above slide q1 is both structurally driven(assign) and procedurally driven(initial),
such mixed drive is not allowed in system Verilog.

Above example is of write-write race, depending upon the compiler out may be 0 or 1 i.e
whichever is executed first.
 In above example a is of wire type and both trying to drive a with different value, in such
cases output will be x. It is not race.

logic variable cannot be drive by mixed I.e., structural, procedural drive, primitive drive, driven
by module any of the two at the same time but both can be drive procedurally.
Reg—Verilog/SV
Logic---SV
(RS: As no resolution exist, to prevent you from wasting time.)
Packed allowed complete access in oneshot, also individual array element can be access
individual array element. As element are begin stored side by side in memory.

**Try to read big Indian little Indian for & 7:0 and 0:7.
%P to print complete contain at one go in array, structure, enum.
Packed and unpacked structure are synthesizable.

Real, short real, not synthesizable.

Writing to one member and reading from other , result in garbadge collection.
Un.i is garbadge value.unpacked union are not synthesizable while packed can be.
Method to avoid accidental read. To track what member last member. To track automatically
language, define tagged
Packed union must be same size.
Eg use case for struct, easy to pass parameter from one design to other.

Read .* intantiation of module.

Choose union in this sanraio(as we using only one header or load at a time.):
ADV:
only one 32 ports in synthesis. (If use struct then payload, header will have separate ports).
Memory efficient.
Default vaule of variable type get printed if index is out of bound.
New stuff.

New stuff comapir to Verilog, esily maintainable, as for automatically change if size of array
changes.

** read if wire can be used inside intial block, always block.

*Read static and dynamic data types. All data types are static except string type, please read on
it. Dynamic array, associative arra, class are dynamic.
D1=new[8], vanishes the old data and create new array with 8 rows each with one element, if
we kept d1 than old data will ekpt as it is and new added element will be having default f\value.
Associative arry allow arbitrary index,

Here size is 2, not 5 as of dynamic array.

Before writing in associative array please check first if that index exist, if exist than we can’t
write in that index.
First and next method return true or false. K get index value.
Ques give error if size exceed 256, this error facility not available for dynamic , associative array.
After inserting index readjusted.
Please observe the index adjustment.

Not allowed to use string, unpacked array, in packed structure.

https://www.edaplayground.com/x/VfSh

To see waveform , please add four lines in test bench.

https://www.edaplayground.com/x/4xCG
https://www.edaplayground.com/x/vmZz

I am getting run time error, source and destination type is mismatched while filling a vector
with all 1. I tried for 0, x,z similar error has observed.
Infinite loop: simulation hang occurs, because control hangs at that point it won’t allow other
parallel task to get execute, hence always use delay inside infinite loop.
Break --- control will go end of while loop, stop executing loop.

Continue---- skip remaining statement in the loop and start the loop execution again.
 $urandom ----- generate unsigned random values.

 $random ----- generate signed and unsigned values.

Chop the 32-bit len, into 8 bit parts and store it into pack.
Take 8 bit from pack , and arrange in len_upacka, upacking.
First operation is packing.
***Try to use $display, in every method to see the progress.
Lecture 3:

No facility in Verilog to tell intention of user to synthesis tool.

Isuue due to missing signal in sensitivity list:

In general thumb rule for adding sensitivity list --- > signals that u are reading or sampling.
Driving--- use this word for output port connected to wire, and in procedural assignment i.e. in
assign statement.

Verilog will not issue any error for such scenario (i.e. if use always *). But with always_comb
issue compiler error.

At time zero:

First time control come to always block it note down the values of signals which are part of
sensitivity list and goes to waiting mode (actvating always block available at 0).

(It is behavior of language--- at time 0 control first go to always, note down value of sensitivity
list and goes to waiting mode.) i.e. logically to see changes on sensitivity list it must need first
note value of sensitivity list hence languge maje control goes to always make it on wait state.

Control goes to initial block

Inp1 and inp2 goes to zero.

Than delay

So at time zero always is waiting control goes to always block, than always executed and
always note down new value of inp1 and inp2.

Now time reached to 10.

See always changing between waiting and ready mode:
Normal always block no behaving like combinational ckt.

In simulation parallelism mean--- do one task if it goes to wai than it moves to other task in
same time. (i.e task getting switched e.g between initial always).
Start initial block first. Both always initial goes in waiting ,

Those always com which not executed in time 0, executed once in time 0 , irrespective of
change in selectivity list to mimic exact rela combo behavor. (genral always block mimicking
combo after time zero and not behaving like combo only at time zero.)
How to solve time zero initialization in evrilog,, apply stimulus in <=.
Always_latch also executed once in time zero iirrespective there sensitivity list changed or not.

with always ff it checks no one uses LHS.

No delay , time control in final block. It is procedural block executed at the end of simulation to
print.

Array element accessed individually. While vector intire at once.

Bit(0,1) and reg(0,1,x,z), byte are 32 bit.

Programm block as it i

Solve port connection problem

Adding deleting signal becomes easy.

Topic 9:

Why at time 5, d=1 and q2=0? Even if q1 is directly connected to D of second flop.

Clk appearing simultaneously at each flop, hence it samples whatever valve available at q1 i.e 0
hence 0 at q2. (as flop executing in parallel)
At T5 Q1=1 Q2= 0 Q3=0.

When clk and data available at same time flop sample old value to mimic rela hardware
behaviors.

If executed as describe above than behavior is wrong(q2=1).

Reading and updating of Q1 happning at same time which is causing the issue, if we read old
value and update latter than behvaiour will be correct hence language introduces non blocking
assignement i.e to read old value.
Model sequential using blocking, so that it sample old value to mimic rela hardware behaviors.

Rate at which input arrive at combo input is clk frequency of combo.

Time 1
Time 5

Let RTL executed first

Now consoder second order TB thread executed first at T5
This order is not producing expected hardware behavour.
***Use non-blocking operator when u drive input into RTL.

IF RTL executed thread executed first than issue will also resolves (first case.)

Topic 10
Code from program end program as part of “Re”.

Prepond nd postpond are read only region.

Use program block to avoid races use of program block make RTL thread to execute first , you
can use non-blocking in module to avoid races.
Now see effect pf moving clk in program block.
Now posedge happen,
1)control move from re-active to active.
2) TB thread executed first than move to RTL.

Above two chances are possible in SV language. Hence clk generation must not be part of
program block it needs to be done in top module.

(RTL executed first than bachh gaya else mar gaya)