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16 Mbit (2Mb x8 or 1Mb x16) UV EPROM and OTP EPROM: Description Figure 1. Logic Diagram
16 Mbit (2Mb x8 or 1Mb x16) UV EPROM and OTP EPROM: Description Figure 1. Logic Diagram
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h 1
DESCRIPTION
The M27C160 is a 16 Mbit EPROM offered in the
two ranges UV (ultra violet erase) and OTP (one Figure 1. Logic Diagram
time programmable). It is ideally suited for micro-
processor systems requiring large data or program
storage and is organised as either 2 Mbit words of
8 bit or 1 Mbit words of 16 bit. The pin-out is com-
patible with a 16 Mbit Mask ROM. VCC
The FDIP42W (window ceramic frit-seal package)
has a transparent lid which allows the user to ex-
pose the chip to ultraviolet light to erase the bit pat- 20
tern. Q15A–1
A0-A19
15
Table 1. Signal Names Q0-Q14
A0-A19 Address Inputs E M27C160
Q0-Q7 Data Outputs G
Q8-Q14 Data Outputs
BYTEVPP
Q15A–1 Data Output / Address Input
E Chip Enable
G Output Enable
VSS
AI00739B
BYTEVPP Byte Mode / Program Supply
VSS Ground
Figure 2A. DIP Pin Connections Figure 2B. PLCC Pin Connections
A18 1 42 A19
A17 2 41 A8
A7 3 40 A9
VSS
A17
A18
A19
A10
A11
A5
A6
A7
A8
A9
A6 4 39 A10
A5 5 38 A11
1 44
A4 6 37 A12 A4 A12
A3 7 36 A13 A3 A13
A2 8 35 A14 A2 A14
A1 9 34 A15 A1 A15
A0 10 33 A16 A0 A16
M27C160
E 11 32 BYTEVPP E 12 M27C160 34 BYTEVPP
VSS 12 31 VSS VSS VSS
G 13 30 Q15A-1 G Q15A–1
Q0 14 29 Q7 Q0 Q7
Q8 15 28 Q14 Q8 Q14
Q1 16 27 Q6 Q1 Q6
Q9 17 26 Q13 23
Q2 18 25 Q5
Q10
Q11
Q12
Q13
NC
VCC
Q9
Q2
Q3
Q4
Q5
Q10 19 24 Q12
Q3 20 23 Q4 AI03012
Q11 21 22 VCC
AI00740
Figure 2C. SO Pin Connections A new pattern can then be written rapidly to the de-
vice by following the programming procedure.
For applications where the content is programmed
NC 1 44 NC only one time and erasure is not required, the
A18 2 43 A19 M27C160 is offered in PDIP42, PLCC44 and
A17 3 42 A8 SO44 packages.
A7 4 41 A9
A6 5 40 A10 DEVICE OPERATION
A5 6 39 A11 The operating modes of the M27C160 are listed in
A4 7 38 A12 the Operating Modes Table. A single power supply
A3 8 37 A13 is required in the read mode. All inputs are TTL
A2 9 36 A14
compatible except for VPP and 12V on A9 for the
Electronic Signature.
A1 10 35 A15
A0 11 34 A16 Read Mode
M27C160
E 12 33 BYTEVPP The M27C160 has two organisations, Word-wide
VSS 13 32 VSS and Byte-wide. The organisation is selected by the
G 14 31 Q15A-1 signal level on the BYTEVPP pin. When BYTEVPP
Q0 15 30 Q7 is at VIH the Word-wide organisation is selected
Q8 16 29 Q14
and the Q15A–1 pin is used for Q15 Data Output.
When the BYTEVPP pin is at VIL the Byte-wide or-
Q1 17 28 Q6
ganisation is selected and the Q15A–1 pin is used
Q9 18 27 Q13
for the Address Input A–1. When the memory is
Q2 19 26 Q5 logically regarded as 16 bit wide, but read in the
Q10 20 25 Q12 Byte-wide organisation, then with A–1 at VIL the
Q3 21 24 Q4 lower 8 bits of the 16 bit data are selected and with
Q11 22 23 VCC A–1 at VIH the upper 8 bits of the 16 bit data are
AI01264 selected.
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M27C160
Read Word-wide VIL VIL V IH X Data Out Data Out Data Out
Read Byte-wide Upper VIL VIL VIL X Data Out Hi-Z VIH
The M27C160 has two control functions, both of the output pins independent of device selection.
which must be logically active in order to obtain Assuming that the addresses are stable, the ad-
data at the outputs. In addition the Word-wide or dress access time (tAVQV) is equal to the delay
Byte- wide organisation must be selected. from E to output (tELQV). Data is available at the
Chip Enable (E) is the power control and should be output after a delay of tGLQV from the falling edge
used for device selection. Output Enable (G) is the of G, assuming that E has been low and the ad-
output control and should be used to gate data to dresses have been stable for at least tAVQV-tGLQV.
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M27C160
1.3V
High Speed
1N914
3V
1.5V
0V 3.3kΩ
DEVICE
Standard UNDER OUT
TEST
2.4V CL
2.0V
0.8V
0.4V
CL = 30pF for High Speed
AI01822
CL = 100pF for Standard
CL includes JIG capacitance AI01823B
4/16
M27C160
E = VIL, G = VIL,
70 mA
IOUT = 0mA, f = 8MHz
ICC Supply Current
E = VIL, G = VIL,
50 mA
IOUT = 0mA, f = 5MHz
5/16
M27C160
Symbol Alt Parameter Test Condition -70 (3) -90 -100 -120/-150 Unit
BYTE Low to
tBLQX tOH E = VIL, G = VIL 5 5 5 5 ns
Output Transition
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP
2. Sampled only, not 100% tested.
3. Speed obtained with High Speed Measurement Conditions and VCC = 5V ± 5%.
tAVQV tAXQX
tEHQZ
tGLQV
tELQV tGHQZ
Hi-Z
Q0-Q15
AI00741B
6/16
M27C160
tAVQV tAXQX
tEHQZ
tGLQV
tELQV tGHQZ
Hi-Z
Q0-Q7
AI00742B
A0-A19 VALID
A–1 VALID
tAVQV tAXQX
BYTEVPP
tBHQV
tBLQX
Hi-Z
Q8-Q15 DATA OUT
tBLQZ
AI00743C
7/16
M27C160
8/16
M27C160
A0-A19 VALID
tAVEL
tQVEL tEHQX
BYTEVPP
tVCHAV tGHAX
tELEH tQXGL
PROGRAM VERIFY
AI00744
9/16
M27C160
10/16
M27C160
Device Type
Speed
-70 (1,2) = 70 ns
-90 = 90 ns
-100 = 100 ns
-120 = 120 ns
-150 = 150 ns
V CC Tolerance
blank = ± 10%
X = ± 5%
Package
F = FDIP42W
B = PDIP42
K = PLCC44 (3)
M = SO44
Temperature Range
1 = –0 to 70 °C
6 = –40 to 85 °C
Optio ns
TR =Tape & Reel Packing
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the ST Sales Office nearest to you.
11/16
M27C160
Table 12. FDIP42W - 42 pin Ceramic Frit-seal DIP, with window, Package Mechanical Data
mm inches
Symb
Typ Min Max Typ Min Max
A 5.72 0.225
A1 0.51 1.40 0.020 0.055
A2 3.91 4.57 0.154 0.180
A3 3.89 4.50 0.153 0.177
B 0.41 0.56 0.016 0.022
B1 1.45 – – 0.057 – –
C 0.23 0.30 0.009 0.012
D 54.41 54.86 2.142 2.160
D2 50.80 – – 2.000 – –
E 15.24 – – 0.600 – –
E1 14.50 14.90 0.571 0.587
e 2.54 – – 0.100 – –
eA 14.99 – – 0.590 – –
eB 16.18 18.03 0.637 0.710
L 3.18 0.125
S 1.52 2.49 0.060 0.098
K 9.40 – – 0.370 – –
K1 11.43 – – 0.450 – –
α 4° 11° 4° 11°
N 42 42
Figure 10. FDIP42W - 42 pin Ceramic Frit-seal DIP, with window, Package Outline
A2 A3 A
A1 L α
B1 B e1 C
eA
D2
eB
D
S
N
K E1 E
1 K1
FDIPW-b
12/16
M27C160
Table 13. PDIP42 - 42 pin Plastic Dual In Line, 600 mils width, Package Mechanical Data
mm inches
Symb
Typ Min Max Typ Min Max
A – 5.08 – 0.200
A1 0.25 – 0.010 –
A2 3.56 4.06 0.140 0.160
B 0.38 0.53 0.015 0.021
B1 1.27 1.65 0.050 0.065
C 0.20 0.36 0.008 0.014
D 52.20 52.71 2.055 2.075
D2 50.80 – – 2.000 – –
E 15.24 – – 0.600 – –
E1 13.59 13.84 0.535 0.545
e1 2.54 – – 0.100 – –
eA 14.99 – – 0.590 – –
eB 15.24 17.78 0.600 0.700
L 3.18 3.43 0.125 0.135
S 0.86 1.37 0.034 0.054
α 0° 10° 0° 10°
N 42 42
Figure 11. PDIP42 - 42 pin Plastic Dual In Line, 600 mils width, Package Outline
A2 A
A1 L α
B1 B e1 C
eA
D2 eB
D
S
N
E1 E
1
PDIP
13/16
M27C160
Table 14. PLCC44 - 44 lead Plastic Leaded Chip Carrier, square, Package Mechanical Data
mm inches
Symb
Typ Min Max Typ Min Max
D A1
D1 A2
1 N
B1
e
Ne E1 E F D2/E2
B
0.51 (.020)
1.14 (.045)
Nd A
R CP
PLCC
14/16
M27C160
Table 15. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data
mm inches
Symb
Typ Min Max Typ Min Max
e 1.27 – – 0.050 – –
H 15.90 16.10 0.626 0.634
L 0.80 – – 0.031 – –
α 3° – – 3° – –
N 44 44
CP 0.10 0.004
Figure 13. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Outline
A2 A
C
B
e CP
E H
1
A1 α L
SO-b
15/16
M27C160
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in lif e support devices or systems without express written approval of STMicroelectronics.
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