1. A nMOS transistor is to be fabricated.

Describe its fabrication steps giving the Mask

sequence. sketch the cross-sectional view of all masking steps
2. Compare Ion implantation & Diffusion
3. Explain the complete fabrication process steps for a CMOS Inverter using n-well process
with the help of cross-sectional diagrams for all important masking steps
4. A reference inverter has (W/L) N= 1/1 & (W/L)P =3/1. Draw the schematic & stick diagram
of two input NAND gate & calculate (W/L) ratio of transistor based on reference inverter
design
5. Explain the complete fabrication process steps for a CMOS Inverter using p-well process
with the help of cross-sectional diagrams for all important masking steps
6. Implement 2:1 Multiplexer circuit using CMOS Transmission gate
7. State different Design style for CMOS Design.
8. Compare Static and Dynamic Design.
9. Explain Pseudo nMOS Design and its advantages
10. Explain working of C2MOS Design Style
11. Explain the Domino Logic Implementation with respect to Pre-charge and Evaluation
phase
12. Significance of demarcation line in case of CMOS stick diagram
13. Implement following function also draw the stick diagram TINY XOR gate (A XOR B OR
A’B+AB’)
14. Using Transmission gates devices design 4:1 MUX
15. Implement following function also draw the stick diagram: F= X + Y Z
16. Explain The ROM Array and how it can be modified as Flash ROM/EPROM
17. Explain Fowler-Nordheim (F-N) tunnel model, the device used in non-volatile Flash
memory
18. Draw the Schematic of 6 - transistor SRAM cell also the stick diagram for the same
19. How the SR latch is implemented using MOS devices?
20. Explain the Need & Effect of scaling.
21. State the need and significance of Design Rules.
22. Compare SRAM cell with that of DRAM Cell
23. Explain the implementation and working of a DRAM Cell
1. A nMOS transistor is to be fabricated. Describe its fabrication steps giving the
Mask sequence. sketch the cross-sectional view of all masking steps

Step 1: doping with p-type impurities

 fabrication process is carried out on a thin wafer cut from a single crystal of silicon
available in its purest form.
 this wafer which is typically 75 to 150 um in diameter and 0.4 um thick is doped with p
type impurities (Eg., boron) during the process of crystal growth

Step 2: oxidation – growth of thick SiO2 layer

 a thick silicon dioxide (SiO2) layer of 1 um thickness is grown over the surface of the
wafer, this process is called oxidation
 this silicon dioxide layer acts as an excellent insulator onto which other layers are
deposited and patterned
 It also protects the surface and acts as a barrier to dopants during fabrication process

Step 3: Lithography
 the wafer is coated with a light sensitive material called photoresist and the wafer is
spun to achieve a uniform distribution of the required thickness.

Step 4: masking

 the centre part of the photoresist layer is shielded while the other parts are exposed to
UV light which makes it polymerized (i.e., makes that area hard).
 the areas which was shielded by the mask remain unaffected.

Step 5: etching
 un-polymerized regions which are soft are then etched so that the wafer surface gets
exposed in the pattern defined by the mask.
 The remaining photoresist is also removed by the hot sulphuric acid.
 Step 6: growing thin oxide layer
 a thin layer of silicon dioxide (SiO2) of 0.1 um thickness is grown over the entire surface
 a layer of heavily doped polysilicon is deposited on the top of SiO2 using chemical
vapour deposition technique.
 This forms the gate structure.

Step 7: Lithography, masking and etching

 After deposition of the polysilicon, again the process of lithography, masking and
etching is done to define the gate structure.

Step 8: Diffusion
 The polymerized photoresist is removed to expose those areas where the n-type
impurities are diffused to form the source and drain.
 Diffusion is achieved by heating the wafer to a high temperature and passing a gas
containing the desired n-type impurity.

Step 9: Lithography, masking and etching

 again the process of lithography, masking and etching is done to define the gate, drain
and source areas where the actual electrical connections will be made.

Step 10: metallization

 Finally, aluminium is deposited over the chip with a thickness of 1 um.
 this metal layer is then masked and etched to form the required electrical connections.

Video link: https://www.youtube.com/watch?v=z6aaFYESgEw

2. Compare Ion implantation & Diffusion

Ion implantation Diffusion

It is a process used to change the chemical Diffusion is the motion of impurities inside a
and physical properties of a material, substance

Done at low temperature. Done at high temperature.

Amount of dopant can be controlled Amount of dopant cannot be controlled

It is expensive It is cheap.

It may damage the surface of the target It will never damage the surface of the target

Both batch and single wafer process Only batch process

An-isotropic dopant profile. Isotropic dopant profile.

3. Explain the complete fabrication process steps for a CMOS
Inverter using n-well process with the help of cross-sectional
diagrams for all important masking steps

Step 1: doping with p-type impurities

 For N- well CMOS, a P-type silicon substrate is used.

Step 2: oxidation
 a thick silicon dioxide (SiO2) layer is grown over the surface of the wafer, this process is
called oxidation
 It also protects the surface of the wafer from contamination of the substrate during
fabrication process.

Step 3: Lithography
 the wafer is coated with photoresist (which is a light sensitive material)
 Then, the wafer is spun to achieve a uniform distribution of the required thickness.

Step 4: masking

 the desired part of the photoresist layer is shielded by the mask, while the other parts
are exposed to UV light which makes it polymerized (i.e., makes that area hard).
 the areas which was shielded by the mask remain unaffected.

Step 5: etching
 un-polymerized regions (which is soft) are then etched and removed so that the wafer
surface gets exposed.
 The remaining photoresist is also removed by the hot sulphuric acid.
Step 6: Formation of N-well and removal of SiO2 layer
 The n-type impurities are diffused into the p-type substrate through the exposed region,
thereby forming an N- well.
 The SiO2 layer is also removed.

Step 7: growing SiO2 and polysilicon layer

 A thin layer of SiO2 is again grown over the surface.
 Then, a layer of polysilicon is grown over the SiO2 layer using chemical deposition
process.

Step 8: Lithography, masking and etching

 Except the two regions needed for the formation of the gate, the remaining portion
again goes through the process of lithography, masking and etching is done.

Step 9: Diffusion
 The polymerized photoresist is removed and the exposed areas are diffused with p-type
and n-type impurities to form the terminals of PMOS and NMOS respectively.

Step 10: Laying of Thick SiO2 layer

 A thick SiO2 layer is grown over the surface to form a protective layer for the
regions of the wafer where no terminals are required.

Step 11: metallization

 Finally, aluminium is deposited over the chip.
 this metal layer is used to form the required electrical connections.
5. Explain the complete fabrication process steps for a CMOS
Inverter using p-well process with the help of cross-sectional
diagrams for all important masking steps

Step 1: doping with p-type impurities

 For P- well CMOS, a N-type silicon substrate is used.

Step 2: oxidation
 a thick silicon dioxide (SiO2) layer is grown over the surface of the wafer, this process is
called oxidation
 It also protects the surface of the wafer from contamination of the substrate during
fabrication process.

Step 3: Lithography
 the wafer is coated with photoresist and then the wafer is spun to achieve a uniform
distribution of the required thickness.

Step 4: masking

 the desired part of the photoresist layer is shielded by the mask, while the other parts
are exposed to UV light which makes it polymerized (i.e., makes that area hard).
 the areas which was shielded by the mask remain unaffected.

Step 5: etching
 un-polymerized regions are then etched and removed so that the wafer surface gets
exposed.
 The remaining photoresist is also removed by the hot sulphuric acid.

Step 6: Formation of P-well and removal of SiO2 layer

 The p-type impurities are diffused into the n-type substrate through the exposed region,
thereby forming an P- well.
  The SiO2 layer is also removed.

Step 7: growing SiO2 and polysilicon layer

 A thin layer of SiO2 is again grown over the surface.
 Then, a layer of polysilicon is grown over the SiO2 layer using chemical deposition
process.

Step 8: Lithography, masking and etching

 Except the two regions needed for the formation of the gate, the remaining portion
again goes through the process of lithography, masking and etching is done.

Step 9: Diffusion
 The polymerized photoresist is removed and the exposed areas are diffused with p-type
and n-type impurities to form the terminals of PMOS and NMOS respectively.

Step 10: Laying of Thick SiO2 layer

 A thick SiO2 layer is grown over the surface to form a protective layer for the
regions of the wafer where no terminals are required.

Step 11: metallization

 Finally, aluminium is deposited over the chip.
 this metal layer is used to form the required electrical connections.

NOTE: in the diagram, just change: P-substrate  N-substrate & n-well  p-well
6. Implement 2:1 Multiplexer circuit using CMOS Transmission
gate
 When the control signal C is high, the upper transmission gate is ON and A is passed through
the output. Therefore, output = A
 When the control signal C is low, the lower transmission gate is turned ON and B is passed
through the output. Therefore, output = B. At that time upper transmission gate is OFF.

2:1 multiplexer using CMOS transmission gate

7. State different Design style for CMOS Design.

Different Design style for CMOS Design are:

1. Colouring the N and P transistor.
2. Having a demarcation line in monochrome diagrams. Above the demarcation line are the P
transistors and below the demarcation line are the N transistors.
8. Compare Static and Dynamic Design

Static Design Dynamic Design

nMOS = k nMOS = k+1

pMOS = k pMOS = 1

overall size is more overall size is less

due to more PMOS, capacitive loading is more. due to less PMOS, capacitive loading is less.

Noise immunity is more. Noise immunity is less

switching characteristics is slow switching characteristics is fast

There is no cascading issues There are some cascading issues

There is no need of pre-charge for operation There is a need of pre-charge for dynamic CMOS
operation.
 9. Explain Pseudo nMOS Design and its advantages

The inverter that uses a p-device pull-up or load that has its gate permanently ground. An n-
device pull-down or driver is driven with the input signal. This roughly equivalent to the use of
a depletion load is NMOS technology and is thus called ‘Pseudo-NMOS’.
The circuit is used in a variety of CMOS logic circuits. In this, PMOS for most of the time will be
linear region. So resistance is low and hence RC time constant is low. When the driver is
turned on a constant DC current flows in the circuit.

The CMOS pull-up network is replaced by a single pMOS transistor with its gate grounded. Since
the pMOS is not driven by signals, it is always ‘on'. The effective gate voltage seen by the pMOS
transistor is VDD. Thus the overvoltage on the p channel gate is always VDD−VTP. When the nMOS
is turned ‘on', a direct path between supply and ground exists and static power will be drawn.
However, the dynamic power is reduced due to lower capacitive loading.

The advantage of pseudo-NMOS logic is its high speed (especially, in large-fan-in NOR gates) and
low transistor count. On the negative side is the static power consumption of the pull-up transistor
as well as the reduced output voltage swing and gain, which makes the gate more susceptible to
noise. At a second glance, when pseudo-NMOS logic is combined with static CMOS in time-critical
signal paths only, the overall speed improvement can be substantial at the cost of only a slight
increase in static power consumption. Furthermore, when the gate of the pull-up transistor is
connected to an appropriate control signal it can be turned off, i.e., pseudo-NMOS supports a
power-down mode at no extra cost.
12. Significance of demarcation line in case of CMOS stick diagram

 In CMOS stick diagram, a demarcation line is drawn to separate N and P transistors.

 All P transistors lies above the demarcation line and all the N transistors lies below the
demarcation line.
14. Using Transmission gates devices design 4:1 MUX
16. Explain The ROM Array and how it can be modified as Flash
ROM/EPROM
ROM Array:
 ROM array is a simple Boolean network which produces a specified output for each
input combination.

 From the above diagram, only one row is activated at a time by turning its voltage to
high, while all other rows are turned to low level.
 If an active transistor exists at the cross point of a column and the selected row, the
column voltage is turned to logic-0 by that transistor.
 If no active transistor exists at the cross point, the column voltage is turned to logic-1 by
the PMOS load device.
 Below table shows the same:
18. Draw the Schematic of 6- transistor SRAM cell also the stick
diagram for the same
19. How the SR latch is implemented using MOS devices?
We need to develop a mechanism to trigger the latch in Figure 2 and make it change state. This is
achieved by the SR (set/reset) latch shown in Figure 3.
The SR latch is created by cross-coupling two NAND gates.
As we’ll discuss below, the SR latch allows us to store one bit of information.

To store a specific state, let’s say Q = logic 1 or Q̅ = logic 0 in the latch; we should apply appropriate
values to the S and R inputs in Figure 3.
Figure 3 shows the state of the inputs and output when S = logic 1 and R = logic 0, which sets the
latch output to the logic 1 state. The S terminal is the set, or preset, input. The latch is set when Q
= logic 1 and Q̅ = logic 0.
Choosing S = logic 0 and R = logic 1 enters a logic 0 into the memory. The R terminal is the reset or
clear input.
Table 1 shows the SR latch truth table.
20. Explain the Need & Effect of scaling.
Need:

1. To boost up the MOS technology, the packing density of MOSFETs should be as high as
possible.
2. In order to meet the demand of high density chips, the sized and dimensions of the
MOSFET are reduced or scaled down.

Effect:

 scaling of MOSFET transistor is about systematic reduction of overall dimension of

the device as much as possible by available technology.
 it increases the packaging density of the devices which is needed to fulfil the demand
of high density chips in MOS technology.
 A constant scaling factor ‘s’ is introduced A. The scaled (reduced) device is obtained
by dividing all horizontal and vertical dimensions of the large size device by this
scaling factor.
21. State the need and significance of Design Rules.

Need:
 To reduce manufacturing problems, design rules specifies certain restrictions to create a
reliable circuit on a small area and to ensure that most of the parts work correctly.
 Main terms in design rules are size, separation and overlap.

Design Rules are significant to solve below problems:

 Transistor problems: Variations in threshold voltage, Variations in substrate and Changes
in source/drain diffusion overlap.
 Wiring problems: Diffusion, variations in height & width resulting in variations in
resistance, capacitance.
 Oxide problems: Variations in height and lack of planarity
 Via problems: Undersize via has too much resistance and via may also be too large.
 22. Compare SRAM cell with that of DRAM Cell
SRAM DRAM

It is a type of RAM that stores data as long as It is a type of RAM that stores data for a very
power is supplied to the chip. If the power is lost, short time which is typically of about 4 msec.
the data will be lost forever.
It uses transistor to store data. It uses capacitors to store data.

It is expensive It is cheap

Manufacturing cost is high Manufacturing cost is low

Power consumption is low Power consumption is high

Memory capacity is less Memory capacity is more

Application - used in cache memories. Application - used in main memories.

23. Explain the implementation and working of a DRAM Cell

 DRAM consists of - transistor and capacitor.

 Transistor is used to charge or discharge the capacitor to put a bit in the memory.
 A charged capacitor is represented by logic 1 and a discharged capacitor is
represented by logic 0.
 Each DRAM cell has 2 lines - wordline and bitline. The charging/discharging of
capacitor is done using this wordline and bitline.
 During a read or write, the wordline goes high and the transistor connects the
capacitor to the bitline.
 Whatever value is on the bitline ('1' or '0') is either get stored or retrieved from the
capacitor.
 The charge stored on each capacitor is too small to be read directly, therefore it is
measured using a sense amplifier.
 The sense amplifier detects the minute differences in charge and gives an output the
corresponding to the logic level.