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-- Company:
-- Engineer:
--
-- Create Date: 13.11.2022 22:11:21
-- Design Name:
-- Module Name: div_clk - arch_div_clk
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity div_clk is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
clk_out_1 : out STD_LOGIC;
clk_out_2 : out STD_LOGIC);
end div_clk;

architecture arch_div_clk of div_clk is

signal compte : integer range 1 to n;
signal x :std_logic :=0;
begin
process(clk)
if (clk'event' and clk='1')then
if (comptee = n ) then
x<=not(x)
compte<=1;
else
compte<=compte+'1';
end if
end if
end process
clk_out<=x;
end arch_div_clk;
//////////////////////
entity 7_seg is
Port ( bcd : in STD_LOGIC_VECTOR(3 down to 0) ;
 c: out STD_LOGIC_VECTOR(6 down to 0));
end 7_seg;

architecture arch_7_seg of 7_seg is

begin
with (bcd) select
seg<="1000000" when"0000"
"1111001" when"0001"
"1011011" when"0010"
"0110000" when"0011"
"0011001" when"0100"
"0010010" when"0101"
"0000010" when"0110"
"0110000" when"0111"
"0000000" when"1000"
"0010000" when"1001"
"zzzzzzz" when"others";
end arch_7_seg;
/////////////////////////////////////////////////////////
entity mux is
Port ( sel,d,sh,sl,m: : in STD_LOGIC_VECTOR(3 down to 0) ;
bcd: out STD_LOGIC_VECTOR(3 down to 0));
end mux;
architecture arch_mux of mux is
begin
bcd<= d when (sel="1110")else

sl when (sel="1101")else
sh when (sel="1011")else
m;
end arch_mux
//////////////////////////////////////////////////////////
entity reg_bal is
Port ( clk: : in STD_LOGIC ;
sel: out STD_LOGIC_VECTOR(3 down to 0));
end reg_bal;
architecture arch_reg_bal of reg_bal is
signal reg:STD_LOGIC_VECTOR(3 down to 0):="1110";
begin
process(clk)
if (clk'event' and clk='1')then
reg<=reg(2 down to 0); !!(3)
end if
end process
sel<=reg
end arch_reg_bal
//////////////////////////////////////////
entity chrono is
Port ( clk,rst,st,ar: : in STD_LOGIC ;
m,sh,sl,d: out STD_LOGIC_VECTOR(3 down to 0));
end chrono;
///////////////////////////////////////////////////
architecture arch_chrono of chrono is
begin
process(rst,st,ar)
begin
if (rst='1') then ce='0';
else
if(st='1')then ce='1';
end if
end process
slkd<=clk when ce='1';
else'0'
process(clkd,rst)
begin
if(rst='1') then
d1<="1001";
if(d1="1001")then
d1<="0000";
clksl<=not(clksl)
else
d1<=d1+1
end if
end process
process(clksl,rst)
begin
if(rst='1') then
sl1<="0000";
elsif(clksl'event' and clksl='1')
then
if (sl1="1001")then
sl1<="0000";
clksh<not(clksh)
else sl1<=sl1+1;
end if
end if
end process
process(clksh,rst)
begin
if(rst='1')then
sh="0000"
elsif (clksh'event'andclksh='1')
then
if(sh1="0101")then
sh1<="0000";
clkm<=not(clkm)
else sh1<=sh1+1;
end if
end if
end process
process(clkm,rst)
begin
if(rst='1')then m<="0000")
elsif (clkm'event' and clkm='1')then
if (m1="1001") then
m1<="0000";
else
m1<=m1+1;
end if
end if
end process
m<=m1
sh<=sh1
sl<=sl1
d<=d1
end erch_chrono;