Hyderabad - 501 301. INDEX Date of Evaluation Record Name of Experiments © of | page| Observation book} Record with _|Viva voio 4 " Experiment with writeup — |results & Printouts|3 weeks 6) (8) ( 1 Basic Lvaic frotes |24lglo2 | 1-2 z.| olf ad } for} 3-4 x |Full Adsor s/a/rr | 5-6 u | g-3 Envodty 26 /alrr| 4-8 6 |2-¢ Decoder 26( grr] 4-10 ac Ie | ¢.|T -Fiip Flop tolio}22 ¢ + Bry S| Devauliple xr Is-16 a @ scanned with OKEN ScannerSNIST (An Autonomous Institution) ———NviSE AB EXPERIMENT : BASIL GATES Alia: Design jsirmulake , syntusiee & verify att furdamedel gate wing, verileg OL & juapliwat gu ART Ix FEP GA Apparodus: > Computin syshes 2) Vevileg MDL CvIVADo) tool 2) ALTIx-FF CGA Theory : Logic goku are beted on boolian alypbra » PRE ony ven mont, every Lermiual ts iu ove of boo leimary condi owt, false Qo gras Fabie represents ‘07 & dua 2epresed ‘Y. Bowte logic ged are BND, OR » NOT and the auiver Sed. logie gyi are NAND Noe. Procedure: Doper ViVvADE, chick on create project & specify prope 2) Te pape vravigator WI create O who project with given specifi codiont 3) Go to prpt manager UD Enter He program & save it vowtke test vend 5 90 to adh source Han scect om $00, Meck, on wot k creake a fie Bick on add sours & crecke file rand vworite Test bench prgra' AF4) (A1,02,07,04, 0S, 06, AF, bi, b2, ¥32 bu); ONprs 03,04, 05,06, a4; C266 Class I= _Rolt No, 2021!80U31 Academic Year 2022-23 Page No, il @ scanned with OKEN Scanner& Scanned with OKEN ScannerSNIST (An Autonomous Institution) LAB assign lewar, assiqu brs ar kaa; 3 : in asstgu b3= 241 aS; assiqu uz acrat; avd module Text lence Peon: module gtgi- tle; TED ON, A2AB, AUD AS Ab, AF; ‘i wire bl, b2,b3,b45 afg\ cut Carlar),.ar(ac), aaa), aulaus,-as(as) » sbi bi), ya Cbad,-b3 Cea), - ba (lud); aé(ad), arta) obtoiued aud. om logke gates Arutit %s walt vc verileg Hoe. The detiqu 96 How : PGA kik ond Go skaed Ampewanted an Neat EI Ges functionality %S verifrek B. Tech Branch __ECE @ scanned with OKEN Scannert = @ scanned with OKEN ScannerSNIST EXPE RIUENT - KALE Amnee Alar Te Sesign, simudate , verity aud symtlasize half ~ adder wasting verilog HOL & amploment ju ALTIX-ZEPGA ni 21) Com puter syste 2) VIVADO tool 4) ARTIK-7 FPGA Theor - ; wolf adder fs Oo combi rationed Crauth thet adds £ vols : & on off. Half coh of? vdhoked oud product a sum Wit awd carry bi adder is uch for Wit addition and legt oferatien na compat 3 5 A 4 oO D opew VIVARO, Beck on creake project & spec Hy Pes name Ay \ t project navigat? wilh cree a who errject wi 2) Te | eyon speciicakk ove > . ae " preick wanager dick om odd Sources & ertake BE) re +e fle A wens oe te program & save 1* gud. vovike test ben u) Ewter pepe” i sdhect adhe 6 rt \oench bo 5) To write tet 79 : & cyutiobon. Sours, Te ow vert ee evecthen o fe kick ow O% 6) Clicle ow ovkpud $405 assign $= oslo; we sak @ scanned with OKEN Scannerenpiigilll & Scanned with OKEN ScannerSNIST (An Autonomous Institution) = _'‘ViS) ag oe sinuokea. B. Tech Branch Year 2022723 @ scanned with OKEN Scanner& Scanned with OKEN ScannerSNIST (An Autonomous Institution) ves\ EXPERIMENT = ext ee givulate, verify and synthesize full-oddey LL ADDER Pia: Desig > uaiag verilog HDL ond tapleuerct iu ARTIX-#FPGA Agearotus . Computer 2) Verilog HDL Sup lem Cutvare) toe s) pRtIx —F FPGA pre duces Thuory: Full Adders ad ba Heres sapuds q oo oufpuds. Jt caw take aglt jn pus together to be a bye wide adder to anobher Tae outpul jg dastgued as s Csam) Frrocaduare : creahe projet @ specthy Dopan VINADI, click, on” $ 2 oe Coe oe “ } A wih ereake % i 2) The propt navig al? vo’ Ki, at porta Fer specificote / o ; a Ce ee sources & 3) fo & pret PAavregey > alo + » cree Fe rite bok bade eras & save I* ond ud Euler de pOarow bo lovite Hest bende? 2 fo odd sere Ete Chin souvces , de om was Ginierreste adie odor a Blo 0 vish & cack on OF B.Tech Branch ECE Class @ scanned with OKEN Scanner& Scanned with OKEN ScannerSNIST (An Autonomous Institution) NLS Las Verilog pr : ote | ae (A,B, C, 5,60) 5 fupuk AsB.C5 outpt $505 assign Coz Cada (ah dlceka); assign Sz (An arc)s endvodulye Tort bench prooprown + wire $603 fodder ust ACA), C8), (CLO, -$E5),.C00609)5 intial Daud & Frmabache d using. asized, ae Te Ta design of vewilog HDL. The dost fn Nexy4 FPGA Eid B, Tech Braneh __ECE 2 y 2922-23 @ scanned with OKEN Scanner& Scanned with OKEN ScannerSNIST (An Autonomous Institution) — _VtS\ ag EXPERIMENT: 8-3 ENcodDER Miva: To dufiqu , simubate , verity Ce waing verileg HDL Q twplomeat tn ARTIX <2 FPGA Apparatus: 1) Compuciot cysleun 2)VIVABO tool 3) ARTIX-4 FPGA Theory: Encodtr is a sensine, device tet provides fecdloock. converts MOK Lo an sechical signed. block can be ype of contol davie tn motor coutnl sow » suck at PLE dade on create prt & specify prac Li create a nuo prick voit vivADO, 2) Too project ravi gactor given spect teakens to 4 fect rnanager, Sick om fo to pry : ud Enler the program & save 14 & wile tek bende Progr \ To write Jes bendk, go + add sours Hav gelet off 5) Te writ Gruledion Sour, Side ow ware & creake a fle on fivish & dick ow ok- _— add sours & Creede filo] Z) Chick, 2) Observe He oubpbe Verilog code Ai Y4o% 5 gu 2 Celflgl li; yeCeld lglh); Class 2E=2 Rolt No.203u16 B. Tech aan Z \\ \\Y @ scanned with OKEN Scanner& Scanned with OKEN Scanner= CLIdIEIWS assign = oud module “Tsk Ter bends progpaw’ produle — oreod.o* kbs egy ares do Of 97 : Bs cn, 600, AID, ele) sf CAs « lg o Ws ACAD, YOY * 2(2))5 20920} 72) gro; bees cals AO) Oe oy dr) 97" wo be04 C20; Az; e790 FeO) YO" =o) Leo, at 100 ar #00 aT peos exvidizos e213 feos gros WO? at 100 nso; bao seri Azo 220, F215 gro) 203 ot azo; v2.03 C205dz0; e205 fro4 gals = 05 akico gro} bro yc 20; Azo y eros Fe03 470} hey end ‘ain Brabus? Rael: a olatatued. and the datign of om vert log HOC The dutqu 1s Hoon ay pleased. tm Neags FPGA bit aud 74s 4 yeriGied Su Hue st, 7 B.Tech Branch ECE ___ ins UE @ scanned with OKEN Scanner& Scanned with OKEN Scanner(An Autonomous Institution) en naeereeeetapenstpaeneceel ae SNIST EXPERIMENT — 3-3 DECODER veridy & sywtesize 3 -to-g ARTIX -F FPGA Mu: To diestgqu, sivulate ~ | Q Susplumarck tu decoder usting ve vileg HDL & Amp wade AgPovadse? G Cam © VivADo tool @nenix-4 PGA fovia Ha gunn ct Hoe pio coded Mpat Signal and converts Ww jute on Mer of output spectdy project Wane it potter suslus erginad Agrall de om create projec & vivPDe, hk , AL credo a nwo projec # project navigator voi oven Seecificodieud ‘ a pete ? d sources & erecta fro be Prmect managers dice ow of ie tte tert bench progra >) Enter La program & save 44 oud vorvite ter prey Gp cas 2 : mn ) eo prite Lert bench, go to add sours ton select aff =) wre a omudemen sours, dick ow uasct ond crecte o fe Cc on fivish oud clttk on OK- 6c nt) Observe Hrs ovspuds yz eorkk (ny) Le C25 ce (ew ky blag), @ scanned with OKEN ScannerSNIST (An Autonomous Institution) Vis} LAB bac & yd Sead; assign @ 20% & (ny) & (m2); w f= 00 & Coys Bleais gs wd &lgd &e-2)s he Oo & ly) ted; al and weodule Teak _bencl_pre grow sive ‘ 7 (aah; WW), wire reves ds bobs 920 a Ata 22s fhe Qs A uu (Ceaca) ) Wwe)" , 1X00 5-404); 225 022-23 B. Tech Branch ECE _ ece Class =B__Roll No, 2021.00 Academie Year Page @ scanned with OKEN Scanner& Scanned with OKEN ScannerSNIST (An Autonomous Institution) ves) LAB EXPERIMENT : -T-FLIP FLOP fu: Dofgu, simulate , verify Q syntlestze T fie flop Q wting verilog HDL & Aap Wuset ju AR TIX -% EPGA ApeHratwA? O Compartir sysler ® veriloy Hou @ aetix-# FPGA ator * x T flip flop ts also calle: toggle flip _flep: $4 1s a dhange 1 te ae ftip- flop. The 7 tip-flep ts vecetved by ds of a SK flip-flop The T flip ~flep sy? & Se, olen T29, both sup bu vetoing ple inputs ¢ veceived bots AND gale owe 33s aed Proce dures: . seer wivioo, clteke on cveate popes & spectty pe nod an 2) The project navigator wit credle a wo project wl Gfven specifications 3) Ge 40 Cope WAG 4A.Ger y click ow KEL coures & creche Se Ay save 7% avd rite tet anche wd enter Hee pregrat ergo ( ae wae desk lbouch, 90 +e add sours Hien sallert &. add. stteulol ou Sores 6) UK on fuish § of vr Observe Ws odor vewle ro : module + -f40 quput £, clk rst e, a @ scanned with OKEN Scanner& Scanned with OKEN Scanneroudpul x44 4); always @ (posedgg cle G4 (ast) begt a ) G c= Ibe) . : ip) begin acs! eu d and module Test Berck code: eee t_fLAle; end lve ly; Y : coat C4), valle CER) 4 + . ost (est) AD) , clk so; a8t20 gers ered ond — sivuulacked: Tes Dusigu of o T-FF grat 15 ovtdlvar AEs Viv8DO PDL. Ths design ts Hee PGA kit & 94s sina, veitleg HDL im SynHaest 22d viva pleaded Aw Nery € functionalily 15 verified @ scanned with OKEN Scanner& Scanned with OKEN ScannerSNIST (An Autonomous Institution) Vist LAB EXPERIMENT: MULTIPLEXER Alin: Design, simulote, verify and syutiestze @x) nuttplerer using verilog HDL ond fuapliucnt PRTIX— 4 FPOA AgPpowahas DComputer sy stun 2) Vevileg HDL (vivADe) Tool DARTIK-Z Efan TWeory: Sn te 8x1 wulkidexer, Here are total eight Tupds, 2 selecte Rae and Single —outpt on the boats ef combination ef i/p?s Hook are present ck selectou huss, out of Hese ave connected to opal f et f Fracedre Doren VivAD0, dick om create project & specidy protect name #) The prject hovigator AL crectte a nwo project with Given spectfeations 5) Ge to project manoger, dick on add sources L create Ab DEnter de prrqram & save te aud voile Tet Bench Argram IS) To Lorvtte test bends, ge to add sourey Hen select adde simulation sources, chick on next & create o fle @) dick on finish & dick on ok FF) Obcewe tre oudpds Verlag. prego: wacdule men (arbre, det, gsbsx,y,2, ok); fiwpuk: be bef. gsh ix, ye; output ods ouk= Coan bevy) Klar ba) [Oo eny) bce) &b)I leon fecyr & toed be IC Aly) &C2) LAV er king) Coot | (00 & coy) Ce) Lp | Go Key) Kad SEMMCn WON) bead By assign end mods B.Tech Branch __€CE_Class_I-B Roll No. & @ scanned with OKEN Scanner& Scanned with OKEN ScannerSNIST (An Autonomous Institution) Ves = LAB Test bench program : module me xi tl; fogsh, 4,23 mex! unk Cacer, Cm), Ce), AAD, . eve), ff), -9 0), hl), - oukloudi), futtiol andmodule Result: Te dasigu ef ont wwliplixer 4s obtatinad & sinmwlaled wing werileg HOL. Tha ditigu 4s Hew sytasized, Smplemated a Nort craa Kk & Bits fanctioualihy 13 verified _ B. Tech Branch _€CE __ Class. @ scanned with OKEN Scanner& Scanned with OKEN ScannerSNIST (An Autonomous Institution) eo es LAB EXPERIMENT: DE MULTIPLE XR Alun: Design, simulebe, verify & sytlesize Ix¢ deurux using verilog HDL and furpturcit Gu ARTIK-7 FPGA Agporedus: 1) computer ey teu 2) Verilog HDL 3) ARTIX-F FE RGA 10S Aewuubtiplerer couststs of one Vp Ine , 2 output Hue & 3 select lies. gk Ys 0 prrcess of taking Se for medion € from Oe VI? Ged howswitting over ont of Ht many eutpds Proceduxre + Doren ViVABO, dick on create project & specify project name 2) The project navigator will Create a novo project with given spectticoH ens te project manager, click on add sources & create file e)enter the program & save it ond wri fest bench Praram Delile on frutsh & lt on OK. 6) Observe He outputs Ge Vevi or wodube demure Cnput Fra yse, out asbye,d, 2, £5 9h); assign as (aad f (ay) & c~z) BS, assign We (m9 2 (uy) & C2) 24, assign C= (xd & fy & a) Bt; assign A= (and & Cy) & (2d Bis jastign €= (09h (ay) & (wad Bi, assign fe Gok (mgd &arks, assign G= Crk Cy (ne) Ai; aston ee GO & tyr bh cer &5; eud module @ scanned with OKEN Scannerpveoo-y tmakc Akogvous & Scanned with OKEN ScannerTest bends praram : modo module dumuxie Lb; reg 1,204,235 wire ane, dies fas Aemux ts uel CIO, . 00), yg). 2@),. ala), -blb),. le), Dray ae FCs. 9 G)y (4d); 7 awikal begin enrdurcdult Aesulk: Ths dasiqu of 168 Stumulfipleaer 15 obtained & simulated uSivg verilog HDL. Te dasigqu is Han syudlasiced , Auaplamaded fw Nexye @PGA Kit © aks functionality 4s verified B.Tech Branch ECE Class 27-8 _ Roll No. @ scanned with OKEN Scanner& Scanned with OKEN Scanner& Scanned with OKEN Scanner& Scanned with OKEN Scanner& Scanned with OKEN Scanner& Scanned with OKEN Scanner& Scanned with OKEN Scanner