STM32F031x4 STM32F031x6

STM32F031x4 STM32F031x6
ARM®-based 32-bit MCU with up to 32 Kbyte Flash, 9 timers,

ADC and communication interfaces, 2.0 - 3.6 V
Datasheet - production data
Features
• Core: ARM® 32-bit Cortex®-M0 CPU,
frequency up to 48 MHz
LQFP32 7x7 mm UFQFPN32 5x5 mm WLCSP25 TSSOP20
• Memories LQFP48 7x7 mm UFQFPN28 4x4 mm 2.1x2.1 mm 6.5x4.4 mm
– 16 to 32 Kbytes of Flash memory
– 1 x 16-bit timer, with IC/OC and OCN,
– 4 Kbytes of SRAM with HW parity deadtime generation, emergency stop and
• CRC calculation unit modulator gate for IR control
• Reset and power management – 1 x 16-bit timer with 1 IC/OC
– Digital and I/Os supply: 2.0 to 3.6 V – Independent and system watchdog timers
– Analog supply: VDDA = from VDD to 3.6 V – SysTick timer: 24-bit downcounter
– Power-on/Power-down reset (POR/PDR) • Calendar RTC with alarm and periodic wakeup
– Programmable voltage detector (PVD) from Stop/Standby
– Low power modes: Sleep, Stop and • Communication interfaces
Standby – 1 x I2C interface, supporting Fast Mode
– VBAT supply for RTC and backup registers Plus (1 Mbit/s) with 20 mA current sink,
• Clock management SMBus/PMBus, and wakeup from Stop
mode
– 4 to 32 MHz crystal oscillator
– 1 x USART supporting master synchronous
– 32 kHz oscillator for RTC with calibration
SPI and modem control, ISO7816
– Internal 8 MHz RC with x6 PLL option interface, LIN, IrDA capability, auto baud
– Internal 40 kHz RC oscillator rate detection and wakeup feature
• Up to 39 fast I/Os – 1 x SPI (18 Mbit/s) with 4 to 16
– All mappable on external interrupt vectors programmable bit frames, with I2S interface
– Up to 26 I/Os with 5 V tolerant capability multiplexed
• 5-channel DMA controller • Serial wire debug (SWD)
• 1 × 12-bit, 1.0 µs ADC (up to 10 channels) • 96-bit unique ID

– Conversion range: 0 to 3.6V • Extended temperature range: -40 to +105°C
– Separate analog supply from 2.4 up to • All packages ECOPACK®2
3.6 V
• Up to 9 timers Table 1. Device summary
– 1 x 16-bit 7-channel advanced-control timer Reference Part number
for 6 channels PWM output, with deadtime
STM32F031C6, STM32F031E6,
generation and emergency stop
STM32F031x6 STM32F031F6, STM32F031G6,
– 1 x 32-bit and 1 x 16-bit timer, with up to 4 STM32F031K6
IC/OC, usable for IR control decoding
STM32F031C4, STM32F031F4,
– 1 x 16-bit timer, with 2 IC/OC, 1 OCN, STM32F031x4
STM32F031G4, STM32F031K4
deadtime generation and emergency stop
May 2017 DocID025743 Rev 6 1/106

This is information on a product in full production. www.st.com
Contents STM32F031x4 STM32F031x6
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 ARM®-Cortex®-M0 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.2 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.3 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.4 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 12
3.5 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.5.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.5.2 Power supply supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.5.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.5.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.6 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.7 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.8 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.9 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.9.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 15
3.9.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 15
3.10 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.10.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.10.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.10.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.11 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.11.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.11.2 General-purpose timers (TIM2, 3, 14, 16, 17) . . . . . . . . . . . . . . . . . . . . 17
3.11.3 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.11.4 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.11.5 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.12 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 19
3.13 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.14 Universal synchronous/asynchronous receiver/transmitter (USART) . . . 20
2/106 DocID025743 Rev 6

STM32F031x4 STM32F031x6 Contents
3.15 Serial peripheral interface (SPI) / Inter-integrated sound interface (I2S) . 21

3.16 Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 41
6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 42
6.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.3.6 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.3.10 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
6.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.3.16 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.3.17 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.3.18 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.3.19 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
DocID025743 Rev 6 3/106

4
Contents STM32F031x4 STM32F031x6
6.3.20 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
7.1 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
7.2 LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
7.3 UFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
7.4 UFQFPN28 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
7.5 WLCSP25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
7.6 TSSOP20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
7.7 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.7.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.7.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 100
8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4/106 DocID025743 Rev 6

STM32F031x4 STM32F031x6 List of tables
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. STM32F031x4/x6 family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . 9
Table 3. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 6. Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 7. STM32F031x4/x6 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 8. STM32F031x4/x6 USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 9. STM32F031x4/x6 SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 10. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 11. Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 12. Alternate functions selected through GPIOA_AFR registers for port A . . . . . . . . . . . . . . . 31
Table 13. Alternate functions selected through GPIOB_AFR registers for port B . . . . . . . . . . . . . . . 32
Table 14. Peripheral register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 15. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 16. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 17. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 18. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 19. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 20. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 21. Programmable voltage detector characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 22. Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 23. Typical and maximum current consumption from VDD at 3.6 V . . . . . . . . . . . . . . . . . . . . . 44
Table 24. Typical and maximum current consumption from the VDDA supply . . . . . . . . . . . . . . . . . 45
Table 25. Typical and maximum current consumption in Stop and Standby modes . . . . . . . . . . . . 46
Table 26. Typical and maximum current consumption from the VBAT supply. . . . . . . . . . . . . . . . . . . 47
Table 27. Typical current consumption, code executing from Flash memory,
running from HSE 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 28. Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 29. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 30. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 31. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 32. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 33. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 34. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 35. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 36. HSI14 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 37. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 38. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 39. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 40. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 41. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 42. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 43. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 44. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 45. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 46. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 47. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
DocID025743 Rev 6 5/106

6
List of tables STM32F031x4 STM32F031x6
Table 48. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 49. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 50. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 51. RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 52. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 53. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 54. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 55. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 56. IWDG min/max timeout period at 40 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 57. WWDG min/max timeout value at 48 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 58. I2C analog filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 59. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 60. I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 61. LQFP48 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 62. LQFP32 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 63. UFQFPN32 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 64. UFQFPN28 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 65. WLCSP25 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 66. WLCSP25 recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 67. TSSOP20 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 68. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 69. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 70. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6/106 DocID025743 Rev 6

STM32F031x4 STM32F031x6 List of figures
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 3. LQFP48 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 4. LQFP32 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 5. UFQFPN32 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 6. UFQFPN28 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 7. WLCSP25 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 8. TSSOP20 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 9. STM32F031x6 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 10. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 11. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 12. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 13. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 14. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 15. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 16. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 17. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 18. HSI oscillator accuracy characterization results for soldered parts . . . . . . . . . . . . . . . . . . 58
Figure 19. HSI14 oscillator accuracy characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 20. TC and TTa I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 21. Five volt tolerant (FT and FTf) I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 22. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 23. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 24. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 25. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 26. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 27. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 28. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 29. I2S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 30. I2S master timing diagram (Philips protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 31. LQFP48 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 32. Recommended footprint for LQFP48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 33. LQFP48 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 34. LQFP32 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 35. Recommended footprint for LQFP32 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 36. LQFP32 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 37. UFQFPN32 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 38. Recommended footprint for UFQFPN32 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 39. UFQFPN32 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 40. UFQFPN28 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 41. Recommended footprint for UFQFPN28 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 42. UFQFPN28 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 43. WLCSP25 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 44. Recommended footprint for WLCSP25 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 45. WLCSP25 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 46. TSSOP20 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 47. Recommended footprint for TSSOP20 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 48. TSSOP20 package marking example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
DocID025743 Rev 6 7/106

7
Introduction STM32F031x4 STM32F031x6
1 Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32F031x4/x6 microcontrollers.
This document should be read in conjunction with the STM32F0xxxx reference manual
(RM0091). The reference manual is available from the STMicroelectronics website
www.st.com.
For information on the ARM® Cortex®-M0 core, please refer to the Cortex®-M0 Technical
Reference Manual, available from the www.arm.com website.
8/106 DocID025743 Rev 6

STM32F031x4 STM32F031x6 Description
2 Description
The STM32F031x4/x6 microcontrollers incorporate the high-performance ARM® Cortex®-

M0 32-bit RISC core operating at up to 48 MHz frequency, high-speed embedded memories
(up to 32 Kbytes of Flash memory and 4 Kbytes of SRAM), and an extensive range of
enhanced peripherals and I/Os. All devices offer standard communication interfaces (one
I2C, one SPI/ I2S and one USART), one 12-bit ADC,
five 16-bit timers, one 32-bit timer and an advanced-control PWM timer.
The STM32F031x4/x6 microcontrollers operate in the -40 to +85 °C and -40 to +105 °C
temperature ranges, from a 2.0 to 3.6 V power supply. A comprehensive set of
power-saving modes allows the design of low-power applications.
The STM32F031x4/x6 microcontrollers include devices in six different packages ranging
from 20 pins to 48 pins with a die form also available upon request. Depending on the
device chosen, different sets of peripherals are included.
These features make the STM32F031x4/x6 microcontrollers suitable for a wide range of
applications such as application control and user interfaces, hand-held equipment, A/V
receivers and digital TV, PC peripherals, gaming and GPS platforms, industrial applications,
PLCs, inverters, printers, scanners, alarm systems, video intercoms and HVACs.
Table 2. STM32F031x4/x6 family device features and peripheral counts

Peripheral STM32F031Fx STM32F031Ex STM32F031Gx STM32F031Kx STM32F031Cx
Flash memory (Kbyte) 16 32 32 16 32 16 32 16 32

SRAM (Kbyte) 4
Advanced
1 (16-bit)
control
Timers
General 4 (16-bit)
purpose 1 (32-bit)
SPI [I2S](1) 1 [1]
Comm. 2
I C 1
interfaces
USART 1
12-bit ADC 1 1
(number of channels) (9 ext. + 3 int.) (10 ext. + 3 int.)
25 (on LQFP32)
GPIOs 15 20 23 39
27 (on UFQFPN32)
Max. CPU frequency 48 MHz
Operating voltage 2.0 to 3.6 V
Ambient operating temperature: -40°C to 85°C / -40°C to 105°C
Operating temperature
Junction temperature: -40°C to 105°C / -40°C to 125°C
LQFP32
Packages TSSOP20 WLCSP25 UFQFPN28 LQFP48
UFQFPN32
1. The SPI interface can be used either in SPI mode or in I2S audio mode.
DocID025743 Rev 6 9/106

22
Description STM32F031x4 STM32F031x6
Figure 1. Block diagram
32:(5
6:&/. 6HULDO:LUH
6:',2 'HEXJ 92/75(* 9'' WR9
DV$) 9'' 9WR9 966
2EO
PHPRU\
LQWHUIDFH
)ODVK*3/
)ODVK
8SWR.%
#9''
&257(;0&38 ELW
I0$; 0+] 6833/<
683(59,6,21
325 1567
65$0
%XVPDWUL[
FRQWUROOHU
65$0
.% 5HVHW 9''$
,QW 3253'5 966$
19,& #9''$
9''
+6, 39'
5&0+]
+6,
5&0+] #9''$
3//&/. #9''
3//
/6,
*3'0$ 5&N+] ;7$/26& 26&B,1
FKDQQHOV 0+] 26&B287
,QG:LQGRZ:'*
3RZHU
5(6(7 &/2&. &RQWUROOHU 9''
&21752/
3$>@ *3,2SRUW$ #9%$7 9%$7 WR9
$+%GHFRGHU
3%>@ *3,2SRUW% ;7$/N+] 26&B,1

6\VWHPDQGSHULSKHUDO
26&B287
FORFNV
3&>@ *3,2SRUW& %DFNXS 7$03(557&
57&
UHJ $/$50287
3)>@ *3,2SRUW) &5& 57&LQWHUIDFH
FKDQQHOV
3:07,0(5 FRPSOFKDQQHOV
$+% %5.(75LQSXWDV$)
$3% 7,0(5ELW FK(75DV$)
7,0(5 FK(75DV$)
$) (;7,7:.83
7,0(5 FKDQQHODV$)
026,6' FKDQQHO
7,0(5
0,620&. FRPSO%5.DV$)
63,,6 :LQGRZ:'*
6&.&. FKDQQHO
166:6DV$) 7,0(5
FRPSO%5.DV$)
7HPS '%*0&8 ,5B287DV$)

VHQVRU
[
$'LQSXW ELW$'& ,) 6<6&)*,) 5;7;&76576
86$57
&.DV$)
9''$ 6&/6'$60%$
966$ ,&
P$)0DV$)
#9''$
3RZHUGRPDLQRIDQDORJEORFNV 9%$7 9'' 9''$

06Y9
10/106 DocID025743 Rev 6

STM32F031x4 STM32F031x6 Functional overview
3 Functional overview
Figure 1 shows the general block diagram of the STM32F031x4/x6 devices.
3.1 ARM®-Cortex®-M0 core

The ARM® Cortex®-M0 is a generation of ARM 32-bit RISC processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM® Cortex®-M0 processors feature exceptional code-efficiency, delivering the high
performance expected from an ARM core, with memory sizes usually associated with 8- and
16-bit devices.
The STM32F031x4/x6 devices embed ARM core and are compatible with all ARM tools and
software.
3.2 Memories
The device has the following features:
• 4 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states and featuring embedded parity checking with exception generation for fail-critical
applications.
• The non-volatile memory is divided into two arrays:
– 16 to 32 Kbytes of embedded Flash memory for programs and data
– Option bytes
The option bytes are used to write-protect the memory (with 4 KB granularity) and/or
readout-protect the whole memory with the following options:
– Level 0: no readout protection
– Level 1: memory readout protection, the Flash memory cannot be read from or
written to if either debug features are connected or boot in RAM is selected
–
®
Level 2: chip readout protection, debug features (Cortex -M0 serial wire) and
boot in RAM selection disabled
3.3 Boot modes

At startup, the boot pin and boot selector option bit are used to select one of the three boot
options:
• boot from User Flash memory
• boot from System Memory
• boot from embedded SRAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART on pins PA14/PA15 or PA9/PA10.
DocID025743 Rev 6 11/106

22
Functional overview STM32F031x4 STM32F031x6
3.4 Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a CRC-32 (Ethernet) polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
3.5 Power management
3.5.1 Power supply schemes

• VDD = VDDIO1 = 2.0 to 3.6 V: external power supply for I/Os (VDDIO1) and the internal
regulator. It is provided externally through VDD pins.
• VDDA = from VDD to 3.6 V: external analog power supply for ADC, Reset blocks, RCs
and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC is used). It is
provided externally through VDDA pin. The VDDA voltage level must be always greater
or equal to the VDD voltage level and must be established first.
• VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
For more details on how to connect power pins, refer to Figure 12: Power supply scheme.
3.5.2 Power supply supervisors

The device has integrated power-on reset (POR) and power-down reset (PDR) circuits.
They are always active, and ensure proper operation above a threshold of 2 V. The device
remains in reset mode when the monitored supply voltage is below a specified threshold,
VPOR/PDR, without the need for an external reset circuit.
• The POR monitors only the VDD supply voltage. During the startup phase it is required
that VDDA should arrive first and be greater than or equal to VDD.
• The PDR monitors both the VDD and VDDA supply voltages, however the VDDA power
supply supervisor can be disabled (by programming a dedicated Option bit) to reduce
the power consumption if the application design ensures that VDDA is higher than or
equal to VDD.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD power supply and compares it to the VPVD threshold. An interrupt can be generated
when VDD drops below the VPVD threshold and/or when VDD is higher than the VPVD
threshold. The interrupt service routine can then generate a warning message and/or put
the MCU into a safe state. The PVD is enabled by software.
3.5.3 Voltage regulator

The regulator has two operating modes and it is always enabled after reset.
• Main (MR) is used in normal operating mode (Run).
• Low power (LPR) can be used in Stop mode where the power demand is reduced.
12/106 DocID025743 Rev 6

In Standby mode, it is put in power down mode. In this mode, the regulator output is in high
impedance and the kernel circuitry is powered down, inducing zero consumption (but the
contents of the registers and SRAM are lost).
3.5.4 Low-power modes

The STM32F031x4/x6 microcontrollers support three low-power modes to achieve the best
compromise between low power consumption, short startup time and available wakeup
sources:
• Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
• Stop mode
Stop mode achieves very low power consumption while retaining the content of SRAM
and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the
HSE crystal oscillators are disabled. The voltage regulator can also be put either in
normal or in low power mode.
The device can be woken up from Stop mode by any of the EXTI lines. The EXTI line
source can be one of the 16 external lines, the PVD output, RTC, I2C1 or USART1.
USART1 and I2C1 peripherals can be configured to enable the HSI RC oscillator so as
to get clock for processing incoming data. If this is used when the voltage regulator is
put in low power mode, the regulator is first switched to normal mode before the clock
is provided to the given peripheral.
• Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the RTC
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a
rising edge on the WKUP pins, or an RTC event occurs.
Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
or Standby mode.
3.6 Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example on
failure of an indirectly used external crystal, resonator or oscillator).
Several prescalers allow the application to configure the frequency of the AHB and the APB
domains. The maximum frequency of the AHB and the APB domains is 48 MHz.
DocID025743 Rev 6 13/106

22
Figure 2. Clock tree
)/,7)&/. )ODVKPHPRU\
SURJUDPPLQJ
,&6: LQWHUIDFH
0+] +6, +6, +6,
+6,5& ,&
6<6&/.
,6
$+%FRUHPHPRU\'0$
+&/. &RUWH[)&/.IUHHUXQFORFN
6: 6<6&/.
3//65& 3//08/ &RUWH[

+6, V\VWHPWLPHU
3// « 3&/.
3//&/. $3%
[[ «
+6( SHULSKHUDOV
[
35(',9
+35( 335(

&66
335(
[[ 7,0
26&B287 +6(
0+]
+6(26& 86$576:
26&B,1 3&/.
/6( 6<6&/.
86$57
+6,
/6(
26&B,1 57&&/.
N+] /6( 57&
/6(26&
26&B287
57&6(/
N+] /6, ,:'*

/6,5&
3//12',9 $'&
0+]5& +6,
+6, DV\QFKURQRXV
0&235( 3//&/. FORFNLQSXW

0DLQFORFN +6,
RXWSXW +6,

0&2 +6( /HJHQG
6<6&/.
/6, EODFN FORFNWUHHHOHPHQW
/6(
ZKLWH FORFNWUHHFRQWUROHOHPHQW
WR7,0
0&2 FORFNOLQH
FRQWUROOLQH
06Y9
3.7 General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions.
The I/O configuration can be locked if needed following a specific sequence in order to
avoid spurious writing to the I/Os registers.
14/106 DocID025743 Rev 6

3.8 Direct memory access controller (DMA)

The 5-channel general-purpose DMAs manage memory-to-memory, peripheral-to-memory
and memory-to-peripheral transfers.
The DMA supports circular buffer management, removing the need for user code
intervention when the controller reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.
DMA can be used with the main peripherals: SPIx, I2Sx, I2Cx, USARTx, all TIMx timers
(except TIM14) and ADC.
3.9 Interrupts and events
3.9.1 Nested vectored interrupt controller (NVIC)

The STM32F0xx family embeds a nested vectored interrupt controller able to handle up to
®
32 maskable interrupt channels (not including the 16 interrupt lines of Cortex -M0) and 4
priority levels.
• Closely coupled NVIC gives low latency interrupt processing
• Interrupt entry vector table address passed directly to the core
• Closely coupled NVIC core interface
• Allows early processing of interrupts
• Processing of late arriving higher priority interrupts
• Support for tail-chaining
• Processor state automatically saved
• Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
3.9.2 Extended interrupt/event controller (EXTI)

The extended interrupt/event controller consists of 24 edge detector lines used to generate
interrupt/event requests and wake-up the system. Each line can be independently
configured to select the trigger event (rising edge, falling edge, both) and can be masked
independently. A pending register maintains the status of the interrupt requests. The EXTI
can detect an external line with a pulse width shorter than the internal clock period. Up to 39
GPIOs can be connected to the 16 external interrupt lines.
3.10 Analog-to-digital converter (ADC)

The 12-bit analog-to-digital converter has up to 16 external and 3 internal (temperature
sensor, voltage reference, VBAT voltage measurement) channels and performs conversions
in single-shot or scan modes. In scan mode, automatic conversion is performed on a
selected group of analog inputs.
The ADC can be served by the DMA controller.
DocID025743 Rev 6 15/106

22
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
3.10.1 Temperature sensor

The temperature sensor (TS) generates a voltage VSENSE that varies linearly with
temperature.
The temperature sensor is internally connected to the ADC_IN16 input channel which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.
Table 3. Temperature sensor calibration values

Calibration value name Description Memory address
TS ADC raw data acquired at a

TS_CAL1 temperature of 30 °C (± 5 °C), 0x1FFF F7B8 - 0x1FFF F7B9
VDDA= 3.3 V (± 10 mV)
TS ADC raw data acquired at a
TS_CAL2 temperature of 110 °C (± 5 °C), 0x1FFF F7C2 - 0x1FFF F7C3
VDDA= 3.3 V (± 10 mV)
3.10.2 Internal voltage reference (VREFINT)

The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the
ADC. VREFINT is internally connected to the ADC_IN17 input channel. The precise voltage
of VREFINT is individually measured for each part by ST during production test and stored in
the system memory area. It is accessible in read-only mode.
Table 4. Internal voltage reference calibration values

Calibration value name Description Memory address
Raw data acquired at a

VREFINT_CAL temperature of 30 °C (± 5 °C), 0x1FFF F7BA - 0x1FFF F7BB
VDDA= 3.3 V (± 10 mV)
3.10.3 VBAT battery voltage monitoring

This embedded hardware feature allows the application to measure the VBAT battery voltage
using the internal ADC channel ADC_IN18. As the VBAT voltage may be higher than VDDA,
and thus outside the ADC input range, the VBAT pin is internally connected to a bridge
divider by 2. As a consequence, the converted digital value is half the VBAT voltage.
16/106 DocID025743 Rev 6

3.11 Timers and watchdogs

The STM32F031x4/x6 devices include up to five general-purpose timers and an advanced
control timer.
Table 5 compares the features of the different timers.
Table 5. Timer feature comparison

DMA
Timer Counter Counter Prescaler Capture/compare Complementary
Timer request
type resolution type factor channels outputs
generation
Advanced Up, down, integer from

TIM1 16-bit Yes 4 3
control up/down 1 to 65536
Up, down, integer from
TIM2 32-bit Yes 4 -
up/down 1 to 65536
Up, down, integer from
TIM3 16-bit Yes 4 -
General up/down 1 to 65536
purpose integer from
TIM14 16-bit Up No 1 -
1 to 65536
TIM16 integer from
16-bit Up Yes 1 1
TIM17 1 to 65536
3.11.1 Advanced-control timer (TIM1)

The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on six
channels. It has complementary PWM outputs with programmable inserted dead times. It
can also be seen as a complete general-purpose timer. The four independent channels can
be used for:
• input capture
• output compare
• PWM generation (edge or center-aligned modes)
• one-pulse mode output
If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If
configured as the 16-bit PWM generator, it has full modulation capability (0-100%).
The counter can be frozen in debug mode.
Many features are shared with those of the standard timers which have the same
architecture. The advanced control timer can therefore work together with the other timers
via the Timer Link feature for synchronization or event chaining.
3.11.2 General-purpose timers (TIM2, 3, 14, 16, 17)

There are five synchronizable general-purpose timers embedded in the STM32F031x4/x6
devices (see Table 5 for differences). Each general-purpose timer can be used to generate
PWM outputs, or as simple time base.
DocID025743 Rev 6 17/106

22
TIM2, TIM3
STM32F031x4/x6 devices feature two synchronizable 4-channel general-purpose timers.
TIM2 is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. TIM3 is based
on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. They feature 4 independent
channels each for input capture/output compare, PWM or one-pulse mode output. This
gives up to 12 input captures/output compares/PWMs on the largest packages.
The TIM2 and TIM3 general-purpose timers can work together or with the TIM1 advanced-
control timer via the Timer Link feature for synchronization or event chaining.
TIM2 and TIM3 both have independent DMA request generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.
Their counters can be frozen in debug mode.
TIM14
This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM14 features one single channel for input capture/output compare, PWM or one-pulse
mode output.
Its counter can be frozen in debug mode.
TIM16 and TIM17

Both timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
They each have a single channel for input capture/output compare, PWM or one-pulse
mode output.
TIM16 and TIM17 have a complementary output with dead-time generation and
independent DMA request generation.
Their counters can be frozen in debug mode.
3.11.3 Independent watchdog (IWDG)

The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with
user-defined refresh window. It is clocked from an independent 40 kHz internal RC and as it
operates independently from the main clock, it can operate in Stop and Standby modes. It
can be used either as a watchdog to reset the device when a problem occurs, or as a free
running timer for application timeout management. It is hardware or software configurable
through the option bytes. The counter can be frozen in debug mode.
3.11.4 System window watchdog (WWDG)

The system window watchdog is based on a 7-bit downcounter that can be set as free
running. It can be used as a watchdog to reset the device when a problem occurs. It is
clocked from the APB clock (PCLK). It has an early warning interrupt capability and the
counter can be frozen in debug mode.
18/106 DocID025743 Rev 6

3.11.5 SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
• a 24-bit down counter
• autoreload capability
• maskable system interrupt generation when the counter reaches 0
• programmable clock source (HCLK or HCLK/8)
3.12 Real-time clock (RTC) and backup registers

The RTC and the five backup registers are supplied through a switch that takes power either
on VDD supply when present or through the VBAT pin. The backup registers are five 32-bit
registers used to store 20 bytes of user application data when VDD power is not present.
They are not reset by a system or power reset, or at wake up from Standby mode.
The RTC is an independent BCD timer/counter. Its main features are the following:
• calendar with subseconds, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format
• automatic correction for 28, 29 (leap year), 30, and 31 day of the month
• programmable alarm with wake up from Stop and Standby mode capability
• on-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize the RTC with a master clock
• digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal
inaccuracy
• two anti-tamper detection pins with programmable filter. The MCU can be woken up
from Stop and Standby modes on tamper event detection
• timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event. The MCU can be
woken up from Stop and Standby modes on timestamp event detection
• reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision
The RTC clock sources can be:
• a 32.768 kHz external crystal
• a resonator or oscillator
• the internal low-power RC oscillator (typical frequency of 40 kHz)
• the high-speed external clock divided by 32
3.13 Inter-integrated circuit interface (I2C)

The I2C interface (I2C1) can operate in multimaster or slave modes. It can support Standard
mode (up to 100 kbit/s), Fast mode (up to 400 kbit/s) and Fast Mode Plus (up to 1 Mbit/s)
with 20 mA output drive.
It supports 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (two
addresses, one with configurable mask). It also includes programmable analog and digital
noise filters.
DocID025743 Rev 6 19/106

22
Table 6. Comparison of I2C analog and digital filters

Aspect Analog filter Digital filter
Pulse width of Programmable length from 1 to 15

≥ 50 ns
suppressed spikes I2Cx peripheral clocks
–Extra filtering capability vs.
Benefits Available in Stop mode standard requirements
–Stable length
Wakeup from Stop on address
Variations depending on
Drawbacks match is not available when digital
temperature, voltage, process
filter is enabled.
In addition, I2C1 provides hardware support for SMBUS 2.0 and PMBUS 1.1: ARP
capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts
verifications and ALERT protocol management. I2C1 also has a clock domain independent
from the CPU clock, allowing the I2C1 to wake up the MCU from Stop mode on address
match.
The I2C peripheral can be served by the DMA controller.
Table 7. STM32F031x4/x6 I2C implementation

I2C features(1) I2C1
7-bit addressing mode X

10-bit addressing mode X
Standard mode (up to 100 kbit/s) X
Fast mode (up to 400 kbit/s) X
Fast Mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s) X
Independent clock X
SMBus X
Wakeup from STOP X
1. X = supported.
3.14 Universal synchronous/asynchronous receiver/transmitter

(USART)
The device embeds one universal synchronous/asynchronous receiver/transmitter
(USART1) which communicates at speeds of up to 6 Mbit/s.
It provides hardware management of the CTS, RTS and RS485 DE signals, multiprocessor
communication mode, master synchronous communication and single-wire half-duplex
communication mode. USART1 supports also SmartCard communication (ISO 7816), IrDA
SIR ENDEC, LIN Master/Slave capability and auto baud rate feature, and has a clock
domain independent of the CPU clock, allowing to wake up the MCU from Stop mode.
The USART interface can be served by the DMA controller.
20/106 DocID025743 Rev 6

Table 8. STM32F031x4/x6 USART implementation

USART modes/features(1) USART1
Hardware flow control for modem X

Continuous communication using DMA X
Multiprocessor communication X
Synchronous mode X
Smartcard mode X
Single-wire half-duplex communication X
IrDA SIR ENDEC block X
LIN mode X
Dual clock domain and wakeup from Stop mode X
Receiver timeout interrupt X
Modbus communication X
Auto baud rate detection X
Driver Enable X
1. X = supported.
3.15 Serial peripheral interface (SPI) / Inter-integrated sound

interface (I2S)
The SPI is able to communicate up to 18 Mbit/s in slave and master modes in full-duplex
and half-duplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame size is configurable from 4 bits to 16 bits.
One standard I2S interface (multiplexed with SPI1) supporting four different audio standards
can operate as master or slave at half-duplex communication mode. It can be configured to
transfer 16 and 24 or 32 bits with 16-bit or 32-bit data resolution and synchronized by a
specific signal. Audio sampling frequency from 8 kHz up to 192 kHz can be set by an 8-bit
programmable linear prescaler. When operating in master mode, it can output a clock for an
external audio component at 256 times the sampling frequency.
Table 9. STM32F031x4/x6 SPI/I2S implementation

SPI features(1) SPI
Hardware CRC calculation X

Rx/Tx FIFO X
NSS pulse mode X
I2S mode X
TI mode X
1. X = supported.
DocID025743 Rev 6 21/106

22
3.16 Serial wire debug port (SW-DP)

An ARM SW-DP interface is provided to allow a serial wire debugging tool to be connected
to the MCU.
22/106 DocID025743 Rev 6

STM32F031x4 STM32F031x6 Pinouts and pin description
4 Pinouts and pin description
Figure 3. LQFP48 package pinout
%227
7RSYLHZ
3$
3$
9''
966
3%
3%
3%
3%
3%
3%
3%

9%$7 3)
3& 3)
3&26&B,1 3$
3&26&B287 3$
3)26&B,1 3$
3)26&B287 3$
1567
/4)3 3$
966$ 3$
9''$ 3%
3$ 3%
3$ 3%
3$ 3%

3%
3%
3%
3%
966
9''
3$
3$
3$
3$
3$
3%
06Y9
Figure 4. LQFP32 package pinout

%227
3$
966
3%
3%
3%
3%
3%
7RSYLHZ

9'' 3$
3)26&B,1 3$
3)26&B287 3$
1567 3$
9''$
/4)3 3$
3$ 3$
3$ 3$
3$ 9''

3%
3%
966
3$
3$
3$
3$
3$
06Y9
DocID025743 Rev 6 23/106

32
Pinouts and pin description STM32F031x4 STM32F031x6
Figure 5. UFQFPN32 package pinout
7RSYLHZ
%227
3$
3%
3%
3%
3%
3%
3%

9'' 3$

3)26&B,1 3$
3)26&B287 3$
1567 3$
9''$ 8)4)31 3$
3$ 3$
3$ ([SRVHGSDG 3$
3$ 9''

966
3%
3%
3%
3$
3$
3$
3$
3$
06Y9
Figure 6. UFQFPN28 package pinout
7RSYLHZ
3$
3$
3%
3%
3%
3%
3%

%227 3$
3)26&B,1 3$
3)26&B287 3$
1567 8)4)31 3$
9''$ 9''
3$ 966
3$ 3%

3%
3$
3$
3$
3$
3$
3$
06Y9
24/106 DocID025743 Rev 6

Figure 7. WLCSP25 package pinout
7RSYLHZ

$ 3$ 3$ 3% %227 3)
% 3$ 3% 3$ 3$ 3)
& 3$ 3% 3$ 3$ 1567
' 9'' 3$ 3$ 3$ 9''$
( 966 3% 3% 3$ 3$
:/&63
06Y9
1. The above figure shows the package in top view, changing from bottom view in the previous document
versions.
Figure 8. TSSOP20 package pinout
7RSYLHZ
76623
%227 3$
3)26&B,1 3$
3)26&B287 3$
1567 3$
9''$ 9''
3$ 966
3$ 3%
3$ 3$
3$ 3$
3$ 3$
06Y9
DocID025743 Rev 6 25/106

32
Table 10. Legend/abbreviations used in the pinout table

Name Abbreviation Definition
Unless otherwise specified in brackets below the pin name, the pin function
Pin name
during and after reset is the same as the actual pin name
S Supply pin
Pin type I Input-only pin
I/O Input / output pin
FT 5 V-tolerant I/O
FTf 5 V-tolerant I/O, FM+ capable
TTa 3.3 V-tolerant I/O directly connected to ADC
I/O structure
TC Standard 3.3V I/O
B Dedicated BOOT0 pin
RST Bidirectional reset pin with embedded weak pull-up resistor
Unless otherwise specified by a note, all I/Os are set as floating inputs during
Notes
and after reset
Alternate
Functions selected through GPIOx_AFR registers
functions
Pin
functions Additional
Functions directly selected/enabled through peripheral registers
functions
Table 11. Pin definitions

Pin number Pin functions
I/O structure
Pin type
Pin name
UFQFPN32
UFQFPN28
WLCSP25
TSSOP20
LQFP48
LQFP32
(function upon Notes

Additional
reset) Alternate functions
functions
1 - - - - - VBAT S - - Backup power supply

RTC_TAMP1,
(1)(2) RTC_TS,
2 - - - - - PC13 I/O TC -
RTC_OUT,
WKUP2
PC14-OSC32_IN (1)(2)
3 - - - - - I/O TC - OSC32_IN
(PC14)
PC15-
OSC32_OUT (1)(2)
4 - - - - - I/O TC - OSC32_OUT
(PC15)
PF0-OSC_IN
5 2 2 2 A5 2 I/O FT - - OSC_IN
(PF0)
26/106 DocID025743 Rev 6

Table 11. Pin definitions (continued)

I/O structure
Pin type
Pin name
UFQFPN32
UFQFPN28
WLCSP25
TSSOP20
LQFP48
LQFP32

Additional
functions
PF1-OSC_OUT
6 3 3 3 B5 3 I/O FT - - OSC_OUT
(PF1)
Device reset input / internal reset output
7 4 4 4 C5 4 NRST I/O RST -
(active low)
16 16 E1 15
8 (3) 0(3) (3) (3) (3) VSSA S - Analog ground
9 5 5 5 D5 5 VDDA S - Analog power supply

ADC_IN0,
TIM2_CH1_ETR,
10 6 6 6 B4 6 PA0 I/O TTa - RTC_TAMP2,
USART1_CTS
WKUP1
TIM2_CH2,
11 7 7 7 C4 7 PA1 I/O TTa - EVENTOUT, ADC_IN1
USART1_RTS
TIM2_CH3,
12 8 8 8 D4 8 PA2 I/O TTa - ADC_IN2
USART1_TX
TIM2_CH4,
13 9 9 9 E5 9 PA3 I/O TTa - ADC_IN3
USART1_RX
SPI1_NSS,
I2S1_WS,
14 10 10 10 B3 10 PA4 I/O TTa - ADC_IN4
TIM14_CH1,
USART1_CK
SPI1_SCK,
15 11 11 11 C3 11 PA5 I/O TTa - I2S1_CK, ADC_IN5
TIM2_CH1_ETR
SPI1_MISO,
I2S1_MCK,
TIM3_CH1,
16 12 12 12 D3 12 PA6 I/O TTa - ADC_IN6
TIM1_BKIN,
TIM16_CH1,
EVENTOUT
DocID025743 Rev 6 27/106

32

I/O structure
Pin type
Pin name
UFQFPN32
UFQFPN28
WLCSP25
TSSOP20
LQFP48
LQFP32

Additional
functions
SPI1_MOSI,
I2S1_SD,
TIM3_CH2,
17 13 13 13 E4 13 PA7 I/O TTa - TIM14_CH1, ADC_IN7
TIM1_CH1N,
TIM17_CH1,
EVENTOUT
TIM3_CH3,
18 14 14 14 E3 - PB0 I/O TTa - TIM1_CH2N, ADC_IN8
EVENTOUT
TIM3_CH4,
19 15 15 15 E2 14 PB1 I/O TTa - TIM14_CH1, ADC_IN9
TIM1_CH3N
(4)
20 - 16 - - - PB2 I/O FT - -
TIM2_CH3,
21 - - - - - PB10 I/O FTf - -
I2C1_SCL
TIM2_CH4,
22 - - - - - PB11 I/O FTf - EVENTOUT, -
I2C1_SDA
23 16 0 16 E1 15 VSS S - - Ground
24 17 17 17 D1 16 VDD S - - Digital power supply
TIM1_BKIN,
25 - - - - - PB12 I/O FT - EVENTOUT, -
SPI1_NSS
TIM1_CH1N,
26 - - - - - PB13 I/O FT - -
SPI1_SCK
TIM1_CH2N,
27 - - - - - PB14 I/O FT - -
SPI1_MISO
TIM1_CH3N,
28 - - - - - PB15 I/O FT - RTC_REFIN
SPI1_MOSI
USART1_CK,
TIM1_CH1,
29 18 18 18 D2 - PA8 I/O FT - -
EVENTOUT,
MCO
28/106 DocID025743 Rev 6


I/O structure
Pin type
Pin name
UFQFPN32
UFQFPN28
WLCSP25
TSSOP20
LQFP48
LQFP32

Additional
functions
USART1_TX,
30 19 19 19 C1 17 PA9 I/O FTf - TIM1_CH2, -
I2C1_SCL
USART1_RX,
TIM1_CH3,
31 20 20 20 B1 18 PA10 I/O FTf - -
TIM17_BKIN,
I2C1_SDA
USART1_CTS,
32 21 21 - - - PA11 I/O FT - TIM1_CH4, -
EVENTOUT
USART1_RTS,
33 22 22 - - - PA12 I/O FT - TIM1_ETR, -
EVENTOUT
PA13 (5) IR_OUT,
34 23 23 21 A1 19 I/O FT -
(SWDIO) SWDIO
35 - - - - - PF6 I/O FTf - I2C1_SCL -
36 - - - - - PF7 I/O FTf - I2C1_SDA -
PA14 (5) USART1_TX,
37 24 24 22 A2 20 I/O FT -
(SWCLK) SWCLK
SPI1_NSS,
I2S1_WS,
(6)
38 25 25 23 - - PA15 I/O FT TIM2_CH_ETR, -
EVENTOUT,
USART1_RX
SPI1_SCK,
(6) I2S1_CK,
39 26 26 24 - - PB3 I/O FT -
TIM2_CH2,
EVENTOUT
SPI1_MISO,
(6) I2S1_MCK,
40 27 27 25 - - PB4 I/O FT -
TIM3_CH1,
EVENTOUT
DocID025743 Rev 6 29/106

32

I/O structure
Pin type
Pin name
UFQFPN32
UFQFPN28
WLCSP25
TSSOP20
LQFP48
LQFP32

Additional
functions
SPI1_MOSI,
I2S1_SD,
41 28 28 26 C2 - PB5 I/O FT - I2C1_SMBA, -
TIM16_BKIN,
TIM3_CH2
I2C1_SCL,
42 29 29 27 B2 - PB6 I/O FTf - USART1_TX, -
TIM16_CH1N
I2C1_SDA,
43 30 30 28 A3 - PB7 I/O FTf - USART1_RX, -
TIM17_CH1N
44 31 31 1 A4 1 BOOT0 I B - Boot memory selection
(4) I2C1_SCL,
45 - 32 - - - PB8 I/O FTf -
TIM16_CH1
I2C1_SDA,
IR_OUT,
46 - - - - - PB9 I/O FTf - -
TIM17_CH1,
EVENTOUT
47 32 0 - E1 - VSS S - - Ground
48 1 1 - - - VDD S - - Digital power supply
1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF
- These GPIOs must not be used as current sources (e.g. to drive an LED).
2. After the first RTC domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content
of the RTC registers which are not reset by the system reset. For details on how to manage these GPIOs, refer to the RTC
domain and RTC register descriptions in the reference manual.
3. VSSA pin is not in package pinout. VSSA pad of the die is connected to VSS pin.
4. On the LQFP32 package, PB2 and PB8 should be treated as unconnected pins (even when they are not available on the
package, they are not forced to a defined level by hardware).
5. After reset, these pins are configured as SWDIO and SWCLK alternate functions, and the internal pull-up on the SWDIO pin
and the internal pull-down on the SWCLK pin are activated.
6. On the WLCSP25 package, PB3, PB4 and PA15 must be set to defined levels by software, as their corresponding pads on
the silicon die are left unconnected. Apply same recommendations as for unconnected pins.
30/106 DocID025743 Rev 6

Table 12. Alternate functions selected through GPIOA_AFR registers for port A
Pin name AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
TIM2_CH1_
PA0 - USART1_CTS - - - - -
ETR
PA1 EVENTOUT USART1_RTS TIM2_CH2 - - - - -
PA2 - USART1_TX TIM2_CH3 - - - - -
PA3 - USART1_RX TIM2_CH4 - - - - -
SPI1_NSS,
PA4 USART1_CK - - TIM14_CH1 - - -
I2S1_WS
SPI1_SCK, TIM2_CH1_
PA5 - - - - - -
I2S1_CK ETR
SPI1_MISO,
PA6 TIM3_CH1 TIM1_BKIN - - TIM16_CH1 EVENTOUT -
DocID025743 Rev 6
I2S1_MCK
SPI1_MOSI,
PA7 TIM3_CH2 TIM1_CH1N - TIM14_CH1 TIM17_CH1 EVENTOUT -
I2S1_SD
PA8 MCO USART1_CK TIM1_CH1 EVENTOUT - - - -
PA9 - USART1_TX TIM1_CH2 - I2C1_SCL - - -
PA10 TIM17_BKIN USART1_RX TIM1_CH3 - I2C1_SDA - - -
PA11 EVENTOUT USART1_CTS TIM1_CH4 - - - - -
PA12 EVENTOUT USART1_RTS TIM1_ETR - - - - -
PA13 SWDIO IR_OUT - - - - - -
Pinouts and pin description

PA14 SWCLK USART1_TX - - - - - -
SPI1_NSS, TIM2_CH1_
PA15 USART1_RX EVENTOUT - - - -
I2S1_WS ETR
31/106
Table 13. Alternate functions selected through GPIOB_AFR registers for port B
32/106
Pinouts and pin description

Pin name AF0 AF1 AF2 AF3
PB0 EVENTOUT TIM3_CH3 TIM1_CH2N -

PB1 TIM14_CH1 TIM3_CH4 TIM1_CH3N -
PB2 - - - -
PB3 SPI1_SCK, I2S1_CK EVENTOUT TIM2_CH2 -
PB4 SPI1_MISO, I2S1_MCK TIM3_CH1 EVENTOUT -
PB5 SPI1_MOSI, I2S1_SD TIM3_CH2 TIM16_BKIN I2C1_SMBA
PB6 USART1_TX I2C1_SCL TIM16_CH1N -
PB7 USART1_RX I2C1_SDA TIM17_CH1N -
PB8 - I2C1_SCL TIM16_CH1 -
PB9 IR_OUT I2C1_SDA TIM17_CH1 EVENTOUT
DocID025743 Rev 6
PB10 - I2C1_SCL TIM2_CH3 -

PB11 EVENTOUT I2C1_SDA TIM2_CH4 -
PB12 SPI1_NSS EVENTOUT TIM1_BKIN -
PB13 SPI1_SCK - TIM1_CH1N -
PB14 SPI1_MISO - TIM1_CH2N -
PB15 SPI1_MOSI - TIM1_CH3N -
STM32F031x4 STM32F031x6 Memory mapping
5 Memory mapping
To the difference of STM32F031x6 memory map in Figure 9, the two bottom code memory
spaces of STM32F031x4 end at 0x0000 3FFF and 0x0800 3FFF, respectively.
Figure 9. STM32F031x6 memory map

[))))))))
[))
2ESERVED
!("

[
[(
&RUWH[0LQWHUQDO
[( SHULSKHUDOV
2ESERVED
2ESERVED
[&
[))
!("
2ESERVED
[
2ESERVED
[$
[
2ESERVED [))))))) !0"

2ESERVED
[))))& [
2SWLRQ%\WHV
[ [))))
2ESERVED
6\VWHPPHPRU\
[
2ESERVED
[)))(&
!0"
[
[
2ESERVED
2ESERVED
[ 3HULSKHUDOV
[
2ESERVED

)ODVKPHPRU\
[ 65$0
[
2ESERVED
&2'(
[
&LASHSYSTEM
MEMORYOR32!-
[
DEPENDINGON"//4
CONFIGURATION
[
069
DocID025743 Rev 6 33/106

35
Memory mapping STM32F031x4 STM32F031x6
Table 14. Peripheral register boundary addresses

Bus Boundary address Size Peripheral
0x4800 1800 - 0x5FFF FFFF ~384 MB Reserved

0x4800 1400 - 0x4800 17FF 1KB GPIOF
0x4800 0C00 - 0x4800 13FF 2KB Reserved
AHB2 0x4800 0800 - 0x4800 0BFF 1KB GPIOC
0x4800 0400 - 0x4800 07FF 1KB GPIOB
0x4800 0000 - 0x4800 03FF 1KB GPIOA
0x4002 4400 - 0x47FF FFFF ~128 MB Reserved
0x4002 3400 - 0x4002 3FFF 3 KB Reserved
0x4002 3000 - 0x4002 33FF 1 KB CRC
0x4002 2000 - 0x4002 23FF 1 KB Flash memory interface
AHB1
0x4002 1000 - 0x4002 13FF 1 KB RCC
0x4002 0000 - 0x4002 03FF 1 KB DMA
0x4001 8000 - 0x4001 FFFF 32 KB Reserved
0x4001 5C00 - 0x4001 7FFF 9KB Reserved
0x4001 5800 - 0x4001 5BFF 1KB DBGMCU
0x4001 4800 - 0x4001 4BFF 1KB TIM17
0x4001 4400 - 0x4001 47FF 1KB TIM16
0x4001 3800 - 0x4001 3BFF 1KB USART1
APB 0x4001 3400 - 0x4001 37FF 1KB Reserved
0x4001 3000 - 0x4001 33FF 1KB SPI1/I2S1
0x4001 2C00 - 0x4001 2FFF 1KB TIM1
0x4001 2800 - 0x4001 2BFF 1KB Reserved
0x4001 2400 - 0x4001 27FF 1KB ADC
0x4001 0800 - 0x4001 23FF 7KB Reserved
0x4001 0400 - 0x4001 07FF 1KB EXTI
0x4001 0000 - 0x4001 03FF 1KB SYSCFG
0x4000 8000 - 0x4000 FFFF 32 KB Reserved
34/106 DocID025743 Rev 6

STM32F031x4 STM32F031x6 Memory mapping
Table 14. Peripheral register boundary addresses (continued)

Bus Boundary address Size Peripheral
0x4000 7400 - 0x4000 7FFF 3KB Reserved

0x4000 7000 - 0x4000 73FF 1KB PWR
0x4000 5400 - 0x4000 57FF 1KB I2C1
0x4000 3400 - 0x4000 53FF 8KB Reserved
0x4000 3000 - 0x4000 33FF 1KB IWDG
APB 0x4000 2C00 - 0x4000 2FFF 1KB WWDG
0x4000 2800 - 0x4000 2BFF 1KB RTC
0x4000 2400 - 0x4000 27FF 1KB Reserved
0x4000 2000 - 0x4000 23FF 1KB TIM14
0x4000 0400 - 0x4000 07FF 1KB TIM3
0x4000 0000 - 0x4000 03FF 1KB TIM2
DocID025743 Rev 6 35/106

35
Electrical characteristics STM32F031x4 STM32F031x6
6 Electrical characteristics
6.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.
6.1.1 Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3σ).
6.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3.3 V. They
are given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ±2σ).
6.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 10.
6.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 11.
Figure 10. Pin loading conditions Figure 11. Pin input voltage
0&8SLQ 0&8SLQ
& S) 9,1
069 069
36/106 DocID025743 Rev 6

STM32F031x4 STM32F031x6 Electrical characteristics
6.1.6 Power supply scheme
Figure 12. Power supply scheme
9%$7
/6(57&
±9
:DNHXSORJLF
3RZHUVZLWFK
9'' 9&25(
[9''
5HJXODWRU
9'',2
287
/HYHOVKLIWHU
.HUQHOORJLF
[Q) ,2 &38'LJLWDO
*3,2V ORJLF
[) ,1 0HPRULHV
[966
9''$
9''$
Q) 95() $QDORJ

) $'&
95() 5&V3//«
966$
06Y9
Caution: Each power supply pair (VDD/VSS, VDDA/VSSA etc.) must be decoupled with filtering ceramic
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure the good functionality of
the device.
DocID025743 Rev 6 37/106

80
6.1.7 Current consumption measurement
Figure 13. Current consumption measurement scheme
, ''B9%$7
9%$7
,''
9''
,''$
9''$
069
38/106 DocID025743 Rev 6

6.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 15: Voltage characteristics,
Table 16: Current characteristics and Table 17: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Table 15. Voltage characteristics(1)

Symbol Ratings Min Max Unit
VDD–VSS External main supply voltage - 0.3 4.0 V

VDDA–VSS External analog supply voltage - 0.3 4.0 V
VDD–VDDA Allowed voltage difference for VDD > VDDA - 0.4 V
VBAT–VSS External backup supply voltage - 0.3 4.0 V
Input voltage on FT and FTf pins VSS - 0.3 VDDIOx + 4.0(3) V
Input voltage on TTa pins VSS - 0.3 4.0 V
VIN(2)
BOOT0 0 9.0 V
Input voltage on any other pin VSS - 0.3 4.0 V
|∆VDDx| Variations between different VDD power pins - 50 mV
Variations between all the different ground
|VSSx - VSS| - 50 mV
pins
Electrostatic discharge voltage see Section 6.3.12: Electrical
VESD(HBM) -
(human body model) sensitivity characteristics
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 16: Current characteristics for the maximum
allowed injected current values.
3. Valid only if the internal pull-up/pull-down resistors are disabled. If internal pull-up or pull-down resistor is
enabled, the maximum limit is 4 V.
DocID025743 Rev 6 39/106

80
Table 16. Current characteristics

Symbol Ratings Max. Unit
ΣIVDD Total current into sum of all VDD power lines (source)(1) 120
(1)
ΣIVSS Total current out of sum of all VSS ground lines (sink) -120
(1)
IVDD(PIN) Maximum current into each VDD power pin (source) 100
IVSS(PIN) Maximum current out of each VSS ground pin (sink)(1) -100
Output current sunk by any I/O and control pin 25
IIO(PIN)
Output current source by any I/O and control pin -25
(2)
Total output current sunk by sum of all I/Os and control pins 80
ΣIIO(PIN)
Total output current sourced by sum of all I/Os and control pins(2) -80 mA
Injected current on B, FT and FTf pins -5/+0(4)
IINJ(PIN) (3) Injected current on TC and RST pin ±5
(5)
Injected current on TTa pins ±5
ΣIINJ(PIN) Total injected current (sum of all I/O and control pins)(6) ± 25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the
permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.
3. A positive injection is induced by VIN > VDDIOx while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be
exceeded. Refer to Table 15: Voltage characteristics for the maximum allowed input voltage values.
4. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum
value.
5. On these I/Os, a positive injection is induced by VIN > VDDA. Negative injection disturbs the analog performance of the
device. See note (2) below Table 52: ADC accuracy.
6. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and
negative injected currents (instantaneous values).
Table 17. Thermal characteristics

Symbol Ratings Value Unit
TSTG Storage temperature range –65 to +150 °C

TJ Maximum junction temperature 150 °C
40/106 DocID025743 Rev 6

6.3 Operating conditions
6.3.1 General operating conditions
Table 18. General operating conditions

Symbol Parameter Conditions Min Max Unit
fHCLK Internal AHB clock frequency - 0 48

MHz
fPCLK Internal APB clock frequency - 0 48
VDD Standard operating voltage - 2.0 3.6 V
Analog operating voltage
VDD 3.6
(ADC not used) Must have a potential equal
VDDA V
Analog operating voltage to or higher than VDD
2.4 3.6
(ADC used)
VBAT Backup operating voltage - 1.65 3.6 V
TC and RST I/O –0.3 VDDIOx+0.3
TTa I/O –0.3 VDDA+0.3(1)
VIN I/O input voltage V
FT and FTf I/O –0.3 5.5(1)
BOOT0 0 5.5
LQFP48 - 364
UFQFPN32 - 526
Power dissipation at TA = 85 °C LQFP32 - 357
PD for suffix 6 or TA = 105 °C for mW
suffix 7(2) UFQFPN28 - 169
WLCSP25 - 267
TSSOP20 - 182
Ambient temperature for the Maximum power dissipation –40 85

°C
suffix 6 version Low power dissipation (3) –40 105
TA
Ambient temperature for the Maximum power dissipation –40 105
°C
suffix 7 version Low power dissipation(3) –40 125
Suffix 6 version –40 105
TJ Junction temperature range °C
Suffix 7 version –40 125
1. For operation with a voltage higher than VDDIOx + 0.3 V, the internal pull-up resistor must be disabled.
2. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax. See Section 7.7: Thermal characteristics.
3. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 7.7:
Thermal characteristics).
6.3.2 Operating conditions at power-up / power-down

The parameters given in Table 19 are derived from tests performed under the ambient
temperature condition summarized in Table 18.
DocID025743 Rev 6 41/106

80
Table 19. Operating conditions at power-up / power-down

VDD rise time rate 0 ∞

tVDD -
VDD fall time rate 20 ∞
µs/V
VDDA rise time rate 0 ∞
tVDDA -
VDDA fall time rate 20 ∞
6.3.3 Embedded reset and power control block characteristics

temperature and supply voltage conditions summarized in Table 18: General operating
conditions.
Table 20. Embedded reset and power control block characteristics

Symbol Parameter Conditions Min Typ Max Unit
Power on/power down Falling edge(2) 1.80 1.88 1.96(3) V

VPOR/PDR(1)
reset threshold Rising edge 1.84(3) 1.92 2.00 V
VPDRhyst PDR hysteresis - - 40 - mV
tRSTTEMPO(4) Reset temporization - 1.50 2.50 4.50 ms
1. The PDR detector monitors VDD and also VDDA (if kept enabled in the option bytes). The POR detector
monitors only VDD.
2. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
3. Data based on characterization results, not tested in production.
4. Guaranteed by design, not tested in production.
Table 21. Programmable voltage detector characteristics

Rising edge 2.1 2.18 2.26 V

VPVD0 PVD threshold 0
Falling edge 2 2.08 2.16 V
Rising edge 2.19 2.28 2.37 V
Falling edge 2.09 2.18 2.27 V
Rising edge 2.28 2.38 2.48 V
Rising edge 2.38 2.48 2.58 V
Rising edge 2.47 2.58 2.69 V
Rising edge 2.57 2.68 2.79 V
42/106 DocID025743 Rev 6

Table 21. Programmable voltage detector characteristics (continued)

Rising edge 2.66 2.78 2.9 V

Rising edge 2.76 2.88 3 V
VPVDhyst(1) PVD hysteresis - - 100 - mV
IDD(PVD) PVD current consumption - - 0.15 0.26(1) µA
6.3.4 Embedded reference voltage

conditions.
Table 22. Embedded internal reference voltage

VREFINT Internal reference voltage –40 °C < TA < +105 °C 1.2 1.23 1.25 V
ADC_IN17 buffer startup
tSTART - - - 10(1) µs
time
ADC sampling time when
tS_vrefint reading the internal - 4(1) - - µs
reference voltage
Internal reference voltage
∆VREFINT spread over the VDDA = 3 V - - 10(1) mV
temperature range
TCoeff Temperature coefficient - - 100(1) - 100(1) ppm/°C

6.3.5 Supply current characteristics

The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 13: Current consumption
measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to CoreMark code.
DocID025743 Rev 6 43/106

80
Typical and maximum current consumption

The MCU is placed under the following conditions:
• All I/O pins are in analog input mode
• All peripherals are disabled except when explicitly mentioned
• The Flash memory access time is adjusted to the fHCLK frequency:
– 0 wait state and Prefetch OFF from 0 to 24 MHz
– 1 wait state and Prefetch ON above 24 MHz
• When the peripherals are enabled fPCLK = fHCLK
The parameters given in Table 23Table 23 to Table 27 are derived from tests performed
under ambient temperature and supply voltage conditions summarized in Table 18: General
operating conditions.
Table 23. Typical and maximum current consumption from VDD at 3.6 V
All peripherals enabled All peripherals disabled
Symbol Parameter Conditions fHCLK Max @ TA(1) Max @ TA(1) Unit

Typ Typ
25 °C 85 °C 105 °C 25 °C 85 °C 105 °C
48 MHz 18.4 20.0 20.1 20.4 11.4 12.5 12.5 12.6

HSE
bypass, 32 MHz 12.4 13.2 13.2 13.8 7.9 8.3 8.5 8.6
PLL on
24 MHz 9.9 10.7 10.7 11.0 6.2 6.8 7.0 7.0
Supply
current in HSE 8 MHz 3.3 3.6 3.8 3.9 2.2 2.6 2.6 2.6
Run mode, bypass,
PLL off 1 MHz 0.8 1.1 1.1 1.1 0.7 0.9 0.9 0.9
code
executing 48 MHz 18.9 20.9 21.1 21.5 11.7 12.3 12.9 13.1
from Flash HSI clock,
memory 32 MHz 12.8 13.7 14.2 14.8 8.0 8.7 9.1 9.1
PLL on
24 MHz 9.7 10.4 11.2 11.3 6.1 6.5 6.7 6.9
HSI clock,
8 MHz 3.5 4.0 4.0 4.1 2.4 2.6 2.7 2.7
PLL off
IDD mA
48 MHz 17.3 19.7(2) 19.8 20.0(2) 10.3 11.2(2) 11.3 11.7(2)
HSE
bypass, 32 MHz 11.2 12.5 12.7 12.7 6.7 7.3 7.6 7.6
PLL on
24 MHz 8.9 10.0 10.1 10.2 5.1 5.5 5.8 5.9
Supply HSE 8 MHz 2.8 3.1 3.3 3.4 1.7 2.0 2.1 2.1
current in bypass,
Run mode, PLL off 1 MHz 0.3 0.6 0.6 1.3 0.2 0.5 0.8 0.9
code
executing 48 MHz 17.4 19.7 20.0 20.2 10.4 11.2 11.3 11.8
from RAM HSI clock,
32 MHz 11.8 12.8 13.1 13.3 6.8 7.4 7.7 7.9
PLL on
24 MHz 9.0 10.0 10.1 10.2 5.2 5.7 6.0 6.0
HSI clock,
8 MHz 3.0 3.2 3.5 3.6 1.8 2.0 2.2 2.2
PLL off
44/106 DocID025743 Rev 6

Table 23. Typical and maximum current consumption from VDD at 3.6 V (continued)
All peripherals enabled All peripherals disabled
Symbol Parameter Conditions fHCLK Max @ TA(1) Max @ TA(1) Unit

Typ Typ
25 °C 85 °C 105 °C 25 °C 85 °C 105 °C
48 MHz 10.7 11.7(2) 11.9 12.5(2) 2.4 2.6(2) 2.7 2.9(2)

HSE
bypass, 32 MHz 7.1 7.8 8.1 8.2 1.6 1.7 1.9 1.9
PLL on
24 MHz 5.5 6.3 6.4 6.4 1.3 1.4 1.5 1.5
HSE 8 MHz 1.8 2.0 2.0 2.1 0.4 0.4 0.5 0.5
Supply bypass,
current in PLL off 1 MHz 0.2 0.5 0.5 0.5 0.1 0.1 0.1 0.1
IDD mA
Sleep
mode 48 MHz 10.8 11.9 12.1 12.6 2.4 2.7 2.7 2.9
HSI clock,
32 MHz 7.3 8.0 8.4 8.5 1.7 1.9 1.9 2.0
PLL on
24 MHz 5.5 6.2 6.5 6.5 1.3 1.5 1.5 1.6
HSI clock,
8 MHz 1.9 2.2 2.3 2.4 0.5 0.5 0.5 0.6
PLL off
1. Data based on characterization results, not tested in production unless otherwise specified.
2. Data based on characterization results and tested in production (using one common test limit for sum of IDD and IDDA).
Table 24. Typical and maximum current consumption from the VDDA supply
VDDA = 2.4 V VDDA = 3.6 V
Conditions
Symbol Parameter (1) fHCLK Max @ TA(2) Max @ TA(2) Unit
Typ Typ
25 °C 85 °C 105 °C 25 °C 85 °C 105 °C
48 MHz 150 170(3) 178 182(3) 164 183(3) 195 198(3)

HSE
bypass, 32 MHz 104 121 126 128 113 129 135 138
Supply PLL on
current in 24 MHz 82 96 100 103 88 102 106 108
Run or HSE 8 MHz 2.0 2.7 3.1 3.3 3.5 3.8 4.1 4.4
Sleep bypass,
mode, PLL off 1 MHz 2.0 2.7 3.1 3.3 3.5 3.8 4.1 4.4
IDDA µA
code
executing 48 MHz 220 240 248 252 244 263 275 278
from Flash HSI clock,
32 MHz 174 191 196 198 193 209 215 218
memory or PLL on
RAM 24 MHz 152 167 173 174 168 183 190 192
HSI clock,
8 MHz 72 79 82 83 83.5 91 94 95
PLL off
1. Current consumption from the VDDA supply is independent of whether the digital peripherals are enabled or disabled, being
in Run or Sleep mode or executing from Flash memory or RAM. Furthermore, when the PLL is off, IDDA is independent of
clock frequencies.
DocID025743 Rev 6 45/106

80
Table 25. Typical and maximum current consumption in Stop and Standby modes
Typ @VDD (VDD = VDDA) Max(1)
Sym- Para-
Conditions Unit
bol meter TA = TA = TA =
2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V
25 °C 85 °C 105 °C
Regulator in run
Supply mode, all oscillators 15 15.1 15.3 15.5 15.7 16 18(2) 38 55(2)
current OFF
in Stop Regulator in low-
mode power mode, all 3.2 3.3 3.4 3.5 3.7 4 5.5(2) 22 41(2)
IDD oscillators OFF
Supply LSI ON and IWDG
0.8 1.0 1.1 1.2 1.4 1.5 - - -
current ON
in
Standby LSI OFF and IWDG
0.7 0.8 0.9 1.0 1.1 1.3 2(2) 2.5 3(2)
mode OFF
Regulator in run
Supply mode, all 1.9 2 2.2 2.3 2.5 2.6 3.5(2) 3.5 4.5(2)
current oscillators OFF
VDDA monitoring ON

mode power mode, all 1.9 2 2.2 2.3 2.5 2.6 3.5(2) 3.5 4.5(2)
oscillators OFF µA
Supply LSI ON and
2.3 2.5 2.7 2.9 3.1 3.3 - - -
current IWDG ON
in
Standby LSI OFF and
1.8 1.9 2 2.2 2.3 2.5 3.5(2) 3.5 4.5(2)
mode IWDG OFF
IDDA
Regulator in run
Supply mode, all 1.1 1.2 1.2 1.2 1.3 1.4 - - -
oscillators OFF
VDDA monitoring OFF
current
mode power mode, all 1.1 1.2 1.2 1.2 1.3 1.4 - - -
oscillators OFF
Supply LSI ON and
1.5 1.6 1.7 1.8 1.9 2.0 - - -
current IWDG ON
in
Standby LSI OFF and
1 1.0 1.1 1.1 1.2 1.2 - - -
mode IWDG OFF
46/106 DocID025743 Rev 6

Table 26. Typical and maximum current consumption from the VBAT supply
Typ @ VBAT Max(1)
Symbol Parameter Conditions Unit
1.65 V
2.7 V
TA = TA = TA =
1.8 V
2.4 V
3.3 V
3.6 V
25 °C 85 °C 105 °C
LSE & RTC ON; “Xtal

mode”: lower driving
0.5 0.5 0.6 0.7 0.8 0.9 1.0 1.3 1.7
RTC capability;
domain LSEDRV[1:0] = '00'
IDD_VBAT µA
supply LSE & RTC ON; “Xtal
current mode” higher driving
0.8 0.8 0.9 1.0 1.1 1.2 1.3 1.6 2.1
capability;
LSEDRV[1:0] = '11'
Typical current consumption

The MCU is placed under the following conditions:
• VDD = VDDA = 3.3 V
• All I/O pins are in analog input configuration
• The Flash memory access time is adjusted to fHCLK frequency:
– 0 wait state and Prefetch OFF from 0 to 24 MHz
– 1 wait state and Prefetch ON above 24 MHz
• When the peripherals are enabled, fPCLK = fHCLK
• PLL is used for frequencies greater than 8 MHz
• AHB prescaler of 2, 4, 8 and 16 is used for the frequencies 4 MHz, 2 MHz, 1 MHz and
500 kHz respectively
DocID025743 Rev 6 47/106

80
Table 27. Typical current consumption, code executing from Flash memory,
running from HSE 8 MHz crystal
Typical run mode Typical Sleep mode unit
Symbol fHCLK
Parameter Peripheral Peripheral
Peripheral Peripheral -
s enabled s enabled
s disabled s disabled
48MHz 20.2 12.3 11.1 2.9

36 MHz 15.3 9.5 8.4 2.4
32 MHz 13.6 8.6 7.5 2.2
24 MHz 10.5 6.7 5.9 1.8
Current 16 MHz 7.2 4.7 4.1 1.4
IDD from VDD mA
supply 8 MHz 3.8 2.7 2.3 0.9
4 MHz 2.4 1.8 1.7 0.9
2 MHz 1.6 1.3 1.2 0.8
1 MHz 1.2 1.1 1.0 0.8
500 kHz 1.0 1.0 0.9 0.8
48MHz 155
36 MHz 117
32 MHz 105
24 MHz 83
Current 16 MHz 60
IDDA from VDDA uA
supply 8 MHz 2.2
4 MHz 2.2
2 MHz 2.2
1 MHz 2.2
500 kHz 2.2
I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 46: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
48/106 DocID025743 Rev 6

trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption measured previously (see
Table 29: Peripheral current consumption), the I/Os used by an application also contribute
to the current consumption. When an I/O pin switches, it uses the current from the I/O
supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load
(internal or external) connected to the pin:
I SW = V DDIOx × f SW × C
where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDDIOx is the I/O supply voltage
fSW is the I/O switching frequency
C is the total capacitance seen by the I/O pin: C = CINT + CEXT + CS
CS is the PCB board capacitance including the pad pin.
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
DocID025743 Rev 6 49/106

80
Table 28. Switching output I/O current consumption

I/O toggling
Symbol Parameter Conditions(1) Typ Unit
frequency (fSW)
4 MHz 0.07
8 MHz 0.15
VDDIOx = 3.3 V
C =CINT 16 MHz 0.31
24 MHz 0.53
48 MHz 0.92
4 MHz 0.18
VDDIOx = 3.3 V 8 MHz 0.37

CEXT = 0 pF 16 MHz 0.76
C = CINT + CEXT+ CS 24 MHz 1.39
48 MHz 2.188
4 MHz 0.32

CEXT = 10 pF 16 MHz 1.25
I/O current 48 MHz 4.442

ISW mA
consumption
4 MHz 0.49
VDDIOx = 3.3 V
8 MHz 0.94
CEXT = 22 pF
16 MHz 2.38
C = CINT + CEXT+ CS
24 MHz 3.99
4 MHz 0.64
CEXT = 33 pF
16 MHz 3.24
C = CINT + CEXT+ CS
24 MHz 5.02
CEXT = 47 pF 8 MHz 1.7
C = CINT + CEXT+ CS
C = Cint 16 MHz 3.67
4 MHz 0.66
VDDIOx = 2.4 V
CEXT = 47 pF 8 MHz 1.43
C = Cint
24 MHz 4.97
1. CS = 7 pF (estimated value).
50/106 DocID025743 Rev 6

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in Table 29. The MCU is placed
under the following conditions:
• All I/O pins are in analog mode
• All peripherals are disabled unless otherwise mentioned
• The given value is calculated by measuring the current consumption
– with all peripherals clocked off
– with only one peripheral clocked on
• Ambient operating temperature and supply voltage conditions summarized in Table 15:
Voltage characteristics
• The power consumption of the digital part of the on-chip peripherals is given in
Table 29. The power consumption of the analog part of the peripherals (where
applicable) is indicated in each related section of the datasheet.
Table 29. Peripheral current consumption

Peripheral Typical consumption at 25 °C Unit
BusMatrix(1) 3.8
DMA1 6.3
SRAM 0.7
Flash memory interface 15.2
CRC 1.61
AHB µA/MHz
GPIOA 9.4
GPIOB 11.6
GPIOC 1.9
GPIOF 0.8
All AHB peripherals 47.5
DocID025743 Rev 6 51/106

80
Table 29. Peripheral current consumption (continued)

Peripheral Typical consumption at 25 °C Unit
APB-Bridge (2)
2.6
SYSCFG 1.7
(3)
ADC 4.2
TIM1 17.1
SPI1 9.6
USART1 17.4
TIM16 8.2
TIM17 8.0
APB µA/MHz
DBG (MCU Debug Support) 0.5
TIM2 17.4
TIM3 12.8
TIM14 6.0
WWDG 1.5
I2C1 5.1
PWR 1.2
All APB peripherals 110.9
1. The BusMatrix automatically is active when at least one master is ON (CPU or DMA1).
2. The APBx Bridge is automatically active when at least one peripheral is ON on the same Bus.
3. The power consumption of the analog part (IDDA) of peripherals such as ADC is not included. Refer to the
tables of characteristics in the subsequent sections.
52/106 DocID025743 Rev 6

6.3.6 Wakeup time from low-power mode

The wakeup times given in Table 30 are the latency between the event and the execution of
the first user instruction. The device goes in low-power mode after the WFE (Wait For
Event) instruction, in the case of a WFI (Wait For Interruption) instruction, 16 CPU cycles
must be added to the following timings due to the interrupt latency in the Cortex M0
architecture.
The SYSCLK clock source setting is kept unchanged after wakeup from Sleep mode.
During wakeup from Stop or Standby mode, SYSCLK takes the default setting: HSI 8 MHz.
The wakeup source from Sleep and Stop mode is an EXTI line configured in event mode.
The wakeup source from Standby mode is the WKUP1 pin (PA0).
All timings are derived from tests performed under the ambient temperature and supply
voltage conditions summarized in Table 18: General operating conditions..
Table 30. Low-power mode wakeup timings

Typ @VDD = VDDA
Symbol Parameter Conditions Max Unit
= 2.0 V = 2.4 V = 2.7 V =3V = 3.3 V
Regulator in run
3.2 3.1 2.9 2.9 2.8 5
Wakeup from Stop mode
tWUSTOP
mode Regulator in low
7.0 5.8 5.2 4.9 4.6 9
power mode
µs
Wakeup from
tWUSTANDBY - 60.4 55.6 53.5 52 51 -
Standby mode
Wakeup from Sleep
tWUSLEEP - 4 SYSCLK cycles -
mode
6.3.7 External clock source characteristics

High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.14. However,
the recommended clock input waveform is shown in Figure 14: High-speed external clock
source AC timing diagram.
Table 31. High-speed external user clock characteristics

Symbol Parameter(1) Min Typ Max Unit
fHSE_ext User external clock source frequency - 8 32 MHz

VHSEH OSC_IN input pin high level voltage 0.7 VDDIOx - VDDIOx
V
VHSEL OSC_IN input pin low level voltage VSS - 0.3 VDDIOx
tw(HSEH)
OSC_IN high or low time 15 - -
tw(HSEL)
ns
tr(HSE)
OSC_IN rise or fall time - - 20
tf(HSE)
DocID025743 Rev 6 53/106

80
Figure 14. High-speed external clock source AC timing diagram
WZ+6(+
9+6(+

9+6(/
WU+6( W
WI+6( WZ+6(/
7+6(
069
Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.14. However,
the recommended clock input waveform is shown in Figure 15.
Table 32. Low-speed external user clock characteristics

Symbol Parameter(1) Min Typ Max Unit
fLSE_ext User external clock source frequency - 32.768 1000 kHz

VLSEH OSC32_IN input pin high level voltage 0.7 VDDIOx - VDDIOx
V
VLSEL OSC32_IN input pin low level voltage VSS - 0.3 VDDIOx
tw(LSEH)
OSC32_IN high or low time 450 - -
tw(LSEL)
ns
tr(LSE)
OSC32_IN rise or fall time - - 50
tf(LSE)
Figure 15. Low-speed external clock source AC timing diagram
WZ/6(+
9/6(+

9/6(/
WU/6( W
WI/6( WZ/6(/
7/6(
069
54/106 DocID025743 Rev 6

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Table 33. In the
application, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins in order to minimize output distortion and startup stabilization time. Refer
to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).
Table 33. HSE oscillator characteristics

Symbol Parameter Conditions(1) Min(2) Typ Max(2) Unit
fOSC_IN Oscillator frequency - 4 8 32 MHz

RF Feedback resistor - - 200 - kΩ
(3)
During startup - - 8.5
VDD = 3.3 V,
Rm = 30 Ω, - 0.4 -
CL = 10 pF@8 MHz
VDD = 3.3 V,
Rm = 45 Ω, - 0.5 -
CL = 10 pF@8 MHz
IDD HSE current consumption VDD = 3.3 V, mA

Rm = 30 Ω, - 0.8 -
CL = 5 pF@32 MHz
VDD = 3.3 V,
Rm = 30 Ω, - 1 -
CL = 10 pF@32 MHz
VDD = 3.3 V,
Rm = 30 Ω, - 1.5 -
CL = 20 pF@32 MHz
gm Oscillator transconductance Startup 10 - - mA/V
tSU(HSE)(4) Startup time VDD is stabilized - 2 - ms
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 20 pF range (Typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 16). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2.
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
DocID025743 Rev 6 55/106

80
Figure 16. Typical application with an 8 MHz crystal
5HVRQDWRUZLWKLQWHJUDWHG
FDSDFLWRUV
&/
26&B,1 I+6(
%LDV
0+] FRQWUROOHG
UHVRQDWRU 5) JDLQ
5(;7 26&B287
&/
069
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator
oscillator. All the information given in this paragraph are based on design simulation results
obtained with typical external components specified in Table 34. In the application, the
resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
Table 34. LSE oscillator characteristics (fLSE = 32.768 kHz)

Symbol Parameter Conditions(1) Min(2) Typ Max(2) Unit
low drive capability - 0.5 0.9

medium-low drive capability - - 1
IDD LSE current consumption µA
medium-high drive capability - - 1.3
high drive capability - - 1.6
low drive capability 5 - -
Oscillator medium-low drive capability 8 - -

gm µA/V
transconductance medium-high drive capability 15 - -
high drive capability 25 - -
tSU(LSE) (3)
Startup time VDDIOx is stabilized - 2 - s
1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers”.
3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is
reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer
56/106 DocID025743 Rev 6

Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 17. Typical application with a 32.768 kHz crystal
5HVRQDWRUZLWKLQWHJUDWHG
FDSDFLWRUV
&/
26&B,1 I/6(
N+] 'ULYH
UHVRQDWRU SURJUDPPDEOH
DPSOLILHU
26&B287
&/
069
Note: An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.
6.3.8 Internal clock source characteristics

The parameters given in Table 35 are derived from tests performed under ambient
conditions. The provided curves are characterization results, not tested in production.
DocID025743 Rev 6 57/106

80
High-speed internal (HSI) RC oscillator
Table 35. HSI oscillator characteristics(1)

fHSI Frequency - - 8 - MHz

(2)
TRIM HSI user trimming step - - - 1 %
DuCy(HSI) (2) (2)
Duty cycle - 45 - 55 %
(3) (3)
TA = -40 to 105°C -2.8 - 3.8
TA = -10 to 85°C -1.9(3) - 2.3(3)
Accuracy of the HSI TA = 0 to 85°C -1.9(3) - 2(3)

ACCHSI %
oscillator TA = 0 to 70°C -1.3(3) - 2(3)
TA = 0 to 55°C -1(3) - 2(3)
TA = 25°C(4) -1 - 1
tsu(HSI) HSI oscillator startup time - 1(2) - 2(2) µs
HSI oscillator power
IDDA(HSI) - - 80 100(2) µA
consumption
1. VDDA = 3.3 V, TA = -40 to 105°C unless otherwise specified.
4. Factory calibrated, parts not soldered.
Figure 18. HSI oscillator accuracy characterization results for soldered parts
."9
.*/

5<$>
"

069
58/106 DocID025743 Rev 6

High-speed internal 14 MHz (HSI14) RC oscillator (dedicated to ADC)
Table 36. HSI14 oscillator characteristics(1)

fHSI14 Frequency - - 14 - MHz

(2)
TRIM HSI14 user-trimming step - - - 1 %
DuCy(HSI14) Duty cycle (2) (2)
- 45 - 55 %
TA = –40 to 105 °C –4.2 (3) (3)
- 5.1 %
Accuracy of the HSI14 TA = –10 to 85 °C –3.2(3) - 3.1(3) %

ACCHSI14
oscillator (factory calibrated) TA = 0 to 70 °C –2.5 (3)
- 2.3 (3)
%
TA = 25 °C –1 - 1 %
tsu(HSI14) HSI14 oscillator startup time - 1(2) - 2(2) µs
HSI14 oscillator power
IDDA(HSI14) - - 100 150(2) µA
consumption
1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
Figure 19. HSI14 oscillator accuracy characterization results

-!8

-).

4; #=
!

-36
DocID025743 Rev 6 59/106

80
Low-speed internal (LSI) RC oscillator
Table 37. LSI oscillator characteristics(1)

Symbol Parameter Min Typ Max Unit
fLSI Frequency 30 40 50 kHz

(2)
tsu(LSI) LSI oscillator startup time - - 85 µs
IDDA(LSI)(2) LSI oscillator power consumption - 0.75 1.2 µA
1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
6.3.9 PLL characteristics

The parameters given in Table 38 are derived from tests performed under ambient
conditions.
Table 38. PLL characteristics

Value
Symbol Parameter Unit
Min Typ Max
PLL input clock(1) 1(2) 8.0 24(2) MHz

fPLL_IN
(2)
PLL input clock duty cycle 40 - 60(2) %
fPLL_OUT PLL multiplier output clock 16(2) - 48 MHz
tLOCK PLL lock time - - 200(2) µs
JitterPLL Cycle-to-cycle jitter - - 300(2) ps
1. Take care to use the appropriate multiplier factors to obtain PLL input clock values compatible with the
range defined by fPLL_OUT.
6.3.10 Memory characteristics

Flash memory
The characteristics are given at TA = –40 to 105 °C unless otherwise specified.
Table 39. Flash memory characteristics

Symbol Parameter Conditions Min Typ Max(1) Unit
tprog 16-bit programming time TA = - 40 to +105 °C 40 53.5 60 µs

tERASE Page (1 KB) erase time TA = - 40 to +105 °C 20 - 40 ms
tME Mass erase time TA = - 40 to +105 °C 20 - 40 ms
Write mode - - 10 mA
IDD Supply current
Erase mode - - 12 mA
60/106 DocID025743 Rev 6

Table 40. Flash memory endurance and data retention

Symbol Parameter Conditions Min(1) Unit
NEND Endurance TA = –40 to +105 °C 10 kcycle

1 kcycle(2) at TA = 85 °C 30
tRET (2)
Data retention 1 kcycle at TA = 105 °C 10 Year
10 kcycle(2) at TA = 55 °C 20
2. Cycling performed over the whole temperature range.
6.3.11 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 41. They are based on the EMS levels and classes
defined in application note AN1709.
Table 41. EMS characteristics

Level/
Symbol Parameter Conditions
Class
VDD = 3.3 V, LQFP48, TA = +25 °C,

Voltage limits to be applied on any I/O pin
VFESD fHCLK = 48 MHz, 2B
to induce a functional disturbance
conforming to IEC 61000-4-2
Fast transient voltage burst limits to be VDD = 3.3 V, LQFP48, TA = +25°C,
VEFTB applied through 100 pF on VDD and VSS fHCLK = 48 MHz, 4B
pins to induce a functional disturbance conforming to IEC 61000-4-4
Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
DocID025743 Rev 6 61/106

80
Software recommendations
The software flowchart must include the management of runaway conditions such as:
• Corrupted program counter
• Unexpected reset
• Critical Data corruption (for example control registers)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 42. EMI characteristics

Max vs. [fHSE/fHCLK]
Monitored
Symbol Parameter Conditions Unit
frequency band
8/48 MHz
0.1 to 30 MHz -11

VDD = 3.6 V, TA = 25 °C,
LQFP48 package 30 to 130 MHz 21 dBµV
SEMI Peak level
compliant with 130 MHz to 1 GHz 21
IEC 61967-2
EMI Level 4 -
6.3.12 Electrical sensitivity characteristics

Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
62/106 DocID025743 Rev 6

Table 43. ESD absolute maximum ratings

Maximum
Symbol Ratings Conditions Packages Class Unit
value(1)
Electrostatic discharge voltage TA = +25 °C, conforming

VESD(HBM) All 2 2000 V
(human body model) to JESD22-A114
Electrostatic discharge voltage TA = +25 °C, conforming
VESD(CDM) All C3 250 V
(charge device model) to ANSI/ESD STM5.3.1
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
• A supply overvoltage is applied to each power supply pin.
• A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 44. Electrical sensitivities

Symbol Parameter Conditions Class
LU Static latch-up class TA = +105 °C conforming to JESD78A II level A
6.3.13 I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDDIOx (for standard, 3.3 V-capable I/O pins) should be avoided during normal
product operation. However, in order to give an indication of the robustness of the
microcontroller in cases when abnormal injection accidentally happens, susceptibility tests
are performed on a sample basis during device characterization.
Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of the -5 µA/+0 µA range) or other functional failure (for example reset occurrence or
oscillator frequency deviation).
The characterization results are given in Table 45.
Negative induced leakage current is caused by negative injection and positive induced
leakage current is caused by positive injection.
DocID025743 Rev 6 63/106

80
Table 45. I/O current injection susceptibility

Functional
susceptibility
Symbol Description Unit
Negative Positive
injection injection
Injected current on BOOT0 –0 NA

IINJ Injected current on all FT and FTf pins –5 NA mA
Injected current on all TTa, TC and RESET pins –5 +5
6.3.14 I/O port characteristics

General input/output characteristics
Unless otherwise specified, the parameters given in Table 46 are derived from tests
performed under the conditions summarized in Table 18: General operating conditions. All
I/Os are designed as CMOS- and TTL-compliant (except BOOT0).
Table 46. I/O static characteristics

TC and TTa I/O - - 0.3 VDDIOx+0.07(1)

FT and FTf I/O - - 0.475 VDDIOx–0.2(1)
Low level input
VIL BOOT0 - - 0.3 VDDIOx–0.3(1) V
voltage
All I/Os except
- - 0.3 VDDIOx
BOOT0 pin
TC and TTa I/O 0.445 VDDIOx+0.398(1) - -
FT and FTf I/O 0.5 VDDIOx +0.2(1) - -
High level input
VIH BOOT0 0.2 VDDIOx +0.95(1) - - V
voltage
All I/Os except
0.7 VDDIOx - -
BOOT0 pin
TC and TTa I/O - 200(1) -
Schmitt trigger (1)
Vhys FT and FTf I/O - 100 - mV
hysteresis
(1)
BOOT0 - 300 -
TC, FT and FTf I/O
TTa in digital mode - - ± 0.1
VSS ≤ VIN ≤ VDDIOx
TTa in digital mode
Input leakage - - 1
Ilkg VDDIOx ≤ VIN ≤ VDDA µA
current(2)
TTa in analog mode
- - ± 0.2
VSS ≤ VIN ≤ VDDA
FT and FTf I/O
- - 10
VDDIOx ≤ VIN ≤ 5 V
64/106 DocID025743 Rev 6

Table 46. I/O static characteristics (continued)

Weak pull-up
RPU equivalent resistor VIN = VSS 25 40 55 kΩ
(3)
Weak pull-down
RPD equivalent VIN = - VDDIOx 25 40 55 kΩ
resistor(3)
CIO I/O pin capacitance - - 5 - pF
1. Data based on design simulation only. Not tested in production.
2. The leakage could be higher than the maximum value, if negative current is injected on adjacent pins. Refer to Table 45:
I/O current injection susceptibility.
3. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10% order).
All I/Os are CMOS- and TTL-compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 20 for standard I/Os, and in Figure 21 for
5 V-tolerant I/Os. The following curves are design simulation results, not tested in
production.
DocID025743 Rev 6 65/106

80
Figure 20. TC and TTa I/O input characteristics

7(67('5$1*(
77/VWDQGDUGUHTXLUHPHQW
HQW
HTX LUHP
QG DUGU
6VWD
9,19 &02
[

9 '',2

9 ,+PLQ
',2[
81'(),1(',13875$1*(
9'
9,+PLQ

9'',2[
9,/PD[ XLUHPHQW
& 0 2 6 V WDQGDUGUHT

9'',2[
9,/PD[
7(67('5$1*(

9'',2[9
06Y9
Figure 21. Five volt tolerant (FT and FTf) I/O input characteristics

7(67('5$1*(
HQW
HTX LUHP
QG DUGU
6VWD
9,19 &02
[

9 '',2
81'(),1(',13875$1*(
9 ,+PLQ

'',2[
9
9,+PLQ

'',2[
9
9,/PD[ 77/VWDQGDUGUHTXLUHPHQW
XLUHPHQW
WD QGDUGUHT
[
&026V
9'',2
9,/PD[
7(67('5$1*(

9'',2[9
06Y9
66/106 DocID025743 Rev 6

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or
source up to +/- 20 mA (with a relaxed VOL/VOH).
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2:
• The sum of the currents sourced by all the I/Os on VDDIOx, plus the maximum
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
ΣIVDD (see Table 15: Voltage characteristics).
• The sum of the currents sunk by all the I/Os on VSS, plus the maximum consumption of
the MCU sunk on VSS, cannot exceed the absolute maximum rating ΣIVSS (see
Table 15: Voltage characteristics).
Output voltage levels

Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 18: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT, TTa or
TC unless otherwise specified).
Table 47. Output voltage characteristics(1)

VOL Output low level voltage for an I/O pin CMOS port(2) - 0.4
|IIO| = 8 mA V
VOH Output high level voltage for an I/O pin VDDIOx ≥ 2.7 V VDDIOx–0.4 -
VOL Output low level voltage for an I/O pin TTL port(2) - 0.4
|IIO| = 8 mA V
VOH Output high level voltage for an I/O pin VDDIOx ≥ 2.7 V 2.4 -
VOL(3) Output low level voltage for an I/O pin |IIO| = 20 mA - 1.3
V
VOH(3) Output high level voltage for an I/O pin VDDIOx ≥ 2.7 V VDDIOx–1.3 -
VOL(3) Output low level voltage for an I/O pin - 0.4
|IIO| = 6 mA V
VOH(3) Output high level voltage for an I/O pin VDDIOx–0.4 -
|IIO| = 20 mA
Output low level voltage for an FTf I/O pin in - 0.4 V
VOLFm+(3) VDDIOx ≥ 2.7 V
Fm+ mode
|IIO| = 10 mA - 0.4 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 15:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings ΣIIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Data based on characterization results. Not tested in production.
DocID025743 Rev 6 67/106

80
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 22 and
Table 48, respectively. Unless otherwise specified, the parameters given are derived from
tests performed under the ambient temperature and supply voltage conditions summarized
in Table 18: General operating conditions.
Table 48. I/O AC characteristics(1)(2)

OSPEEDRy
[1:0] Symbol Parameter Conditions Min Max Unit
value(1)
fmax(IO)out Maximum frequency(3) - 2 MHz

x0 tf(IO)out Output fall time CL = 50 pF - 125
ns
tr(IO)out Output rise time - 125
01 tf(IO)out Output fall time CL = 50 pF - 25
ns
CL = 30 pF, VDDIOx ≥ 2.7 V - 50
fmax(IO)out Maximum frequency(3) CL = 50 pF, VDDIOx ≥ 2.7 V - 30 MHz
CL = 50 pF, VDDIOx < 2.7 V - 20
CL = 30 pF, VDDIOx ≥ 2.7 V - 5
11 tf(IO)out Output fall time CL = 50 pF, VDDIOx ≥ 2.7 V - 8
CL = 50 pF, VDDIOx < 2.7 V - 12
ns
CL = 30 pF, VDDIOx ≥ 2.7 V - 5
tr(IO)out Output rise time CL = 50 pF, VDDIOx ≥ 2.7 V - 8
CL = 50 pF, VDDIOx < 2.7 V - 12
Fm+
configuration tf(IO)out Output fall time CL = 50 pF - 12
(4) ns
Pulse width of external
- tEXTIpw signals detected by - 10 - ns
the EXTI controller
1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the STM32F0xxxx RM0091 reference
manual for a description of GPIO Port configuration register.
3. The maximum frequency is defined in Figure 22.
4. When Fm+ configuration is set, the I/O speed control is bypassed. Refer to the STM32F0xxxx reference
manual RM0091 for a detailed description of Fm+ I/O configuration.
68/106 DocID025743 Rev 6

Figure 22. I/O AC characteristics definition

W U,2RXW W I,2RXW
0D[LPXPIUHTXHQF\LVDFKLHYHGLIWW 7DQGLIWKHGXW\F\FOHLV

U I
ZKHQORDGHGE\&VHHWKHWDEOH,2$&FKDUDFWHULVWLFVGHILQLWLRQ
-
069
6.3.15 NRST pin characteristics

The NRST pin input driver uses the CMOS technology. It is connected to a permanent pull-
up resistor, RPU.
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 18: General operating conditions.
Table 49. NRST pin characteristics

VIL(NRST) NRST input low level voltage - - - 0.3 VDD+0.07(1)

V
VIH(NRST) NRST input high level voltage - 0.445 VDD+0.398(1) - -
NRST Schmitt trigger voltage
Vhys(NRST) - - 200 - mV
hysteresis
Weak pull-up equivalent
RPU VIN = VSS 25 40 55 kΩ
resistor(2)
VF(NRST) NRST input filtered pulse - - - 100(1) ns
2.7 < VDD < 3.6 300(3) - -
VNF(NRST) NRST input not filtered pulse ns
(3)
2.0 < VDD < 3.6 500 - -
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance is minimal (~10% order).
DocID025743 Rev 6 69/106

80
Figure 23. Recommended NRST pin protection
([WHUQDO
UHVHWFLUFXLW 9''
538
1567 ,QWHUQDOUHVHW
)LOWHU
)
069
1. The external capacitor protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 49: NRST pin characteristics. Otherwise the reset will not be taken into account by the device.
6.3.16 12-bit ADC characteristics

Unless otherwise specified, the parameters given in Table 50 are derived from tests
performed under the conditions summarized in Table 18: General operating conditions.
Note: It is recommended to perform a calibration after each power-up.
Table 50. ADC characteristics

Analog supply voltage for

VDDA - 2.4 - 3.6 V
ADC ON
Current consumption of
IDDA (ADC) VDDA = 3.3 V - 0.9 - mA
the ADC(1)
fADC ADC clock frequency - 0.6 - 14 MHz
fS(2) Sampling rate 12-bit resolution 0.043 - 1 MHz
fADC = 14 MHz,
- - 823 kHz
fTRIG(2) External trigger frequency 12-bit resolution
12-bit resolution - - 17 1/fADC
VAIN Conversion voltage range - 0 - VDDA V
See Equation 1 and
RAIN(2) External input impedance - - 50 kΩ
Table 51 for details
Sampling switch
RADC(2) - - - 1 kΩ
resistance
Internal sample and hold
CADC(2) - - - 8 pF
capacitor
fADC = 14 MHz 5.9 µs
tCAL(2)(3) Calibration time
- 83 1/fADC
70/106 DocID025743 Rev 6

Table 50. ADC characteristics (continued)

1.5 ADC 1.5 ADC

ADC clock = HSI14 cycles + 2 - cycles + 3 -
fPCLK cycles fPCLK cycles
ADC_DR register ready
WLATENCY(2)(4) fPCLK
latency ADC clock = PCLK/2 - 4.5 -
cycle
fPCLK
ADC clock = PCLK/4 - 8.5 -
cycle
fADC = fPCLK/2 = 14 MHz 0.196 µs
fADC = fPCLK/2 5.5 1/fPCLK
(2) Trigger conversion latency fADC = fPCLK/4 = 12 MHz 0.219 µs
tlatr
fADC = fPCLK/4 10.5 1/fPCLK
fADC = fHSI14 = 14 MHz 0.179 - 0.250 µs
ADC jitter on trigger
JitterADC fADC = fHSI14 - 1 - 1/fHSI14
conversion
fADC = 14 MHz 0.107 - 17.1 µs
tS(2) Sampling time
- 1.5 - 239.5 1/fADC
tSTAB(2) Stabilization time - 14 1/fADC
fADC = 14 MHz,
1 - 18 µs
Total conversion time 12-bit resolution
tCONV(2)
(including sampling time) 14 to 252 (tS for sampling +12.5 for
12-bit resolution 1/fADC
successive approximation)
1. During conversion of the sampled value (12.5 x ADC clock period), an additional consumption of 100 µA on IDDA and 60 µA
on IDD should be taken into account.
3. Specified value includes only ADC timing. It does not include the latency of the register access.
4. This parameter specify latency for transfer of the conversion result to the ADC_DR register. EOC flag is set at this time.
Equation 1: RAIN max formula

TS
R AIN < ---------------------------------------------------------------
N+2
- – R ADC
f ADC × C ADC × ln ( 2 )
The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
Table 51. RAIN max for fADC = 14 MHz

Ts (cycles) tS (µs) RAIN max (kΩ)(1)
1.5 0.11 0.4

7.5 0.54 5.9
13.5 0.96 11.4
DocID025743 Rev 6 71/106

80
Table 51. RAIN max for fADC = 14 MHz (continued)

Ts (cycles) tS (µs) RAIN max (kΩ)(1)
28.5 2.04 25.2

41.5 2.96 37.2
55.5 3.96 50
71.5 5.11 NA
239.5 17.1 NA
Table 52. ADC accuracy(1)(2)(3)

Symbol Parameter Test conditions Typ Max(4) Unit
ET Total unadjusted error ±1.3 ±2

EO Offset error fPCLK = 48 MHz, ±1 ±1.5
fADC = 14 MHz, RAIN < 10 kΩ
EG Gain error ±0.5 ±1.5 LSB
VDDA = 3 V to 3.6 V
ED Differential linearity error TA = 25 °C ±0.7 ±1
EL Integral linearity error ±0.8 ±1.5
EO Offset error fPCLK = 48 MHz, ±1.9 ±2.8
EG Gain error ±2.8 ±3 LSB
VDDA = 2.7 V to 3.6 V
ED Differential linearity error TA = - 40 to 105 °C ±0.7 ±1.3
EO Offset error fPCLK = 48 MHz, ±1.9 ±2.8
EG Gain error ±2.8 ±3 LSB
VDDA = 2.4 V to 3.6 V
ED Differential linearity error TA = 25 °C ±0.7 ±1.3
1. ADC DC accuracy values are measured after internal calibration.
2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-robust) analog input
pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog
input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject
negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.14 does not affect the ADC
accuracy.
3. Better performance may be achieved in restricted VDDA, frequency and temperature ranges.
72/106 DocID025743 Rev 6

Figure 24. ADC accuracy characteristics
966$
(* ([DPSOHRIDQDFWXDOWUDQVIHUFXUYH

7KHLGHDOWUDQVIHUFXUYH
(QGSRLQWFRUUHODWLRQOLQH

(7 7RWDO8QDMXVWHG(UURUPD[LPXPGHYLDWLRQ
EHWZHHQWKHDFWXDODQGLGHDOWUDQVIHUFXUYHV
(7 (2 2IIVHW(UURUPD[LPXPGHYLDWLRQ

EHWZHHQWKHILUVWDFWXDOWUDQVLWLRQDQGWKHILUVW

LGHDORQH
(* *DLQ(UURUGHYLDWLRQEHWZHHQWKHODVW

(2 (/
LGHDOWUDQVLWLRQDQGWKHODVWDFWXDORQH
(' 'LIIHUHQWLDO/LQHDULW\(UURUPD[LPXP
GHYLDWLRQEHWZHHQDFWXDOVWHSVDQGWKHLGHDORQHV
('
(/ ,QWHJUDO/LQHDULW\(UURUPD[LPXPGHYLDWLRQ

EHWZHHQDQ\DFWXDOWUDQVLWLRQDQGWKHHQGSRLQW
/6%,'($/
FRUUHODWLRQOLQH
9''$

069
Figure 25. Typical connection diagram using the ADC
9''$
6DPSOHDQGKROG$'&
97
FRQYHUWHU
5$,1 $,1[ 5$'&

ELW
,/ $ FRQYHUWHU
&SDUDVLWLF 97
9$,1
&$'&
069
1. Refer to Table 50: ADC characteristics for the values of RAIN, RADC and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 12: Power supply
scheme. The 10 nF capacitor should be ceramic (good quality) and it should be placed as
close as possible to the chip.
DocID025743 Rev 6 73/106

80
6.3.17 Temperature sensor characteristics
Table 53. TS characteristics

TL(1) VSENSE linearity with temperature - ±1 ±2 °C

(1)
Avg_Slope Average slope 4.0 4.3 4.6 mV/°C
(2)
V30 Voltage at 30 °C (± 5 °C) 1.34 1.43 1.52 V
tSTART(1) ADC_IN16 buffer startup time - - 10 µs
ADC sampling time when reading the
tS_temp(1) 4 - - µs
temperature
2. Measured at VDDA = 3.3 V ± 10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte. Refer to Table 3:
Temperature sensor calibration values.
6.3.18 VBAT monitoring characteristics
Table 54. VBAT monitoring characteristics

R Resistor bridge for VBAT - 2 x 50 - kΩ

Q Ratio on VBAT measurement - 2 - -
Er(1) Error on Q –1 - +1 %
tS_vbat(1) ADC sampling time when reading the VBAT 4 - - µs
6.3.19 Timer characteristics

The parameters given in the following tables are guaranteed by design.
Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Table 55. TIMx characteristics

- - 1 - tTIMxCLK
tres(TIM) Timer resolution time
fTIMxCLK = 48 MHz - 20.8 - ns
Timer external clock - - fTIMxCLK/2 - MHz
fEXT frequency on CH1 to
CH4 fTIMxCLK = 48 MHz - 24 - MHz
16-bit timer maximum - - 216 - tTIMxCLK

period fTIMxCLK = 48 MHz - 1365 - µs
tMAX_COUNT
32-bit counter - - 232 - tTIMxCLK
maximum period fTIMxCLK = 48 MHz - 89.48 - s
74/106 DocID025743 Rev 6

Table 56. IWDG min/max timeout period at 40 kHz (LSI)(1)

Min timeout RL[11:0]= Max timeout RL[11:0]=
Prescaler divider PR[2:0] bits Unit
0x000 0xFFF
/4 0 0.1 409.6
/8 1 0.2 819.2
/16 2 0.4 1638.4
/32 3 0.8 3276.8 ms
/64 4 1.6 6553.6
/128 5 3.2 13107.2
/256 6 or 7 6.4 26214.4
1. These timings are given for a 40 kHz clock but the microcontroller internal RC frequency can vary from 30
to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing
of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty.
Table 57. WWDG min/max timeout value at 48 MHz (PCLK)

Prescaler WDGTB Min timeout value Max timeout value Unit
1 0 0.0853 5.4613
2 1 0.1706 10.9226
ms
4 2 0.3413 21.8453
8 3 0.6826 43.6906
6.3.20 Communication interfaces

I2C interface characteristics
The I2C interface meets the timings requirements of the I2C-bus specification and user
manual rev. 03 for:
• Standard-mode (Sm): with a bit rate up to 100 kbit/s
• Fast-mode (Fm): with a bit rate up to 400 kbit/s
• Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
The I2C timings requirements are guaranteed by design when the I2Cx peripheral is
properly configured (refer to Reference manual).
The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and VDDIOx is disabled, but is still present. Only FTf I/O pins
support Fm+ low level output current maximum requirement. Refer to Section 6.3.14: I/O
port characteristics for the I2C I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog
filter characteristics:
DocID025743 Rev 6 75/106

80
Table 58. I2C analog filter characteristics(1)

Symbol Parameter Min Max Unit
Maximum width of spikes that are

tAF 50(2) 260(3) ns
suppressed by the analog filter
2. Spikes with widths below tAF(min) are filtered.
3. Spikes with widths above tAF(max) are not filtered
SPI/I2S characteristics
Unless otherwise specified, the parameters given in Table 59 for SPI or in Table 60 for I2S
are derived from tests performed under the ambient temperature, fPCLKx frequency and
supply voltage conditions summarized in Table 18: General operating conditions.
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S).
Table 59. SPI characteristics(1)

fSCK Master mode - 18

SPI clock frequency MHz
1/tc(SCK) Slave mode - 18
tr(SCK) SPI clock rise and fall
Capacitive load: C = 15 pF - 6 ns
tf(SCK) time
tsu(NSS) NSS setup time Slave mode 4Tpclk -
th(NSS) NSS hold time Slave mode 2Tpclk + 10 -
tw(SCKH) Master mode, fPCLK = 36 MHz,
SCK high and low time Tpclk/2 -2 Tpclk/2 + 1
tw(SCKL) presc = 4
tsu(MI) Master mode 4 -

Data input setup time
tsu(SI) Slave mode 5 -
th(MI) Master mode 4 -
Data input hold time ns
th(SI) Slave mode 5 -
ta(SO)(2) Data output access time Slave mode, fPCLK = 20 MHz 0 3Tpclk
(3)
tdis(SO) Data output disable time Slave mode 0 18
tv(SO) Data output valid time Slave mode (after enable edge) - 22.5
tv(MO) Data output valid time Master mode (after enable edge) - 6
th(SO) Slave mode (after enable edge) 11.5 -
Data output hold time
th(MO) Master mode (after enable edge) 2 -
SPI slave input clock
DuCy(SCK) Slave mode 25 75 %
duty cycle
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z
76/106 DocID025743 Rev 6

Figure 26. SPI timing diagram - slave mode and CPHA = 0
166LQSXW
WF6&. WK166
WVX166 WZ6&.+ WU6&.

&3+$
6&.LQSXW
&32/
&3+$
&32/
WD62 WZ6&./ WY62 WK62 WI6&. WGLV62
0,62RXWSXW )LUVWELW287 1H[WELWV287 /DVWELW287
WK6,
WVX6,
026,LQSXW )LUVWELW,1 1H[WELWV,1 /DVWELW,1
06Y9
Figure 27. SPI timing diagram - slave mode and CPHA = 1
166LQSXW
WF6&.
WVX166 WZ6&.+ WI6&. WK166

&3+$
6&.LQSXW
&32/
&3+$
&32/
WD62 WZ6&./ WY62 WK62 WU6&. WGLV62
0,62RXWSXW )LUVWELW287 1H[WELWV287 /DVWELW287
WVX6, WK6,
026,LQSXW )LUVWELW,1 1H[WELWV,1 /DVWELW,1
06Y9
1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.
DocID025743 Rev 6 77/106

80
Figure 28. SPI timing diagram - master mode
+LJK
166LQSXW
WF6&.
6&.2XWSXW
&3+$
&32/
&3+$
&32/
6&.2XWSXW
&3+$
&32/
&3+$
&32/
WZ6&.+ WU6&.
WVX0, WZ6&./ WI6&.
0,62
,13 87 06%,1 %,7,1 /6%,1
WK0,
026,
06%287 % , 7287 /6%287
287387
WY02 WK02
DLF
1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.
Table 60. I2S characteristics(1)

Master mode (data: 16 bits, Audio

fCK 1.597 1.601
I2S clock frequency frequency = 48 kHz) MHz
1/tc(CK)
Slave mode 0 6.5
tr(CK) I2S clock rise time - 10
Capacitive load CL = 15 pF
tf(CK) I2S clock fall time - 12
tw(CKH) I2S clock high time Master fPCLK= 16 MHz, audio 306 -
tw(CKL) 2
I S clock low time frequency = 48 kHz 312 -
ns
tv(WS) WS valid time Master mode 2 -
th(WS) WS hold time Master mode 2 -
tsu(WS) WS setup time Slave mode 7 -
th(WS) WS hold time Slave mode 0 -
I2S slave input clock duty
DuCy(SCK) Slave mode 25 75 %
cycle
78/106 DocID025743 Rev 6

Table 60. I2S characteristics(1) (continued)

tsu(SD_MR) Master receiver 6 -

Data input setup time
tsu(SD_SR) Slave receiver 2 -
(2)
th(SD_MR) Master receiver 4 -
Data input hold time
(2)
th(SD_SR) Slave receiver 0.5 -
ns
tv(SD_MT)(2) Master transmitter - 4
Data output valid time
tv(SD_ST)(2) Slave transmitter - 20
th(SD_MT) Master transmitter 0 -
Data output hold time
th(SD_ST) Slave transmitter 13 -
1. Data based on design simulation and/or characterization results, not tested in production.
2. Depends on fPCLK. For example, if fPCLK = 8 MHz, then TPCLK = 1/fPLCLK = 125 ns.
Figure 29. I2S slave timing diagram (Philips protocol)
WF&.
&32/
&.,QSXW
&32/
WZ&.+ WZ&./ WK:6
:6LQSXW
WVX:6 WY6'B67 WK6'B67
6'WUDQVPLW /6%WUDQVPLW 06%WUDQVPLW %LWQWUDQVPLW
WVX6'B65 WK6'B65
6'UHFHLYH /6%UHFHLYH 06%UHFHLYH %LWQUHFHLYH /6%UHFHLYH
06Y9
1. Measurement points are done at CMOS levels: 0.3 × VDDIOx and 0.7 × VDDIOx.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
DocID025743 Rev 6 79/106

80
Figure 30. I2S master timing diagram (Philips protocol)

WI&. WU&.
WF&.
&.RXWSXW
&32/
WZ&.+
&32/
WY:6 WZ&./ WK:6
:6RXWSXW
WY6'B07 WK6'B07
6'WUDQVPLW /6%WUDQVPLW 06%WUDQVPLW %LWQWUDQVPLW /6%WUDQVPLW
WVX6'B05 WK6'B05
6'UHFHLYH /6%UHFHLYH 06%UHFHLYH %LWQUHFHLYH /6%UHFHLYH
06Y9

2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
80/106 DocID025743 Rev 6

STM32F031x4 STM32F031x6 Package information
7 Package information
In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
7.1 LQFP48 package information

LQFP48 is a 48-pin, 7 x 7 mm low-profile quad flat package.
Figure 31. LQFP48 package outline
3%!4).'
0,!.%
#
!
!
!
C
MM
'!5'%0,!.%
CCC #
$ +
!
,
$ ,
$

B
%
%

0).
)$%.4)&)#!4)/.
E "?-%?6
1. Drawing is not to scale.
DocID025743 Rev 6 81/106

102
Package information STM32F031x4 STM32F031x6
Table 61. LQFP48 package mechanical data

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D 8.800 9.000 9.200 0.3465 0.3543 0.3622
D1 6.800 7.000 7.200 0.2677 0.2756 0.2835
D3 - 5.500 - - 0.2165 -
E 8.800 9.000 9.200 0.3465 0.3543 0.3622
E1 6.800 7.000 7.200 0.2677 0.2756 0.2835
E3 - 5.500 - - 0.2165 -
e - 0.500 - - 0.0197 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0° 3.5° 7° 0° 3.5° 7°
ccc - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 32. Recommended footprint for LQFP48 package

AID
1. Dimensions are expressed in millimeters.
82/106 DocID025743 Rev 6

Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 33. LQFP48 package marking example
WƌŽĚƵĐƚ ;ϭͿ
ŝĚĞŶƚŝĨŝĐĂƚŝŽŶ 670)
&7
ĂƚĞĐŽĚĞ
^ƚĂŶĚĂƌĚ^důŽŐŽ
< ::
ZĞǀŝƐŝŽŶĐŽĚĞ
WŝŶϭŝĚĞŶƚŝĨŝĞƌ
D^ϯϴϯϵϰsϭ
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST's Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
DocID025743 Rev 6 83/106

102
7.2 LQFP32 package information

LQFP32 is a 32-pin, 7 x 7 mm low-profile quad flat package.
Figure 34. LQFP32 package outline
3%!4).'
0,!.%
# !
!
C
!
MM
'!5'%0,!.%
CCC #
+
$
,
!
$
,
$

B
%
%

0).
)$%.4)&)#!4)/.
E 7@.&@7
84/106 DocID025743 Rev 6

Table 62. LQFP32 package mechanical data

Symbol
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.300 0.370 0.450 0.0118 0.0146 0.0177
c 0.090 - 0.200 0.0035 - 0.0079
D 8.800 9.000 9.200 0.3465 0.3543 0.3622
D1 6.800 7.000 7.200 0.2677 0.2756 0.2835
D3 - 5.600 - - 0.2205 -
E 8.800 9.000 9.200 0.3465 0.3543 0.3622
E1 6.800 7.000 7.200 0.2677 0.2756 0.2835
E3 - 5.600 - - 0.2205 -
e - 0.800 - - 0.0315 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0° 3.5° 7° 0° 3.5° 7°
ccc - - 0.100 - - 0.0039
Figure 35. Recommended footprint for LQFP32 package

6?&0?6
DocID025743 Rev 6 85/106

102
Device marking
location.
Figure 36. LQFP32 package marking example
ŝĚĞŶƚŝĨŝĐĂƚŝŽŶ 670)
.7
ĂƚĞĐŽĚĞ
< ::
D^ϯϰϵϱϯsϮ
7.3 UFQFPN32 package information

UFQFPN32 is a 32-pin, 5x5 mm, 0.5 mm pitch ultra-thin fine-pitch quad flat package.
86/106 DocID025743 Rev 6

Figure 37. UFQFPN32 package outline
'
GGG &
H $
&
$
6($7,1*
3/$1(
'
E
( E
( (

/

' /
3,1,GHQWLILHU
!"?-%?6

2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. This pad is used for the device
ground and must be connected. It is referred to as pin 0 in Table: Pin definitions.
DocID025743 Rev 6 87/106

102
Table 63. UFQFPN32 package mechanical data

Symbol
A 0.500 0.550 0.600 0.0197 0.0217 0.0236

A1 0.000 0.020 0.050 0.0000 0.0008 0.0020
A3 - 0.152 - - 0.0060 -
b 0.180 0.230 0.280 0.0071 0.0091 0.0110
D 4.900 5.000 5.100 0.1929 0.1969 0.2008
D1 3.400 3.500 3.600 0.1339 0.1378 0.1417
D2 3.400 3.500 3.600 0.1339 0.1378 0.1417
E 4.900 5.000 5.100 0.1929 0.1969 0.2008
E1 3.400 3.500 3.600 0.1339 0.1378 0.1417
E2 3.400 3.500 3.600 0.1339 0.1378 0.1417
e - 0.500 - - 0.0197 -
L 0.300 0.400 0.500 0.0118 0.0157 0.0197
ddd - - 0.080 - - 0.0031
Figure 38. Recommended footprint for UFQFPN32 package

$%B)3B9
88/106 DocID025743 Rev 6

Device marking
location.
Figure 39. UFQFPN32 package marking example
ŝĚĞŶƚŝĨŝĐĂƚŝŽŶ
).
ĂƚĞĐŽĚĞ
< ::
D^ϯϴϯϵϲsϭ
DocID025743 Rev 6 89/106

102
7.4 UFQFPN28 package information

UFQFPN28 is a 28-lead, 4x4 mm, 0.5 mm pitch, ultra-thin fine-pitch quad flat package.
Figure 40. UFQFPN28 package outline
' 'HWDLO<
'
'
(
'HWDLO=
!"?-%?6
Table 64. UFQFPN28 package mechanical data(1)

millimeters inches
Symbol
A 0.500 0.550 0.600 0.0197 0.0217 0.0236

A1 - 0.000 0.050 - 0.0000 0.0020
D 3.900 4.000 4.100 0.1535 0.1575 0.1614
D1 2.900 3.000 3.100 0.1142 0.1181 0.1220
E 3.900 4.000 4.100 0.1535 0.1575 0.1614
E1 2.900 3.000 3.100 0.1142 0.1181 0.1220
L 0.300 0.400 0.500 0.0118 0.0157 0.0197
L1 0.250 0.350 0.450 0.0098 0.0138 0.0177
T - 0.152 - - 0.0060 -
b 0.200 0.250 0.300 0.0079 0.0098 0.0118
e - 0.500 - - 0.0197 -
90/106 DocID025743 Rev 6

Figure 41. Recommended footprint for UFQFPN28 package

$%B)3B9
DocID025743 Rev 6 91/106

102
Device marking
location.
Figure 42. UFQFPN28 package marking example

*
ĂƚĞĐŽĚĞ ZĞǀŝƐŝŽŶĐŽĚĞ
< ::
Žƚ
;ƉŝŶϭŝĚĞŶƚŝĨŝĞƌͿ
D^ϯϴϯϵϳsϭ
92/106 DocID025743 Rev 6

7.5 WLCSP25 package information

WLCSP25 is a 25-ball, 2.423 x 2.325 mm, 0.4 mm pitch wafer level chip scale package.
Figure 43. WLCSP25 package outline
H $EDOOORFDWLRQ EEE =
H )
$ *
H 'HWDLO$
H
(
$
$
$
%XPSVLGH 6LGHYLHZ
%XPS
$
RULHQWDWLRQ HHH = $
UHIHUHQFH
DDD =
EEDOOV E
[ 6HDWLQJSODQH
FFF = ; <
GGG =
:DIHUEDFNVLGH 'HWDLO$
URWDWHG
:/&63B$1B0(B9
Table 65. WLCSP25 package mechanical data

Symbol
A 0.525 0.555 0.585 0.0207 0.0219 0.0230

A1 - 0.175 - - 0.0069 -
A2 - 0.380 - - 0.0150 -
A3(2) - 0.025 - - 0.0010 -
b(3) (4) 0.220 0.250 0.280 0.0087 0.0098 0.0110
D 2.388 2.423 2.458 0.0940 0.0954 0.0968
E 2.29 2.325 2.36 0.0902 0.0915 0.0929
e - 0.400 - - 0.0157 -
e1 - 1.600 - - 0.0630 -
e2 - 1.600 - - 0.0630 -
F - 0.4115 - - 0.0162 -
G - 0.3625 - - 0.0143 -
DocID025743 Rev 6 93/106

102
Table 65. WLCSP25 package mechanical data (continued)

Symbol
aaa - 0.100 - - 0.0039 -

bbb - 0.100 - - 0.0039 -
ccc - 0.100 - - 0.0039 -
ddd - 0.050 - - 0.0020 -
eee - 0.050 - - 0.0020 -
2. Back side coating.
3. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
4. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
Figure 44. Recommended footprint for WLCSP25 package
'SDG
'VP
:/&63B$1B)3B9
Table 66. WLCSP25 recommended PCB design rules

Dimension Recommended values
Pitch 0.4 mm
Dpad 0.225 mm
0.290 mm typ. (depends on the soldermask
Dsm
registration tolerance)
Stencil opening 0.250 mm
Stencil thickness 0.100 mm
94/106 DocID025743 Rev 6

Device marking
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
Figure 45. WLCSP25 package marking example
'RW
3URGXFW
LGHQWLILFDWLRQ
)
'DWHFRGH
5HYLVLRQFRGH
<:: 5
D^ϯϵϬϯϭsϮ
DocID025743 Rev 6 95/106

102
7.6 TSSOP20 package information

TSSOP20 is a 20-lead thin shrink small-outline, 6.5 x 4.4 mm, 0.65 mm pitch, package.
Figure 46.TSSOP20 package outline
ϮϬ ϭϭ
Đ
ϭ
^d/E' Ϭ͘Ϯϱŵŵ
W>E 'h'W>E

ϭ ϭϬ
W/Eϭ
/Ed/&/d/KE
Ŭ
ĂĂĂ
ϭ >
Ϯ
>ϭ
ď Ğ
zͺDͺsϯ
Table 67. TSSOP20 package mechanical data

Symbol
Min. Typ. Max. Min. Typ. Max.
A - - 1.200 - - 0.0472
A1 0.050 - 0.150 0.0020 - 0.0059
A2 0.800 1.000 1.050 0.0315 0.0394 0.0413
b 0.190 - 0.300 0.0075 - 0.0118
c 0.090 - 0.200 0.0035 - 0.0079
(2)
D 6.400 6.500 6.600 0.2520 0.2559 0.2598
E 6.200 6.400 6.600 0.2441 0.2520 0.2598
E1(3) 4.300 4.400 4.500 0.1693 0.1732 0.1772
e - 0.650 - - 0.0256 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
96/106 DocID025743 Rev 6

Table 67. TSSOP20 package mechanical data (continued)

Symbol
Min. Typ. Max. Min. Typ. Max.
k 0° - 8° 0° - 8°
aaa - - 0.100 - - 0.0039
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs
shall not exceed 0.15mm per side.
3. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not
exceed 0.25mm per side.
Figure 47. Recommended footprint for TSSOP20 package

9!?&0?6
DocID025743 Rev 6 97/106

102
Device marking
location.
Figure 48. TSSOP20 package marking example
))3
ĂƚĞĐŽĚĞ ZĞǀŝƐŝŽŶĐŽĚĞ
< ::
D^ϯϴϯϵϱsϭ
98/106 DocID025743 Rev 6

7.7 Thermal characteristics

The maximum chip junction temperature (TJmax) must never exceed the values given in
Table 18: General operating conditions.
The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max x ΘJA)
Where:
• TA max is the maximum ambient temperature in °C,
• ΘJA is the package junction-to-ambient thermal resistance, in °C/W,
• PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
• PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = Σ (VOL × IOL) + Σ ((VDDIOx – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
Table 68. Package thermal characteristics

Symbol Parameter Value Unit
Thermal resistance junction-ambient

55
LQFP48 - 7 × 7 mm
38
UFQFPN32 - 5 × 5 mm
56
LQFP32 - 7 × 7 mm
ΘJA °C/W
118
UFQFPN28 - 4 × 4 mm
74
WLCSP25 - 2.13 x 2.07 mm
110
TSSOP20 - 6.5 x 4.4 mm
7.7.1 Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org
DocID025743 Rev 6 99/106

102
7.7.2 Selecting the product temperature range

When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Section 8: Ordering information.
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and, to a specific maximum junction temperature.
As applications do not commonly use the STM32F031x4/x6 at maximum dissipation, it is
useful to calculate the exact power consumption and junction temperature to determine
which temperature range will be best suited to the application.
The following examples show how to calculate the temperature range needed for a given
application.
Example 1: High-performance application

Assuming the following application conditions:
Maximum ambient temperature TAmax = 80 °C (measured according to JESD51-2),
IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output
at low level with IOL = 20 mA, VOL= 1.3 V
PINTmax = 50 mA × 3.5 V= 175 mW
PIOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW
This gives: PINTmax = 175 mW and PIOmax = 272 mW:
PDmax = 175 + 272 = 447 mW
Using the values obtained in Table 68 TJmax is calculated as follows:
– For LQFP48, 55 °C/W
TJmax = 80 °C + (55°C/W × 447 mW) = 80 °C + 24.585 °C = 104.585 °C
This is within the range of the suffix 6 version parts (–40 < TJ < 105 °C) see Table 18:
General operating conditions.
In this case, parts must be ordered at least with the temperature range suffix 6 (see
Section 8: Ordering information).
Note: With this given PDmax we can find the TAmax allowed for a given device temperature range (order code suffix
6 or 7).
Suffix 6: TAmax = TJmax - (55°C/W × 447 mW) = 105-24.585 = 80.415 °C
Suffix 7: TAmax = TJmax - (55°C/W × 447 mW) = 125-24.585 = 100.415 °C
Example 2: High-temperature application

Using the same rules, it is possible to address applications that run at high ambient
temperatures with a low dissipation, as long as junction temperature TJ remains within the
specified range.
100/106 DocID025743 Rev 6

Assuming the following application conditions:

Maximum ambient temperature TAmax = 100 °C (measured according to JESD51-2),
IDDmax = 20 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V
PINTmax = 20 mA × 3.5 V= 70 mW
PIOmax = 20 × 8 mA × 0.4 V = 64 mW
This gives: PINTmax = 70 mW and PIOmax = 64 mW:
PDmax = 70 + 64 = 134 mW
Thus: PDmax = 134 mW
Using the values obtained in Table 68 TJmax is calculated as follows:
– For LQFP48, 55 °C/W
TJmax = 100 °C + (55 °C/W × 134 mW) = 100 °C + 7.37 °C = 107.37 °C
This is above the range of the suffix 6 version parts (–40 < TJ < 105 °C).
In this case, parts must be ordered at least with the temperature range suffix 7 (see
Section 8: Ordering information) unless we reduce the power dissipation in order to be able
to use suffix 6 parts.
DocID025743 Rev 6 101/106

102
Ordering information STM32F031x4 STM32F031x6
8 Ordering information
For a list of available options (memory, package, and so on) or for further information on any
aspect of this device, please contact your nearest ST sales office.
Table 69. Ordering information scheme

Example: STM32 F 031 G 6 T 6 x
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
F = General-purpose
Sub-family
031 = STM32F031xx
Pin count
F = 20 pins
E = 25 pins
G = 28 pins
K = 32 pins
C = 48 pins
User code memory size

4 = 16 Kbyte
6 = 32 Kbyte
Package
P = TSSOP
U = UFQFPN
T = LQFP
Y = WLCSP
Temperature range
6 = –40 °C to +85 °C
7 = –40 °C to +105 °C
Options
xxx = code ID of programmed parts (includes packing type)
TR = tape and reel packing
blank = tray packing
102/106 DocID025743 Rev 6

STM32F031x4 STM32F031x6 Revision history
9 Revision history
Table 70. Document revision history

Date Revision Changes
13-Jan-2014 1 Initial release.

Changed the document status to Datasheet - production
data.
Updated the following:
– Table: STM32F031x4/6 family device features and
peripheral counts,
– Figure: Clock tree,
– Figure: Power supply scheme,
– Table: Peripheral current consumption.
11-Jul-2014 2
Replaced Table Typical current consumption in Run
mode, code with data processing running from Flash
and Table Typical current consumption in Sleep mode,
code running from Flash or RAM with Table: Typical
current consumption, code executing from Flash,
running from HSE 8 MHz crystal.
Added the LQFP32 package: updates in Section:
Description, Section: Pinouts and pin description and
Section: Package information.
Updated:
– Figure 9: STM32F031x6 memory map
– AF1 alternate functions for PA0, PA1, PA2, PA3 and
PA4 in Table 12: Alternate functions selected through
GPIOA_AFR registers for port A
– the footnote for VIN max value in Table 15: Voltage
characteristics
– the footnote for max VIN in Table 18: General
operating conditions
– Table 22: Embedded internal reference voltage with
the addition of tSTART parameter
– Table 50: ADC characteristics
28-Aug-2015 3
– Table 53: TS characteristics: removed the min. value
for tSTART parameter
– the typical value for R parameter in Table 54: VBAT
monitoring characteristics
– the structure of Section 7: Package information.
Added:
– Figure 33: LQFP48 marking example (package top
view), Figure 36: LQFP32 marking example (package
top view), Figure 39: UFQFPN32 marking example
(package top view), Figure 42: UFQFPN28 marking
example (package top view), Figure 48: TSSOP20
marking example (package top view)
DocID025743 Rev 6 103/106

105
Revision history STM32F031x4 STM32F031x6
Table 70. Document revision history (continued)

Added WLCSP25 package, updates in the following:

– Table 1: Device summary,
– Section 2: Description,
– Table 2: STM32F031x4/x6 family device features and
peripheral counts,
3 – Section 4: Pinouts and pin description: addition of
28-Aug-2015
(continued) Figure 7: WLCSP25 25-ball package ballout (bump
side) and update of Table 11: Pin definitions,
– Table 18: General operating conditions,
– Section 7: Package information with the addition of
Section 7.5: WLCSP25 package information,
– Table 68: Package thermal characteristics.
Cover page:
– number of timers added in the title
– Table 1: Device summary - STM32F031x4 added
Section 2: Description:
– Figure 1: Block diagram updated
Section 3: Functional overview:
– Figure 2: Clock tree updated
– Section 3.5.4: Low-power modes - added explicit inf.
on peripherals configurable to operate with HSI
– Section 3.10.2: Internal voltage reference (VREFINT) -
removed information on comparators
– Section 3.11.2: General-purpose timers (TIM2, 3, 14,
16, 17) - number of gen-purpose timers corrected
– Table 7: STM32F031x4/x6 I2C implementation -
added 20mA output drive current
Section 4: Pinouts and pin description:
16-Dec-2015 4
– Package pinout figures updated (look and feel)
– Figure 7: WLCSP25 package pinout - now presented
in top view
– Table 11: Pin definitions - notes 3 and 6 added
Section 5: Memory mapping:
– added information on memory mapping difference of
STM32F031x4 from STM32F031x6
Section 6: Electrical characteristics:
– Table 22: Embedded internal reference voltage:
removed -40°-to-85° condition and associated note for
VREFINT
– Table 25 and Table 26 values rounded to 1 decimal
– Table 46: I/O static characteristics - removed note
– Table 50: ADC characteristics - updated some
parameter values, test conditions and added
footnotes (3) and (4)
104/106 DocID025743 Rev 6

STM32F031x4 STM32F031x6 Revision history
Table 70. Document revision history (continued)

– Section 6.3.16: 12-bit ADC characteristics - changed

introductory sentence
– Table 60: I2S characteristics: table reorganized,
tv(SD_ST) max value updated
4 Section 7: Package information:
16-Dec-2015
(continued)
– Figure 41: Recommended footprint for UFQFPN28
package updated
Section 8: Part numbering:
– added tray packing to options
Section 6: Electrical characteristics:
– Table 34: LSE oscillator characteristics (fLSE = 32.768
kHz) - information on configuring different drive
capabilities removed. See the corresponding
reference manual.
– Table 22: Embedded internal reference voltage -
06-Jan-2017 5 VREFINT values
– Figure 26: SPI timing diagram - slave mode and
CPHA = 0 and Figure 27: SPI timing diagram - slave
mode and CPHA = 1 enhanced and corrected
Section 8: Ordering information:
– The name of the section changed from the previous
“Part numbering”
Section 7: Package information:
– Figure 45: WLCSP25 package marking example - the
composition of the package marking fields and
15-May-2017 6
character sizes corrected. Check the product errata
sheet for additional information.
– Notes under package marking figures modified.
DocID025743 Rev 6 105/106

105
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2017 STMicroelectronics – All rights reserved
106/106 DocID025743 Rev 6

STM32F031x4 STM32F031x6

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

STM32F031x4 STM32F031x6

Uploaded by

Copyright:

Available Formats

STM32F031x4 STM32F031x6

ARM®-based 32-bit MCU with up to 32 Kbyte Flash, 9 timers,

• 5-channel DMA controller • Serial wire debug (SWD)

• 1 × 12-bit, 1.0 µs ADC (up to 10 channels) • 96-bit unique ID

May 2017 DocID025743 Rev 6 1/106

2/106 DocID025743 Rev 6

3.15 Serial peripheral interface (SPI) / Inter-integrated sound interface (I2S) . 21

4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

DocID025743 Rev 6 3/106

6.3.20 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

4/106 DocID025743 Rev 6

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

DocID025743 Rev 6 5/106

Table 48. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

6/106 DocID025743 Rev 6

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

DocID025743 Rev 6 7/106

8/106 DocID025743 Rev 6

The STM32F031x4/x6 microcontrollers incorporate the high-performance ARM® Cortex®-

Table 2. STM32F031x4/x6 family device features and peripheral counts

Flash memory (Kbyte) 16 32 32 16 32 16 32 16 32

DocID025743 Rev 6 9/106

Figure 1. Block diagram

3%>@ *3,2SRUW% ;7$/N+] 26&B,1

7HPS '%*0&8 ,5B287DV$)

3RZHUGRPDLQRIDQDORJEORFNV 9%$7 9'' 9''$

10/106 DocID025743 Rev 6

Figure 1 shows the general block diagram of the STM32F031x4/x6 devices.

3.1 ARM®-Cortex®-M0 core

3.3 Boot modes

DocID025743 Rev 6 11/106

3.4 Cyclic redundancy check calculation unit (CRC)

3.5 Power management

3.5.1 Power supply schemes

3.5.2 Power supply supervisors

3.5.3 Voltage regulator

12/106 DocID025743 Rev 6

3.5.4 Low-power modes

3.6 Clocks and startup

DocID025743 Rev 6 13/106

Figure 2. Clock tree

N+] /6, ,:'*

3.7 General-purpose inputs/outputs (GPIOs)

14/106 DocID025743 Rev 6

3.8 Direct memory access controller (DMA)

3.9 Interrupts and events

3.9.1 Nested vectored interrupt controller (NVIC)

3.9.2 Extended interrupt/event controller (EXTI)

3.10 Analog-to-digital converter (ADC)

DocID025743 Rev 6 15/106

3.10.1 Temperature sensor

Table 3. Temperature sensor calibration values

TS ADC raw data acquired at a

3.10.2 Internal voltage reference (VREFINT)

Table 4. Internal voltage reference calibration values

Raw data acquired at a

3.10.3 VBAT battery voltage monitoring

16/106 DocID025743 Rev 6

3.11 Timers and watchdogs

Table 5. Timer feature comparison

Advanced Up, down, integer from

3%>@ *3,2SRUW% ;7$/N+] 26&B,1

7HPS '%*0&8 ,5B287DV$)

3RZHUGRPDLQRIDQDORJEORFNV 9%$7 9'' 9''$

N+] /6, ,:'*

$ 3$ 3$ 3% %227 3)

% 3$ 3% 3$ 3$ 3)

& 3$ 3% 3$ 3$ 1567

' 9'' 3$ 3$ 3$ 9''$

( 966 3% 3% 3$ 3$

2ESERVED [))))))) !0"