Acer Aspire 4739 Quanta ZQH-P Acer Aspire 4739 (Quanta ZQH) .PDF (Diagramas - Com.br)

5 4 3 2 1
VER : 1A
BOM P/N Description =4+6<67(0%/2&.',$*5$0
D D
Channel B
64Mb * 16 *4 pc
P22
Arrandale ATI-Park
rPGA 989 VRAM DDRIII EXT_HDMI
Dual Channel DDR III P4, 5, 6, 7 PCI-E x16 512MB
DDRIII-SODIMM1
800/1066 MHZ IMC GFX
DDRIII-SODIMM2 EXT_CRT
P14,15
CRT Con.
EXT_LVDS P23
P16, 17, 18, 21, 22, 23
FDI DMI
X'TAL SLG8LV595 DMI(x4)

14.318MHz CLOCK USB-8
LVDS/CCD/MIC
INT_CRT
GENERATOR P3 FDI DMI Con.
INT_LVDS Int. MIC P23
CLK
Display
C C
SATA 0
SATA - HDD
P28 INT_HDMI PS8101
SATA
LS P24 HDMI Con.
SATA - ODD SATA 1
P28 EXT_HDMI P24
PCIE-6
PCI-E x1
USB Port USB-1 MINI CARD
USB Ibex Peak-M USB-13
P33 WLAN
P27
USB-3/9/11 PCH
USB/B Con. P33 P8, 9, 10, 11, 12, 13
(USB Port x2) PCIE-1 BRM 57780
RJ45
USB-4
GIGA LAN P26
Bluetooth Con. X'TAL P26
32.768KHz
P33
X'TAL
B 25MHz B
Cardreader AU6437-GBL USB-12 X'TAL 25MHz
P31
Cardreader control
P31
P9 BATTERY RTC
Azalia SPI SPI ROM

IHDA
P9
LPC
ISL88731A UP6111AQDD ISL62881HRZ-T
LPC Batery Charger P36 +1.05V P39 +VGFX_AXG P41
Int. MIC ALC272X NPCE781 X'TAL RT8206B RT8207A HPA00835RTER

AUDIO CODEC P30 EC P37 32.768KHz 3V/5V P37 +1.5V_SUS P40 +1.8V P43
ADP3212 MAX8792ETD+T Discharger

CPU core P38 +VGPU_CORE P42 P43
BOM Option Table

GMT 1453L amp Touch Pad
A MIC JACK P29 A
P30 Board Con. RT9018A Thermal Protection

Reference Description
P34 +1V P44 P44
IV@ for UMA only SKU
for Discrete Graphic only SKU Speaker W25X40BVSSIG
EV@
P30 SPI FLASH P35
for different VRAM parts K/B Con. Fan Driver Quanta Computer Inc.
VRAM@
HP P30 P34 (PWM Type) P34
* do not stuff PROJECT : ZQH
www.vinafix.vn http://hobi-elektronika.net
Size Document Number Rev
1A
Block Diagram
Date: Monday, March 14, 2011 Sheet 1 of 35
5 4 3 2 1
1 2 3 4 5 6 7 8
GPU PWR CTRL Option 1 (Default/ VDDR3 before VDDC)

+3.3V VIN VIN +1.5V +1.5V_SUS +1.8V +5V
VDDR3 +3V_D VDDC PG_GPUIO_EN VDDCI PG_1V_EN +1V (DP PLL PWR) PG_1.5V_EN VDDR1 PG_1.5V_EN VDDR4 PG_1.5V_EN BJT dGPU_PWROK MOS
dGPU_VRON dGPU_PWR_EN#
MOS (AO3413) ISL6264 ISL62872 G9334ADJ & MOS MOS (AO4710) MOS (AO6402) AO3413
P22 P44 P45 P47 P43 P43 P22 P22
A
+3_D (0.5A) +VGPU_CORE (20A) +VGPU_IO (4.5A) +1V (3A) +1.5V_GPU (10A) +1.8V_GPU (3A) +5_GPU A
GPU PWR CTRL Option 2 (VDDR3 after VDDR1)

VIN VIN +1.5V +1.5V_SUS +3.3V +1.8V +5V
VDDC PG_GPUIO_EN VDDCI PG_1V_EN +1V (DP PLL PWR) PG_1.5V_EN VDDR1 +1.5V_GPU VDDR3 +3V_D VDDR4 PG_1.5V_EN BJT dGPU_PWROK MOS
dGPU_VRON dGPU_PWR_EN#
ISL6264 ISL62872 G9334ADJ & MOS MOS (AO4710) MOS (AO3413) MOS (AO6402) AO3413
P44 P45 P47 P43 P22 P43 P22 P22
+VGPU_CORE (20A) +VGPU_IO (4.5A) +1V (3A) +1.5V_GPU (10A) +3_D (0.5A) +1.8V_GPU (3A) +5_GPU
Thermal Follow Chart

Power States
CONTROL
POWER PLANE VOLTAGE DESCRIPTION ACTIVE IN
SIGNAL
B VIN +10V~+19V MAIN POWER ALWAYS ALWAYS B
+VCCRTC +3V~+3.3V RTC POWER ALWAYS ALWAYS NTC

Thermal
+3VPCU +3.3V EC POWER ALWAYS ALWAYS
Protection
+5VPCU +5V CHARGE POWER ALWAYS ALWAYS
+15V +15V CHARGE PUMP POWER ALWAYS ALWAYS
+3V_S5 +3.3V LAN/BT/CIR POWER S5_ON S0-S5 CPU 3V/5 V

H_ORICHOT# PM_THRMTRIP# SYS_SHDN#
CORE PWR
CPU WIRE-AND SYS PWR
+5V_S5 +5V USB POWER S5_ON S0-S5 H/W Throttling
+5V +5V HDD/ODD/Codec/TP/CRT/HDMI POWER MAINON S0
+3V +3.3V PCH/GPU/Peripheral component POWER MAINON S0

SML1ALERT#
+1.5VSUS +1.5V CPU/SODIMM CORE POWER SUSON S0-S3
PCH FAN Driver FAN
+0.75V_DDR_VTT +0.75V SODIMM Termination POWER MAINON S0
+VGFX_AXG variation Internal GPU POWER GFX_ON S0

SM-Bus
+1.8V +1.8V CPU/PCH/Braidwood POWER MAINON S0
C C
+1.5V +1.5V MINI CARD/NEW CARD POWER MAINON S0

EC
+1.1V_VTT +1.05V or +1.1V CPU VTT POWER MAINON S0 CPUFAN#
+1.05V +1.05V PCH CORE POWER MAINON S0
+VCC_CORE variation CPU CORE POWER VRON S0
LCDVCC +3.3V LCD POWER LVDS_VDDEN S0
+5V_GPU +5V SWITCHABLE PWM IC POWER dGPU_PWR_EN# Discrete enable
+GPU_CORE +0.9V~+1.1V GPU CORE POWER +3V_D Discrete enable
+GPU_IO +0.9V~+1.1V GPU I/O POWER PG_GPUIO_EN Discrete enable
+1.5V_GPU +1.5V VRAM CORE POWER PG_1.5V_EN Discrete enable
+1.8V_GPU +1.8V GPU_CRE/LVDS/PLL POWER +1.5V_GPU Discrete enable
+1V +1V DP/PEG POWER PG_1V_EN Discrete enable
D D
Quanta Computer Inc.
www.vinafix.vn
PROJECT : ZQH
http://hobi-elektronika.net Size Document Number
PWR Status & GPU PWR CRL & THRM
Rev
1A

1 2 3 4 5 6 7 8
5 4 3 2 1
D D
150mA(30mil)
+1.5V L50 *PBY160808T-181Y-N/2A/180ohm_6 +1.5V_CLK 80mA(20mil)
+VDDIO_CLK L48 PBY160808T/2A/180ohm_6 +1.05V
C243 C627 C246
C613 C244 C607 C609
.1u/16V_4 .1u/16V_4 .1u/16V_4
R565 .1u/16V_4 .1u/16V_4 10u/Y5V_8 10u/Y5V_8
0_6 U20
Place each 0.1uF cap as close as
1 VDD_DOT possible to each VDD IO pin. Place
17 VDD_SRC VDD_SRC_I/O 15 the 10uF caps on the VDD_IO plane.
24 VDD_CPU VDD_CPU_I/O 18
20mil 5 VDD_27
+3V L23 BLM18AG601SN1D/200mA/600ohm_6 +3V_CLK 29 3
VDD_REF DOT_96 CLK_BUF_DREFCLK <10>
DOT_96# 4 CLK_BUF_DREFCLK# <10>
CLK_SDATA 31
C238 C267 C251 CLK_SCLK SDA
32 SCL 27M 6
27M_SS 7
4.7u/10V_8 .1u/16V_4 .1u/16V_4
R455 33_4 CPU_SEL 30 10
<10> CLK_ICH_14M REF_0/CPU_SEL SRC_1/SATA CLK_BUF_DREFSSCLK <10>
SRC_1#/SATA# 11 CLK_BUF_DREFSSCLK# <10>
C614 33p/50V_4 13
SRC_2 CLK_BUF_PCIE_3GPLL <10>
C SRC_2# 14 CLK_BUF_PCIE_3GPLL# <10> C
XTAL_IN 28
Y6 XTAL_IN +3V
14.318MHz XTAL_OUT 27 16 R130 10K_4
XTAL_OUT *CPU_STOP#
C612 33p/50V_4 2 20
VSS_DOT CPU_1 TP23
8 VSS_27 CPU_1# 19 TP24
9 VSS_SATA CPU_0 23 CLK_BUF_BCLK <10>
12 VSS_SRC CPU_0# 22 CLK_BUF_BCLK# <10>
21 VSS_CPU
IDT: AL003197001 (ICS9LVS3197AKLFT) 26 25 CK_PWRGD_R
VSS_REF CKPWRGD/PD#
33
Realtek: AL000890000 (RTM890N-632-GRT) GND
Silego: AL000595000 (SLG8LV595VTR)
ICS9LRS3197AKLFT
+3V
CPU_CLK select SMBus
B
+1.05V
CLK Enable +3V B
R543
R545
2
R451 2.2K_4 1K/F_4
*10K_4
3 1 CLK_SDATA CLK_SDATA <14,15,19>
<10> ICH_SMBDATA
CK_PWRGD_R
CPU_SEL Q18
3
2N7002K Q19
2N7002K
R446 C617
+3V <30> VR_PWRGD_CK505# 2 R544
10K_4 *10p/50V/COG_4 100K/F_4
1
R542
2
2.2K_4
0 1
3 1 CLK_SCLK CLK_SCLK <14,15,19>
<10> ICH_SMBCLK
A CPU_SEL CPU0/1=133MHz CPU0/1=100MHz Q17 A
2N7002K
(default)

PROJECT : ZQH
1A
Clock Generator
5 4 3 2 1
5 4 3 2 1
AUBURNDALE/CLARKSFIELD PROCESSOR (DMI,PEG,FDI) AUBURNDALE/CLARKSFIELD PROCESSOR (CLK,MISC,JTAG)

DPLL_REF_SSCLK and DPLL_REF_SSCLK# can be connected to GND on Arrandale
directly if motherboard only supports discrete graphics. If motherboard supports
integrated graphics but without eDP, these pins can also be connected to GND directly.
Processor Compensation Signals
U22A U22B T20
B26 R436 49.9/F_4 R444 20/F_4 H_COMP3 AT23
PEG_ICOMPI COMP3
A26 A16 CLK_CPU_BCLK <11>
PEG_ICOMPO BCLK
MISC
A24 B27 R442 20/F_4 H_COMP2 AT24 B16 CLK_CPU_BCLK# <11>
<8> DMI_TXN0 DMI_RX#[0] PEG_RCOMPO COMP2 BCLK#
C23 A25 R437 750/F_4
<8> DMI_TXN1 DMI_RX#[1] PEG_RBIAS R173 49.9/F_4 H_COMP1 T62 T21
CLOCKS
<8> DMI_TXN2 B22 G16 AR30
DMI_RX#[2] COMP1 BCLK_ITP T67
<8> DMI_TXN3 A21 K35 AT30
D DMI_RX#[3] PEG_RX#[0] R440 49.9/F_4 H_COMP0 BCLK_ITP# D
J34 AT26
PEG_RX#[1] COMP0
<8> DMI_TXP0 B24 J33 E16 CLK_PCIE_3GPLL <10>
DMI_RX[0] PEG_RX#[2] PEG_CLK
<8> DMI_TXP1 D23 G35 D16 CLK_PCIE_3GPLL# <10>
DMI_RX[1] PEG_RX#[3] PEG_CLK#
DMI
B23 G32 T10 AH24
<8> DMI_TXP2 DMI_RX[2] PEG_RX#[4] SKTOCC#
<8> DMI_TXP3 A22 F34 A18 DPLL_REF_SSCLK_R R465 *0_4 DPLL_REF_SSCLK <10>
DMI_RX[3] PEG_RX#[5] DPLL_REF_SSCLK
F31 A17 DPLL_REF_SSCLK#_R R471 *0_4 DPLL_REF_SSCLK# <10>
PEG_RX#[6] H_CATERR# DPLL_REF_SSCLK# R472 0_4
<8> DMI_RXN0 D24 D35 AK14
DMI_TX#[0] PEG_RX#[7] CATERR#
THERMAL
G24 E33 R463 0_4
<8> DMI_RXN1 DMI_TX#[1] PEG_RX#[8]
<8> DMI_RXN2 F23
DMI_TX#[2] PEG_RX#[9]
C33 Layout Note: Place
<8> DMI_RXN3 H23 D32 F6 DDR3_DRAMRST# <14,15> these resistors
DMI_TX#[3] PEG_RX#[10] SM_DRAMRST#
B32 <11> H_PECI AT15
PEG_RX#[11] PECI SM_RCOMP_0 R254 100/F_4 near Processor
<8> DMI_RXP0 D25 C31 AL1
DMI_TX[0] PEG_RX#[12] SM_RCOMP[0] SM_RCOMP_1 R253 24.9/F_4
<8> DMI_RXP1 F24 B28 AM1
DMI_TX[1] PEG_RX#[13] SM_RCOMP[1] SM_RCOMP_2 R252 130/F_4
<8> DMI_RXP2 E23 B30 AN1
DMI_TX[2] PEG_RX#[14] H_PROCHOT# SM_RCOMP[2]
<8> DMI_RXP3 G23 A31 <27,30> H_PROCHOT# AN26
DMI_TX[3] PEG_RX#[15] PROCHOT#
AN15 PM_EXTTS#0 <14>
PM_EXT_TS#[0]
DDR3
MISC
J35 AP15 R187 10K_4
PEG_RX[0] PM_EXT_TS#[1] R183 10K_4
H34 +1.05V
PEG_RX[1]
H33 <11> PM_THRMTRIP# AK15 PM_EXTTS#1 <15>
PEG_RX[2] THERMTRIP#
<8> FDI_TXN0 E22 F35
FDI_TX#[0] PEG_RX[3]
<8> FDI_TXN1 D21 G33
FDI_TX#[1] PEG_RX[4] T68
<8> FDI_TXN2 D19 E34 AT28
FDI_TX#[2] PEG_RX[5] PRDY# XDP_PREQ# T69
<8> FDI_TXN3 D18 F32 AP27
FDI_TX#[3] PEG_RX[6] PREQ#
<8> FDI_TXN4 G21 D34
FDI_TX#[4] PEG_RX[7] XDP_TCLK T8
<8> FDI_TXN5 E19 F33 AN28
FDI_TX#[5] PEG_RX[8] TCK
PCI EXPRESS -- GRAPHICS
F21 B33 H_CPURST# AP26 AP28 XDP_TMS T9
<8> FDI_TXN6 FDI_TX#[6] PEG_RX[9] RESET_OBS# TMS
PWR MANAGEMENT
Intel(R) FDI
G18 D31 AT27 XDP_TRST# T71

<8> FDI_TXN7 FDI_TX#[7] PEG_RX[10] TRST#
JTAG & BPM

A32
PEG_RX[11] XDP_TDI_R T70
C30 <8> PM_SYNC AL15 AT29
PEG_RX[12] PM_SYNC TDI XDP_TDO_R T66
<8> FDI_TXP0 D22 A28 AR27
FDI_TX[0] PEG_RX[13] TDO XDP_TDI_M T65
<8> FDI_TXP1 C21 B29 AR29
FDI_TX[1] PEG_RX[14] TDI_M XDP_TDO_M T64
<8> FDI_TXP2 D20 A30 AN14 AP29
FDI_TX[2] PEG_RX[15] VCCPWRGOOD_1 TDO_M
<8> FDI_TXP3 C18
FDI_TX[3] H_DBR#_R R149 *Short_4
<8> FDI_TXP4 G22 L33 AN25 XDP_DBRST# <8>
C FDI_TX[4] PEG_TX#[0] DBR# C
<8> FDI_TXP5 E20 M35 <11,27> H_PWRGOOD AN27
FDI_TX[5] PEG_TX#[1] VCCPWRGOOD_0
<8> FDI_TXP6 F20 M33
FDI_TX[6] PEG_TX#[2] XDP_OBS0 T19
<8> FDI_TXP7 G19 M30 AJ22
FDI_TX[7] PEG_TX#[3] BPM#[0] XDP_OBS1 T18
L31 <8> PM_DRAM_PWRGD AK13 AK22
PEG_TX#[4] SM_DRAMPWROK BPM#[1] XDP_OBS2 T17
<8> FDI_FSYNC0 F17 K32 AK24
FDI_FSYNC[0] PEG_TX#[5] BPM#[2] XDP_OBS3 T13
<8> FDI_FSYNC1 E17 M29 AJ24
FDI_FSYNC[1] PEG_TX#[6] H_VTTPWRGD BPM#[3] XDP_OBS4 T11
J31 AM15 AJ25
PEG_TX#[7] VTTPWRGOOD BPM#[4] XDP_OBS5 T15
<8> FDI_INT C17 K29 AH22
FDI_INT PEG_TX#[8] BPM#[5] XDP_OBS6 T16
H30 AK23
PEG_TX#[9] T14 BPM#[6] XDP_OBS7 T12
<8> FDI_LSYNC0 F18 H29 AM26 AH23
FDI_LSYNC[0] PEG_TX#[10] TAPPWRGOOD BPM#[7]
<8> FDI_LSYNC1 D17 F29
FDI_LSYNC[1] PEG_TX#[11]
E28
PEG_TX#[12] R193 1.5K/F_4 CPU_PLTRST# AL14
D29 <10,18,19,23,27> PLTRST#
PEG_TX#[13] RSTIN#
D27
PEG_TX#[14] R196
C26
PEG_TX#[15] 750/F_4
L34 Clarksfield/Auburndale
PEG_TX[0]
M34
PEG_TX[1]
M32
PEG_TX[2]
L30
PEG_TX[3]
M31
PEG_TX[4]
K31
PEG_TX[5]
M28
PEG_TX[6]
H31
PEG_TX[7]
K28
PEG_TX[8]
G30
PEG_TX[9]
G29
PEG_TX[10]
F28
PEG_TX[11]
E27
PEG_TX[12]
D28
PEG_TX[13]
C27
PEG_TX[14]
C25
PEG_TX[15]
B B
Clarksfield/Auburndale
Processor pull-up JTAG MAPPING

Thermaltrip protect VTT PWR_Good
XDP_TDI_R XDP_TDI
+1.05V R433 0_4
XDP_TDO_M XDP_TDO
XDP_TDO R420 51/F_4 R429 *0_4
+1.05V H_CATERR# R192 49.9/F_4
H_PROCHOT# R137 68_4 R431
H_CPURST# R438 *68_4
3
XDP_TMS R135 *51_4 0_4

+3V XDP_TDI_R R435 *51_4
XDP_PREQ# R434 *51_4 XDP_TDI_M
2 Q16 XDP_TCLK R133 *51_4 R432 *0_4
<8,30> DELAY_VR_PWRGOOD
XDP_TRST# R439 51/F_4 XDP_TDO_R
FDV301N C309 R430 0_4
0.1u/10V_4
1
Scan Chain STUFF -> R469, R491, R507

5
R209 (Default) NO STUFF -> R489, R490

1K_4 <27> MPWROK 2 R176 +1.5VSUS
4 H_VTTPWRGD
1 CPU Only STUFF -> R490, R491
2K/F_4 Use a voltage divider with VDDQ NO STUFF -> R469, R489, R507
U5 R205 (1.5V) rail (ON in S3) and
3
2
A R179 1.1K/F_4 A
resistor combination of 4.75K (to
Q15 TC7SH08FU 1K_4 GMCH Only STUFF -> R489, R507
VDDQ)/12K(to GND) to generate the
<11> PM_THRMTRIP#
PM_THRMTRIP# 1 3 MMBT3904 SYS_SHDN# <29,34>
PM_DRAM_PWRGD NO STUFF -> R491, R490, R469
required voltage.
R199 Note: CRB uses a 3.3V (always ON)
3K/F_4 rail with 2K and 1K combination.

PROJECT : ZQH
1A
AUBURNDA 1/4
5 4 3 2 1
5 4 3 2 1
AUBURNDALE/CLARKSFIELD PROCESSOR (DDR3) U22D
U22C
<15> M_B_DQ[63:0] SB_CK[0] W8 M_B_CLK0 <15>

SB_CK#[0] W9 M_B_CLK0# <15>
M_B_DQ0 B5 M3 M_B_CKE0 <15>
M_B_DQ1 SB_DQ[0] SB_CKE[0]
A5 SB_DQ[1]
AA6 M_B_DQ2 C3
SA_CK[0] M_A_CLK0 <14> SB_DQ[2]
AA7 M_B_DQ3 B3 V7
SA_CK#[0] M_A_CLK0# <14> SB_DQ[3] SB_CK[1] M_B_CLK1 <15>
P7 M_A_CKE0 <14> M_B_DQ4 E4 V6 M_B_CLK1# <15>
D <14> M_A_DQ[63:0] M_A_DQ0 SA_CKE[0] M_B_DQ5 SB_DQ[4] SB_CK#[1] D
A10 A6 M2 M_B_CKE1 <15>
M_A_DQ1 SA_DQ[0] M_B_DQ6 SB_DQ[5] SB_CKE[1]
C10 A4
M_A_DQ2 SA_DQ[1] M_B_DQ7 SB_DQ[6]
C7 C4
A7 Y6 M_A_CLK1 <14> D1
M_A_DQ4 SA_DQ[3] SA_CK[1] M_B_DQ9 SB_DQ[8]
B10 Y5 M_A_CLK1# <14> D2
M_A_DQ5 SA_DQ[4] SA_CK#[1] M_B_DQ10 SB_DQ[9]
D10 P6 M_A_CKE1 <14> F2 AB8 M_B_CS#0 <15>
M_A_DQ6 SA_DQ[5] SA_CKE[1] M_B_DQ11 SB_DQ[10] SB_CS#[0]
E10 F1 AD6 M_B_CS#1 <15>
M_A_DQ7 SA_DQ[6] M_B_DQ12 SB_DQ[11] SB_CS#[1]
A8 C2
D8 F5
F10 AE2 M_A_CS#0 <14> F3
M_A_DQ10 SA_DQ[9] SA_CS#[0] M_B_DQ15 SB_DQ[14]
E6 AE8 M_A_CS#1 <14> G4 AC7 M_B_ODT0 <15>
M_A_DQ11 SA_DQ[10] SA_CS#[1] M_B_DQ16 SB_DQ[15] SB_ODT[0]
F7 SA_DQ[11] H6 SB_DQ[16] SB_ODT[1] AD1 M_B_ODT1 <15>
M_A_DQ12 E9 M_B_DQ17 G2
B7 SA_DQ[13] J6 SB_DQ[18]
M_A_DQ14 E7 AD8 M_A_ODT0 <14> M_B_DQ19 J3
M_A_DQ15 SA_DQ[14] SA_ODT[0] M_B_DQ20 SB_DQ[19]
C6 SA_DQ[15] SA_ODT[1] AF9 M_A_ODT1 <14> G1 SB_DQ[20] M_B_DM[7:0] <15>
M_A_DQ16 H10 M_B_DQ21 G5 D4 M_B_DM0
M_A_DQ17 SA_DQ[16] M_B_DQ22 SB_DQ[21] SB_DM[0] M_B_DM1
G8 SA_DQ[17] J2 SB_DQ[22] SB_DM[1] E1
M_A_DQ18 K7 M_B_DQ23 J1 H3 M_B_DM2
J8 SA_DQ[19] J5 SB_DQ[24] SB_DM[3] K1
M_A_DQ20 G7 M_B_DQ25 K2 AH1 M_B_DM4
G10 SA_DQ[21] M_A_DM[7:0] <14> L3 SB_DQ[26] SB_DM[5] AL2
M_A_DQ22 J7 B9 M_A_DM0 M_B_DQ27 M1 AR4 M_B_DM6
M_A_DQ23 SA_DQ[22] SA_DM[0] M_A_DM1 M_B_DQ28 SB_DQ[27] SB_DM[6] M_B_DM7
J10 SA_DQ[23] SA_DM[1] D7 K5 SB_DQ[28] SB_DM[7] AT8
M_A_DQ24 L7 H7 M_A_DM2 M_B_DQ29 K4
M_A_DQ25 SA_DQ[24] SA_DM[2] M_A_DM3 M_B_DQ30 SB_DQ[29]
M6 SA_DQ[25] SA_DM[3] M7 M4 SB_DQ[30]
M_A_DQ26 M8 AG6 M_A_DM4 M_B_DQ31 N5
M_A_DQ27 SA_DQ[26] SA_DM[4] M_A_DM5 M_B_DQ32 SB_DQ[31]
L9 SA_DQ[27] SA_DM[5] AM7 AF3 SB_DQ[32]
M_A_DQ28 L6 AN10 M_A_DM6 M_B_DQ33 AG1
M_A_DQ29 SA_DQ[28] SA_DM[6] M_A_DM7 M_B_DQ34 SB_DQ[33] M_B_DQS#0 M_B_DQS#[7:0] <15>
K8 SA_DQ[29] SA_DM[7] AN13 AJ3 SB_DQ[34] SB_DQS#[0] D5
M_A_DQ30 N8 M_B_DQ35 AK1 F4 M_B_DQS#1
M_A_DQ31 SA_DQ[30] M_B_DQ36 SB_DQ[35] SB_DQS#[1] M_B_DQS#2
P9 SA_DQ[31] AG4 SB_DQ[36] SB_DQS#[2] J4
C M_A_DQ32 M_B_DQ37 M_B_DQS#3 C
AH5 SA_DQ[32] AG3 SB_DQ[37] SB_DQS#[3] L4
M_A_DQ33 AF5 M_B_DQ38 AJ4 AH2 M_B_DQS#4
SA_DQ[33] M_A_DQS#[7:0] <14> SB_DQ[38] SB_DQS#[4]
DDR SYSTEM MEMORY - B

M_A_DQ34 AK6 C9 M_A_DQS#0 M_B_DQ39 AH4 AL4 M_B_DQS#5
SA_DQ[34] SA_DQS#[0] SB_DQ[39] SB_DQS#[5]
DDR SYSTEM MEMORY A
M_A_DQ35 AK7 F8 M_A_DQS#1 M_B_DQ40 AK3 AR5 M_B_DQS#6

M_A_DQ36 SA_DQ[35] SA_DQS#[1] M_A_DQS#2 M_B_DQ41 SB_DQ[40] SB_DQS#[6] M_B_DQS#7
AF6 SA_DQ[36] SA_DQS#[2] J9 AK4 SB_DQ[41] SB_DQS#[7] AR8
M_A_DQ37 AG5 N9 M_A_DQS#3 M_B_DQ42 AM6
M_A_DQ38 SA_DQ[37] SA_DQS#[3] M_A_DQS#4 M_B_DQ43 SB_DQ[42]
AJ7 SA_DQ[38] SA_DQS#[4] AH7 AN2 SB_DQ[43]
M_A_DQ39 AJ6 AK9 M_A_DQS#5 M_B_DQ44 AK5
AJ10 AP11 AK2
AJ9 AT13 AM4
M_A_DQ42 SA_DQ[41] SA_DQS#[7] M_B_DQ47 SB_DQ[46]
AL10 AM3 M_B_DQS[7:0] <15>
M_A_DQ43 SA_DQ[42] M_B_DQ48 SB_DQ[47] M_B_DQS0
AK12 AP3 C5
M_A_DQ44 SA_DQ[43] M_B_DQ49 SB_DQ[48] SB_DQS[0] M_B_DQS1
AK8 AN5 E3
M_A_DQ45 SA_DQ[44] M_B_DQ50 SB_DQ[49] SB_DQS[1] M_B_DQS2
AL7 M_A_DQS[7:0] <14> AT4 H4
M_A_DQ46 SA_DQ[45] M_A_DQS0 M_B_DQ51 SB_DQ[50] SB_DQS[2] M_B_DQS3
AK11 C8 AN6 M5
M_A_DQ47 SA_DQ[46] SA_DQS[0] M_A_DQS1 M_B_DQ52 SB_DQ[51] SB_DQS[3] M_B_DQS4
AL8 F9 AN4 AG2
AN8 H9 AN3 AL5
AM10 M9 AT5 AP5
AR11 AH8 AT6 AR7
M_A_DQ51 SA_DQ[50] SA_DQS[4] M_A_DQS5 M_B_DQ56 SB_DQ[55] SB_DQS[7]
AL11 AK10 AN7
M_A_DQ52 SA_DQ[51] SA_DQS[5] M_A_DQS6 M_B_DQ57 SB_DQ[56]
AM9 AN11 AP6
M_A_DQ53 SA_DQ[52] SA_DQS[6] M_A_DQS7 M_B_DQ58 SB_DQ[57]
AN9 AR13 AP8
M_A_DQ54 SA_DQ[53] SA_DQS[7] M_B_DQ59 SB_DQ[58]
AT11 AT9
AP12 AT7
AM12 AP9
AN12 M_A_A[15:0] <14> AR10 M_B_A[15:0] <15>
M_A_DQ58 SA_DQ[57] M_A_A0 M_B_DQ63 SB_DQ[62] M_B_A0
AM13 Y3 AT10 U5
M_A_DQ59 SA_DQ[58] SA_MA[0] M_A_A1 SB_DQ[63] SB_MA[0] M_B_A1
AT14 W1 V2
M_A_DQ60 SA_DQ[59] SA_MA[1] M_A_A2 SB_MA[1] M_B_A2
AT12 AA8 T5
AL13 AA3 V3
AR14 V1 R1
AP14 AA9 <15> M_B_BS#0 AB1 T8
B SA_DQ[63] SA_MA[5] M_A_A6 SB_BS[0] SB_MA[5] M_B_A6 B
V8 <15> M_B_BS#1 W5 R2
SA_MA[6] M_A_A7 SB_BS[1] SB_MA[6] M_B_A7
T1 <15> M_B_BS#2 R7 R6
SA_MA[7] M_A_A8 SB_BS[2] SB_MA[7] M_B_A8
Y9 R4
SA_MA[8] M_A_A9 SB_MA[8] M_B_A9
<14> M_A_BS#0 AC3 U6 R5
SA_BS[0] SA_MA[9] M_A_A10 SB_MA[9] M_B_A10
<14> M_A_BS#1 AB2 AD4 <15> M_B_CAS# AC5 AB5
SA_BS[1] SA_MA[10] M_A_A11 SB_CAS# SB_MA[10] M_B_A11
<14> M_A_BS#2 U7 T2 <15> M_B_RAS# Y7 P3
SA_BS[2] SA_MA[11] M_A_A12 SB_RAS# SB_MA[11] M_B_A12
U3 <15> M_B_WE# AC6 R3
SA_MA[12] M_A_A13 SB_WE# SB_MA[12] M_B_A13
AG8 AF7
T3 P5
<14> M_A_CAS# AE1 V9 N1
SA_CAS# SA_MA[15] SB_MA[15]
<14> M_A_RAS# AB3
SA_RAS#
<14> M_A_WE# AE9
SA_WE#
Clarksfield/Auburndale Clarksfield/Auburndale
Channel A DQ[15,32,48,54], DM[5] Channel B DQ[16,18,36,42,56,57,60,61,62]

Requires minimum 12mils spacing Requires minimum 12mils spacing
with all other signals, including data signals. with all other signals, including data signals.
A A

PROJECT : ZQH
www.vinafix.vn
http://hobi-elektronika.net
1A
AUBURNDA 2/4
5 4 3 2 1
5 4 3 2 1
CPU Core Power U22F
VTT Rail Values are AUBURNDALE/CLARKSFIELD PROCESSOR (GRAPHICS POWER)

ARD:48A Auburndal VTT=1.05V
+VCC_CORE Clarksfield VTT=1.1V
CFD:52A
18A
C568 10U/6.3V_8 AG35 AH14 +1.05V U22G
C626 22U/6.3V_8 VCC1 VTT0_1 T72
AG34 AH12
C234 10U/6.3V_8 AG33
VCC2 VTT0_2
AH11 +VGFX_AXG
22A AT21
C589 22U/6.3V_8 VCC3 VTT0_3 C658 10U/6.3V_8 VAXG1
AG32 AH10 AT19 AR22 VCC_AXG_SENSE <33>
D C623 22U/6.3V_8 VCC4 VTT0_4 C657 10U/6.3V_8 VAXG2 VAXG_SENSE D
SENSE
LINES
AG31 J14 AT18 AT22 VSS_AXG_SENSE <33>
C643 10U/6.3V_8 VCC5 VTT0_5 C634 10U/6.3V_8 VAXG3 VSSAXG_SENSE
AG30 J13 AT16
C642 10U/6.3V_8 VCC6 VTT0_6 C327 10U/6.3V_8 VAXG4 T73
AG29 H14 AR21
C590 22U/6.3V_8 VCC7 VTT0_7 C648 10U/6.3V_8 VAXG5
AG28 H12 AR19
C567 22U/6.3V_8 VCC8 VTT0_8 C649 10U/6.3V_8 + VAXG6
AG27 G14 AR18
C640 10U/6.3V_8 VCC9 VTT0_9 C644 10U/6.3V_8 C635 C281 C280 VAXG7
AG26 G13 AR16 AM22 GFX_VID0 <33>
C230 10U/6.3V_8 VCC10 VTT0_10 C659 10U/6.3V_8 *330U/2V_7343 22u/6.3V_8 22u/6.3V_8 VAXG8 GFX_VID[0]
AF35 G12 AP21 AP22 GFX_VID1 <33>
VCC11 VTT0_11 VAXG9 GFX_VID[1]
GRAPHICS VIDs
C588 22U/6.3V_8 AF34 G11 C652 10U/6.3V_8 AP19 AN22 GFX_VID2 <33>
C235 10U/6.3V_8 VCC12 VTT0_12 C331 10U/6.3V_8 VAXG10 GFX_VID[2]
AF33 F14 AP18 AP23 GFX_VID3 <33>
C569 10U/6.3V_8 VCC13 VTT0_13 VAXG11 GFX_VID[3]
AF32 F13 AP16 AM23 GFX_VID4 <33>
AF31 F12 C316 AN21 AP24 GFX_VID5 <33>
VCC15 VTT0_15 VAXG13 GFX_VID[5]
GRAPHICS
C624 10U/6.3V_8 AF30 F11 AN19 AN24 GFX_VID6 <33>
+
AF29 E14 AN18
C638 10U/6.3V_8 VCC17 VTT0_17 VAXG15
AF28 E12 AN16
C625 10U/6.3V_8 VCC18 VTT0_18 VAXG16
AF27 D14 AM21 AR25 GFX_ON <33>
C566 10U/6.3V_8 VCC19 VTT0_19 330u/2V_7343 VAXG17 GFX_VR_EN
AF26 D13 AM19 AT25 GFX_DPRSLPVR <33>
C622 10U/6.3V_8 VCC20 VTT0_20 VAXG18 GFX_DPRSLPVR
AD35 D12 AM18 AM24
1.1V RAIL POWER

VCC21 VTT0_21 + VAXG19 GFX_IMON GFX_IMON <33>
C266 10U/6.3V_8 AD34 D11 AM16
C265 10U/6.3V_8 VCC22 VTT0_22 C651 C298 C299 VAXG20
AD33 C14 AL21
C236 10U/6.3V_8 VCC23 VTT0_23 *330U/2V_7343 10u/6.3V_8 10u/6.3V_8 VAXG21
C641 10U/6.3V_8
AD32
VCC24 VTT0_24
C13 AL19
VAXG22 ARD:3A
AD31 C12 AL18
C287 10U/6.3V_8 VCC25 VTT0_25 VAXG23 CFD:6A
AD30 C11 AL16
C232 10U/6.3V_8 VCC26 VTT0_26 VAXG24
AD29 B14 AK21 AJ1 +1.5VSUS
C633 10U/6.3V_8 VCC27 VTT0_27 VAXG25 VDDQ1
AD28 B12 AK19 AF1
C275 0.1u/10V_4_X7R VCC28 VTT0_28 VAXG26 VDDQ2
- 1.5V RAILS
AD27 A14 AK18 AE7
C271 0.1u/10V_4_X7R VCC29 VTT0_29 VAXG27 VDDQ3 C358 C356 C355 C352
AD26 A13 AK16 AE4
VCC30 VTT0_30 VAXG28 VDDQ4
AC35 A12 AJ21 AC1
+
C284 330u/2V_7343 AC34 A11 AJ19 AB7 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4
AC33 AJ18 AB4
VCC33 VAXG31 VDDQ7
+
C285 330u/2V_7343 AC32 +1.05V AJ16 Y1

VCC34 VAXG32 VDDQ8
AC31 AH21 W7
VCC35 VAXG33 VDDQ9
POWER
AC30 AF10 AH19 W4
C VCC36 VTT0_33 VAXG34 VDDQ10 C417 C360 C357 + C363 C
AC29 AE10 AH18 U1
AC28 AC10 AH16 T7
CPU CORE SUPPLY

AC27 AB10 C313 22U/6.3V_8 T4 1U/6.3V_4 22U/6.3V_8 22U/6.3V_8 330U/2V_7343
VCC39 VTT0_36 VDDQ13
AC26 Y10 P1
VCC40 VTT0_37 C326 22U/6.3V_8 VDDQ14
AA35 W10 N7
AA34 U10 N4
VCC42 VTT0_39 +1.05V VDDQ16
DDR3
AA33 T10 L1
AA32 J12 J24 H1
VCC44 VTT0_41 VTT1_45 VDDQ18
FDI
AA31 J11 J23
VCC45 VTT0_42 VTT1_46
AA30 J16 H25
AA29 J15
VCC47 VTT0_44
AA28
VCC48 C311 C655
AA27 P10 +1.05V
VCC49 10U/6.3V_8 22u/6.3V_8 VTT0_59
AA26 N10
VCC50 VTT0_60 C660 10U/6.3V_8
Y35 L10
VCC51 VTT0_61 C654 10U/6.3V_8
Y34 K10
VCC52 VTT0_62
Y33
VCC53
Y32
VCC54
Y31
VCC55
Y30
VCC56
1.1V
Y29 J22
VCC57 VTT1_63 10U/6.3V_8 C618
Y28 K26 J20
VCC58 VTT1_48 VTT1_64 10U/6.3V_8 C630
Y27 J27 J18
PEG & DMI

Y26 J26 H21
VCC60 H_PSI# C332 C656 C312 C330 VTT1_50 VTT1_66
V35 AN33 H_PSI# <30> J25 H20
VCC61 PSI# 10U/6.3V_8 10U/6.3V_8 22u/6.3V_8 22u/6.3V_8 VTT1_51 VTT1_67
V34 H27 H19
POWER

V33 G28
VCC63 H_VID0 VTT1_53
V32 AK35 H_VID0 <30> G27
VCC64 VID[0] H_VID1 VTT1_54
V31
VCC65 VID[1]
AK33
H_VID2
H_VID1 <30> G26
VTT1_55 0.6A
V30 AK34 H_VID2 <30> F26
VCC66 VID[2] H_VID3 VTT1_56
V29 AL35 H_VID3 <30> E26 L26 +1.8V
VCC67 VID[3] VTT1_57 VCCPLL1
CPU VIDS
1.8V
V28 AL33 H_VID4 H_VID4 <30> E25 L27
B VCC68 VID[4] H_VID5 VTT1_58 VCCPLL2 22U/6.3V_8 C258 B
V27 AM33 H_VID5 <30> M26
VCC69 VID[5] H_VID6 VCCPLL3 4.7U/6.3V_6 C274
V26 AM35 H_VID6 <30>
VCC70 VID[6] H_DPRSLPVR 2.2U/6.3V_6 C231
U35 AM34 H_DPRSLPVR <30>
VCC71 PROC_DPRSLPVR 1U/6.3V_4 C233
U34
VCC72 1U/6.3V_4 C239
U33
VCC73
U32
VCC74
U31 G15
VCC75 VTT_SELECT
U30
VCC76 Clarksfield/Auburndale
U29
VCC77 H_VTTVID1=Low, 1.1V
U28
VCC78 H_VTTVID1=High, 1.05V
U27
VCC79
U26
VCC80
R35
VCC81
R34
VCC82
R33
VCC83
R32 AN35 I_MON <30>
VCC84 ISENSE
R31
VCC85
R30
VCC86 R104 100/F_4
R29 +VCC_CORE
VCC87
R28 AJ34
SENSE LINES
VCC88 VCC_SENSE VCCSENSE <30>

R27 AJ35 VSSSENSE <30>
1 H_VID0 R388 1K_4 +1.05V
VCC89 VSS_SENSE R395 *1K/F_4
R26
VCC90 R103 100/F_4 1 H_VID1 R387 1K_4
P35
VCC91 VTT_SENSE R394 *1K/F_4
P34 B15 T75
VCC92 VTT_SENSE VSS_SENSE_VTT 1 H_VID2 R389 1K_4
P33 A15 T74
VCC93 VSS_SENSE_VTT R396 *1K/F_4
P32
VCC94 0 H_VID3 R400 *1K/F_4
P31
VCC95 R409 1K_4
P30
VCC96 0 H_VID4 R401 *1K/F_4
P29
VCC97 R410 1K_4
P28
VCC98 1 H_VID5 R404 1K_4
P27
VCC99 R413 *1K/F_4
P26
A VCC100 0 H_VID6 R402 *1K/F_4 A
R411 1K_4
1 H_DPRSLPVR R403 1K_4
R412 *1K/F_4
0 H_PSI# R419 *1K/F_4
R418 1K_4
Note:
For Validating IMVP VR R6451 should be STUFF
HFM_VID : Max 1.4V
and R2N1 NO_STUFF LFM_VID : Min 0.65V PROJECT : ZQH
AUBURNDALE/CLARKSFIELD PROCESSOR (POWER) Size Document Number Rev
1A
AUBURNDA 3/4 (PWR)
5 4 3 2 1
5 4 3 2 1
AUBURNDALE/CLARKSFIELD PROCESSOR (GND) AUBURNDALE/CLARKSFIELD PROCESSOR( RESERVED, CFG)

U22H U22I U22E
AT20 VSS1 VSS81 AE34 RSVD32 AJ13

AT17 VSS2 VSS82 AE33 RSVD33 AJ12
AR31 VSS3 VSS83 AE32 K27 VSS161
AR28 VSS4 VSS84 AE31 K9 VSS162 AP25 RSVD1
AR26 VSS5 VSS85 AE30 K6 VSS163 AL25 RSVD2 RSVD34 AH25
AR24 VSS6 VSS86 AE29 K3 VSS164 AL24 RSVD3 RSVD35 AK26
AR23 VSS7 VSS87 AE28 J32 VSS165 AL22 RSVD4
AR20 VSS8 VSS88 AE27 J30 VSS166 AJ33 RSVD5 RSVD36 AL26
AR17 VSS9 VSS89 AE26 J21 VSS167 AG9 RSVD6 RSVD_NCTF_37 AR2
AR15 VSS10 VSS90 AE6 J19 VSS168 M27 RSVD7
D AR12 VSS11 VSS91 AD10 H35 VSS169 L28 RSVD8 RSVD38 AJ26 D
AR9 VSS12 VSS92 AC8 H32 VSS170 <14> VREF_DQ_DIMM0 J17 SA_DIMM_VREF RSVD39 AJ27
AR6 VSS13 VSS93 AC4 H28 VSS171 <15> VREF_DQ_DIMM1 H17 SB_DIMM_VREF
AR3 VSS14 VSS94 AC2 H26 VSS172 G25 RSVD11
AP20 VSS15 VSS95 AB35 H24 VSS173 G17 RSVD12
AP17 VSS16 VSS96 AB34 H22 VSS174 E31 RSVD13 RSVD_NCTF_40 AP1
AP13 VSS17 VSS97 AB33 H18 VSS175 E30 RSVD14 RSVD_NCTF_41 AT2
AP10 VSS18 VSS98 AB32 H15 VSS176
AP7 VSS19 VSS99 AB31 H13 VSS177 RSVD_NCTF_42 AT3
AP4 VSS20 VSS100 AB30 H11 VSS178 RSVD_NCTF_43 AR1
AP2 VSS21 VSS101 AB29 H8 VSS179
AN34 VSS22 VSS102 AB28 H5 VSS180
AN31 VSS23 VSS103 AB27 H2 VSS181
AN23 VSS24 VSS104 AB26 G34 VSS182 RSVD45 AL28
AN20 AB6 G31 CFG0 AM30 AL29
VSS25 VSS105 VSS183 CFG[0] RSVD46
AN17 VSS26 VSS106 AA10 G20 VSS184 AM28 CFG[1] RSVD47 AP30
AM29 VSS27 VSS107 Y8 G9 VSS185 AP31 CFG[2] RSVD48 AP32
AM27 Y4 G6 CFG3 AL32 AL27
VSS28 VSS108 VSS186 CFG4 CFG[3] RSVD49
AM25 VSS29 VSS109 Y2 G3 VSS187 AL30 CFG[4] RSVD50 AT31
AM20 VSS30 VSS110 W 35 F30 VSS188 AM31 CFG[5] RSVD51 AT32
AM17 VSS31 VSS111 W 34 F27 VSS189 AN29 CFG[6] RSVD52 AP33
AM14 W 33 F25 CFG7 AM32 AR33
VSS32 VSS112 VSS190 CFG[7] RSVD53
AM11 VSS33 VSS113 W 32 F22 VSS191 AK32 CFG[8] RSVD_NCTF_54 AT33
AM8 W 31 F19 AK31 AT34
RESERVED
VSS34 VSS114 VSS192 CFG[9] RSVD_NCTF_55
AM5 VSS35 VSS115 W 30 F16 VSS193 AK28 CFG[10] RSVD_NCTF_56 AP35
AM2 VSS36 VSS116 W 29 E35 VSS194 AJ28 CFG[11] RSVD_NCTF_57 AR35
AL34 W 28 E32 AN30 AR32
AL31
AL23
VSS37
VSS38
VSS39
VSS VSS117
VSS118
VSS119
W 27
W 26
E29
E24
VSS195
VSS196
VSS197
VSS AN32
AJ32
CFG[12]
CFG[13]
CFG[14]
RSVD58
AL20 VSS40 VSS120 W6 E21 VSS198 AJ29 CFG[15] RSVD_TP_59 E15

AL17 VSS41 VSS121 V10 E18 VSS199 AJ30 CFG[16] RSVD_TP_60 F15
C AL12 U8 E13 AK30 A2 C
VSS42 VSS122 VSS200 CFG[17] KEY
AL9 VSS43 VSS123 U4 E11 VSS201 H16 RSVD_TP_86 RSVD62 D15
AL6 VSS44 VSS124 U2 E8 VSS202 RSVD63 C15
AL3 VSS45 VSS125 T35 E5 VSS203 RSVD64 AJ15 TP8
AK29 VSS46 VSS126 T34 E2 VSS204 VSS_NCTF1 AT35 RSVD65 AH15 TP9
AK27 VSS47 VSS127 T33 D33 VSS205 VSS_NCTF2 AT1
AK25 VSS48 VSS128 T32 D30 VSS206 VSS_NCTF3 AR34 TP20 B19 RSVD15
AK20 VSS49 VSS129 T31 D26 VSS207 VSS_NCTF4 B34 TP22 A19 RSVD16
AK17 T30 D9 B2 TP34
NCTF
VSS50 VSS130 VSS208 VSS_NCTF5
AJ31 VSS51 VSS131 T29 D6 VSS209 VSS_NCTF6 B1 TP25 A20 RSVD17
AJ23 VSS52 VSS132 T28 D3 VSS210 VSS_NCTF7 A35 TP26 B20 RSVD18
AJ20 VSS53 VSS133 T27 C34 VSS211 RSVD_TP_66 AA5
AJ17 VSS54 VSS134 T26 C32 VSS212 U9 RSVD19 RSVD_TP_67 AA4
AJ14 VSS55 VSS135 T6 C29 VSS213 T9 RSVD20 RSVD_TP_68 R8
AJ11 VSS56 VSS136 R10 C28 VSS214 RSVD_TP_69 AD3
AJ8 VSS57 VSS137 P8 C24 VSS215 AC9 RSVD21 RSVD_TP_70 AD2
AJ5 VSS58 VSS138 P4 C22 VSS216 AB9 RSVD22 RSVD_TP_71 AA2
AJ2 VSS59 VSS139 P2 C20 VSS217 RSVD_TP_72 AA1
AH35 VSS60 VSS140 N35 C19 VSS218 RSVD_TP_73 R9
AH34 VSS61 VSS141 N34 C16 VSS219 RSVD_TP_74 AG7
AH33 VSS62 VSS142 N33 B31 VSS220 C1 RSVD_NCTF_23 RSVD_TP_75 AE3
AH32 VSS63 VSS143 N32 B25 VSS221 A3 RSVD_NCTF_24
AH31 VSS64 VSS144 N31 B21 VSS222
AH30 VSS65 VSS145 N30 B18 VSS223 RSVD_TP_76 V4
AH29 VSS66 VSS146 N29 B17 VSS224 RSVD_TP_77 V5
AH28 VSS67 VSS147 N28 B13 VSS225 RSVD_TP_78 N2
AH27 VSS68 VSS148 N27 B11 VSS226 J29 RSVD26 RSVD_TP_79 AD5
AH26 VSS69 VSS149 N26 B8 VSS227 J28 RSVD27 RSVD_TP_80 AD7
AH20 VSS70 VSS150 N6 B6 VSS228 RSVD_TP_81 W3
AH17 VSS71 VSS151 M10 B4 VSS229 A34 RSVD_NCTF_28 RSVD_TP_82 W2
AH13 VSS72 VSS152 L35 A29 VSS230 A33 RSVD_NCTF_29 RSVD_TP_83 N3
B B
AH9 VSS73 VSS153 L32 A27 VSS231 RSVD_TP_84 AE5
AH6 VSS74 VSS154 L29 A23 VSS232 C35 RSVD_NCTF_30 RSVD_TP_85 AD9
AH3 VSS75 VSS155 L8 A9 VSS233 B35 RSVD_NCTF_31
AG10 VSS76 VSS156 L5
AF8 VSS77 VSS157 L2 VSS AP34 TP19
AF4 VSS78 VSS158 K34
AF2 K33 AP34 can be NC on CRB; EDS/DG suggestion to GND
VSS79 VSS159
AE35 VSS80 VSS160 K30
Clarksfield/Auburndale Clarksfield/Auburndale
Processor Strapping
1 0 DEFAULT
CFG0 CFG0 R128 *3.01K_NC
(PCI-Epress Single PEG Bifurcation enabled 1
Configuration Select)
CFG3
(PCI-Epress Static Normal Operation Lane Numbers Reversed CFG3 R125
1 3.01K/F_4
Lane Reversal)
A CFG4 Enabled; An external Display port A
(Embended Disabled; No Physical Display Port device is connected to the Embedded CFG4 R127
1 *3.01K
Display Port Presence) attached to Embedded Diplay Port Display port
7
V
K CFG7 R126 *3.01K/F_4
,S
H
D
Q
H
PROJECT : ZQH
F
Q
WF
&
1A
R
G
AUBURNDA 4/4
H
LO
www.vinafix.vn
P
OID
5 4 3 2 1
S
%
LU
R
*
UF
N
5 4 3 2 1
IBEX PEAK-M (DMI,FDI,GPIO) AC-coupling CAP place close to PCH
IBEX PEAK-M (LVDS,DDI)

U21C
BA18 FDI_TXN0 <4>
FDI_RXN0 U21D
<4> DMI_RXN0 BC24 BH17 FDI_TXN1 <4>
DMI0RXN FDI_RXN1
<4> DMI_RXN1 BJ22 BD16 FDI_TXN2 <4> <16> INT_LVDS_BLON T48 BJ46
DMI1RXN FDI_RXN2 L_BKLTEN SDVO_TVCLKINN
D <4> DMI_RXN2 AW20 BJ16 FDI_TXN3 <4> <16> INT_LVDS_DIGON T47 BG46 D
DMI2RXN FDI_RXN3 L_VDD_EN SDVO_TVCLKINP
<4> DMI_RXN3 BJ20 BA16 FDI_TXN4 <4>
DMI3RXN FDI_RXN4
BE14 FDI_TXN5 <4> <16> INT_LVDS_BRIGHT Y48 BJ48
FDI_RXN5 L_BKLTCTL SDVO_STALLN
<4> DMI_RXP0 BD24 BA14 FDI_TXN6 <4> BG48
DMI0RXP FDI_RXN6 SDVO_STALLP
<4> DMI_RXP1 BG22 BC12 FDI_TXN7 <4> <16> INT_LVDS_EDIDCLK AB48
DMI1RXP FDI_RXN7 L_DDC_CLK
<4> DMI_RXP2 BA20 <16> INT_LVDS_EDIDDATA Y45 BF45
DMI2RXP L_DDC_DATA SDVO_INTN
<4> DMI_RXP3 BG20 BB18 FDI_TXP0 <4> BH45
DMI3RXP FDI_RXP0 R119 10K_4 SDVO_INTP
BF17 FDI_TXP1 <4> +3V AB46
FDI_RXP1 R120 10K_4 L_CTRL_CLK
<4> DMI_TXN0 BE22 BC16 FDI_TXP2 <4> V48
DMI0TXN FDI_RXP2 L_CTRL_DATA
<4> DMI_TXN1 BF21 BG16 FDI_TXP3 <4>
DMI1TXN FDI_RXP3 R144 2.37K/F_4
<4> DMI_TXN2 BD20 AW16 FDI_TXP4 <4> AP39 T51 SDVO_CTRLCLK <17>
DMI2TXN FDI_RXP4 LVD_IBG SDVO_CTRLCLK
<4> DMI_TXN3 BE18 BD14 FDI_TXP5 <4> AP41 T53 SDVO_CTRLDAT <17>
DMI3TXN FDI_RXP5 LVD_VBG SDVO_CTRLDATA
BB14 FDI_TXP6 <4>
FDI_RXP6 R111 0_4
<4> DMI_TXP0 BD22 BD12 FDI_TXP7 <4> AT43
DMI0TXP FDI_RXP7 R112 0_4 LVD_VREFH
<4> DMI_TXP1 BH21 AT42 BG44
DMI1TXP LVD_VREFL DDPB_AUXN
<4> DMI_TXP2 BC20 BJ44
DMI2TXP DDPB_AUXP
<4> DMI_TXP3 BD18 BJ14 FDI_INT <4> AU38 INT_HDMI_HPD <17>
DMI3TXP FDI_INT DDPB_HPD
LVDS
<16> INT_TXLCLKOUT- INT_TXLCLKOUT- AV53
DMI
FDI
INT_TXLCLKOUT+ AV51 LVDSA_CLK# INT_HDMITX2N_R C249 0.1u/10V_4_X7R
BF13 FDI_FSYNC0 <4> <16> INT_TXLCLKOUT+ BD42 INT_HDMITX2N <17>
FDI_FSYNC0 LVDSA_CLK DDPB_0N INT_HDMITX2P_R C247 0.1u/10V_4_X7R
BH25 BC42 INT_HDMITX2P <17>
DMI_ZCOMP INT_TXLOUT0- DDPB_0P INT_HDMITX1N_R C242 0.1u/10V_4_X7R
BH13 FDI_FSYNC1 <4> <16> INT_TXLOUT0- BB47 BJ42 INT_HDMITX1N <17>
R441 49.9/F_4 FDI_FSYNC1 INT_TXLOUT1- LVDSA_DATA#0 DDPB_1N INT_HDMITX1P_R C245 0.1u/10V_4_X7R
BF25 BA52 BG42
Digital Display Interface

+1.05V DMI_IRCOMP <16> INT_TXLOUT1- LVDSA_DATA#1 DDPB_1P INT_HDMITX1P <17>
BJ12 INT_TXLOUT2- AY48 BB40 INT_HDMITX0N_R C253 0.1u/10V_4_X7R
FDI_LSYNC0 FDI_LSYNC0 <4> <16> INT_TXLOUT2- LVDSA_DATA#2 DDPB_2N INT_HDMITX0N <17>
AV47 BA40 INT_HDMITX0P_R C250 0.1u/10V_4_X7R
LVDSA_DATA#3 DDPB_2P INT_HDMITX0P <17>
BG14 AW38 INT_HDMICLK-_R C237 0.1u/10V_4_X7R
FDI_LSYNC1 FDI_LSYNC1 <4> DDPB_3N INT_HDMICLK- <17>
<16> INT_TXLOUT0+ INT_TXLOUT0+ BB48 BA38 INT_HDMICLK+_R C241 0.1u/10V_4_X7R
LVDSA_DATA0 DDPB_3P INT_HDMICLK+ <17>
<16> INT_TXLOUT1+ INT_TXLOUT1+ BA50
INT_TXLOUT2+ LVDSA_DATA1
C <16> INT_TXLOUT2+ AY49 C
LVDSA_DATA2
AV48 Y49
LVDSA_DATA3 DDPC_CTRLCLK
AB49
DDPC_CTRLDATA
AP48
XDP_DBRST# LVDSB_CLK#
<4> XDP_DBRST# T6 J12 PCIE_WAKE# <18,19> AP47 BE44
SYS_RESET# WAKE# LVDSB_CLK DDPC_AUXN
BD44
DDPC_AUXP
AY53 AV40
SYS_PWROK LVDSB_DATA#0 DDPC_HPD
M6 Y1 CLKRUN# <27> AT49
SYS_PWROK CLKRUN# / GPIO32 LVDSB_DATA#1
AU52 BE40
LVDSB_DATA#2 DDPC_0N
AT53 BD40
LVDSB_DATA#3 DDPC_0P
System Power Management
B17 BF41
PWROK DDPC_1N
AY51 BH41
LVDSB_DATA0 DDPC_1P
AT48 BD38
LVDSB_DATA1 DDPC_2N
K5 P8 AU50 BC38
MEPWROK SUS_STAT# / GPIO61 LVDSB_DATA2 DDPC_2P
AT51 BB36
LVDSB_DATA3 DDPC_3N
BA36
RSV_ICH_LAN_RST# A10 R234 *Short_4 DDPC_3P
F3 ICH_SUSCLK <27>
LAN_RST# SUSCLK / GPIO62
INT_CRT_BLU AA52 U50
<16> INT_CRT_BLU CRT_BLUE DDPD_CTRLCLK
D9 E4 INT_CRT_GRN AB53 U52
<4> PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63 <16> INT_CRT_GRN CRT_GREEN DDPD_CTRLDATA
INT_CRT_RED AD53
<16> INT_CRT_RED CRT_RED
<27> ICH_RSMRST# C16 H7 SUSC# <27> BC46

RSMRST# SLP_S4# DDPD_AUXN
<16> INT_CRT_DDCCLK V51
CRT_DDC_CLK DDPD_AUXP
BD46 R place close to PCH
<16> INT_CRT_DDCDAT V53 AT38
SUS_PWR_ACK_R CRT_DDC_DATA DDPD_HPD R425 150_4 INT_CRT_BLU
M1 P12 SUSB# <27>
SUS_PWR_DN_ACK / GPIO30 SLP_S3#
B BJ40 B
DDPD_0N R426 150_4 INT_CRT_GRN
<16> INT_HSYNC Y53 BG40
SLP_M# R225 *0_4 CRT_HSYNC DDPD_0P
<27> DNBSWON# P5 K8 <16> INT_VSYNC Y51 BJ38
PWRBTN# SLP_M# CRT_VSYNC DDPD_1N R427 150_4 INT_CRT_RED
BG38
DDPD_1P
CRT
BF37
R246 *0_4 ACIN_R DAC_IREF DDPD_2N
<27> PCH_ACIN P7 N2 TP32 AD48 BH37
ACPRESENT / GPIO31 TP23 DAC_IREF DDPD_2P
AB51 BE36
CRT_IRTN DDPD_3N
BD36
PM_BATLOW# R134 DDPD_3P
A6 BJ10 PM_SYNC <4>
BATLOW# / GPIO72 PMSYNCH 1K/F_4 IbexPeak-M_R1P0
PM_RI# F14 F6 PM_SLP_LAN# TP18

RI# SLP_LAN# / GPIO29
IbexPeak-M_R1P0
PCH Pull-high/low +3V_S5

System PWR_OK
+3V
PM_RI# R184 10K_4

CLKRUN# R523 8.2K_4 +3V_S5
PM_BATLOW# R514 10K_4 '(/$<B95B3:5*22'QHHG38.WR9
XDP_DBRST# R226 1K_4 C636 *.1u_4
A
PCIE_WAKE# R230 10K_4
38DWSRZHUVLGH A
5
ICH_RSMRST# R482 10K_4 PM_SLP_LAN# R248 *10K_4 1 DELAY_VR_PWRGOOD <4,30>
SYS_PWROK 4
RSV_ICH_LAN_RST# R499 10K_4 SUS_PWR_ACK_R R530 10K_4 2
U24
PWROK_EC <27>
3
SYS_PWROK R477 10K_4 ACIN_R R227 10K_4 R538 100K_4
TC7SH08FU
PROJECT : ZQH
1A
IBEX PEAK-M 1/6
5 4 3 2 1
5 4 3 2 1
RTC Circuitry C335

15p/50V_4
2
1
+VCCRTC
CR1 Y1
R195
+3VPCU U21A
R483 20K/F_4 RTC_RST# 32.768KHZ 10M_4
VCCRTC_1
3
4
C328
1
RTC_X1 B13 D33
RTCX1 FWH0 / LAD0 LPC_LAD0 <19,27>
BAT54C C662 J2 15p/50V_4 RTC_X2 D13 B33
RTCX2 FWH1 / LAD1 LPC_LAD1 <19,27>
R473 1u/10V_4 *SHORT_ PAD1 C32
FWH2 / LAD2 LPC_LAD2 <19,27>
1K_4 A32 LPC_LAD3 <19,27>
2
RTC_RST# FWH3 / LAD3
C14
RTCRST#
C34 LPC_LFRAME# <19,27>
N18608864 SRTC_RST# FWH4 / LFRAME#
D17
D
R474 20K/F_4 SRTC_RST# SRTCRST# D
A34
RTC
LPC
1
R479 1M_4 SM_INTRUDER# LDRQ0#

+VCCRTC A16 F34
INTRUDER# LDRQ1# / GPIO23
1
BT1 R222 10K_4 +3V
RTC_CONN C663 C650 J1 PCH_INVRMEN A14 AB9
INTVRMEN SERIRQ IRQ_SERIRQ <27>
1u/10V_4 1u/10V_4 *SHORT_ PAD1
2
2
HDA_SYNC (PCH strap pin) ACZ_BIT_CLK A30
HDA_BCLK SATA_RXN0_C
AK7 SATA_RXN0_C <20>
ACZ_SYNC SATA0RXN SATA_RXP0_C
Internal weak pull-down D29 AK6 SATA_RXP0_C <20>
HDA_SYNC SATA0RXP
VCCVRM=>+1.8V (default) AK11 SATA_TXN0 <20>
SPKR SATA0TXN
external pull-up <21> SPKR P1 AK9 SATA_TXP0 <20>
SPKR SATA0TXP
VCCVRM=>+1.5V ACZ_RST# C30
HDA_RST# SATA_RXN1_C
AH6 SATA_RXN1_C <20>
SATA1RXN SATA_RXP1_C
AH5 SATA_RXP1_C <20>
SATA1RXP
<21> PCH_AZ_CODEC_SDIN0 G30 AH9 SATA_TXN1 <20>
HDA_SDIN0 SATA1TXN
AH8 SATA_TXP1 <20>
SATA1TXP
F30
HDA_SDIN1
AF11
SATA2RXN
E32 AF9
IHDA
HDA_SDIN2 SATA2RXP
AF7
SATA2TXN
F32
HDA_SDIN3 SATA2TXP
AF6 Note:
SATA port2/3 may not be available on all PCH sku
AH3
ACZ_SDOUT B29
SATA3RXN
AH1
(HM55 support 3 port only)
HDA_SDO SATA3RXP
AF3
SATA3TXN
AF1
PCH_GPIO33 SATA3TXP
H32
SATA
HDA_DOCK_EN# / GPIO33
AD9
R460 *10K_4 PCH_GPIO13 SATA4RXN
+3V_S5 J30 AD8
HDA_DOCK_RST# / GPIO13 SATA4RXP
AD6
SATA4TXN
AD5
HDA Bus <17> HDMI_HPD_PCH#
SATA4TXP
M3 AD3
JTAG_TCK SATA5RXN
AD1
SATA5RXP
K3 AB3
R453 33_4 ACZ_SYNC JTAG_TMS SATA5TXN
C
<21> PCH_AZ_CODEC_SYNC AB1 C
SATA5TXP
K1
JTAG_TDI
JTAG
R449 33_4 ACZ_RST# J2 AF16
<21> PCH_AZ_CODEC_RST# JTAG_TDO SATAICOMPO
J4 AF15 R182 37.4/F_4 +1.05V
R456 33_4 ACZ_SDOUT TRST# SATAICOMPI
<21> PCH_AZ_CODEC_SDOUT
SPI_CLK_R BA2
SPI_CLK
R450 33_4 ACZ_BIT_CLK SPI_CS0#_R AV3
<21> PCH_AZ_CODEC_BITCLK SPI_CS0#
+3VPCU R525 *10K_4 SPI_CS1# AY3 T3

C628 SPI_CS1# SATALED# TP13
*27p_4
SPI_SI_R AY1 Y9 R240 43K/F_4 +3V
SPI_MOSI SATA0GP / GPIO21
SPI
SPI_SO_R AV1 V1 R521 43K/F_4 +3V
SPI_MISO SATA1GP / GPIO19
IbexPeak-M_R1P0
3&+6WUDS3LQ&RQILJXUDWLRQ7DEOH
INTVRMEN Integrated 1.05V VRM Enable / 1 = Integrated VRM is enabled
R489 330K_6 PCH_INVRMEN
Disable 0 = Integrated VRM is disabled +VCCRTC
SPI_MOSI TPM Functionality 1 = Enabled

Disable R540 *1K_4 SPI_SI_R
0 = Disable +3V
PCH SPI
SPKR Reboot option at power-up 0 = Default Mode (Internal weak Pull-down)
R532 *1K/F_4 SPKR
1 = No Reboot Mode with TCO Disabled +3V
B 0 = Flash Descriptor Security will be overridden B

HDA_DOCK_EN Flash Descriptor 1 = Security measure defined in the Flash
PCH_GPIO33 R164 *1K/F_4
#/GPIO33 Security Override Descriptor will be enabled.
R145 *10K_4 +3V
+3V
U25
SPI_CS0#_R 1 8 R129 1K_4 +3V
SPI_CLK_R CE# VDD R122 1K_4
6
SCK GNT0#, (0,0) = LPC (0,1) = Reserved NAND
SPI_SI_R 5 Boot BIOS Strap R123 *1K_4
SPI_SO_R 2
SI
7 R539 3.3K/F_4 GNT1# (1,0) = PCI (1,1) = SPI <10> PCI_GNT0#
R131 *1K_4
SO HOLD# <10> PCI_GNT1#
3
WP# VSS
4 GNT2#/ ESI compatible mode is for server
C671 ESI Strap
W25Q32BVSSIG .1u/10V_4 GPIO53 platforms only R158 *1K/F_4
(Server Only) <10> PWM_SELECT#
GNT3#/ Top-Block 0 = Top Block Swap Mode

R541 3.3K/F_4 R421 *10K/F_4
+3V
GPIO55 Swap Override 1 = Default Mode (Internal pull-up) <10> PCI_GNT3#
IntelR Anti-Theft Technology

HDD Data Protection 1 = Enabled
NV_ALE R202 *1K/F_4
(Intel AT-d) Enable 0 = Disabled (Default) <10> NV_ALE +1.8V
NV_CLE DMI Termination DMI termination voltage. Weak

R206 *1K/F_4
Voltage internal pull-up. Do not pull low. <10> NV_CLE +1.8V
GPIO8 Reserved This signal has a weak internal pull up.

R204 10K_4
NOTE: This signal should not be pulled low<11> RSV_GPIO8 +3V_S5
R203 *1K_4
0 = Intel ME Crypto Transport Layer Security

(TLS) cipher suite with no confidentiality
GPIO15 Reserved
A 1 = Intel ME Crypto Transport Layer Security<11> CR_WAKE# R244 1K_4 +3V_S5 A
(TLS) cipher suite with confidentiality
GPIO27 On-Die PLL Voltage 0 = Disables the VccVRM.

Regulator 1 = Enables the internal VccVRM to have
<internal weak pull-up> a clean supply for analog rails. <11> PCH_GPIO27 R221 *10K_4

PROJECT : ZQH
1A
IBEX PEAK-M 2/6
5 4 3 2 1
5 4 3 2 1
U21B
U21E
H40 AY9 BG30 B9 RSV_SMBALERT#
AD0 NV_CE#0 <18> PCIE_RX1- PERN1 SMBALERT# / GPIO11
N34 BD1 <18> PCIE_RX1+ BJ30
AD1 NV_CE#1 C615 0.1u/10V_4_X7R PCIE_TXN1_C PERP1 ICH_SMBCLK
C44 AP15 LAN <18> PCIE_TX1- BF29 H14 ICH_SMBCLK <3>
AD2 NV_CE#2 C616 0.1u/10V_4_X7R PCIE_TXP1_C PETN1 SMBCLK
A38 BD8 <18> PCIE_TX1+ BH29
AD3 NV_CE#3 PETP1 ICH_SMBDATA
C36 C8 ICH_SMBDATA <3>
AD4 SMBDATA
J34 AV9 AW30
AD5 NV_DQS0 PERN2
A40 BG8 BA30
AD6 NV_DQS1 PERP2 RSV_SML0ALERT#
D45 BC30 J14
D AD7 PETN2 SML0ALERT# / GPIO60 D
E36 AP7 BD30
AD8 NV_DQ0 / NV_IO0 PETP2 SMB_CLK_ME0
H48 AP6 C6
AD9 NV_DQ1 / NV_IO1 SML0CLK
E40 AT6 AU30
SMBus
AD10 NV_DQ2 / NV_IO2 PERN3 SMB_DATA_ME0
C40 AT9 AT30 G8
AD11 NV_DQ3 / NV_IO3 PERP3 SML0DATA
M48 BB1 AU32
AD12 NV_DQ4 / NV_IO4 PETN3
M45 AV6 AV32
AD13 NV_DQ5 / NV_IO5 PETP3 RSV_SML1ALERT# R242 *0_4
F53 BB3 M14 SML1ALERT# <11,26,27>
AD14 NV_DQ6 / NV_IO6 SML1ALERT# / GPIO74
M40 BA4 BA32
AD15 NV_DQ7 / NV_IO7 PERN4 SMB_CLK_ME1
NVRAM
M43 BE4 BB32 E10
AD16 NV_DQ8 / NV_IO8 PERP4 SML1CLK / GPIO58
J36 BB6 BD32
AD17 NV_DQ9 / NV_IO9 PETN4 SMB_DATA_ME1
K48 BD6 BE32 G12
AD18 NV_DQ10 / NV_IO10 PETP4 SML1DATA / GPIO75
F40 BB7
PCI-E*
AD19 NV_DQ11 / NV_IO11
C42 BC8 BF33
AD20 NV_DQ12 / NV_IO12 PERN5 CL_CLK1
K46 BJ8 BH33 T13 CL_CLK1 <19>
AD21 NV_DQ13 / NV_IO13 PERP5 CL_CLK1
Controller
M51 BJ6 BG32
AD22 NV_DQ14 / NV_IO14 PETN5 CL_DATA1
J52 BG6 BJ32 T11 CL_DATA1 <19>
AD23 NV_DQ15 / NV_IO15 PETP5 CL_DATA1
K51
Link
AD24 NV_ALE CL_RST1#
L34 BD3 NV_ALE <9> <19> PCIE_RX6- BA34 T9 CL_RST1# <19>
AD25 NV_ALE NV_CLE PERN6 CL_RST1#
F42 AY6 NV_CLE <9> <19> PCIE_RX6+ AW34
AD26 NV_CLE C259 0.1u/10V_4_X7R PCIE_TXN6_C PERP6
J40 Wireless <19> PCIE_TX6- BC34
AD27 C268 0.1u/10V_4_X7R PCIE_TXP6_C PETN6
G46 <19> PCIE_TX6+ BD34
AD28 PETP6
F44 AU2 NV_RCOMP R508 *32.4/F_4 H1 PEG_CLKREQ#_R
AD29 NV_RCOMP PEG_A_CLKRQ# / GPIO47
M47 AT34
AD30 PERN7
PCI
H36 AV7 AU34
AD31 NV_RB# PERP7
AU36 AD43
PETN7 CLKOUT_PEG_A_N
J50 AY8 AV36 AD45
C/BE0# NV_WR#0_RE# PETP7 CLKOUT_PEG_A_P
G42 AY5
C/BE1# NV_WR#1_RE#
H47 BG34 AN4 CLK_PCIE_3GPLL# <4>
C/BE2# PERN8 CLKOUT_DMI_N
PEG
G34 AV11 BJ34 AN2 CLK_PCIE_3GPLL <4>
C/BE3# NV_WE#_CK0 PERP8 CLKOUT_DMI_P
BF5 BG36
PCI_PIRQA# NV_WE#_CK1 PETN8
G38 BJ36
PCI_PIRQB# PIRQA# PETP8
H51 AT1 DPLL_REF_SSCLK# <4>
PCI_PIRQC# PIRQB# CLKOUT_DP_N / CLKOUT_BCLK1_N
B37
PIRQC# USBP0N
H18 Port1 and port9 can be used on debug mode CLKOUT_DP_P / CLKOUT_BCLK1_P
AT3 DPLL_REF_SSCLK <4>
PCI_PIRQD# A44 J18 AK48
PIRQD# USBP0P CLKOUT_PCIE0N
A18 USBP1- <25> AK47
USBP1N CLKOUT_PCIE0P
From CLK BUFFER

PCI_REQ0# F51 C18 MB USB AW24
C PCI_REQ1# REQ0# USBP1P USBP1+ <25> CLK_PCIE_REQ0# CLKIN_DMI_N CLK_BUF_PCIE_3GPLL# <3> C
A46 N20 P9 BA24 CLK_BUF_PCIE_3GPLL <3>
dGPU_SELECT# REQ1# / GPIO50 USBP2N PCIECLKRQ0# / GPIO73 CLKIN_DMI_P
TP1 B45 P20
PCI_REQ3# REQ2# / GPIO52 USBP2P
M53 J20
REQ3# / GPIO54 USBP3N
TP3 L20 AM43 AP3 CLK_BUF_BCLK# <3>
PCI_GNT0# USBP3P CLKOUT_PCIE1N CLKIN_BCLK_N
<9> PCI_GNT0# F48
GNT0# USBP4N
F20 USBP4- <25> EHCI1 AM45
CLKOUT_PCIE1P CLKIN_BCLK_P
AP1 CLK_BUF_BCLK <3>
PCI_GNT1# K45 G20 BLUETOOTH 3.0
<9> PCI_GNT1# PWM_SELECT# GNT1# / GPIO51 USBP4P USBP4+ <25> CLK_PCIE_REQ1#_R
<9> PWM_SELECT# F36 A20 TP29 U4
PCI_GNT3# GNT2# / GPIO53 USBP5N PCIECLKRQ1# / GPIO18
<9> PCI_GNT3# H53 C20 TP30 F18 CLK_BUF_DREFCLK# <3>
GNT3# / GPIO55 USBP5P CLKIN_DOT_96N
M22 E18 CLK_BUF_DREFCLK <3>
PCI_PIRQE# USBP6N USB port6/7 may not be available on all PCH sku CLKIN_DOT_96P
B41 N22 <19> CLK_PCH_SRC2# AM47
PCI_PIRQF# PIRQE# / GPIO2 USBP6P CLKOUT_PCIE2N
K53 B21 (HM55 support 12port only) <19> CLK_PCH_SRC2 AM48
PCI_PIRQG# PIRQF# / GPIO3 USBP7N CLKOUT_PCIE2P
A36 D21 AH13 CLK_BUF_DREFSSCLK# <3>
PCI_PIRQH# PIRQG# / GPIO4 USBP7P R531 *Short_4CLK_PCIE_REQ2#_R CLKIN_SATA_N / CKSSCD_N
A48 H22 USBP8- <16> <19> PCIE_CLK_REQ2# N4 AH12 CLK_BUF_DREFSSCLK <3>
PIRQH# / GPIO5 USBP8N PCIECLKRQ2# / GPIO20 CLKIN_SATA_P / CKSSCD_P
USBP8P
J22 USBP8+ <16> Camera
USB
PCI_RST# K6 E22
<19> PCI_RST# PCIRST# USBP9N USBP9- <25>
USBP9P
F22 USBP9+ <25> USB/B-USB1-2 AH42
CLKOUT_PCIE3N REFCLK14IN
P41 CLK_ICH_14M <3>
PCI_SERR# E44 A22 AH41
SERR# USBP10N TP28 CLKOUT_PCIE3P
PCI_PERR# E50 C22 C600 27p/50V_4
PERR# USBP10P TP27
G24 EHCI2 CLK_PCIE_REQ3# A8 J42 CLK_PCI_FB
USBP11N USBP11- <25> PCIECLKRQ3# / GPIO25 CLKIN_PCILOOPBACK
USBP11P
H24 USBP11+ <25> USB/B-USB1-1
1
PCI_IRDY# A42 L24
IRDY# USBP12N USBP12- <23> XTAL25_IN
H44 M24 Card Reader AM51 AH51 R428 Y5
PCI_DEVSEL# PAR USBP12P USBP12+ <23> CLKOUT_PCIE4N XTAL25_IN XTAL25_OUT
F46 A24 AM53 AH53 1M_4 25MHz
PCI_FRAME# DEVSEL# USBP13N USBP13- <19> CLKOUT_PCIE4P XTAL25_OUT
C46 C24 Mini Card (WLAN )
2
FRAME# USBP13P USBP13+ <19> CLK_PCIE_REQ4# M9 AF38 XCLK_RCOMP R141 90.9/F_4 +1.05V C599 27p/50V_4
PCI_PLOCK# PCIECLKRQ4# / GPIO26 XCLK_RCOMP
D49
PLOCK# USB_BIAS R466 22.6/F_4
B25
PCI_STOP# USBRBIAS# BOARD_ID1
D41 AJ50 T45
PCI_TRDY# STOP# CLKOUT_PCIE5N CLKOUTFLEX0 / GPIO64
C48 D25 AJ52
TRDY# USBRBIAS TP4 CLKOUT_PCIE5P
ICH_PME# M7 CLK_PCIE_REQ5# H6 P43 BOARD_ID2
Clock Flex
TP15 PME# PCIECLKRQ5# / GPIO44 CLKOUTFLEX1 / GPIO65
N16 USB_OC0#
PCI_PLTRST# OC0# / GPIO59 USB_OC1# USB_OC0# <25>
D5 J16 TP5
PLTRST# OC1# / GPIO40 USB_OC2# BOARD_ID3
F16 TP11 <18> CLK_PCIE_LOM# AK53 T42
R423 22_4 CLK_LPC_DEBUG_C OC2# / GPIO41 USB_OC3# CLKOUT_PEG_B_N CLKOUTFLEX2 / GPIO66
<19> CLK_LPC_DEBUG N52 L16 TP10 <18> CLK_PCIE_LOM AK51
TP21 CLK_PCI_PCCARD CLKOUT_PCI0 OC3# / GPIO42 USB_OC4_5# CLKOUT_PEG_B_P
P53 E14 USB_OC4_5# <25>
B R105 22_4 CLK_PCI_775_C CLKOUT_PCI1 OC4# / GPIO43 R233 *Short_4PCIE_CLK_REQB# R760 *0_4 B
<27> CLK_PCI_775 P46 G16 <18> CLK_PCIE_LAN_REQ# P13 N50 EXT48MHZ <23>
CLK_PCI_FB R117 22_4 CLK_PCI_FB_C CLKOUT_PCI2 OC5# / GPIO9 USB_OC6# PEG_B_CLKRQ# / GPIO56 CLKOUTFLEX3 / GPIO67
P51 F12 TP6
CLKOUT_PCI3 OC6# / GPIO10 USB_OC7#
P48 T15 TP7
CLKOUT_PCI4 OC7# / GPIO14 IbexPeak-M_R1P0
IbexPeak-M_R1P0
48MHz output for cardreader
+3V +3V_S5
+3V_S5
+3V_S5 R406 *10K_4 BOARD_ID1 R132 10K_4
RP2 R245 10K_4 CLK_PCIE_REQ0#
USB_OC3# 6 5 R513 10K_4 CLK_PCIE_REQ3# R407 10K_4 BOARD_ID2 R136 *10K_4 R180
USB_OC2# 7 4 USB_OC1# R229 10K_4 CLK_PCIE_REQ4#
2
USB_OC4_5# 8 3 USB_OC0# R247 10K_4 CLK_PCIE_REQ5# R408 *10K_4 BOARD_ID3 R414 10K_4 2.2K_4
9 2 USB_OC6# R232 10K_4 PCIE_CLK_REQB#
+3V_S5 10 1 USB_OC7# R517 10K_4 PEG_CLKREQ#_R 1 3 SMB_CLK_ME1
+3V_S5 <27> 2ND_MBCLK
Q4
8.2K_10P8R +3V 2N7002K
C353 R534 10K_4 CLK_PCIE_REQ1#_R +3V_S5

+3V BOARD_ID1 Not Defined
.1u/10V_4 RP4 +3V
PCI_PIRQD# 6 5
5
PCI_REQ1# 7 4 PCI_REQ3# High = 80port output to LPC

PCI_PLTRST# 2 PCI_FRAME# 8 3 PCI_PIRQB# BOARD_ID2 R181
4 PCI_TRDY# 9 2 PCI_REQ0# R138 10K_4 dGPU_SELECT# Low = 80port output to PCI
PLTRST# <4,18,19,23,27>
2
1 10 1 PCI_PIRQH# R139 8.2K_4 PCI_PIRQE# 2.2K_4
A
+3V A
R422 8.2K_4 PCI_PIRQF# High = Reserved
U7 R251 8.2K_10P8R R143 8.2K_4 PCI_PIRQG# BOARD_ID3 1 3 SMB_DATA_ME1
3
CLK_PCIE_REQ2#_R <27> 2ND_MBDATA

TC7SH08FU R518 10K_4 Low = Reserved (Default) Q5
100K_4 2N7002K
+3V
RP1
PCI_PIRQC# 6 5
R249 *0_4 PCI_PIRQA# 7 4 PCI_DEVSEL#
PCI_STOP# 8 3 PCI_PLOCK# +3V_S5
PCI_IRDY# 9 2 PCI_PERR#
+3V 10 1 PCI_SERR# R504 10K_4 RSV_SMBALERT#
RSV_SML0ALERT#
R211 10K_4
8.2K_10P8R R243 10K_4 RSV_SML1ALERT#
R512 2.2K_4 ICH_SMBCLK PROJECT : ZQH
R511 2.2K_4 ICH_SMBDATA Size Document Number Rev
R214 2.2K_4 SMB_CLK_ME0 1A
R212 2.2K_4 SMB_DATA_ME0 IBEX PEAK-M 3/6
5 4 3 2 1
5 4 3 2 1
GPU RST#
D D
IBEX PEAK-M (GPIO,VSS_NCTF,RSVD)
U21F
TP31 BMBUSY# Y3 AH45

BMBUSY# / GPIO0 CLKOUT_PCIE6N
CLKOUT_PCIE6P AH46
<27> SIO_EXT_SMI# SIO_EXT_SMI# C38 TACH1 / GPIO1
<27> SIO_EXT_SCI# SIO_EXT_SCI# D37 TACH2 / GPIO6

CLKOUT_PCIE7N AF48
MISC
TP2 BOARD_ID0 J32 AF47
TACH3 / GPIO7 CLKOUT_PCIE7P
RSV_GPIO8 F10
<9> RSV_GPIO8 GPIO8
TP14 LAN_DISABLE# K9 U2
LAN_PHY_PWR_CTRL / GPIO12 A20GATE SIO_A20GATE <27>
CR_WAKE# T7
<9> CR_WAKE# GPIO15
dGPU_HOLD_RST# AA2 AM3
SATA4GP / GPIO16 CLKOUT_BCLK0_N / CLKOUT_PCIE8N CLK_CPU_BCLK# <4>
F38 TACH0 / GPIO17 CLKOUT_BCLK0_P / CLKOUT_PCIE8P AM1 CLK_CPU_BCLK <4>
GPIO22 Y7 BG10
SCLOCK / GPIO22 PECI H_PECI <4>
GPIO
H10 T1
GPIO Pull-up/Pull-down
GPIO24 RCIN# SIO_RCIN# <27>
PCH_GPIO27 AB12 BE10
<9> PCH_GPIO27 GPIO27 PROCPWRGD H_PWRGOOD <4,27>
CPU
+3V_S5
TP_PCH_GPIO28 V13 BD10 PCH_THRMTRIP#_R R197 56/F_4
GPIO28 THRMTRIP# PM_THRMTRIP# <4>
C C
STP_PCI# M11 R200 56/F_4 +1.05V
STP_PCI# / GPIO34 TP_PCH_GPIO28 R239 10K_4
V6 GPIO45 R516 10K_4
SATACLKREQ# / GPIO35 RST_GATE# R515 10K_4
TP17 dGPU_PWR_EN# AB7 BA22 GPIO57 R208 *10K_4
SATA2GP / GPIO36 TP1 LAN_DISABLE# R231 10K_4
TP12 dGPU_PRSNT# AB13 AW22
SATA3GP / GPIO37 TP2 +3V
dGPU_PWR_EN# should be stable GPIO38 V3 BB22
SLOAD / GPIO38 TP3 SIO_EXT_SMI# R146 10K_4
before dGPU_VRON enable
SAVE_LED# P3 AY45 SIO_EXT_SCI# R445 10K_4
SDATAOUT0 / GPIO39 TP4 dGPU_PWR_EN# R223 10K_4
GPIO45 H3 AY46
PCIECLKRQ6# / GPIO45 TP5
TP33 RST_GATE# F1 AV43
PCIECLKRQ7# / GPIO46 TP6
SV_SET_UP AB6 AV45 +3V
SDATAOUT1 / GPIO48 TP7
<10,26,27> SML1ALERT# R524 *Short_4 SATA5GP AA4 AF13 SIO_RCIN# R533 10K_4
SATA5GP / GPIO49 TP8 SIO_A20GATE R520 10K_4
EC suggestion use GPIO49 for FAN control GPIO57 F8 M18 dGPU_HOLD_RST# R536 *10K_4
GPIO57 TP9 SATA5GP R537 10K_4
N18 GPIO22 R224 10K_4
TP10
A4 AJ24 SAVE_LED# R519 10K_4
VSS_NCTF_1 TP11 STP_PCI# R228 10K_4
A49
NCTF
VSS_NCTF_2
RSVD
SATA5GP / GPIO49 / TEMP_ALERT# is used to A5

VSS_NCTF_3 TP12
AK41
A50 GPIO38 R535 10K_4
alert for EC when CPU or Graph/Memory A52
VSS_NCTF_4
AK42
VSS_NCTF_5 TP13
B
controllers' temperature go out of limit. A53
VSS_NCTF_6
BMBUSY# R522 8.2K_4 B
So connecting GPIO49 to EC and avoid this B2 M32
VSS_NCTF_7 TP14 SV_SET_UP R241 10K_4
B4
pin to be used for other purpose VSS_NCTF_8
B52 N32
VSS_NCTF_9 TP15
B53
VSS_NCTF_10 SV_SET_UP 1-X High = Strong (Default)
BE1 M30
VSS_NCTF_11 TP16
BE53
VSS_NCTF_12
BF1 N30
VSS_NCTF_13 TP17
BF53
VSS_NCTF_14 GPIO57 stuff PD and not stuff PU for Intel suggestion at 6/1
BH1 H12
VSS_NCTF_15 TP18
BH2
VSS_NCTF_16 GPIO57 R207 10K_4
BH52 AA23
VSS_NCTF_17 TP19
BH53
VSS_NCTF_18
BJ1 AB45
VSS_NCTF_19 NC_1
BJ2
VSS_NCTF_20
BJ4 AB38
VSS_NCTF_21 NC_2
BJ49
VSS_NCTF_22 R148 *10K_4 BOARD_ID0 R155 10K_4
BJ5 AB42 +3V
VSS_NCTF_23 NC_3
BJ50
VSS_NCTF_24 R238 10K_4 dGPU_PRSNT# R220 *10K_4
BJ52 AB41
VSS_NCTF_25 NC_4
BJ53
VSS_NCTF_26 dGPU always exist
D1 T39
VSS_NCTF_27 NC_5
D2
VSS_NCTF_28
D53
VSS_NCTF_29
E1 P6
VSS_NCTF_30 INIT3_3V# High = 15"
E53
VSS_NCTF_31 BOARD_ID0
C10
TP24 Low = 14"
IbexPeak-M_R1P0
High = Disable
RSV_GPIO8
A Low = Enable A

PROJECT : ZQH
1A
IBEX PEAK-M 4/6
5 4 3 2 1
5 4 3 2 1
3.3 V. This rail should be powered up during S0 system state.
IBEX PEAK-M (POWER) U21G POWER VCCADAC= 69mA(15mils)
Note that Thermal Sensor shares the same power supply rail with DAC.
The external filters on this pin are not needed in case internal graphic is
AB24 AE50 +VCCA_DAC_1_2 L44 disabled so only 3.3-V connection is required.
+1.05V VCCCORE[1] VCCADAC[1] +3V
AB26 PBY160808T/2A/180ohm_6
VCCCORE[2]
AB28 AE52
C291 C283 C340 VCCCORE[3] VCCADAC[2] C604.01u/25V_4 C574 C572
AD26
VCCCORE[4]
CRT
AD28 AF53
10u/6.3V_8 1u/6.3V_4 .1u/16V_4 AF26
VCCCORE[5]
VCCCORE[6]
VSSA_DAC[1] C598 22u/6.3V_8 22u/6.3V_8 U21J POWER VCCIO = 3.208A(150mils)
VCC CORE
AF28 AF51 0.1u/10V_4_X7R VCCACLK= 52mA(15mils)
VCCCORE[7] VSSA_DAC[2] L47 *10uh_8 +V1.1LAN_VCCA_CLK
AF30
VCCCORE[8]
VCCALVDS= 1mA +1.05V AP51
VCCACLK[1] VCCIO[5]
V24 +1.05V
AF31 C597 *10u/6.3V_6 V26
VCCCORE[9] R114 *Short_4 C603 *1u/6.3V_4 VCCIO[6] C295 1U/6.3V_4
AH26 +3V AP53 Y24
VCCCORE[10] VCCACLK[2] VCCIO[7]
VCCCORE(+1.05V) = 1.432A(80mils) AH28 Y26
VCCCORE[11] VCCIO[8]
AH30
VCCCORE[12]
VCCLAN = 320mA(30mils)
AH31 AH38 VCCALVDS +1.05V R175 *0_6 +1.05V_VCCAUX AF23 V28 +3V_S5_VCCPUSB R162 *SHORT0805 +3V_S5
D VCCCORE[13] VCCALVDS VCCLAN[1] VCCSUS3_3[1] D
AJ30 U28
VCCCORE[14] VCCSUS3_3[2] C303 0.1u/10V_4_X7R
AJ31 AH39 AF24 U26
VCCCORE[15] VSSA_LVDS VCCLAN[2] VCCSUS3_3[3] C290 0.1u/10V_4_X7R
U24
C300 VCCSUS3_3[4] C302 0.022U/16V_4
VCCTX_LVDS= 59mA(15mils) VCCSUS3_3[5]
P28
AP43 1U/6.3V_4 TP_PCH_VCCDSW Y20 P26
VCCTX_LVDS[1] VCCTX_LVDS L24 0.1UH_8/250mA +1.8V DCPSUSBYP VCCSUS3_3[6]
AP45 N28
VCCTX_LVDS[2] VCCSUS3_3[7]
AT46 N26
LVDS
R174 *SHORT0603 +1.05V_PCH_VCCDPLL_EXP VCCTX_LVDS[3] C256 C255 C248 C307 VCCSUS3_3[8]
+1.05V AK24 AT45 AD38 M28
VCCIO[24] VCCTX_LVDS[4] C482 change to 0 ohm resistor. VCCME[1] VCCSUS3_3[9]
1u/6.3V_4 M26
.01u/25V_4 .01u/25V_4 22u/6.3V_8 VCCSUS3_3[10]
AD39 L28
VCCSUS3_3 = 0.163A(20mils)
USB
L49 *1uh_6 +V1.1LAN_VCCAPLL_EXP VCCME[2] VCCSUS3_3[11]
40mA(15mils) +1.05V BJ24 L26
VCCAPLLEXP VCCSUS3_3[12]
AB34 AD41 J28
C629 *10u/6.3V_6 VCC3_3[2] VCCME[3] VCCSUS3_3[13]
J26
VCCSUS3_3[14] R172 *SHORT0603
AN20
VCCIO[25] VCC3_3[3]
AB35 VCC3_3 = 357mA(30mils) AF43
VCCME[4] VCCSUS3_3[15]
H28 +1.05V
AN22 H26
HVCMOS
VCCIO[26] +3V_VCC_GIO R417 *SHORT0603 VCCSUS3_3[16]
AN23 AD35 VCCME(+1.05V) = 1.849A(100mils) AF41 G28
AN24
VCCIO[27]
VCCIO[28]
VCC3_3[4] +3V VCCME[5] VCCSUS3_3[17]
VCCSUS3_3[18]
G26 V5REF_SUS< 1mA
AN26 C279 C339 +1.05V R140 *SHORT0805 +1.05V_VCCEPW AF42 F28 R468 100/F_4 +5V_S5
VCCIO[29] VCCME[6] VCCSUS3_3[19]
VCCIO = 3.062A(150mils) AN28
VCCIO[30] VCCSUS3_3[20]
F26
+1.05V BJ26 .1u/16V_4 .1u/16V_4 R150 0_8 V39 E28 D17 RB500V-40 +3V_S5
Clock and Miscellaneous

BJ28 E26
VCCIO[32] VCCSUS3_3[22] C639 1U/6.3V_4
AT26 V41 C28
AT28 C26
VCCIO[34] C257 22U/6.3V_8 VCCSUS3_3[24]
AU26 V42 B27
AU28
VCCIO[36]
VCCVRM= 196mA(15mils) VCCSUS3_3[26]
A28
C289 10U/6.3V_8 AV26 C269 22U/6.3V_8 Y39 A26
C292 1U/6.3V_4 VCCIO[37] +VCCVRM R178 *SHORT0603 VCCME[10] VCCSUS3_3[27]
AV28 AT24
C305 1U/6.3V_4 AW26
VCCIO[38]
VCCIO[39]
VCCVRM[2] +V1.5S_1.8S
C277 1U/6.3V_4 Y41
VCCME[11] VCCSUS3_3[28]
U23 V5REF< 1mA
C294 1U/6.3V_4 AW28 R115 100/F_4 +5V
VCCIO[40]
DMI
C282 1U/6.3V_4 BA26 AT16 +VCCDMI R194 *Short_4 +1.05V VCCDMI= 61mA(15mils) C278 1U/6.3V_4 Y42 V23
VCCIO[41] VCCDMI[1] VCCME[12] VCCIO[56] D4 RB500V-40
BA28 +3V
VCCIO[42] V5REF_SUS
BB26 AU16 F24
C VCCIO[43] VCCDMI[2] V5REF_SUS C240 1U/6.3V_4 C
BB28
VCCIO[44] +VCCRTCEXT
BC26 V9
VCCIO[45] DCPRTC
PCI E*
BC28 C324 C334 0.1u/10V_4_X7R
VCCIO[46] 1u/10V_4
BD26
VCCIO[47] V5REF
BD28 K49
VCCIO[48] V5REF
BE26 AM16 +V1.5S_1.8S AU24
PCI/GPIO/LPC
VCCIO[49] VCCPNAND[1] VCCVRM[3]
BE28
VCCIO[50] VCCPNAND[2]
AK16 VCCPNAND= 156mA(15mils)
BG26 AK20 J38 +3V_VCCPPCI R142 *SHORT0603 +3V
VCCIO[51] VCCPNAND[3] VCCPNAND R210 *SHORT0805 VCC3_3[8]
BG28 AK19 +1.8V BB51
VCCIO[52] VCCPNAND[4] +V1.1LAN_VCCA_A_DPL VCCADPLLA[1]
BH27
VCCIO[53] VCCPNAND[5]
AK15 68mA(15mils) BB53
VCCADPLLA[2] VCC3_3[9]
L38 VCC3_3 = 0.357A(30mils)
AK13 C319 C261 0.1u/10V_4_X7R
VCCPNAND[6]
AN30 AM12 M36
VCCIO[54] VCCPNAND[7] VCC3_3[10]
NAND / SPI
AN31 AM13 .1u/16V_4 69mA(15mils) +V1.1LAN_VCCA_B_DPL BD51
VCCIO[55] VCCPNAND[8] VCCADPLLB[1]
AM15 BD53 N36
VCCPNAND[9] VCCADPLLB[2] VCC3_3[11] C260 0.1u/10V_4_X7R
+3V R113 *SHORT0603 +3V_VCCA3GBG AN35 +1.05V AH23 P36
VCC3_3[1] VCCIO[21] VCC3_3[12]
AJ35
VCCIO[22]
37mA(15mils) VCCIO = 3.062A(150mils) AH35
VCCIO[23] VCC3_3[13]
U35
+V1.5S_1.8S R185 *SHORT0603 +VCCAFDI_VRM AT22
VCCVRM[1] C288 1U/6.3V_4
VCCME3_3= 85mA(15mils) AF34
VCCIO[2]
+1.05V L51 *1uH_6 +V1.1LAN_VCCAPLL_FDI BJ18 AM8 C286 1U/6.3V_4 AD13
VCCFDIPLL VCCME3_3[1] +3V_VCCME_SPI R201 *SHORT0603 C273 1U/6.3V_4 VCC3_3[14]
AM9 +3V AH34
VCCME3_3[2] VCCIO[3]
FDI
+1.05V_VCCDPLL_FDI AM23 AP11 31mA(15mils)

C645 VCCIO[1] VCCME3_3[3] C329
AP9 AF32
*10u/6.3V_6 VCCME3_3[4] VCCIO[4] +V1.1LAN_VCCAPLL L28 *10uh_8
AK3 +1.05V
.1u/16V_4 +VCCSST VCCSATAPLL[1]
V12 AK1
C325 0.1u/10V_4_X7R DCPSST VCCSATAPLL[2] C668 C351
IbexPeak-M_R1P0 *1u/6.3V_4 *10u/6.3V_6
+V1.1LAN_INT_VCCSUS Y22 VCCIO = 3.062A(150mils)

C306 0.1u/10V_4_X7R DCPSUS +V1.1LAN_VCC_SATA
AH22 +1.05V
R169 *SHORT0603 VCCIO[9]
B
+1.05V B
P18 AT20 +V1.5S_1.8S C320
VCCSUS3_3[29] VCCVRM[4] 1u/10V_4
VCCSUS3_3 = 163mA(20mils)
VCCVRM=196mA(15mils) HDA_SYNC (PCH strap pin) +3V_S5 R168 *SHORT0603
+3V_S5_VCCPSUS U19
SATA
VCCSUS3_3[30]
PCI/GPIO/LPC
AH19
R213 *SHORT0603 VCCIO[10]
+1.8V +V1.5S_1.8S Internal weak pull-down U20
VCCSUS3_3[31]
VCCVRM=>+1.8V (default) AD20
C314 0.1u/10V_4_X7R U22 VCCIO[11]
C344 C345
external pull-up VCCSUS3_3[32]
AF22
.1u/16V_4 .1u/16V_4 VCCVRM=>+1.5V VCCIO[12]
VRM enable by strap pin GPIO27 VCC3_3 = 0.357A(30mils) VCCIO[13]
AD19
+3V R186 *SHORT0603 +3V_VCCPCORE V15 AF20
which supply clean 1.05V for VCC3_3[5] VCCIO[14]
AF19
[VCCACLK,VCCAPLLEXP,VCCFDIPLL,VCCSATAPLL] VCCIO[15]
V16 AH20
VCC3_3[6] VCCIO[16]
C318 0.1u/10V_4_X7R Y16 AB19
VCC3_3[7] VCCIO[17]
AB20
L45 *10uh_8 +V1.1LAN_VCCA_A_DPL VCCIO[18]
+1.05V AB22
VCCIO[19]
V_CPU_IO >1mA(15mils) AD22
C592 + R198 0_6 +VTT_VCCPCPU VCCIO[20]
+1.05V AT18
V_CPU_IO[1]
VCCME = 1.849A(100mils)
*220u_3528 R424 AA34 +1.05V_VCCEPW
CPU
C342 4.7U/6.3V_6 VCCME[13]
*SHORT0805 Y34
C338 0.1u/10V_4_X7R VCCME[14]
AU18 Y35
L46 10uh_8 +V1.1LAN_VCCA_B_DPL C336 0.1u/10V_4_X7R V_CPU_IO[2] VCCME[15]
AA35
VCCME[16]
C601 + VCCRTC= 2mA(15mils)
RTC
+VCCRTC A12 L30 +V3.3A_1.5A_HDA_IO R163 *Short_4 +3V_S5
VCCRTC VCCSUSHDA
HDA
220u_3528
C664 0.1u/10V_4_X7R VCCSUSHDA= 6mA(15mils)
C665 0.1u/10V_4_X7R IbexPeak-M_R1P0 C276
1u/10V_4
A A

PROJECT : ZQH
1A
IBEX PEAK-M 5/6
5 4 3 2 1
5 4 3 2 1
U21I
AY7 H49
IBEX PEAK-M (GND) B11
B15
VSS[159]
VSS[160]
VSS[259]
VSS[260] H5
J24
VSS[161] VSS[261]
D B19 VSS[162] VSS[262] K11 D
B23 VSS[163] VSS[263] K43
B31 VSS[164] VSS[264] K47
B35 VSS[165] VSS[265] K7
B39 VSS[166] VSS[266] L14
B43 VSS[167] VSS[267] L18
B47 VSS[168] VSS[268] L2
B7 VSS[169] VSS[269] L22
BG12 VSS[170] VSS[270] L32
BB12 VSS[171] VSS[271] L36
U21H BB16 L40
VSS[172] VSS[272]
AB16 VSS[0] BB20 VSS[173] VSS[273] L52
BB24 VSS[174] VSS[274] M12
AA19 VSS[1] VSS[80] AK30 BB30 VSS[175] VSS[275] M16
AA22 VSS[3] VSS[82] AK32 BB38 VSS[177] VSS[277] N38
AM19 VSS[4] VSS[83] AK34 BB42 VSS[178] VSS[278] M34
AA28 VSS[7] VSS[86] AK43 BC10 VSS[181] VSS[281] M46
AB11 VSS[11] VSS[90] AK8 BC22 VSS[185] VSS[285] N24
AB15 VSS[12] VSS[91] AL2 BC32 VSS[186] VSS[286] P11
AB23 VSS[13] VSS[92] AL52 BC36 VSS[187] VSS[287] AD15
AB30 VSS[14] VSS[93] AM11 BC40 VSS[188] VSS[288] P22
AB31 VSS[15] VSS[94] BB44 BC44 VSS[189] VSS[289] P30
AB32 VSS[16] VSS[95] AD24 BC52 VSS[190] VSS[290] P32
AB39 VSS[17] VSS[96] AM20 BH9 VSS[191] VSS[291] P34
AB43 VSS[18] VSS[97] AM22 BD48 VSS[192] VSS[292] P42
C C
AB8 VSS[21] VSS[100] AM28 BE12 VSS[195] VSS[295] R2
AC2 VSS[22] VSS[101] BA42 BE16 VSS[196] VSS[296] R52
AC52 VSS[23] VSS[102] AM30 BE20 VSS[197] VSS[297] T12
AD11 VSS[24] VSS[103] AM31 BE24 VSS[198] VSS[298] T41
AD31 VSS[29] VSS[108] AM39 BE46 VSS[203] VSS[303] U30
AD32 VSS[30] VSS[109] AM42 BE48 VSS[204] VSS[304] U31
AD34 VSS[31] VSS[110] AU20 BE50 VSS[205] VSS[305] U32
AU22 VSS[32] VSS[111] AM46 BE6 VSS[206] VSS[306] U34
AD42 VSS[33] VSS[112] AV22 BE8 VSS[207] VSS[307] P38
AD46 VSS[34] VSS[113] AM49 BF3 VSS[208] VSS[308] V11
AD49 VSS[35] VSS[114] AM7 BF49 VSS[209] VSS[309] P16
AD7 VSS[36] VSS[115] AA50 BF51 VSS[210] VSS[310] V19
AE2 VSS[37] VSS[116] BB10 BG18 VSS[211] VSS[311] V20
AE4 VSS[38] VSS[117] AN32 BG24 VSS[212] VSS[312] V22
AF12 VSS[39] VSS[118] AN50 BG4 VSS[213] VSS[313] V30
Y13 VSS[40] VSS[119] AN52 BG50 VSS[214] VSS[314] V31
AH49 VSS[41] VSS[120] AP12 BH11 VSS[215] VSS[315] V32
AU4 VSS[42] VSS[121] AP42 BH15 VSS[216] VSS[316] V34
AF35 VSS[43] VSS[122] AP46 BH19 VSS[217] VSS[317] V35
AP13 VSS[44] VSS[123] AP49 BH23 VSS[218] VSS[318] V38
AN34 VSS[45] VSS[124] AP5 BH31 VSS[219] VSS[319] V43
AF45 VSS[46] VSS[125] AP8 BH35 VSS[220] VSS[320] V45
AF46 VSS[47] VSS[126] AR2 BH39 VSS[221] VSS[321] V46
AF49 VSS[48] VSS[127] AR52 BH43 VSS[222] VSS[322] V47
AF5 VSS[49] VSS[128] AT11 BH47 VSS[223] VSS[323] V49
AF8 VSS[50] VSS[129] BA12 BH7 VSS[224] VSS[324] V5
B AG2 AH48 C12 V7 B
VSS[51] VSS[130] VSS[225] VSS[325]
AG52 VSS[52] VSS[131] AT32 C50 VSS[226] VSS[326] V8
AH11 VSS[53] VSS[132] AT36 D51 VSS[227] VSS[327] W2
AH15 VSS[54] VSS[133] AT41 E12 VSS[228] VSS[328] W52
AH16 VSS[55] VSS[134] AT47 E16 VSS[229] VSS[329] Y11
AH24 VSS[56] VSS[135] AT7 E20 VSS[230] VSS[330] Y12
AH32 VSS[57] VSS[136] AV12 E24 VSS[231] VSS[331] Y15
AV18 VSS[58] VSS[137] AV16 E30 VSS[232] VSS[332] Y19
AJ19 VSS[62] VSS[141] AV34 E46 VSS[236] VSS[336] Y31
AJ23 VSS[66] VSS[145] AV49 F49 VSS[240] VSS[340] Y46
AJ26 VSS[67] VSS[146] AV5 F5 VSS[241] VSS[341] P49
AJ28 VSS[68] VSS[147] AV8 G10 VSS[242] VSS[342] Y5
AJ32 VSS[69] VSS[148] AW14 G14 VSS[243] VSS[343] Y6
AJ34 VSS[70] VSS[149] AW18 G18 VSS[244] VSS[344] Y8
AT5 VSS[71] VSS[150] AW2 G2 VSS[245] VSS[345] P24
AJ4 VSS[72] VSS[151] BF9 G22 VSS[246] VSS[346] T43
AK12 VSS[73] VSS[152] AW32 G32 VSS[247] VSS[347] AD51
AM41 VSS[74] VSS[153] AW36 G36 VSS[248] VSS[348] AT8
AN19 VSS[75] VSS[154] AW40 G40 VSS[249] VSS[349] AD47
AK26 VSS[76] VSS[155] AW52 G44 VSS[250] VSS[350] Y47
AK22 VSS[77] VSS[156] AY11 G52 VSS[251] VSS[351] AT12
AK23 VSS[78] VSS[157] AY43 AF39 VSS[252] VSS[352] AM6
AK28 VSS[79] VSS[158] AY47 H16 VSS[253] VSS[353] AT13
H20 VSS[254] VSS[354] AM5
IbexPeak-M_R1P0 H30 AK45
VSS[255] VSS[355]
A H34 VSS[256] VSS[356] AK39 A
H38 VSS[257] VSS[366] AV14
H42 VSS[258]
IbexPeak-M_R1P0
PROJECT : ZQH
1A
IBEX PEAK-M 6/6
5 4 3 2 1
5 4 3 2 1
+1.5VSUS
JDIM1B
JDIM1A M_A_DQ[63:0] <5>
<5> M_A_A[15:0] 75 VDD1 VSS16 44
M_A_A0 98 5 M_A_DQ4 76 48
M_A_A1 A0 DQ0 M_A_DQ0 VDD2 VSS17
97 A1 DQ1 7 81 VDD3 VSS18 49
M_A_A2 96 15 M_A_DQ2 82 54
95 A3 DQ3 17 87 VDD5 VSS20 55
M_A_A4 92 4 M_A_DQ1 88 60
91 A5 DQ5 6 93 VDD7 VSS22 61
M_A_A6 90 16 M_A_DQ6 94 65
M_A_A7 86
A6 DQ6
18 M_A_DQ7
2.48A 99
VDD8 VSS23
66
D 89 A8 DQ8 21 100 VDD10 VSS25 71 D
M_A_A9 85 23 M_A_DQ13 105 72
PC2100 DDR3 SDRAM SO-DIMM

107 A10/AP DQ10 33 106 VDD12 VSS27 127
M_A_A11 84 35 M_A_DQ10 111 128
83 A12/BC# DQ12 22 112 VDD14 VSS29 133
M_A_A13 119 24 M_A_DQ9 117 134
80 A14 DQ14 34 118 VDD16 VSS31 138
M_A_A15 78 36 M_A_DQ15 123 139
A15 DQ15 M_A_DQ17 VDD17 VSS32

DQ16 39 124 VDD18 VSS33 144
109 41 M_A_DQ20 145
<5> M_A_BS#0 BA0 DQ17 VSS34
108 51 M_A_DQ18 199 150
<5> M_A_BS#1 BA1 DQ18 +3V VDDSPD VSS35
79 53 M_A_DQ19 151
<5> M_A_BS#2 BA2 DQ19 VSS36
114 40 M_A_DQ16 77 155
<5> M_A_CS#0 S0# DQ20 NC1 VSS37
121 42 M_A_DQ21 122 156
<5> M_A_CS#1 S1# DQ21 NC2 VSS38
101 50 M_A_DQ22 125 161
<5> M_A_CLK0 CK0 DQ22 NCTEST VSS39
103 52 M_A_DQ23 162
<5> M_A_CLK0# CK0# DQ23 VSS40
102 57 M_A_DQ24 198 167
<5> M_A_CLK1 CK1 DQ24 <4> PM_EXTTS#0 EVENT# VSS41
104 59 M_A_DQ28 30 168
<5> M_A_CLK1# CK1# DQ25 <4,15> DDR3_DRAMRST# RESET# VSS42
M_A_DQ25
<5> M_A_CKE0 73
74
CKE0 DQ26 67
69 M_A_DQ26
M3 solution VSS43 172
173
<5> M_A_CKE1 CKE1 DQ27 VSS44
115 56 M_A_DQ27 R266 *M3@0_6 +SMDDR_VREF_DQ0 1 178
<5> M_A_CAS# CAS# DQ28 <7> VREF_DQ_DIMM0 VREF_DQ VSS45
110 58 M_A_DQ29 +SMDDR_VREF_DIMM 126 179
<5> M_A_RAS# RAS# DQ29 +SMDDR_VREF_DIMM VREF_CA VSS46
113 68 M_A_DQ31 184
<5> M_A_WE# WE# DQ30 VSS47
R270 10K_4 DIMM0_SA0 197 70 M_A_DQ30 185
R269 10K_4 DIMM0_SA1 SA0 DQ31 M_A_DQ36 VSS48
201 SA1 DQ32 129 2 VSS1 VSS49 189
CLK_SCLK 202 131 M_A_DQ33 3 190
<3,15,19> CLK_SCLK CLK_SDATA SCL DQ33 M_A_DQ35 VSS2 VSS50
200 141 8 195
(204P)
<3,15,19> CLK_SDATA SDA DQ34 M_A_DQ34 VSS3 VSS51
C DQ35 143 9 VSS4 VSS52 196 C
116 130 M_A_DQ32 13
<5> M_A_ODT0 ODT0 DQ36 VSS5
120 132 M_A_DQ37 14
<5> M_A_ODT1 ODT1 DQ37 VSS6
140 M_A_DQ38 19
<5> M_A_DM[7:0] DQ38 VSS7
M_A_DM0 11 142 M_A_DQ39 20
M_A_DM1 DM0 DQ39 M_A_DQ45 VSS8
28 DM1 DQ40 147 25 VSS9
M_A_DM2 46 149 M_A_DQ44 26 203 +0.75V_DDR_VTT
M_A_DM3 63
DM2
DM3
(204P) DQ41
DQ42 157 M_A_DQ47 31
VSS10
VSS11
VTT1
VTT2 204
M_A_DM4 136 159 M_A_DQ42 +1.5VSUS 32
M_A_DM5 DM4 DQ43 M_A_DQ41 VSS12
153 DM5 DQ44 146 37 VSS13 GND 205
M_A_DM6 170 148 M_A_DQ40 38 206
M_A_DM7 DM6 DQ45 M_A_DQ46 VSS14 GND
187 DM7 DQ46 158 43 VSS15
160 M_A_DQ43 R276
<5> M_A_DQS[7:0] DQ47
M_A_DQS0 12 163 M_A_DQ48 *10K_4
M_A_DQS1 DQS0 DQ48 M_A_DQ49
29 DQS1 DQ49 165 DDR3-DIMM1_H=8.0_Reverse
M_A_DQS2 47 175 M_A_DQ50
M_A_DQS3 DQS2 DQ50 M_A_DQ51 R275 *SHORT0603 +SMDDR_VREF_DIMM
64 DQS3 DQ51 177 +SMDDR_VREF
M_A_DQS4 137 164 M_A_DQ52
154 DQS5 DQ53 166
M_A_DQS6 171 174 M_A_DQ54 R264 C403
<5> M_A_DQS#[7:0] 188 DQS7 DQ55 176 *10K_4 470p/X7R_4
M_A_DQS#0 10 181 M_A_DQ56
M_A_DQS#1 DQS#0 DQ56 M_A_DQ57
27 DQS#1 DQ57 183
M_A_DQS#2 45 191 M_A_DQ62
62 DQS#3 DQ59 193
M_A_DQS#4 135 180 M_A_DQ60
152 DQS#5 DQ61 182
M_A_DQS#6 169 192 M_A_DQ63 +1.5VSUS
B DQS#6 DQ62 B
M_A_DQS#7 186 194 M_A_DQ58
DQS#7 DQ63
R259
DDR3-DIMM1_H=8.0_Reverse *10K/F_4
M1 solution
+SMDDR_VREF R268 *SHORT0603 +SMDDR_VREF_DQ0
Place these Caps near So-Dimm0.
R260 C380
*10K/F_4 470p/X7R_4
+1.5VSUS
+SMDDR_VREF_DIMM +SMDDR_VREF_DQ0
C366 C381 C369 C377 C387
10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 .1u/16V_4 .1u/16V_4
C365 + C367 C379 C378 C385 C383

*330u/2V_7343
10u/6.3V_6 .1u/16V_4 .1u/16V_4
C391 C372 C370 C371 C376 2.2u/6.3V_6 2.2u/6.3V_6

10u/6.3V_6 10u/6.3V_6 .1u/16V_4 .1u/16V_4 .1u/16V_4
A A
+3V +0.75V_DDR_VTT
C393 C375 C374 C389 C373 C396 C412

C397
2.2u/6.3V_6
C394
.1u/16V_4
1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4
4.7U/6.3V_6 4.7U/6.3V_6 4.7U/6.3V_6
PROJECT : ZQH
www.vinafix.vn
http://hobi-elektronika.net DDRIII SO-DIMM-0 1A

5 4 3 2 1
5 4 3 2 1
+1.5VSUS
JDIM2A M_B_DQ[63:0] <5> JDIM2B
<5> M_B_A[15:0]
M_B_A0 98 5 M_B_DQ5 75 44
M_B_A1 A0 DQ0 M_B_DQ1 VDD1 VSS16
97 A1 DQ1 7 76 VDD2 VSS17 48
M_B_A2 96 15 M_B_DQ2 81 49
95 A3 DQ3 17 82 VDD4 VSS19 54
M_B_A4 92 4 M_B_DQ0 87 55
91 A5 DQ5 6 88 VDD6 VSS21 60
M_B_A6 90 16 M_B_DQ6 93 61
86 A7 DQ7 18 94 VDD8 VSS23 65
M_B_A8 89 21 M_B_DQ8 99 66
D
M_B_A9 85
A8 DQ8
23 M_B_DQ9
2.48A 100
VDD9 VSS24
71
D

107 A10/AP DQ10 33 105 VDD11 VSS26 72
M_B_A11 M_B_DQ11

84 A11 DQ11 35 106 VDD12 VSS27 127
M_B_A12 83 22 M_B_DQ12 111 128
M_B_A13 A12/BC# DQ12 M_B_DQ13 VDD13 VSS28
119 A13 DQ13 24 112 VDD14 VSS29 133
M_B_A14 80 34 M_B_DQ14 117 134
78 A15 DQ15 36 118 VDD16 VSS31 138
M_B_DQ18

DQ16 39 123 VDD17 VSS32 139
109 41 M_B_DQ17 124 144
<5> M_B_BS#0 BA0 DQ17 VDD18 VSS33
108 51 M_B_DQ16 145
<5> M_B_BS#1 BA1 DQ18 VSS34
79 53 M_B_DQ19 199 150
<5> M_B_BS#2 BA2 DQ19 +3V VDDSPD VSS35
114 40 M_B_DQ20 151
<5> M_B_CS#0 S0# DQ20 VSS36
121 42 M_B_DQ21 77 155
<5> M_B_CS#1 S1# DQ21 NC1 VSS37
101 50 M_B_DQ22 122 156
<5> M_B_CLK0 CK0 DQ22 NC2 VSS38
103 52 M_B_DQ23 125 161
<5> M_B_CLK0# CK0# DQ23 NCTEST VSS39
102 57 M_B_DQ26 162
<5> M_B_CLK1 CK1 DQ24 VSS40
104 59 M_B_DQ25 198 167
<5> M_B_CLK1# CK1# DQ25 <4> PM_EXTTS#1 EVENT# VSS41
73 67 M_B_DQ30 30 168
<5> M_B_CKE0 CKE0 DQ26 <4,14> DDR3_DRAMRST# RESET# VSS42
M_B_DQ27
<5> M_B_CKE1 74
115
CKE1 DQ27 69
56 M_B_DQ29
M3 solution VSS43 172
173
<5> M_B_CAS# CAS# DQ28 VSS44
110 58 M_B_DQ24 R302 *M3@0_6 +SMDDR_VREF_DQ1 1 178
<5> M_B_RAS# RAS# DQ29 <7> VREF_DQ_DIMM1 VREF_DQ VSS45
113 68 M_B_DQ28 126 179
<5> M_B_WE# WE# DQ30 +SMDDR_VREF_DIMM VREF_CA VSS46
R295 10K_4 DIMM1_SA0 197 70 M_B_DQ31 184
R298 10K_4 DIMM1_SA1 SA0 DQ31 M_B_DQ32 VSS47
+3V 201 SA1 DQ32 129 VSS48 185
202 131 M_B_DQ33 2 189
<3,14,19> CLK_SCLK SCL DQ33 M_B_DQ34 VSS1 VSS49
200 SDA DQ34 141 3 VSS2 VSS50 190
<3,14,19> CLK_SDATA 143 M_B_DQ35 8 195
(204P)
C DQ35 VSS3 VSS51 C
116 130 M_B_DQ36 9 196
<5> M_B_ODT0 ODT0 DQ36 VSS4 VSS52
120 132 M_B_DQ37 13
<5> M_B_ODT1 ODT1 DQ37 VSS5
140 M_B_DQ38 14
<5> M_B_DM[7:0] DQ38 VSS6
M_B_DM0 11 142 M_B_DQ39 19
M_B_DM1 DM0 DQ39 M_B_DQ40 VSS7
28 DM1 DQ40 147 20 VSS8
M_B_DM2 46 149 M_B_DQ45 +1.5VSUS 25
M_B_DM3 63
DM2
DM3
(204P) DQ41
DQ42 157 M_B_DQ47 26
VSS9
VSS10 VTT1 203 +0.75V_DDR_VTT
M_B_DM4 136 159 M_B_DQ43 31 204
M_B_DM5 DM4 DQ43 M_B_DQ44 VSS11 VTT2
153 DM5 DQ44 146 32 VSS12
M_B_DM6 M_B_DQ41 R301
M_B_DM7
170
187
DM6 DQ45 148
158 M_B_DQ46
M1 solution *10K/F_4
37
38
VSS13 GND 205
206
DM7 DQ46 M_B_DQ42 VSS14 GND
<5> M_B_DQS[7:0] DQ47 160 43 VSS15
M_B_DQS0 12 163 M_B_DQ48
M_B_DQS1 DQS0 DQ48 M_B_DQ53 R299 *SHORT0603 +SMDDR_VREF_DQ1
29 DQS1 DQ49 165 +SMDDR_VREF
M_B_DQS2 47 175 M_B_DQ50 DDR3-DIMM1_H=4.0_Reverse
M_B_DQS3 DQS2 DQ50 M_B_DQ54
64 DQS3 DQ51 177
M_B_DQS4 137 164 M_B_DQ52 R304 C452
M_B_DQS5 DQS4 DQ52 M_B_DQ49 *10K/F_4
154 DQS5 DQ53 166 470p/X7R_4
M_B_DQS6 171 174 M_B_DQ51
M_B_DQS7 DQS6 DQ54 M_B_DQ55
<5> M_B_DQS#[7:0] 188 DQS7 DQ55 176
M_B_DQS#0 10 181 M_B_DQ60
M_B_DQS#1 DQS#0 DQ56 M_B_DQ57
27 DQS#1 DQ57 183
M_B_DQS#2 45 191 M_B_DQ63
62 DQS#3 DQ59 193
M_B_DQS#4 135 180 M_B_DQ59
152 DQS#5 DQ61 182
B M_B_DQS#6 169 192 M_B_DQ62 B
186 DQS#7 DQ63 194
DDR3-DIMM1_H=4.0_Reverse
+1.5VSUS Place these Caps near So-Dimm1.

+SMDDR_VREF_DIMM +SMDDR_VREF_DQ1
C438 C435 C437 C434 C405
10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 .1u/16V_4 .1u/16V_4
C439 + C450 C413 C416 C440 C444

330u/2V_7343
10u/6.3V_6 .1u/16V_4 .1u/16V_4
C436 C408 C407 C406 C433 2.2u/6.3V_6 2.2u/6.3V_6

10u/6.3V_6 10u/6.3V_6 .1u/16V_4 .1u/16V_4 .1u/16V_4
+3V +0.75V_DDR_VTT
A C425 C414 C424 C415 C411 C421 C402 A

C443 C427 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4
2.2u/6.3V_6 .1u/16V_4 4.7U/6.3V_6 4.7U/6.3V_6 4.7U/6.3V_6

PROJECT : ZQH
www.vinafix.vn
http://hobi-elektronika.net DDRIII SO-DIMM-1 1A

5 4 3 2 1
1 2 3 4 5 6 7 8
CRT Switch CRT

C272 0.1u/10V_4_X7R
0_ohm Resistor place close to Joint-Point F2
D16 SSM22LLPT CRTVDD5
16
+5V 2 1
CN8
INT_CRT_RED SMD1206P110TFT CRT-CONN
<8> INT_CRT_RED
INT_CRT_GRN 6
<8> INT_CRT_GRN
INT_CRT_BLU INT_CRT_RED L27 BLM18BA750SN1D/0.3A/75ohm_6 CRT_R1 1 11 CRT_11 T22
<8> INT_CRT_BLU
7
INT_CRT_GRN L26 BLM18BA750SN1D/0.3A/75ohm_6 CRT_G1 2 12 DDCDAT_1
INT_VSYNC 8
<8> INT_VSYNC
INT_HSYNC INT_CRT_BLU L25 BLM18BA750SN1D/0.3A/75ohm_6 CRT_B1 3 13 CRTHSYNC
<8> INT_HSYNC
9
4 14 CRTVSYNC
A A
INT_CRT_DDCDAT R189 R177 R165 C322 C308 C293 C637 C647 C653 10
<8> INT_CRT_DDCDAT
INT_CRT_DDCCLK 5 15 DDCCLK_1
<8> INT_CRT_DDCCLK
150/F_4 150/F_4 150/F_4 10p/50V_4 10p/50V_4 10p/50V_4 10p/50V_4 10p/50V_4 10p/50V_4
17
+3V
C301 U23
CRTVDD5 1 16 CRT_VSYNC2 R458 0_4 CRTVSYNC C661 .1u/10V_4 CRTVDD5
0.1u/10V_4_X7R VCC_SYNC SYNC_OUT2 CRT_HSYNC2 R457 0_4 CRTHSYNC
14
SYNC_OUT1 C620 10p/50V_4 CRTVSYNC
7
C632 .22u/25V_6 CRT_BYP VCC_DDC
8
BYP INT_VSYNC CRTVDD5 C619 10p/50V_4 CRTHSYNC
15
SYNC_IN2 INT_HSYNC +3V
+3V 2 13
VCC_VIDEO SYNC_IN1 C631 *10p/50V_4 DDCCLK_1
C315 R452 R476
CRT_R1 3 10 INT_CRT_DDCCLK R462 2.7K_4 C646 *10p/50V_4 DDCDAT_1
0.1u/10V_4_X7R CRT_G1 VIDEO_1 DDC_IN1 INT_CRT_DDCDAT R469 2.7K_4 2.7K_4 2.7K_4
4 11
CRT_B1 VIDEO_2 DDC_IN2
5
VIDEO_3 DDCCLK_1
9
DDC_OUT1 DDCDAT_1
6 12
GND DDC_OUT2
CM2009-02QR
B B
LCD Power
+3V VIN
LVDS +3V
C8 C7
C2 C3
0.1u/10V_4_X7R C1 U1
1000p/50V_4 4.7u/25V_8 1000p/50V_4
1U/6.3V_4 6 1 LCDVCC
IN OUT
4 2
IN GND C6 C5 C9 C10 C4
CN5 INT_LVDS_DIGON 3 5
ON/OFF GND *.1u/10V_4 *2.2u/10V_8 0.1u/10V_4_X7R.01u/25V_4 22u/6.3V_8
G_5
+3V R10 2.2K_4 INT_LVDS_EDIDDATA AAT4280-4
R9 2.2K_4 INT_LVDS_EDIDCLK 40
LVDS_BRIGHT R6 39
BL_ON BLM15AG121SS1/0.5A/120ohm_4 38 R4
37
INT_TXLCLKOUT+ 36
INT_TXLCLKOUT- 35 100K_4
34
0_ohm Resistor place close to Joint-Point INT_TXLOUT0+ 33
INT_TXLOUT0- 32
31 G_4
INT_TXLOUT1+ 30
INT_TXLOUT1- 29
28
CCD-USB CCD +3V-current budget 0.2A 27
INT_TXLOUT2+
INT_TXLOUT2- 26
25
24
C
INT_LVDS_EDIDCLK
C12 C13 23
22
Backlight Control C
*1u/6.3V_4 *1u/6.3V_4
<8> INT_LVDS_EDIDCLK 21
INT_LVDS_EDIDDATA
<8> INT_LVDS_EDIDDATA 20
INT_LVDS_DIGON 19
<8> INT_LVDS_DIGON +3V 18
INT_LVDS_BLON R5 *SHORT0603 +3VPCU
<8> INT_LVDS_BLON 17
16
CCD_PWR 15
C14 14
C11 R375
*1u/6.3V_4 *1u/6.3V_4 13 *100K_4
USBP8-_R 12
11 LID591# <27>
USBP8+_R
10 G_1
9
+3V
8
7
LID591#,EC intrnal PU
LCDVCC R11 *SHORT0603 +3V
6
5
1
INT_TXLCLKOUT+ 1/10 delete R8 0.8A
<8> INT_TXLCLKOUT+ 4
INT_TXLCLKOUT- D14
<8> INT_TXLCLKOUT- 3
INT_TXLOUT0+ VIN R14 *SHORT0805 INVCC0 BAS316
<8> INT_TXLOUT0+ 2
INT_TXLOUT0-
<8> INT_TXLOUT0- 1
G_0
INT_TXLOUT1+ R16 *SHORT0805 R376
<8> INT_TXLOUT1+
2
INT_TXLOUT1-
<8> INT_TXLOUT1-
INT_TXLOUT2+ R377 10K_4
<8> INT_TXLOUT2+
INT_TXLOUT2- BL_ON
<8> INT_TXLOUT2-
LVDS_CONN 10K_4
3
R7 *0_4 LVDS_BRIGHT
<27> CONTRAST
BL# 2
R2 *0_4 2 EC_FPBACK# <27>
3
R13 0_4 Q10
<8> INT_LVDS_BRIGHT
L1 2N7002K Q9
2 1 USBP8+_R DTC144EUA
<10> USBP8+
1
+3VPCU 2 1 USBP8-_R INT_LVDS_BLON
<10> USBP8- 3 4 2
3 4
RFCMF1632100M3T/200mA/90ohm Q11
D R3 *0_4 R378 2N7002K D
1
C491 0.1u/10V_4_X7R 100K_4
1
2 LID591#
HE1
2
PT3661-BB
3
PT3661-BB : AL003661003 D13

EM-6781-T3 : AL006781000 *VPORT_6
PROJECT : ZQH
www.vinafix.vn
1
1A
Lid Switch (Hall sensor) CRT/LVDS/CAMERA/LID
1 2 3 4 5 6 7 8
5 4 3 2 1
HDMI-detect
+3V
HDMI LEVEL SHIFTER
R282 *0_4
<9> HDMI_HPD_PCH#
R278
+3V 10K_4
HDMI_MB_HP
HDMI_DDCDATA_MB HDMI_HPD_EC#
<27> HDMI_HPD_EC#
HDMI_DDCCLK_MB
C346 C667 C349 C350 C666 +3V R219 *4.7K_4 HDMI_HPD_EC# +5V
2.2u/6.3V_6 .1u/10V_4 .1u/10V_4 .1u/10V_4 .1u/10V_4 DDCBUF_EN

CFG
D D
+3V +3V R283
3
Active Buffer *10K_4
close to pin2/11/15/21/26/33/40/46
+3V
HDMI_MB_HP
36
35
34
33
32
31
30
29
28
27
26
25
U6 2
CCT2
CCT1
OE#
HPD_SINK
SDA_SINK
SCL_SINK
GND
VCC
GND
GND
DDC_EN
VCC
C341 C321 Q20
2N7002D
from PCH
1
.1u/10V_4 *.1u/10V_4 37 24
GND GND MB_HDMITX0N
<8> INT_HDMITX0N 38 23
IN_D1- OUT_D1- MB_HDMITX0P
<8> INT_HDMITX0P 39 22
IN_D1+ OUT_D1+
+3V 40 21 +3V
VCC VCC MB_HDMITX2P
1/7 swap IN_D2- OUT_D2- MB_HDMITX2N 1/7 swap
42 19
<8> INT_HDMITX2N
43
IN_D2+
GND
OUT_D2+
GND
18
MB_HDMITX1P
I2C
IN_D3- OUT_D3- MB_HDMITX1N
<8> INT_HDMITX1N 45 16
IN_D3+ OUT_D3+
+3V 46 15 +3V
VCC VCC MB_HDMICLK+
<8> INT_HDMICLK+ 47 14
IN_D4- OUT_D4- MB_HDMICLK-
<8> INT_HDMICLK- 48 13
IN_D4+ OUT_D4+ D19 2 1RB501V-40
HPDEN
49
HPD_S
SDA_S
SCL_S
GND +5V
REXT
TRIM
GND
GND
GND
VCC
VCC
NC
1
2
3
4
5
6
7
8
9
10
11
12
PS8101 R528
+3V 1.5K_4
R547 4.7K_4 PC0

R548 *4.7K_4 +3V +3V
LS_REXT
PC0 HDMI_DDCCLK_MB
R549 *4.7K_4 PC1 PC1
C C
R510 *4.7K_4 DDCBUF_EN from PCH
R217 *4.7K_4 R188 499/F_4
R509 *4.7K_4 CFG Control by pin4 HPDEN_R

R218 *4.7K_4 +5V D18 2 1RB501V-40
<8> INT_HDMI_HPD
R527
<8> SDVO_CTRLDAT
1.5K_4
<8> SDVO_CTRLCLK
Equalization Control
PC0 internal PD HDMI_DDCDATA_MB
PC1 PC0 PC1 internal PD
PIN4 PIN3 EQ Control DDCBUF_EN internal PD R486 2.2K_4
L L 8dB CFG internal PD +3V R485 2.2K_4
L H 4dB DDC_EN internal PU
H L 12dB
H H 0dB
B B
EMI
HDMI connector
MB_HDMITX2P CN11
20
R502 *100/F_4 MB_HDMITX2P SHELL1
1
D2+
2
MB_HDMITX2N MB_HDMITX2N D2 Shield
3
MB_HDMITX1P D2-
4
MB_HDMITX1P D1+
5
MB_HDMITX1N D1 Shield
6
R496 *100/F_4 MB_HDMITX0P D1-
7
D0+
8
MB_HDMITX1N MB_HDMITX0N D0 Shield
9 23
MB_HDMICLK+ D0- GND
10
MB_HDMITX0P CK+
11 22
MB_HDMICLK- CK Shield GND
12
R507 *100/F_4 +5V CK-
13
CE Remote
14
MB_HDMITX0N F1 HDMI_DDCCLK_MB NC
15
SMD1206P110TFT D20 HDMI_DDCDATA_MB DDC CLK
16
MB_HDMICLK+ N126408677 SSM22LLPT DDC DATA
2 1 17
N56126873 GND
18
R490 *100/F_4 +5V
19
C721 HDMI_MB_HP R271 *Short_4 N137984458 HP DET
21
MB_HDMICLK- SHELL2
470p/X7R_4
HDMI
R546
100K_4
A A

PROJECT : ZQH
1A
HDMI (PS8101)
5 4 3 2 1
5 4 3 2 1
LAN (LAN)
<BOM note> * Why does Pin17 CLKREQn connect to Pin16(LED2) and Pin30(DVDDL)?
If center tap power come from internal switch
regulator 76.1mA ; 30mil <Layout note> PU in CLK Gen.
=>Stuff 52SWR@ (Default) +3V_S5 +3V_LAN
Close to Pin2 Power Sequence: TP35
U8
If center tap power come from internal LDO VDD33 to PERSTn >= 100ms
=>Stuff 52LDO@ R36 2.2_6
40mil *
1
LX 1 17 R236 0/J_4
1/10 change to 2.2 ohm LX CLKREQn CLK_PCIE_LAN_REQ# <10>
C69 C45 C37
D <Layout note> 10U/10V_8 1U/10V_4 0.1U/16V_4 D
2 18
2
TP36 VDD33 SMCLK TP39
Close to Pin1
3 19 SMBUS for debug only
<4,10,19,23,27> PLTRST# PERSTn SMDATA TP38
L3 4.7uH/1A
DCR:0.15ohm
LX * Int. PU in SB <8,19> PCIE_WAKE#
TP37 4
WAKEn TESTMODE
20
C47 C43
VDDCT_REG 20mil 5
VDDCT_REG
AR8158
4X4mm NC
21
0.1U/16V_4 10U/10V_8 C39 VDDCT 6 32Pin QFN 22 PCIE_RXN0_LAN C20 .1U/10V_4

VDDCT TX_N PCIE_RX1- <10>
0.1U/16V_4 20mil
AVDDL 7 23 PCIE_RXP0_LAN C22 .1U/10V_4
AVDDL_REG TX_P PCIE_RX1+ <10>
C40
1
0.1U/16V_4 XTLO_LAN 8 24 AVDDL
VDDCT C41 C42 XTLO AVDDL
1U/10V_4 0.1U/16V_4 XTLI_LAN 9 25
2
XTLI REFCLK_N CLK_PCIE_LOM# <10> C29
20mil
C44 33P/50V_4 XTLO_LAN AVDDH 10 26 0.1U/16V_4
AVDDH_REG REFCLK_P CLK_PCIE_LOM <10>
1
XTLI_LAN R29 2.37K/F_4 RBIAS 11 27
C33 C34 RBIAS AVDDL
1
1U/10V_4 0.1U/16V_4 TX0P 12 28
2
Y2 TRXP0 RX_P PCIE_TX1+ <10> C28
25MHz-LAN TX0N 13 29 0.1U/16V_4
TRXN0 RX_N PCIE_TX1- <10>
2
TX1P 14 30 DVDDL 20mil

TRXP1 DVDDL_REG
1
C49 33P/50V_4 TX1N 15 31 LAN_ACTLED
TRXN1 LED[0] C30 C27 C17
16 32 LAN_LINKLED# *0.1U/16V_4 1U/10V_4 0.1U/16V_4
2
TX0P C48 6.8PF/50V_4 TP16 LED[2] LED[1]
GND10
GND9
GND8
GND7
GND6
GND5
GND4
GND3
GND2
GND1 33
TX0N C46 6.8PF/50V_4 <Layout note>
C C
TX1P
Close to LAN Chip 1/7 swap the pin define for layout
C51 6.8PF/50V_4
42
41
40
39
38
37
36
35
34
1nF reserved for EMI AR8158-BL1A-RL
TX1N C52 6.8PF/50V_4
4
2
4
2
RN2 RN1
49.9/F_4P2R 49.9/F_4P2R
3
1
3
1
1/7 change solution for surge
C32 C35 C16 C38

0.1U/16V_4 *1000P/50V_4 0.1U/16V_4 *1000P/50V_4
U4 U2
X-TX1N 1 8 TX1N 1 8
X-TX1P 1 8 TX1P 1 8
2 7 2 7
X-TX0N 2 7 TX0N 2 7
3 6 3 6
X-TX0P 3 6 TX0P 3 6
4 5 4 5
4 5 4 5
*UCLAMP2512T.TCT *UCLAMP2512T.TCT
+3V_S5 2 VDD33 AVDDL_REG 7 +1.1V regulator output (For all the analog 1.1V supply pins)
AVDDL
ATHEROS AVDDH_REG
+1.1V analog power 24/27 10 +2.7V regulator output
AR8158 DVDDL_REG 30 +1.1V regulator output (For all the digital 1.1V supply pins)
VDDCT_REG 5 +1.8V regulator output (For VDDCT when LDO mode)
+1.7V analog power 6 VDDCT LX 1 +1.7V Switching regulator (For VDDCT when switching mode)
B B
TRANSFORMER (LAN) RJ45 Connector (LAN)

CN9
9
R25 5.1K/J_8 LAN_ACTLED R12 N27354430 YELLOW_N
10
*510/J_6 YELLOW_P R265
U26 14 *0_6
C19 *0.1U/50V_8 LAN_ACTLED X-TX0P GND2 *0_6
1 13
X-TX0N 0+ GND1 R235
2
TX1N X-TX1N X-TX1P 0-
8 9 Active LED Pin: 3
C24 0.1U/16V_4 TX1P TD- TX- X-TX1P TERM9 1+
7 10 Non-overclocking=>active high 4
VDDCT L2 0_6 AVDD_CEN TD+ TX+ TERM0 2+
6 11 5
CT CT X-TX1N 2-
CX8EG601000: 0.5A/600ohm_6 C26 *1000P/50V_4 5 12 6
C23 0.1U/16V_4 NC NC TERM9 1-
4 13 7
C31 NC NC TERM1 3+
3 14 8
C25 *1000P/50V_4 TX0N CT CT X-TX0N R30 *5.1K/J_8 3-
2 15
*1U/6.3V_4 TX0P RD- RX- X-TX0P
1 16
RD+ RX+ LAN_LINKLED# R20 *510/J_6 11
LAN_LINKLED# GREEN_N
1nF reserved for EMI C54 *0.1U/50V_8 12
NS0014 LF_Bothhand R15 *0_8 GREEN_P
+3V_S5
R18 R19 LINK LED Pin: RJ45
SWR mode=>active low
75/F_8 75/F_8 LDO mode=>active high
A A
TERM9
2
R21 C18
*1M_8 220P/3KV_1808
1/7 change to 10/100 type D2
*B88069X9231T203 1/11 change to 220p by EMI's request Quanta Computer Inc.
1
PROJECT : ZQH
www.vinafix.vn
1A
LAN AR8158L
5 4 3 2 1
1 2 3 4 5 6 7 8
MINI-CARD WLAN(MPC)
Debug Check LED signal. (active high or low) +3V +WL_VDD
+3.3V: 1000mA R556 0_4 CL_DATA1_WLAN
+3.3Vaux:330mA <10> PCI_RST#
<10> CLK_LPC_DEBUG
R306 0_4 CL_CLK1_WLAN H=7.0mm R303 *SHORT0805 +WL_VDD
CN13 LTS_AAA-PCI-046-K01
+1.5V:500mA
51 52 +WL_VDD
R561 *0_4 CL_RST1#_WLAN Reserved +3.3V C457 C458 C697 C432
<10> CL_RST1# 49 50
R555 *0_4 CL_DATA1_WLAN Reserved GND 10u/6.3V_8 0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4
<10> CL_DATA1 47 48 +1.5V
R307 *0_4 CL_CLK1_WLAN Reserved +1.5V
<10> CL_CLK1 45 46
Reserved LED_WPAN#
43 44
Reserved LED_WLAN#
+WL_VDD 41 42
Reserved LED_WWAN#
39 40
Reserved GND
A 37 38 USBP13+ <10> A
Reserved USB_D+
35 36 USBP13- <10>
GND USB_D-
<10> PCIE_TX6+ 33 34
PETp0 GND
<10> PCIE_TX6- 31 32
PETn0 SMB_DATA CLK_SDATA <3,14,15>
29 30
GND SMB_CLK CLK_SCLK <3,14,15>
27 28 +1.5V
GND +1.5V +1.5V
<10> PCIE_RX6+ 25 26
PERp0 GND
<10> PCIE_RX6- 23 24 +WL_VDD
PERn0 +3.3Vaux PLTRST#
21 22 PLTRST# <4,10,18,23,27>
GND PERST#
19 20 RF_EN <27>
UIM_C4 W_DISABLE#
17 18
UIM_C8 GND
A_LFRAME#_R R293 0_4
Debug
15 GND UIM_VPP 16 LPC_LFRAME# <9,27>
R574 0_4 CLK_PCH_WIFI 13 14 A_LAD3_R R288 0_4 C695 C684 C688
<10> CLK_PCH_SRC2 REFCLK+ UIM_RST LPC_LAD3 <9,27>
R314 0_4 CLK_PCH_WIFI# 11 12 A_LAD2_R R285 0_4 1000p/50V_4 0.1u/10V_4 10u/6.3V_8
<10> CLK_PCH_SRC2# REFCLK- UIM_CLK LPC_LAD2 <9,27>
9 10 A_LAD1_R R281 0_4
GND UIM_DATA LPC_LAD1 <9,27>
7 8 A_LAD0_R R280 0_4
<10> PCIE_CLK_REQ2# CLKREQ# UIM_PWR LPC_LAD0 <9,27>
5 Reserved +1.5V 6 +1.5V
3 4
GND
GND
PCIE_WAKE#_R Reserved GND
1 WAKE# +3.3V 2 +WL_VDD
+WL_VDD
53
54
2
Q6 modify 10/19
*DTC144EUA
3 1 PCIE_WAKE#_R
<8,18> PCIE_WAKE#
B B
C C
D D

PROJECT : ZQH
1A
MINI PCI-E card/TV
www.vinafix.vn
1 2 3 4 5 6 7 8
1 2 3 4
MAIN SATA HDD EE RETURN-PATH CAPACITORS

VIN 1/10 add for plane
+5V
+3V
C471 0.1u/25V_4_X5R VIN
CN12
C711 *.1u/10V_4
23 C507 .1u/10V_4 C495
GND23 C470 0.1u/25V_4_X5R 2200p/50V_4
1 C670 *.1u/10V_4
GND1 SATA_TXP0_C C461 .01u/25V_4
A RXP 2 SATA_TXP0 <9> A
3 SATA_TXN0_C C459 .01u/25V_4 SATA_TXN0 <9> C361 *.1u/10V_4 C474 0.1u/25V_4_X5R
RXN C718 .1u/10V_4
GND2 4
5 SATA_RXN0 C456 .01u/25V_4 1/11 add by EMI's request
TXN SATA_RXN0_C <9>
6 SATA_RXP0 C453 .01u/25V_4 C323 0.1u/25V_4_X5R
TXP SATA_RXP0_C <9> +VGFX_AXG
7 C483 *.1u/10V_4 C719 .1u/10V_4
GND3
C672 0.1u/25V_4_X5R
8 C497 C720 .1u/10V_4
3.3V +3V 220p/50V_4
3.3V 9
10 C333 0.1u/25V_4_X5R
3.3V C722 470p/X7R_4
GND 11
12 C506 .1u/10V_4
GND C673 0.1u/25V_4_X5R
GND 13
14 +5V_HDD
5V
5V 15
16 C359 *.1u/10V_4 C460 0.1u/25V_4_X5R
5V +5V_S5
GND 17
RSVD 18
19 C430 0.1u/25V_4_X5R
GND C462 *.1u/10V_4 C704 *.1u/10V_4
12V 20
21 +1.05V
B 12V C426 0.1u/25V_4_X5R C479 .1u/10V_4 B
12V 22
R550 *SHORT0805 +5V_HDD C489 *.1u/10V_4 C553 .1u/10V_4
+5V
GND24 24
C676 C386 C400 C398 C395 C392 C224 0.1u/25V_4_X5R
MAIN_SATA + C723 470p/X7R_4 C496 2200p/50V_4
*100u/6.3V_3528 10u/6.3V_6 *.1u/16V_4 *.1u/16V_4 .01u/25V_4 .01u/25V_4
C669 0.1u/25V_4_X5R 1/11 add by EMI's request +VCC_CORE
C490 2200p/50V_4 C498 220p/50V_4
C480 0.1u/25V_4_X5R
C493 2200p/50V_4 C499 220p/50V_4 C508 *.1u/10V_4
6$7$+''
C494 2200p/50V_4 C337 0.1u/25V_4_X5R C500 220p/50V_4
1/11 add by EMI's request

C674 0.1u/25V_4_X5R
CN20 1/11 add for plane
26 24
25 23 ODD (SATA)
22
C 21 CN7 C
20 GND14 14
19 SATA_TXP0_C
18 SATA_TXN0_C 1
GND SATA_TXP1_C C317 .01u/25V_4
17 A+ 2 SATA_TXP1 <9>
16 SATA_RXN0 3 SATA_TXN1_C C310 .01u/25V_4 SATA_TXN1 <9>
SATA_RXP0 A-
15 GND 4
14 5 SATA_RXN1 C304 .01u/25V_4
B- SATA_RXN1_C <9>
13 6 SATA_RXP1 C296 .01u/25V_4
B+ SATA_RXP1_C <9>
12 7
11 0.94A(80mils) +5V
GND
10 +5V
9 8 SATA_DP R159 *1K_4
C401 C399 DP +5V_ODD R443 *SHORT0805
8 5V 9
7 5V 10
*.1u/16V_4 *10u/6.3V_6 C263 C262 C254 C264 C252 C611
+
6 MD 11
5 GND 12
4 13 .01u/25V_4 .01u/25V_4 *.1u/16V_4 *.1u/16V_4 10u/6.3V_6 *100u/6.3V_3528
GND
3
2 GND15 15
1
D SATA_ODD_H=7.7 D
*SATA_CONN
PROJECT : ZQH
1A
SATA-HDD/ODD/USB-ESATA
1 2 3 4
5 4 3 2 1
Mute(ADO) +3V +5VA
HP <22> HP-L
R585 *0_4
reverse R441 R615 R599
<22> HP-R ADOGND
*10K_4 10K_4
R551 0_4 MIC1-VREFO-L
MIC1-VREFO-L <22>
PD# *BAS316 D22 EAPD#
MIC1-VREFO-R
MIC1-VREFO-R <22>
D D
ADOGND MIC2-VREFO BAS316 D23
AMP_MUTE# <27>
R584 *0_4 MIC1-VREFO-L
BAS316 D24 PCH_AZ_CODEC_RST#
Codec(ADO) C478
C760 10u/6.3V_6 ADOGND
+ Place next to pin 27

2.2u/6.3V_6
1/7 by FAE's recommend
C476 C473
C477 ADOGND +5VA
+5VA + 2.2u/6.3V_6 0.1u/10V_4
Place next to pin 25
2.2u/6.3V_6
C468 C466 C472 C475

10u/6.3V_6 0.1u/10V_4
36
35
34
33
32
31
30
29
28
27
26
25
U10
0.1u/10V_4 10u/6.3V_6
CBP
CPVEE
HP-OUT-L
MIC1-VREFO-L
MIC2-VREFO
LDO-CAP
AVSS1
AVDD1
CBN
HP-OUT-R
MIC1-VREFO-R
VREF
ADOGND ADOGND
ANALOG +5V_S5
Place next to pin 38
37 24 ADOGND
AVSS2 LINE1-R T29
Spilt by AGND 38 23 T28 U29
AVDD2 LINE1-L
5
<27> AMP_MUTE# 1
+5V R581 *SHORT0603 +5VPVDD1 39 22 MIC1-R 4 R323
PVDD1 MIC1-R MIC1-R <22> HP_MUTE# <22>
EAPD# 2 0_4
<22> L_SPK+ L_SPK+ 40 21 MIC1-L
MIC1-L <22>
MIC TC7SH08FU C485
3
C784 C780 C783 C779 SPK-L+ MIC1-L
<22> L_SPK- L_SPK- 41 20 *4.7u/10V_6
C
10u/6.3V_6 0.1u/10V_4 10u/6.3V_6 0.1u/10V_4 SPK-L- MONO-OUT C
R582 20K/F_4
42
PVSS1 (Vista Premium Version) JDREF
19 ADOGND
43 18
PVSS2 Sense-B
<22> R_SPK- R_SPK- 44 17 MIC2_INT_R C469 1u/10V_6 R308 1K_4 MIC2_INTL1
SPK-R- MIC2-R
<22> R_SPK+ R_SPK+ 45 16 MIC2_INT_L C463 1u/10V_6 R309 1K_4
SPK-R+ MIC2-L
+5V R587 *SHORT0603 +5VPVDD2 46 15

PVDD2 LINE2-R
GPIO0/DMIC-DATA
EAPD# 47
GPIO1/DMIC-CLK
14
C792 C793 C790 C789 SPDIFO2/EAPD LINE2-L
48 13 SENSEA R305 20K/F_4 MIC1_JD
SDATA-OUT
SPDIFO Sense A MIC1_JD <22>
10u/6.3V_6 0.1u/10V_4 10u/6.3V_6 0.1u/10V_4
SDATA-IN
DVDD-IO
PCBEEP
RESET#
BIT-CLK
49
DVDD1
DVSS2
PGND
SYNC
ANALOG R313 39.2K/F_4
PD#
HPOUT_JD <22>
Place next to pin 46 Spilt by DGND ALC271X-VB3-GR

1
10
11
12
PCBEEP dont coupling any signals if possible
DIGITAL 8/17 separate PCBEEP to Digital from Realtek suggestion
1.6Vrms
+3V
PCBEEP C451 1u/10V_6 BEEP_1 R297 47K/F_4 D10 BAS316
SPKR <9>
C428 R296
C447 C448 4.7K_4 D11 BAS316
PCBEEP_EC <27>
0.1u/10V_4 10u/6.3V_6 100p/50V_4
2/17 change
B B
Place next to pin 1
R588 *SHORT0603 +3V
C431 C441
PCH_AZ_CODEC_RST# <9>
0.1u/10V_4 10u/6.3V_6
C429
PCH_AZ_CODEC_SYNC <9>
ACZ_SDIN0_R R586 22_4 *100p/50V_4
PCH_AZ_CODEC_SDIN0 <9>
PCH_AZ_CODEC_SDOUT <9>
Place next to pin 9
PD#
PCH_AZ_CODEC_BITCLK <9>
0V : Power down Class D SPK amplifer
3.3V : Power up Class D SPK amplifer C445 *22p/50V_4
Power (ADO) INT MIC array

DIGITAL ANALOG
+5V L58 UPB201209T-310Y-N/6A/31ohm_8 CN4 R337
+5VA R553 0_4 1 MIC2_INTL1 MIC2-VREFO
U30 1
2
2 C492 2.2K_4
3 4
IN OUT R564 0_4
2 R563 0_4 INT_MIC *22P_4 1/7 by FAE's recommend
GND R571 0_4
A A
1 5 R569 *29.4K/F_4 R311 *0_4
SHDN SET C464 *1000p/50V_4
*G923-330T1UF C689 *1000p/50V_4
R566 + C709 C710 ADOGND
*10K/F_4
*10u/10V_3216 *0.1u/10V_4
C707 C708 ADOGND C467 .1U_4
+ R331 *0_4
Tied at one point only under Quanta Computer Inc.
*0.1u/10V_4 *10u/10V_3216
the codec or near the codec
ADOGND ADOGND PROJECT : ZQH
ADOGND cap place close to MIC-connector 1A
C730, C787 close U37 pin3 and L65
REALTEK ALC663&888/MDC
5 4 3 2 1
5 4 3 2 1
MIC <21> MIC1-VREFO-R
<21> MIC1-VREFO-L
Internal Speaker
Normal OPEN Jack
R325 R324
4.7K/F_4 4.7K/F_4
CN18 BLACK
1 7 1/7 swap CN16
D C482 4.7u/6.3V_6 MIC1_L2 R318 1K/F_4 MIC1_L3 L35 MIC1_L L_SPK+ R572 0_6 L_SPK+_1 D
<21> MIC1-L 2 <21> L_SPK+ 1
BLM15AG121SS1/0.5A/120ohm_4 6 <21> L_SPK- L_SPK- R570 0_6 L_SPK-_1
C481 4.7u/6.3V_6 MIC1_R2 R317 1K/F_4 MIC1_R3 L34 MIC1_R R_SPK- R215 0_6 R_SPK-_1 25
<21> MIC1-R 3 <21> R_SPK- 36
BLM15AG121SS1/0.5A/120ohm_4 MIC1_JD 4 <21> R_SPK+ R_SPK+ R216 0_6 R_SPK+_1
4
<21> MIC1_JD 8
5
MIC C384 C388 C382 C390 SPEAKER-CONN
C486 C484
Max. 100mVrms input for Mic-IN 470p/50V_4 470p/50V_4
*0.22u/25V_6 *0.22u/25V_6 *0.22u/25V_6 *0.22u/25V_6
MIC1_JD ADOGND
1
ADOGND
D21
*VPORT_6
ADOGND
C C
HP/SPDIF
<21> HP_MUTE#
BLACK
1 CN17 7
2
HP-L-2 R328 56/F_4 HPL-1 L37 BLM15AG121SS1/0.5A/120ohm_4 HPL_SYS 2

HP-R-2 R327 56/F_4 HPR-1 L36 BLM15AG121SS1/0.5A/120ohm_4 HPR_SYS 6
<21> HP-L 3 1 HP-L-2 3
4
Q23 R326 R329 C487 C488 <21> HPOUT_JD 8
FDV301N 5
*1K_4 *1K_4 2200p/50V_4 2200p/50V_4 JA6331-0230T3B-8H
R322 *0_6
ADOGND
ADOGND
HP_MUTE#
B B
2
<21> HP-R 3 1 HP-R-2
Q24
FDV301N
R321 *0_6
HPOUT_JD
1
D12
A *VPORT_6 A
2
ADOGND Quanta Computer Inc.
PROJECT : ZQH
1A
AMP /AUDIO JACK CONN
5 4 3 2 1
A B C D E
CARD READER Controller 2 IN 1 CARD READER (SD/MMC) SD_WP
Main DFHS11FR011 SD_CD#
AU6435-GDL
11
12
Second DFHS11FR033
4
CN3
SW COM
CD/SW
WP/SW
SD_DAT1 10
SD_DAT0 DATA1
9 DATA0
8 VSS2
4 SD_CLK 4
7 CLK
VCC_XD 6 VDD
5 VSS1
SD_CMD 3 CMD
GND1
SD_DAT3 2
GND
SD_DAT2 DATA3
1 DATA2
SD-CARD
13
14
PIN45=Clock input selection
VCC_XD
'1' for 48MHz input [Default,Internal PU]
'0' for 12MHz input C442 C454
R554 *Short_4 XTALSEL 4.7u/10V_6 0.1u/16V_4
PIN43=Power saving mode enable.

C743 close PIN46, 47 '1' for enable [Default]
+1.8V_VDD '0' for disable Close to CN14 pin 14 & pin23
C708 close PIN48, 47 4.7u CAP close to pin23
+3V T95
C692 C694
3
0.1u/16V_4 0.1u/16V_4 3
XTALSEL
DATA1
DATA0
CTRL1
CTRL3
CTRL0, CRTL 1 trace length shorter ,
NBMD
HID
and surround with GND.
The trace length difference for each card interfaces should be

R559 *100K_4 smaller than 500 mil
48
47
46
45
44
43
42
41
40
39
38
37
+3V U28
R580 0_4
<4,10,18,19,27> PLTRST#
GND
VDD
HID
NBMD
VDDHM
C1_VSSHM
XTALSEL
CTRL1
CTRL3
DATA1
DATA0
DATA7
C700 *0.47u/10V_6 DATA0 R562 33_4 SD_DAT0
C726 *4.7u/10V_6
+3V R557 *SHORT0603 C724 0.1u/16V_4
C701 1 36 C1_IOP DATA1 R577 33_4 SD_DAT1
LED C1_VDDHM
<10> EXT48MHZ 2 EXT48IN DATA6 35
4.7u/10V_6 3 34 CTRL0
R560 330_4 RSTN CTRL0 DATA2 R578 33_4 SD_DAT2
4 REXT DATA5 33
+3V_VDD 5 32 CTRL2
VD33P CTRL2
<10> USBP12+ 6 DP DATA4 31
7 AU6435-GDL 30 DATA3 DATA3 R579 33_4 SD_DAT3
<10> USBP12- DM DATA3
8 29 DATA2
C698 C699 XI VS33P DATA2 XD_WP#
9 XI XDWPN 28
XO 10 27 XD_CE# T92
*5p/50V_4 *5p/50V_4 XO XDCEN EEPDATA T94
11 VDD EEPDATA 26
EEPCLK T91
+1.8V_VDD 12 25 Close to connector
VSSA_SYN
V18 EEPCLK T93
SDWPEN
AGND5V
AVDD5V
VDDHM
C1_V33
C696
C1_IOP
XDCDN
CTRL4
GND
VDD
V33
2 4.7u/10V_6 2
13
14
15
16
17
18
19
20
21
22
23
24
CLK length should be as short as possible. Shorter than

crystal trace width needs at least 10 mils. pin13 output 20mils 1200 mil is good.
*0_4 R552 SD write protect
VCC_XD XD_CD# 1:decided by SDWP[Default]
C702 18p/50V_4 XI T96 0:letting SD always CTRL0 R529 33_4 SD_CLK
C1_IOP write-able
C725 0.1u/16V_4
Y7 R558 +3V +1.8V_VDD CTRL1 SD_WP C449
12MHz 270K_4 C270 2.2u/6.3V_6 +3V *10p/50V_4
+3V
C703 18p/50V_4 XO C690 4.7u/10V_6 C691 CTRL2 R573 33_4 SD_CMD
0.1u/16V_4 1/12 add by FAE's request

CTRL3 SD_CD#
1 1
352-(&7=4
4XDQWD&RPSXWHU,QF
www.vinafix.vn
http://hobi-elektronika.net AU6433 CardReader 1A

A B C D E
5 4 3 2 1
LED
D D
+3V_S5
POWER Amber
R342 100/F_4 LED3 Bule

<27> PWRLED#
Blue
C C
R339 *1M_4 +3VPCU
R336 *1M_4
+3VPCU
Battery Amber
LED_B/R
R338 300/F_4 1 2
<27> BATLED0#
R335 100/F_4 4 3
<27> BATLED1# LED5
Blue
B B
A A

PROJECT : ZQH
1A
POWER/MMB/LAUNCH/LED
5 4 3 2 1
5 4 3 2 1
USB +5V_S5
C455
U9
1U/6.3V_4 2 8 USBPWR1
IN1 OUT3
3 IN2 OUT2 7
6 C693 C465 BLUETOOTH CONNECTOR for 3.0
D OUT1 + D
4 CN15
<27> USBON# EN# 1000p/50V_4 BT_POWER
1 GND +3V_S5 1 3 5
OC# 5 4
330u/6.3V_6X5.7 Q22 USBP4+_R
G547F2P81U + C705 C706 USBP4-_R 3
2
*AO3413 *1000p/50V_4 BT_LED 2 7
*2.2u/6.3V_6 T101 1 6
<10> USB_OC0# <27> BT_POWERON#
*BT_CONN
CN14
1 8 C712
USBP1-_R 1 8 R567 *0_4 *.01u/16V_4
2 2 7 7
USBP1+_R 3 6 L57
3 6 USBP4+_R
4 4 5 5 <10> USBP4+ 3 3 4 4
2 2 1 USBP4-_R
<10> USBP4- 1
R310 *0_4 USB_MB_Turbo
*RFCMF1632100M3T/200mA/90ohm
L33 R568 *0_4
2 1 USBP1+_R
<10> USBP1+ 2 1
1
3 4 USBP1-_R
<10> USBP1- 3 4 RV2 RV1
DLW21HN900SQ2L/300mA/90ohm
R312 *0_4 *EGA-0402 *EGA-0402
2
C C
+5V_S5
USB/B
C446
*1u/6.3V_4
R279
*SHORT1206
C409
*1u/6.3V_4
USB_DB FFC CONN

16
R261 *0_4 15
B B
14
L29 13
USBP9+_R 12
<10> USBP9+ 2 2 1 1 <10> USB_OC4_5# 11
3 4 USBP9-_R
<10> USBP9- 3 4 10
DLW21HN900SQ2L/300mA/90ohm USBP11-_R 9
R262 *0_4 USBP11+_R 8
7
6
R274 *0_4 USBP9-_R 5
USBP9+_R 4
L31 3
USBP11+_R 2 17
<10> USBP11+ 2 2 1 1 1 18
USBP11-_R <27> USBON#
<10> USBP11- 3 3 4 4
CN10
DLW21HN900SQ2L/300mA/90ohm
R273 *0_4
A A

PROJECT : ZQH
1A
USB/ BT
5 4 3 2 1
5 4 3 2 1
+3V
K/B CN2 CPU FAN
MY0 1
<27> MY0
7 8 MX3 MY1 2 R385
<27> MY1
5 6 MX2 MY2 3
<27> MY2 +5V
3 4 MX4 MY3 4 10K_4
<27> MY3
1 2 MX5 MY4 5
<27> MY4
CP6 *100p/50Vx4 MY5 6
<27> MY5
7 8 MX6 MY6 7
<27> MY6
2
5 6 MX7 MY7 8 C549
D <27> MY7 <27> FANSIG D
3 4 MY17 MY8 9 2.2U_6
<27> MY8
1 2 MY16 MY9 10 U17 CN6
<27> MY9
1
CP5 *100p/50Vx4 MY10 11 2 3 TH_FAN_POWER 1
<27> MY10 VIN VO
7 8 MY3 MY11 12 5 2
<27> MY11 GND
5 6 MY2 MY12 13 1 6 3
<27> MY12 <10,11,27> SML1ALERT# /FON GND
2
3 4 MY1 MY13 14 7 C547 C548 C546
<27> MY13 GND
1 2 MY0 MY14 15 4 8 FAN_CONN
<27> MY14 <27> CPUFAN# VSET GND
CP4 *100p/50Vx4 MY15 16 2.2U_6 .01U_4 *.01U_4
<27> MY15
1
7 8 MY7 MY16 17 G995P1U
<27> MY16
5 6 MY6 MY17 18
<27> MY17
MY5 MX7
3
1
4
2 MY4
<27> MX7
MX6
19
20
FANPWR = 1.6*VSET
<27> MX6
CP3 *100p/50Vx4 MX5 21
<27> MX5
7 8 MY11 MX4 22
<27> MX4
5 6 MY10 MX3 23
<27> MX3
3 4 MY9 MX2 24 27
<27> MX2
1 2 MY8 MX1 25 28
<27> MX1
CP2 *100p/50Vx4 MX0 26
<27> MX0
7 8 MY15
5 6 MY14 KB
3 4 MY13 +3VPCU
1 2 MY12
CP1 *100p/50Vx4
C
C222 *100p/50V_4 MX1
MX0
RP3 10K_10P8R TOUCHPAD & Switch CONN. C
C221 *100p/50V_4 10 1 MX3
MX4 9 2 MX2
MX5 8 3 MX1
MX6 7 4 MX0
MX7 6 5 +5V +5V
L20 *SHORT0603 +TPVDD
C223
HOLE R86
10K_4
R87
10K_4
0.1u/10V_4_X7R
CN1
HOLE2 HOLE21 HOLE3 HOLE22 1
*hg-c315d110p2 *H-C197D87P2 *H-C94D94N *H-O95X134D95X134N L18 *SHORT0603 2
<27> TPDATA
7 6 TPDATA_R 3
8 5 L19 *SHORT0603 TPCLK_R 4
<27> TPCLK
9 4 5
C219 C220 6
RIGHT# 7
1
2
3
1
*.01u/25V_4 8
*.01u/25V_4 9
10 13
B 11 14 B
HOLE13 HOLE14 HOLE15 HOLE9 LEFT# 12
*hg-c315d118p2 *hg-c315d118p2 *hg-c315d118p2 *hg-c315d118p2
7 6 7 6 7 6 7 6 Aces 88501-120N
8 5 8 5 8 5 8 5
9 4 9 4 9 4 9 4 HOLE8 HOLE11 HOLE12
*H-TC256BC165D165P2 *H-TC256BC165D165P2 *H-TC256BC165D165P2
1
2
3
1
2
3
1
2
3
1
2
3
SW3 SW2
RIGHT# 3 2 LEFT# 3 2
HOLE6 HOLE17 HOLE10 HOLE16 HOLE7 1 4 1 4
*hg-c315d118p2 *hg-c315d118p2 *hg-c315d118p2 *hg-c315d118p2 *hg-c315d118p2
1
7 6 7 6 7 6 7 6 7 6 SWITCH_1.5 SWITCH_1.5
8 5 8 5 8 5 8 5 8 5
9 4 9 4 9 4 9 4 9 4
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
A A

PROJECT : ZQH
1A
KB/FAN/TP+FP
5 4 3 2 1
5 4 3 2 1
EC(KBC) L22 PBY160808T-250Y-N/3A/25ohm_6 +A3VPCU

+3V
I/O ADDRESS SETTING(KBC)
C226 C227
30mil
0.1u/10V_4_X7R
10u/6.3V_6
+3VPCU E775AGND
R108 2.2_6 D15 C570 C571
1 2 +3VPCU_EC 0.03A(30mils)
BAS316 4.7U/6.3V_6 0.1u/10V_4_X7R
C573 C538 C593 C551 C229 C225
115
102
19
46
76
88
4
4.7U/6.3V_6 0.1u/10V_4_X7R
*.1u/16V_4 0.1u/10V_4_X7R
*.1u/16V_4 0.1u/10V_4_X7R U18
AVCC
VDD
VCC1
VCC2
VCC3
VCC4
VCC5
E775AGND C595 10u/6.3V_8 ICMNT SHBM=0: Enable shared memory with host BIOS
D D
C605 0.01u/16V_4
<9,19> LPC_LFRAME# 3 97 TEMP_MBAT <28>
LFRAME GPIO90/AD0 WL_SW
<9,19> LPC_LAD0 126 98 T58
LAD0 GPIO91/AD1 SHBM_R R405 10K_4
<9,19> LPC_LAD1 127
LAD1 GPIO92/AD2
99 SML1ALERT# <10,11,26> SHBM
<9,19> LPC_LAD2 128
LAD2 A/D GPIO93/AD3
100 ICMNT <28>
<9,19> LPC_LAD3 1 108
CLK_PCI_775 CLK_PCI_775 LAD3 GPIO05
<10> CLK_PCI_775 2
LCLK GPIO04
96 1/13 Comfirm by vendor mail :
Disabled ('1') if using FWH device on LPC.
<8> CLKRUN# 8 GPIO11/CLKRUN
101
Enabled ('0') if using SPI flash for both system BIOS and EC firmware
GPIO94/DA0 T6
R106 121 105 T7
<11> SIO_A20GATE GPIO85/GA20 GPI95/DA1
*22_4
D/A GPI96/DA2 106 CPUFAN# <26>
<11> SIO_RCIN# 122 KBRST/GPIO86 GPI97 107
<11> SIO_EXT_SCI#
D3 BAS316 29 ECSCI/GPIO54 LPC SM BUS PU(KBC) +3VPCU
GPIO01/TB2 64 ACIN <28>
C228 EC_FPBACK# 6 95 NBSWON#
<16> EC_FPBACK# GPIO24/LDRQ GPIO03
*10p/50V_4 93 MBCLK R92 10K_4
GPIO06/IOX_DOUT LID591# <16>
T60 NOCIR# 124 94 MBDATA R91 10K_4
GPIO10/LPCPD GPIO07 SUSB# <8>
GPIO23/SCL3 119
PLTRST# 7 109 T61
<4,10,18,19,23> PLTRST# LREST GPIO30/CIRTX2
GPIO31/SDA3 120
USBON# 123 65
<25> USBON# GPIO67/PWUREQ GPIO32/D_PWM BATLED0# <24>
GPIO33/H_PWM 66 BATLED1# <24>
IRQ_SERIRQ 125 15 +3V
<9> IRQ_SERIRQ SERIRQ GPIO36 VRON <30>
GPIO40/F_PWM 16
9 17 AC_OFF T52
<11> SIO_EXT_SMI# GPIO65/SMI GPIO42/TCK
GPIO 20 2ND_MBCLK R88 10K_4
GPIO43/TMS AMP_MUTE# <21> 2/17 add for throttling function
21 3G_SW T49 2ND_MBDATA R89 10K_4
MX0 GPIO44/TDI
<26> MX0 54 KBSIN0 GPIO45/E_PWM 22 T48
MX1 55 23 T47
<26> MX1 KBSIN1 GPIO46/CIRRXM/TRST
MX2 56 24 T46
<26> MX2 KBSIN2 GPO47/SCL4
1
MX3 57 25 +3VPCU
C <26>
<26>
MX3
MX4
MX4
MX5
58
KBSIN3
KBSIN4
GPIO50/TDO
GPIO51 26
D/C# <28>
S5_ON <29,34>
Q12 PWR/B C
<26> MX5 59 KBSIN5 GPIO52/CIRTX2/RDY 27 HDMI_HPD_EC# <17> *DMN601K-7

MX6 60 28 H_PROCHOT_EC 2
<26> MX6 KBSIN6 GPIO53/SDA4
MX7 61 91 R26
<26> MX7 KBSIN7 GPIO81 DNBSWON# <8> 1/10 change P/N & footprint
110 10K_4
MY0 GPO82/TEST
<26> MY0 53 KBSOUT0/JENK GPO84/TRIST 112
MY1 52 80 T50
<26> MY1
3
MY2 KBSOUT1/TCK GPIO41 CN21
<26> MY2 51 KBSOUT2/TMS
MY3 50 NBSWON# 1
<26> MY3 KBSOUT3/TDI <4,30> H_PROCHOT# 1
MY4 49 KB 31 ODDLED T45 2
<26> MY4 KBSOUT4/JEN0 GPIO56/TA1 2
MY5 48 117
<26> MY5 KBSOUT5/TDO GPIO20/TA2/IOX_DIN SUSON <32>
MY6 47 63 C36 C50
<26> MY6 KBSOUT6/RDY GPIO14/TB1 FANSIG <26>
MY7 43 0.1U/10V/X5R_4 *1000P/16V/X7R_4 SPEAKER-CONN
<26> MY7 KBSOUT7
MY8 42 TIMER 32
<26> MY8 KBSOUT8 GPIO15/A_PWM CONTRAST <16>
MY9 41 118
<26> MY9 KBSOUT9/SDP_VIS GPIO21/B_PWM PCBEEP_EC <21>
MY10 40 62
<26> MY10 KBSOUT10/P80_CLK GPIO13/C_PWM PWRLED# <24>
MY11 39 81 T5
<26> MY11 KBSOUT11/P80_DAT GPIO66/G_PWM
MY12 38
<26> MY12 KBSOUT12/GPIO64
MY13 37
<26>
<26>
MY13
MY14
MY14
MY15
36
KBSOUT13/GPIO63
KBSOUT14/GPIO62 GPIO77/SPI_DI
84
SHBM_R
T54 SPI FLASH(KBC) +3VPCU
<26> MY15
MY16
35
KBSOUT15/GPIO61/XOR_OUT SPI GPO76/SPI_DO/SHBM
83 T51
U19
<26> MY16 34 82
MY17 GPIO60/KBSOUT16 GPIO75/SPI_SCK SPI_SDI_uR R99 22_4 SPI_SDI_uR_R
<26> MY17 33 2 8
GPIO57/KBSOUT17 SO VDD
75 RSMRST#_uR R90 *Short_4 R96 *100K_4 SPI_SDO_uR 5 7 C591
GPIO72/IRRX1/SIN2 ICH_RSMRST# <8> SI HOLD
MBCLK 70 73
<28> MBCLK GPIO17/SCL1 GPIO70/IRRX2_IRSL0 SUSC# <8> 7/24 modify
MBDATA 69 74 PWROK_EC_uR R386 *Short_4 SPI_SCK_uR 6 3 0.1u/10V_4
<28> MBDATA GPIO22/SDA1 GPIO71/IRTX/SOUT2 PWROK_EC <8> SCK WP
<10> 2ND_MBCLK 2ND_MBCLK 67 SMB IR 113
GPIO73/SCL2 GPIO87/CIRRXM/SIN_CR RF_EN <19>
<10> 2ND_MBDATA 2ND_MBDATA 68 14 T53 +3VPCU R101 10K_4 SPI_CS0#_uR 1 4
GPIO74/SDA2 GPIO34/CIRRXL HWPG CE VSS
114
GPIO16/CIRTX P_SAVE_LED# W25X40BVSSIG
GPO83/SOUT_CR/XORTR 111 T59
TPCLK 72
<26> TPCLK GPIO37/PSCLK1
TPDATA 71 1/13 Comfirm by vendor mail :
<26> TPDATA GPIO35/PSDAT1
B PCH_ACIN 10 86 SPI_SDI_uR If the Southbridge enables 'Long Wait Abort' by B
<8> PCH_ACIN GPIO26/PSCLK2 F_SDI
11 PS/2 87 SPI_SDO_uR_R R97 22_4 SPI_SDO_uR
<25> BT_POWERON# GPIO27PSDAT2 F_SDO default, the flash device should be 50MHz (or faster)
12 FIU 90 SPI_CS0#_uR
<31,32,34> MAINON GPIO25/PSCLK3 F_CS0
T55 MAINOND 13 92 SPI_SCK_uR_R R102 22_4 SPI_SCK_uR
GPIO12/PSDAT3 F_SCK
<8> ICH_SUSCLK R390 *Short_4 E775_32KX1 77 30 ECDB_CLOCK T43
GPIO00/32KCLKIN GPIO55/CLKOUT/IOX_DIN
VCC_POR
85 VCC_POR# R415 47K/F_4 +3VPCU HWPG(KBC) +3V
VCORF
AGND
GND1
GND2
GND3
GND4
GND5
GND6
R392 *20M_6 E775_32KX2 79 104 VREF_uR R107 *Short_4 +A3VPCU

GPIO02 VREF
R398 NPCE781 R110

5
18
45
78
89
116
103
VCORF_uR 44
10K_4
Y4 *33K/F_4 SM BUS ARRANGEMENT TABLE
1 4 D9 BAS316 HWPG
<34> HWPG_1.8V
SM Bus 1 Battery
L21 PBY160808T-250Y-N/3A/25ohm_6 D7 BAS316
<31> HWPG_1.05V
C550 *32.768KHz C552 C539 SM Bus 2 PCH D8 BAS316
<32> HWPG_1.5V
*15p/50V_4 *15p/50V_4 R109
1u/6.3V_4 D6 BAS316 *Short_4
<29> SYS_HWPG
E775AGND E775AGND SM Bus 3 GPU-I2C
D5 BAS316
<33> HWPG_GFX
MPWROK <4>
SM Bus 4 N/A
Power sequence CN19 POWER-ON Switch(KBC) INTERNAL KEYBOARD STRIP SET(KBC)

NBSWON# 2 1
+3V_S5 4 3 S5_ON
A DNBSWON# 6 5 ICH_RSMRST# SW1 A
SUSON 8 7 SUSC# *DIP:TME-533B-Q-T/R +3VPCU
SUSB# 10 9
+3V 12 11 NBSWON# 1 2 MY0 R393 10K_4
MAINON <31,32,34>
14 13 3 4
+VCC_CORE 16 15 VRON <30> 5
PWROK_EC 18 17 HWPG 6
PLTRST# 20 19
22 21
24 23 Quanta Computer Inc.
26 25
28 27 PROJECT : ZQH
<4,11> H_PWRGOOD 30 29
*CON30_DEBUG 1A
www.vinafix.vn
WPCE781 & FLASH
5 4 http://hobi-elektronika.net 3 2
Date: Monday, March 14, 2011
1
Sheet 27 of 35
5 4 3 2 1
PR145
VA1 PD6 0.01_0612
PL2 SBR1045SP5-13 PQ27 VIN PQ29
PJ1 HI0805R800R-00_8 1 FDD6685_G FDD6685_G
1 VA 3 VA2 3 4 1 2 3 4
2 2
3
1
4
1
PC81 PC82 PR147 PR144 PC6 PC1 PR156
POWER_JACK PL1 0.1u/50V_6 0.1u/50V_6 220K_4 0_4 0.1u/50V_6 2200p/50V_6 33K/F_4
HI0805R800R-00_8 PD5 PR146
SMAJ20A 0_4 CSIN_1
2
D D
PC78 PC79 CSIP_1
0.1u/50V_6 2200p/50V_6 1 6
PD1 PR157
SW1010CPT PR148 2 5 10K_4
D/C# <27>
220K_4
3 4 PR149
3
0_4
PQ28
IMD2AT108
CSIN_1 2
PQ32
CSIP_1 DMN601K-7
1
VIN
PC11
PR9 PR8 1u/16V_6
10/F_4 10/F_4
PC14
0.1u/50V_6 PR159
4.7_6 PC7
1u/16V_6
27 CSIN
28 CSIP
ISL88731_VDDP
PC84
5
10u/25V_1206
33
32
31
30
26
21
C C
1
+3VPCU PD7 PC83
*RB500V-40 2200p/50V_6
CSSP
VDDP
NC
GND
GND
GND
GND
CSSN
VCC
PC12 PR6 PC10 4
0.1u/50V_6 2.7_6 0.1u/50V_8
+3VPCU 11 25 88731B_2 88731B_1 PQ31 PR158
VDDSMB BOOT AON7410 0.01_0612
3
2
1
PL5
<27> MBDATA 9 24 ISL88731_UGATE 6.8uH
PR7 SDA UGATE BAT-V
1 2
100K_4
<27> MBCLK 10 23 ISL88731_PHASE
SCL PHASE
5
13 20 ISL88731_LGATE PR155
<27> ACIN ACOK LGATE *4.7_6
4
PR5 PC9 19
49.9/F_6 0.1u/50V_6 PGND PQ30
DCIN 22 AON7410 CSOP_1
3
2
1
DCIN PR3 PC85 PC87 PC86
PR11 10/F_4 PC88 BAT-V 2200p/50V_6 10u/25V_1206 10u/25V_1206
82.5K/F_4 PU1
CSOP 18 CSOP CSOP_1 *680p/50V_6
PC3 88731ACSET 2 ISL88731C
0.1u/50V_6 ACIN PC8
2 1 0.1u/50V_6
3 VREF
B
PC2 PR12
CSON 17 CSON BAT-V
B
100p/50V_6 PL4 22K/F_4
HI0805R800R-00_8 4 PR1
ICOMP 10/F_4
NC 16
MBAT+ BAT-V
C114F3-108A1-L_Batt_Conn 5 PR4
PL3 NC *SHORT0402
HI0805R800R-00_8 15 BAT-V
10 1 PR153 VBF
2 6 VCOMP
100_4 29 PR2
3 TEMP_MBAT GND 100_4
GND
4 TEMP_MBAT <27>
ICM
NC
NC
5
6 PR152 PR10
7
14
12
7 100K_4 2.21K/F_4
9 8
+3VPCU
PJ2
PC5 PC4
47p/50V_6 47p/50V_6 PC13
0.01u/50V_6
ISL88731 thermal pad
ICMNT
tie to Pin12
ICMNT <27>
PR154
*SHORT_PAD_4 PR150 PR151
100_4 100_4 PC15 PC16 PC17
*1u/16V_6 0.01u/50V_6 *0.01u/50V_6
MBCLK <27>
A MBDATA <27> A
PU6
CM1293A-04SO
1 6 MBDATA
CH1 CH4
2 VN VP 5 +3VPCU Quanta Computer Inc.
TEMP_MBAT 3 4 MBCLK
CH2 CH3 PROJECT : ZQH
Add ESD diode base on EC FAE suggestion 1A
Charger(ISL88731A)
5 4 3 2 1
5 4 3 2 1
MAIND SYS_SHDN#
MAIND <32,34> SYS_SHDN# <4,34>
Ven=7.23V
<27> SYS_HWPG VIN VIN VL 8223REF +3VPCU

+3VPCU
D VIN VIN D
PR240
4.7u/6.3V_6
4.7u/6.3V_6
PR239 10_8
665K/F_4
1
+ PC183 PR241
1u/6.3V_4 *0_4
8223_VIN
8223_EN
PC173 PC170 PC63 PC181 PC165 PC171
2
PC184
PC182
100u/25V_6X5.8 4.7u/25V_8 2200p/50V_6 PR245 0.1u/25V_4 2200p/50V_6 4.7u/25V_8
0_4
PR242 PR243
5
PR244 PR246 PR247 *0_4 0_4
*100K/F_4 330K/F_4 0_4
PQ14
+5VPCU +3VPCU
16
17
5
3
AON7410
5 Volt +/- 5% 4 3 Volt +/- 5%
VIN
VREG3
VREG5
REF
TDC : 5A PQ13
SYS_SHDN# 13 EN SKIPSEL 14 +3V_SKIP TDC : 3.7A
4
3
2
1
PEAK : 6.5A AON7410 +3V_PG 23 PGOOD TONSEL 4 +3V_TON PEAK : 5A
+5VPCU OCP : 8A +5V_DH 21 10 +3V_DH PC65 OCP : 6A +3VPCU
1
2
3
UGATE1 UGATE2 0.1u/50V_6
Width : 200mil PL13 PC66 PR107 +5V_B 22 BOOT1 BOOT2 9 +3V_B PR106 PL14 Width : 120mil
2.2uH 0.1u/50V_6 1/F_6 PU5 1/F_6 2.2uH
+5V_LX 20 RT8223M 11 +3V_LX
PHASE1 PHASE2
+5V_DL 19 12 +3V_DL
LGATE1 LGATE2
5
C PR125 24 7 C
VOUT1 OUT2
ENTRIP1
ENTRIP2
15.4K/F_4 PR98 PR126
PQ11 +5V_FB 2 5 +3V_FB *4.7_6 6.81K/F_4
GND
GND
ENC
+ PR97 AON7702 FB1 FB2 +
4
*4.7_6 4
PC178
18
25
15
PR248 0.1u/50V_6
1
2
PC174 PC177 3 0_4 PQ12 PC59 PC175
3
2
1
330u/6.3V_6X5.7 0.1u/50V_6 8223_EN AON7702 *680p/50V_6 330u/6.3V_6X5.7
PR117 PC58
2
10K/F_4 *680p/50V_6
PR249 PC185
100K/F_4 0.1u/10V_4 PR131
10K/F_4
1
PR251
PR250 71.5K/F_4
97.6K/F_4
+5V_DL
OCP:6A
PC186 PR252 L(ripple current)
2 0.1u/50V_6 *0_6
OCP:8A PD9 +3V_DL PR253 =(9-3.3)*3.3/(2.2u*0.5M*9)
CHN217 3 0_6
L(ripple current) PR254
~1.9A
=(9-5)*5/(2.2u*0.4M*9) 1 0_6 PR255
PC187 0_6
Iocp=6-(1.9/2)=5.05A
B =2.525A 0.1u/50V_6 Vth=5.05A*14mOhm=70.7mV B
2
Iocp=8-(2.525/2)=6.74A PD10
R(Ilim)=(70.7mV*10)/10uA
Vth=6.74A*14mOhm=94.32mV 3
CHN217 =70.7K
PC188
R(Ilim)=(94.32mV*10)/10uA 1 0.1u/50V_6
~94.32K
+15V_ALWP
+15V
PR256
22_8
PC189
0.1u/50V_6
VIN +3V_S5 +5V_S5 +15V VIN +5VPCU +5VPCU +3VPCU +3VPCU
PR140 PR138 PR139 PR143 PR142
3
1M_6 22_8 22_8 1M_6 *1M_6
5
6
7
8
5
6
7
8
5
6
7
8
S5D
S5D 4 MAIND 4 MAIND 4
2
+3V_S5
TDC : 0.23
3
PQ57
A PQ15 PQ56 PQ58 AO3404 PEAK : 0.3A A
1
2 AO4468 AO4468 AO4468
<27,34> S5_ON
2 2 2 +3V_S5 Width : 20mil
3
2
1
3
2
1
3
2
PR141 PQ17 PQ18 1
1
PQ16 1M_6 DMN601K-7 DMN601K-7

DTC144EU PQ19 PC75
+5V_S5 +5V_S5 +5V +5V +3V +3V Quanta Computer Inc.
1
DMN601K-7 *2.2n/50V_4
TDC : 2.85A TDC : 2.17A TDC : 2.66A
PEAK : 3.8A PEAK : 2.9A PEAK : 3.6A PROJECT : ZQH
www.vinafix.vn
Width : 120mil Width : 90mil Width : 120mil SYSTEM 5V/3V (RT8206) 1A
5 4
http://hobi-elektronika.net 3 2
Date: Monday, March 14, 2011
1
Sheet 29 of 35
5 4 3 2 1
VID 1.2875V
+3VPCU PR199 *0_4 H_VID0 DELAY_VR_PWRGOOD <4,8>
PR200 *0_4 H_VID1 Connect to input caps

VIN +VCC_CORE
Countinue current:36A
1
+ +
PR198 *0_4 H_VID2
Peak current:48A
2
PQ41
OCP minimum 55A
5
PR197 *0_4 H_VID3 AOL1448
PR55
1K/F_4
Loadline=1.9mV/A (IMVP 6.5)
+3VPCU PR196 *0_4 H_VID4 2/16 change for leakage 4 PC179 PC121 PC120 PC122 PC124 Rilm=1.69K
D 100u/25V_6X5.8 4.7u/25V_8 4.7u/25V_8 4.7u/25V_8 100u/25V_6X5.8 D
1
2
3
PR195 *0_4 H_VID5 +5V_S5 +3V PC118 PL8 +VCC_CORE
0.1u/50V_6 0.36uH
PR193 *0_4 H_VID6 2/16 change for leakage 1 2

PC130
1000p/50V_4 PQ43
4
5
1
PR236 *SHORT_PAD_4 AOL1718 + +
+5V_S5 PR52 PR39 PR35 PC136 PC22
PR203 649K/F_4 1.91K/F_4 *2.2/F_6 0.1u/50V_6 330u/2V_7343
2
4
16 3212_RAMP
*SHORT_PAD_8 PR34
1
2
3
10_6 PC123
PC24 *330u/2V_7343
*1000p/50V_6
3212_VCC 1/12 stuff
PR30 PR33
37
39
38
2
0_6 10/F_6
+1.05V PC23
PH0
PH1
VCC
PWRGD
RAMP
2.2u/6.3V_6
PR50 12 35 3212_DH1
*499/F_4 AGND DRVH1
49 36 3212_BOOT1
AGND BST1 PR38 2.2_6
<4,27> H_PROCHOT# PR31
0_4 PC25
PSI#_1 41 0.22u/25V_6
<6> H_PSI# PSI#
3
PQ9 34 3212_SW1
*DMN601K-7 SW1
2 10 VIN
VR_TT
C C
This NTC Close to Phase 1 Inductor
1
PR207 31 3212_DL1 +
DRVL1
+5V_S5
1
7.32K/F_4 PC137
PR191
2
11 100u/25V_6X5.8
TTSNS
*220K_6 NTC +5V_S5
+5V_S5 PR47 5.1K/F_4 8 PU2
PC129 TRDET# PC29
1 2 9
VARFR
5
Panasonic *0.01u/16V_4 ADP3212 32 1 2 PQ48 PC135 PC133 PC134 PC132
CPU_VID0 PVCC AOL1448 0.1u/50V_6 4.7u/25V_8 4.7u/25V_8 4.7u/25V_8
<6> H_VID0 48
ERT-J0EV474J VID0 4.7u/6.3V_6
CPU_VID1 47 26 3212_DH2 4
<6> H_VID1 VID1 DRVH2
CPU_VID2 46 25 3212_BOOT2
<6> H_VID2
1
2
3
VID2 BOOT2
CPU_VID3 45 PR49 PL9 +VCC_CORE
<6> H_VID3 VID3 2.2_6 PC31 0.36uH
CPU_VID4 44 0.22u/25V_6
<6> H_VID4 VID4
27 3212_SW2 1 2
CPU_VID5 SW2
<6> H_VID5 43
VID5
5
PQ46
4
CPU_VID6 42 AOL1718
<6> H_VID6 VID6 PR54
1
PR37 0_4 VR_ON 1 29 3212_DL2 4 *2.2/F_6 + +
<27> VRON EN DRVL2 PC117
2
PR32 499/F_4 DPRSLPVR_R 40 0.1u/50V_6

<6> H_DPRSLPVR
1
2
3
2
PR36 DPRSLPVR
30
100K/F_4 PGND PC32
<3> VR_PWRGD_CK505# 4
CLK_EN# *1000p/50V_6 PR59 PR60
+3V PR43 1.91K/F_4 0_6 10/F_6 PC30 PC128
1
330u/2V_7343 *330u/2V_7343
28 PR48 100/F_4 3212_CS_PH2
SWFB2 1/12 unstuff
22
OD3#
23 33 PR44 100/F_4 3212_CS_PH1
PWM3 SWFB1
B B
24
PC27 SWFB3 3212_CSSUM PR61
19
150p/50V_4 CSSUM 150K/F_6
PC34
3212_FB 6 1000p/50V_4 PR58 PR56
FB
1
165K/F_4 150K/F_6
1
PC26
2
12p/50V_4 PC33 Short the net trace

PC28 PR45 1000p/50V_4 PR190
2
150p/50V_4 39.2K/F_4 220K_6 NTC

PR46 3212_COMP 7 20
COMP CSCOMP
1.65K/F_4
17 3212_CSCOMP
3212_FBRTN PC127 1000p/50V_4 LLINE PR57
5
FBRTN Close to Phase 1 Inductor
73.2K/F_4
21 3212_ILIM
ILIM
3
CSREF
IMON PR51
IREF
RPM
PR204 1.69K/F_4
RT
4.99K/F_4
1 2 PR53
13
14
15
18
0_4
PC126 3212_CSREF CSREF
0.082u/16V_4
<6> I_MON
PC131
PR202 1u/6.3V_4 Peak :40A ; OCP:53A (1.69K/F_4)
PR206 *0_4
*27.4_4 Peak :48A ; OCP:55A (1.74K/F_4)
PR210 PR208
+1.05V 80.6K/F_4 162K/F_4
A PR209 A
69.8K/F_4
PR42
0_4
VSSSENSE <6>
VCCSENSE <6>
PR41
0_4 Quanta Computer Inc.
PR40
*27.4_4
PROJECT : ZQH
www.vinafix.vn
+VCC_CORE
1A
+VCC_CORE ADP3212
5 4 3 2 1
5 4 3 2 1
[PWM] +1.05V
VIN
D +5V_S5 1.05 Volt +/- 5% D
TDC : 11A
PEAK : 15A
PR71 + +
10_6 OCP : 18A
PR96 PD2 PC164 PC57 PC163 PC180
2.2/F_6 RB500V-40 2.2n/50V_4 4.7u/25V_8 *4.7u/25V_8 100u/25V_6X5.8 Width : 1320mil
PR79
1M/F_4 PC56
4.7u/6.3V_6 PQ55 +1.05V
5
PR95 PC54 AOL1448 PC168
PU4 0_6 0.1u/50V_6 100u/25V_6X5.8
PR91 G5602
0_4 4
<27,32,34> MAINON 15 EN/DEM BOOT 13
1
2
3
+3V 16 12 UGATE-1.05V PL12
PC48 TON UGATE 1uH
*0.1u/50V_6 1 11 PHASE-1.05V
VOUT PHASE
PR74 2 10 PR94
VDD OC
5
C *10K/F_4 3.4K/F_4 C
3 9 PC55 PR86
FB VDDP 1u/16V_6 2.2_6 + +
4 8 LGATE-1.05V 4
<27> HWPG_1.05V PGOOD LGATE PC153 PC144 PC145
6 7 PC47 560u/2.5V *560u/2.5V 0.1u/50V_6
1
2
3
GND PGND PQ54 2200p/50V_6
5 17 AOL1718
NC TPAD
14 NC
PC42 PC46
1u/16V_6 *1000p/50V_6
PR75
B 4.02K/F_4 PC41 B
R1 *33p/50V_6
1.05V_FB
PR73
10K/F_4
R2
PR237 0_6
TON=3.85p*RTON*Vout/(Vin-0.5) AO1718 Rdson=3~4.3mOhm
L(ripple current) PR222 0_6
Frequency=Vout/(Vin*TON) =(19-1.05)*1.05/(1u*272k*19)
~3.647A
A TON=3.85p*1M*1/(Vin-0.5) A
RILIM=4.3mohm*18-1.823/20uA=3.477Kohm
Frequency=1/(0.0036767)=272K I(choke)peak=21.647A Quanta Computer Inc.
PROJECT : ZQH
1A
+VTT (G5602R41U)
5 4 3 2 1
5 4 3 2 1
[PWM]
D D
PC162
10u/6.3V_8
PR223 PC161
0_6 0.1u/50V_6
8207A_VBST
+0.75V_DDR_VTT
8207A_DH VIN
PC167 PC166
2.25A 10u/6.3V_8 10u/6.3V_8 8207A_LX
5
8207A_DL +
PC49 PC158 PC160
4.7u/25V_8 4.7u/25V_8 100u/25V_6X5.8
4
25
24
23
22
21
20
19
PC159
1
2
3
PQ53 2200p/50V_6
LL
DRVL
VTT
VBST
GND
VLDOIN
DRVH
AOL1448 PL11
1uH
1 18 +1.5VSUS
VTTGND PGND
2 VTTSNS CS_GND 17
+1.5V_SUS
5
3 PU11 16 PR99
GND CS
RT8207L 7.15K/F_4
PR84
1 Volt +/- 5%
C
+1.5VSUS 4 MODE V5IN 15 +5V_S5 4 *4.7_6 + TDC : 12A C
PQ51 PEAK : 16A
1
2
3
5 14 AOL1718
+SMDDR_VREF VTTREF V5FILT OCP : 18A
PR100
Width : 480mil
VDDQSNS
VDDQSET
PC62 +5V_S5 6 13 PC61 5.1/F_6 PC60 PC45

0.15A 0.033u/50V_6 COMP PGOOD
1u/10V_4 1u/10V_4 *680p/50V_6 PC150
560u/2.5V
NC
NC
S3
S5
PR102 +3V
100K/F_4
7
10
11
12
FOR DDR III

HWPG_1.5V <27>
PR225
VIN (For RT8207A 400KHZ ) close to pc2008
620K/F_4
S5_1.8V
SUSON <27>
S3_1.8V
MAINON <27,31,34>
PR238 0_6
PR228 +5V_S5
PR101 0_6 *0_4
PC172 PR226
*33p/50V_6 10K/F_4
Vout = (PR150/PR149) X 0.75 + 0.75
B B
AO1718 Rdson=3.8~4.3mOhm
8207A_SET
L(ripple current)
=(19-1.5)*1.5/(1u*400k*19)
PR227 S5_1.8V PR224 S3_1.8V ~3.454A
10K/F_4 *0_4 Vtrip= (18-3.454/2)*4.3mohm=0.0699V
+1.5VSUS RILIM=Vtrip/10u=6.997K
5
6
7
8
MAIND 4
<29,34> MAIND
PQ59
AO4468 S3 S5 +1.5VSUS REF VTT
3
2
1
S0 1 1 ON ON ON
+1.5V
2.03A S3 0 1 ON ON OFF
A
S4/S5 0 0 OFF OFF OFF A

PROJECT : ZQH
www.vinafix.vn
1A
DDR 1.5V(RT8207A)
5 4 3 2 1
A B C D E F G H
Int_VGA [PWM]
<6> GFX_VID0
<6> GFX_VID1 +1.05V +1.05V

<6> GFX_VID2
OCP:25A
<6> GFX_VID3
Ri=2.49K
1 PR78 PR76 PR70 PR69 PR67 PR65 PR64 1
<6> GFX_VID4
*0_4 *0_4 *0_4 *0_4 *0_4 *0_4 *0_4
Change Ri can adjust OCP point
<6> GFX_VID5 LL=7.03mv/A
<6> GFX_VID6 Rdroop=8.87K
PC149
*0.01u/25V_4 GFX_VID6 GFX_VID5 GFX_VID4 GFX_VID3 GFX_VID2 GFX_VID1 GFX_VID0 Change Rdroop can adjust loadline
62881_GND 2 1
PR215 100K_4
<6> GFX_ON
PR217 0_4
<6> GFX_DPRSLPVR
PR81 0_4
PR221
0_6 VIN
62881_GND
62881DPRSLPVR
62881_GND
62881VR_ON
1
PC138 PC140
GFX_VID6
GFX_VID5
GFX_VID4
GFX_VID3
GFX_VID2
4.7u/25V_8 4.7u/25V_8
2
+3V PC139 PC141
0.1u/50V_6 2.2n/50V_4
5/26 modify power budget
30
31
29
28
27
26
25
24
23
22
5
PR89
VID6
VID5
VID4
VID3
VID2
GND
GND
GND
DPRSLPVR
VR_ON
GFX_VID1
GFX_VID0
*100K_4
PR90 1
OCP:25A
0_4 CLK_EN#
2
62881PGOOD 2 21 +5V_S5
4 22A 2
<27> HWPG_GFX PGOOD VID1
1
2
3
PQ50
PR219 47K/F_4 62881RBIAS 3 20 AOL1448
62881_GND RBIAS VID0 +VGFX_AXG
PR218
*150K/F_4 PC37
PR87 8.06K/F_4 62881VW 4 19 1 2
62881_GND VW VCCP
PC53 4.7u/6.3V_6
18 62881LGATE PL10
1000p/50V_4 62881COMP 5 LGATE 0.56uH
COMP PU3
PR92 PC50 ISL62881HRTZ-T 17 1 2
820K/F_4 22p/50V_4 VSSP
62881FB 6
4
FB
16 62881PHASE
PC51 PHASE PQ49
100P/50V_4 PR88 AOL1718 PR62
5
8.87K/F_4 15 62881UGATE *2.2/F_4
62881VSEN UGATE PR213 + +
7
VSEN 3.65K/F_4
ISUM+
BOOT
ISUM-
IMON PC36
Rdroop 4
VDD
RTN
VIN
PR93 PC52 PC142 PC143 10u/6.3V_8

PR66 PR211 560u/2.5V 560u/2.5V
1
2
3
PR63 PC38 2.61K/F_4 10K_6_NTC
8
10
11
12
13
14
17.8K/F_4 150p/50V_4 PC157 1_6 0.22u/25V_6 PC35
PC156 330p/50V_4 62881BOOT 1 2 Close to Phase
62881VDD
62881ISUM+
62881ISUM-
62881VIN
330p/50V_4 *2.2n/50V_4
62881RTN PR68 Inductor
GFX_IMON
GFX_IMON <6>
PC155 11K/F_4
2
62881_GND PR77
1000p/50V_4 *10K/F_4 PC44
*0.22u/10V_4
1
PC40 PC151
3 0.15U/10V_4 0.1u/10V_4 3
VSS_AXG_SENSE <6>
62881_GND
PR214 VIN
*SHORT_PAD_4 PC147 62881_GND
PC148 *0.1u/10V_4
0.22u/25V_6
62881_GND
+5V_S5
Ri
PC154
*180P/50V_4
PR216
PR212 2.49K/F_4
10_6
PC152
1u/6.3V_4 PR220
*100/F_4
62881_GND
2 1
PR72 PC43
82.5/F_4 0.01u/25V_4
Close to Pin9 and Pin10
Parallel
PR82 10/F_4
PR80
0_4
VSS_AXG_SENSE <6>
4 4
PR85 10/F_4
PR83
0_4
VCC_AXG_SENSE <6>

PROJECT : ZQH
1A
1.Level 1 Environment-related Substances Should NEVER be Used. +VGFX_AXG (ISL62881)
2.Purchase ink, paint, wire rods, and Molding resins only from the business Partners that Sony approves as Green Partners. Date: Monday, March 14, 2011 Sheet 33 of 35
www.vinafix.vn
A B C D E F G H
5 4 3 2 1
+1.8V
1.8 Volt +/- 5% 1.76A PQ60 +3V_S5
TDC : 0.76A +1.8V AO4468
1 8
PEAK : 1.01A 2 7
2
3 6 +3V_S5
Width : 40mil 5
PC190 PC191
1
10u/6.3V_8 0.1u/25V_6
4
D D
PR257
100K_4
PR258
261/F_4 PU12
G9334
Rg 5 DRV PGD 4 HWPG_1.8V <27>
1 MAINON
PC192 PC193 EN MAINON <27,31,32>
3 FB
10u/6.3V_8 10u/6.3V_8 +5VPCU
GND
VCC 6
PR260
2
PR259 Rh 47/F_6
100/F_4 PC194 PR261
PC195 0.1u/25V_6 *100K_4
1
33n/50V_6
Vout1 = (1+Rg/Rh)*0.5
C C
For EC control thermal protection (output 3.3V)

VIN
PU10B
LM393
5 +
PD8 7
SW1010CPT 6 -
VIN +3V +5V +0.75V_DDR_VTT +1.5V +1.8V +15V

PR205
Thermal protection 1M_6
1
PQ45 PR128 PR118 PR119 PR121 PR120 PR122 PR123

AO3409 1M_4 22_8 22_8 22_8 22_8 *22_8 1M_4
2
MAINON_ON_G MAIND
MAIND <29,32>
3
3
B B
3
3
S5_ON 2
<27,29> S5_ON
PR136
2 PQ26 1M_4 2 2 2 2 2 2
PQ44 PR201 <27,31,32> MAINON DTC144EU PC68
1
DTC144EU SHORT0603 PQ20 PQ21 PQ23 PQ22 PQ24 PQ25 *2.2n/50V_4

DMN601K-7 DMN601K-7 DMN601K-7 DMN601K-7 *DMN601K-7 DMN601K-7
1
PR127
1
VL VL *100K/F_6
SYS_SHDN# <4,29>
Need fine tune
for thermal protect point PR194
200K_6
PR189 PC125
PR188 200K/F_4 0.1u/50V_6
3
1.54K/F_4
8
PR187
10K_6_NTC 2.469V 3
+
1 2
2 - PQ39
3
PU10A DMN601K-7
4
Note placement position LM393 PC119

1
0.1u/50V_6
S5_ON 2
PR192
PQ40 200K/F_4
DMN601K-7
A A
1

PROJECT : ZQH
1A
Discharge/1.8V)
5 4 3 2 1 7/7 modify
5 4 3 2 1
MODEL
ZQ9
Model REV CHANGE LIST FRO M To
X 1A
1A X 1A
ZQH 1/7 page.24 U6 HDMI pin 19,20 & pin 41,42 swap for layout
page.30 CN16 speaker conn. pin1,2,3,4 swap for layout X 1A
page.25 U26 transformer change to 10/100 type
page.25 U2, U4 change type, add D2, R21 for surge solution.
page.25 RN1, RN2 swap the pin define for layout 1A B 2A
page.29 R337 change to 2.2K, R476 change to 10u by FAE's recommend 1A B 2A
1A B 2A
1/10 page.16 delete R8 1A B 2A
page.20 add C323, C333, C470, C471, C474, C672, C673 for Vin plane 1A B 2A
page.27 change CN21 PWR/B connector P/N & footprint
1A B 2A
page.18 change R36 to 2.2 ohm
1A B 2A
1/11 page.20 add C480, C337, C674 for Vin plane 1A B 2A
page.34 delete +1V LDO power circuit
1A B 2A
page.20 add C490, C493, C494, C495, C496 by EMI's request
1A B 2A
page.18 change C18 to 220P by EMI's request
1A B 2A
1/10 page.30 stuff PC123, unstuff PC30 1A B 2A
page.23 add R573 for FAE's request 1A B 2A
1A B 2A
1A B 2A
1A B 2A
1A B 2A
1A B 2A
1A B 2A
1A B 2A
1A B 2A
1A B 2A
1A B 2A
1A B 2A
1A B 2A
2/14 Test-Point change footprint. 1A B 2A

2A TP3075 change to TP2675 1A B 2A
TP3050 change to TP2650 1A B 2A
1A B 2A
2/14 page.21 Add R574 & R575
1A B 2A
page.21 R599 chane to 10K ohm resistor.
D
1A B 2A D
2/14 page.30 PC123 unstuff , PC30 stuff. 1A B 2A

page.27 unstuff SW1 & CN19 1A B 2A
page.25 unstuff Bluetooth group. 1A B 2A
page.26 EMI CP1, CP2, CP3, CP4, CP5, CP6 stuff 100pF cap array 1A B 2A
page.20 EMI stuff C553 , ADD C361/C483/C507,C497,C498,C499,C500. 1A B 2A
page.16 EMI stuff C619/C620 1A B 2A
2/14 page20 Reserve C508 1A B 2A
2/14 page19 LED5 , PIN1 connect to<BATLED0#>& PIN4 connect to<BATLED1#> 1A B 2A
2/14 page16 add R16 1A B 2A
C671 & C40 change to TOP side. 1A B 2A
1A
2/14 FDI :: delete R152/R161/R157/R171/R167 , R454/R470/R481/R487/R464/R480/R500/R495/R459/R475/R478/R491/R461/R484/R498/R493 B 2A
Change to 0402short :: R149/R234/R233/R531/R524/R114/R163/R194/R271/R554/R107/R109/R386/R390/R90 1A B 2A
2/14 Change to 0603short :: R113/R142/R168/R186/R169/R172/R174/R178/R185/R201/R213/R417/R268/R275/R299/R5/R11/R581/R587/R588/R557/L18/L19/L20
1A B 2A
2/14 page.18 Add C46/C48/C51/C52 1A B 2A
2/15 POWER cahnge to shortpad 1A B 2A
1A B 2A
2/15 page12 delete R116 & R124. Add C574. 1A B 2A
C598 & C604 change to TOP
1A B 2A
Add C339 , C340
1A B 2A
page16 stuff C661
1A B 2A
2/16 page.30 change +5V_PCU power to +5V_S5 for leakage 1A B 2A
1A B 2A
2/17 page.21 remove R574, R575 & add D10, D11
2/17 page.27 add Q12 and use GPIO53 for throttling function for 40W adaptor 1A B 2A
1A B 2A
2/17 page.21 change U10 P/N 1A B 2A
2/17 page.16 change R14, R16 to 0805 shortpad 1A B 2A
page.18 change R15 to 0805 shortpad 1A B 2A
page.12 change R140, R162, R210,R424 to 0805 shortpad 1A B 2A
page.19 change R303 to 0805 shortpad
page.20 change R443, R550 to 0805 shortpad 1A B 2A
2/17 page.25 change R279 to 1206 shortpad 1A B 2A
1A B 2A
2/17 page.18 unstuff C30
B 2A C 3A
B 2A C 3A
3C 3/10 page.27 Unstuff Q12 B 2A C 3A
3/14 page25. L33 exchange order for USB signal routing. B 2A C 3A
B 2A C 3A
3/14 page.18 R12 & R20 unstuff , R15 change to 0805 resistor and unstuff. B 2A C 3A
3/10 page.19 Add R314 & R574 , 0 ohm or CAP depend on result. B 2A C 3A
B 2A C 3A
3/10 page.32 delete shortpad , PR229 & PR230
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
B 2A C 3A
C C
4A

PROJECT MODEL : ZQH APPROVED BY: DATE:
PROJECT : ZQH DOC NO.
1A
Change list2 PART NUMBER: DRAWING BY: REVISON:
B B
A A
5 4 3 2 1
www.vinafix.vn

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5 4 3 2 1

X'TAL SLG8LV595 DMI(x4)

Cardreader AU6437-GBL USB-12 X'TAL 25MHz

Azalia SPI SPI ROM

Int. MIC ALC272X NPCE781 X'TAL RT8206B RT8207A HPA00835RTER

ADP3212 MAX8792ETD+T Discharger

BOM Option Table

P30 Board Con. RT9018A Thermal Protection

GPU PWR CTRL Option 1 (Default/ VDDR3 before VDDC)

GPU PWR CTRL Option 2 (VDDR3 after VDDR1)

Thermal Follow Chart

+VCCRTC +3V~+3.3V RTC POWER ALWAYS ALWAYS NTC

+15V +15V CHARGE PUMP POWER ALWAYS ALWAYS

+3V_S5 +3.3V LAN/BT/CIR POWER S5_ON S0-S5 CPU 3V/5 V

+5V +5V HDD/ODD/Codec/TP/CRT/HDMI POWER MAINON S0

+3V +3.3V PCH/GPU/Peripheral component POWER MAINON S0

+VGFX_AXG variation Internal GPU POWER GFX_ON S0

+1.5V +1.5V MINI CARD/NEW CARD POWER MAINON S0

+1.05V +1.05V PCH CORE POWER MAINON S0

+VCC_CORE variation CPU CORE POWER VRON S0

LCDVCC +3.3V LCD POWER LVDS_VDDEN S0

+5V_GPU +5V SWITCHABLE PWM IC POWER dGPU_PWR_EN# Discrete enable

+GPU_CORE +0.9V~+1.1V GPU CORE POWER +3V_D Discrete enable

+GPU_IO +0.9V~+1.1V GPU I/O POWER PG_GPUIO_EN Discrete enable

+1.5V_GPU +1.5V VRAM CORE POWER PG_1.5V_EN Discrete enable

+1.8V_GPU +1.8V GPU_CRE/LVDS/PLL POWER +1.5V_GPU Discrete enable

+1V +1V DP/PEG POWER PG_1V_EN Discrete enable

Quanta Computer Inc.

Date: Monday, March 14, 2011 Sheet 2 of 45

Quanta Computer Inc.

AUBURNDALE/CLARKSFIELD PROCESSOR (DMI,PEG,FDI) AUBURNDALE/CLARKSFIELD PROCESSOR (CLK,MISC,JTAG)

G18 D31 AT27 XDP_TRST# T71

JTAG & BPM

Processor pull-up JTAG MAPPING

XDP_TMS R135 *51_4 0_4

Scan Chain STUFF -> R469, R491, R507

R209 (Default) NO STUFF -> R489, R490

Quanta Computer Inc.

AUBURNDALE/CLARKSFIELD PROCESSOR (DDR3) U22D

<15> M_B_DQ[63:0] SB_CK[0] W8 M_B_CLK0 <15>

DDR SYSTEM MEMORY - B

M_A_DQ35 AK7 F8 M_A_DQS#1 M_B_DQ40 AK3 AR5 M_B_DQS#6

Channel A DQ[15,32,48,54], DM[5] Channel B DQ[16,18,36,42,56,57,60,61,62]

Quanta Computer Inc.

CPU Core Power U22F

VTT Rail Values are AUBURNDALE/CLARKSFIELD PROCESSOR (GRAPHICS POWER)

1.1V RAIL POWER

C285 330u/2V_7343 AC32 +1.05V AJ16 Y1

CPU CORE SUPPLY

PEG & DMI

VCC62 VTT1_52 VTT1_68

VCC88 VCC_SENSE VCCSENSE <30>

AUBURNDALE/CLARKSFIELD PROCESSOR (GND) AUBURNDALE/CLARKSFIELD PROCESSOR( RESERVED, CFG)

AT20 VSS1 VSS81 AE34 RSVD32 AJ13

AL20 VSS40 VSS120 W6 E21 VSS198 AJ29 CFG[15] RSVD_TP_59 E15

IBEX PEAK-M (DMI,FDI,GPIO) AC-coupling CAP place close to PCH

IBEX PEAK-M (LVDS,DDI)

Digital Display Interface

<27> ICH_RSMRST# C16 H7 SUSC# <27> BC46

PM_RI# F14 F6 PM_SLP_LAN# TP18

PCH Pull-high/low +3V_S5

PM_RI# R184 10K_4

RTC Circuitry C335