Avrasm

Basics
Directives
Expression
Instruction set
AVR assembler
Dr. György Schuster
OE-KVK-MAI
schuster.gyorgy@kvk.uni-obuda.hu
2013. október 9.
Dr. György Schuster AVR assembler

Basics
Directives
Expression
Instruction set
Assembly
Definition
An assembly language is a low-level programming language for a computer,
or other programmable device, in which there is a very strong (generally
one-to-one) correspondence between the language and the architecture’s
machine code instructions.

Basics
Directives
Expression
Instruction set
Assembly
Definition
Each assembly language is specific to a particular computer architecture.

Basics
Directives
Expression
Instruction set
Assembly
Definition
Each assembly language is specific to a particular computer architecture.
Assembler
Assembly language is converted into executable machine code by a utility
program referred to as an assembler.

Basics
Directives
Expression
Instruction set
Structure of an assembly line
Variations:
[label:] directive [operands] [Comment]

Basics
Directives
Expression
Instruction set
Variations:
[label:] instruction [operands] [Comment]

Basics
Directives
Expression
Instruction set
Variations:
Comment

Basics
Directives
Expression
Instruction set
Variations:
Comment
Empty line

Basics
Directives
Expression
Instruction set
Parts:
[label:] is an optional mark on the given line. Reason for its usage we want to
address this line i.e. as a jump aim.

Basics
Directives
Expression
Instruction set
Parts:
directive is a control command for assembler, which has special effect(s) on
the compiling procedure.

Basics
Directives
Expression
Instruction set
Parts:
[operands] is optional variable(s) for directive.

Basics
Directives
Expression
Instruction set
Parts:
[comment] is some optional remark or explanation to help follow the given
program.

Basics
Directives
Expression
Instruction set
Parts:
[comment] is some optional remark or explanation to help follow the given
program.
instruction is the mnemonic of the current assembly instruction.

Basics
Directives
Expression
Instruction set
Examples:
label: .equ v1=5 ;Set v1 to 5 (directive)

Basics
Directives
Expression
Instruction set
Examples:
loop: rjmp loop ;Infinite loop (instruction)

Basics
Directives
Expression
Instruction set
Examples:
loop: rjmp loop ;Infinite loop (instruction)
;End of this example (pure comment)

Basics
Directives
Expression
Instruction set
Define which device to assemble for

DEVICE
The DEVICE directive allows the user to tell the Assembler which device the code is to
be executed on.

Basics
Directives
Expression
Instruction set

DEVICE
be executed on.
If this directive is used, a warning is issued if an instruction not supported by the
specified device occurs in the code.

Basics
Directives
Expression
Instruction set

DEVICE
be executed on.
If the size of the Code Segment or EEPROM Segment is larger than supported by the
specified device, a warning is issued.

Basics
Directives
Expression
Instruction set

DEVICE
be executed on.
If the DEVICE directive is not used, it is assumed that all instructions are supported
and that there are no restrictions on memory sizes.

Basics
Directives
Expression
Instruction set

DEVICE
be executed on.
If the DEVICE directive is not used, it is assumed that all instructions are supported
and that there are no restrictions on memory sizes.
Example
.DEVICE AT90S1200 | AT90S2313

Basics
Directives
Expression
Instruction set
Segment definitions
Symbols:
CSEG The CSEG directive defines the start of a Code Segment. An Assembler file may
consist of several Code Segments, which are concatenated into one Code
Segment when assembled.

Basics
Directives
Expression
Instruction set
Segment definitions
Symbols:
The Code Segments have their own location counter which is a word counter.

Basics
Directives
Expression
Instruction set
Segment definitions
Symbols:
The directive does not take any parameters.

Basics
Directives
Expression
Instruction set
Segment definitions
Symbols:
DSEG The DSEG directive defines the start of a Data Segment. An Assembler file can
consist of several Data Segments, which are concatenated into one Data

Basics
Directives
Expression
Instruction set
Segment definitions
Symbols:

Basics
Directives
Expression
Instruction set
Segment definitions
Symbols:
ESEG The ESEG directive defines the start of an EEPROM Segment. An Assembler
file can consist of several EEPROM Segments, which are concatenated into one
EEPROM Segment when assembled.

Basics
Directives
Expression
Instruction set
Segment definitions
Symbols:
ESEG The ESEG directive defines the start of an EEPROM Segment. An Assembler
file can consist of several EEPROM Segments, which are concatenated into one
EEPROM Segment when assembled.

Basics
Directives
Expression
Instruction set
Set program origin

ORG
The ORG directive sets the location counter to an absolute value. The value to
set is given as a parameter.

Basics
Directives
Expression
Instruction set
Set program origin

ORG
If an ORG directive is given within a Data Segment, then it is the SRAM location
counter which is set.

Basics
Directives
Expression
Instruction set
Set program origin

ORG
If the directive is given within a Code Segment, then it is the Program memory

Basics
Directives
Expression
Instruction set
Set program origin

ORG
If the directive is given within an EEPROM Segment, then it is the EEPROM
location counter which is set.

Basics
Directives
Expression
Instruction set
Set program origin

ORG
It is possible to apply symbolic labels.

Basics
Directives
Expression
Instruction set
Set program origin

ORG
The ORG directive can also be used to place the
variables at specific locations in the SRAM.

Basics
Directives
Expression
Instruction set
Set program origin

ORG
variables at specific locations in the SRAM.
The ORG directive can also be used to place
constants at specific locations in the EEPROM
memory.

Basics
Directives
Expression
Instruction set
Set program origin

ORG
variables at specific locations in the SRAM. Example
The ORG directive can also be used to place
constants at specific locations in the EEPROM .ORG 0x100
memory.

Basics
Directives
Expression
Instruction set
Memory space allocation
DB
The DB directive reserves memory resources in the program memory or the EEPROM
memory. The DB directive must be placed in a Code Segment or an EEPROM
Segment.

Basics
Directives
Expression
Instruction set
DB
Segment.
In order to be able to refer to the reserved locations, the DB directive should be
preceded by a label.

Basics
Directives
Expression
Instruction set
DB
Segment.
The DB directive takes a list of expressions, and must contain at least one expression.
The expression list is a sequence of expressions, delimited by commas.

Basics
Directives
Expression
Instruction set
DB
Segment.
Each expression must evaluate to a number between -128 and 255. If the expression
evaluates to a negative number, the 8 bits two’s complement of the number will be
placed in the program memory or EEPROM memory location.

Basics
Directives
Expression
Instruction set
DB
Segment.
Each expression must evaluate to a number between -128 and 255. If the expression
placed in the program memory or EEPROM memory location.

Basics
Directives
Expression
Instruction set
DB
If the DB directive is used in a Code Segment and the expressionlist contains more
than one expression, the expressions are packed so that two bytes are placed in each
program memory word.

Basics
Directives
Expression
Instruction set
DB
If the expressionlist contains an odd number of expressions, the last expression will be
placed in a program memory word of its own, even if the next line in the assembly code
contains a DB directive.

Basics
Directives
Expression
Instruction set
DB
If the expressionlist contains an odd number of expressions, the last expression will be
placed in a program memory word of its own, even if the next line in the assembly code
contains a DB directive.
Example
consts: .DB 0, 255, 0b01010101, -128, 0xaa

Basics
Directives
Expression
Instruction set

DW
The DW directive reserves memory resources in the program memory or EEPROM
memory. In order to be able to refer to the reserved locations, the DW directive should
be preceded by a label.

Basics
Directives
Expression
Instruction set

DW
The DW directive takes a list of expressions, and must contain at least one expression.
The DB directive must be placed in a Code Segment or an EEPROM Segment.

Basics
Directives
Expression
Instruction set

DW
The expression list is a sequence of expressions, delimited by commas. Each expres-
sion must evaluate to a number between -32768 and 65535. If the expression
placed in the program memory location.

Basics
Directives
Expression
Instruction set

DW
The expression list is a sequence of expressions, delimited by commas. Each expres-
sion must evaluate to a number between -32768 and 65535. If the expression
placed in the program memory location.
Example
consts: .DW 0,0xffff,0b1001110001010101,-32768,65535

Basics
Directives
Expression
Instruction set
BYTE
The BYTE directive reserves memory resources in the SRAM. In order to be able to
refer to the reserved location, the BYTE directive should be preceded by a label.

Basics
Directives
Expression
Instruction set
BYTE
The directive takes one parameter, which is the number of bytes to reserve. The
directive can only be used within a Data Segment.

Basics
Directives
Expression
Instruction set
BYTE
Note that a parameter must be given. The allocated bytes are not initialized.

Basics
Directives
Expression
Instruction set
BYTE
Note that a parameter must be given. The allocated bytes are not initialized.
Example
var1: .BYTE 240

Basics
Directives
Expression
Instruction set
Set a symbol equal to an expression

Instructions:
EQU The EQU directive assigns a value to a label.

Basics
Directives
Expression
Instruction set

Instructions:
This label can then be used in later expressions.

Basics
Directives
Expression
Instruction set

Instructions:
A label assigned to a value by the EQU directive is a constant and can not be
changed or redefined.

Basics
Directives
Expression
Instruction set

Instructions:
Example:
.EQU setup = 0x23

Basics
Directives
Expression
Instruction set

Instructions:
Example:
.EQU setup = 0x23
SET The SET directive assigns a value to a label.

Basics
Directives
Expression
Instruction set

Instructions:
Example:
.EQU setup = 0x23

Basics
Directives
Expression
Instruction set

Instructions:
Example:
.EQU setup = 0x23
A label assigned to a value by the SET directive can be changed later in the
program.

Basics
Directives
Expression
Instruction set

Instructions:
Example:
.EQU setup = 0x23
A label assigned to a value by the SET directive can be changed later in the
program.
Example:
.SET setup = 0x23

Basics
Directives
Expression
Instruction set
Set a symbolic name on a register
DEF
The DEF directive allows the registers to be referred to through symbols.

Basics
Directives
Expression
Instruction set
DEF
A defined symbol can be used in the rest of the program to refer to the register it is
assigned to.

Basics
Directives
Expression
Instruction set
DEF
assigned to.
A register can have several symbolic names attached to it.

Basics
Directives
Expression
Instruction set
DEF
assigned to.
A symbol can be redefined later in the program.

Basics
Directives
Expression
Instruction set
DEF
assigned to.
A symbol can be redefined later in the program.
Example
.DEF temp = R16

Basics
Directives
Expression
Instruction set
Include another file
INCLUDE
The INCLUDE directive tells the Assembler to start reading from a specified file.

Basics
Directives
Expression
Instruction set
INCLUDE
The Assembler then assembles the specified file until end of file (EOF) or an EXIT
directive is encountered.

Basics
Directives
Expression
Instruction set
INCLUDE
An included file may itself contain INCLUDE directives.

Basics
Directives
Expression
Instruction set
INCLUDE
An included file may itself contain INCLUDE directives.
Example
.INCLUDE "parms.inc"

Basics
Directives
Expression
Instruction set
Begin and end macro

MACRO
The MACRO directive tells the Assembler that this is the start of a macro.

Basics
Directives
Expression
Instruction set
Begin and end macro

MACRO
The MACRO directive takes the macro name as parameter.

Basics
Directives
Expression
Instruction set
Begin and end macro

MACRO
A macro can take up to 10 parameters. These parameters are referred to as @0-@9
within the macro definition.

Basics
Directives
Expression
Instruction set
Begin and end macro

MACRO
ENDMACRO
The ENDMACRO directive defines the end of a macro definition. The directive does
not take any parameters.

Basics
Directives
Expression
Instruction set
Begin and end macro

MACRO
ENDMACRO
The ENDMACRO directive defines the end of a macro definition. The directive does
not take any parameters.
Example
.MACRO SUBI16 ; Start macro definition

subi r16,low(@0) ; Subtract low byte
sbci r17,high(@0) ; Subtract high byte
.ENDMACRO

Basics
Directives
Expression
Instruction set
Turn the listfile generation on and off

LIST
The LIST directive tells the Assembler to turn listfile generation on.

Basics
Directives
Expression
Instruction set

LIST
The Assembler generates a listfile which is a combination of assembly source code,
addresses and opcodes.

Basics
Directives
Expression
Instruction set

LIST
Listfile generation is turned on by default. The directive can also be used together with
the NOLIST directive in order to only generate listfile of selected parts of an assembly
source file.

Basics
Directives
Expression
Instruction set

LIST
source file.
NOLIST
The NOLIST directive tells the Assembler to turn listfile generation off.

Basics
Directives
Expression
Instruction set

LIST
source file.
NOLIST
The NOLIST directive tells the Assembler to turn listfile generation off.
Example
.NOLIST ;Disable listfile generation

.INCLUDE "macro.inc" ;The included files are not
.INCLUDE "const.def" ;be shown in the listfile
.LIST ;Reenable listfile generation
Basics
Directives
Expression
Instruction set
Turn macro expansion onto listfile
LISTMAC
The LISTMAC directive tells the Assembler that when a macro is called, the expansion
of the macro is to be shown on the listfile generated by the Assembler.

Basics
Directives
Expression
Instruction set
LISTMAC
The default is that only the macro-call with parameters is shown in the listfile.

Basics
Directives
Expression
Instruction set
LISTMAC
The default is that only the macro-call with parameters is shown in the listfile.
Example
.LISTMAC ;Enable macro expansion

MACX ;Call macro, show expansion

Basics
Directives
Expression
Instruction set
Operands
Numbers
a Decimal: 10, 255, -30,

Basics
Directives
Expression
Instruction set
Operands
Numbers
a Decimal: 10, 255, -30,
b Hexadecimal: 0x0a, 0x0A, $0a, 0xff, $ff,

Basics
Directives
Expression
Instruction set
Operands
Numbers
a Decimal: 10, 255, -30,
c Binary: 0b00001010,

Basics
Directives
Expression
Instruction set
Operands
Numbers
a Decimal: 10, 255, -30,
c Binary: 0b00001010,
d Program counter: PC

Basics
Directives
Expression
Instruction set
Functions
Parts
LOW(expression) returns the low byte of an expression,

Basics
Directives
Expression
Instruction set
Functions
Parts
HIGH(expression) returns the second byte of an expression,

Basics
Directives
Expression
Instruction set
Functions
Parts
BYTE2(expression) is the same function as HIGH,

Basics
Directives
Expression
Instruction set
Functions
Parts
BYTE3(expression) returns the third byte of an expression,

Basics
Directives
Expression
Instruction set
Functions
Parts
BYTE4(expression) returns the fourth byte of an expression,

Basics
Directives
Expression
Instruction set
Functions
Parts
LWRD(expression) returns bits 0-15 of an expression,

Basics
Directives
Expression
Instruction set
Functions
Parts
HWRD(expression) returns bits 16-31 of an expression,

Basics
Directives
Expression
Instruction set
Functions
Parts
PAGE(expression) returns bits 16-21 of an expression,

Basics
Directives
Expression
Instruction set
Functions
Parts
EXP2(expression) returns 2expression ,

Basics
Directives
Expression
Instruction set
Functions
Parts
EXP2(expression) returns 2expression ,
LOG2(expression) returns the integer part of log2(expression)

Basics
Directives
Expression
Instruction set
Operators
TRUE - FALSE
In AVR8 Assembler the:
TRUE value is ’1’,

Basics
Directives
Expression
Instruction set
Operators
TRUE - FALSE
FALSE value is ’0’.

Basics
Directives
Expression
Instruction set
Operators
TRUE - FALSE
Operators
AVR8 Assembler supports all the operators used in ANSI C language exept for special
group ones.

Basics
Directives
Expression
Instruction set
Operators
TRUE - FALSE
Operators
AVR8 Assembler supports all the operators used in ANSI C language exept for special
group ones.

Notation of operands
Basics The Program and Data Addressing Modes
Directives Data transfer instructions
Expression Arithmetic instructions
Instruction set Logic instructions
Bit and bit-test instructions
Branch Instruction
Notation of flags
SREG: Status register (contains flag bits)

Branch Instruction
Notation of flags

C: Carry flag

Branch Instruction
Notation of flags

C: Carry flag
Z: Zero flag

Branch Instruction
Notation of flags

C: Carry flag
Z: Zero flag
N: Negative flag

Branch Instruction
Notation of flags

C: Carry flag
Z: Zero flag
N: Negative flag
V: Twos complement overflow indicator

Branch Instruction
Notation of flags

C: Carry flag
Z: Zero flag
N: Negative flag
S: N ⊕ V signed test

Branch Instruction
Notation of flags

C: Carry flag
Z: Zero flag
N: Negative flag
H: Half Carry Flag

Branch Instruction
Notation of flags

C: Carry flag
Z: Zero flag
N: Negative flag
H: Half Carry Flag
T: Transfer bit used by BLD and BST instructions

Branch Instruction
Notation of flags

C: Carry flag
Z: Zero flag
N: Negative flag
H: Half Carry Flag
T: Transfer bit used by BLD and BST instructions
I: General Interrupt Enable flag

Branch Instruction
Rd: R0-R31 or R16-R31 (depending on instruction)

Branch Instruction

Rr: R0-R31

Branch Instruction

Rr: R0-R31
b: Constant (0-7), can be a constant expression

Branch Instruction

Rr: R0-R31
s: Constant (0-7), can be a constant expression

Branch Instruction

Rr: R0-R31
P: Constant (0-31/63), can be a constant expression

Branch Instruction

Rr: R0-R31
K: Constant (0-255), can be a constant expression

Branch Instruction

Rr: R0-R31
k: Constant, value range depending on instruction.
Can be a constant expression.

Branch Instruction

Rr: R0-R31
k: Constant, value range depending on instruction.
Can be a constant expression.
q: Constant (0-63), can be a constant expression

Branch Instruction
The Program and Data Addressing Modes

Direct Single Register Adrressing
Register file 0
15 4 0
OP Rd
31

Branch Instruction

Direct Register Addressing, Two Registers
Register file 0
15 9 54 0
OP Rr Rd
31

Branch Instruction

I/O Direct Addressing
I/O memory 0
15 5 0
OP Rd/Rr A
63

Branch Instruction

Direct Data Addressing
Data space 0x0000
31 19 16
OP Rr/Rd
Data address
15 0
RAMEND

Branch Instruction

Data Indirect with Displacement
Data space 0x0000
15 0
s
OP
15 10 5 0
RAMEND

Branch Instruction

Data Indirect Addressing
Data space 0x0000
15 0
X, Y or Z regiszter ,
RAMEND

Branch Instruction

Data Indirect Addressing with Pre-decrement
Data space 0x0000
15 0
X, Y or Z regiszter
RAMEND

Branch Instruction

Data Indirect Addressing with Post-increment
Data space 0x0000
15 0
X, Y or Z regiszter
RAMEND

Branch Instruction

Program Memory Constant Addressing
0x0000
15 0
Z regiszter
LSB
FLASHEND

Branch Instruction

Program Memory Addressing with Post-increment
15 0 0x0000
Z regiszter
LSB
FLASHEND

Branch Instruction

Direct Program Memory Addressing
31 16 0x0000
OP 6 MSB
16 LSBs
15 0
15 0
PC
FLASHEND
Used by JMP and CALL instructions.

Branch Instruction

Indirect Program Memory Addressing
15 0 0x0000
Z regiszter
15 0
PC
FLASHEND
Used by IJMP and ICALL instructions.

Branch Instruction

Relative Program Memory Addressing
15 0 0x0000
PC
15 12 11 0
OP k
FLASHEND
Used by RJMP and RCALL instructions. k∈ [−2048, 2047].

Branch Instruction
Data transfer instructions
MOV
This instruction makes a copy of one register into another.

Branch Instruction
MOV
The source register Rr is left unchanged while the destination register Rd is loaded
with a copy of Rr.

Branch Instruction
MOV
The source register Rr is left unchanged while the destination register Rd is loaded
with a copy of Rr.
Operation: Rd←Rr
Syntax: MOV Rd,Rr
Operands: 0≤d≤31, 0≤r≤31
Flags: no effects on flags
Words: 1
Cycles: 1

Branch Instruction

MOVW
This instruction makes a copy of one register pair into another register pair.

Branch Instruction

MOVW
The source register pair Rr+1:Rr is left unchanged, while the destination register pair
Rd+1:Rd is loaded with a copy of Rr + 1:Rr.

Branch Instruction

MOVW
This instruction is not available in all devices.
Refer to the device specific instruction set summary.

Branch Instruction

MOVW
Operation: Rd+1:Rd←Rr+1:Rr
Syntax: MOVW Rd+1:Rd,Rr+1:Rr
Operands: d∈{0,2,· · · ,28,30} r∈{0,2,· · · ,28,30}
Example: MOVW R31:R30,R17:R16
Words: 1
Cycles: 1

Branch Instruction
LDI
Loads an 8 bit constant directly to register 16 to 31.

Branch Instruction
LDI
Loads an 8 bit constant directly to register 16 to 31.
Operation: Rd←k
Syntax: LDI Rd,k
Operands: 16≤d≤31, 0≤k≤255
Words: 1
Cycles: 1

Branch Instruction
LDS
Loads one byte from the data space to a register.

Branch Instruction
LDS
For parts with SRAM, the data space consists of the Register File, I/O memory and
internal SRAM (and external SRAM if applicable).

Branch Instruction
LDS
Operation: Rd←(k)
Syntax: LDS Rd,k
Operands: 0≤d≤31, 0≤k≤65535
Words: 2
Cycles: 2

Branch Instruction
LD, LDD
Loads one byte indirect with or without displacement from the data space to a register.

Branch Instruction
LD, LDD

Branch Instruction
LD, LDD
For parts without SRAM, the data space consists of the Register File only.

Branch Instruction
LD, LDD
The data location is pointed to by the Z (16 bits) Pointer Register in the Register File.
Memory access is limited to the current data segment of 64K bytes.

Branch Instruction

LD, LDD
Operation: Rd←(Z)
Rd←(Z++) ;postincrement 0≤q≤31
Rd←(--Z) ;predecrement 0≤q≤31
Rd←(Z+q) ;0≤d≤31, 0≤q≤63
Syntax: LD Rd,Z
LD Rd,Z+
LD Rd,-Z
LDD Rd,Z+q
Operands: 0≤d≤31, 0≤k≤65535
Words: 1
Cycles: 2

Branch Instruction

STS
Stores one byte from a Register to the data space.

Branch Instruction

STS

Branch Instruction

STS

Branch Instruction

STS
Operation: (k)←Rr
Syntax: STS k,Rr
Operands: 0≤r≤31, 0≤k≤65535
Words: 2
Cycles: 2

Branch Instruction

ST, STD
Stores one byte indirect with or without displacement from a register to data space.

Branch Instruction

ST, STD
internal SRAM (and external SRAM if applicable). For parts without SRAM, the data
space consists of the Register File only.

Branch Instruction

ST, STD

Branch Instruction

ST, STD
The Z-pointer Register can either be left unchanged by the operation, or it can be
post-incremented or pre-decremented.

Branch Instruction

ST, STD
These features are especially suited for Stack Pointer usage of the Z-pointer Register,
however because the Z-pointer Register can be used for indirect subroutine calls,
indirect jumps and table lookup, it is often more convenient to use the X or Y-pointer as
a dedicated Stack Pointer.

Branch Instruction

ST, STD
Not all variants of this instruction is available in all devices. Refer to the device specific
instruction set summary.

Branch Instruction

ST, STD
Not all variants of this instruction is available in all devices. Refer to the device specific
instruction set summary.
*
Branch Instruction

ST, STD
Operation: (Z) ← Rr
(Z++) ← Rr ;post-increment 0≤q≤31
(--Z) ← Rr ;pre-decrement 0≤q≤31
(Z+q) ← Rr ; 0≤r≤31, 0≤q≤63
Syntax: ST Z,Rr
ST Z+,Rr
ST -Z,Rr
STD Z+q,Rr
Operands: 0≤d≤31, 0≤k≤65535
Words: 1
Cycles: 2

Branch Instruction

LPM
Loads one byte pointed to by the Z-register into the destination register Rd.

Branch Instruction

LPM
This instruction features a 100% space effective constant initialization or constant data
fetch.

Branch Instruction

LPM
fetch.
The Program memory is organized in 16-bit words while the Z-pointer is a byte address.

Branch Instruction

LPM
fetch.
Thus, the least significant bit of the Z-pointer selects either low byte (ZLSB = 0) or high
byte (ZLSB = 1).

Branch Instruction

LPM
fetch.
byte (ZLSB = 1).
This instruction can address the first 64K bytes (32K words) of Program memory.

Branch Instruction

LPM
fetch.
byte (ZLSB = 1).
incremented.

Branch Instruction

LPM
fetch.
byte (ZLSB = 1).
incremented.
Devices with Self-Programming capability can use the LPM instruction to read the Fuse
and Lock bit values.

Branch Instruction

LPM
fetch.
byte (ZLSB = 1).
incremented.
Not all variants of the LPM instruction are available in all devices.

Branch Instruction

LPM
fetch.
byte (ZLSB = 1).
incremented.
Not all variants of the LPM instruction are available in all devices.
*
Branch Instruction

LPM
Operation: R0 ← (Z)
Rd ← (Z) ;0≤d≤31
Rd ← (Z++) ;0≤d≤31
Syntax: LPM ;R0
LPM Rd,Z
LMP Rd,Z+
Operands: 0≤d≤31, 0≤k≤65535
Words: 1
Cycles: 3

Branch Instruction
IN
Loads data from the I/O Space (Ports, Timers, Configuration Registers etc.) into
register Rd in the Register File.

Branch Instruction
IN
Loads data from the I/O Space (Ports, Timers, Configuration Registers etc.) into
register Rd in the Register File.
Operation: Rd←I/O(A)
Syntax: IN Rd,A
Operands: 0≤d≤31, 0≤A≤63
Words: 1
Cycles: 1

Branch Instruction
OUT
Stores data from register Rr in the Register File to I/O Space (Ports, Timers,
Configuration Registers etc.).

Branch Instruction
OUT
Stores data from register Rr in the Register File to I/O Space (Ports, Timers,
Configuration Registers etc.).
Operation: I/O(A)←Rr
Syntax: OUT A,Rr
Operands: 0≤r≤31, 0≤A≤63
Words: 1
Cycles: 1

Branch Instruction

PUSH
This instruction stores the contents of register Rr on the STACK.

Branch Instruction

PUSH
The Stack Pointer is post-decremented by 1 after the PUSH.

Branch Instruction

PUSH
This instruction is not available in all devices. Refer to the device specific instruction set
summary.

Branch Instruction

PUSH
This instruction is not available in all devices. Refer to the device specific instruction set
summary.
Operation: STACK ← Rr, SP--

Syntax: PUSH Rr
Operands: 0 ≤ r ≤ 31
Words: 1
Cycles: 2

Branch Instruction
POP
This instruction loads register Rd with a byte from the STACK. The Stack Pointer is
pre-incremented by 1 before the POP.

Branch Instruction
POP
This instruction loads register Rd with a byte from the STACK. The Stack Pointer is
pre-incremented by 1 before the POP.
Operation: Rd,←STACK ++SP

Syntax: POP Rd
Operands: 0 ≤ d ≤ 31
Words: 1
Cycles: 2

Branch Instruction
CLR
Clears a register. This instruction performs an Exclusive OR between a register and
itself. This will clear all bits in the register.

Branch Instruction
CLR
Clears a register. This instruction performs an Exclusive OR between a register and
itself. This will clear all bits in the register.
Operation: Rd ← Rd⊕Rd
Syntax: CLR Rd
Operands: 0≤d≤31
Flags: Z=1
Words: 1
Cycles: 1

Branch Instruction
SER
Loads $FF directly to register Rd.

Branch Instruction
SER
Loads $FF directly to register Rd.
Operation: Rd ← $FF
Syntax: SER Rd
Flags: No effects on flags
Words: 1
Cycles: 1

Branch Instruction
Arithmetic instructions
ADD
Adds two registers without the C Flag and places the result in the destination register
Rd.
Operation: Rd,←Rd+Rr
Syntax: ADD Rd,Rr
Operands: 0 ≤ d ≤ 31 0 ≤ r ≤ 31
Flags: H, S, V, N, Z, C
Words: 1
Cycles: 1

Branch Instruction
ADC
Adds two registers with the C Flag and places the result in the destination register Rd.
Operation: Rd,←Rd+Rr+C
Syntax: ADC Rd,Rr
Operands: 0 ≤ d ≤ 31 0 ≤ r ≤ 31
Words: 1
Cycles: 1

Branch Instruction
ADIW
Adds an immediate value (0 - 63) to a register pair and places the result in the register
pair.
This instruction operates on the upper four register pairs, and is well suited for
operations on the pointer registers. This instruction is not available in all devices.
Operation: Rd+1:Rd,←Rd+1:Rd+k
Syntax: ADIW Rd+1,Rd,k
Operands: d ∈ 24,26,28,30 0 ≤ k ≤ 63
Flags: S, V, N, Z, C
Words: 1
Cycles: 2

Branch Instruction
SUB
Subtracts two registers and places the result in the destination register Rd.
Operation: Rd,←Rd-Rr
Syntax: SUB Rd,Rr
Operands: 0 ≤ d ≤ 31 0 ≤ r ≤ 31
Words: 1
Cycles: 1

Branch Instruction
SUBI
Subtracts a register and a constant and places the result in the destination register Rd.
This instruction is working on Register R16 to R31 and is very well suited for
operations on the X, Y and Z-pointers.
Operation: Rd←Rd-k
Syntax: SUBI Rd,k
Operands: 16≤d≤31, 0≤k≤255
Words: 1
Cycles: 1

Branch Instruction
SBC
Subtracts two registers and subtracts with the C Flag and places the result in the
destination register Rd.
Operation: Rd,←Rd-Rr-C
Syntax: SBC Rd,Rr
Operands: 0 ≤ d ≤ 31 0 ≤ r ≤ 31

Branch Instruction
SBCI
Subtracts a constant from a register and subtracts with the C Flag and places the result
in the destination register Rd.
Operation: Rd,←Rd-K-C
Syntax: SBCI Rd,K
Operands: 0 ≤ d ≤ 31 0 ≤ K ≤ 255

Branch Instruction
SBIW
Subtracts an immediate value (0-63) from a register pair and places the result in the
register pair. This instruction operates on the upper four register pairs, and is well
suited for operations on the Pointer Registers.
Operation: Rd+1:Rd,←Rd+1:Rd-k
Syntax: SBIW Rd+1,Rd,k
Operands: d ∈ 24,26,28,30 0 ≤ k ≤ 63
Words: 1
Cycles: 2

Branch Instruction
NEG
Replaces the contents of register Rd with its two’s complement; the value $80 is left
unchanged.
Operation: Rd ← 0-Rd
Syntax: NEG Rd
Words: 1
Cycles: 1

Branch Instruction
INC
Adds one -1- to the contents of register Rd and places the result in the destination
register Rd.
The C Flag in SREG is not affected by the operation, thus allowing the INC instruction
to be used on a loop counter in multiple-precision computations.
When operating on unsigned numbers, only BREQ and BRNE branches can be
expected to perform consistently. When operating on twos complement values, all
signed branches are available.
Operation: Rd++
Syntax: INC Rd
Words: 1
Cycles: 1

Branch Instruction
DEC
Subtracts one -1- from the contents of register Rd and places the result in the
destination register Rd.
The C Flag in SREG is not affected by the operation, thus allowing the DEC instruction
to be used on a loop counter in multiple-precision computations.
When operating on unsigned values, only BREQ and BRNE branches can be expected
to perform consistently.
When operating on two’s complement values, all signed branches are available.
Operation: Rd--
Syntax: DEC Rd
Words: 1
Cycles: 1

Branch Instruction
MUL
This instruction performs 8-bit 8-bit 16-bit unsigned multiplication.
The multiplicand Rd and the multiplier Rr are two registers containing unsigned
numbers.
The 16-bit unsigned product is placed in R1 (high byte) and R0 (low byte).
Note that if the multiplicand or the multiplier is selected from R0 or R1 the result will
overwrite those after multiplication.
Operation: R1:R0 ← Rd x Rr
Syntax: MUL Rd,Rr
Operands: 0≤d≤31 0≤r≤31
Flags: Z, C
Words: 1
Cycles: 2
Branch Instruction
MULS
This instruction performs 8-bit 8-bit 16-bit signed multiplication.
The multiplicand Rd and the multiplier Rr are two registers containing signed numbers.
The 16-bit signed product is placed in R1 (high byte) and R0 (low byte).
Syntax: MULS Rd,Rr
Flags: Z, C
Words: 1
Cycles: 2

Branch Instruction
MULSU
This instruction performs 8-bit 8-bit 16-bit multiplication of a signed and an unsigned
number.
The multiplicand Rd and the multiplier Rr are two registers.
The multiplicand Rd is a signed number, and the multiplier Rr is unsigned.
The 16-bit signed product is placed in R1 (high byte) and R0 (low byte).
Syntax: MULSU Rd,Rr
Flags: Z, C
Words: 1
Cycles: 2

Branch Instruction
FMULS
This instruction performs 8-bit 8-bit 16-bit signed multiplication and shifts the result
one bit left.
Let (N.Q) denote a fractional number with N binary digits left of the radix point, and Q
binary digits right of the radix point.
A multiplication between two numbers in the formats (N1.Q1) and (N2.Q2) results in
the format ((N1+N2).(Q1+Q2)).
A left shift is required for the high byte of the product to be in the same format as the
inputs. The FMULS instruction incorporates the shift operation in the same number of
cycles as MULS.
The multiplicand Rd and the multiplier Rr are two registers containing signed fractional
numbers where the implicit radix point lies between bit 6 and bit 7.
The 16-bit signed fractional product with the implicit radix point between bit 14 and bit
15 is placed in R1 (high byte) and R0 (low byte).
Note that when multiplying 0x80 (-1) with 0x80 (-1), the result of the shift operation is
0x8000 (-1). The shift operation thus gives a twos complement overflow. This must be
checked and handled by software.
Refer to the device specific instruction
Dr. Gy set summary.
örgy Schuster AVR assembler
Branch Instruction
FMULS
Syntax: FMULS Rd,Rr
Flags: Z, C
Words: 1
Cycles: 2

Branch Instruction
FMULSU
This instruction performs 8-bit 8-bit 16-bit signed multiplication and shifts the result
one bit left.
Let (N.Q) denote a fractional number with N binary digits left of the radix point, and Q
binary digits right of the radix point.
A multiplication between two numbers in the formats (N1.Q1) and (N2.Q2) results in
the format ((N1+N2).(Q1+Q2)).
A left shift is required for the high byte of the product to be in the same format as the
inputs. The FMULSU instruction incorporates the shift operation in the same number of
cycles as MULSU.
The MSB of the multiplication before shifting must be taken into account, and is found
in the carry bit.
The multiplicand Rd and the multiplier Rr are two registers containing fractional
numbers where the implicit radix point lies between bit 6 and bit 7. The multiplicand Rd
is a signed fractional number, and the multiplier Rr is an unsigned fractional number.
The 16-bit signed fractional product with the implicit radix point between bit 14 and bit
15 is placed in R1 (high byte) and R0 (low byte).
Refer to the device specific instruction
Dr. Gy set summary.
örgy Schuster AVR assembler
Branch Instruction
FMULSU
Syntax: FMULSU Rd,Rr
Flags: Z, C
Words: 1
Cycles: 2

Branch Instruction
CP
This instruction performs a compare between two registers Rd and Rr. None of the
registers are changed. All conditional branches can be used after this instruction.
Operation: Rd-Rr
Syntax: CP Rd,Rr
Operands: 0 ≤ d ≤ 31 0 ≤ r ≤ 31
Words: 1
Cycles: 1

Branch Instruction
CPI
This instruction performs a compare between register Rd and a constant. The register
is not changed. All conditional branches can be used after this instruction.
Operation: Rd-K
Syntax: CPI Rd,K
Operands: 0 ≤ d ≤ 31 0 ≤ K ≤ 255
Words: 1
Cycles: 1

Branch Instruction
CPC
This instruction performs a compare between two registers Rd and Rr and also takes
into account the previous carry. None of the registers are changed. All conditional
branches can be used after this instruction.
Operation: Rd-Rr-C
Syntax: CPC Rd,Rr
Operands: 0 ≤ d ≤ 31 0 ≤ r ≤ 31

Branch Instruction
Logic instructions
AND
Performs the logical AND between the contents of register Rd and register Rr and
places the result in the destination register Rd.
Operation: Rd ← Rd ∧ Rr
Syntax: AND Rd,Rr
Flags: S, N, Z
Words: 1
Cycles: 1

Branch Instruction
Logic instructions
ANDI
Performs the logical AND between the contents of register Rd and a constant and
Operation: Rd ← Rd ∧ k
Syntax: ANDI Rd,k
Operands: 0≤d≤31 0≤k≤255
Flags: S, N, Z
Words: 1
Cycles: 1

Branch Instruction
Logic instructions
OR
Performs the logical OR between the contents of register Rd and register Rr and
Operation: Rd ← Rd ∨ Rr
Syntax: OR Rd,Rr
Flags: S, N, Z
Words: 1
Cycles: 1

Branch Instruction
Logic instructions
ORI
Performs the logical OR between the contents of register Rd and a constant and places
the result in the destination register Rd.
Operation: Rd ← Rd ∨ k
Syntax: ANDI Rd,k
Operands: 16≤d≤31 0≤k≤255
Flags: S, N, Z
Words: 1
Cycles: 1

Branch Instruction
Logic instructions
EOR
Performs the logical EOR between the contents of register Rd and register Rr and
Operation: Rd ← Rd ⊕ Rr
Syntax: EOR Rd,Rr
Flags: S, N, Z
Words: 1
Cycles: 1

Branch Instruction
Logic instructions
COM
This instruction performs a Ones Complement of register Rd.
Operation: Rd ← ¬Rd
Syntax: COM Rd
Flags: S, N, Z
Words: 1
Cycles: 1

Branch Instruction

LSL
Shifts all bits in Rd one place to the left.
Bit 0 is cleared. Bit 7 is loaded into the C Flag of the SREG.
This operation effectively multiplies signed and unsigned values by two.
Operation: C ← Rd(7) · · · Rd(n+1) ← Rd(n) ← Rd(0) ← 0

Syntax: LSL Rd
Words: 1
Cycles: 1

Branch Instruction

LSR
Shifts all bits in Rd one place to the right.
Bit 7 is cleared. Bit 0 is loaded into the C Flag of the SREG.
This operation effectively divides an unsigned value by two.
The C Flag can be used to round the result.
Operation: 0 → Rd(7) · · · Rd(n+1) → Rd(n) → Rd(0) → C

Syntax: LSR Rd
Words: 1
Cycles: 1

Branch Instruction

ROL
Shifts all bits in Rd one place to the left. The C Flag is shifted into bit 0 of Rd. Bit 7 is
shifted into the C Flag.
This operation, combined with LSL, effectively multiplies multi-byte signed and
unsigned values by two.
Operation: C ← Rd(7) · · · Rd(n+1) ← Rd(n) ← Rd(0) ← C

Syntax: ROL Rd
Words: 1
Cycles: 1

Branch Instruction

ROR
Shifts all bits in Rd one place to the right.
The C Flag is shifted into bit 7 of Rd. Bit 0 is shifted into the C Flag.
This operation, combined with ASR, effectively divides multi-byte signed values by two.
Combined with LSR it effectively divides multibyte unsigned values by two.
The Carry Flag can be used to round the result.
Operation: C → Rd(7) · · · Rd(n+1) → Rd(n) → Rd(0) → C

Syntax: ROR Rd
Words: 1
Cycles: 1

Branch Instruction

ASR
Shifts all bits in Rd one place to the right. Bit 7 is held constant. Bit 0 is loaded into the
C Flag of the SREG.
This operation effectively divides a signed value by two without changing its sign.
The Carry Flag can be used to round the result.
Operation: Rd(7) → Rd(7) · · · Rd(n+1) → Rd(n) → Rd(0) → C

Syntax: ASR Rd
Words: 1
Cycles: 1

Branch Instruction
SWAP
Swaps high and low nibbles in a register.
Operation: Rd(7:4)⇄Rd(3:0)
Syntax: SWAP Rd
Words: 1
Cycles: 1

Branch Instruction
BSET
Sets a single Flag or bit in SREG.
Operation: SREG(s)←1
Syntax: BSET s
Operands: 0≤s≤7
Flags: I, T, H, S, V, N, C, Z just the addressed one, the others
remain unchanged
Words: 1
Cycles: 1

Branch Instruction
BCLR
Clears a single Flag in SREG.
Operation: SREG(s)←0
Syntax: BCLR s
Operands: 0≤s≤7
Flags: I, T, H, S, V, N, C, Z just the addressed one, the others
remain unchanged
Words: 1
Cycles: 1

Branch Instruction
SBI
Sets a specified bit in an I/O Register.
This instruction operates on the lower 32 I/O Registers addresses 0-31.
Operation: IO(A,b)←1
Syntax: SBI A,b
Operands: 0≤A≤31, 0≤b≤7
Words: 1
Cycles: 1

Branch Instruction
CBI
Clears a specified bit in an I/O Register.
This instruction operates on the lower 32 I/O Registers addresses 0-31.
Operation: IO(A,b)←0
Syntax: CBI A,b
Operands: 0≤A≤31, 0≤b≤7
Words: 1
Cycles: 1

Branch Instruction
BST
Stores bit b from Rd to the T Flag in SREG (Status Register).
Operation: T←Rd(b)
Syntax: BST Rd,b
Operands: 0≤Rd≤31, 0≤b≤7
Flags: T
Words: 1
Cycles: 1

Branch Instruction
BLD
Copies the T Flag in the SREG (Status Register) to bit b in register Rd.
Operation: Rd(b)←T
Syntax: BLD Rd,b
Operands: 0≤Rd≤31, 0≤b≤7
Flags: no effects on the flags
Words: 1
Cycles: 1

Branch Instruction
SEC CLC
Sets the Carry Flag (C) in SREG (Status Clears the Carry Flag (C) in SREG (Status
Register). Register).
Operation: C←1 Operation: C←0

Syntax: SEC Syntax: CLC
Operands: none Operands: none
Flags: C Flags: C
Words: 1 Words: 1
Cycles: 1 Cycles: 1

Branch Instruction
SEN CLN
Sets the Negative Flag (N) in SREG Clears the Negative Flag (N) in SREG
(Status Register). (Status Register).
Operation: N←1 Operation: C←0

Syntax: SEN Syntax: CLN
Flags: N Flags: N
Words: 1 Words: 1
Cycles: 1 Cycles: 1

Branch Instruction
SEZ CLZ
Sets the Zero Flag (Z) in SREG (Status Clears the Zero Flag (Z) in SREG (Status
Operation: Z←1 Operation: Z←0

Syntax: SEZ Syntax: CLZ
Flags: Z Flags: Z
Words: 1 Words: 1
Cycles: 1 Cycles: 1

Branch Instruction
SEI CLI
Sets the Interrupt Enable Flag (I) in SREG Clears the Interrupt Enable Flag (I) in
(Status Register). SREG (Status Register).
Operation: I←1 Operation: I←0

Syntax: SEI Syntax: CLI
Flags: I Flags: I
Words: 1 Words: 1
Cycles: 1 Cycles: 1

Branch Instruction
SES CLS
Sets the Signed Flag (S) in SREG (Status Clears the Signed Flag (S) in SREG
Register). (Status Register).
Operation: S←1 Operation: S←0

Syntax: SES Syntax: CLS
Flags: S Flags: S
Words: 1 Words: 1
Cycles: 1 Cycles: 1

Branch Instruction
SEV CLV
Sets the Overflow Flag (V) in SREG Clears the Overflow Flag (V) in SREG
(Status Register). (Status Register).
Operation: V←1 Operation: V←0

Syntax: SEV Syntax: CLV
Flags: V Flags: V
Words: 1 Words: 1
Cycles: 1 Cycles: 1

Branch Instruction
SET CLT
Sets the T Flag (T) in SREG (Status Clears the T Flag (V) in SREG (Status
Operation: T←1 Operation: T←0

Syntax: SET Syntax: CLT
Flags: T Flags: T
Words: 1 Words: 1
Cycles: 1 Cycles: 1

Branch Instruction
SEH CLH
Sets the Half Carry (H) in SREG (Status Clearss the Half Carry (H) in SREG (Status
Operation: H←1 Operation: H←0

Syntax: SEH Syntax: CLH
Flags: H Flags: H
Words: 1 Words: 1
Cycles: 1 Cycles: 1

Branch Instruction
Branch Instructions
JMP
Jump to an address within the entire Program memory. See also RJMP.
Operation: PC←K
Syntax: JMP K
Operands: 0≤K≤4M
Words: 2
Cycles: 3

Branch Instruction
Branch Instructions
RJMP
Relative jump to an address within PC - 2K +1 and PC + 2K (words).
For AVR microcontrollers with Program memory not exceeding 4K words (8K bytes) this
instruction can address the entire memory from every address location. See also JMP.
Operation: PC←PC+K+1
Syntax: RJMP K
Operands: -2K≤K≤2K
Words: 1
Cycles: 2

Branch Instruction
Branch Instructions
IJMP
Indirect jump to the address pointed to by the Z (16 bits) Pointer Register in the
Register File.
The Z-pointer Register is 16 bits wide and allows jump within the lowest 64K words
(128K bytes) section of Program memory.
Operation: PC←Z
Syntax: IJMP
Operands: none
Words: 1
Cycles: 2

Branch Instruction
Branch Instructions
CALL
Calls to a subroutine within the entire Program memory.
The return address (to the instruction after the CALL) will be stored onto the Stack.
The Stack Pointer uses a post-decrement scheme during CALL.
Operation: PC←K
STACK←PC+2
SP←SP-2
Syntax: CALL K
Operands: 0≤K≤64K
Words: 2
Cycles: 4

Branch Instruction
Branch Instructions
RCALL
Relative call to an address within PC - 2K + 1 and PC + 2K (words).
The return address (the instruction after the RCALL) is stored onto the Stack.
For AVR microcontrollers with Program memory not exceeding 4K words (8K bytes)
this instruction can address the entire memory from every address location.
The Stack Pointer uses a post-decrement scheme during RCALL.
Operation: PC←PC+K+1
STACK←PC+1
SP←SP-2
Syntax: CALL K
Operands: -2K≤K≤2K
Words: 1
Cycles: 3

Branch Instruction
Branch Instructions
ICALL
Calls to a subroutine within the Program memory.
The return address (to the instruction after the CALL) will be stored onto the Stack.
See also RCALL.
The Stack Pointer uses a post-decrement scheme during CALL.
Operation: PC←Z
STACK←PC+1
SP←SP-2
Syntax: ICALL
Operands: none
Words: 1
Cycles: 3
Branch Instruction
Branch Instructions
RET
Returns from subroutine. The return address is loaded from the STACK.
The Stack Pointer uses a pre-increment scheme during RET
Operation: SP←SP+2 PC←STACK

Syntax: RET
Operands: none
Words: 1
Cycles: 4

Branch Instruction
Branch Instructions
RETI
Returns from interrupt. The return address is loaded from the STACK and the Global
Interrupt Flag is set.
Note that the Status Register is not automatically stored when entering an interrupt
routine, and it is not restored when returning from an interrupt routine. This must be
handled by the application program. The Stack Pointer uses a pre-increment scheme
during RETI.
Operation: SP←SP+2 PC←STACK I←1

Syntax: RETI
Operands: none
Flags: I=1
Words: 1
Cycles: 4

Branch Instruction
Branch Instructions
CPSE
This instruction performs a compare between two registers Rd and Rr, and skips the
next instruction if Rd = Rr.
Operation: if(Rd==Rr) then PC←PC+2

else PC←PC+1
Syntax: CPSE Rd,Rr
Operands: 0 ≤ d ≤ 31 0 ≤ r ≤ 31
Words: 1
Cycles: 1 if condition is false
2 if condition is true

Branch Instruction
Branch Instructions
SBRS SBRC
This instruction tests a single bit in a This instruction tests a single bit in a
register and skips the next instruction if the register and skips the next instruction if the
bit is set. bit is cleared.
Operation: if(Rr(b)==1) then Operation: if(Rr(b)==0) then

PC←PC+2 PC←PC+2
else PC←PC+1 else PC←PC+1
Syntax: SBRS Rd,b Syntax: SBRC Rd,b
Operands: 0 ≤ r ≤ 31 0≤b≤7 Operands: 0 ≤ r ≤ 31 0≤b≤7
Flags: no effects on flags Flags: no effects on flags
Words: 1 Words: 1
Cycles: 1 if condition is false Cycles: 1 if condition is false
2 if condition is true 2 if condition is true

Branch Instruction
Branch Instructions
SBIS SBIC
This instruction tests a single bit in an I/O This instruction tests a single bit in an I/O
Register and skips the next instruction if Register and skips the next instruction if the
the bit is set. This instruction operates on bit is cleared. This instruction operates on
the lower 32 I/O Registers addresses 0-31. the lower 32 I/O Registers addresses 0-31.
Operation: if(I/O(A,b)==1) Operation: if(I/O(A,b)==0)

then PC←PC+2 then PC←PC+2
Syntax: SBIS A,b Syntax: SBIC A,b
Operands: 0 ≤ A ≤ 31 0≤b≤7 Operands: 0 ≤ A ≤ 31 0≤b≤7
Words: 1 Words: 1
Cycles: 1 if condition is false Cycles: 1 if condition is false
2 if condition is true 2 if condition is true

Branch Instruction
Branch Instructions According to Flags

If the given flag is set If the given flag is cleared
Conditional relative branch. Tests the Carry Conditional relative branch. Tests the Carry
Flag (C) and branches relatively to PC if C Flag (C) and branches relatively to PC if C
is set. is cleared.
Operation: if(FLAG==1) then Operation: if(FLAG==0) then

PC←PC+K+1 PC←PC+K+1
Syntax: INSTRUCTION K Syntax: INSTRUCTION K
Operands: -64 ≤ K ≤ 63 Operands: -64 ≤ K ≤ 63
Words: 1 Words: 1
Cycles: 1 Cycles: 1
The parameter k is the offset from PC and is represented in twos

complement form. Dr. György Schuster AVR assembler
Branch Instruction
Branch Instructions (pure flags)

TRUE FALSE
BRCS C==1 BRCC C==0

Branch Instruction

TRUE FALSE
BRCS C==1 BRCC C==0
BRMI N==1 BRPL N==0

Branch Instruction

TRUE FALSE
BRCS C==1 BRCC C==0
BRMI N==1 BRPL N==0
BRVS V==1 BRVC V==0

Branch Instruction

TRUE FALSE
BRCS C==1 BRCC C==0
BRMI N==1 BRPL N==0
BRVS V==1 BRVC V==0
BREQ Z==1 BRNE Z==0

Branch Instruction

TRUE FALSE
BRCS C==1 BRCC C==0
BRMI N==1 BRPL N==0
BRVS V==1 BRVC V==0
BREQ Z==1 BRNE Z==0
BRTS T==1 BRTC T==0

Branch Instruction

TRUE FALSE
BRCS C==1 BRCC C==0
BRMI N==1 BRPL N==0
BRVS V==1 BRVC V==0
BREQ Z==1 BRNE Z==0
BRTS T==1 BRTC T==0
BRHS H==1 BRHC H==0

Branch Instruction

TRUE FALSE
BRCS C==1 BRCC C==0
BRMI N==1 BRPL N==0
BRVS V==1 BRVC V==0
BREQ Z==1 BRNE Z==0
BRTS T==1 BRTC T==0
BRHS H==1 BRHC H==0
BRIS I==1 BRIC I==0

Branch Instruction
Branch Instructions (arithmetic)
Usually after CP instruction.

Statement
BREQ Rd==Rr Z==1

Branch Instruction

Statement
BREQ Rd==Rr Z==1
BRNE Rd!=Rr Z==0

Branch Instruction

Statement
BREQ Rd==Rr Z==1
BRNE Rd!=Rr Z==0
BRGE Rd>=Rr V⊕N==0

Branch Instruction

Statement
BREQ Rd==Rr Z==1
BRNE Rd!=Rr Z==0
BRLT Rd<Rr V⊕N==1

Branch Instruction

Statement
BREQ Rd==Rr Z==1
BRNE Rd!=Rr Z==0
BRLT Rd<Rr V⊕N==1
BRSH Rd>=Rr C==0

Branch Instruction

Statement
BREQ Rd==Rr Z==1
BRNE Rd!=Rr Z==0
BRLT Rd<Rr V⊕N==1
BRSH Rd>=Rr C==0
BRLO Rd<Rr C∨Z==0

Branch Instruction
Special instructions
NOP
This instruction performs a single cycle No Operation.

Branch Instruction
NOP
SLEEP
This instruction sets the circuit in sleep mode defined by the MCU Control Register.

Branch Instruction
NOP
SLEEP
This instruction sets the circuit in sleep mode defined by the MCU Control Register.
WDR
This instruction resets the Watchdog Timer. This instruction must be executed within a
limited time given by the WD prescaler.
See the Watchdog Timer hardware specification.

Avrasm

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Basics

Dr. György Schuster

Dr. György Schuster AVR assembler

Dr. György Schuster AVR assembler

Dr. György Schuster AVR assembler

Dr. György Schuster AVR assembler

Structure of an assembly line

Dr. György Schuster AVR assembler

Structure of an assembly line

Dr. György Schuster AVR assembler

Structure of an assembly line

Dr. György Schuster AVR assembler

Structure of an assembly line

Dr. György Schuster AVR assembler

Structure of an assembly line

Dr. György Schuster AVR assembler

Structure of an assembly line

Dr. György Schuster AVR assembler

Structure of an assembly line

Dr. György Schuster AVR assembler

Structure of an assembly line

Dr. György Schuster AVR assembler

Structure of an assembly line

Dr. György Schuster AVR assembler

Structure of an assembly line

label: .equ v1=5 ;Set v1 to 5 (directive)

Dr. György Schuster AVR assembler

Structure of an assembly line

label: .equ v1=5 ;Set v1 to 5 (directive)

loop: rjmp loop ;Infinite loop (instruction)

Dr. György Schuster AVR assembler

Structure of an assembly line

label: .equ v1=5 ;Set v1 to 5 (directive)

loop: rjmp loop ;Infinite loop (instruction)

;End of this example (pure comment)

Dr. György Schuster AVR assembler

Define which device to assemble for

Dr. György Schuster AVR assembler

Define which device to assemble for

Dr. György Schuster AVR assembler

Define which device to assemble for

Dr. György Schuster AVR assembler

Define which device to assemble for

Dr. György Schuster AVR assembler

Define which device to assemble for

Dr. György Schuster AVR assembler

Dr. György Schuster AVR assembler

Dr. György Schuster AVR assembler

Dr. György Schuster AVR assembler

Dr. György Schuster AVR assembler

Dr. György Schuster AVR assembler

Dr. György Schuster AVR assembler

Dr. György Schuster AVR assembler

Set program origin

Dr. György Schuster AVR assembler

Set program origin

Dr. György Schuster AVR assembler

Set program origin

Dr. György Schuster AVR assembler

Set program origin

Dr. György Schuster AVR assembler

Set program origin