UG_201512_PL30_004

XMC™ Link
Based on SEGGER J-Link Technology

About this document

Scope and purpose
This is the user’s manual for the XMC™ Link also called isolated debug probe, providing technical information
and hints on how to use it.
Intended audience
This document is intended for anyone who wants to use the XMC™ Link.

Table of contents
About this document .............................................................................................................................................1
Table of contents ...................................................................................................................................................1
1 Introduction.......................................................................................................................................2
1.1 Block diagram..........................................................................................................................................2
1.2 Getting started.........................................................................................................................................3
2 Hardware description ........................................................................................................................4
2.1 Known limitation.....................................................................................................................................4
2.2 Debug connector.....................................................................................................................................4
2.2.1 Pinout of debug connectors ..............................................................................................................5
2.3 Power supply ...........................................................................................................................................6
2.4 Virtual COM Port (UART-to-USB Bridge) .................................................................................................6
3 Production data .................................................................................................................................7
3.1 Schematics ..............................................................................................................................................7
3.1.1 Differences in hardware versions ......................................................................................................7
3.2 Components placement and geometry .................................................................................................9
3.3 List of material.........................................................................................................................................9
Revision history ...................................................................................................................................................11

User's Manual R1.0

www.infineon.com 2015-12-11
XMC™ Link
Based on SEGGER J-Link Technology
Table of contents

1 Introduction
This document describes the features and hardware details of the XMC™ Link. XMC™ Link is an isolated debug
probe for all XMC™ microcontrollers.

The debug probe is based on SEGGER J-Link debug firmware, which enables use with DAVE™ and all major
third-party compiler/IDEs known from the wide ARM® ecosystem. Table 1 shows its specification.

Table 1 XMC™ Link specification

Supported Processor All Infineon Cortex®-M based XMC™ Microcontroller
Dimensions 62 x 33 mm (without cables plugged in)
Power PC side: 5 V via Micro-AB USB Connector
Target side: 2.5 V – 5 .5V via one of the debug connector (VDD)
Connectors • 10-pin Cortex® Debug Connector
• 8-pin XMC™ MCU Debug Connector
• Micro –AB USB Connector
Supported Protocols • Serial Wire Debug (SWD)
• Single Pin Debug (SPD)
• Serial Wire Viewer (SWV via SWO pin)
• JTAG
• UART-to-USB Bride, Virtual COM (VCOM)
Others • 1 kV functional isolation

1.1 Block diagram

The block diagram in Figure 1 shows the main components of the XMC™ Link and their interconnections. There
are following main building blocks:
• XMC4200 Microcontroller in a VQFN42 package
• Isolating Device
• 10-pin Cortex® Debug Connector
• 8-pin XMC™ MCU Debug Connector
• Micro-AB USB Connector
• 2 LEDs: Debug LED and Communication LED
• 12 MHz Crystal

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Based on SEGGER J-Link Technology
Table of contents

XMC™ Link V1 12 MHz Debug COM

Crystal LED LED

2.5V -5.5V DIR GPIO OCS CCU80

RESET

SPD U0C0
8-pin XMC™ MCU SPD
SWD
Debug Connector SWD
RX/TX XMC4200
Micro
Isolating JTAG U0C1 Micro- USB USB
USB
SPD Device controller
10-pin Cortex™ SWD
JTAG SWV U1C1
Debug Connector
SWV

RX/TX U1C0 EVR

IFX54441
3.3V 5V
Voltage
Regulator

BlockDiag.emf

Figure 1 Block diagram of the XMC™ Link

1.2 Getting started

To operate the XMC™ Link the installation of the J-Link Driver is required.
1. Please download the latest version from https://www.segger.com/jlink-software.html and install it on your
PC/laptop.

Note: The J-Link driver is also part of the typical installation of DAVE™ and 3rd party tools supporting SEGGER J-
Link.

2. Connect XMC™ Link with your PC/laptop using the Micro USB cable.
3. A proper connection and installation of the J-Link driver is indicated by a constantly illuminated DEBUG
LED.
4. Connect your XMC™ target board with XMC™ Link using one of the enclosed cables.
5. Select SEGGER J-Link as debugger in your preferred IDE e.g. DAVE™
6. Start the flash programming and debugging session

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XMC™ Link
Based on SEGGER J-Link Technology
Table of contents

2 Hardware description
The following chapters provide a detailed description of the hardware and how it can be used. The hardware is
depicted in Figure 2.

Figure 2 PCB of the XMC™ Link

2.1 Known limitation

XMC Link™ V1 has a minor known limitation which could occur only during programming the BMI of a XMC1000
device in ASC-BSL mode to another BMI mode. This limitation is solved in the PCB version V1.1. The version
number is printed on the bottom side of the PCB below the USB connector.
The limitation can be avoided if the XMC™ Link V1 is powered before the target XMC™ will be powered.

2.2 Debug connector

The XMC™ Link can be connected to the XMC™ target microcontroller by either of the debug connectors:
• 8-pin XMC™ MCU Debug Connector (2 x 4 pin, 0.1”, 2.54mm)
• 10-pin Cortex™ Debug Connector (2 x 5 pin, 0.05”, 1.27mm)

The 8-pin XMC™ MCU Debug Connector is mainly used for the XMC1000 applications. The 10-pin Cortex™ Debug
Connector can be used for all XMC™ families but is focusing on the XMC4000 family supporting Serial Wire
Viewer (SWV) via the SWO pin.

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XMC™ Link
Based on SEGGER J-Link Technology
Table of contents

The common debug protocol supported by both connectors is Serial Wire Debug (SWD). Figure 3 provides an
overview on all supported debug protocols and communication channels.

XMC1000 Family XMC4000 Family

8-pin XMC™ MCU 10-pin Cortex™ 10-pin Cortex™

Debug Connector Debug Connector Debug Connector
Serial Wire Debug
(SWD)   
Single Pin Debug
(SPD)  
Serial Wire Viewer
(SWV/SWO) 
Virtual COM Port
(UART-to-USB Bridge) 
JTAG 
Figure 3 Supported debug protocols

2.2.1 Pinout of debug connectors

The pinout of both debug connectors and to which pins of the XMC™ the debugger must be connected can be
found in Table 2 and Table 3.

Table 2 Pinout of the 10-pin Cortex™ debug connector

Pin Function XMC1000 Connection (Pin name) XMC4000 Connection (Pin name)
1 VCC Power Supply 2.5 V – 5.5 V (VDD) Power Supply VDDP 3.3 V (VDDP)
2 SWIO/TMS Serial Wire Data (P0.14 | P1.3) Serial Wire Data, JTAG-TMS (TMS)
3 GND Ground (VSS) Ground (VSS)
4 SWCLK/TCK Serial Wire Clock (P0.15 | P1.2) Serial Wire Clock, JTAG-TCK (TCK)
5 GND Ground (VSS) Ground (VSS)
6 SWO/TDO Not connected Serial Wire Output, JTAG-TDO (P2.1) (optional)
7 KEY Not connected Not connected
8 TDI Not connected JTAG-TDI (P0.7)(optional)
9 GNDDetect Can be used to switch off an on-board debug probe (PORST# of OBD) (optional)
10 RESET# Not connected PORST# (mandatory)

Table 3 Pinout of the 8-pin XMC™ MCU debug connector

Pin Function XMC1000 Connection (Pin name)
1 SC Serial Wire Clock (P0.15 | P1.2)
2 SD Serial Wire Data (P0.14 | P1.3)
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Based on SEGGER J-Link Technology
Table of contents

Pin Function XMC1000 Connection (Pin name)

3 + Power supply 2.5 V – 5.5 V (VDD)
4 0 Ground (VSS)
5 0 Ground (VSS)
6 + Power supply 2.5 V – 5.5 V (VDD)
7 TX (PC-TX)) Transmissstion line of PC/laptop, receive line of XMC™ device (optional)
8 RX (PC-RX) Receive line of PC/laptop, transmission line of of XMC™ device (optional)

2.3 Power supply

XMC™ Link is powered from the Micro USB plug and typically draws about 70 mA. The on-board voltage
regulator IFX54441LDV33 generates the required 3.3 V for the XMC4200 microcontroller out of the 5 V USB
voltage. The debug probe is not designed to provide power for the target device.
The target application must power the isolated part of the debugger. The isolated side the XMC™ Link draws a
few mA of current from the target application.

2.4 Virtual COM Port (UART-to-USB Bridge)

The 8-pin XMC™ MCU Debug Connector supports communication between a PC/laptop and target XMC™ device
via Virtual COM Port (UART-to-USB Bridge). Therefore UART pins of the target XMC™ device needs to be
connected to TX/RX pins of the debug connector (see Table 3).

Note: Take care of the UART cross connection: TX pin of debugger needs to be connected to RX pin of the
XMC device. RX pin of debugger needs to be connected to TX pin of the XMC device.

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XMC™ Link
Based on SEGGER J-Link Technology
Table of contents

3 Production data
This chapter covers schematics, board dimensions, component placement and the list of material.

3.1 Schematics
Figure 4 shows the schematics of XMC™ Link V1 in hardware version 1.1.

3.1.1 Differences in hardware versions

In hardware version 1.1 compared to hardware version v1.0 (V1) the pull-down resistor R20 was added to the TX
line. The version number is printed on the bottom side of the PCB below the USB connector.

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 1 2 3 4 5 6 7 8

Figure 4
ON-BOARD DEBUGGER (OBD) and ISO IF Power 3,3V

User's Manual
GNDISO VISO3.3
SPI Master U0C0
XMC™ Link

SWD_DIR SWD DIR GPIO-P1.3 Configure Debugger RESET# signal at P0.3 as open-drain output.
SWD_IN MISO DX0B-P1.4 VISO3.3
SWD_OUT MOSI DOUT0-P1.5

R1
R2
U2 U1

VISO5
SWCLK/TCK CLK_OUT SCLKOUT-P1.1
Table of contents

A CS_OUT SELO0-P1.0 TDI 21 42 9*2 1*2 A

P2.5 IN

R20
10k/0402
R21
10k/0402
22 P0.8 43 OUT
SWCLK/TCK P2.4 P0.7
SPI Slave U0C1 CS 23 P2.3 44 7 EN 4
24 P0.6 45 SENSE/ADJ
CS_IN DX2A-P2.3 SWO/TDO P2.2 P0.5
TX
CLK_IN DX1A-P2.4 25 P2.1 46 RX
26 P0.4 47 5
TDI MISO DOUT0-P2.5 P2.0 RESET# C1
P0.3 BYP

LED1 680R/0603
LED-GN/D/0603
LED2 680R/0603
LED-RT/D/0603
SWO/TDO MOSI DX0A-P2.2 48 DEBUG_LED# 6 EXP
P0.2 GND EXP
1 COM_LED# 10nF/0402
C3
P0.1 2
UART U1C1 P0.0
SWO/TDO IFX54441LDV33
SWV RXD DX0D-P0.0
Digital 35 SWD_OUT
P1.5

10uF/10V/0603
C2
UART2 U1C0 36 SWD_IN
P1.4
10uF/10V/0603

RX RXD DX0A-P0.4 37 SWD_DIR

P1.3 38
TX TXD DOUT0-P0.5 P1.2
TX_ENABLE GPIO-P0.7 VISO3.3 39 SWCLK/TCK
P1.1 40
TX_ACTIVE# GPIO-P0.6 CS GNDISO GNDISO GNDISO
P1.0
CONTROL GPIOs 19
P14.9 20
RESET# RESET# GPIO-P0.3 P14.8
COM LED
DEBUG_LED# DEBUG_LED# GPIO-P0.2 11 Level Shifter
B P14.7 12 B
COM_LED# AUX_LED# GPIO-P0.1 Analog No RESET Pin
C4 P14.6 13
P14.5
UART

VISO3.3
VISO5
14 SPD
100nF/0402 18 P14.4 15
VAREF SWV
P14.3
Based on SEGGER J-Link Technology

17 VAGND 16 JTAG
P14.0
9 GNDISO
RTC_XTAL_2
GNDISO Hibernate/RTC 7 X3C
8 HIB_IO_0 10
L1
RTC_XTAL_1 VBAT BLM18PG600
1
3 R3 22R/0402
Q1 USB_D- 2
R4 510R/0402 30
XTAL2 USB USB_D+ 4 R5 22R/0402 3
12MHZ/S/3.2X2.5 4
29
XTAL1 5

ZX62-AB-5PA

2
41

R6
4k7/0402
VDDP2

V2
OBD_OFF# 32 PORST# 28
34 VDDP1 5
OBD_TCK TCK Supply

D2
33 VDDP
OBD_TMS TMS

3 D1
C C7 C

8
VISO3.3 27 31 100nF/0402
VSS

R7
10k/0402
R8
1M/0402
EPAD VDDC1 6

ESD8V0L2B-03L 1

C5 15pF/0402
C6 15pF/0402
EPAD VDDC

VISO3.3
XMC4200_QFN48
X4 GNDISO GNDISOGNDISO
1
2

R9
100k/0402
3
GNDISO GNDISO 4
5

no ass. ADJ_1 ADJ_2 ADJ_3

C8 100nF/0402
C9 100nF/0402
C13 4u7F/6.3V/0603
C10 100nF/0402
C11 100nF/0402
C12 100nF/0402
C14 10uF/10V/0603
C15 10uF/10V/0603

Schematic of the XMC™ Link V1 (Hardware Version 1.1)

VDDP

GNDISO GNDISO
Debug Connectors
GNDISO GNDISO X1
R11 VDDP

VISO3.3 U4 1 2 SWIO/TMS*
D D
100k/0402

U3 SWD_DIR* 1 5 3 4 SWCLK/TCK*
OE VCC

VDDP
1 16 3 VDDP 5 6 SWO/TDO*
VDD1 VDD2 GND R18
SWD_OUT* 2 4 SWIO/TMS* 7 8 TDI*
A Y
RESET# 2 15 RESET#* 9 10 RESET#_OD
GND

A1 B1 100R/0402
SWCLK/TCK 3 14 R12 100R/0402 SWCLK/TCK* 74LVC1G126GW
A2 B2
TX 4 13 R13 100R/0402 PC_TX* C16 VDDP FTS-105-01-L-DV
A3 B3
SWO/TDO 5 12 R15 100R/0402 SWO/TDO* ISO_SWIO/TMS*
A4 B4

C23
C17
C18
C19
RX 6 11 R14 100R/0402 PC_RX* Cortex Debug
GND

A5 B5
7 10 100nF/0402

100nF/0402
100nF/0402
EN1 EN2

10uF/10V/0603
10uF/10V/0603
R19 no ass./0R/0603
X2

VDDP
VDDP

8 9 GND
GND1 GND2
VDDP PC_RX* 8 7 PC_TX*
SI8652BB-B-IS1 6 5 VDDP
R10
GND

U5 4 3
100k/0402

GNDISO GND
5 3 SWIO/TMS* 2 1 SWCLK/TCK*
GND

VCC GND
VISO3.3
U6 TSM-104-01-F-DH-A
R17

VDDP
1 16 RESET#* 2 4 RESET#_OD
VDD1 VDD2 A Y
100R/0402 XMC BootKit
SWD_DIR 2 A1 15 SWD_DIR* NL17SZ07DF
E 3 B1 14 E
SWD_OUT A2 B2
SWD_OUT*
TDI 4 13 R16 100R/0402 TDI*
A3 B3
C20
SWD_IN 5 12 ISO_SWIO/TMS*
A4 B4

C24
C21
C22
C25
6 11 Legal Disclaimer
100nF/0402

A5 B5
7 10

100nF/0402
100nF/0402
EN1 EN2 The information given in this document shall in no event be regarded as a guarantee of conditions or

10uF/10V/0603
GND GND characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
XMC-Link-V1.1
10uF/10V/0603
8 9
GND1 GND2 information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
02.12.2015 12:23:57
SI8652BB-B-IS1
of any third party.
GNDISO GND Sheet: 1/1
1 2 3 4 5 6 7 8

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R1.0
 XMC™ Link
Based on SEGGER J-Link Technology
Table of contents

3.2 Components placement and geometry

Figure 5 shows the board dimensions and the placement of components on the PCB.

60mm
C17 C20
R10

C18
C19
ADJ_2
C23
C2

U5
R12
C1 R17
U1

R13
R8

R21

U3
C7

R15
C3

R19
C15 R20
R6

X1
R7
C12
30mm

R3
L1

C24
R9

C9 X2
X3

R5
V2

C21

C22

C25
U2

C11

R4

R14
C10
C16
C8
C5

R11
Q1

U4
C4
C13

C6
R1

U6

R2 C14 R16
R18
ADJ_1
LED1
LED2

ADJ_3

X4

Figure 5 Components placement and geometry

3.3 List of material

The list of material is valid for the XMC™ Link V1 in hardware version 1.1.

Table 4 List of material

Value Device Qty Reference Designator
15pF 50V 10% 0402 Capacitor COG 2 C5, C6
C2, C3, C14, C15, C19, C23, C24,
10uF 10V 20% 0603 Capacitor X5R 8 C25
C4, C7, C8, C9, C10, C11, C12,
100nF 16V 10% 0402 Capacitor X7R 13 C16, C17, C18, C20, C21, C22
10nF 16V 10% 0402 Capacitor X7R 1 C1
4u7F 6.3V +-10% 0603 Capacitor X7R 1 C13
ZX62-AB-5PA Connector Micro USB AB SMD Hirose 1 X3
12MHz 3.2x2.5 Crystal 12MHz 4Pad NX3225SA NDK 1 Q1
ESD8V0L2B-03L TSLP-3-1 Diode Protection Infineon 1 V2
BLM18PG600SN1D 0603 Ferrite Bead 60R 500mA Murata 1 L1
SI8652BB-B-IS1 NB-SOIC-16 Isolation IC 2 U3, U6
LSQ971-Z LED-GN 0603 LED SMD gn 1 LED1
LSQ976-Z LED-RT 0603 LED SMD rt 1 LED2
74LVC1G126GW TSSOP5 Line Driver 1 U4
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Table of contents

Value Device Qty Reference Designator

SN74LVC1G07 SC70-5 Line Driver 1 U5
XMC4200-Q48K256 QFN48 Microcontroller XMC4200 Infineon 1 U2
FTS-105-01-L-DV 2x5pin X1
0.05" Pin Header SMD Samtec 1
TSM-104-01-F-DH-A 2x4pin X2
0.1" Pin Header SMD Samtec 1
no ass. 1x5pin 0.1" Pin Header THT 1 X4
100R 1% 0402 Resistor 7 R12, R13, R14, R15, R16, R17, R18
100k 1% 0402 Resistor 3 R9, R10, R11
10k 1% 0402 Resistor 3 R7, R20, R21
1M 1% 0603 Resistor 1 R8
22R 1% 0402 Resistor 2 R3, R5
4k7 1% 0402 Resistor 1 R6
510R 1% 0402 Resistor 1 R4
680R 1% 0603 Resistor 2 R1, R2
no ass. 0R 0603 Resistor 1 R19
IFX54441LDV33 PG-TSON-10 Voltage Regulator 3.3 V Infineon 1 U1

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Based on SEGGER J-Link Technology
Revision history

Revision history
Major changes since the last revision
Page or reference Description of change

User's Manual 11 R1.0

2015-12-11
Trademarks of Infineon Technologies AG
µHVIC™, µIPM™, µPFC™, AU-ConvertIR™, AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, CoolDP™, CoolGaN™, COOLiR™, CoolMOS™, CoolSET™, CoolSiC™,
DAVE™, DI-POL™, DirectFET™, DrBlade™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, GaNpowIR™,
HEXFET™, HITFET™, HybridPACK™, iMOTION™, IRAM™, ISOFACE™, IsoPACK™, LEDrivIR™, LITIX™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OPTIGA™,
OptiMOS™, ORIGA™, PowIRaudio™, PowIRStage™, PrimePACK™, PrimeSTACK™, PROFET™, PRO-SIL™, RASIC™, REAL3™, SmartLEWIS™, SOLID FLASH™,
SPOC™, StrongIRFET™, SupIRBuck™, TEMPFET™, TRENCHSTOP™, TriCore™, UHVIC™, XHP™, XMC™

Trademarks updated November 2015

Other Trademarks
All referenced product or service names and trademarks are the property of their respective owners.

IMPORTANT NOTICE
Edition 2015-12-11 The information contained in this application note
is given as a hint for the implementation of the
Published by product only and shall in no event be regarded as a
description or warranty of a certain functionality,
Infineon Technologies AG condition or quality of the product. Before
81726 Munich, Germany implementation of the product, the recipient of this
application note must verify any function and other
technical information given herein in the real
© 2016 Infineon Technologies AG. application. Infineon Technologies hereby
disclaims any and all warranties and liabilities of
All Rights Reserved. any kind (including without limitation warranties of
non-infringement of intellectual property rights of
Do you have a question about this any third party) with respect to any and all
information given in this application note.
document?
Email: erratum@infineon.com The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer’s technical departments
Document reference to evaluate the suitability of the product for the
UG_201512_PL30_004 intended application and the completeness of the
product information given in this document with
respect to such application.
For further information on the product, technology,
delivery terms and conditions and prices please
contact your nearest Infineon Technologies office
(www.infineon.com).
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Due to technical requirements products may
contain dangerous substances. For information on
the types in question please contact your nearest
Infineon Technologies office.
Except as otherwise explicitly approved by Infineon
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Technologies, Infineon Technologies’ products may
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