Stanley College of Engineering & Technology for Women Chapel Road, Abids, Hyderabad All Eligible UG Courses Accredited by NBA - Accredited with NAAC “A” Grade Certificate This is to certify that this is a bonafide record of the work, done by Miss bearing RollNo.__ of BE. branch in the Laboratory during the academic year Number of experiments conducted: Internal Examiner External ExaminerVision of the Institute and Department The Vision of the STLW: Empower Women; Impact the World Empowering girl students through professional education integrated with values and character to make an impact in the World. The Mission STLW, in pursuance of its vision: M1: Providing quality engineering education for girl students to make them competent and confident to succeed in professional practice and advanced learning. M2: Establish state-of-art-facilities and resources to facilitate world class education. M3: Integrating qualities like humanity, social values, ethics, and leadership in order to. encourage contribution to society. Vision of the Information Technology Department: Empowering girl students with the contemporary knowledge in Information Technology, for their success in life Mission of the Information Technology Department: M1: Providing quality education and excellent environments for students to learn and practice various latest hardware, software and firmware platforms. M2: To establish industry oriented training integrated with opportunities for team work, leadership. M3: To groom students with values, ethics and social activities Programme Educational Objectives PEO1: Graduates shall have enhanced skills and contemporary knowledge to adapt new software and hardware technologies for professional excellence, employment and Research, PEO2: Proficient in analyzing, developing, solving engineering problems to assist life-long learning and to develop team work. PEOS: To inculcate self-confidence, acquire professional and ethical attitude, infuse leadership qualities, impart proficiency in soft-skills and the ability to relate engineering with social issues.POs and PSOs of IT Dept Programme Outcomes: 10. 1 12. Engineering knowledge: Apply the knowledge of mathematics, science, engineering fundamentals and an engineering specialization to the solution of complex engineering problems. Problem Analysis: Identify, formulate, research literature and analyze complex engineering problems reaching substantiated conclusions using first principles of mathematics and natural sciences and engineering sciences. Design/development of solutions: Design solutions for complex engineering problems and design system components or processes that meet the specified needs with appropriate consideration for the public health and safety and the cultural, societal, and environmental considerations. Conduct investigations of complex problems: Use research-based knowledge and research methods including design of experiments, analysis and interpretation of data, and synthesis of the information to provide valid conclusions. Modern Tool Usage: Create, select, and apply appropriate techniques, resources, and modern engineering and IT tools, including prediction and modeling, to complex engineering activities, with an understanding of the limitations. ‘The engineer and society: Apply reasoning informed by contextual knowledge to assess societal, health, safety, legal and cultural issues and the consequent responsibilities relevant to the professional engineering practice. Environment & sustainability: Understand the impact of professional engineering solutions in societal and environmental context, and demonstrate knowledge of, and need for sustainable development. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms of the engineering practice. Individual and Team work: Function effectively as an individual, and as a member or leader in diverse teams, and in multidisciplinary settings. Communication: Communicate effectively on complex engineering activities with the engineering community and with society at large, such as being able to comprehend and write effective reports and design documentation, make effective presentations, and give and receive clear instructions. . Project Management and Finance: Demonstrate knowledge and understanding of the engineering and management principles and apply these to one’s own work, as a member and leader in a team, to manage projects and in multidisciplinary environments. Life-long Learning: Recognize the need for, and have the preparation and ability to engage in independent and life-long learning in the broadest context of technological change. Programme Specific Outcomes: PSO1 Skilled Professional: Ability to apply technical skills and involve in the creation, maintenance and use of Computer, Computer Networks and Computer Information Systems, Psoz: Research Capability: Use fundamental knowledge of mathematics and basic sciences to investigate emerging technologies leading to innovations in the field of Data Analytics and Artificial Intelligence.INDEX EXP No. NAME OF THE EXPERIMENT Date. Page No. Performed [Submitted] From | To RemarksINDEX EXP No. NAME OF THE EXPERIMENT Date Page No. Performed | Submitted| From | To RemarksProgram no: 1(a) Title: Implement the logical gates operation using Verilog HDL switch-level model and simulate the output by forcing the input values, Aim: To implement the logical gates operation using Verilog HDL switch-level model and simulate the output by forcing the input values. Apparatus: Personal Computer, modelsim ‘Truth table: Input Iza Input 2:b | Output: | Output: | Output: | Output: oRz__|_ANp2__| NAND2 0 0 0 0 1 0 1 1 0 1 1 o i 0 1 1 1 1 1 0 Tnputsa ‘Output: NOTI o 1 1 o Flowchart: start Define input and output ports eo Define supply rails Assign the nmos and pmos connections to all the gatesNAND GATE: ‘Transistor level implementation: DESIGN CODE(verilog code) module mynand(a.b, input a,b; output y: supply pwr: supply0 gnd; wire wl: nmos nl (w1,gnd,b); nos n2(y,w1 pmos pI (y,pws pmos p2{y,pwr.b): endmoduleDice ec SILL ee © Kaew NOR GATE: Logic Diagram: Transistor level implementaticDESIGN CODE(verilog code): Nor Gat module nor(a,b, out); input a,b; output out: wire w1; supply pwr: supply0 gnd; nmos ml (out,gnd.a); nmos n2(out,gnd,b): pmos pl (w1,pwr.a); pmos 2 (out,w1,b); endmodule Sada ees iw =a rkuN WORD PreegieccTitle: Implement the logical AOI and OAL gate operation using Verilog HDL switch-level model and simulate using test bench. Aim: To implement the logical AOT and OAL gate operation using Verilog HDL switch: evel model and simulate using test bench. Apparatus: Personal Computer,modelsim Logic Diagram: AOI gate Circuit Diagram/ transistor level/CMOS LEVEL:Verilog module AOI gate: module aoi(out,a,b,c,d); input a,b.c.d: output out; wire w1,w2,w3; supply pwr; supply0 gnd; nmos nl (out,wl,a); mos n2(w!,gnd,b); nmos n3(out,w2,c); nmos nd (w2,gnd,d); pmos pl (w3,pwr,a); pmos p2(w3,pwr,b); pmos p3(out.w3,c); mos p4 (out,w3,d); endmodule Verilog test fixture: module aoil_tb; reg abcd; wire f; aoil uut(a,b,c,d,out); initial begin a=0;b=0;0=0;d=0; 410 a: #10 a=l;:b=1;c=1:d=1: end endmoduleSimulation Output Logic Diagram: OAI gate F=(arb).(crd)Verilog module OAT gate: module oaig(a,b,c,d, out); input a,b,c,d; output out; wire wl,w2,w3; supply! pwr: supply0 gnd; mos ni (out,w1.a); nmos n2(out,w1,b); nmos n3(w1,gnd,c); nmos n4(w1,gnd.d); pmos p1 (w2,pwr.a); pmos p2(out,w2,b); pmos p3(w3,pwr,0}; pmos p4(out,w3,d); endmodule Verilog Text Fixture:timescale Ins/Ips; module oaig_th0: // Inputs rega; reg b: rege: reg di; wire out: oai uut (a,b,¢,4,out); initial begin b=0; c=0; d=0; #10 a=0;b=1;c=0;d=1; #10 a=1;b=1:c=1,d=1; end endmodule Simulation Output:Program no: 1(c & d) ‘Title: Implement Transmission gate and Complex logic gate operation using Verilog HDL switch-level model and simulate the results using test bench. Aim: To implement Transmission gate and Complex logic gate operation using Verilog HDL switch-level model and simulate the results using test bench. Apparatus: Personal Computer, modelsim Flowchart: start 4 Define input and output ports i Define supply rails and wires I Assign nmos and pmos connections input and output connectionsComplex Logic gate: y=(a+b).c Logic diagram : Verilog module Complex Logic gate: module complexg(a.b.c,0; input a,b,c output f; wire wl,w2; supply! pwr; supply0 gnd;nmos ni (w1,gnd,c): mos n2(f,wl.a) nmos n3(F,wl,b); pmos pl (w2,pwraa); pmos p2(f,w2,b); pmos p3(f,pwr.c) endmodule TEST BENCH (Verilog test fixture/STIMULUS): ‘timescale Ins/Ips; module complexg_tb(); reg a,b,c: wire f; complexg uut(a,b,c,f); initial begin a=0;b=0;c=0; Result: The verilog code for Transmission gate and complex logic gate has been written and simulated using test benchProgram no: 2(a) Title: Implement the Half Adder, Full adder circuits using Verilog HDL gate-level mode! and by simulating using test bench. Aim: To implement the Half Adder, Full Adder circuits using Verilog HDL gate-level model and simulating the results using test bench. Apparatus: Personal Computer modelsim start Define input and output ports Assign the inputs and outputs ports to adder 0 0 Input2: b ‘Output: Output2: Sum Cant _ 0 1 0 i 0 1 0 0 1 ‘or Sum:For Carry: b a 0 1 0 1 1 expression: sum=a ® b carry= ab Block diagram: Sal Half Adder ——— sum |————> carry —— b Logic diagram: | a | carry —> b Verilog Module ( Half Adder Gate-level model):module hffa, b, carry, sum); input a; input b; output carry; output sum; xor x1 (sum, a, b); and al (carry, a, b); endmodule Design Block: Module hf(a, b, sum, carry); input a, b; output sum, carry; assign sum= a “ b; assign carry= a & b; endmodule Verilog Test Fixture(test bench): “timescale Ins/1ps; module hf_tb; reg a; reg b; wire carry; wire sum; hf uut (a,b,sum,carry); initial begin #1 a=0; b=0; #1 a=1;b=0; #1 b=1;b=1; end endmodule model):ol i ee CLS TT} Fy | oa ee a) 4 ce la _ ey) CTBEST wef Full Adder: Truth table: Inputl: a Input2: b Inputs: cin Outputl: ‘Output2: Sum Carry 0 0 0 0 a 0 0 1 1 0 0 T 0 1 0 0 T 1 0 1 T 0 0 1 0 1 0 1 0 1 1 1 0 0 L i T 1 1 IK-Maps: For sum: bein 00 ol lL 10 1 1 a 1 1 1 For carry: bcin a 00 ol i 10Logic Expressions: sum=a @®b © cin carry=a.b+ be+ea Logic diagram: a b —> sum ——+ cin a b b carry a —T~ — }— Verilog Module (Full Adder Gate-level Model): module fulla(a,b,c,s.ca): Input a,b,c; output s,ca; wire wl,w2,w3; xor x1(3,a,,0); and al (w1,a,b); and a2(w2,b,0): and a3(w3,c,a); or 01 (ca,w1,w2,w3); Verilog Module (Full Adder dataflow! Model): Module fulla(a, b, cin, sum, carry); input a, b, cin; output sum, carry;assign sum= a*b‘cin; assign carry= (a&b)|(b&cin)|(cin& a); endmodule endmodule Verilog Test Fixture: “timescale Ins/Ips; module fulla_tbQ: initial begin endmodule Simulation Results: “paw h ah Result: The verilog codes for Half Adder, Full Adder circuits has been written and simulated using test bench.Program no:2(b) ‘Title: Implement the logical AOI gate operation using Verilog HDL gate-level model with and without delay and simulate using test bench. Aim: To implement the logical AOI gate operation using Verilog HDL gate-level model and simulate using test bench. Apparatus: modelsim, Personal Computer Flowchart: 0 Define input and output ports and wires Assign the ports to gates Logic Diagram: f=a.b+c.d Feabred Verilog module: module aoig(a.b,cd,f) input a,b,c.d; output f; wire w1,w2,w3; and al (w1,a.b); and a2 (w2,c,d); or 01 (w3,W1,w2): not nl (f,w3);endmodule Neril With delays “timescale Ins/Ips: module aoig_tb0; reg ab, wite f: aoig uut(a,b.c.d,0) test fixture: endmodule Without delays: module aoil-v; reg a,b,c.d: wire f; aoil uut(a,b,c,d); | a-0;b=0;c=0;d=0 yealid=1 end endmodule —_(-in this only last combination o/p will be executed Simulation Output: AOI with delay—all the combination will be executed after some delay called non blocking assignments 109118852 /AE SH = ® weeee Rea ky alte gijsace TaEnun PP aD]AOI without delay: only last combination will be executed bez of not providing the delay, it will overwrite the previous inputs called blocking assignments Te Yr oh te St Boo id eer —— DsU6 O02 MESA) ASSAM] Fey DT eeu AR aD wolisam | gett [Roa mai @])9aea| #0 tes Tepe [ie se Result: The verilog code for AOI gate have been written, simulated with and without delay using test benchProgram no:2(c) Title: Implement the logical OAL gate operation using Verilog HDL gate-level model with and without delay and simulate using test bench. Aim: To implement the logical OAT gate operation using Verilog HDL gate-level model and simulate using test bench, Apparatus: modelsim, Personal Computer Flowchart: start Define input and output ports and wires Assign the ports to gates Logic Diagram: y= _(a+b).(crd) Verilog module: module aoiggta.b.c.d.): input a,b,c.d output f; wire w1,w2,W3:or ol (w1,a,b); or 02(w2,c,d) and al (w3,w1,w2); not nl (f,w3): endmodule Verilog test fixture: With delays “timescale 1ns/Ips; module oaig_tb(); reg a,b,c,d; wire f; oaigg uut(a,b,c,d,0; initial #1 a=Ozb=t #1 aet:b=Le=1sd=1; end endmodule Simulation Output: OAL with delay: All combination will module oail-v; reg aed; wire f; ail wut(a,b,c,d); a=0;b=0;c=0;d=t a=O:b=1: end endmodule a dues] ¢ +> oscamO RE = Reuiey aw anan,OAL without delay: Last combination only will be executed Result: The verilog code for OAI gate have been written and simulated with and without delay using test bench.Program no: 3(a) Title: Design 4:1 multiplexer using verilog HDL behavioral model and simulate the results using test bench. Aim: To design 4:1 multiplexer using verilog HDL behavioral model and simulate the results using test bench Apparatus: Personal Computer,modeisim Flowchart: Define input and output ports and wires | Assign the ports to gates 4:1 MUX: Block diagram: a0) 4:1 MUX all] f al2| a3]Truth table: Select line input: s{1] = 0 0 Select line input2: s{2] + oO Output: a0 all} 1 1 1 0 T al2} a3] [3:0]a are the data inputs, [1:0]s are the select lines input, fis the output line. Module: module mux4tol (a, s,f) input [3:0] a; input [1:0] s; output reg f; always@(*) feal2); else feal3]; endmodule Verilog test Fixture: “timescale Ins/Ips; module mux4to1_tb0: reg [3: reg [1:0] s: wire f; muxdtol unt (a,5,0; initial begin a=4'b1010; s=2'b00;#10 s=2'b01 #10 s=2'b10; #10 s=2'b11 end endmodule Simulation Result: NCCU ee OIL bem eaeProgram no: 3(b) Title: Design 2x4 decoder using behavioural model simulate the results using test bench. ‘Aim: To design 2x4 decoder using behavioural mode! simulating the results using test bench. Apparatus: modelsim, Personal Computer Flowchart P start Define input and output ports and wires ¥ Assign the ports to gatessass 20000/P =2002-=00/) 2onos0-0/P s=coo0oo00 oD oez-ccc000/D ceos=cc000 09D eoos=c0000/9 io oeoco=000/9 s cooc0os00/9 ooooco=0/9 is ceooooco3D Source Code-: module dec38(a.d); input [2:0]a; output reg{7:0}d; always@(*) begin case(a) 3'b000:b=8'b00000001 ; 3'b001:b=8'b00000010: 3'b010:b-8'b00000100; 3'bO1 1:b=8'b00001000; 3'b100:b=8'b00010000; 3'b101:b=8'b00 100000, 3'b110:b=8'b01000000; 3'b111:b=8'b10000000, endease end endmodule Test Bench: “timescale Ins/1ps; module dec38_tb0) reg [2:0]; wire reg[7:0]d; dec38 wut (ad);initial begin endmodule Simulation Results: a Seam aes = > @)/ eaaa,Program no: Title: Implement the following using behavioral verilog model, simulate the results using test bench. (a) D flip flop, (0) T flip flop. Aim: To implement the following Flip-Flops using behavioral verilog model, simulate the results using test bench. (a) D flip flop, (b) T flip flop. (JK flip flop. Apparatus: Personal Computer,modelsim Flowchart: Define input and output ports and wires Assign the ports to flip flop D- Flip flop: Block Diagram: D flip —T*| flop —, q lt resetn— qe gn x 0 0 0 0 1 T 1 0 1 1 ‘T.Hlip flop: Block Diagram: T flip flop rst Characteristic Table: Rst Clk a qui 1 t x 0 0 | 0 0 + 0 + | 0 1 o LT | 1 1 9 | 1 0output reg q; always @(posedge clock) if(resetn) q<=0; else q<=d; endmodule Verilog test fixture: “timescale 1ns/Ips; module dflipflop tb; reg d:; reg clock; reg resetn; wire q; dflipflop uut (d,clock,resetn,q); always #1 clock=~clock; initial begin clock=1; resetn=0; d=1; #1 resetn=1; d=0; #1 resetn=0; d=0; #1 resetn=0;an oaamleeoe Rash 6) eaan Janne a T flip flop Verilog module: module tffi(t, clock, resetn, q): input t; input clock; input resetn; output reg q; always@ (posedge clock) if(resetn == 1) 4-0; else begin if(t ) q=-4 else q=4 end endmodule Verilog test fixtu timescale Ins/Ips:module tffd_tb() reg t; reg clock: reg resetn; wire q. {ff uut(t,clock.resetn,q); always #1 clock = ~clock: initial begin clock= 1; resetn = 1; t=0; 150810852 AE GR) we ‘| SHAM) eo Wee uN Ae ay Soliman w/e ES Rabe a) aaeaProgram no: 4(a) 4-input AND gate using CMOS 2-input NAND and NOR gates using iB. Aim: To Constructing a 4-iny using mixed level modeling. Title omenieting a mixed level modellin, put AND gate using CMOS 2-input NAND and NOR gates Apparatus: Modelsim, Personal Computer Flowchart Define input and output ports and wires Assign the ports to gates leve ror level and level am:Verilog module: module and4(a.b.c.d,y): input a,b,c; output y; wire wl, w2,w3,w4; supply! pwr; supply0 gnd; nmos nl (w3,w1,a); nmos n2(w1,gnd,b); mos n3(w/,w2,0); nmos n4(w2,gnd,d); pmos pl (w3,pwr.a); pmos p2(w3,pwr,b); pmos p3(w4,pwr,c); pmos p4(w4,pwr.d); nor n5(y,w3,w4); endmodule Test bench code: module and4_tb; reg a: reg b; reg.c; reg d; wire y; and4 uut (a,b,c.d,y); initial begin aoe "onon ses #1; a=0; b=0;end end module Result; Constructed a 4-input AND gate using CMOS 2-input NAND and NOR gates and simulated using test bench.Program no: 4(b) Title: Constructing a decoder using CMOS 2-input AND gates and NOT gates etc. using mixed level modelling. Aim: To Constructing a decoder using CMOS 2-input AND gates and NOT gates etc. using mixed level modeling. Apparatus: modelsim, Personal Computer Flowchart a Define input and output ports and wires Assign the ports to gates Logic Diagram: A BK SE AND Gate Inverter = AB A Q, = AB Binary Decoded Inputs ai Output Q:= AB 8 Qs = AB Data Lines Transistor I id gate levelvs module: module decs(a,b,d0,d1,d2,d3); input a; input b; output d0,d1,d2,d3; supply! pwr: supply0 gnd; wire w1,w2; mos ni (w1,gnd,a); pmos pI (w1,pwr.a); nmos n2(w2.gnd,b); pmos p2(w2,pwr.b); and al (d0,w1,w: and a2(d1,w1,b); and a3(d2,a,w2); and a4(d3,a,b); endmodule Verilog test fixture(Test bench): timescale Ins/1ps; module dees_tb(); reg a: reg b; wire d0,41,42,43;decs uut(a,b,d0,d1,d2,d3); initial begin a-0;b-0; #1 a=O:b=1; #1 a=1:b=0; #1 a=1;b=1 end endmodule Simulation output: Result: 2x4 decoder using mixed level modeling has been designed and Simulated the result using test bench and results are obtained.Program no: 5 Title: Implement and synthesize 4bit Full adder (ripple carry adder ) and carry look ahead adder circuits in verilog HDL, simulate the results using test bench. Aim: To implement 4bit Full adder circuit in verilog HDL, simulate the results. Apparatus: Modelsim, Personal Computer Theory: An N- bit ripple carry adder requires N number of full adder circuits.A ripple carry adder is a digital circuit that produces the arithmetic sum of two binary numbers.A ripple carry adder is a logic cireuit in which the carry-out of each full adder is the carry-in of the succeeding full adder. It is called a ripple carry adder because each carry bit gets rippled into the next stage. Propagation delay is time elapsed between the application of an input and occurrence of the corresponding output. The carry propagation delay is the time elapsed between the application of the carry in signal and the occurrence of the carry out (Cout) signal. lowchart. Define input and output ports and input-output ports + Assign the ports to adder stages Block Diagram 4-bit full adder: [3:0] [> [3:0]sum [3:0]b Ripple Carry Adder Cin [> ontFull Adder 4 Full Adder 3 Full Adder 2 Full Adder 4 in| Cout Cin Cout Cin} ICout ICout Cout Cin Submodule(Full Adder): A Cour B| ADDER s Cw ‘Sum = A xor B xor Cin Carry =A.B+B.Cin+ Cin.AFor sum: bein a 00 ol ra 10 | Ol | 1 For carry: bein A 00 01 1 10 Logic Expressions: carry=a.b+ b.cin+cina Logic diagram: ram: a ——+ \—> sum b———> cincin cin a 2 Verilog Module: Structural modelling(bottom-top design method): module fulladdr(a,b,c,s,ca); //submodule input a,b,c; output s,ca; assigns =a“b*c; assign ca = (a&b) | (b&c) | (c&a): endmodule module rca(a,b,cin,sum,carry ); /Aop module:in this ,we call submodule program 4 times input [3:0]a ; input [3:0]b ; input cin; output [3:0]sum ; output carry ; wire c0,cl,c2; fuladdr f0(a[0],b[0} ,cin,sum|[0},cO); fulladdr f1 (a[1],b{1],cO,sum[1],c1);fulladdr £2 (a[2],b[2],cl,sum|2],c2); fulladdr £3 (a[3],b[3],c2,sum[3] carry); endmodule Verilog test fixture: “timescale Ins/1 module rec_tb(); reg [3:0]a,b; reg cin; wire [3:0]sum: wire carry: rec uut(a,b,cin,sum,carry); initial begin a=4'b1010; b=4'b0010; cin = 0; #1 a=4'b1110; b=4b1001; cin=1; end endmoduleTheory: Carry-Lookahead Adder (CLA) improves speed by reducing the amount of time required to determine carry bits. In CLA, the carry bit is calculated alongside the sum bit without waiting for the previous carry. The CLA calculates one or more carry bits before the sum, which reduces the wait time to calculate the result of the larger value bits. Carry lookahead logic uses the concepts of generating and propagating carries. G=AB P=A xor B Cra = Gre (PLC) Ci> carry bit of digit and Pi > propagate bit of digit / Gi> generate bit of digit / ‘The sum of the adder is given as Sumi] = Pli] xor Cli] ‘The equations for carry are: C1 =Got+ Py Co C2 =G, +P -Cy C3 =G2+ Pr Cr Cy = G3 + Ps Cy On substituting, we get the expanded equations Cy =Go+ Py Cy Cr =Gi +Go-Pi+Ou-Pa- Ph Cs = G2 +Gi-Pe+Go- Pi: Prt Cy Py Py + Py C4 = Gs + Ga Py + Gy Pa Py t+ Go» Py- Pa: Py t+ Cy: Py Py Pa- Ps Source Code: module cla(a.b,cin,sum,carry); input [3:0] a;input [3: input cin; output [3:0] sum; output carry; wire [3:0]p,g; wire [2:0]cy; assign p=a"b: assign g=aéb; assign sumn|0] = p[O]"cin, sum[1] = p[1]*cylol, sum[2] = p[2]*cy[1], sum|3] = p[3}*cy[2]; assign cy[0]= g[0}|(p[0] &cin), cy[11= U1] (PL & gO) |(pl11&pt0] &cin), cyl2}= gl21](Pl21 >11)|(pl21 &pl 1] &gl0}) |(pl2}&pl 1] &p{0) &cin); assign carry = 831 \(pl3] &gl2))|(pI3] &p[2] &g{1}) |(pI3] &pl2] &pi1] &gl0})| (pl3] &pl2] &p|1] &plO] &cin); endmodule Test Bench: module cla_tb; reg [3:0] a, b; reg cin; wire [3:0] sum; wire carry; cla uut(a,b,cin.sum.carry); initial begin a-4b1011:Result: 4-bit full adder (ripple carry adder) and 4-bit Carry Look ahead Adder are designed and Simulated the result using test bench.Program No: 6 Aim: To Design 4-bit sequence detector to detect the sequence from 1101 using mealy final state machine. Apparatus: Xilinx 13.2, Personal Computer Flowchart: Define input and output ports and wires Assign the ports to Theory: ‘A 1101 sequence detector detects 1101 consecutive bits in a string of binary bits. In the design of 1101 sequence detector, involves 5 states. State SI: Beginning at state $1 when 0 is received it stays in the same. When I arrives when in state SI, then it goes to next state S2 and it remembers that 1 was received which is part of the sequence 1101 which is to be detected. State $2:‘When in state S2, when 1 arrives, since it is part of the sequence it goes to next state S3, meaning it remembers 1. When 0 is received it cannot go to next state S3 and it cannot remain in the same state S2 because this would mean 010 indefinite loop while in state S2, therefore it goes back to the initial state S1, State $3: When in state S3, when 0 is received then since it is part of the sequence 1101 it goes to new state S4 because the machine has to remember the new bit 0 as part of the sequence detection algorithm. When 1 is received it stays in the same state. State S4: When in state $4, when 1 is received then since it is part of the sequence 1101 to be detected {it goes to S2. And when 0 is received then it goes back to initial state S1. At this point the machine outputs I, Source Code: module seqdec(clk,rst,w,2); input clk,rst,w: output reg z; reg [2:0}ps.ns; parameter a: always@ (posedge clk, posedge rst) begin iftst) ps <=a; else ps <=ns; end always@(*) begin case(ps) azif(w) ns<=b; else ns <= a; bi iff) ms<= else ns <=a; c:if(-w) ns else ns d: begin i) begin zal; ns end elsens <= ai end endcase end endmodule Test Bench: timescale Ins/Ips; module seqdet_tb( ) reg clk, rst, w; wire z seqdec nut (clk,rst,w,2) initial begin clk = 0; rst = 1 w=0; #2 rst = 0; end initial begin #lwe=l #1 w=0; #1 w=1; #1 w=0 end always #5 clk = -clk; endmodule Simulation Results Result: 4-bit sequence 1101 is detected and the output is verified. RTL for the same is obtained.