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Datasheet
Advance Information
Synchronous Buck Controller
with Auto Power Saving
Mode and Built-In LDO
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NCP81148 is a dual synchronous buck controller that is optimized
for converting the battery voltage or adaptor voltage into multiple
power rails required in desktop and notebook system. NCP81148 MARKING
consists of two buck switching controllers with fixed 5.0 V output on DIAGRAM
channel 2, 3.3 V on channel 1 and two on−board LDOs with three
outputs: 5 V / 60 mA and 3.3 V or 12 V / 10 mA. NCP81148 supports 1 81148
ALYWG
high efficiency, fast transient response and provides power good 28 PIN QFN, 4x4 G
signals. ON Semiconductor proprietary adaptive−ripple control MN SUFFIX
enables seamless transition from CCM to DCM, where converter runs CASE 485AR
at reduced switching frequency with much higher efficiency at light
81148 = Specific Device Code
load. The part operates with supply voltage ranging from 5.5 V to A = Assembly Location
28 V. NCP81148 is available in a 28−pin QFN package. L = Wafer Lot
Y = Year
Features W = Work Week
• Wide Input Voltage Range: from 5.5 V to 28 V G = Pb−Free Package
• Built−in 5 V / 60 mA LDO (Note: Microdot may be in either location)
• Built−in selectable 3.3 V or 12 V / 10 mA LDO
• Three Selectable Fixed Frequency 300 KHz, 400 KHz or 600 KHz
PIN CONNECTIONS
• 180 Interleaved Operation Between the Two Channels in
5V_LDOOUT
5V_LDOBYP
LDO2_OUT
5V_LDOEN
Continue−Conduction−Mode (CCM)
LDO2_EN
• Selected Power−Saving Mode/Forced PWM Mode
SKIP
• Transient−Response−Enhancement (TRE) Control
VIN
• Input Supply Voltage Feed Forward Control 28
• Resistive or Lossless Inductor’s DCR Current Sensing GH2
1
GH1
• Over−Temperature Protection BST2 BST1
SWN2 SWN1
• Internal Fixed 8.5 ms Soft−Start GL2 GND GL1/FSET
• Fixed Output Voltages 5 V and 3.3 V PGND2 PGND1
CSP2 CSP1
• Power Good Outputs for Both Channels CSN2 CSN1
• Built−in Adaptive Gate Drivers
• Output Discharge Operation
FB2
COMP2
EN1/SS1
PG
COMP1
FB1
EN2/SS2
Applications
ORDERING INFORMATION
• Desktop / Notebook Computers
Device Package Shipping†
• System Power Supplies
NCP81148MNTWG QFN−28 4,000 /
• I/O Power Supplies (Pb−Free) Tape & Reel
VIN 5V_LDOOUT
−
+ +
5V_LDOEN ENABLE − 5V_LDOBYP
LDO LDO2_OUT
VREF
−
+
LDO2_EN ENABLE
SKIP
CSP1 + CSA
CSN1 − BST1
Control Logic
Ramp Generator GH1
And
COMP1 Vbias PWM Logic
SW1
VREF
+ E/A
SS
FB1 −
OC & TRE Detection 5V_LDOOUT
UVLO,
UVP, OVP,
EN1 Power Good GL1/
PG1 Vbias FSET
PG OCP, TSD and
Protection PGND1
GND PG2 VIN
Switcher 1 Shown
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NCP81148
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NCP81148
5V_LDO LDO2_OUT
(3.3 V)
10 K VIN
10 K
EN5
VOUT1 SKIP
5V_LDOOUT
5V_LDOBYP
LDO2_OUT
5V_LDOEN
22 mFx2
LDO2_EN
SKIP
VIN
28 27 26 25 24 23 22
GH2
GH1
BST2 1 21
Vout2 0.1 mF BST1
2 20 0.1 mF 3.3 mH Vout1
5.0 V / 6.0 V SWN2 3.3 V / 6.0 A
3 SWN1
19
GL2 GL1/FSET
4 AGND 18
PGND2 PGND1
5 17
CSP2
6 16 CSP1
CSN2 CSN1
7 15
8 9 10 11 12 13 14
FB2
FB1
COMP1
COMP2
EN1/SS1
EN2/SS2
PG
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NCP81148
LDO2_OUT Current 10 15 mA
SUPPLY CURRENT
BSTx Quiescent Current IBST VFB = 1.5 V, EN = 5.0 0.3 mA
(No Switching), GH and GL are open
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NCP81148
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NCP81148
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NCP81148
DETAILED DESCRIPTION
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NCP81148
Forced Pulse Width Modulation (FPWM Mode) Over Voltage Protection (OVP)
The device is operating as force PWM mode if SKIP is When VFB voltage is above 110% (typical) of the
tied to VCC. Under this mode, the low−side gate driver nominal VFB voltage, the top gate drive is turned off and the
signal is forced to be the complement of the high−side gate bottom gate drive is turned on trying to discharge the output.
driver signal. This mode allows reverse inductor current, in It over voltage condition still exists after 1.5 ms, an OV fault
such a way that it provides more accurate voltage regulation is set. The power good will go low at the same time. The
and better (fast) transient response. During the soft start bottom gate drive will be turned off when VFB drops below
operation, the NCP81148 automatically runs as FPWM the under voltage threshold. If then over voltage condition
mode regardless of the SKIP setting at either FPWM or happens again, the high side MOSFET stays off and low side
SKIP mode to make sure to have smooth power up. MOSFET will turn on again till output voltage drops down
to under voltage threshold. Then low side gate will be off.
Power Save Mode (Skip Mode) EN resets or power recycle the device can exit the fault.
If the load current decreases, the converter will enter
power save mode operation when SKIP pin is grounded. Under Voltage Protection (UVP)
During power save mode, the converter skips switching and An UVP circuit monitors the VFB voltage to detect under
operates with reduced frequency but with minimum voltage event. The under voltage limit is 50% (typical) of the
switching frequency of 33 KHz, which minimizes the nominal VFB voltage. If the VFB voltage is below this
quiescent current and maintains high efficiency. If SKIP pin threshold over 1 ms, an UV fault is set and the device is
is open, the channel 1 will enter power saving mode with latched off such that both top and bottom gate drives are off.
reduced load but with minimum switching frequency of EN resets or power recycle the device can exit the fault. UVP
33 KHz and channel 2 will stay in forced PWM mode. is delayed for soft start period (8.5 ms) after EN goes high.
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NCP81148
L V O @ (V in * V O)
DCR I LIM + I LIM(Peak) *
Vin Vout 2 @ V in @ f SW @ L
Rs1 C where Vin is the input supply voltage of the power stage, and
fsw is normal switching frequency.
Rs2 Fig. X+1 shows NTC resistor network to compensate the
temperature drift of DCR.
If inductor current exceeds the current threshold, the
high−side gate driver will be turned off cycle−by−cycle. In
the mean time, an internal OC fault timer will be triggered.
+ Vc − If the fault still exists after 16 clocks, the part latches off,
Figure 3. X both the high−side MOSFET and the low−side MOSFET are
turned off. If the sensed current reaches 60 mV, the part will
L latch off right away. The fault remains set until the system
Vin DCR Vout has shutdown and re−applied VCC and/or the enable signal
EN is toggled.
R C
Pre−Bias Startup
R2 In some applications the controller will be required to start
R1
switching when its output capacitors are charged anywhere
from slightly above 0 V to just below the regulation voltage.
RTHE RNTC This situation occurs for a number of reasons: the
converter’s output capacitors may have residual charge on
+ Vc − them or the converter’s output may be held up by a low
Figure 4. X + 1 current standby power supply. NCP81148 supports pre−bias
The Rs1, Rs2 and C can be calculated as: start up by holding Low side FETs off till soft start ramp
reaches the FB pin voltage.
C @ ǒR S1ńńR S2Ǔ + L
DCR Thermal Shutdown
The inductor peak current limit is: The NCP81148 protects itself from over heating with an
internal thermal monitoring circuit. If the junction
V th_DC R S2
I LIM(Peak) + , where k + temperature exceeds the thermal shutdown threshold the
k @ DCR R S1 ) R S2 voltage at the COMP pin will be pulled to GND and both the
upper and lower MOSFETs will be shut OFF.
The DC current limit is:
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NCP81148
PACKAGE DIMENSIONS
ÇÇÇÇ
NOTES:
D A B L L 1. DIMENSIONING AND TOLERANCING PER ASME
ÇÇÇÇ
Y14.5M, 1994.
PIN ONE 2. CONTROLLING DIMENSION: MILLIMETERS.
REFERENCE 3. DIMENSION b APPLIES TO PLATED TERMINAL
ÇÇÇÇ
L1 AND IS MEASURED BETWEEN 0.15 AND 0.30 MM
FROM THE TERMINAL TIP.
ÇÇÇÇ
4. COPLANARITY APPLIES TO THE EXPOSED PAD
DETAIL A AS WELL AS THE TERMINALS.
ALTERNATE TERMINAL
E CONSTRUCTIONS MILLIMETERS
ÉÉ
DIM MIN MAX
A 0.80 1.00
EXPOSED Cu MOLD CMPD A1 0.00 0.05
ÉÉ
A3 0.20 REF
0.10 C b 0.15 0.25
D 4.00 BSC
D2 2.50 2.70
0.10 C DETAIL B
TOP VIEW ALTERNATE
E 4.00 BSC
E2 2.50 2.70
CONSTRUCTION
A e 0.40 BSC
DETAIL B
K 0.30 REF
A3 L 0.30 0.50
0.10 C L1 −−− 0.15
0.08 C
NOTE 4 A1 SEATING
SIDE VIEW C PLANE
0.10 C A B
RECOMMENDED
DETAIL A D2 MOUNTING FOOTPRINT
K 4.30
8
28X
2.71
15 0.10 C A B 0.62
28X L
1
E2
2.71 4.30
1
PIN 1
INDICATOR 22
e 28X b PACKAGE
OUTLINE 28X
0.07 C A B 0.40 0.26
BOTTOM VIEW 0.05 C NOTE 3 PITCH
DIMENSIONS: MILLIMETERS
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