UNIDIRECTIONAL SINGLE-PHASE AC-DC-AC

THREE-LEVEL THREE-LEG CONVERTER

A PROJECT REPORT

Submitted by

DHARISH S (311617105006)
KRISHNASWAMY G (311617105011)
LOKESH S (311617105013)
in partial fulfillment for the award of the degree

of

BACHELOR OF ENGINEERING

IN

ELECTRICAL AND ELECTRONICS ENGINEERING

MISRIMAL NAVAJEE MUNOTH JAIN ENGINEERING COLLEGE

ANNA UNIVERSITY: CHENNAI 600 025

APRIL 2021
 ANNA UNIVERSITY: CHENNAI 600 025

BONAFIDE CERTIFICATE

Certified that this project report “UNIDIRECTIONAL SINGLE-PHASE

AC-DC-AC THREE-LEVEL THREE-LEG CONVERTER” is the bonafide
work of “DHARISH S (311617105006), KRISHNASWAMY G
(311617105011) & LOKESH S (311617105013)” who carried out the project
work under my supervision.

SIGNATURE SIGNATURE
Dr. N. GNANASEKARAN Dr. N. GNANASEKARAN
HEAD OF THE DEPARTMENT SUPERVISOR
Professor Professor
Department of Electrical and Department of Electrical and
Electronics Engineering Electronics Engineering
Misrimal Navajee Munoth Jain Misrimal Navajee Munoth Jain
Engineering College Engineering College
Thoraipakkam, Chennai-600 097 Thoraipakkam, Chennai-600 097

Submitted for Anna University viva-voce examination held on _________

INTERNAL EXAMINER EXTERNAL EXAMINER

 ACKNOWLEDGEMENT

We express our gratitude to Chairman Shri. LALCHAND MUNOTH for

providing us all the infrastructural facilities to complete our project work.

We extend our sincere thanks to the Secretary: Administration Dr. HARISH L

METHA and to the Secretary: Academic & Finance Shri. JASWANT
MUNOTH for providing us an opportunity to pursue this project work.

We sincerely thank our Principal Dr.C.CHANDRASEKAR CHRISTOPHER

for creating an atmosphere conducive to the studies that enabled us to complete
this project work.

We owe our deep gratitude to our Project Supervisor

Dr.N.GNANASEKARAN, Professor and Head, Department of Electrical and
Electronics Engineering who took a keen interest in our project work and
guided us all along, till the completion of our project work by providing all the
necessary information and knowledge.

We are thankful and fortunate enough to get constant encouragement, support,

and guidance from all the Teaching and Non-Teaching staff of the Department
of Electrical and Electronics Engineering who helped us in the successful
completion of our project work. We thank our parents and all our friends for
their moral support and encouragement.
 ABSTRACT
The converter is composed of a unidirectional Neutral Point Clamped leg

(NPC) and two bidirectional NPC legs. A bidirectional NPC leg is shared

between the rectifier and inverter sides. Compared with the two-level leg, the

three-level leg presents voltage stress reduction on switches for the same

DC-link voltage level and also allows a reduction in harmonic distortion for the

same switching frequency. Also, a method for balancing DC-link capacitor

voltages is shown. As the converter is unidirectional, the grid current and the

generated voltage at the load side must be synchronized with generated voltage

on the grid side. That eliminates the zero-crossover distortion in the grid current

caused by the use of diodes without hysteresis control.

iv
 TABLE OF CONTENTS

S.No. Content Pg.No.

Abstract iv
Table Of Contents v
List Of Figures vii
List Of Tables viii

1. Introduction 1
1.1 General 1
1.2 Organization of the Project Report 2

2. Literature Survey 4
2.1 Paper 1 4
2.2 Paper 2 4
2.3 Paper 3 5
2.4 Paper 4 6
2.5 Paper 5 6

3. Description Of The Project 8

3.1 Existing System 8
3.2 Proposed System 8
3.3 Working of the Proposed System 9
3.4 Hardware Components 10
3.4.1 Microcontroller 10
3.4.1.1 High-Performance Modified RISC CPU 13
3.4.1.2 DSP Engine Feature 14
3.4.1.3 Peripheral Feature 14
3.4.1.4 Motor Control PWM Module Feature 15

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 3.4.1.5 Quadrature Encoder Interface Module Feature 15
3.4.1.6 Analog Feature 15
3.4.1.7 Special Microcontroller Feature 15
3.4.1.8 CMOS Technology 16
3.4.2 Driver Circuit 16
3.4.2.1 Pinout Diagram & Configuration of TLP250 17
3.4.2.2 Pins Function 17
3.4.2.3 Electrical Features & Specifications 19
3.4.3 MOSFET 19
3.4.3.1 MOSFET Operating Principle 20
3.4.3.2 Features 21
3.4.4 Software Requirement 22
3.4.4.1 MATLAB 22
3.4.4.2 MATLAB System 22
3.4.4.3 Graphics 23
3.4.4.4 MATLAB Documentation 24
3.4.4.5 MATLAB Library 24

4. Results and Simulation 26

4.1 General 26
4.2 Simulation Diagram Of The Project 26
4.3 Simulations Results 27
4.3.1 Input Waveform 27
4.3.2 Output Waveform 27

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 4.4 Final Model of Project 28

4.5 Hardware output 29

4.6 Applications 30
30
4.6.1 UPS
31
4.6.2 Universal Active Power Filters
31
4.6.3 Power line conditioners

5. 32
Conclusion
33
5.1 References

vi
 LIST OF FIGURES

S.No. Figure Pg.No.

1. Existing System: Two-level Four Leg Converter 7

2. Proposed System: Three-level Three Leg Converter 9

3. Pin-Diagram: dsPIC30F2010 12

4. Pin-Diagram: TLP250 17

5. Pin-Diagram: IRF840 20

6. MATLAB UI 23

7. MATLAB Simulink Library 25

8. Three-level three-leg converter MATLAB simulation 26

9. Input AC Waveform from Grid 27

10. Three-level Output Waveform 27

11. Finalized model of single phase ac dc ac converter 28

12. Pulse for Mosfet 29

13. Output waveform 29

14. Block diagram of UPS 30

15. Power conditioner 31

vii
 LIST OF TABLES

S.No. Table Pg.No.

1. Pin Configuration: dsPIC30F2010 12

2. Pin Configuration: TLP250 18

3. Pin Configuration: IRF840 21

viii
 CHAPTER 1:INTRODUCTION

1.1: GENERAL

Single-phase AC-DC-AC converters have their use widespread in several

applications, such as line conditioners, universal active power filters, standby
power supplies, and uninterruptible power supplies (UPS), connecting sensitive
loads that need stable AC voltage (e.g., computers, communication equipment,
and biomedical instrumentation, etc.) to weak or disturbed supplies. Several
single-phase converters have been studied in the literature with the goal of
feeding single-phase AC loads, such as electric motors and electronic
equipment. An uninterruptible power supply system usually employs a
single-phase AC-DC-AC two-level three-leg converter. Alternatively, the
two-level legs can be replaced by three-level Neutral Point Clamped (NPC)
legs. The NPC leg presents some advantages regarding the two-level leg, such
as:

i) voltage reduction on the switches

ii) lower dv/dt stress in the semiconductors
iii) reduction in switching losses and
iv) lower harmonic distortion

One of the problems of using an NPC-type leg is the unbalance of

DC-link capacitor voltages due to the midpoint connection. Some techniques of
balancing DC-link capacitor voltages were developed, such as an additional
controller and space-vector PWM strategy.

In applications where the power flow is unidirectional, in order to reduce

the converter costs (consequently fewer drivers), the controlled switches (e.g.,
Insulated Gate Bipolar Transistor (IGBT)) can be replaced by non-controlled
switches (e.g., diodes) at the rectifier side, where it can still obtain low

1
harmonic distortion, low losses in the semiconductors and high-power factor. In
order to reduce the harmonic distortion, multilevel voltages can be obtained
using both controlled switches and diodes.

A three-phase unidirectional rectifier is presented based on three

unidirectional NPC legs composed of two controlled switches and four
uncontrolled switches (i.e., diodes). In a unidirectional three-phase,
series-connected converters are proposed using three-level legs with reduced
active switch count. Two three-phase unidirectional open-end AC-DC
configurations are proposed, in which some active switches are replaced by
diodes. The influence of dead-time in the AC current quality of AC-DC
converters is studied. It is proposed in a high-efficiency three-level bridgeless
rectifier with power factor correction.

This project presents a new unidirectional single-phase AC-DC-AC

three-level three-leg converter. The converter is composed of a unidirectional
NPC leg and two bidirectional NPC legs, where a bidirectional leg is shared
between the grid and load side. The proposed converter has similar
characteristics regarding the conventional three-level topology and better
performance compared with the conventional two-level converter. A suitable
model, PWM, and control strategies of the proposed topology are presented, as
well as the voltage balance of the DC-link capacitors realized by the vectorial
PWM. In addition, detailed analysis and comparison with the conventional
configurations are performed. Simulation and experimental results are also
presented.

2
1.2: ORGANISATION OF THE PROJECT REPORT

This project report is organized into five chapters. Chapter 1 introduces

the main concepts and the objectives of the project. It also gives an introduction
to the AC-DC-AC converter. It also includes the organization of the thesis.
Chapter 2 is the literature survey. It explains the important concepts described in
the various papers that were used as references for this project. Chapter 3 gives
a general description of the project. The first part of the chapter describes the
existing model and compares it with the proposed model. It explains the
drawbacks of the existing model and how these drawbacks have overcome in
the proposed system. The second part of this chapter shows the hardware design
and also gives details of the various components used in the hardware. Chapter
4 gives the results obtained in this project. It also shows the applications and
various location obtained after simulation for both the proposed system. This
chapter also describes the simulation circuit diagram of the proposed system.
Chapter 5 is the conclusion of this project. The last part of this project is the list
of references.

3
 CHAPTER 2: LITERATURE SURVEY

2.1: PAPER 1
Chung-Chuan Hou, Hsin-Ping Su "A multi-carrier PWM for AC-DC-AC
converter without DC link electrolytic capacitor", 2014 International Power
Electronics Conference (IPEC-Hiroshima 2014 - ECCE ASIA).

This study proposes a multi-carrier pulse width modulation (PWM) for

AC-DC-AC converter without DC link electrolytic capacitor. The AC-DC-AC
converter consists of an AC-DC active front-end converter, a DC-AC voltage
source inverter, and a 10uF ceramic capacitor in dc link. The DC bus voltage
controller with load compensator is utilized to maintain the voltage of the DC
link capacitor at the designed value. Furthermore, the multi-carrier PWM is
utilized to reduce the common-mode voltage (CMV) of AC-DC active front-end
converter and DC-AC inverter. The simulation and test results are presented to
validate the performances of the proposed scheme.

2.2: PAPER 2
Anil Kumar Yadav, Rajesh Gupta, Shweta Gautam "AC/DC/AC converter based
on parallel AC/DC and cascaded multilevel DC/AC converter", 2012 Students
Conference on Engineering and Systems.
This paper presents a single-phase AC/DC/AC converter based on
parallel AC/DC and cascaded multi-level DC/AC Converter. For a two-cell
AC/DC/AC converter, two units of full-bridges are connected in parallel and
two units of half-bridges are connected in cascade. It is proposed that instead of
using two separate control loops of DC link voltages at the AC to DC
conversion stage, only a single control loop with only one voltage sensor is
proposed in this paper when two cells are equally loaded. It is also shown that
by controlling only one cell DC link voltage, the other dc-link voltage also gets

4
controlled automatically. In addition, the power factor is also improved to unity
at the AC side of the AC/DC conversion stage. The use of simple and unipolar
ramp comparison control at both stages leads to fixed switching frequency
operation of all the switches along with the improved quality of input current
and the output voltage is compared to simple PWM control. The simulation
result for the proposed topology has been obtained through the
PSCAD/EMTDC simulation studies, for a two-cell-based parallel cum cascaded
AC/DC/AC converter. The experimental verification of the proposed topology
and control strategy has been obtained using LABVIEW FPGA module with the
help of the PCI-7831R data acquisition board.

2.3: PAPER 3

Jianlin Zhu, Lidan Xiang, Shasha Liu, Xiaoping Zhang "Study of Sepic
AC-DC-AC matrix converter based on AC chopper principle", 2008 7th World
Congress on Intelligent Control and Automation.

A new AC-DC-AC matrix converter topology based on Sepic is

proposed. The basic configuration of the new topology and its fundamental
principle is firstly introduced, the analytic expression on the function of voltage
transfer ratio and the duty cycle is analyzed, and the rationale of the double-loop
control strategy is clarified. Finally, the validity and feasibility of the new
topology are tested by means of computer simulation and prototype
experiments. The results indicate that the regulation of the voltage transfer ratio
and output frequency can be realized by the new converter, furthermore, the
system can be started well and the harmonic distortion of the waveform is
lower. So, the inherent drawback of the low voltage transfer ratio of the
traditional matrix converter is effectively settled.

5
2.4: PAPER 4

Hiroki Takahashi, Jun-ichi Itoh, Takumi Mura "Investigation of switching loss

reduction for the matrix converter based on virtual AC/DC/AC conversion
using space vector modulation", 2012 IEEE 13th Workshop on Control and
Modelling for Power Electronics (COMPEL).

This paper proposes a space vector modulation based on the virtual

AC/DC/AC conversion method for a matrix converter to reduce the switching
loss. The switching loss of the matrix converter is not decided by only the
number of switching times but also depending on the voltage and current in the
selected switching devices based on the modulation. The proposed method can
minimize the maximum instantaneous switching loss which is caused by the
selection of switching state with the absolute maximum values in the input
voltages and the output currents. This can be achieved by changing over the
zero-vectors of virtual inverter in the proposed method. In this paper, the loss
characteristics of the matrix converter using the proposed method are
demonstrated experimentally. From the experimental result, it was confirmed
that the proposed method can reduce the losses by 23.9 % in comparison with a
conventional space vector modulation method.

2.5: PAPER 5

Antonio de Paula Dias Queiroz, Cursino Brandão Jacobina, Nayara Brandão

de Freitas, Ayslan Caisson Noroes Maia, Victor Felipe Moura Bezerra Melo
"Single-Phase AC–DC–AC Multilevel Converter Based on H-Bridges and
Three-Leg Converters Connected in Series", IEEE Transactions on Industry
Applications.

This paper investigates an ac-dc-ac multilevel power converter. The

studied configuration is composed of two single-phase ac-dc-ac three-leg

6
modules and series-connected H-bridges in the shared part of the system.
Because the proposed converter has shared legs between the input and output, it
is employed in applications with the same input and output frequency.
Uninterrupted power supply and unified power quality conditioner are
application examples for this converter. Such multilevel topology has a lower
dc-link voltage rating, which, consequently, presents low switch blocking
voltages when compared to conventional topologies. System model, a
space-vector pulse width modulation (PWM) strategy to symmetrical and
asymmetrical dc-link voltages, and an overall control strategy to adjust the
system variables are presented. A power flux analysis shows the operation zone
in which the individual dc-link voltage balancing is possible. PWM and control
strategies are developed to reduce the semiconductor total losses, harmonic
distortion, and switching stress. Two ac-dc-ac multilevel conventional structures
are used for comparison. Simulation and experimental results demonstrate the
feasibility of the studied converter.

7
 CHAPTER 3: DESCRIPTION OF THE PROJECT

3.1: EXISTING SYSTEM

The existing system is a two-level four-leg converter. This system
comprises a full bridge rectifier and a full-bridge inverter. This is a
disadvantageous system due to the presence of a unidirectional inverter and
rectifier. Also, the output that is produced by this converter consists of only two
levels, which has a higher level of harmonic distortion which directly affects the
efficiency of the system. Also, the presence of four legs makes the system
clumpy and large.

Fig.1:Existing System: Two-level Four Leg Converter

3.2: PROPOSED SYSTEM

The proposed configuration comprises three legs (two bidirectional

controlled legs and a unidirectional controlled leg), inductive and capacitive
filters, and a DC-link capacitor bank. The unidirectional leg is made out of
switches qg1 and qg2 and diodes dg1 and dg2. The shared leg is composed of the

8
switches qs1, qs2, qs1, and qs2 and the leg at the load side is comprises switches
ql1, ql2, ql1, and ql2.

Due to the use of a unidirectional NPC leg, two operation conditions can
be described. Notice that when the grid current is positive(ig ≥ 0), the state of
switch qg2 defines the pole voltage vg0 because the diode dg2 is reverse-biased.
Likewise, when the grid current is negative (ig < 0), the state of switch qg1
defines the pole voltage vg0 because the diode dg1 is reverse-biased.

In this way, due to the unidirectional power flow in the converter, the
voltage vl and current ig must be synchronized with the voltage vg, so that the
pole voltage vg0 is properly modulated, avoiding distortion in the grid current
(ig).

Fig.2:Proposed System: Three-level Three Leg Converter

3.3: WORKING OF THE PROPOSED SYSTEM

There are two major parts in the working of this system. One is the
rectifier part and the other is the inverter part. In the rectifier part, the rectifier
leg and the shared leg work together to rectify the input AC voltage, and the
voltage is stored in the capacitor banks C1 and C2. The splitting of the capacitor

9
banks enables us to perform the development of the three-level output
waveform. Similar to the rectifier, the inverter is also formed using the shared
leg and the inverter leg. Moreover, the presence of more than two switches in a
single leg helps to achieve the third level in the output thereby reducing the
level of harmonics in the output voltage waveform. This method is termed
Neutral Point Clamping, where the third level in the output is obtained by
splitting the input DC voltage into two parts and then using it to produce an AC
output waveform.

3.4: HARDWARE COMPONENTS

The hardware components used in the model are as stated and explained
below.

3.4.1: MICROCONTROLLER

The DSPIC30F devices contain extensive Digital Signal Processor (DSP)

functionality within a high-performance 16-bit microcontroller (MCU)
architecture. The core always has 24-bit instructional words. PC (Program
Counter) is 23 bits extensive with LSB (least significant bit) and the MSB (most
significant bit) is always ignored during the normal running of the program
except for certain conditions or instructions. Then the PC addresses up to 4M
instructional words. There it uses an instructional mechanism just to maintain
throughput. The program loop uses the DO and REPEAT instructions. These
both are interruptible at any point in the program. 16 x 16-bit register acts as
data, address, and offset register. When we talk about data space which is 64
Kbytes (32K words) and split into 2 blocks referred to as X and Y data memory.
Both of these blocks have their own Address Generation Unit (AGU).
There is a specification of X and Y in the dsPIC30f2010 Microcontroller
that these are device-specific and could not be altered by their users. While the

10
overhead free circular buffer is supported in both X and Y address space.The
core maintenance Inherent, Relative, Literal, Register Offset, Register Direct,
Register Indirect, Literal Offset Addressing Modes. Most of the instructions are
related to the predefined Addressing modes and depending upon their functional
specifications. In most of the instructions, the core is clever enough to run a
program data memory read, a data memory writes, and an instruction memory
read per its instruction cycle. And core does not backing or support a
multi-stage data pipeline but a single-stage data prefetch mechanism is used
here, which partially decodes instructions a cycle ahead of running, just to
increase the available running time. Most of the data/instructions run in a single
cycle, with certain exceptions.
Programmer’s Model of dsPIC30f2010 Microcontroller mostly consists
of 16 x 16-bit working registers. Some registers as like Status Register (SR),
DO and REPEAT register, Program Space Visibility Page registers (PSVPAG),
Data Table Page register (TBLPAG) and Program Counter (PC) act as an
address, data, or offset registers. These all are memory-mapped. Some of them
have a shadow register with each of these registers. Actually, the shadow
register is used temporarily and these can move its data or contents from its host
register on the occurrence of an event. But there is a specific condition that
occurs that the shadow register could not access directly. At the working register
when a byte operation is performed, at that time just the Least Significant Byte
(LSB) of the specific register is affected.
In dsPIC  DSC devices, SOFTWARE STACK POINTER or FRAME
POINTER are used. W15 is software Stack Pointer (SP), which has the ability
to modify automatically by processing, calls, and returns. However, W15 could
be referenced through any order but in the same manner as all other W registers.
It simplifies the reading, writing, and many other manipulations of the Stack
Pointer. During a Reset, W15 is initialized to 0x0800. You may reprogram the
SP (Stack Pointer) during initialization to any position within data space. W14

11
register has been devoted as a Stack Frame Pointer (SP) as defined by the
ULNK  and LNK  instructions.

Fig.3:Pin-Diagram: dsPIC30F2010

Table 1: Pin Configuration: dsPIC30F2010

PIN # PIN NAME + DESCRIPTION  Port
(n)
1 MCLR Master Clear
(Reset) input or
programming
voltage input.
2 EMUD3/AN0/VREF+/CN2/RB0 B
3 EMUC3/AN1/VREF-/CN3/RB1 B
4 AN2/SS1/CN4/RB2 B
5 AN3/INDX/CN6/RB3 B
6 AN4/QEA/IC7/CN6/RB4 B
7 AN5/QEB/IC8/CN7/RB5 B
8 Vss Ground reference
for analog module
9 OSC1/CLKI Oscillator Input

12
 10 OSC2/CLKO/RC15 Oscillator
11 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 C
12 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 C
13 RC2/CCP1/VDD1A C
14 EMUD2/OSC2/IC2/INT2/RD1 D
15 EMUC2/OC1/IC1/INT1/RD0 D
16 FLTA/INT0/SCK1/OCFA/RE8 E
17 PGD/EMUD/U1TX/SDO1/SCL/RF3 F
18 PGC/EMUC/U1RX/SDI1/SDA/RF2 F
19 Vss Ground
20 VDD Positive Power
Supply for analog
module
21 PWM3H/RE5 E
22 PWM3L/RE4 E
23 PWM2H/RE3 E
24 PWM2L/RE2 E
25 PWM1H/RE1 E
26 PWM1L/RE0 E
27 AVSS Analogue Ground
28 AVDD Analogue Power
Supply

3.4.1.1 HIGH-PERFORMANCE MODIFIED RISC CPU:

● It has Modified Harvard Architecture

● 84 base directions with flexible tending to modes
● C compiler optimized instruction set of design
● 27 intersect sources

13
 ● 3 external interrupt sources
● 24-bit wide guidelines, 16-bit wide data way
● 16 x 16-bit working register cluster
● Up to 30 MIPs task
● DC to 40 MHz outer clock input
● 4 MHz-10 MHz oscillator contribution with PLL active (4x, 8x, 16x)
● Peripheral and External interface with sources
● 8 user-selectable need levels for each hinder
● 4 processor exemptions and programming traps
● Primary and Alternate interface with Vector Tables

3.4.1.2 DSP ENGINE FEATURE:

● Modulo and Bit-Reversed Addressing modes
● Two, 40-bit wide aggregators with discretionary saturation logic
● 17-bit x 17-bit single-cycle equipment fragmentary/whole number
multiplier
● Single-cycle Multiply-Accumulate (MAC) task
● Dual information fetch
● 40-organize Barrel Shifter

3.4.1.3 PERIPHERAL FEATURE:

● High current source/sink I/O pins: 25 mA/25 mA
● Optionally combine up 16-bit timers into 32-bit clock modules
● 3-wire SPI™ modules (underpins 4 Frame modes)
● I2C™ module bolsters Multi-Master/Slave mode and 7-bit/10-bit
addressing
● There addressable UART modules with FIFO buffers

14
3.4.1.4 MOTOR CONTROL PWM MODULE FEATURE:
● Complementary or Independent Output modes
● Edge and Center Aligned modes
● Multiple obligation cycle generators
● Dedicated time base with 4 modes
● Programmable yield polarity
● Deadtime control for Complementary mode
● Manual yield control
● Trigger for synchronized A/D transformations

3.4.1.5 QUADRATURE ENCODER INTERFACE MODULE FEATURE:

● Phase A, Phase B, and Index Pulse input
● 16-bit up/down position counter
● Count bearing status
● Position Measurement (x2 and x4) mode
● Programmable digital noise filters on contributions (inputs)
● Alternate 16-bit Timer/Counter mode
● Interrupt on position counter rollover

3.4.1.6 ANALOG FEATURE:

● 10-bit 1 Msps Analog-to-Digital Converter (A/D)
● A/D Conversion accessible amid Sleep and Idle
● 4 Sample/Hold Channels
● Multiple Conversion Sequencing Options

3.4.1.7 SPECIAL MICROCONTROLLER FEATURE:

● Improved Flash program memory: 10,000 delete/write cycle (min.) for
industrial temperature range, 100K (typical)

15
 ● Data EEPROM memory: 100,000 delete/write cycle (min.) for industrial
temperature range, 1M (typical)
● Self-re programmable under software control
● Power-up Timer (PWRT), Power-on Reset (POR), and Oscillator Start-up
Timer (OST)
● Flexible Watchdog Timer (WDT) with on-chip low power RC oscillator
is used for reliable operation
● Fail-Safe clock screen/monitor task
● Detects clock catastrophe and switches to the on-chip low power RC
oscillator
● Programmable code assurance
● In-Circuit Serial Programming™ (ICSP™)
● Programmable Brown-out Detection and Reset generation
● Selectable Power Management modes: Idle, sleep, and Alternate Clock
modes

3.4.1.8 CMOS TECHNOLOGY:

● High-speed Flash machinery with low power

● Wide operating voltage range (2.5V to 5.5V)
● Industrial and Extended temperature ranges
● Low power utilization

3.4.2 DRIVER CIRCUIT

TLP250 is an isolated IGBT/Mosfet driver IC.  The input side consists of

a GaAlAs light-emitting diode. The output side gets a drive signal through an
integrated photodetector. Therefore, the main feature is electrical isolation
between low and high power circuits. It transfers electrical signals optically via

16
light. Users can use it to drive the gate terminal of high voltage switches in both
configurations such as high side and low side drive. It is available as an 8-pin
DIP package.

3.4.2.1 PINOUT DIAGRAM AND CONFIGURATION OF TLP250

The Pinout diagram of TLP250 is given below. It is clearly shown in the
figure that led at the input stage and photodetector diode at the output stage is
used to provide isolation between high and low power circuits. Pin numbers 1
and 4 are not connected to any point. They are marked as NC ( No connection).
Hence they are not in use. Pin 2 is the anode point of the input stage
light-emitting diode and pin 3 is the cathode point of the input stage. Input is
provided to pin numbers 2 and 3. Pin number 8 is for supply connection. Pin
number 5 is for a ground of power supply.

Fig.4:Pin-Diagram: TLP250

3.4.2.2 PINS FUNCTIONS

● Pin number one and four is not connected to any point physically.
Therefore they are not in use.

17
 ● Pin number 8 is used to provide power supply to TLP250 and pin number
5 is a ground pin that provides a return path to power supply ground. A
maximum power supply voltage between 15-30 volt dc can be given to
TLP250. But it also depends on the temperature of the environment
where it is being used.
● Pin numbers 2 and 3 are anode and cathode points of input stage LED. It
works like a normal light-emitting diode. It has similar characteristics of
forwarding voltage and inputs current. The maximum input current is in
the range of 7-10mA and the forward voltage drop is about 0.8 volt.
TLP250 provides output from low to high with a minimum threshold
current of 1.2mA and above.
● Pin number six and seven is internally connected to each other. Output
can be taken from either pin number 6 and 7. The totem pole
configuration of two transistors is used in TLP250. In the case of high
input, the output becomes high with output voltage equal to a supply
voltage and in case of low input, the output becomes low with output
voltage level equal to ground.
● Mosfet driver TLP250 can be used up to 25khz frequency due to slow
propagation delay.

Table 2: Pin Configuration: TLP250

PIN # PIN NAME + DESCRIPTION  Details
1 NC No Connection – Not
Used
2 Anode Anode Terminal Of
LED Diode
3 Cathode Cathode Terminal Of
LED

18
4 NC No Connection – Not
Used
5 GND Connect With Ground
Of Power Supply
6 Vo Output Terminal
7 Vo Output Terminal
8 Vcc Connect With Positive
Terminal Of Power
Supply

3.4.2.3 ELECTRICAL FEATURES AND SPECIFICATION

● Operating frequency: 0-25kHz

● Input Supply voltage: 10-35 volts
● Output voltage:  10-35 volts
● Output drive current: 1.5A
● Electrical isolation voltage: 3500 VRMS
● Switching rise and fall time: 1.5μs
● Operating temperature range: -20 – 85 degrees

3.4.3 MOSFET

The IRF840 is an N-Channel Power MOSFET that can switch loads up to

500V. The Mosfet could switch loads that consume up to 8A, it can be turned on
by providing a gate threshold voltage of 10V across the Gate and Source pin.
Since the MOSFET is for switching high current high voltage loads it has a
relatively high gate voltage, hence cannot be used directly with an I/O pin of a
CPU.

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3.4.3.1 MOSFET OPERATING PRINCIPLE:

The N channel enhancement MOSFET is similar to the depletion type in

the construction except that there is no physical existence of the channel when it
is unbiased.

When the positive voltage is applied between the gate and the source, the
electron gets accumulated in the channel by capacitive induction in the channel

Fig.5:Pin-Diagram: IRF840

formed out of electrons allowing the flow of current. This channel gets widened
as a more positive voltage is applied between gate and source. There will not be
any condition through the device if the gate-source voltage is negative.

Setting VGS to a constant value, varying VDS and nothing the

corresponding changes into giving the drain characteristic. VGS ≤0, the device
does not conduct drain current and the device is considered to be in the off state.
In this state, the entire voltage drops across the device i.e., between drain and
source.

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 In the ON state of the device, gate-source voltage is positive and the drain
current is increased with the increase in the gate-source voltage. It is understood
clearly in the transfer characteristics.

As the enhancement type MOSFET conduct only after applying a positive

gate voltage, it is also called normally OFF MOSFET. For this reason, it
becomes easily controllable and is used in power electronics as a switch.

3.4.3.2 FEATURES

● N-Channel Power MOSFET

● Continuous Drain Current (ID): 8A
● Gate threshold voltage (VGS-th) is 10V (limit = ±20V)
● Drain to Source Breakdown Voltage: 500V
● Drain Source Resistance (RDS) is 0.85 Ohms
● Rise time and fall-time is 23nS and 20nS
● Available in To-220 package

Table 3: Pin Configuration: IRF840

Pin Number Pin Name Description

1 Source Current flows out through Source (maximum

8A)

2 Gate Controls the biasing of the MOSFET (Threshold

voltage 10V)

3 Drain Current flows in through Drain

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3.4.4 SOFTWARE REQUIREMENT

3.4.4.1 MATLAB

MATLAB is a high-performance language for technical computing. It

integrates computation, visualization, and programming in an easy-to-use
environment where problems and solutions are expressed in familiar
mathematical notation. Typical uses include
1. Math and computation
2. Algorithm development
3. Data acquisition
4. Modelling, simulation, and prototyping
5. Data analysis, exploration, and visualization
6. Scientific and engineering graphics
7. Application development, including graphical user interface
building
MATLAB is an interactive system whose basic data element is an array
that does not require dimensioning. This allows you to solve many technical
computing problems, especially those with matrix and vector formulations, in a
fraction of the time it would take to write a program in a scalar non-interactive
language such as C or FORTRAN. The name MATLAB stands for matrix
laboratory.

3.4.4.2 MATLAB SYSTEM

The MATLAB system consists of five main parts: Desktop Tools and
Development Environment This is the set of tools and facilities that help you
use MATLAB functions and files. Many of these tools are graphical user
interfaces. It includes the MATLAB desktop and Command Window, a
command history, an editor and debugger, a code analyzer and other reports, and

22
browsers for viewing help, the workspace, files, and the search path. The
MATLAB Language This is a high-level matrix/array language with control
flow statements, functions, data structures, input/output, and object-oriented
programming features. It allows both "programming in the small" to rapidly
create quick and dirty throw-away programs, and "programming n the large" to
create large and complex application programs.

Fig.6:MATLAB UI

3.4.4.3 GRAPHICS

MATLAB has extensive facilities for displaying vectors and matrices as

graphs, as well as annotating and printing these graphs. It includes high-level
functions for two-dimensional and three-dimensional data visualization, image
processing, animation, and presentation graphics. It also includes low-level
functions that allow you to fully customize the appearance of graphics as well as
to build complete graphical user interfaces on your MATLAB applications. The
MATLAB External Interfaces/API This is a library that allows you to write C
and Fortran programs that interact with MATLAB. It includes facilities for

23
calling routines from MATLAB (dynamic linking), calling MATLAB as a
computational engine, and for reading and writing MAT-files.

3.4.4.4 MATLAB DOCUMENTATION

MATLAB provides extensive documentation, in both printed and online

format, to help you learn about and use all of its features. If you are a new user,
start with this Getting Started book. It covers all the primary MATLAB features
at a high level, including many examples. The MATLAB online help provides
task-oriented and references information about MATLAB features. MATLAB
documentation is also available in printed form and in PDF format. MATLAB
Online Help to view the online documentation, select MATLAB Help from the
Help menu in MATLAB.

3.4.4.5 MATLAB LIBRARY

American utility located in Canada, and also on the experience of Ecolede

Technologies superior and University Laval. The capabilities of Sim Power
Systems for modeling a typical electrical system are illustrated in demonstration
files. And for users who want to refresh their knowledge of power system
theory, there are also self-learning case studies. The Sim Power Systems main
library, power lib, organizes its blocks into libraries according to their behavior.
The power lib library window displays the block library icons and names.
Double-click a library icon to open the library and access the blocks.

24
Fig.7:MATLAB Simulink Library

25
 CHAPTER 4: RESULTS AND SIMULATION

4.1 GENERAL

Simulation has become a very powerful tool in industrial applications as

well as in academics, nowadays. It is now essential for an electrical engineer to
understand the concept of simulation and learn its use in various applications.
Simulation is one of the best ways to study the system or circuit behavior
without damaging it. The tools for doing the simulation in various fields are
available in the market for engineering professionals. Many industries are
spending a considerable amount of time and money on doing simulations before
manufacturing their product. In most of the research and development (R&D)
work, simulation plays a very important role. Without simulation, it is quite
impossible to proceed further. It should be noted that in power electronics,
computer simulation and a proof of concept hardware prototype in the

laboratory are complementary to each other.

4.2 SIMULATION DIAGRAM OF THE PROJECT

Fig.8:Three-level three-leg converter MATLAB simulation

26
4.3 SIMULATION RESULTS

4.3.1 INPUT WAVEFORM:

Fig.9:Input AC Waveform from Grid

4.3.2 OUTPUT WAVEFORM:

Fig.10:Three-level Output Waveform

27
4.4 FINAL MODEL OF PROJECT:

Fig.11: Finalized model of Single phase ac dc ac converter

28
4.5 HARDWARE OUTPUT:

Fig.12:Pulse for Mosfet

Fig 13:Output waveform

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4.6 APPLICATIONS:

4.6.1 UPS:

The UPS provides the electric backup to the appliances without delay and
fluctuation. And, the inverter is a medium between the primary power supply
and the battery. The battery helps in storing the energy and during the power
outages convert the store AC into DC and provides power to the electrical
inverter.

Fig 14: Block diagram of UPS

30
4.6.2 UNIVERSAL ACTIVE POWER FILTER:

Universal active power filters are filters, which can perform the job of
harmonic elimination. Universal active power filters can be used to filter out
harmonics in the power system which are significantly below the switching
frequency of the filter. These active power filters are used to filter out both
higher and lower order harmonics in the power system.

4.6.3 POWER LINE CONDITIONER:

A power conditioner (also known as a line conditioner or power line
conditioner) is a device intended to improve the quality of the power that is
delivered to electrical load equipment. The term most often refers to a device
that acts in one or more ways to deliver a voltage of the proper level and
characteristics to enable load equipment to function properly. In some uses,
power conditioner refers to a voltage regulator with at least one other function
to improve power quality (e.g. power factor correction, noise suppression,
transient impulse protection, etc.)

Fig 15:Power conditoner

31
 CHAPTER 5: CONCLUSION

A novel unidirectional single-phase three-level converter has been

investigated in this project. It is composed of three three-level legs, of which
two are NPC-type legs and the other has reduced switch count. The feasibility
of the proposed configuration and synchronization method, provided by a PLL
and a current control loop, has been validated through simulation and
experimentally. The synchronization between current and voltage of the grid
side of the converter is mandatory since the PWM strategy depends on the
current flow direction on the synthesis of the voltages.

The replacement of switches by diodes does not mean only less active
switches, but also, less driver circuitry. This implies a less complex topology
with reduced cost in relation to the C3L one. Furthermore, dead time is not
necessary on the grid side leg, because, independently of the switch states, it is
not possible to short-circuit the DC-link. The proposed configuration was
compared experimentally in terms of efficiency and harmonic distortion (of
grid-side current) with the C3L one. The results have shown that the proposed
converter is more efficient with similar THD. Tests with nonlinear load were
performed and shown that the proposed topology is well suited for this load
type. Also, tests with load transient were presented and shown the proper
functioning of the control strategy and capacitor voltages balancing technique.

32
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