AZ3028-04P

Transient Voltage Suppressing Device

For Surge/ESD/Latch-Up Protection

Preliminary

Features During transient conditions, the proprietary

clamping cells provide low clamping voltages to
z Transient Protection for 2 Differential Line Pairs minimize the stress on the protected
(4 lines) with Bi-directional. components.
z Provide Transient Protection for the Protected

Differential Line Pair to AZ3028-04P is bi-directional and may be used on

IEC 61000-4-2 (ESD) ±30kV (contact/air) lines where the signal swings above and below
IEC 61000-4-4 (EFT) 60A (5/50ns) ground.
IEC 61000-4-5 (Lightning) 30A (8/20μs)
AZ3028-04P may be used to meet the ESD
Cable Discharge Event (CDE)
immunity requirements of IEC 61000-4-2, Level 4
z JEDEC SO-8 Package.
(±15kV air, ±8kV contact discharge).
z Specific Pin Out For Easy Board Layout.

z Fast Turn-On and Low Clamping Voltage.

Circuit Diagram /
z Low Operating Voltage: 2.8V.
Pin Configuration
z Low Leakage Current
z Solid-State Silicon-Avalanche and Active
1 8
Circuit Triggering Technology.

Applications 2 7

z WAN/LAN Device AZ3028-04P

z 10/100/1000 Ethernet
3 6
z Switching Systems

z Computers
z Instruments 4 5
z Differential Inputs

SO-8 (Top View)

Description

Circuit Board Layout Example

AZ3028-04P is a design which includes
bi-directional surge rated clamping cells to Line 1
1 8
protect two differential high speed data-line pairs Differential
in an electronic systems. The AZ3028-04P has Line Pair 1
Line 2
been specifically designed to protect sensitive 2 7

components which are connected to the

differential line pairs from over-voltage damage
Line 3
and latch-up caused by Electrostatic Discharging 3 6

(ESD), Electrical Fast Transients (EFT), Differential

Line Pair 2
Lightning, and Cable Discharge Event (CDE). Line 4
4 5
AZ3028-04P is a unique design which includes
proprietary clamping cells in a single package.

Revision 2008/10/17 ©2008-2009 Amazing Micro. 1 www.amazingIC.com

 AZ3028-04P
Transient Voltage Suppressing Device
For Surge/ESD/Latch-Up Protection

Preliminary

SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATING UNITS
Peak Pulse Current (tp =8/20us) for
IPP 30 A
each differential line pair
ESD per IEC 61000-4-2 (Contact /Air)
VESD ±30 kV
for each differential line pair
o
Lead Soldering Temperature TSOL 260 (10 sec.) C
o
Operating Temperature TOP -55 to +125 C
o
Storage Temperature TSTO -55 to +150 C

ELECTRICAL CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Reverse Stand-Off Voltage VRWM T=25 oC. 2.8 V

Reverse Leakage Current ILeak VRWM = 2.8V, T=25 oC (Each Line) 1 μA

IBV = 1mA, T=25 oC.

Reverse Breakdown Voltage VBV 3 V
(Each Differential Line Pair)
ISB = 50mA.
Snap-Back Voltage VSB 2.8 V
(Each Differential Line Pair)
IPP=5A, tp=8/20us, T=25 oC.
Clamping Voltage VCL 10 V
(Each Differential Line Pair)
IPP=24A, tp=8/20us, T=25 oC.
Clamping Voltage VCL 13 V
(Each Differential Line Pair)
IPP=30A, tp=8/20us, T=25 oC.
Clamping Voltage VCL 15 V
(Each Differential Line Pair)
VR = 0V, f = 1MHz, T=25 oC.
Channel Input Capacitance CIN 5.5 pF
(Each Differential Line Pair)

Revision 2008/10/17 ©2008-2009 Amazing Micro. 2 www.amazingIC.com

 AZ3028-04P
Transient Voltage Suppressing Device
For Surge/ESD/Latch-Up Protection

Preliminary

Typical Characteristics

Clamping Voltage vs. Peak Pulse Current

20
18
16

Clamping Voltage (V)

14
12
Differential Line Pair
10
8
6 Waveform
Parameters:
4
tr=8μs
2 td=20μs

0
0 5 10 15 20 25 30 35 40 45
Peak pulse Current (A)

Transmission Line Pulsing (TLP) Measurement

Transmission Line Pulsing (TLP) Current (A)

Typical Variation of CIN vs. VIN

7 20
V_pulse

Differential Line Pair 15 Pulse from a

transmission line
6 TLP_I
100ns +
10
Input Capacitance (pF)

TLP_V DUT
5
-
5
4
0
3 Differential Line Pair
-5

2 -10
f = 1MHz, T=25 oC,
1 -15

-20
0
-3 -2 -1 0 1 2 3 -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12

Input Voltage (V) Transmission Line Pulsing (TLP) Voltage (V)

Insertion Loss S21

50

40

30

20

10
Differential Line Pair
dB

-10

-20

-30

-40

-50
1e+5 1e+6 1e+7 1e+8 1e+9

Frequency (Hz)

Revision 2008/10/17 ©2008-2009 Amazing Micro. 3 www.amazingIC.com

 AZ3028-04P
Transient Voltage Suppressing Device
For Surge/ESD/Latch-Up Protection

Preliminary

Applications Information

The AZ3028-04P is designed to protect four lines

against System ESD/EFT/Lightning pulses by
Line 1
clamping them to an acceptable reference. It 1 8

provides bi-directional protection. Differential

Line Pair 1
Line 2
2 7
The usage of the AZ3028-04P is shown in Fig. 1.
It can be configured to protect two high speed
line pairs (four lines). The first line pair is Line 3
3 6
connected to Pin-1, Pin-2, Pin-8, and Pin-7,
Differential
simultaneously. The second line pair is Line Pair 2
Line 4
connected to Pin-3, Pin-4, Pin-6, and Pin-5, 4 5

simultaneously. The traces must be connected at

the bottom of AZ3028-04P.
Fig. 1
In order to obtain enough suppression of ESD Configuration for protecting two
induced transient, good circuit board is critical. differential line pairs
Thus, the following guidelines are recommended:
z Minimize the path length between the
protected lines and the AZ3028-04P.
z Place the AZ3028-04P near the input
terminals or connectors to restrict transient
coupling.
z The ESD current return path to ground
should be kept as short as possible.
z Use ground planes whenever possible.
z NEVER route critical signals near board
edges and near the lines which the ESD
transience easily injects to.

Revision 2008/10/17 ©2008-2009 Amazing Micro. 4 www.amazingIC.com

 AZ3028-04P
Transient Voltage Suppressing Device
For Surge/ESD/Latch-Up Protection

Preliminary

Typical Applications

10M/100M Ethernet LAN Connector

VCC

I/O1+ I/O2+ Tx+

8
Tx+
0.1uF
I/O1- I/O2- Tx-

7
Tx- I/O3+ I/O4+ Rx+

6
Rx+ I/O3- I/O4- Rx-

5
0.1uF

Rx- AZ3028-04P
Line5
Line6
I/O I/O
1

Line7
Line8
GND VDD
2

75Ω
0.1uF
I/O I/O (optional)
3

Amazing's 6- 0.1uF/2KV
pin TVS array

10M/100M Ethernet Protection Circuit

LED-G
Amazing's
Gigabit Ethernet LAN Connector
0.1uF 2 2-pin TVS 1

VCC
Amazing's
2 2-pin TVS 1

Tx1+ I/O1+ I/O2+ Tx1+

1

0.1uF
I/O1- I/O2- Tx1-
2

Tx1-
I/O3+ I/O4+ Rx1+
3

Rx1+
0.1uF I/O3- I/O4- Rx1-
4

Rx1-
AZ3028-04P
Tx2+
0.1uF
I/O1+ I/O2+ Tx2+
1

Tx2-
I/O1- I/O2- Tx2-
2

Rx2+
0.1uF I/O3+ I/O4+ Rx2+
3

Rx2- I/O3- I/O4- Rx2-

4

I/O I/O I/O I/O AZ3028-04P

1

GND VDD GND VDD

2

75Ω

I/O I/O I/O I/O

3

4
LED-G

LED-G

Amazing's 6-pin Amazing's 6-pin 0.1uF/2KV

TVS array TVS array

Gigabit Ethernet Protection Circuit

Revision 2008/10/17 ©2008-2009 Amazing Micro. 5 www.amazingIC.com

 AZ3028-04P
Transient Voltage Suppressing Device
For Surge/ESD/Latch-Up Protection

Preliminary

Mechanical Details
SO-8
PACKAGE DIAGRAMS
TOP VIEW SIDE VIEW

END VIEW

PACKAGE DIMENSIONS

Revision 2008/10/17 ©2008-2009 Amazing Micro. 6 www.amazingIC.com

 AZ3028-04P
Transient Voltage Suppressing Device
For Surge/ESD/Latch-Up Protection

Preliminary

LAND LAYOUT

X
Dimensions
Index Millimeter Inches
A 7.40 0.291
B 3.00 0.118
D B A
C 2.20 0.087
D 5.20 0.205
E 1.27 0.050
C
X 0.60 0.24

E
Notes:
This LAND LAYOUT is for reference
purposes only. Please consult your
manufacturing partners to ensure your
company’s PCB design guidelines are met.

MARKING CODE
8

Part Number Marking Code

302804P AZ3028-04P 302804P

YYWWXX (Rohs Part) YYWWXX

AZ3028-04P E4742
1

(Engineering Part)

302804P = Device Code

YYWWXX = Date Code

Revision 2008/10/17 ©2008-2009 Amazing Micro. 7 www.amazingIC.com

 AZ3028-04P
Transient Voltage Suppressing Device
For Surge/ESD/Latch-Up Protection

Preliminary

Revision History

Revision Modification Description

Revision 2008/10/17 Preliminary Release.

Revision 2008/10/17 ©2008-2009 Amazing Micro. 8 www.amazingIC.com