Computer Architecture Dr. Abeer SaberStructure and Function ® Structure - The way in which components relate to each other * Function -What each component doFunction * There are four basic functions that a computer can perform: Data processing = Data may take a wide variety of forms and the range of processing requirementsis broad © Data storage * Short-term © Long-term * Data movement * input-output (W/O) - when data are received from or delivered toa device (peripheral) that is directly connected to the computer © Data communications - when data are moved over longer distances, to or from a remote device * Control * Acontrol unit manages the computer's resources and ‘orchestrates the performance of its functional parts in response toinstructionsStructure— COMPUTER Main memory \ ‘System\_|_ busENIAC * The first electrical computer * It use decimal system * Can't store programCentral Arithmetic Unit Central Control UnitVon Neuman Architecture ® Data & instructions are stored * Memory consists of addresses © Instructions executed in order (until modified)Instructions ® Every instructions is an arithmetic or logical operation ® Any operations consists of - operator, represents the operation itself - operand, represents the data to process (J Unary operator (take one operand) (J Binary operator (take two operand)Give me the instruction from address x _—_—___— Here it isFetch instructionInstructions Opcode = operation code Opcode OperandInstructions * We use binary system to store instructions * We need unique code for each instruction ® If | have 8 instructions, | need 3 bit (2%3=8) - 000, 001, 010, 011, 100, 101, 110, 1110 34 15 a (@ Instuetion format o4 15 | (Integer format Program Counter (PC) = Address of instruction Instruction Register (UR) = Instruction being executed ‘Accumulator (AC) = Temporary storage (6 Internal CPU reise 0001 = Load AC fom Memory 0010 = Sore AC 10 Memory 0101 = Add to AC from Memory (@ Partial ist of opcodes Figure 34. Characteristics ofa Hypothetical MaeMAR System Bus MBR HO AR 10 BR AR Inpuoutpu addres register Figure 32 Computer Components: Top-Level ViewFetch Cycle At the beginning of each instruction cycle the processor fetches an instruction from memory The program counter (PC) holds the address of the instruction to be fetched next ‘The processor increments the PC after each instruction fetch so that it wil fetch the next instruction in sequence The fetched instruction is loaded into the instruction register (IR) =n The processor interprets the instruction and performs the required actionRegisters instruction register (IR) Q) Program counter (PC) Liceneral-purpose register (R,—R,..) Clothers{orn sep 7 So sirc i X ( Hit Example of Program Execution sf memory and registers in hexadecimal)ATypical Instruction Load R2, LOC reads the contents of a memory location whose address is represented symbolically by the label LOC and loads them into processor register R2ATypical Instruction Add Rg, R2, R3 adds the contents of registers R2 and R3, then places their sum into register Ry, Place the sum into register R4. The original contents of R2 and R3 are preserved. The original contents of Rg is overwritten. Instruction is fetched from the memory into the processor -the resulting sum is stored in register R.ATypical Instruction Store R4, LOC * copies the operand in register R4 to memory location LOC.Interconnections “COMPUTERBuses Transfer data Consists of set of lines/path ways Each line transfer one bit Bits can move in paralleloN Me 0) yInstructions Taterrapt Signalsees Memory Write Words Aadres > econo Data N-1 cooV/O Module => Data External Address Daa > Taverrup? Seat >Type of buses * Data bus * Address bus * Control busData Bus * Consist of set of lines (data bus width) + If data = 64 bit & bus width = 32 bit you need 2 cyclesAddress Bus * Width represents max accessible memory address * Canhold memory or iO device address Higher order bits for module to connect with (memory, lO) The remaining partis the address Module Address X1010011 ° x=0 memory © Xe1 vo Control Bus * Used to control the access and the Use ofthe data and address lines * Because the data and address lines are shared by all components there rust be a means of controlling theiruse+++] Memory Cosel ines Figure 3.16 Bus Interconnection Scheme