Khoa : in T- Vin Thng

Mn : Vi iu khin 8051

Sch tham kho

H Vi iu khin 8051, Dch: Tng Vn n v Hong c Hi, 2001 Ng Din Tp, K thut ghp ni my tnh, 2000 Ng Din Tp, o lng v iu khin bng my tnh, 1998 Xun Tin, K thut Vi x l v lp trnh Assembly cho h vi x l, 2003

Ni dung
1 Gii thiu 2 S khi v chn 3 T chc b nh cu 8051 4 Cc thanh ghi chc nng c bit 5 Tp lnh ca 8051 6 Hot ng nh thi 7 Giao tip ni tip 8 Lp trnh ngt

Gv : Nguyn Vn Sum

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Khoa : in T- Vin Thng

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Chng 1
1 Vi x l

GII THIU

CPU cho cc my tnh Khng c RAM, ROM, I/O trn CPU Vd: Intels x86, Motorolas 680x0

Data Bus
CPU Vi x l
RAM

Nhiu chips trn bo mch ch

RO M I/O Port Time r Cng ni tip

Address Bus H thng vi x l

2 Vi iu khin L my tnh mini C RAM, ROM, I/O ports trn CPU chip Vd: Motorolas 6811, Intels 8051, Zilogs Z80, & PIC 16X

CPU

RAM

ROM

tt c bn trong 1 chip
I/O Port Timer Cng ni tip

Gv : Nguyn Vn Sum

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So snh Vi x l & Vi iu khin Vi iu khin CPU, RAM, ROM, I/O & Timer nm trn cng 1 chip C nh lng ROM, RAM, I/O Ports trn chip Thch hp cho cc ng dng: Gi c thp Nng lng tiu th thp Khng gian hn ch n mc ch Embedded System B x l c gn (embedded) vo mt ng dng c th Mt sn phm embedded ch s dng VXL hoc VK thc thi 1 cng vic duy nht Ch c mt phn mm ng dng & thng thng c np trong ROM vdprinter, keyboard, video game player Vi x l CPU chip ring bit. RAM, ROM, I/O, Timer bn ngoi Lng ROM, RAM, I/O Ports ty Gi thnh cao a nng a mc ch

3 tiu ch chn vi iu khin 1. p ng yu cu v nhim v v gi thnh thi cng Tc , lng b nh, cng I/O, timers, kch c, ng gi, nng lng tiu th D nng cp Gi thnh 2. Cc cng c pht trin phn mm Assember, b sa li, trnh dch C, m phng, h tr k thut 3. Th trng cung cp sn phm tin cy

Gv : Nguyn Vn Sum

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Mn : Vi iu khin 8051

Chng 2
2.1 S khi
INT1 INT0

S KHI V CHN

Timer 2 (8032/8052) Timer 1 Timer 0 Serial port Interrupt control Other registers Timer2 8032\8052 Timer 1 Timer 0

T2EX

128 bytes RAM 8032\8052 128 bytes RAM

T2 T1 T0

ROM 0K:8031\8032 4K:8051 8K:8052

CPU

Oscillator

Bus control

I/0 Ports

Serial port

EA RST

ALE PSEN P0 P1 P2 P3 TXD RXD

Address / Data

2.2 So snh cc thnh vin h 8051

Specification
Code Mem on chip (bytes) Data Mem on chip (bytes) Timers I/O pins Serial Port Interrupt sources

8031

8051
4K ROM

8751
4K EPROM

8951
4K Flash

8052
8K ROM

8752
8K EPROM

0K

128 2 32 1 5

128 2 32 1 5

128 2 32 1 5

128 2 32 1 5

256 3 32 1 6

256 3 32 1 6

Gv : Nguyn Vn Sum

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2.3 S chn
30pF 19 XTAL.1 12 MHz XTAL.2 30pF 18 29 30 ALE 31 9
17 16 15 14 13 12 11 10

Vcc
P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 32 AD7 33 AD6 34 AD5 35 AD4 36 AD3 37 AD2 38 AD1 39 AD0

PSEN

EA RST
P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0

8051

P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0

8 7 6 5 4 3 2 1

RD/ WR/ T1 T0 INT1/ INT0/ TXD RXD

Vss

P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0

28 A15 27 A14 26 A13 25 A12 24 A11 23 A10 22 A9 21 A8

20

Vcc (chn 40): Cung cp ngun cho chip +5V GND (chn 20): t XTAL1 & XTAL2 (chn 19, 18) 2 chn cung cp xung clock ngoi Cch 1: dao ng dng thch anh Cch 2: dao ng t ngun xung clock TTL bn ngoi Quan h gia chu k my v XTAL RST (chn 9): reset input & kch hot mc cao m bo hot ng reset xy ra, xung kch khi phi ko di t nht l 2 chu k my Gv : Nguyn Vn Sum Trang: 5

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Gi tr cc thanh ghi chu tc ng bi hot ng reset, xem bng trong phn 5 bi ging Mch reset c chng rung /EA (chn 31): External Access /EA ni mass ch nh rng code lu trn b nh ngoi /PSEN & ALE dng cho ROM ngoi Vi 8051, 8031, 8032 th /EA ni Vcc /: ch nh tc ng mc thp /PSEN (chn 29): Program Store Enable Output, cho php truy xut b nh chng trnh ngoi Ni ti chn /OE ca ROM/EPROM
Khi thc thi chng trnh ROM ni, /PSEN c gi mc 1

ALE (pin 30)Address Latch Enable L chn output cho php cht a ch gii a hp (demultiplexing) bus d liu v bus a chALE xut tn hiu cht a ch (byte thp a ch 16-bit) vo 1 thanh ghi ngoi trong sut na u ca chu k b nh (memory cycle). Trong na chu k b nh cn li, P0 s xut/nhp d liu ALE c f=1/6f C 1 ngoi l: trong thi gian thc thi lnh MOVX, mt xung ALE b b qua Cng I/O: P0, P1, P2, & P3. Mi cng: 8 chn. 4 cng I/O Port 0 (chn 32-39)P0 (P0.0P0.7) Port 1 (chn 1-8) P1 (P1.0P1.7)

Port 2 (chn 21-28)P2 (P2.0P2.7) Port 3 (chn 10-17)P3 (P3.0P3.7) Mi cng c 8 chn nh tn P0.X (X=0,1,...,7), P1.X, P2.X, P3.X ExP0.0 l bit 0 (LSB) ca P0 ExP0.7 l bit 7 (MSB) ca P0 8 bits ny cu thnh 1 byte Mi cng c th c dng nh input hay output

Gv : Nguyn Vn Sum

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Port 0 Cng 0 l cng c hai chc nng trn chn t 32 n chn 39 ca IC 8051. vic thit k ti thiu , n c dng nh mt cng I/O vn nng. i vi nhng bn thit k ln hn c b nh bn ngoi, n tr thnh bus a ch thp v bus d liu.(Xem b nh ngoi).
Port 1

Cng 1 l cng I/O chuyn dng trn chn 1-8. Nhng chn ny , c k hiu l P1.0, P1.1, P1.2 v.v...th cho php ghp ni n cc thit b ngoi vi khi c yu cu. Cc chn cng ch c s dng duy nht cho vic giao tip vi cc thit b ngoi vi.
Port 2

Cc chn cng 2 (chn 21-28 ) l cng c hai chc nng ngoi chc nng xut / nhp, cc chn ny cn lm dng byte cao ca Bus a ch truy xut n ROM gn bn ngoi b nh RAM c dung lng ln 256 bytes.
Port 3

Cng 3 cng l port c hai chc nng (t chn 10-17 ) ngoi kh nng xut /nhp mi chn cn c cc chc nng khc nhau tu theo c im ca 8051. Cc chc nng c bit ca port 3 c tm tt theo bng sau:
Bit P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 Tn RXD TXD INT0 INT1 T0 T1 WR RD

Chc nng
Nhn d liu cho port ni tip Pht d liu cho port ni tip

Interrupt ngoi 0
Interrupt ngoi 1 u vo bn ngi ca ng h/b m 0 u vo bn ngi ca ng h/b m 1 Tn hiu cho php ghi RAM ngoi

Tn hiu cho php ghi RAM trong

Gv : Nguyn Vn Sum

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Khoa : in T- Vin Thng

Mn : Vi iu khin 8051

Chng 3

T CHC B NH CA 8051

Hu ht cc b vi x l theo cu trc Von Neuman l dng chung khng gian b nh lu d liu v chng trnh. iu ny hp l bi v chng trnh c lu trn a v a vo RAM khi thi hnh. C d liu v chng trnh u nm trong RAM. Cn i vi vi iu khin t khi dng nh mt CPU trong h thng my tnh m thay bng cc thnh phn trung tm trong vic thit k iu khin i tng. N c b nh gii hn v cng khng c a v h iu hnh. Chng trnh iu khin phi nm trong ROM. Chnh v l do ny m cu trc phn cng dnh cho khng gian b nh l chia khng gian b nh ra thnh vng dnh cho chng trnh v vng dnh cho d liu trong. Tuy nhin c th dung cc thnh phn m rng m rng khng gian ny n 64K b nh ROM v 64 K b nh RAM. B nh bn trong c RAM. Trong chip RAM cha ng nhiu s sp xp lu tr chung, lu tr cc bit a ch, cc blank thanh ghi v cc thanh ghi chc nng c bit. C hai c im ng ch l: o Cc thanh ghi v cc cng xut nhp l b nh c sp t trc v c th truy xut ging nh cc vng b nh khc. o Ngn xp (Stack) nm trong RAM ni nh hn RAM ngoi nh b vi x l. Hnh v cho bit chi tit b nh d liu trn chip. Theo hnh v, khng gian b nh ni c chia ra thnh cc blank thanh ghi (00H-FFH), cc bit RAM c th a ch ho (20H-2FH), RAM a dng (30H-7FH) v cc thanh ghi chc nng c bit (80H-FFH).

Gv : Nguyn Vn Sum

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3.1 Khng gian b nh ROM ni

0000H

0000H

0000H

4k 8k
0FFFH

32k

8751 AT89C51

1FFFH

8752 AT89C52
7FFFH

DS5000-32 Atmel Corporation Dallas Semiconductor

3.2 Khng gian b nh RAM ni 3.2.1 Vng RAM a mc ch : Mc d trong hnh 2.6 ch ra bytes RAM a dng t 30H n 7FH. Bt k v tr no trong RAM a dng cng c th truy xut dng ch a ch trc tip hoc gin tip. RAM ni cung c th truy xut dng a ch gin tip trong qua R0 hoc R1. V d : MOV A, 5FH Hay nh: MOV R0, #5FH MOV A, @R0

Gv : Nguyn Vn Sum

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a ch Byte 7F

a ch Bit

a ch Byte FF

a ch Bit

F0 F7 F6 F5 F4 F3 F2 F1 RAM a dng

F0

B ACC PSW IP

E0 E7 E6 E5 E4 E3 E2 E1 E0 D0 D7 D6 D5 D4 D3 D2 D1 D0 30 2F 2E 2D 2C 2B 2A 29 28 27 26 25 24 23 7F 77 6F 67 5F 57 4F 47 3F 37 2F 27 1F 7E 76 6E 66 5E 56 4E 46 3E 36 2E 26 1E 7D 75 6D 65 5D 55 4D 45 3D 35 2D 25 1D 7C 74 6C 64 5C 54 4C 44 3C 34 2C 24 1C 7B 73 6B 63 5B 53 4B 43 3B 33 2B 23 1B 7A 72 6A 62 5A 52 4A 42 3A 32 2A 22 1A 79 71 69 61 59 51 49 41 39 31 29 21 19 78 70 68 60 58 50 48 40 38 30 28 20 18 B8 BC BB BA B9 B8

B0 B7 B6 B5 B4 B3 B2 B1 B0 A8 AF AC AB AA A9 A8 A0 A7 A6 A5 A4 A3 A2 A1 A0 99 Khng nh a ch bit 98 90

P.3 IE P2 SBUF SCON P1 TH1 TH0 TL1 TL0 TMOD

98 9F 9E 9D 9C 9B 9A 99 90 97 96 95 94 93 92 91 8D 8C 8B 8A 89 Khng nh a ch bit Khng nh a ch bit Khng nh a ch bit Khng nh a ch bit Khng nh a ch bit

22 17 16 15 14 13 12 11 10 21 0F 0E 0D 0C 0B 0A 09 08 20 07 06 05 04 03 02 01 00 1F 18 17 10 0F 08 07 00 Dy thanh ghi 0 (mc nh cho R0 -R7) Dy 3 Dy 2 Dy 1

88 8F 8E 8D 8C 8B 8A 89 87 Khng nh a ch bit 83 82 81 Khng nh a ch bit Khng nh a ch bit Khng nh a ch bit

88

TCON PCON DPH DPL SP

80 87 86 85 84 83 82 81

80

P0

Hnh : B nh d liu trn chip 8051

Gv : Nguyn Vn Sum

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Mn : Vi iu khin 8051

3.2.2 Vng RAM nh a ch bit: 8051 c cha 210 v tr bit c th a ch ho trong 128 bit a ch 20H n 2FH cn li nm trong thanh ghi chc nng c bit (s trnh by sau). tng truy xut ring tng bit qua phn mm l c bit mnh ca vi iu khin, cc bit c th c t, xo, AND, OR v.v... bng lnh n gin. Trong khi hu ht cc vi x l i hi tun t c sa ghi lnh to hiu qu nh vy. Hn na cc cng xut nhp ca 8051 l cc bit c th a ch ho lm n gin ho giao tip phn mm nhp hay xut tng bit mt.C 128 v tr c th a ch ho dng chung t byte c a ch 20FH n 2FH (8 bits x 16 bytes = 128 bits). Cc a ch c truy xut khi l byte khi l bit tu thuc vo lnh s dng. V d : SETB 7FH

3.2.3 Cc dy thanh ghi: 32 v tr thp nht ca b nh ni cha cc dy thanh ghi. Tp lnh ca 8051 cung cp 8 thanh ghi, t R0 n R7. Trng thi mc nh (sau khi h thng khi ng) cc thanh ghi ny a ch 00H-07H. Cc lnh dng cc thanh ghi t R0 n R7 th ngn v nhanh hn cc lnh tng ng dng a ch trc tip. Khi gi tr ca d liu c lp i lp li nn dng cc thanh ghi ny. Bng cch thay i cc bit chn dy thanh ghi trong t trng thi chng trnh ta s thay i mc tch cc cho dy thanh ghi. 3.2.4 Cc thanh ghi chc nng c bit (SFR) Cc thanh ghi ni 8051 c cu hnh ngay trong chip RAM v th mi thanh ghi c a ch. Chnh v l do ny m s thanh ghi trong 8051 khng th nhiu v d cc thanh ghi R0 n R7. Ngoi ra c 21 thanh ghi chc nng c bit nh ca RAM ni t 80H n FFH. Ch hu ht 128 bytes t 80H n FFH khng c xc nh ngoi tr 21 thanh ghi chc nng c bit (SRF) c xc nh.

Gv : Nguyn Vn Sum

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Bng sau trnh by chc nng ca cc thanh ghi c bit :

Thanh ghi A hoc ACC B DPL DPH IE IP SCON SBUF SP PSW PCON TCON TMOD TH0 TL0 TH1 TL1 P0 P1 P2 P3

a ch 0xE0 0xF0 0x82 0x83 0xA8 0xB8 0x98 0x99 0x81 0xD0 0x87 0x88 0x89 0x8C 0x8A 0x8D 0x8B 0x80 0x90 0xA0 0xB0

Tn thanh ghi Tch lu (Accumulator) Thanh ghi B Byte thp con tr d liu Byte cao con tr d liu Cho php ngt Quyn u tin ngt iu khin ni tip m d liu ni tip Con tr ngn xp T trng thi chng trnh iu khin ngun iu khin m / nh thi Ch m / nh thi Byte cao timer 0 Byte thp timer 1 Byte cao timer 0 Byte thp timer 1 Cng 0 Cng 1 Cng 3 Cng 4

3.2.4 Ngn xp
Thanh ghi dng truy cp ngn xp gi l SP (Stack Pointer) SP l thanh ghi 8 bit, c gi tr t 00h FFh Khi c cp ngun hay sau khi Reset SP = 07h Scratch pad RAM 30H Bit-Addressable RAM 20H 18H 17H 0FH 08H 07H 00H Register Bank 3 Register Bank 2 (Stack) Register Bank 1 Register Bank 0

Gv : Nguyn Vn Sum

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Khoa : in T- Vin Thng VD: MOV R6, #25H MOV R1, #12H MOV R4, #0F3H PUSH R6 PUSH R1 PUSH R4

Mn : Vi iu khin 8051

0BH 0AH 09H 08H Start SP=07H

Hai c tnh cn lu

0BH 0AH 09H 08H 25 SP=08H

0BH 0AH 09H 08H 12 25 SP=09H

0BH 0AH 09H 08H F3 12 25

SP=0AH

Cc thanh ghi v cc port I/O c nh a ch theo kiu nh x b nh (memory mapped) & do c truy xut nh 1 v tr nh trong b nh

Stack l trn RAM ni thay v trn RAM ngoi nh i vi cc b VXL

3.3 B nh ngoi v cc dch v truy xut 3.3.1 B nh ngoi Ngoi b nh trong ca 8051 ta c th m rng b nh cho 8051 c th l c th thm 64 Kb ROM v 64 Kb RAM. Khi dng b nh ngoi, nh sn xut khuyn co dung port 0 lm bus d liu (D0 D7) ng thi l bus a ch ca byte thp (A0 A7) bng tn hiu cht ALE cht byte thp ca a ch khi bt u mi chu k b nh ngoi. Cn port 2 dng cho byte cao ca bus a ch. Cch t chc port 0 va mang d liu va mang a ch, trong na u chu k b nh byte a ch thp c xut ra port 0 v c cht li bng ALE. IC cht 74HC373 hoc tng ng s gi byte thp ca i ch ny n ht cho chu k b nh. Trong na chu k th hai ca chu k b nh port 0 c dng nh bus d liu c c hay vit tu thuc vo thao tc ca lnh. Gv : Nguyn Vn Sum

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Khoa : in T- Vin Thng

Mn : Vi iu khin 8051 D0 D7 RAM (1K byte) A0 A7

Port 0 EA\
74HC573

AT89C51 ALE P2.0 P2.1 RD\ WR\ PSEN\ NC

D G

A8 A9 OE\ W\ CS\

Hnh : Truy xut b nh chng trnh ngoi 3.3.2 Truy xut ROM ROM l b nh ch c th c v c php truy xut bng tn hiu PSEN. Cch kt ni phn cng gia 8051 vi ROM nh hnh v: Mi chu k my ko di khong 12 xung clock. Nu 8051 hot ng vi ngun dao ng l 12Mhz th thi gian ca mt chu k my l 1s. Trong mt chu k my, xung ALE xut hin hai ln v hai byte c c ra t ROM (nu lnh hin hnh l lnh mt byte th byte th hai s c b qua). 3.3.3 Gii m a ch cho 8051 Nu c nhiu chip ROM hoc RAM cng giao tip vi 8051, vn c ra l phi gii m a ch cho chng. Vn gii m cng tng t nh hu ht cc vi x l. Thng thng ngi ta dng IC gii m nh 74HC138, ni cc chn ra ca n vi cc u vo chn chip (Chip Select CS) ca ROM hoc RAM. iu ny c minh ho trong hnh trn gii m cho h thng dng IC EROM 8K x 8 BIT (2764) v ADC 0809.

Gv : Nguyn Vn Sum

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Chng 4 CC THANH GHI CHC NNG C BIT (SFR)

4.1 Thanh ghi PSW Thanh ghi PSW (bit addressable) Bit PSW.7 PSW.6 PSW.5 PSW.4 PSW.3 PSW.2 PSW.1 PSW.0 P K hiu CY AC F0 RS1 RS0 OV a ch D7h D6h D5h D4h D3h D2h D1h D0h Bit chn dy thanh ghi 1 Bit chn dy thanh ghi 0 C trn D tr C kim tra chn l M t bit C nh C nh ph

AC

F0

RS1

RS0

OV

--

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RS1 R0-R7 0 0 1 1

RS0 0 1 0 1

Register Bank 0 1 2 3

Byte Address of 00H-07H 08H-0FH 10H-17H 18H-1FH

C (carry flag) - C nh c set bng 1 nu c s nh t php cng bit 7 hay c s mn mang n bit 7 MOV A, #FFH ADD A, #1

Cn c dng nh 1 thanh ghi 1 bit i vi cc lnh logic thao tc trn cc bit ANL C, 25H

AC (auxiliary carry) C nh ph

c set bng 1 nu c s nh t bit 3 sang bit 4

RS1, RS0 - Cc bit chn dy (bank) thanh ghi

Dng xc nh dy thanh ghi tch cc Chng c xa khi reset Set bng 1 sau php ton cng hoc tr nu c xut hin 1 trn s hc. Khi cc s c du c cng hoc tr, phn mm c th kim tra bit trn OV xc nh KQ c nm trong tm hay khng

OV (overflow flag) - C trn

Vi cc s c du, KQ nh hn -128 hoc ln hn +127 s set c OV = 1. Vi cc s khng du, OV=1 khi KQ vt qu 255

VD: 0F +7F 8E thp phn 15 +127 142

8EH biu din -114 khng ng vi KQ mong mun l 142 nn OV = 1

Gv : Nguyn Vn Sum

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P (parity) - C chn l

Kim tra chn l cho thanh cha A S cc bit 1 trong thanh cha A cng vi bit P lun lun chn MOV A, #10101101B P=1

Bit chn l c s dng kt hp vi cc chng trnh xut/nhp ni tip trc khi truyn d liu hoc kim tra chn l sau khi nhn d liu VD1: MOV A,#88H ADD A,#93H VD3: MOV A,#38H ADD A,#2FH VD2: MOV A,#9CH ADD A,#64H VD4: MOV A,#FFH ADD A,#1

VD: MOV A,#88H ADD A,#93H 88 +93 ---11B C=1 VD: MOV A,#38H ADD A,#2FH 38 +2F ---67 C=0 00111000 +00101111 -------------01100111 AC=1 P=1 AC=0 10001000 +10010011 -------------00011011 P=0

VD: MOV A,#9CH ADD A,#64H 9C +64 ---100 C=1 AC=1 VD: MOV A,#FFH ADD A,#1 A=00H; C=1;AC=1; 10011100 +01100100 -------------00000000 P=0

Nhng lnh nh hng n cc bit c

Gv : Nguyn Vn Sum

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4.2 Thanh ghi B B c dng vi thanh cha A trong cc php ton nhn, chia MUL A, B ; nhn 2 s 8-bit khng du cha trong A & B, KQ 16- bit cha vo cp thanh ghi B:A (B cha byte cao) DIV

AB

; chia A bi B, thng s ct trong A, d ct trong B

B cn c x l nh thanh ghi nhp B c nh a ch bit

Gv : Nguyn Vn Sum

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Mn : Vi iu khin 8051

F7
4.3 Con tr ngn xp (SP)

F6

F5

F4

F3

F2

F1

F1

SP cha a ch ca d liu hin ang nh ca stack Cc lnh lin quan n stack bao gm lnh ct d liu vo stack (lm tng SP trc khi ghi d liu) v lnh ly d liu khi stack (gim SP) Mun stack bt u 60H:

MOV

SP, #5FH

Th vng stack s l 32 byte trn 8051 v a ch cao nht ca RAM ni l 7FH

5FH c dng v SP tng ln 60H trc khi thao tc ct vo stack u tin c thc thi

Nu khng khi ng SP, ni dung mc nh l 07H ( duy tr s tng thch vi 8048) l thao tc ct vo stack u tin s lu d liu vo v tr nh c a ch 08H

Trong trng hp ny, nu phn mm ng dng khng khi ng SP, dy thanh ghi 1 (v c l 2, 3) s khng cn hp l v chng c s dng lm stack

PUSH & POP ct d liu vo stack v ly d liu t stack ACALL, LCALL, RET, RETI ct v phc hi b m chng trnh PC

VD:

MOV MOV MOV PUSH R6 PUSH R1 PUSH R4

R6, #25H R1, #12H R4, #0F3H

4.4 Con tr d liu (DPTR) DPTR c dng truy xut b nh chng trnh ngoi hoc b nh d liu ngoi

Gv : Nguyn Vn Sum

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Mn : Vi iu khin 8051

VD: MOV MOV MOVX A, #55H DPTR, #1000H @DPTR, A

83H 82H
4.5 Cc thanh ghi I/O port: P0, P1, P2, P3 Tt c port u c nh a ch bit VD: (iu khin motor ni bit P1.0) SETB P1.0 CLR P1.0

DPH DPL

on chng trnh kim tra trng thi BUSY ca thit b: WAIT: JB P1.5, WAIT

4.6 Cc thanh ghi nh thi 8051 c 2 b m/nh thi 16-bit nh cc khong thi gian hoc m cc s kin Hot ng ca b nh thi c thit lp bi:

TMOD (Timer Mode Register) TCON (Timer Control Register)

4.7 Cc thanh ghi ca port ni tip 8051 c 1 port ni tip truyn thng vi cc thit b ni tip SBUF (Serial Data Buffer): lu tr d liu truyn v nhn SCON (Serial Port Control Register): chn ch hot ng 4.8 Cc thanh ghi ngt IE (interrupt enable) IP (interrupt priority)

Gv : Nguyn Vn Sum

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Khoa : in T- Vin Thng

Mn : Vi iu khin 8051

Chng 5

TP LNH CA 8051

5.1 Cc ch nh a ch D liu cha u khi thc thi 1 lnh? Nhiu li gii tng ng cc kiu nh a ch khc nhau Cc kiu nh a ch cho php xc nh ngun v ch ca d liu theo nhiu cch khc nhau ty tnh hung lp trnh. 1. Thanh ghi ( register ) 2. Trc tip ( direct ) 3. Gin tip ( inderect ) 4. Tng i ( immediate ) 5. Tuyt i ( relative ) 6. Di ( long ) 7. Tham chiu (Index) 5.1.1 a ch ha thanh ghi Trong 8051 c 4 bank thanh ghi, mi thanh ghi c 8 thanh ghi c k hiu R0 n R7. Trong mi thi im ch c mt thanh ghi c kch. Mun chn thanh ghi no ta ch cn gn ni dung nh phn thch hp vo thanh ghi t trng thi (PSW). Trong ch ny ta khng quan tm n a ch thanh ghi m ch quan tm n tn thanh ghi c n nh sn A, B, DPTR, PC MOV ADD MOV Rn, A A, Rn DPL, R6 ;n=0,..,7

5.1.2 a ch ha trc tip Trong ch ny lnh tc ng trc tip ln ni dung ca thanh ghi ni bn trong 8051 MOV A, #65H MOV R6, #65H MOV DPTR, #2343H Gv : Nguyn Vn Sum

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Khoa : in T- Vin Thng

Mn : Vi iu khin 8051

MOV P1, #65H VD : Num EQU 30 MOV R0, #Num MOV DPTR, #data1 ORG 100H data1: db DANATES

5.1.3 a ch ha gin tip Lm th no nhn bit 1 bin khi a ch bin c xc nh, tnh ton hoc sa i trong khi 1 chng trnh ang chy? Khi qun l cc v tr nh lin tip. Cc im nhp c nh ch s trong cc bng cha trong RAM (cc dy s hay cc chui k t) Gii php l kiu nh a ch gin tip Khi ny, thanh ghi c s dng nh 1 con tr (pointer) n d liu MOV A, @Ri MOV @R1, B Ni cch khc, ni dung ca cc thanh ghi R0 hay R1 c th l ngun hoc ch trong cc lnh MOV, ADD & SUBB

; copy d liu tr bi Ri vo A (i=0 hay 1)

8051 dng du @ trc mt gi tr nh a ch gin tip. Gi tr ny c th nm trong ton t dung hng, k hiu nh ngha hay biu thc s hc Assembler s t ng tnh ton v thay th d liu trc tip vo trong lnh

Bi ton 7. Copy bytes trong RAM ni Vit chng trnh copy 10 bytes t vng RAM c a ch bt u l 37H ti vng RAM c a ch bt u l 59H Gii p: MOV R0,37h MOV R1,59h MOV R2,10 Gv : Nguyn Vn Sum ; Con tr ngun ; Con tr ch ; B m Trang: 22

Khoa : in T- Vin Thng

Mn : Vi iu khin 8051

L1:

MOV A,@R0 MOV @R1,A INC INC R0 R1

DJNZ R2,L1 Bi ton 7. Xa RAM ni Vit chng trnh xa RAM ni t 60H 7FH Tr li: MOV R0, #60H LOOP: MOV @R0, #0 INC R0

CJNE R0, #80H, LOOP 5.1.4 a ch tng i a ch tng i c dng trong cc lnh nhy, 8051 dng gi tr 8 bit c du cng thm vo trong thanh ghi m chng trnh (PC). Tm nhy ca lnh ny trong khong -128 n 127 nh. Trc khi cng, thanh ghi PC s tng a ch sau lnh nhy ri tnh ton a ch offset cn thit nhy n a ch yu cu. Thng lnh ny c lin quan n nhn c nh ngha trc. 5.1.5 a ch tuyt i a ch tuyt i dng trong cc lnh ACALL v AJMP. Lnh 2 byte ny s dng r nhnh vo trong 2 Kb ca b nh m bng cch cp 11 byte (A0-A10) xc nh a ch ch. Cn 5 byte cao xc nh a ch ch ca vng nh 2 Kb no.
A15 A10 A0

Xc nh trang m

Xc nh a ch trongtrang m

Gv : Nguyn Vn Sum

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Khoa : in T- Vin Thng

Mn : Vi iu khin 8051

5.1.6 a ch di a ch di ch dng cho lnh LCALL v lnh LJMP. Lnh ny gm ngt byte v dng 2 byte sau (byte 2 v byte 3) nh a ch ca lnh. u im ca lnh ny l c th s dng ton b vng nh 64 Kb. Tuy nhin lnh ny chim nhiu byte (3 byte) v l thuc vo v tr vng nh. 5.1.7 a ch tham chiu a ch tham chiu dng thanh ghi c bn (thanh ghi PC hoc thanh ghi con tr d liu DPTR) v a ch offset (trong thanh ghi A) to a ch tc ng cho cc lnh JMP hoc MOVC. Bng nhy hoc bng tm kim (look-up) d dng to c s dng a ch tham chiu. c s dng khi truy cp cc thnh phn d liu ca bng nhy hoc bng tm kim MOVC A, @A+DPTR

A = ni dung ti a ch A+DPTR trong ROM Ch :

Cc thnh phn d liu c lu trong khng gian b nh chng trnh ROM ca 8051, nn s dng MOVC thay v MOV. C: code. Thanh ghi nn Offset a ch tc ng

PC (or DPTR)

PC (or DPTR)

Bi ton 7.3. Copy bytes ROM v RAM VD: Gi s khng gian b nh ROM bt u ti a ch 250H cha ROBOCON, vit chng trnh truyn cc bytes trn vo vng nh RAM bt u ti a ch 40H
Gii p: ORG MOV MOV L1: CLR MOVC JZ MOV 0 DPTR,#MYDATA R0,#40H A A,@A+DPTR L2 @R0, A

Gv : Nguyn Vn Sum

Trang: 24

Khoa : in T- Vin Thng INC INC SJMP L2: SJMP DPTR R0 L1 L2

Mn : Vi iu khin 8051

;------------------------------------ORG MYDATA: END 250H DB ROBOCON,0

Bi ton 7. c x & xut x2 Vit chng trnh c gi tr x t port 1 v xut gi tr x2 ra port 2 ? Gii p: ORG MOV MOV MOV L01: MOV MOVC MOV SJMP A, P1 A, @A+DPTR P2, A L01 0 DPTR, #TAB1 A, #0FFH P1, A ; ch !

;---------------------------------------------------ORG TAB1: DB END MOVC A,@A+PC ;hot ng tng t, ngoi tr y, b m chng trnh PC c dng cha a ch nn v bng c truy xut nh vo chng trnh con. S ca im nhp (entry-number) yu cu cho vo thanh cha A, sau chng trnh con c gi. Bng phi c nh ngha ngay sau lnh RET trong chng trnh. MOV A, entry-number CALL TIM-KIEM Gv : Nguyn Vn Sum Trang: 25 300H 0,1,4,9,16,25,36,49,64,81

Khoa : in T- Vin Thng

Mn : Vi iu khin 8051

TIM-KIEM: INC A MOVC RET TABLE: DB data1,data2,data3, A, @A+PC

5.2 Cc nhm lnh ca 8051 c chia lm 5 nhm sau: S hc Lun l Chuyn d liu Bin lun l R nhnh chng trnh
Cc ch dn thit lp lnh Rn Data : : Thanh ghi R0 n R7 ca bank thanh ghi c chn 8 bit a ch vng d liu trong. N c th l vng RAM d liu trong (0-127) hoc cc thanh ghi chc nng c bit (SFR) @Ri : 8 bit vng RAM d liu trong (0-255) c a ch ha gin tip qua thanh ghi R0 hoc R1 #data #data addr16 addr11 Rel : : : : : hng 8 bit cha trong cu lnh hng 16 bit cha trong cu lnh 16 bit a ch ch c dng trong cu lnh LCALL v LJMP 11 bit a ch ch c dng trong cu lnh ACALL v AJMP. byte offset 8 bit c du c dng trong lnh SJMP v nhng lnh nhy c iu kin.

5.2.1 Nhm lnh x l s hc:

ADD A, Rn ADD A, direct ADD A, @Ri : : : cng ni dung mt thanh ghi (Rn) vo thanh ghi A cng trc tip 1 byte vo thanh ghi A cng gin tip ni dung RAM cha ti a ch c khai bo trong Ri vo thanh ghi A ADD A, #data ADDC ADDC A, Rn A, direct : : : cng d liu tc thi vo A cng ni dung thanh ghi vo vi c nh (carry) cng trc tip d liu vo A vi c nh

Gv : Nguyn Vn Sum

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Khoa : in T- Vin Thng ADDC ADDC A, @Ri A, #data

Mn : Vi iu khin 8051

: cng gin tip ni dung RAM vo A vi c nh : cng d liu tc thi vo A vi c nh

VD ADD ADD A,#6 ADD A,R6 ADD A,6 ADDC SETB C ADDC A,R5 A, Source ;A=A+6 ;A=A+R6 ;A=A+[6] or A=A+R6 A, source ;CY=1 ;A=A+R5+1 ;A=A+source+CY ;A=A+Source

SUBB A, Ri : tr ni dung thanh ghi A vi ni dung thanh ghi Ri ri ct kt qu vo thanh ghi A. SUBB A, direct : vo thanh ghi A SUBB A, @Ri vo thanh ghi A SUBB A, #data vo thanh ghi A VD : tr ni dung thanh ghi A cho d liu tc thi ct kt qu : tr ni dung thanh ghi A cho ni dung RAM ct kt qu tr ni dung thanh ghi A cho mt s tc thi ct kt qu

SUBB SETB SUBB

INC INC INC INC INC A Rn direct @Ri : DPTR : : : :

A, source C A,R5

;A=A-source-CY ;CY=1 ;A=A-R5-1

tng ni dung thanh ghi A ln thanh ghi tng ni dung thanh ghi Rn ln 1 : tng ni dung trc tip ln 1

tng gin tip ni dung vng RAM ln 1 : tng ni dung con tr d liu

DEC A DEC Rn DEC direct

gim ni dung thanh ghi A ln 1 gim ni dung thanh ghi Rn ln 1 : gim ni dung trc tip ln 1

DEC @Ri : MUL AB VD :

gim gin tip ni dung thanh ghi Rn ln 1 nhn ni dung thanh ghi A vi ni dung thanh ghi B

Gv : Nguyn Vn Sum

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Khoa : in T- Vin Thng

Mn : Vi iu khin 8051

MUL MOV MOV MUL

AB A,#25H B,#65H AB

;B|A = A*B

;25H*65H=0E99 ;B=0EH, A=99H

DIV

AB

chia ni dung thanh ghi A vi ni dung thanh ghi B

DIV MOV MOV DIV

DA A :

AB A,#25 B,#10 AB

;A = A/B, B = A mod B

;A=2, B=5

iu chnh thp phn thanh ghi

5.2.2 Nhm lnh logic ANL A, Rn

ANL A, @Ri

: AND thanh ghi Rn vi thanh ghi A ri ct kt qu vo A.

: AND gin tip ni dung RAM vi thanh ghi A ri ct kt qu vo A

ANL A, direct : AND trc tip 1 byte vi thanh ghi A ri ct kt qu vo A

ANL A, #data ANL direct, A

: AND d liu tc thi vi thanh ghi A ri ct kt qu vo A : AND ni dung A vi mt byte ri ct kt qu vo bin trc tip A

ANL direct, #data AND d liu tc thi vi mt byte ri ct kt qu vo bin trc tip ANL A, Rn : OR ni dung thanh ghi Rn vi ni dung thanh ghi A ri ct kt qu vo thanh ghi A ORL A, direct : OR trc tip 1 byte ni dung thanh ghi A ri ct kt qu vo thanh ghi A ORL A, @Ri : OR gin tip ni dung RAM vi ni dung thanh ghi A ri ct kt qu vo thanh ghi A ORL A, #data : OR d liu tc thi vi ni dung thanh ghi A ri ct kt qu vo thanh ghi A ORL direct, A : OR thanh ghi A vi 1 byte ri ct kt qu vo bin trc tip ORL direct, #data OR d liu tc thi vi 1 byte ri ct kt qu vo bin trc tip

Gv : Nguyn Vn Sum

Trang: 28

Khoa : in T- Vin Thng XRL A, Rn :

Mn : Vi iu khin 8051

XOR ni dung thanh ghi Rn vi ni dung thanh ghi A ri ct kt qu vo thanh ghi A

XRL A, direct XRL A, #data

: :

XOR trc tip 1 byte vi ni dung thanh ghi

XOR tc thi d liu vi ni dung thanh ghi A ri ct kt qu vo thanh ghi A

XRL direct, A

XOR ni dung thanh ghi A vi 1 byte ri ct kt qu vo bin trc tip

XRL direct,@data

XOR d liu tc thi vi 1 byte ri ct kt qu vo trc tip

CLR CPL RL RLC RR RRC SWAP A

A A A A A A :

: : : : : : i

Xa ni dung thanh ghi A B ni dung thanh ghi A Quay tri ni dung thanh ghi A Quay tri ni dung thanh ghi A thng qua c C Quay phi ni dung thanh ghi A Quay phi ni dung thanh ghi A thong qua c C byte ni dung A

5.2.3 Nhm lnh chuyn d liu

MOV MOV MOV MOV MOV MOV MOV MOV MOV A, Rn A, direct A, @Ri A, #data Rn, A : : : : : Chuyn ni dung thanh ghi A vo thanh ghi A Chuyn trc tip 1 byte vo thanh ghi Chuyn ni dung RAM vo thanh ghi A Chuyn d liu tc thi vo thanh ghi A Chuyn ni dung thanh ghi A vo thanh ghi Rn Chuyn d liu tc thi vo thanh ghi Rn Chuyn ni dung thanh ghi A vo 1 byte Chuyn ni dung thanh ghi Rn vo 1 byte

Rn, direct : direct, A :

direct, Rn :

direct, direct : Chuyn 1 byte vo 1 byte

VD MOV MOV MOV MOV MOV dest, source A, #72H R4, #62H A, R4 B, 7EH ; dest = source ;A=72H ;R4=62H ;A=62H

Gv : Nguyn Vn Sum

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Khoa : in T- Vin Thng

Mn : Vi iu khin 8051

MOV
XCH A, Rn

P1, A
ghi Rn

;mov A to port 1

: Trao i ni dung thanh ghi A vi mt ni dung thanh

XCH XCH

A, direct A, Rn

: Trao i 1 byte trc tip vi ni dung thanh ghi A : Trao i gin tip RAM vi ni dung thanh ghi A : Trao i nible th t thp gin tip RAM vo thanh ghi

XCHD A, @Ri A

5.2.4 Nhm lnh thao tc trn bin lun l:

CLR CLR SETB SETB CPL CPL ANL ANL ORL MOV MOV C bit C bit C bit C, bit C, /bit C, /bit C, bit bit, C : : : : : : : : : : : Xa c nh Xa trc tip 1 bit Lp c nh Lp trc tip 1 bit Ly b c nh Ly b trc tip 1 bit AND trc tip bit vi c nh AND 1 bit ly b vi c nh OR trc tip bit vi c nh Chuyn 1 bit vo c nh Chuyn c nh vo 1 bit

5.2.5 Nhm lnh iu khin ACALL addr11 : Gi chng trnh con (gi tuyt i)
LCALL RET RETI trnh 3 AJMP LJMP addr11 addr16 : : Nhy tuyt i Nhy xa adddr 16 : : : Gi chng trnh con Lnh quay v t chng trnh con Lnh quay v t chng trnh phc v chng

SJMP
JMP JZ JC JNC

rel
rel rel rel

:
: : :

Nhy ngn (i ch tng i)

Nhy gin tip t con tr d liu Nhy nu ni dung thanh ghi A l 0 Nhy nu c C c lp Nhy nu c C khng c lp.

@A+DPTR

Gv : Nguyn Vn Sum

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Khoa : in T- Vin Thng

Mn : Vi iu khin 8051

Chng 6
6.1 Gii thiu

HOT NG NH THI

8051 c 2 timers/counters: timer/counter 0 & timer/counter 1. Chng c th c dng nh: B nh thi (Timer) dng nh 1 b to trNgun xung clock chnh l dao ng thch anh bn trong B m s kin (Event Counter)u vo t chn bn ngoi m s s kin C th dng m s ngi i qua cng, s vng quay ca bnh xe, hay bt k cc s kin m chuyn c sang dng xung To tc baud (baud rate) cho port ni tip ca 8051 Timer Khi to gi tr ban u cho cc thanh ghi Kch hot Timer, sau 8051 tnh ln Ng vo l t clock ni (machine cycle) Khi cc thanh ghi bng 0 th 8051 s set c trn

8051

Set Timer 0

P2

P1 TH0 TL0

to LCD

Counter m s s kin: Ch ra s s kin trn cc thanh ghi Counter 0: Ng vo t chn bn ngoi T0 (P3.4) Counter 1: Ng vo t chn bn ngoi T1 (P3.5)

Gv : Nguyn Vn Sum

Trang: 31

Khoa : in T- Vin Thng

Mn : Vi iu khin 8051

TH0 TL0 P3.4 a switch T0 Cc thanh ghi dng truy xut Timer/Counter TH0, TL0, TH1, TL1

P1

to LCD

TMOD thanh ghi ch nh thi (Timer mode register) TCON thanh ghi iu khin nh thi (Timer control register)

8052 vi 3 timers/counters s c thm cc thanh ghi T2CON (Timer 2 control register), TH2 and TL2

SFR Name TH0 TL0 TH1 TL1 TCON TMOD

Description Timer 0 High Byte Timer 0 Low Byte Timer 1 High Byte Timer 1 Low Byte Timer Control Timer Mode

SFR Address 8Ch 8Ah 8Dh 8Bh 88h 89h

TH0, TL0, TH1, TL1 (not bit addressable) C timer 0 & timer 1 u c rng 16 bits Cc thanh ghi ny lu tr - Gi tr to thi gian tr (time delay) (nu l timer) - S s kin (number of events) (nu l counter) Timer 0: TH0 & TL0 - Timer 0 high byte, timer 0 low byte Timer 1: TH1 & TL1 - Timer 1 high byte, timer 1 low byte

Gv : Nguyn Vn Sum

Trang: 32

Khoa : in T- Vin Thng

Mn : Vi iu khin 8051

Mi b nh thi 16-bit c th c truy cp nh 2 thanh ghi 8-bit tch

bit

TH0
D15 D14 D13 D12 D11 D10 D9 D8

TL0
D7 D6 D5 D4 D3 D2 D1 D0

Timer 0 TH1
D15 D14 D13 D12 D11 D10 D9 D8

TL1
D7 D6 D5 D4 D3 D2 D1 D0

Timer 1
6.2 Thanh ghi ch nh thi TMOD Timer mode register: TMOD (not bit addressable)Thanh ghi 8-bit Thit lp ch hot ng cho cc b nh thi: o 4 bits thp dnh cho Timer 0 (Set to 0000 if not used)
o 4 bits cao dnh cho Timer 1 (Set to 0000 if not used)

(MSB)
GATE C/T M1 M0 GATE C/T M1

(LSB)
M0

Timer 1
o GATE

Timer 0

Bit iu khin cng. Khi set ln 1, timer ch hot ng khi chn /INTx mc cao v TRx = 1. Khi xa, timer hot ng khi TRx = 1

o C/T thi o M1 o M0

Bit chn chc nng m hoc nh thi: 1: m; 0: nh

Chn mode - bit 1 Chn mode - bit 0

GATE GATE=0 o iu khin bn trong (Internal control) o Bt hay tt timer bng phn mm o Timer c cho php khi TR c set Gv : Nguyn Vn Sum Trang: 33

Khoa : in T- Vin Thng

Mn : Vi iu khin 8051

GATE=1 o iu khin bn ngoi (External control) o Bt hay tt timer bng phn mm & mt ngun bn ngoi (external source) o Timer c cho php khi chn /INT mc cao & TR c set

M1

M0

Mode

Hot ng Ch nh thi 13 bit 8-bit THx + 5-bit TLx (x= 0 or 1) Ch nh thi 16 bit 8-bit THx + 8-bit TLx Ch t ng np li 8 bit (auto reload mode) 8-bit auto reload timer/counter; THx l tr gi tr np li cho TLx mi khi u trn (overflow) Ch thi chia s nh (Split timer mode)

VD: Tm gi tr TMOD nu mun lp trnh Timer 0 lm vic mode 2 ? Dng 8051 XTAL cho xung clock, & dng lnh bt hay tt timer

timer 1

timer 0

TMOD= 0000 0010

Timer 1 khng dng Timer 0, mode 2 GATE = 0 iu khi bng phn mm

Gv : Nguyn Vn Sum

Trang: 34

Khoa : in T- Vin Thng

Mn : Vi iu khin 8051

Chng 7
7.1 Gii thiu

GIAO TIP NI TIP

Port ni tip hot ng song cng (full duplex), ngha l c kh nng thu v pht ng thi S dng 2 thanh ghi chc nng c bit SBUF (a ch byte l 99H) & SCON (a ch byte l 98H) truy xut port ni tip Vic ghi ln SBUF s np d liu pht, v vic c SBUF s truy xut d liu nhn c thc ra c 2 SBUF ring r SCON cha cc bit trng thi v iu khin, thanh ny c nh a ch bit Tn s hot ng ca port ni tip hay cn gi l tc baud (baud rate) c th c nh hoc thay i

TXD (P3.1)

RXD (P3.0)

D Clk SBUF Q (write only) Baud rate clock (pht) Baud rate clock (thu) Shift Register Clk

SBUF (read only)

8051 internal bus

7.2 Thanh khi iu khin port ni tip SM0 SM1 SM2 REN SM1, SM0 : chn ch ca port ni tip SM2 : cho php truyn thng a x l REN : cho php thu, phi c set nhn cc k t SCON TB8 RB8 TI RI

Gv : Nguyn Vn Sum

Trang: 35

Khoa : in T- Vin Thng

Mn : Vi iu khin 8051

TB8 : bit th 9 c pht ch 2 & 3 RB8 : bit th 9 nhn c TI : c ngt pht, c set ngay sau khi kt thc vic pht 1 k t; c xa bi phn mm RI : c ngt thu, c set ngay sau khi kt thc vic thu 1 k t; c xa bi phn mm 7.3 Cc ch hot ng SM0 SM1 Mode M t 0 0 1 1 0 1 0 1 0 1 2 3 Thanh ghi dch UART 8-bit UART 9-bit UART 9-bit Tc baud C nh (fOSC/12) Thay i (thit lp bi b nh thi) C nh (fOSC/12 hoc fOSC/64) Thay i (thit lp bi b nh thi)

7.3.1 Thanh ghi dch 8-bit (mode 0) Khi pht v thu d liu 8-bit, bit LSB c pht hoc thu trc tin Tc baud c nh = fOSC/12 Chn RxD dng cho c vic thu pht d liu trong khi TxD dng lm chn xut clock dch bit Pht: Ghi vo SBUF D liu c dch ra ngoi trn chn RxD (P3.0) Xung clock dch bit c gi ra trn chn TxD (P3.1) Mi bit hp l truyn i trn RxD trong 1 chu k my Thu: Ch c khi ng khi REN = 1 & RI = 0, ngha l phi set REN = 1 thi im bt u chng trnh & xa RI bt u cng vic thu d liu D liu c dch vo chn RxD bi xung clock dch bit (tc ng sn ln)

Gv : Nguyn Vn Sum

Trang: 36

Khoa : in T- Vin Thng

Mn : Vi iu khin 8051

1 ng dng ca mode 0: M rng thm cc ng ra cho 8051

8 ng ra m rng 8051 TxD(P3.1) RxD(P3.0)

Clock Shift Regsiter Data

7.3.2 UART 8-bit c tc baud thay i (mode 1) UART l b thu pht d liu ni tip vi mi k t d liu c ng trc bi 1 bit start v ng sau bi 1 bit stop. Thnh thong 1 bit parity c chn vo. Hot ng ch yu ca UART l bin d liu pht t // thnh nt v bin d liu thu t nt thnh // C ngt pht TI c set bng 1 ngay khi bit stop xut hin trn TxD Vic nhn c khi ng bi 1 chuyn trng thi t 1 xung 0 trn ng RxD (bit start) Bit start sau c b qua & 8 bit d liu sau c nhn tun t vo thanh ghi dch bit ca port ni tip. Khi c 8 bit c nhn, ta c: Bit th 9 (bit stop) RB8 ca SCON 8 bit d liu c np vo SBUF C ngt thu RI c set Note: Cc iu trn ch xy ra nu trc c RI = 0

Gv : Nguyn Vn Sum

Trang: 37

Khoa : in T- Vin Thng

1 / baud rate TxD Start bit

Mn : Vi iu khin 8051

Stop bit D0 D1 D2 D3 D4 D5 D6 D7 TI (ready for more data)

TI

7.4 Khi ng v truy xut cc thanh ghi Cho php nhn: REN trong SCON phi c set bi phn mm cho php nhn k t : SETB REN Hoc MOV SCON, #xxx1xxxxB Thm vo bit chn l: bit P trong PSW c set hoc xa mi chu k my thit lp vic kim tra chn cho 8 bit cha trong A MOV C, P MOV TB8, C MOV SBUF, A ; a bit kim tra chn vo TB8 ; bit ny tr thnh bit th 9 ; di chuyn 8 bit d liu vo SBUF

Cc c ngt: RI v TI c set bng phn cng nhng phi xa bng phn mm CTC nhn 1 k t qua port ni tip nh sau: INCHAR: JNB RI, $ CLR RI MOV A, SBUF RET CTC pht 1 k t qua port nt: OUTCHAR: JNB TI, $ CLR TI MOV SBUF, A RET

Gv : Nguyn Vn Sum

Trang: 38

Khoa : in T- Vin Thng

Mn : Vi iu khin 8051

7.5 Tc baud ca port ni tip

On-chip OSC Mode 0

1 2 6 4
SMOD=0 SMOD=1

Baud rate clock

On-chip OSC Mode 2

Timer 1 overflow Mode 1 & 3

3 2 3 2 1 6

Baud rate clock

SMOD=0 SMOD=1 Baud rate clock

Dng timer 1 lm xung clock tc baud Thng thng khi ng thanh ghi TMOD ch t ng np li 8-bit (mode 2) & t gi tr np li thch hp vo thanh ghi TH1 c tc trn ng, t to ra tc baud MOV TMOD, #0010xxxxB ;for timer 1

Baud rate = Timer 1 overflow / 32 hay /16 ty thuc gi tr bit SMOD Tnh ton cc gi tr np li cho thanh ghi TH1 i vi cc tc baud 9600, 4800, 2400, 1200 (XTAL = 11, 0592MHz) Tc baud 9600 1200 19200 9600 4800 2400 1200 Tn s thch anh (MHz) 12 12 11,0592 11,0592 11,0592 11,0592 11,0592 Tc Gi tr np baud thc cho TH1 t -7 (F9H) -26 (E6H) -3 (FDH) -3 (FDH) -6 (FAH) -12 (F4H) -24 (E8H) 8929 1202 19200 9600 4800 2400 1200

SMOD 1 0 1 0 0 0 0

Sai s ~7% 0,16% 0% 0% 0% 0% 0%

Gv : Nguyn Vn Sum

Trang: 39

Khoa : in T- Vin Thng

Mn : Vi iu khin 8051

Tm li: Nu PCON.7 = 0 TH1 = 256 - ((Crystal / 384) / Baud) Nu PCON.7 =1 TH1 = 256 - ((Crystal / 192) / Baud) Lm vd vi baud rate 19200 chng t vai tr bit SMOD 11.059Mhz crystal: TH1 = 256 - ((Crystal / 384) / Baud) TH1 = 256 - ((11059000 / 384) / 19200 ) TH1 = 256 - ((28,799) / 19200) TH1 = 256 - 1.5 = 254.5 Nu set 254 ta t c 14,400 baud cn vi 255 ta t c 28,800 baud Set PCON.7 (SMOD). Ta c: TH1 = 256 - ((Crystal / 192) / Baud) TH1 = 256 - ((11059000 / 192) / 19200) TH1 = 256 - ((57699) / 19200) TH1 = 256 - 3 = 253 Kt lun vi 19,200 baud (11.059MHz crystal) ta phi: o Cu hnh Port ni tip mode 1 or 3 o Timer 1 hot ng mode 2 (8-bit auto-reload) o Set TH1 bng 253 o Set PCON.7 (SMOD)

Gv : Nguyn Vn Sum

Trang: 40

Khoa : in T- Vin Thng

Mn : Vi iu khin 8051

Chng 8
8.1 Gii thiu
time

LP TRNH NGT

Main

(a) Thc thi chng trnh khng c ngt

ISR Main Main time

ISR Main

ISR Main

Thc thi mc ngt Thc thi mc nn

(b) Thc thi chng trnh c ngt

8.2 T chc ngt C 5 nguyn nhn to ngt i vi h 51: 2 ngt ngoi, 2 ngt b nh thi, 1 ngt do port ni tip Khi reset, tt c cc ngt u b v hiu ha Khi xy ra 2 hay nhiu ngt ng thi, hay 1 ngt mi xut hin trong khi 1 ngt ang thc thi ta c 2 s x l ngt: s chui vng (c nh) v s 2 mc u tin (lp trnh bi ngi dng) Thanh ghi cho php ngt IE

Gv : Nguyn Vn Sum

Trang: 41

Khoa : in T- Vin Thng

Mn : Vi iu khin 8051

Bit IE.7 IE.6 IE.5 IE.4 IE.3 IE.2 IE.1 IE.0

K hiu a ch bit EA -ET2 ES ET1 EX1 ET0 EX0 AFH AEH ADH ACH ABH AAH A9H A8H

M t Cho php/khng cho php ton cc Non-used Cho php ngt do Timer 2 Cho php ngt do port ni tip Cho php ngt do Timer 1 Cho php ngt t bn ngoi ( ngt ngoi 1) Cho php ngt do Timer 0 Cho php ngt t bn ngoi ( ngt ngoi 0)

Thanh ghi u tin ngt IP Bit 7 6 5 4 3 2 1 0 Tn PS PT1 PX1 PT0 PX0 a ch bit BCh BBh BAh B9h B8h M t Undefined Undefined Undefined Serial Interrupt Priority Timer 1 Interrupt Priority External 1 Interrupt Priority Timer 0 Interrupt Priority External 0 Interrupt Priority

8.3 X l ngt Khi c 1 ngt xut hin v c CPU chp nhn c cc thao tc sau: Hon tt vic thc thi lnh hin hnh PC c ct vo stack (Trng thi ca ngt hin hnh c lu gi li) Cc ngt c chn li mc ngt Gv : Nguyn Vn Sum Trang: 42

Khoa : in T- Vin Thng

Mn : Vi iu khin 8051

PC c np a ch vector ngt ca ISR Thc thi ISR Cc c gy ngt Ngt Do bn ngoi (ngt ngoi 1) Do bn ngoi (ngt ngoi 0) Do b nh thi 1 Do b nh thi 0 Do port ni tip Do port ni tip Do b nh thi 2 Do b nh thi 2 Cc vector ngt Ngt do Reset h thng Ngt ngoi 0 B nh thi 0 Ngt ngoi 1 B nh thi 1 Port ni tip B nh thi 2 RST IE0 TF0 IE1 TF1 RI hoc TI TF2 hoc EXF2 C a ch vector 0000H 0003H 000BH 0013H 001BH 0023H 002BH C gy ngt IE1 IE0 TF1 TF0 TI RI TF2 EXF2 SFR & v tr bit TCON.3 TCON.1 TCON.7 TCON.5 SCON.1 SCON.0 T2CON.7 (8052) T2CON.6 (8052)

Gv : Nguyn Vn Sum

Trang: 43

Khoa : in T- Vin Thng

Mn : Vi iu khin 8051

8.4 Thit k chng trnh s dng ngt Khun mu chng trnh c s dng ngt: ORG 0000H LJMP MAIN . . . ORG 0030H MAIN: . . . ; im nhp ca chng trnh chnh ; chng trnh chnh bt u ; cc im nhp ca ISR ; im nhp sau khi reset

8.4.1 ISR kch thc nh

ORG 0000H LJMP MAIN ORG 000BH T0ISR: . . RETI

; im nhp sau khi reset

; im nhp ca ngt do Timer 0 ; bt u ISR cho Timer 0

; tr v chng trnh chnh

MAIN:

. .

; chng trnh chnh bt u

Gv : Nguyn Vn Sum

Trang: 44

Khoa : in T- Vin Thng

Mn : Vi iu khin 8051

8.4.2 ISR kch thc ln

ORG 0000H LJMP MAIN ORG 0003H RETI ORG 000BH LJMP T0ISR ORG 0013H RETI ORG 001BH RETI ORG 0023H RETI

; im nhp sau khi reset

;external interrupt 0

; im nhp ca ngt do Timer 0

;external interrupt 1

;timer 1 interrupt

;serial port interrupt

ORG 0030H MAIN: .

;bt du chng trnh chnh

_____________________________________________ T0ISR: . RETI ; tr v chng trnh chnh . ; bt u ISR cho Timer 0

Ch : V cc vector ngt t y chng trnh nn lnh u tin bao gi cng l lnh nhy di qua khi vng nh cha cc vector ngt ti chng trnh chnh

Gv : Nguyn Vn Sum

Trang: 45

Khoa : in T- Vin Thng

Mn : Vi iu khin 8051

8.5 Cc ngt do port ni tip Cc ngt ny xut hin khi c ngt pht TI hoc c ngt thu RI c set bng 1 C gy ra ngt port ni tip khng c xa bi phn cng khi CPU tr ti ISR 8.6 Cc ngt ngoi Xy ra khi c mc thp hoc c cnh m trn chn /INT0 hoc /INT1 Cc c gy ra cc ngt ny l cc bit IE0, IE1 ca TCON Vic chn cc ngt loi tc ng mc hay cnh c lp trnh thng qua cc bit IT0 v IT1 ca TCON Cc c gy ngt IE0, IE1 t ng c xa khi CPU tr ti ISR tng ng 8.7 Vn bo v thanh ghi ISR thng phi thit k sao cho c th bo v c nhng thanh ghi sau: PSW DPTR (DPH/DPL) ACC B R0-R7

Gv : Nguyn Vn Sum

Trang: 46