3121N-H

PLC-IOT Module Datasheet

 Revision History

Version Date Revision Content Draft Approved

1.0 2019-07-24 Original Version 谭道海 Sunny

2.0 2019-09-03 Delete GPIO20, add PWM1/GPIO5 李显 Sunny

multiplex
 CONTENTS
1 Overview ....................................................................................................................1

2 Block Diagram ...........................................................................................................1

3 Features ......................................................................................................................1

4 Dimension And Pin Definition .................................................................................3

4.1 Dimension...............................................................................................................................3

4.2 Pin Definition.........................................................................................................................3

5 Inteface Design Introduction ..................................................................................6

5.1 Input Power Requirement.................................................................................................6

5.2 GPIO Introductions..............................................................................................................6

5.3 SOR Introductions...............................................................................................................6

5.4 Debug Uart Introductions.................................................................................................6

5.5 PLC Transmission Circuit...................................................................................................6

5.6 PLC Receiving Circuit..........................................................................................................7

5.7 AC220 Power Supply Design Suggestions..................................................................7

6 Typical Applications................................................................................................. 9

6.1 AC220 L-N Coupling...........................................................................................................9

6.2 DC Coupling..........................................................................................................................9

6.3 CCO& STA Typical Networking And Topology.........................................................10

6.3.1 CCO&STATypical Networking.................................................................................10

6.3.2 CCO&STA 's Tree Topology ....................................................................................11

7 Networking Test Introductions............................................................................... 11

3121N-H
1 Overview
3121N-H is a fully integrated power carrier (PLC) communication module, with ultra-small

size、compact structure、wiring easy,it can be widely used in various of PLC instant

communication scenarios such as Smart Lighting、Smart Home、Smart Parking、Central Air-

Conditioning and ubiquitous equipment in IOT IPS.

3121N-H is based on Hi3921SV100 chip,it integrated high speed/low speed multimode

power line carrier communication modem and ARM Cortex-M3 processor. The Hi3921SV100

supports P1901.1,OFDM/FSK modulation, SunSpec standard.

3121N-H provides rich peripheral interfaces such as UART、PWM and ADC,and integrates

the built-in Line-Driver.Equipped with Lite-OS,the open source OS of Huawei IOT,which provides

a more open development environment and a faster and safer OS.

*This document is applicable for HW Development Engineers,HW Testing Engineers and FAE.

2 Block Diagram

3 Features
 Reach IEEE1901.1 standard subset,physical layer peak rate 0.507Mbit/s,application layer

80Kbps

 Support 0.5-3.7M and 2.5-5.7M,which can be configured by software

 Adopt OFDM technology,support BPSK and QPSK modulation mode

 Support FEC and CRC functions,with powerful denoising and error correction
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 Support TDMA and CSMA/CA,provide conflict avoidance mechanism capability

 Support data segmentation and reorganization,improve transmission efficiency,support data

retransmission mechanism

 High -performance Cortex-M3 processor,operating frequency of 200MHz,embedded

SRAM 256KB

 Support dynamic routing,fast networking with multipath addressing, in a typical application, a

CCO can support 200 STA access

 An open OS-LiteOS,provides an open、efficient、secure system development、operating

environment.Flexible protocol support and extension capabilities.

 The software supports whitelist recognition, hardware implementation of AES128/256

encryption and decryption algorithm,RSA signature check algorithm, HASH tamper-

proofing algorithm. Integration of EFUSE, support key storage, secure startup, meet

Huawei’s security requirements.

 Support level 4 Qos( Quality of Service), meet different business service quality requirements.

 Support command propagation of unicast,multicast and broadcast

 Built-in Line Driver, TX power -51dBm/Hz( the software supports configuration of TX power to

-45dBm/Hz)

 Receiving sensitivity up to -98dbm(TX power -51dBm/Hz, under laboratory conditions,

the 30% success rate was taken as the benchmark).

 Static power ≤0.15W( no forward packet when networking)

 Dynamic operating power≤0.5W。

 Operating temperature range ：-40℃～+85℃ 。

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3121N-H
4 Dimension And Pin Definition
4.1.1 Dimension

Model No 3121N-H

Introduction PLC-IOT Module

LxWxH:28.12*18.00*5.80mm（excluded pin header height, the
Dimension actual height is related to the installation of pin header ）

The module is connected to the motherboard with pin header,

which can use a 180 degree straight pin,install at the top or bottom

Installation layer. Or use 90 degree 1*8 bending pin, connect with the
motherboard side plug (in this case, L/N may need to be processed
by welding line).

Operating Temp -40°C to 85°C

Storage Temp -40°C to 125°C

4.2 PIN Definition

3121N-H PIN Definition

Number PIN Name Remark

Module 3.3V power input pin：
1 3.3Vin
3.0~3.6V，ripple＜ 3%，current≥200mA。

2 GND Ground

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3121N-H
UART0、GPIO reuse pin，pull down 10k resistor by default（The

UART0 is used by default to communicate with the upper MCU

when connect to it）：

GPIO10/JTAG_T Multiplexed Signal 0：GPIO_10 default input, universal input-output

3
MS/UART0_TX0 Multiplexed Signal 1：UART0_TXD UART0 data，transmission

Multiplexed Signal 2：HW_ID_9 hardware version， the user can

distinguish the form of hardware products through the pin, the latch

is locked when power on or reset is removed

UART0、GPIO reuse pin，module pull down 10k resistor（The

UART0 is used by default to communicate with the upper MCU

GPIO9/JTAG_T
4 when connect to it）：
CK/UART0_RX0
Multiplexed Signal 0：GPIO_9 default input, universal input-output

Multiplexed Signal 1：UART0_RXD UART0 data receiving

PWM、GPIO reuse pin(the module default is PWM mode, pull up

point resistance not mounted)

Multiplexed Signal 0：GPIO_0 default input, universal input-

GPIO0/PWM_
5 output
OUT
Multiplexed Signal 1：LED4 universal LED。 Multiplexed Signal

2：PWM_OUT PWM（Pulse Width modulation）data

transmission

PWM、GPIO reuse pin(the module default is PWM mode, pull up

point resistance not mounted)

GPIO5/PWM1_
6 Multiplexed Signal 0：GPIO_5 default input, universal input-
OUT
output

Multiplexed Signal 1：PWM1_OUT PWM（Pulse Width

modulation）data transmission
GPIO reuse pin，module pull down 10k resistor inside：

Multiplexed Signal 0：GPIO_19 default input, universal input-

7 GPIO19 output

Multiplexed Signal 1：RTS1_N UART1 the fluid control pin, send

request signal output

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3121N-H
PLC reset input, pull up inside：

Software reset control：during the normal operation，an

effective hard reset of Hi3921S can be achieved by applying a

8 RSTN
low level pulse with a width ≥5ms at the RSTN pin. And it is

required that the pin should not have any burrs (i.e. abnormal

low pulse signals).

9 3.3V The user debugged the serial port UART1

10 GND The user debugged the serial port UART1

UART1、GPIO#14 reuse pin，pull up 10k resistor by default：

Multiplexed Signal 0：UART1_TX: generally used for user

debugging serial port, software programming, networking testing,

11 UART1_TXD
etc

Multiplexed Signal 1：GPIO_14 universal input-output

Multiplexed Signal 2：I2C_SCL I2C clock

UART1、GPIO#13 reuse pin，pull up 10k resistor by default：

Multiplexed Signal 0： UART1_RX: generally used for user

debugging serial port, software programming, networking testing,

12 UART1_RXD
etc

Multiplexed Signal 1：GPIO_13 universal input-output

Multiplexed Signal 2：I2C_SDA I2C data

220V~L；communication port, need to design filter network to

/ L other AC power isolation；

General requirements of protective capability：DM/CM: +/- 4KV;

220V~N；communication port, need to design filter network to

/ N other AC power isolation；

General requirements of protective capability：DM/CM: +/- 4KV;

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 3121N-H
5 Interface Design Introduction

5.1 Input Power Requirement

Min. Typ. Max. Unit

3.3Vin 3.0 3.3 3.6 V

 The motherboard is close to the module’s 3.3V input end, at least one 10uF and 0.1UF

ground energy storage capacitor is placed to reduce the power ripple, and make the ripple

peak within 100mVpp.

 The 3.3V of module is isolated from other 3.3V of the motherboard are all using

600R/100MHz , and magnetic bead isolation 1A and above.

 The 3.3V of module circuit to ensure at least 200mA and above current demand.

5.2 GPIO Introductions

 There are total 7 GPIO multiplexing ports of the module, ee with pull-up or pull-down

resistors

 GPIO_0 and GPIO_5 default to PWM mode

 The UART0 multiplexer pin is used by default when connect to external MCU

5.3 SOR Introductions

 During the normal operation，an effective hard reset of Hi3921S can be achieved by

applying a low level pulse with a width ≥5ms at the RSTN pin

 During the normal operation, it is required that the pin should not have any burrs (i.e.

abnormal low pulse signals).

5.4 Debug UART Introductions

 There are two UART can be used of Hi3921S,under debugging, use UART1

 UART1 supports Hiassistant tool networking testing by default：CCO UART1 connect USB-

TTL to the PC

5.5 PLC Transmission Circuit

Hi3921 with built in Line Driver function, the output signal can directly drive the load, no

need external power amplifier circuit. The output differential signal, through series connect

resistance, parallel connect filter capacitor, and series connect coupling capacitor to the

secondary side of the coupling coil. The source side of coupling coil is connected to a power line

by a series connection safety capacitor. The transmitting and receiving channels share the

secondary side of the coupling coil.

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 3121N-H
 The built in Line Driver output frequency range ：70KHz～6MHz

 The drive capability of chip output：10μH

 The chip differential voltage output range：0V～5.6Vpp

 The chip provide differential output CM voltage

 The specification of safety capacitor：Y1,2.2nF,nominal voltage 400VAC,limit test voltage

4KVAC, test voltage 4KVAC

 The specification of coupling coil：63uH，DCR 0.2ohm，test voltage 1500VAC

5.6 PLC Receiving Circuit

Hi3921 input the differential signal from the external input into the AFE inside the chip

through band-pass filter.

 RX input frequency range：70KHz～12.5MHz。

 The chip RX channel input impedance：1.7kΩ/2MHz，1kΩ/7MHz。

 The differential voltage input range：0V～6.6V。

 The chip provide differential input CM voltage

5.7 AC220 Power Supply Design Suggestions

In the product, AC220V inlet end, in addition to the PLC circuit part, there are other electrical

connection circuit part. The rationality of circuit design of this part will affect the power carrier

communication. The reference design is as follow：

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3121N-H
The main points of design suggestions ：

 The effect of output ripple for PLC performance. If the output is 3.3V then the peak-peak

ripple should be within 100mVPP

 The effect of AC DC power adapter for power line. Suggested that when the AC DC power

adapter is connected to the power line, and if the distance between CCO and primary

STA(PCO) is <50m, the noise power of 500kHz ~ 6MHz on the power line is <-110dbm/H,

and the noise power of >50m is required to be <-120dbm/Hz

 Compared with the narrowband communication signal of several hundred KHz, the

wideband carrier communication frequency band is wider and higher, which requires that

there should be no large capacitor in the communication channel between N/L wires to

reduce the attenuation of the communication signal. In the figure, there is no more than

600pF capacitors are allowed in section X(If multiple devices are connected in parallel.

Should consider the summation of capacitance values of the capacitors.

 If the device needs to reduce the differential noise on L-N by X capacitor, we suggested

that place the X capacitor behind of the 100uH inductor. That can reduce noise, also it can

increase the impedance of the carrier channel and reduce the attenuation of PLC signal.

Recommended capacitance is 2.2nF(the smaller, the better). If need Y capacitor, do the

same as X( and the capacitance of Y is also as small as possible, but it is less impact on the

PLC than X).

 Noted that after the varistor, the inductance before the capacitance of X cannot be a CM

inductance, and the PLC signal is a differential mode signal. The CM inductance cannot isolate

the attenuation of capacitance of X.

 The power switching frequency of concentrator DCDC is suggested to be lower than 1MHz

to suppress out-of-band noise and limit the influence of high frequency out-of-band

within 10dB, that to reduce the risk of excessive EMI of the device, also reduce the impact

on carrier communication.

 According to the level of protection requirements of the device, it is recommended that to

use the appropriate varistor and fuse together, and the recommended capacitance of

varistor is <=100pF(the sum of L-N parallel capacitance is no more than 600pF.

 The device protects the varistor, its protective capability must cover the PLC carrier circuit.

The layout and wiring should make the external power circuit pass through the varistor at

first, and then power supply the PLC carrier circuit and others.

 When PCB layout, note that the safety space requirements of AC220 strong current

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3121N-H
maintenance and the light current end of PLC module.

 The PLC carrier circuit RX channel, especially the filter, coupling coil part are also easy to

absorb the space electromagnetic radiation interference, worsen the board ground noise,

and degrade the receptivity of PLC. Therefore, in the layout, interference the source circuit,

such as DCDC , are required that stay away from the sensitive circuit.

6 Typical Applications
6.1 AC220 L-N Two Wire Coupling

6.2 DC Two Wire Coupling

 The series capacitor between DC and T1 can play the role of isolation and protection. Can

use conventional capacitor, the test voltage requirement is 100V or above.

 The series capacitor between DC and T1 may also be omitted as the case may be.

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3121N-H
6.3 CCO& STA Typical Networking And Topology
6.3.1 CCO& STA Typical Networking

 CCO is PLC centralized controller, STA is PLC

 CCO and STA with the same hardware but different software

 In simple application, CCO can networking independently without external MCU. The cloud

of networking need the external MCU to be realized through the wired Ethernet LANs or

WLAN.

 In a typical networking environment, it is suggested that the 220V AC circuit in the front

end of CCO be added with AC220 isolator to filter the noise of other power network, so as

to avoid affecting the communication quality of local CCO networking and reduce the

interference of local CCO to other PLC communication networking.

 In a typical networking environment, 1 CCO can support 200 STA.

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3121N-H
6.3.2 CCO&STA 's Tree Topology

 PCO is the agent node, the actual home environment recommends the maximum existence

of 3-4 PCO, and the actual street lighting environment recommends the maximum

existence of 6-7 PCO.

 With the distributed routing technology, after STA is changed or reset, the networking can

be accessed quickly, the path can be evaluated quickly, the router can be refreshed in real

time, and the off-line fault of STA can be identified quickly. Even in the absence of routing,

enable broadcast technology to ensure the success rate of communication with the most

complete path.

 PCO with relay function that amplifies the attenuated signal for longer distances

transmission.

7 Networking Test Introductions

 CCO and STA with various ways in networking, the typical ways refer to section 6.1 and 6.4.1

 As the centralized controller of PLC, CCO can control, transmit and receive , and update the

software of STA.

 During the testing, CCO can be connected to the PC through the UART1 and USB-TTL

serial port(In practical application, the STA can be controlled by external MCU or other

upper computer).

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3121N-H
 3121N-H baud rate is 115200bps。

 The testing tool and instruction, please refer to the below file for details. PS: the tool and

instruction are provided separately.

HiAsistant_b01 HiA ssistant简易

0.exe 使用说明.p d f

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