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  • 1990 - K S Tam - Automatedtopologicalgenerationandanalysisofvoltage (Retrieved-2015-08-30)

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    10 views5 pages

    1990 - K S Tam - Automatedtopologicalgenerationandanalysisofvoltage (Retrieved-2015-08-30)

    Uploaded by

    Miguel D. Diaz H.

    Copyright:

    © All Rights Reserved
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    of 5
    oy bs) na, Sint” gkwood os) ne, ‘Automated Topological Generation and Analysis of Voltage Multiplier Circuits Abtact ~The paper demonstrates he fesity of sng computes to erform the geserain of aerate cin (that hae eet ope {a the exahaton ofthese aerate, andthe slctian ofthe et ‘Stton according to a genset of rr Based on ths en, an expert ‘stem VAD (vollage muliper designer) ev Beer esloed for the dlign of voltage muir cuts Some unconventional eee that Ive beter performance the the conentoal crete for xine applica ‘om ae bem generated by V3ED. This paper derbies the ander {theory an the impementatoe of VMD, nd resent some ofthe ei thar VD prvi 1. Isrropvcrion The design of an electric crit fora certain application may be viewed as a search for solution(s) within a feasible design space formed by constraints pertaining to that application. If the feasible design space is large, itis difficult for a human designee to cover all alternatives within the feasible space to determine the best solution for a given set of criteria If the feasible space is very smal, the human designer may have ifculty in finding the ew solutions available. The design process general) invaves the generation of feasible alternatives, the analysis of these altens- lives, and the seletion of the most appropiate ones) based on @ Set of criteria. Usually, due to imitation of time and resources, yn] How the fapactor tres ae labeled will affect ther Gomnection with the diode tee and consequonly different voltage multiplier crit Structures wil result, ‘Tae node labeling scheme in VMGEN performs the labeling of the capacitor tee nodes as fellows, The scheme Fist designates fone ofthe capacitors in Ty 36 the output capacitor and labels ts teeminal nodes (Lpm-+1) if mis even, and (1,-+2) sf mis 08d ‘The rest ofthe toe is then labeled in different patterns that are varied by permutation with numbers nthe range of 0 0 nif is even, and 2 10 (n+) if mis odd, The scheme then chooses ‘ferent capacitor in 7,36 the output capacitor and repeats the ‘permutation process fo labeling the resto the tee. The labeling proces stops when all he capacitors in 7 have been wsed as the ‘urput capacitor and all permutations have been exhausted. The scheme als incorporates the guidelines fr labeling the capacitor taee noes as deseribed in (5) Theo cicuits are considered tobe identical if one iret can be ‘obiained from the other by reversing the connection of every ‘iode. For two identical circuit, the node labels of the output ou capacitor terminals of one circuit are in reverse onder of those of the other ciruit To ciminate the generation of identical circuits, ‘constraint is imposed on the labeling of the output capacitor termina nodes such that only one pattern of labeling is allowed. For example, for even m, the output capacitor terminals are labeled by only (1, +1) and never by (#11. Some applications require thatthe mput ac voltage source and the output capacitor share a common terminal. The common ‘round requirement would impose a constraint on the location of the output capacitor within the tce Ty. A mechanism has heen installed in VMGEN such that ifthe common ground require ment is indicate by the user, VMGEN would reste its gnera- ton of circuits to only those that have a common ground between the input and the output terminals. Siilaly, another ‘mechanism has been installed in VMGEN such that i the wsee wants oaly cireits with isolated inpet and output terminals VMGEN would skip ity generation of circuits with common round and only produce creuits with iolated input and output terminal, With these mechanisms, only potentially useful alter natives are generated and the search proces: becomes mone efficent. If neither common ground nor isolated terminals ate Specified by the user as a circuit requirement, VMGEN would enerate all possible alteratves which would be evaluated and elected based on other eniteia B. VMSEL Using (5, th. 1 and 2) circuit designer can seaily determine the capacitor voltages and the output resistance of voltage multiplier circuit by inspecting the circuit. Theorem 1 in (3) involves the counting of diodes contained in the fundamental loop defined by a capacitor with respect to the diodes wollage-source te forthe determination of the voltage for that xpacitr. Theorem 2 in [5] involves the counting of diodes ‘contained in the fundamental cuset defined by a capacitor with respect to the expaciors-volage-source tee forthe determina- tion of output resistance ofthe sicit. The cei inspection and the consequent computation process are automated in VMSEL to handle large numberof shermatives, To facilitate the automated analysis process, a more sophist- cated representation scheme is used to represent the circuits in VMSEL. When a circuit generated by VMGEN is fed to VMSEL, VMSEL frst converts the circuit representation from the scheme used in VMGEN to the scheme used in VMSEL, oth the siruture of the entre crest as well asthe details of cach circuit component are represented. The circuit structure is represented in a database which abulates how the circuit compo- rents are connected to the nodes, The representation of cach ‘Grout component includes their terminal nodes, component pa rameters (such a voltages of capacitors) and other characteristic features (such as polarity in the ease of 2 diode). Starting withthe terminal nodes of a capacitor and acing though the database, ‘VMSEL can determine the number of diodes contained in the fundamental loop of fundamental eutset defined by the expacitor with respect to other trees (as specified by [5 th. 1 and 2) within the circuit, Using this information, VMSEL then proceeds to compute the output resistance and the vltage of each capacitor ‘sccording to theorems 1 and 2 in [3 'VMSEL analyzes and evaluates the circuits generated by \VMGEN in order to selet the best ereui(s) based onthe eiteia supplied by the usr. VMGEN generates ane alterative cut at 4 ime and sends the circuit to VMSEL. VMSEL determines the steady-state capacitor voltages and the output resistance aoe Jaan RANSACHION ON CIRCUS AND SYSTEMS, OL. 37, HO 3, MARCH 1990 TABLE _Nuwen oF Poste Varrace MU&Tinute CcUnS AS & FENCHON for Meinuctty sted with that czeuit. Ie then calculates the “cost” associated with that eircuit by a cost function defined as follows cost = GSC) + Go) o f(V,) and (Ro) are functions of V, and Ro, respectively, and ‘ue mearre ofthe magaitude ofthe capacitor voltages ad te output reastane. G and Cy ate the corresponding sort oct Gents and are supped by the wer to rect the relative ipo. tance of having minimum capacior voles and/or having Iinimom outpat resistance. How routs ae bing skced by YVMSEL depends onthe lave acs of and Cy If Ry ithe dominant factor, VMSEL vl send signal to'VMGEN to invoke te mechan such shat only cree wih minimum ‘uit restanes cies with T a8 Nat es) are senerated. "VMSEL sores the cet) With the minim cost in & designated Mle Ifthe ccot curently being. esate. by YVMSEL has higher cow than tho inthe le, tl be disposed of I he erent has these ost tote othe let wl be Added fo the ile. I the caren ect has Tower cos than thse inthe let wl eplac all rte that are presenly sored in the fle: When VMSEL finishes with the cent cei, wil Inform VMGEN to provide the nest alenative snd he evalu ti prose repeats unt all candidate ces produced by YMGEN ive been examined By the end of the evaluation process, VMSEL will have Sle of scl wih the minimum i ‘Table I shows the number of posible voltage multiplier ci cuits asa function of the multiplicity n. The number of altema- tives increases very rapily with n. This is because a5 increases, the ways to form the ways to combine Ty and. and the ways 0 tashion. 'VMD has been used to generate the structural design of voltage multiplies for various values of multiplicity (nm) and Under various ses of evaluation entra, Dut to space limitation, only the results fr 7-fold voltage multpirs are presented inthis paper, For comparison, the conventional “laddes” cireuit for ‘old voltage multiplier circuit is shown in Fig. 3. This circuit has a common ground and an output resistance of Ry = 28//C, whereas isthe frequency of the ae voltage and’ Cis the Resuers sees suansne 40 ON INCU A STEMS, VO 37, N03 ane 1980 ig. 3. Comal 0 hag mpi sit an i Fig 4. old age maitre spi by YD common sound ———i-, | | 8s

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