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Superscalar Processors
Able to execute multiple instructions at a single time. Uses multiple ALUs and execution resources. Takes a sequential program and runs adjacent i t ti dj t instructions i parallel if possible. in ll l ibl The Pentium Pro and following Intel processors are superscalar as are many other modern processors.
Superscalar Pipelining
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Superscalar Hazards
Data Dependency Instructions executed in i parallel cannot d ll l t depend upon th results d the lt of the other instruction. Add Sub R1, R2 R3 R1 Needs correct R1 R3,
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Compiler Support
An intelligent compiler can reorder the instructions so that adjacent instructions i t ti th t dj t i t ti do not create data hazards. Compilers for explicitly superscalar processors generate bundles of instructions that are executed in parallel.
RISC Processors
Modern processors take advantage of the architectural advances l hit t l d learned over th d the past decades. Most new processors (i.e. Intel Itanium or MIPS) are RISC processors.
Design Alternatives
CISC Complex Instruction Set Computer
Pentium is the most popular example
No precise definition. The Intel Pentium 4 borrows many design ideas from RISC.
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Simple Instructions
Simple instructions are preferred
Complex instructions are mostly ignored by compilers The Intel Pentium has several instructions that appear to be designed for Cobol programs. Most of the instructions used are very simple.
A i l An implementation th t supports complex t ti that t l instructions slows the execution of simple instructions.
Instruction Frequencies
Dynamic Occurrence Pascal Assign Loop Call IF other 45% 5% 15% 29% 6% C 38% 3% 12% 43% 1% Memory-Reference Weighted Pascal 14% 33% 44% 7% 2% C 15% 26% 45% 13% 1%
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Addressing Modes
Complex addressing modes lead to variable l i bl length i t ti th instructions
Leads to inefficient instruction decoding and scheduling
Register Operands
Almost all RISC instructions use register operands. d Usually only one Load and one Store instruction access RAM. Many RISC systems use three register operands ADD R1,R2,R3 Avoids data hazard of putting the result back in the source register.
Memory Hierarchy
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Function Calls
Most function calls have few arguments
Only 1.25% of the calls have more than 6 arguments
Register Stacks
Many RISC processors have a large number of registers, not all of which are b f i t t ll f hi h visible at any one time. The mapping of register X to a hardware register changes when a function is called.
R0 R7
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R0 R7
R0 R7
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Register-to-register operations
Only load and store operations access memory Rest of the operations on a register-to-register basis
Fixed-length instructions g
Facilitates efficient instruction execution
Example Differences
CISC VAX 11/780 303 22 2-57 2 57 16 Intel 486 235 11 1-12 1 12 8 RISC MIPS R4000 94 1 4 32
chart Dandamudi
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RISC Traits
Pipelined Simple instructions p Few instructions No microcode Few addressing modes Load/Store architecture Sliding register stack Delayed branches Fast
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