Save trees use e-Question Paper Go green DOWNLOAD THIS FREE AT www.viuresource.com CACS SCHEME usN 188 @ Fifth Semester B.E. Degree Examination, Feb./Mar. 202: Verilog HDL Time:3 re Max, Maas ‘Note: er any FIVE ful eto, choosing ONE ful qention ogg moe g Modules E 1 a. Explain atypical design flow for designing VLSLIC circuits using kero. plain ay en ie 1 0 Marky 3b, Explain the importance of DLs (esvtark FS Faplan me wenden HDL (0s Mark B or P22 plain the erent evel of sstation sed forp in verlog. (8 Marks 35 b. Writetheverilog code for-Hbit ripple cary counter. Stimulos, (2 Markey as Modul | 3. a. Explain the components of verilog mocile i (06 tary EP ° BL Explainthe following datatypes with ano i) Reginters ii) Arayn it Parameter i tegers a0 Marks ©. Explain the port connection rules in veslol (os Mtark 4a, Write the vesiog description of SR ag I rite ai a0 stark) Explain display, Smomtior. 8 osntem tasks with examples, Mark) S 4, Whatare iso, fll ana ow they are specified in verilog?” (OG Marks) b. What would be the i) £8 ii) Ac ©. Mention the sym Fving for A= 4°00111 an dB = 4"b1001 iv) {24B}} ¥) A°B vi) A/B vil) APB vill) A<~ BL x Marky and an example for BUFIFI and BUFIFO primitive gates. (6 Marks) oR 6 a. Design AQiigeed wltiplexer and site the verilog deseription and its stimulus (do Marks) 1b, Write thQgrito PAM flow description for 4-bit full adder with earry look ahead logic (0 Marks) Module. 7 -xplain blocking and non-blocking assignments with an example (10 Marks) to aggrilog code for clock generation with a period of 20 unit using forever Lop, (OS Marks) the differences between the tasks andl functions (08 Marks) or ‘2. Biscuss sequential and parallel blocks with examples (0 starksy 1b, Write a verilog program for 8 : 1 multiplexer using case statement, io starks) 1 of 2 BRANCHES | ALL SEMESTERS | NOTES | QUESTON PAPERS | LAB MANUALS A Vturesource Go Green initiativeSave trees use e-Question Paper Go green DOWNLOAD THIS FREE AT www.viuresource.com 181 Module-s, Write the verilog description for D — flipflop using assign and deassign(fprocedsl continuous assignments, 10 Marky Esplain defparam statement with an example, 1 oR What is logic synthesis? Explain the flow diagram for the desi synthesis tool ‘What will be the following statements translate to when run on Assign {C-out, sum } =a} b Cin; Assign out = (6)? il =i0: BRANCHES | ALL SEMESTERS | NOTES | QUESTON PAPERS | LAB MANUALS A Vturesource Go Green initiative