Practical-6

Aim:-Wap of 4-bit ALU using behavioural module.

1) Main module:-
module mona1(a, b, s, y);
input [3:0]a;
input [3:0]b;
input [4:0]s;
output [7:0]y;
reg [7:0]y;
always@(a,b,s)
begin
case(s)
0:y=a+b;
1:y=a-b;
2:y=a*b;
3:y=a/b;
4:y=a%b;
5:y=a**b;
6:y=a&&b;
7:y=a||b;
8:y=!a;
9:y=a>b;
10:y=a<b;
11:y=a>=b;
12:y=a<=b;
13:y=a==b;
14:y=a!=b;
15:y=a!==b;
16:y=a&b;
17:y=!a;
17:y=a|b;
18:y=a^b;
19:y=a^~b;
20:y=&a;
21:y=|a;
22:y=~&a;
23:y=~|a;
24:y=^a;
25:y=^~a;
26:y=a>>b;
27:y=a<<b;
28:y=a>>>b;
29:y=a<<<b;
30:y={a,b};
default:$display("invalid s");
endcase
end
endmodule

2).Test bench:-
module jyoti2_v;
 // Inputs
reg [3:0]a;
reg [3:0]b;
reg [4:0] s;
// Outputs
wire y;
// Instantiate the Unit Under Test (UUT)
mona1 uut (
.a(a),
.b(b),
.s(s),
.y(y)
);
initial begin
// Initialize Inputs
#5 a=4'b0110; b=4'b1010;
s=5'b0;
begin
#5 repeat(32)
#5 s=s+1;
end
#5 $stop;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule