Professional Documents
Culture Documents
and Solutions for
C
Consumer Flash‐Memory Devices
Fl h M D i
Tei-Wei Kuo, Po-Chun Huang, and Yuan-Hao Chang
Dept.
D t off C
Computer
t Science
S i & Info.
I f Engr.
E
y Taiwan
National Taiwan University,
IIS and CITI, Academia Sinica, Taiwan
2011/10/10 Tei‐Wei Kuo, NTU, All Rights Reserved 1
Agenda
• Introduction
• Architecture and Design Issues
Architecture and Design Issues
• Performance Issues
• Reliability/Endurance Issues
• Conclusion
2011/10/10 Tei‐Wei Kuo, NTU, All Rights Reserved 2
3
Introduction
• Diversified Application Domains
Diversified Application Domains
– Portable Storage Devices
– Consumer Electronics
– Servers and Storage Systems
Servers and Storage Systems
– Industrial Applications
2011/10/10 Tei‐Wei Kuo, NTU, All Rights Reserved 3
Trends – Market Growth
• Mobile Devices
– Smartphones: 50%+ of growth
Smartphones: 50%+ of growth
from 2010/02 to 2011/05 Total shipped
– Tablet PCs, e.g., iPad
, g, smart pphones
– Automotive navigation systems
• Flash Memoryy
– 25% growth from 2011/01 to Source: http://www.studioglyphic.com/blog/wp-content/uploads/2011/05/Smart-Phone-Market-Share.png
2011/08
Revenue: 22 billions in 2011
Total shipped
flash units
Revenue
Source: http://www.dramexchange.com/images/monthlyproduction2009.gif
Tei‐Wei Kuo, NTU, All Rights Reserved 4
Trends – Market and Technology
• Competitiveness in the Price
– Dropping Rate and the Price Gap with HDDs
• Technology Trend over the Market
Price gap
– Improved density with HDD
– Degraded performance
– Degraded reliability Source: http://agigatech.com/blog/wp-
content/uploads/2009/12/Handy-HDD-SSD-Cost-Differential.jpg,
from Understanding the NAND Market
– Worsened access constraints
Design rule Lifetime
Price per GB
Source: http://techon.nikkeibp.co.jp/NEA/solutions/0808002.pdf
Source: http://www.storagenewsletter.com/images/public/sites/
StorageNewsletter.com/articles/icono7/intel_and_micron_20nm_f3_54
0.jpg Source: http://agigatech.com/blog/page/2
2011/10/10 Tei‐Wei Kuo, NTU, All Rights Reserved 5
Trends – Solid
Trends Solid‐State
State Disks (SSDs)
Disks (SSDs)
• Flourishing in SSD Developments
– Top 20 Vendors in 2010Q4: Fusion‐io, SandForce, STEC, Violin Memory, Texas
Memory Systems, OCZ, WD Solid State Storage, Pliant Technology, SanDisk,
, y, , , g , g ,
RunCore, ForeMay, Intel, Toshiba, SMART Modular Technologies, Seagate,
Virident Systems, Kove, EMC, BiTMICRO, and DDRdrive
2011/10/10 Tei‐Wei Kuo, NTU, All Rights Reserved 6
Agenda
• Introduction
• Architecture and Design Issues
Architecture and Design Issues
• Performance Issues
• Reliability/Endurance Issues
• Conclusion
2011/10/10 Tei‐Wei Kuo, NTU, All Rights Reserved 7
The Characteristics of
Different Storage Media
Access time
Media
Read Write Erase
13.9ns
13 9ns (1B) 13.9ns
13 9ns (1B)
DRAM N/A
7.12us (512B) 7.12us (512B)
45ns (1B) 14us (1B)
NOR Flash 18ms ((128KB))
23 0 s (512B)
23.0us 7 2ms (512B)
7.2ms
115—135 ns (1B) 115—135 ns (1B)
PCM N/A
13us (512B) 13us (512B)
300us (1B)
NAND Flash 15us (1B) TYP: 1.5ms (1MB)
TYP: 350us (8KB)
(SLC) MAX: 35us (8KB) MAX:3ms (1MB)
MAX: 500us (8KB)
15.8ms 6.06ms
DISK N/A
TYP: 8.2ms (512B) TYP: 9.2ms (512B)
Reference Devices/Modules: DRAM: Micron DDR3-1333. NOR Flash: Silicon Storage Technology SST39LF020. PCM: Micron
P8P Parallel PCM, NAND Flash: Micron MT29F256G08AUAAAC5. Disk: Deskstar™ 7K3000 series.
2011/10/10 Tei‐Wei Kuo, NTU, All Rights Reserved 8
Single Level Cell (SLC) vs
Single Level Cell (SLC) vs
Multi‐Level Cell (MLC)
SLC Flash
LS
NUMBER OF CELL
64
MB
N
1 0 LOGIC STATE
VT
a) BILEVEL (1 BIT/CELL)
MLC Flash
128
MB
2011/10/10 Tei‐Wei Kuo, NTU, All Rights Reserved 9
Single‐Level Cell (SLC)
Each Word-Line is connected to control gates.
Each Bit-Line is connected to the drain.
Control
Co o Ga
Gate
e
Drain
Source
Cell
2011/10/10 Tei‐Wei Kuo, NTU, All Rights Reserved 10
System Architectures
y
AP AP AP AP
Fil S
File-System
Native
File
Block Device Emulation System
MTD Drivers
Management Issues –
Flash‐Memory Characteristics
1 Page = 512B
Write one page 1 Block = 32 p
pages(16KB)
g ( )
Block 0
Block 1
Block 2
Block 3
Erase one block
…
A B C D
Management Issues –
g
Flash‐Memory Characteristics
• Example 1: Out‐place Update
A B C D A B
Dead pages
L D D L D D L D This block is to be
recycled.
L L D L L L F D (3 live pages and 5
dead pages)
L F L L L L D F
A live
e page
F L L F L L F D
A dead page
A free p
page
g
Management Issues –
g
Flash‐Memory Characteristics
• Example 2: Garbage Collection
L F L L L L D L
A live
e page
L L L F L L F D
A dead page
A free p
page
g
L L D L L L L D Overheads:
•live data copying
L F L L L L D L •block erasing.
A live
e page
L L L F L L F D
A dead page
A free p
page
g
Management Issues –
g
Flash‐Memory Characteristics
• Example 3: Wear‐Leveling
Wear-leveling might
100 L D D L D D L D A
interfere with the
10 decisions of the block
block-
L L D L L L F D B
recycling policy.
20 L F L L L L D F C A live page
15
A dead ppage
g
F L L F L L F D D
A free page
Erase cycle counts
2011/10/10 Tei-Wei Kuo, NTU, All Rights Reserved 18
Management Issues –
Flash‐Memory Characteristics
• SLC Flash Access Constraints
– Write‐Once
• No writing on the same page unless its residing block is erased!
N ii h l i idi bl k i d!
• Pages are classified as valid, invalid, and free pages.
– Bulk‐Erasing
Bulk Erasing
• Pages are erased in a block unit to recycle used but invalid pages.
– Wear‐Leveling
• Each block has a limited lifetime in erasing counts.
• Additional MLC Flash Access Constraints
Additi l MLC Fl h A C t i t
– Prohibition of partial page programming
– Serial page programming in a block
Serial page programming in a block
2011/10/10 Tei-Wei Kuo, NTU, All Rights Reserved 19
Agenda
• Introduction
• Architecture and Design Issues
Architecture and Design Issues
• Performance Issues
• Reliability/Endurance Issues
• Conclusion
SD,
Memory Stick,
Compact Flash
xD,
S
SmartMedia
tM di
*FTL:
FTL: Flash Translation Layer, MTD: Memory Technology Device
2011/10/10 Tei‐Wei Kuo, NTU, All Rights Reserved 23
Example Address‐Mapping Policies – FTL
• FTL adopts a page‐level address translation mechanism.
– The main problem of FTL is on large memory space
p g y p
requirements for storing the address translation information.
2011/10/10 Tei‐Wei Kuo, NTU, All Rights Reserved 24
Example Address‐Mapping Policies – NFTL
• A logical address under NFTL is divided into a
virtual block address and a block offset.
– e.g., LBA=1011 => virtual block address (VBA) =
1011 / 8 = 126
/ and block offset = 1011 % 8 = 3
NFTL A Primary Block A Replacement Block
Address‐Mapping Policies –
Fine‐Grained VS. Coarse Grained Ones
FTL NFTL
Memory Space Requirements Larger Smaller
Address Translation Time Shorter Longer
Garbage Collection Overhead Less More
Space Utilization Higher Lower
• The Memory Space Requirements for a 16GB NAND
flash (4KB/Page, 4B/Table Entry, 128 Pages/Block)
– FTL: 16MB (= 4*16G/4K)
– NFTL: 128KB (= 4*16G/(4K*128))
Remark: Each page of small-block(/large-block) SLC NAND can store 512B(/2KB) data, and there are 32(/64) pages per block.
Each page of MLCx2 NAND can store 4KB, and there are 128—256 pages per block.
2011/10/10 Tei‐Wei Kuo, NTU, All Rights Reserved 26
Key Issues and Technologies
y g
• Address Translation
– Reduce the size of address translation information
– Adjust address translation scheme with
Adjust address translation scheme with
heterogeneous mapping granularities
– Store address translation information over flash
Store address translation information over flash
• Garbage Collection and Wear Leveling
– Cost versus Benefits
– Needs in Performance/Real‐time Constraints
/
• Parallelism in Access
– Adaptive Striping and Architecture Designs
d d h
2011/10/10 Tei‐Wei Kuo, NTU, All Rights Reserved 27
Address Translation –
Indexing and Small Writes
• Packing and Caching
P ki d C hi
I1 I2 I3 I4 I5 I6
Coarse-to-Fine Switching
g
PPBA RPBA
Chin-Hsien Wu and Tei-Wei Kuo, 2006, “An Adaptive Two-Level Management for the Flash Translation Layer in Embedded Systems,”
IEEE/ACM 2006 International Conference on Computer-Aided Design (ICCAD), November 5-9, 2006.
3/29/2007 Embedded Systems and Wireless Networking Lab. 29
Address Translation –
Region Based Mapping
Region‐Based Mapping
• A three‐level address translation architecture
LBA VRA VBA VPA
2
2.
1. 3.
Yuan-Hao Chang and Tei-Wei Kuo, "A Commitment-based Management Strategy for the Performance and Reliability Enhancement of
Flash-memory Storage Systems," the ACM/IEEE Design Automation Conference (DAC), San Francisco, Jul. 26-31, 2009.
2011/10/10 Tei‐Wei Kuo, NTU, All Rights Reserved 30
Address Translation –
dd ess a s a o
Commitment‐based Management
• An adaptive block mapping mechanism with a
log‐based
log based strategy
strategy
...
...
...
...
Log-based
....
....
....
....
strategy
t t
...
...
...
...
Commit
Yuan-Hao Chang and Tei-Wei Kuo, "A Commitment-based Management Strategy for the Performance and Reliability Enhancement of
Flash-memory Storage Systems," the ACM/IEEE Design Automation Conference (DAC), San Francisco, Jul. 26-31, 2009.
2011/10/10 Tei‐Wei Kuo, NTU, All Rights Reserved 31
Address Translation –
Adaptivity to Access Patterns
• Good
G d performance
f to
t random
d writes
it and
d sequential
ti l writes
it
– A virtual block up to 2 physical block sets
- Replace
p the block set with fewer valid data.
- Set the remaining one as the old one.
Discarded
(erased)
A free
bl k sett
block
Random
writes
Yuan-Hao Chang and Tei-Wei Kuo, "A Commitment-based Management Strategy for the Performance and Reliability Enhancement of
Flash-memory Storage Systems," the ACM/IEEE Design Automation Conference (DAC), San Francisco, Jul. 26-31, 2009.
Garbage Collection –
Real‐Time Garbage Collection
• Garbage Collection and MLC Write Constraints
Di
Discard
d extra
t tokens
t k
30
T1
Parallel access supports –
Adaptive striping
• Stripping
Stripping and Utilization:
and Utilization:
Distribute hot and cold data evenly over banks
0 15 16 0 5 6 7 8 9 10
Hot data
0 16 7 8
15
6 9 10 Cold data
0
5
Erase Count
100 200 250 300
Source: Li-Pin Chang and Tei-Wei Kuo, "An Adaptive Stripping Architecture for Flash Memory Storage Systems
of Embedded Systems," IEEE Eighth Real-Time and Embedded Technology and Applications Symposium (RTAS),
2011/10/10 Tei‐Wei Kuo, NTU, All Rights Reserved 34
San Jose, USA, Sept 2002
Agenda
• Introduction
• Architecture and Design Issues
Architecture and Design Issues
• Performance Issues
• Reliability/Endurance Issues
• Conclusion
2011/10/10 Tei‐Wei Kuo, NTU, All Rights Reserved 35
Reliability Challenges
Reliability Challenges
• Low Endurance • High Bit Error Rate
• Bad Data Retention • Serious Disturbing
Single‐Level‐Cell
Single Level Cell (SLC)
(SLC) Multi‐Level‐Cell
Multi (MLC)1
Level Cell (MLC)
Distribbution of cells
Reference points
Distribution of cells
Reference point
BILEVEL (1 bit/cell) VT
MPEG-2 (1280x720) 20 20
MPEG-4
MPEG 4 6-7 6-7
* 2010Q2: SLC 6.01USD/GB, MLCx2 1.70USD/GB, TLC 1.49USD/GB
[1][2] Micron MT29F256G08AUCAB & MT29F512G08CUAA; [3] Spectek FNNB63A (downgraded flash product); [4][5] DRAMExchange, October 2011
2011/10/10 Tei‐Wei Kuo, NTU, All Rights Reserved 36
Wear‐Leveling
Wear Leveling Technologies
Technologies
5000
4000
Erase
3000
2000
1000
0
0 20 40 60 80 100 0 20 40 60 80 100 0 20 40 60 80 100
2011/10/10 Tei‐Wei Kuo, NTU, All Rights Reserved 37
37
f1(z)
(y) 2 The corresponding LBA y is hashed
2.
simultaneously by K given hash
0 0 1 1
Logical Block functions.
Add
Address f2(z)
(y) 3 Ch
3. Checkk if th
the H mostt significant
i ifi t bits
bit
y 1 0 0 0
of every counter of the K hashed
values contain a non-zero bit value.
f3(z)
(y)
A Multi-Hash-Function
z 1 0 1 0
f4((y)
(z)) 1 1 1 1 Framework
Jen-Wei Hsieh, Tei-Wei Kuo, Li-Pin Chang,
1 1 0 1 “Efficient Identification of Hot Data for Flash Memory
Storage Systems,” the ACM Transactions on Storage,
Volume 2, Issue 1, pp.22-40, Feb 2006.
H most significant Bits
2011/10/10 Tei‐Wei Kuo, NTU, All Rights Reserved 39
Static Wear Levelingg
• A modular design for compatibility considerations
– An unevenness level (ecnt / fcnt) >= T Triggering of
the Static Wear Leveler
ecnt=0
=1998
=1999
=2000
=2004
=2998
=2999
=3000
=3004
=3999
=4000
fcnt =0
=2
=3
=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1 11
0 0 0 0
1 k=2
Sl spread
p on Sp
Logical blocks
Physical blocks
2011/10/10 Tei‐Wei Kuo, NTU, All Rights Reserved 41
Reliability Enhancement –
A Reliable MTD Design
Log‐based write
g
strategy with ECC
– Segment‐ enhancement
based
based
mirroring with
bad block
bad block
replacement
– Log‐based
Log‐based
write strategy
with ECC
with ECC IIntercept,
t t monitor,
it Bad
B d bl
block
k
enhancement and recreate management
operations
& flash layout
Yuan-Hao Chang and Tei-Wei Kuo 2010, “A Reliable MTD Design for MLC Flash-Memory Storage Systems," ACM
International Conference on Embedded Software (EMSOFT), Scottsdale, Arizona, USA, Oct. 24-29, 2010
2011/10/10
Tei‐Wei Kuo, NTU, All Rights Reserved 42
Reliability Enhancement –
Forward Copying in a Native File System
Forward Copying in a Native File System
• Duplicate data of the latest version of chunks which
affected by the invalidation.
ff d b h i lid i
Which chunks need to be Chunk ID
forward‐copied ? Time 1 2 3
t0 pa a pb b pc c S0
• Consider the co‐existent relation
Consider the co existent relation
– Chunks whose the latest out‐of‐
t1 pa a pd d pc c S1
date version only co‐exist
date version only co exist with the
with the t2 pa a pd d pe e S2
invalidated page.
– Chunks which are latest updated
t3 pf f pd d pe e S3
between the time points that the t4 pf f p’
pdd d pg g S4
invalidated page and the latest out‐
of‐date version.
Pei-Han Hsu, Yuan-Hao Chang, Po-Chun Huang, Tei-Wei Kuo, David Du, “A Version-based Strategy for
2011/10/10
Reliability Enhancement of Flash File Systems”, ACM/IEEE DAC 2011. Tei‐Wei Kuo, NTU, All Rights Reserved 43
Conclusion
• What Is Happening?
– Solid‐State Storage Devices
– New Designs in the Memory Hierarchy
New Designs in the Memory Hierarchy
– Flash‐Powered Storage Servers
– More Applications in Components and Products
M A li ti i C t dP d t
• Challenging Issues: Performance, Cost, and
Reliability
– Scalability Technology
Scalability Technology
– Reliability Technology
– Customization Technology
C i i T h l
2011/10/10 Tei‐Wei Kuo, NTU, All Rights Reserved 44
Contact Information
• Professor Tei‐Wei Kuo
ktw@csie.ntu.edu.tw
URL: http://csie.ntu.edu.tw/
URL: http://csie ntu edu tw/~ktw
ktw
Flash Research:
http://newslab csie ntu edu tw/~flash/
http://newslab.csie.ntu.edu.tw/ flash/
Office: +886‐2‐23625336‐257
Fax: +886‐2‐23628167
Fax: +886 2 23628167
Address:
Dept. of Computer Science & Information Engr.
f f
National Taiwan University, Taipei, Taiwan 106
2011/10/10 Tei‐Wei Kuo, NTU, All Rights Reserved 45
Questions or Comments?
2011/10/10 Tei‐Wei Kuo, NTU, All Rights Reserved 46