Zhao 2018

This article has been accepted for publication in a future issue of this journal, but has not been
fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCPMT.2019.2899898, IEEE
Transactions on Components, Packaging and Manufacturing Technology
Integration of CMOS image sensor and microwell array using

3D WLCSP technology for bio-detector application
Shuai Zhao1, Daquan Yu2,*, Yichao Zou2, Chaodong Yang2, Xiaobing Yang2, Zhiyi Xiao2, Pei Chen1
and Fei Qin1,*
1 Institute of Electronics Packaging Technology and Reliability,
College of Mechanical Engineering and Applied Electronics Technology,
Beijing University of Technology, Beijing, 100124, China
*Email: qfei@bjut.edu.cn
2 Huatian Technology (Kunshan) Electronics Co., Ltd., Kunshan 215300, China
*Email: daquan.yu_ks@ht-tech.com
Abstract
Integration of microfluidics with Integrated Circuit (IC) chip is a promising method to achieve Lab
on a Chip (LoC) for its high level miniaturization and portability in application. In this paper, a novel
approach for integration of Complementary Metal-Oxide-Semiconductor (CMOS) Image Sensor (CIS)
and microwell array using Three-Dimensional Wafer Level Chip Scale Package (3D WLCSP) technology
for bio-detector is presented. Key process including silicon microwell array fabricating, wafer leveling
bonding, backside grinding, Through Silicon Via (TSV) etching, Redistribution Layer (RDL) and Ball
Grid Array (BGA) formation are developed. A high density serpentine electrical circuit is integrated on
the backside of the package to work as a temperature controller. After the fabrication process optimization,
a yield rate of 94.6% is obtained. Reliability of the packages are characterized by Thermal Cycling (TC)
and Highly Accelerated Stress Test temperature storage (HAST) tests, and the results show good package
level reliability. The proposed 3D WLCSP provides a low cost and reliable solution for the fluidic bio-
detector integration.
Key words: LoC; microfluidics; 3D WLCSP; microwell; CIS; TSV; bio-detector
2156-3950 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCPMT.2019.2899898, IEEE
1. Introduction
Compared with conventional diagnostic systems, LoC systems provide higher experimental
throughput, lower reagent consumption and faster analysis time, enabling integration and portability for
biochemical assays [1]. In recent years varieties of fluidic LoCs for chemical synthesis and biological
analysis such as DNA extraction, pathogenic microorganism detection and clinical diagnosis have been
presented [2], [3], while research on manufacturing of cost-effective, robust and industrialization-capable
LoCs was still in its infancy.
Common LoC system typically includes a microfluidic with microchannels or microwells for
biochemical reagent delivery and reaction, and external benchtop devices like fluorescence readers for
the bio-reaction signals capturing and readout, some even require extra thermal heater systems, all of
which lead to high manufacturing costs and incommodity to Point-of-Care (PoC). [4]-[6]. As an
alternative, there is an interest to integrate microfluidics with silicon-based CMOS integrated circuits
such as CIS or CMOS biosensors [7]. With the microfluidic-IC combination, the bio-reaction signals in
color could be converted to the impedance/capacitive changes in electrical signal. The small electrical
signal changes can be detected within milliseconds by CMOS, which enabling high efficient real-time
analysis. Besides, high level miniaturization and standard fabrication processes of the microelectronics
make the manufacturing LoCs portable and costly [8]. Moreover, the application of CMOS chip
miniaturizes the complex detection system into a single chip instead of multi-step experiments and
analyses in laboratory, such that it could be used by non-experts in the field or at home [9]. Hence
integrating the CMOS chips with microfluidics successfully would promote the testing and eventual
commercialization of the LoC technologies.
Though the concept of sensor-fluidics integration has been presented long before, several challenges
still exist limiting the complete LoC systems behind common application. In advance, suitable type of
material should be chosen for the design and development of the microfluidics for the LoCs.
Polydimethylsiloxane (PDMS) has been widely applied in microdevices benefiting from its superior
optical performance and convenience of rapid prototyping, however, some potential spurious effects such
as uncertainty and experimental bias due to the interaction between PDMS and cells in molecules in the
application of PDMS-based bio-detectors have been reported [10]. Besides, PDMS is a soft polymer and
has a relatively low stiffness coefficient, such that it’s hard for the PDMS-based bio-detectors fabrication
using existing standard microelectronics process [11]. Silicon is a common material in microelectronic
manufacture and is easy to pattern using dry etching, while some technology problems still exist in
manufacturing process such as bonding and electrical interconnection [12]. Another challenge is the
footprint mismatch of between microfluidic devices and the CMOS chips. The microfluidics usually have
dimensions of centimeters while CMOS dies have dimensions of millimeters. The mismatch increased
the process difficulties and risk of reliability failure. In addition, sealing the microfluidics with CMOS
sensors with isolating the fluids from electrical interconnects in feasible and simple methods is also a
challenge for the costly integration of the LoCs [13], [14]. Development of a low cost, reliable and mass
product-enabled methodology to solve all these issues concurrently is critical for the application of
advancing LoC technology. Early research of the integration of CMOS chips with microfluidics were
concentrated on direct combination by embedding fluidic systems within an integrated circuit, then
packaging the chip through Pin Grid Array (PGA) or Multichip Module (MCM) package [15], [16]. More
recent approach involved simplifying the sensor/fluidic hybrid microsystem using polymers like PDMS
and wire bonded CMOS chips was put forward [17]-[19]. Welch et al presented a hybrid system using
PDMS/glass microfluidics and flip chip bonding for electrical connection [20]. Lately, with the
development of fan-out wafer level packaging (FOWLP) [21], Brettschneider et al proposed a new
method using FOWLP for the CMOS biosensors then integrated with the microfluidic by laser bonding
[22]. Coincidently, Lindsay et al pursued a heterogeneous integration of CMOS biosensors and
microfluidic using FOWLP with wafer level molding [23]. Comparison of the integrated methods
mentioned above were summarized in Table 1 (A~D). All of the integrated methods have overcome the
challenges related in some extent, however, most of them were fulfilled in a way of “IC chip to fluidics
chip” or “IC chip to reconstructed wafer”, thus introduced some new problems and increased the cost.
In this paper, integration of CIS and silicon microwell array using 3D WLCSP technology for fluidic
bio-detector application was presented. We present a new method of fabricating the microfluidics by
silicon microwell array on silicon wafer, and develop a “sensors to microfluidics” wafer level adhesive
bonding process to bond the CIS wafers and the microwell array together. Via last TSV technology was
introduced to lead the electrical interconnects to the backside of the CMOS sensors, in which the fluidic
was separated with the electrical circuits. Besides, a high density serpentine circuit as a temperature
controller was fabricated to create thermal cycle by an alternating-electric-current induced joule heating,
hence no extra thermal heater was required for the detecting systems. The whole process is accomplished
employing standard wafer scale fabrication process, which is greater productive and less costs. Moreover,
the presented integrated method for the bio-detector was proved to have advantages for mass industrial
production compare to the former methods, as shown in Table 1 (E). The detail fabrication process,
characteristic test and reliability analysis is illustrated in the following.
2. Design concept of the CIS/Silicon microwell array integration
Figure 1(a) shows the design schematic of the CIS/Silicon microwell array integration for the fluidic
bio-detector. The topside of the CIS is bonded with the microwells using wafer level bonding process
and the pads are connected to the BGA on the backside through via last TSVs and RDL. The multi-wells
are achieved by Bosch Deep Reactive Ion Etching (DRIE) on a silicon wafer. Silicon shows good
property for etching and holds a low Coefficient of Thermal Expansion (CTE) and high rigidity. Thus it
could also work as the mechanical support for the thin CIS wafer during the whole process. The most
distinct characteristic of this method is the CIS and microwells are bonded together before the TSV
process. A high density serpentine circuit works as the temperature controller to create thermal cycle by
an alternating-electric-current induced joule heating. Figure 1(b) shows the schematic view of the silicon
microwell array. The main package dimensions are listed in Table 2. Compare to the existing solutions,
the novel integration of silicon microwell array and CIS using 3D WLCSP technology provides following
features: (i) The CIS and microwells are bonded together before the packaging process and diced into
singulation after solder ball forming, the footprint of the CIS and the fluidic microwells are matched well.
(ii) The electrical interconnects are achieved using via last TSV technology, which separate the RDLs
and microfluidic to opposite sides of the CIS. (iii) All the process steps involved are standard wafer scale
fabrication process, which offers high efficiency production and lower cost. (iv) The pattern and volume
of the microwell arrays could be changed easily by changing the pattern of the photomask, such that this
present process is available for integration of other fluidic bio-detectors with different microwell sizes
and patterns.
3. Fabrication and result
3.1 Silicon microwell array fabrication
The microwells work as the bio-reaction chambers for the bio-detector. Using silicon-based
microarray was a simple and stable method for the integration system. Figure 2 shows the fabrication
process of the silicon microwell array. An 8-inch silicon wafer was thinned (DISCO 8540) from 730 µm
to 620 µm firstly. The silicon wells and alignment holes were then formed by photolithography (SUSS
MA8) and Bosch DRIE (SPTS MUS-21). Figure 3 shows the microwell array with different dimensions
of well diameter and pitch on the silicon wafer using DRIE. Good morphology of the multi-well array
and the sidewall scallop was obtained by optimizing the gas flow, cycle time, pressure and platen power.
3.2 CIS/silicon microwell array wafer level adhesive bonding
Alignment accuracy and bonding interface quality were two key aspects for wafer to wafer stacking.
In this package we choose optical microscopy using through wafer holes in combination as the alignment
method, as shown in Figure 4. It’s critical to design the opening size of the through-holes for this
alignment method to get an accuracy alignment and clear cross mark images for the following exposure
process. Ten pieces of dummy wafer with cross-marks which fabricated by sputtering Al and wet etching
were used to validate the bonding accuracy. On kind of adhesive material is selected as the binder for its
less auto-fluorescence and bio-compatible characteristics. The bonding process was conducted as
following. Firstly, the adhesive was spin coated (KS-S200-2C) on the surface of the CIS wafer. Secondly,
the CIS wafer and the silicon substrate were aligned on the bond aligner (Suss BA8) by an optical
microscopy, before which a plasma gas mixture of O2/Ar was used with process time of 5min on the
surface of the silicon substrate. Then the wafers were bonded in the wafer bonder (Suss SB8E). After
bonding, the wafers were baked at 150°C for 4 hours in an oven. Figure 5 shows the alignment mark
captured by a microscope (500×). All of the ten group offset values after bonding were all controlled in
±15 µm, which was a stable and accuracy value for such large size dies.
3.3 Process development of the TSV-based 3D WLCSP
TSV is the key technology for 3D integration which allows shorter electrical path and lower parasitic,
more importantly, it separates the fluidics and RDLs so as to solve many problems introduced by the
mixture of electrical interconnects and microfluidic. The process flow of proposed 3D TSV-based
WLCSP is illustrated in Figure 6. In step (a), the backside of the wafer was thinned to 120 µm using
coarse grinding and fine grinding (DISCO 8540) after bonding. Dry etching (SPTS MUS-21) was
followed to further reduce the wafer to the target thickness of 100 µm. In step (b), trenches were formed
by photolithography and isotropic etching process. In step (c), tapered TSVs were formed at first, then
oxide etching was performed directly using the NMC-GDE200 etch system after photoresist removed.
For the present device, the thickness of the oxide layer on Al pad is ~1 µm. In step (d), the first passivation
layer was deposited by spray coating (KS-S200-1SP) using JSR5100. In step (e), Cu filling and RDL
forming was finished by multi-step depositing process. Ti barrier layer and Cu seed layer were sputtered
on the passivation layer through physical vapor deposition (Oerlikon LSEVO Ⅱ). A Cu layer with about
3.5 µm thickness was then deposited on the whole wafer surface by electroplating (CZ-3001), thus the
trenches and TSVs was partially filled with Cu layer. Partially filling of the TSVs is a relatively simple
and low cost process compared to bottom-up electroplating. After Cu electroplating, RDL were formed
by wet etching Cu/Ti(CZ-2002). Subsequently electroless plating of Ni/Au (CZ-2000-3) was performed
on the Cu layer. In step (f), ASF60 photoresist was used as the final passivation. The openings for BGA
were patterned after photoresist exposure and development. In step (g), solder paste was printed on the
openings through stencil and followed by reflow process. In step (h), the wafer was separated into single
package by blade dicing (DISCO AD20T).
3.4 Package result of the fluidic bio-detector
Figure 7 shows the cross section of a single TSV captured by Scanning Electron Microscopy (SEM)
after step (f). The thickness of the 1st passivation on the die surface was 14±1 µm and the minimum
thickness at the corner was over 2 µm. Such continuous dielectric layer can insure the electrical
interconnection between the metal and silicon in TSV and avoid the failure of the TSV side wall
insulation [24]. For the copper layer, no miss-plating was found at the bottom and sidewall of the TSV.
It can be seen that the Cu layer has good uniformity and is well connected with the Al pad. Morphology
of RDLs on the backside of the package after step (e) was shown in Figure 8. The high-density serpentine
circuit was measured with L/S of 81±3/40±3µm, the thickness of the Cu layer was measured in range of
3.2-3.8 µm. Figure 9 shows the final package of the fluidic bio-detector.
4. Discussion
4.1 Optimization of the quality of the bonding interface
For the CIS/silicon microwell array wafer level adhesive bonding, controlling of the void and
adhesive overflow were critical to get a good bonding quality. The void would lead to a bad bonding
strength and the overflow of adhesive would increase the auto-fluorescence. Ten group tests were applied
to study the relationship between the bonding parameters with the void and overflow. The overflow of
adhesive and void at the bonding interface were measured by SEM. Table 3 shows the bonding
parameters of the ten group tests and the void percentage result after bonding. It was seen that increasing
pre-curing temperature, pre-curing time and bonding pressure appropriately would decrease the
percentage of the void. The void percentage didn’t change obviously when the thickness of the film
varied in the range of 5-15 µm, while the void amount increased gradually when the film thickness
decreased below 4 µm. The reason for that probably because the present pressure and pre-curing
parameters was appropriately to sustain a low percentage of void amount when the adhesive film
thickness was 5-15 µm while the thickness of the adhesive was too thin to tolerate the micro particles
and the Total Thickness Variation (TTV) of the wafers when it was below 4 µm. Based on this pre-curing
parameters and bonding pressure, we investigated the amount of the adhesive overflow with different
adhesive thickness and the result was shown in Figure 10. It seems decreasing the adhesive thickness
was beneficial to control the overflow, while it would increase the void amount if the adhesive film
thickness decreased below 4 µm. Therefore, the eighth group tests were chosen as the ultimate bonding
procedure, of which the bonding overflow was about 50-53 µm at the corner of the bonding interface.
The void percentage at the bonding interface is lower than 2%.
4.2 Electrical characteristic measurement and failure analysis
The electrical characteristics of the package were tested before dicing process on a circuit prober
(YTEC-S50). Connections made via last TSVs were tested for their conductivity and insulation from
other connections. The RDL heaters were tested for their resistance and insulation from the ground (GND)
pads. Five pieces of the bonded wafer (2500 packages in total) were tested for the electrical
characteristics including short, leakage and open failure before dicing. An average of 8.7% short failure
was found. Among them over 85% was the pad GND-pad RDL heater short. To determine the reason of
short failure, the short location was detected by a thermal detector. Figure 11(a) shows the SEM image
at the hot spot of a single package, Figure 11(b) shows the SEM image of the normal chip. It was
determined that the void in the 1st passivation layer lead to the short failure due to the Ti deposited in the
void during PVD process. By optimizing the curing parameters and spraying procedure on the die surface
of the 1st passivation, the average percentage of short was reduced to 2.4%. Finally, a high yield of 94.6%
was achieved. The average resistance of the RDL heater was 23.5 Ω, such value could sustain the
temperature required for the bio-reaction by applying an alternating electric current.
4.3 Reliability assessment
Standard reliability tests were conducted to qualify the 3D bio-detector packages. Prior to the
reliability tests, pre-conditioning was performed to simulate the effects of board assembly. Above all, the
samples were baked at 125°C for 24 hours, then soaked at 85°C under 60% relative humidity (RH) for
168 hours. At last, the samples were reflowed by a profile with 260°C peak temperature for 3 times.
Thermal cycling test (-55~125°C, 500 cycles) and highly accelerated stress test temperature storage
(HAST) test at 110°C for 264 hours were conducted for reliability evaluation. 45 samples were used for
each reliability test. The reliability results were summarized in Table 4. All the samples passed the test
conditions successfully. There was no significant change in the measurements of electrical characteristics
after TC and HAST tests. After reliability test and the following electrical tests, the selected samples
were characterized and cross-sectioned by SEM as shown in Figure 12. No delamination was found in
the polymer-filled trenches and TSVs both after TC 500 cycles and HAST 264 hours. The RDL across
the trench and via was as normal as before the reliability test, and there was no crack at the interface of
the bottom of the via and the Al pad. The fluidic device and the CIS bonded together well, no
delamination was found at the bonding interface after the test. These findings indicate that the packages
are reliable enough to bear the stress during harsh conditions. All the results demonstrate this 3D WLCSP
for the fluidic bio-detectors has good package level reliability performance.
5. Conclusions
In this work, integration design of CIS and silicon microwell array using 3D WLCSP for fluidic bio-
detector is presented. A wafer level adhesive bonding process was performed to bond CIS wafer and
silicon microwell array substrate together before the electrical interconnection process. Bonding offset
values within 15 µm and void percentage lower than 2% was obtained. The average overflow of the
adhesive was controlled within 53 µm by optimizing the bonding parameters appropriately. Good
electrical interconnection was achieved using low aspect ratio tapered TSVs by Via-last technology.
Electrical short failure of 8.4% was found due to the void in the first passivation process. After optimizing
the spraying parameters, the short percentage decreased to 2.4%. Finally, a high yield of 94.6% was
achieved based on electrical test. The entire system integrated the CMOS sensors, microfluidics and a
temperature controller with an average resistance of 23.5 Ω into a single package. For reliability tests,
no electrical failure is observed after TC 500 cycles and HAST 264 hours. All of the results indicate that
the proposed CIS/silicon microwell array integration of the bio-detector using 3D WLCSP technology is
costly and reliable for mass industrial production. Hence, we conclude that our approach can contribute
significantly to the development and application of the LoC systems.
Acknowledgment
The authors gratefully acknowledge the financial support from National Science and Technology
Major Project No. 2014ZX02502 and National High-tech R&D Program No. 2015 AA043601.
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Table 1. Comparison of existing typical and the proposed integrated methods for the sensor/fluidic
systems
Methods Advantages Disadvantages
A. Embedded fluidic • Process with standard • Extensive fabrication and
systems within an IC CMOS fabrication packaging process
using PGA or MCM process & mature • Large packaging size
packaging [15], [16] packaging process
• Relatively higher cost
B. Sensor/fluidic hybrid • Mature packaging • Large size and low I/O counts
systems using polymer- process • Limited available area for the
based microchannels & path of microchannels
wire bonded CMOS
chips [17]-[19] • Interference of the electrical
interconnection with fluidic
• Footprints mismatch
C. Sensor/fluidic hybrid • Smaller size & higher • Excess bonding & sealing
systems using I/O counts than wire process
PDMS/glass-based bonding systems • Interference of the electrical
microchannels & flip • Shorter electrical path interconnection with fluidic
chip bonding [20] & lower parasitic • Relatively higher cost
D. Sensor/fluidics hybrid • Higher I/O counts • Warpage and die shift in
systems using polymer- • Multi-chips/fluidics FOWLP
based microchannels & systems integration • Biocompatibility of the
CMOS sensor with available introduced polymer materials
FOWLP technology was uncertain
[22], [23]
• Interference of the electrical
interconnection with fluidic
E. Current research: • Footprints match well • The overflow at the bonding
Integration of CIS & • Small size &Higher interface in the microwell
silicon microwell array I/O counts limits the miniaturization of
using 3D WLCSP the microwell size.
• Shorter electrical path
technology & lower parasitic
• Separation of
microfluidics and
electrical interconnect
• Costly and mass
production available
• High package level
reliability
Table 2. The main parameters of a single package for the fluidic bio-detector
Parameters Dimensions
Package size 7236×7236×850 µm
Substrate thickness 620 µm
Silicon well dimension 600×600 µm
Silicon well pitch 800 µm
Trench depth/width 70/425µm
Incline angle of the trench 68°
Via depth/diameter 30/70 µm
Taper angle of the via 75°
Pad size 80×80 µm
RDL heater width/space 81/40 µm
Ball diameter 200 µm
Ball height 100 µm
Table 3. Ten group bonding tests using silicon well array substrate and silicon dummy wafer with
different bonding parameters
No. Layer thickness Pre-curing Pre-curing Bonding Void percentage
(µm) temperature (°C) time (s) pressure (bar) (%)
1 15 90 360 1.5 >10
2 15 100 600 1.5 8
3 15 100 600 2 6
4 15 100 600 2.5 <2
5 10 100 600 2.5 <2
6 8 100 600 2.5 <2
7 6 100 600 2.5 <2
8 5 100 600 2.5 <2
9 4 100 600 2.5 5
10 2 100 600 2.5 >10
Table 4. Reliability test results

Test items Times Test samples Fail quantity Failure rate (%)
Bake (125°C) 24 h 90 0 0.00
Soak (85°C/60% RH) 168 h 90 0 0.00
Reflow (260°C) 3× 90 0 0.00
TC (-40 to 125°C) 250 cycles 45 0 0.00
500 cycles 45 0 0.00
Unbiased HAST (110°C/85% RH) 96 h 45 0 0.00
168 h 45 0 0.00
264 h 45 0 0.00
a b
Figure 1. (a) Cross-sectional structure of the 3D WLCSP package for fluidic bio-detector (b) schematic
view of the silicon microwell array on a single package
Figure 2. The schematic flow of the silicon microwell array fabrication using Bosch DRIE
(a) (b) (c) (f)
(d) (e) (g)
Figure 3. The silicon microwell array after Bosch DRIE (a) the 8-inch microwell array substrate
captured by a camera (b a single well with dimension of 600×600 µm (c) space with dimension of 200
µm between adjacent wells (d) cross sectional image of the silicon well array (e) sidewall morphology
of the silicon well (f) silicon microwell array with diameter/space of 100/30 µm (g) silicon microwell
array with diameter/space of 85/15 µm
Figure 4. The schematic flow of wafer level packaging platform using TSVs for the fluidic bio-
detector
Figure 5. The design schematic view and dimension of wafer level alignment method: Optical
microscopy using through-wafer holes in combination
The cross alignment mark
Through wafer hole
Figure 6. The alignment mark captured by a high power microscope
RD
2nd passivation
st
1 passivation
Silicon microwell array substrate
Figure 7. SEM image of a single TSV after the 2nd passivation process
Figure 8. Morphology of RDLs on the backside of the package after Ti/Cu etching
(a) (b)
(c)
Figure 9. 8-inch 3D WLCSP of the fluidic bio-detector (a) packages on a wafer before dicing (b) top
side of a single package for the bio-detector (c) backside of a single package for the bio-detector
(7.236×7.236×0.85 mm)
Figure 10. The bonding interface and amount of adhesive overflow with adhesive thickness of (a) 15
µm (b) 10 µm (c) 8 µm (d) 6 µm (e) 5µm (f) 4 µm (g) 2 µm
(a) (b)
Figure 11. (a) SEM image at the hot spot location of the GND-RDL heater short package sample (b)
SEM image of the normal package sample at the same location
(a)
RDL
nd
2 passivation
st
1 passivation
Si
(b)
(b)
RDL nd
2 passivation
st
1 passivation
Si
Silicon microwell array substrate
Figure 12. SEM image of the TSV of a single package after (a) TC 500 cycles (b) HAST 264 hours
Shuai Zhao received the B.E. degree in engineering mechanics from the North of
China Electronic Power University, Baoding, China, in 2014. He is currently pursuing
the Ph.D. degree in mechanics with the Beijing University of Technology, Beijing,
China.
His current research interests include reliability of materials and structure in the field
of advanced electronic packaging, including the thermal and mechanical modeling, packaging reliability,
3-D integration technology, and mechanical characterization of materials.
Daquan Yu received the B.E. and Ph.D. degree in Materials Science and Engineering
from Dalian University of Technology in 1997 and 2004, respectively. He was a Senior
R&D Engineer in Institute of Microelectronics, Singapore, from 2007-2010. He is the
CTO, President of Research Academy of Advanced Packaging Technology of Huatian
Group since 2014. He had carried out research work on advanced packaging technology
at Fraunhofer IZM, Germany and Institute of Microelectronics in Singapore. He was a professor of
Institute of Microelectronics, Chinese Academy of Sciences from 2010 to 2015. He has authored or co-
authored more than 150 peer-reviewed technical publications and holds more than 40 patents. He is an
IEEE senior member since 2013, the member of expert committee of 02 National Science & Technology
Major Program of China since 2014. He was awarded several honors such as Humboldt fellowship in
2006, 100 Talents Program of the Chinese Academy of Sciences in 2010, high-level innovation talent of
Jiangsu province in 2016.
Pei Chen received the B.S. degree from Xiamen University, Xiamen, China, in 2008,
and the M.S. and Ph.D. degrees from The University of Akron, Akron, OH, USA, in
2013. He joined the Beijing University of Technology, Beijing, China, in 2014, as a
Lecturer. His current research interests include mechanics in electronic packaging and
mechanical behavior of materials in electronic packaging.
Fei Qin received the B.E. degree in applied mechanics from Xi’an Jiaotong University,
Xi’an, China, in 1985, and the M.E. and Ph.D. degrees in solid mechanics from
Tsinghua University, Beijing, China, in 1987 and 1997, respectively. He was a Post-
Doctoral Fellow and Research Fellow with the School of Civil and Structures,
Nanyang Technological University, Singapore, from 1997 to 2000. He has been with
the Beijing University of Technology, Beijing, since 2001, where he is currently a Full
Professor and the Director of Institute of Electronics Packaging Technology and Reliability. He has
authored over 150 journal and conference papers, holds two U.S. patent and more than fifty Chinese
patents. His current research interests include the areas of computer methods in materials science and
engineering, design for reliability of electronic packaging, simulations and characterization of the
mechanical behavior of the materials, and structures and manufacturing processes in electronic packages.

Zhao 2018

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This article has been accepted for publication in a future issue of this journal, but has not been

Integration of CMOS image sensor and microwell array using

approach for integration of Complementary Metal-Oxide-Semiconductor (CMOS) Image Sensor (CIS)

Key words: LoC; microfluidics; 3D WLCSP; microwell; CIS; TSV; bio-detector

LoCs was still in its infancy.

commercialization of the LoC technologies.

[22]. Coincidently, Lindsay et al pursued a heterogeneous integration of CMOS biosensors and

characteristic test and reliability analysis is illustrated in the following.

2. Design concept of the CIS/Silicon microwell array integration

3. Fabrication and result

3.1 Silicon microwell array fabrication

3.2 CIS/silicon microwell array wafer level adhesive bonding

3.3 Process development of the TSV-based 3D WLCSP

package by blade dicing (DISCO AD20T).

3.4 Package result of the fluidic bio-detector

4.1 Optimization of the quality of the bonding interface

The void percentage at the bonding interface is lower than 2%.

4.2 Electrical characteristic measurement and failure analysis

temperature required for the bio-reaction by applying an alternating electric current.

4.3 Reliability assessment

significantly to the development and application of the LoC systems.

multiwall carbon nanotube/ferrocene for genomic DNA detection of Mycobacterium tuberculosis in

Table 4. Reliability test results

(a) (b) (c) (f)

(d) (e) (g)

The cross alignment mark

Through wafer hole

Figure 6. The alignment mark captured by a high power microscope

Silicon microwell array substrate

Silicon microwell array substrate

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