Thinkpad E580 LCFC Nm-b421 Dis E480 E580 r1.0

Vinafix.
com
Vinafix.com
+3V_VGA
+3V_VGA
Vinafix.com
Vinafix.com
5 4 3 2 1
+3VS +3VS <6,9,10,11,12,14,15,23,25,30,32,37,39,40,47,50,51,57,58,59,60,61,63,65,66,67,69,72,85,86>
+VCC_IO +VCC_IO <11,18,21,71>
+3VS
R0502 1 2 2K_0402_5% DDIP1_CTRLCLK DDIP1_HPD R0506 1 @ 2 100K_0402_5%
R0503 1 2 2K_0402_5% DDIP1_CTRLDATA DDIP2_HPD R0507 1 2 100K_0201_1%

D D
R0504 1 @ 2 2.2K_0201_1% DDIP2_CTRLCLK CPU_EDP_HPD R0508 1 2 100K_0402_5%
R0505 1 2 2.2K_0402_5% DDIP2_CTRLDATA ENBKL R0509 1 2 100K_0201_1%
DP port Enable Disable
DDPB_CTRLDATA pull-high no connect
DDPC_CTRLDATA pull-high no connect
SKL_ULT
UC1A
CPU_DDI1_N2 E55 C47 CPU_EDP_TX0-

<47> CPU_DDI1_N2 DDI1_TXN[0] EDP_TXN[0] CPU_EDP_TX0- <60>
CPU_DDI1_P2 F55 C46 CPU_EDP_TX0+
<47> CPU_DDI1_P2 DDI1_TXP[0] EDP_TXP[0] CPU_EDP_TX0+ <60>
CPU_DDI1_N1 E58 D46 CPU_EDP_TX1-
<47> CPU_DDI1_N1 DDI1_TXN[1] EDP_TXN[1] CPU_EDP_TX1- <60>
CPU_DDI1_P1 F58 C45 CPU_EDP_TX1+
<47> CPU_DDI1_P1 DDI1_TXP[1] EDP_TXP[1] CPU_EDP_TX1+ <60>
HDMI CPU_DDI1_N0 F53 A45
<47> CPU_DDI1_N0 DDI1_TXN[2] EDP_TXN[2]
CPU_DDI1_P0 G53 B45
<47> CPU_DDI1_P0 DDI1_TXP[2] EDP_TXP[2]
CPU_DDI1_N3 F56 A47
<47> CPU_DDI1_N3 DDI1_TXN[3] EDP_TXN[3]
CPU_DDI1_P3 G56 B47
<47> CPU_DDI1_P3 DDI1_TXP[3] EDP_TXP[3]
CPU_DDI2_N0 C50 E45 CPU_EDP_AUX# CPU_EDP_AUX# <60>
<42> CPU_DDI2_N0 DDI2_TXN[0] DDI EDP EDP_AUXN
CPU_DDI2_P0 D50 F45 CPU_EDP_AUX CPU_EDP_AUX <60>
<42> CPU_DDI2_P0 DDI2_TXP[0] EDP_AUXP
USB TYPE C CPU_DDI2_N1 C52
C <42> CPU_DDI2_N1 DDI2_TXN[1] C
CPU_DDI2_P1 D52 B52
<42> CPU_DDI2_P1 DDI2_TXP[1] EDP_DISP_UTIL
CPU_DDI2_N2 A50
<42> CPU_DDI2_N2 DDI2_TXN[2]
CPU_DDI2_P2 B50 G50
<42> CPU_DDI2_P2 DDI2_TXP[2] DDI1_AUXN
CPU_DDI2_N3 D51 F50
<42> CPU_DDI2_N3 DDI2_TXN[3] DDI1_AUXP
CPU_DDI2_P3 C51 E48 DDIP2_AUXN
<42> CPU_DDI2_P3 DDI2_TXP[3] DDI2_AUXN DDIP2_AUXN <42>
F48 DDIP2_AUXP
DDI2_AUXP DDIP2_AUXP <42>
G46
DISPLAY SIDEBANDS DDI3_AUXN F46
DDIP1_CTRLCLK L13 DDI3_AUXP
<47> DDIP1_CTRLCLK GPP_E18/DDPB_CTRLCLK
HDMI <47> DDIP1_CTRLDATA DDIP1_CTRLDATA L12 L9 DDIP1_HPD HDMI
GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0 DDIP1_HPD <47>
L7 DDIP2_HPD USB TYPE C
GPP_E14/DDPC_HPD1 DDIP2_HPD <42>
DDIP2_CTRLCLK N7 L6
DDIP2_CTRLDATA N8 GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2 N9
GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 L10 CPU_EDP_HPD
GPP_E17/EDP_HPD CPU_EDP_HPD <60>
N11
+VCC_IO R0501 N12 GPP_E22/DDPD_CTRLCLK R12 ENBKL
GPP_E23/DDPD_CTRLDATA EDP_BKLTEN ENBKL <40>
24.9_0402_1% R11 PCH_EDP_PWM
EDP_BKLTCTL PCH_EDP_PWM <60>
1 2 EDP_COMP E52 U13 PCH_ENVDD
EDP_RCOMP EDP_VDDEN PCH_ENVDD <60>
SKYLAKE-U_BGA1356 REV = 1 1 OF 20
Vinafix.com EDP_RCOMP
1. Trace width=20 mils, Spacing=25mil, Max length=100mils
2. RC1 close to MCP
Trace Width=20mil, Spacing=25mil, Max length=100mil
B B
A A
Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 KBL(A)_DDI/eDP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document
Document Number
Number Rev
Rev
Custom 0.2
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. !!"#$%&'()"*+
Date:
Date: Monday, October
October 30,
30, 2017
2017 Sheet
Sheet 5 of 99
99
5 4 3 2 1
5 4 3 2 1
+3VALW +2.5V
+3VS +3VS <5,9,10,11,12,14,15,23,25,30,32,37,39,40,47,50,51,57,58,59,60,61,63,65,66,67,69,72,85,86>
+2.5V +2.5V <23,24,25,26,94>
1
SKL_ULT
+3VALW UC1B R0601 R0602
+3VALW <9,12,15,19,40,50,58,60,63,65,66,67,72,83,84,91,95>
100K_0402_5% 100K_0402_5%
+1.2V AU53 -M_A_DDRCLK0_1066M @
+1.2V <7,18,23,24,25,26,85> DDR0_CKN[0] -M_A_DDRCLK0_1066M <23>
M_A_DQ0 AL71 AT53 M_A_DDRCLK0_1066M
DDR0_DQ[0] DDR0_CKP[0] M_A_DDRCLK0_1066M <23>
2
M_A_DQ1 AL68 AU55 -M_A_DDRCLK1_1066M
DDR0_DQ[1] DDR0_CKN[1] -M_A_DDRCLK1_1066M <23>
M_A_DQ2 AN68 AT55 M_A_DDRCLK1_1066M
DDR0_DQ[2] DDR0_CKP[1] M_A_DDRCLK1_1066M <23>
M_A_DQ3 AN69 SM_PG_CTRL
DDR0_DQ[3] SM_PG_CTRL <85>
M_A_DQ4 AL70 BA56 M_A_CKE0 +1.2V
DDR0_DQ[4] DDR0_CKE[0] M_A_CKE0 <23>
M_A_DQ5 AL69 BB56 M_A_CKE1
DDR0_DQ[5] DDR0_CKE[1] M_A_CKE1 <23>
1
M_A_DQ6 AN70 AW56
TABLE M_A_DQ7 AN71 DDR0_DQ[6] DDR0_CKE[2] AY56
M_A_DQ8 AR70 DDR0_DQ[7] DDR0_CKE[3] 2 Q0601
DDR0_DQ[8]
D Pin Interleave Non-Interleave M_A_DQ9
M_A_DQ10
AR68
AU71 DDR0_DQ[9] DDR0_CS#[0]
AU45
AU43
-M_A_CS0
-M_A_CS1
-M_A_CS0 <23>
DTC115TMT2L_VMT3 D
DDR0_DQ[10] DDR0_CS#[1] -M_A_CS1 <23>
M_A_DQ11 AU68 AT45 M_A_ODT0
DDR0_DQ[11] DDR0_ODT[0] M_A_ODT0 <23>
3
AL71 DDR0_DQ[0] DDR0_DQ[0] M_A_DQ12
M_A_DQ13
AR71
AR69 DDR0_DQ[12] DDR0_ODT[1]
AT43 M_A_ODT1
M_A_ODT1 <23>
AL68 DDR0_DQ[1] DDR0_DQ[1] M_A_DQ14 AU70 DDR0_DQ[13]
DDR0_DQ[14] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
BA51 M_A_A5 DDR_PG_CTRL DDR_PG_CTRL
M_A_DQ15 AU69 BB54 M_A_A9
AN68 DDR0_DQ[2] DDR0_DQ[2] M_A_DQ32 BB65 DDR0_DQ[15] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] BA52 M_A_A6
DDR0_DQ[16]/DDR0_DQ[32] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
AN69 DDR0_DQ[3] DDR0_DQ[3]
1
M_A_DQ33 AW65 AY52 M_A_A8 1
M_A_DQ34 AW63 DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] AW52 M_A_A7 C0601 R0604
AL70 DDR0_DQ[4] DDR0_DQ[4] M_A_DQ35 AY63 DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] AY55 M_A_BG0 0.1U_0402_10V7-K 10K_0402_5%
DDR0_DQ[19]/DDR0_DQ[35] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] M_A_BG0 <23>
AL69 DDR0_DQ[5] DDR0_DQ[5] M_A_DQ36
M_A_DQ37
BA65
AY65 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
AW54
BA54
M_A_A12
2
@ @
M_A_A11
AN70 DDR0_DQ[6] DDR0_DQ[6] DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]
2
M_A_DQ38 BA63 BA55 -M_A_ACT
DDR0_DQ[22]/DDR0_DQ[38] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# -M_A_ACT <23>
AN71 DDR0_DQ[7] DDR0_DQ[7] M_A_DQ39
M_A_DQ40
BB63
BA61 DDR0_DQ[23]/DDR0_DQ[39] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
AY54 M_A_BG1
M_A_BG1 <23>
+1.2V
Block 0 AR70 DDR0_DQ[8] DDR0_DQ[8] M_A_DQ41 AW61 DDR0_DQ[24]/DDR0_DQ[40]
DDR0_DQ[25]/DDR0_DQ[41] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]
AU46 M_A_A13
AR68 DDR0_DQ[9] DDR0_DQ[9] M_A_DQ42
M_A_DQ43
BB59
AW59 DDR0_DQ[26]/DDR0_DQ[42] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]
AU48
AT46
M_A_A15
M_A_A14 +3VALW +3VS
AU71 DDR0_DQ[10] DDR0_DQ[10] M_A_DQ44 BB61 DDR0_DQ[27]/DDR0_DQ[43]
DDR0_DQ[28]/DDR0_DQ[44]
DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]
DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]
AU50 M_A_A16
AU68 DDR0_DQ[11] DDR0_DQ[11] M_A_DQ45
M_A_DQ46
AY61
BA59 DDR0_DQ[29]/DDR0_DQ[45] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
AU52
AY51 M_A_A2
M_A_BS0
M_A_BS0 <23>
AR71 DDR0_DQ[12] DDR0_DQ[12] DDR0_DQ[30]/DDR0_DQ[46] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]
2
M_A_DQ47 AY59 ? AT48 M_A_BS1
DDR0_DQ[31]/DDR0_DQ[47] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] M_A_BS1 <23>
M_B_DQ0 AY39 AT50 M_A_A10 U0601 @ R0606 R0607
AR69 DDR0_DQ[13] DDR0_DQ[13] M_B_DQ1 AW39 DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] BB50 M_A_A1 R0605 1 6 100K_0402_5% 100K_0402_5%
DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] NC1 Vcc
AU70 DDR0_DQ[14] DDR0_DQ[14] M_B_DQ2 AY37
AY50 M_A_A0 0_0402_5% @ @
M_B_DQ3 AW37 BA50 M_A_A3 DDR_PG_CTRL 2 @ 1 2 5
AU69 DDR0_DQ[15] DDR0_DQ[15] DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] A NC2
1
M_B_DQ4 BB39 BB52 M_A_A4
M_B_DQ5 BA39 DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4] 3 4 SM_PG_CTRL
M_B_DQ6 BA37 DDR0_DQ[37]/DDR1_DQ[5] GND Y
AM70 -M_A_DQS0
M_B_DQ7 BB37 DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQSN[0] AM69 M_A_DQS0 74AUP1G07GF_SOT891-6_1X1
M_B_DQ8 AY35 DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQSP[0] AT69 -M_A_DQS1
DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQSN[1] 1
M_B_DQ9 AW35 AT70 M_A_DQS1 C0602
DDR0_DQ[41]/DDR1_DQ[9] DDR0_DQSP[1]
BB65 DDR0_DQ[16] DDR0_DQ[32] M_B_DQ10
M_B_DQ11
AY33
AW33 DDR0_DQ[42]/DDR1_DQ[10] DDR0_DQSN[2]/DDR0_DQSN[4]
BA64
AY64
-M_A_DQS4
M_A_DQS4
0.1U_0402_10V7-K
@
AW65 DDR0_DQ[17] DDR0_DQ[33] M_B_DQ12 BB35 DDR0_DQ[43]/DDR1_DQ[11]
DDR0_DQSP[2]/DDR0_DQSP[4]
DDR0_DQSN[3]/DDR0_DQSN[5]
AY60 -M_A_DQS5 2
M_B_DQ13 BA35 BA60
AW63 DDR0_DQ[18] DDR0_DQ[34] M_B_DQ14 BA33 DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQSP[3]/DDR0_DQSP[5] BA38
M_A_DQS5
-M_B_DQS0
AY63 DDR0_DQ[19] DDR0_DQ[35] M_B_DQ15 BB33 DDR0_DQ[46]/DDR1_DQ[14]
AY38 M_B_DQS0
C M_B_DQ32 AY31 AY34 -M_B_DQS1 C
BA65 DDR0_DQ[20] DDR0_DQ[36] M_B_DQ33 AW31 DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQSN[5]/DDR1_DQSN[1] BA34 M_B_DQS1
DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQSP[5]/DDR1_DQSP[1]
AY65 DDR0_DQ[21] DDR0_DQ[37] M_B_DQ34 AY29
DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQSN[6]/DDR1_DQSN[4]
BA30 -M_B_DQS4
M_B_DQ35 AW29 AY30 M_B_DQS4
BA63 DDR0_DQ[22] DDR0_DQ[38] M_B_DQ36 BB31 DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQSP[6]/DDR1_DQSP[4] AY26 -M_B_DQS5
M_A_DQ[63:0] <7,23>
DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQSN[7]/DDR1_DQSN[5]
BB63 DDR0_DQ[23] DDR0_DQ[39] M_B_DQ37
M_B_DQ38
BA31
BA29 DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSP[7]/DDR1_DQSP[5]
BA26 M_B_DQS5
Block 2 BA61 DDR0_DQ[24] DDR0_DQ[40] M_B_DQ39 BB29 DDR0_DQ[54]/DDR1_DQ[38]

DDR0_ALERT#
AW50
-M_A_ALERT <23> M_B_DQ[63:0] <7,25>
AW61 DDR0_DQ[25] DDR0_DQ[41] M_B_DQ40
M_B_DQ41
AY27
AW27 DDR0_DQ[56]/DDR1_DQ[40] DDR0_PAR
AT52
M_A_PARITY <23>
BB59 DDR0_DQ[26] DDR0_DQ[42] M_B_DQ42 AY25 DDR0_DQ[57]/DDR1_DQ[41]
DDR0_DQ[58]/DDR1_DQ[42] DDR_VREF_CA
AY67
M_A_VREF_CA_CPU <23> M_A_A[16:0] <23>
AW59 DDR0_DQ[27] DDR0_DQ[43] M_B_DQ43
M_B_DQ44
AW25
BB27 DDR0_DQ[59]/DDR1_DQ[43] DDR CH - A
DDR0_VREF_DQ
AY68
BA67
M_B_VREF_CA_CPU <25> -M_A_DQS[7:0] <7,23>
BB61 DDR0_DQ[28] DDR0_DQ[44] M_B_DQ45 BA27 DDR0_DQ[60]/DDR1_DQ[44]
DDR1_VREF_DQ
M_B_DQ46 AW67
AY61 DDR0_DQ[29] DDR0_DQ[45] M_B_DQ47
BA25
BB25 DDR0_DQ[62]/DDR1_DQ[46] DDR_VTT_CNTL
DDR_PG_CTRL M_A_DQS[7:0] <7,23>
BA59 DDR0_DQ[30] DDR0_DQ[46] DDR0_DQ[63]/DDR1_DQ[47]
-M_B_DQS[7:0] <7,25>
AY59 DDR0_DQ[31] DDR0_DQ[47] SKYLAKE-U_BGA1356 2 OF 20 ?
M_B_DQS[7:0] <7,25>
REV = 1
AY39 DDR0_DQ[32] DDR1_DQ[0]

AW39 DDR0_DQ[33] DDR1_DQ[1]
AW37 DDR0_DQ[35] DDR1_DQ[3]
BB39 DDR0_DQ[36] DDR1_DQ[4] TABLE
BA39 DDR0_DQ[37] DDR1_DQ[5] TABLE
BA37 DDR0_DQ[38] DDR1_DQ[6] Pin DDR3L LPDDR3 DDR4
BB37 Vinafix.com DDR0_DQ[39] DDR1_DQ[7] Pin Interleave Non-Interleave
AY35 DDR0_DQ[40] DDR1_DQ[8] BA51 DDR0_MA[5] DDR0_CAA[0] DDR0_MA[5]
Block 4 BB54 DDR0_MA[9] DDR0_CAA[1] DDR0_MA[9]
B AW35 DDR0_DQ[41] DDR1_DQ[9] AM70 DDR0_DQSN[0] DDR0_DQSN[0] B
AY33 DDR0_DQ[42] DDR1_DQ[10] AM69 DDR0_DQSP[0] DDR0_DQSP[0] BA52 DDR0_MA[6] DDR0_CAA[2] DDR0_MA[6]
AW33 DDR0_DQ[43] DDR1_DQ[11] Block 0 AT69 DDR0_DQSN[1] DDR0_DQSN[1] AY52 DDR0_MA[8] DDR0_CAA[3] DDR0_MA[8]
BB35 DDR0_DQ[44] DDR1_DQ[12] AT70 DDR0_DQSP[1] DDR0_DQSP[1] AW52 DDR0_MA[7] DDR0_CAA[4] DDR0_MA[7]
BA35 DDR0_DQ[45] DDR1_DQ[13] AY55 DDR0_BA[2] DDR0_CAA[5] DDR0_BG[0]
BA33 DDR0_DQ[46] DDR1_DQ[14] AW54 DDR0_MA[12] DDR0_CAA[6] DDR0_MA[12]
BB33 DDR0_DQ[47] DDR1_DQ[15] BA64 DDR0_DQSN[2] DDR0_DQSN[4] BA54 DDR0_MA[11] DDR0_CAA[7] DDR0_MA[11]
AY64 DDR0_DQSP[2] DDR0_DQSP[4] BA55 DDR0_MA[15] DDR0_CAA[8] DDR0_ACT#
Block 2 AY60 DDR0_DQSN[3] DDR0_DQSN[5] AY54 DDR0_MA[14] DDR0_CAA[9] DDR0_BG[1]
BA60 DDR0_DQSP[3] DDR0_DQSP[5]
AW31 DDR0_DQ[49] DDR1_DQ[33] BA38 DDR0_DQSN[4] DDR1_DQSN[0] AU46 DDR0_MA[13] DDR0_CAB[0] DDR0_MA[13]
AY29 DDR0_DQ[50] DDR1_DQ[34] AY38 DDR0_DQSP[4] DDR1_DQSP[0] AU48 DDR0_CAS# DDR0_CAB[1] DDR0_MA[15]
AW29 DDR0_DQ[51] DDR1_DQ[35] Block 4 AY34 DDR0_DQSN[5] DDR1_DQSN[1] AT46 DDR0_WE# DDR0_CAB[2] DDR0_MA[14]
BB31 DDR0_DQ[52] DDR1_DQ[36] BA34 DDR0_DQSP[5] DDR1_DQSP[1] AU50 DDR0_RAS# DDR0_CAB[3] DDR0_MA[16]
BA31 DDR0_DQ[53] DDR1_DQ[37] AU52 DDR0_BA[0] DDR0_CAB[4] DDR0_BA[0]
BA29 DDR0_DQ[54] DDR1_DQ[38] AY51 DDR0_MA[2] DDR0_CAB[5] DDR0_MA[2]
BB29 DDR0_DQ[55] DDR1_DQ[39] BA30 DDR0_DQSN[6] DDR1_DQSN[4] AT48 DDR0_BA[1] DDR0_CAB[6] DDR0_BA[1]
Block 6 AY27 DDR0_DQ[56] DDR1_DQ[40] AY30 DDR0_DQSP[6] DDR1_DQSP[4] AT50 DDR0_MA[10] DDR0_CAB[7] DDR0_MA[10]
AW27 DDR0_DQ[57] DDR1_DQ[41] Block 6 AY26 DDR0_DQSN[7] DDR1_DQSN[5] BB50 DDR0_MA[1] DDR0_CAB[8] DDR0_MA[1]
AY25 DDR0_DQ[58] DDR1_DQ[42] BA26 DDR0_DQSP[7] DDR1_DQSP[5] AY50 DDR0_MA[0] DDR0_CAB[9] DDR0_MA[0]
AW25 DDR0_DQ[59] DDR1_DQ[43] BA50 DDR0_MA[3] Not Used DDR0_MA[3]
BB27 DDR0_DQ[60] DDR1_DQ[44] BB52 DDR0_MA[4] Not Used DDR0_MA[4]
BA27 DDR0_DQ[61] DDR1_DQ[45]
BA25 DDR0_DQ[62] DDR1_DQ[46]
A BB25 DDR0_DQ[63] DDR1_DQ[47] A
LOGIC
LOGIC

LOGIC
Issued Date 2015/09/01 Deciphered Date 2016/12/31 KBL(B)_DDR4 CH.A
Size
Document Number
Number Rev
Rev
Custom 0.2
Date:
Date: Monday, October 30, 2017 Sheet
Sheet 6 of 99
5 4 3 2 1
5 4 3 2 1
SKL_ULT
+1.2V UC1C
+1.2V <6,18,23,24,25,26,85>
M_A_DQ16 AF65 AN45 -M_B_DDRCLK0_1066M

DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKN[0] -M_B_DDRCLK0_1066M <25> M_A_DQ[63:0] <6,23>
M_A_DQ17 AF64 AN46 -M_B_DDRCLK1_1066M
DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[1] -M_B_DDRCLK1_1066M <25>
M_A_DQ18 AK65 AP45 M_B_DDRCLK0_1066M
DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[0] M_B_DDRCLK0_1066M <25>
M_A_DQ19 AK64 AP46 M_B_DDRCLK1_1066M
DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1] M_B_DDRCLK1_1066M <25>
M_A_DQ20 AF66
DDR1_DQ[4]/DDR0_DQ[20] M_B_DQ[63:0] <6,25>
M_A_DQ21 AF67 AN56 M_B_CKE0
DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKE[0] M_B_CKE0 <25>
M_A_DQ22 AK67 AP55 M_B_CKE1
DDR1_DQ[6]/DDR0_DQ[22] DDR1_CKE[1] M_B_CKE1 <25>
M_A_DQ23 AK66 AN55
TABLE M_A_DQ24 AF70 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKE[2] AP53
DDR1_DQ[8]/DDR0_DQ[24] DDR1_CKE[3] M_B_A[16:0] <25>
M_A_DQ25 AF68
M_A_DQ26 DDR1_DQ[9]/DDR0_DQ[25] BB42
Pin Interleave Non-Interleave M_A_DQ27
AH71
AH68 DDR1_DQ[10]/DDR0_DQ[26] DDR1_CS#[0] AY42
-M_B_CS0
-M_B_CS1
-M_B_CS0 <25> -M_A_DQS[7:0] <6,23>
DDR1_DQ[11]/DDR0_DQ[27] DDR1_CS#[1] -M_B_CS1 <25>
D M_A_DQ28 AF71 BA42 M_B_ODT0 D
DDR1_DQ[12]/DDR0_DQ[28] DDR1_ODT[0] M_B_ODT0 <25> M_A_DQS[7:0] <6,23>
M_A_DQ29
AF65 DDR1_DQ[0] DDR0_DQ[16] M_A_DQ30
AF69
AH70 DDR1_DQ[13]/DDR0_DQ[29] DDR1_ODT[1]
AW42 M_B_ODT1
M_B_ODT1 <25>
-M_B_DQS[7:0] <6,25>
AF64 DDR1_DQ[1] DDR0_DQ[17] M_A_DQ31 AH69 DDR1_DQ[14]/DDR0_DQ[30]
AY48 M_B_A5
M_A_DQ48 AT66 AP50 M_B_A9
AK65 DDR1_DQ[2] DDR0_DQ[18] M_A_DQ49 AU66 DDR1_DQ[16]/DDR0_DQ[48] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] BA48 M_B_A6
M_B_DQS[7:0] <6,25>
AK64 DDR1_DQ[3] DDR0_DQ[19] M_A_DQ50 AP65
BB48 M_B_A8
M_A_DQ51 AN65 AP48 M_B_A7
AF66 DDR1_DQ[4] DDR0_DQ[20] M_A_DQ52 AN66 DDR1_DQ[19]/DDR0_DQ[51] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] AP52 M_B_BG0
DDR1_DQ[20]/DDR0_DQ[52] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] M_B_BG0 <25>
M_A_DQ54
AP66
AT65 DDR1_DQ[21]/DDR0_DQ[53] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
AN50
AN48
M_B_A12
M_B_A11
AK67 DDR1_DQ[6] DDR0_DQ[22] M_A_DQ55 AU65 DDR1_DQ[22]/DDR0_DQ[54] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] AN53 -M_B_ACT
-M_B_ACT <25>
DDR1_DQ[23]/DDR0_DQ[55] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
AK66 DDR1_DQ[7] DDR0_DQ[23] M_A_DQ56
M_A_DQ57
AT61
AU61 DDR1_DQ[24]/DDR0_DQ[56] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
AN52 M_B_BG1
M_B_BG1 <25>
Block 1 AF70 DDR1_DQ[8] DDR0_DQ[24] M_A_DQ58 AP60 DDR1_DQ[25]/DDR0_DQ[57]

BA43 M_B_A13
M_A_DQ60
AN60
AN61 DDR1_DQ[27]/DDR0_DQ[59] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]
AY43
AY44
M_B_A15
M_B_A14
AH71 DDR1_DQ[10] DDR0_DQ[26] M_A_DQ61 AP61 DDR1_DQ[28]/DDR0_DQ[60]
DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]
DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]
AW44 M_B_A16
BB44
AH68 DDR1_DQ[11] DDR0_DQ[27] M_A_DQ62
M_A_DQ63
AT60
AU60 DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
? AY47
M_B_BS0
M_B_A2
M_B_BS0 <25>
AF71 DDR1_DQ[12] DDR0_DQ[28] M_B_DQ16 AU40 DDR1_DQ[31]/DDR0_DQ[63]
DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
BA44 M_B_BS1
M_B_BS1 <25>
M_B_DQ17 AT40 AW46 M_B_A10
AF69 DDR1_DQ[13] DDR0_DQ[29] M_B_DQ18 AT37 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] AY46 M_B_A1
AH70 DDR1_DQ[14] DDR0_DQ[30] M_B_DQ19 AU37
BA46 M_B_A0
M_B_DQ20 AR40 BB46 M_B_A3
AH69 DDR1_DQ[15] DDR0_DQ[31] M_B_DQ21 AP40 DDR1_DQ[36]/DDR1_DQ[20] DDR1_MA[3] BA47 M_B_A4
M_B_DQ22 AP37 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[4]
M_B_DQ23 AR37 DDR1_DQ[38]/DDR1_DQ[22] AH66 -M_A_DQS2
M_B_DQ24 AT33 DDR1_DQ[39]/DDR1_DQ[23] DDR1_DQSN[0]/DDR0_DQSN[2] AH65 M_A_DQS2
M_B_DQ25 AU33 DDR1_DQ[40]/DDR1_DQ[24] DDR1_DQSP[0]/DDR0_DQSP[2] AG69 -M_A_DQS3
M_B_DQ26 AU30 DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQSN[1]/DDR0_DQSN[3] AG70 M_A_DQS3
DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQSP[1]/DDR0_DQSP[3]
AT66 DDR1_DQ[16] DDR0_DQ[48] M_B_DQ27
M_B_DQ28
AT30
AR33 DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQSN[2]/DDR0_DQSN[6]
AR66
AR65
-M_A_DQS6
M_A_DQS6
AU66 DDR1_DQ[17] DDR0_DQ[49] M_B_DQ29 AP33 DDR1_DQ[44]/DDR1_DQ[28]
AR61 -M_A_DQS7
M_B_DQ30 AR30 AR60 M_A_DQS7 +1.2V
AP65 DDR1_DQ[18] DDR0_DQ[50] M_B_DQ31 AP30 DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQSP[3]/DDR0_DQSP[7] AT38 -M_B_DQS2
AN65 DDR1_DQ[19] DDR0_DQ[51] M_B_DQ48 AU27 DDR1_DQ[47]/DDR1_DQ[31]
DDR1_DQ[48]
AR38 M_B_DQS2
M_B_DQ49 AT27 AT32 -M_B_DQS3
AN66 DDR1_DQ[20] DDR0_DQ[52] DDR1_DQ[49] DDR1_DQSN[5]/DDR1_DQSN[3]
2
M_B_DQ50 AT25 AR32 M_B_DQS3
DDR1_DQ[50] DDR1_DQSP[5]/DDR1_DQSP[3]
C AP66 DDR1_DQ[21] DDR0_DQ[53] M_B_DQ51 AU25
DDR1_DQ[51] DDR1_DQSN[6]
AR25 -M_B_DQS6 R0703
470_0201_5%
C
M_B_DQ52 AP27 AR27 M_B_DQS6
AT65 DDR1_DQ[22] DDR0_DQ[54] M_B_DQ53 AN27 DDR1_DQ[52] DDR1_DQSP[6] AR22 -M_B_DQS7
DDR1_DQ[53] DDR1_DQSN[7]
AU65 DDR1_DQ[23] DDR0_DQ[55] M_B_DQ54 AN25
DDR1_DQ[54] DDR1_DQSP[7]
AR21 M_B_DQS7
1
M_B_DQ55 AP25
Block 3 AT61 DDR1_DQ[24] DDR0_DQ[56] M_B_DQ56 AT22 DDR1_DQ[55]
DDR1_ALERT#
AN43 -M_B_ALERT -M_B_ALERT <25>
DDR1_DQ[56]
AU61 DDR1_DQ[25] DDR0_DQ[57] M_B_DQ57
M_B_DQ58
AU22
AU21 DDR1_DQ[57] DDR1_PAR
AP43
AT13
M_B_PARITY
-DRAMRST
M_B_PARITY <25>
AP60 DDR1_DQ[26] DDR0_DQ[58] M_B_DQ59 AT21 DDR1_DQ[58]
DDR1_DQ[59]
DRAM_RESET#
DDR_RCOMP[0]
AR18 DDR_RCOMP0 R0704 1 2 121_0201_1%
-DRAMRST <23,25>
AN60 DDR1_DQ[27] DDR0_DQ[59] M_B_DQ60

M_B_DQ61
AN22
AP22 DDR1_DQ[60] DDR_RCOMP[1]
AT18
AU18
DDR_RCOMP1
DDR_RCOMP2
R0701
R0702
1
1
2
2
80.6_0201_1%
100_0201_1%
AN61 DDR1_DQ[28] DDR0_DQ[60] M_B_DQ62 AP21 DDR1_DQ[61]
DDR1_DQ[62]
DDR_RCOMP[2]
AN21
AP61 DDR1_DQ[29] DDR0_DQ[61] M_B_DQ63
DDR1_DQ[63]
DDR CH - B
AT60 DDR1_DQ[30] DDR0_DQ[62] [KBL PDG]for DDR4 COMPENSATION

SKYLAKE-U_BGA1356 3 OF 20 ?
AU60 DDR1_DQ[31] DDR0_DQ[63] REV = 1 DDR_RCOMP[0] Pull down 121 ohm resistor
DDR_RCOMP[1] Pull down 80.6 ohm resistor
DDR_RCOMP[2] Pull down 100 ohm resistor
AU40 DDR1_DQ[32] DDR1_DQ[16]

AT40 DDR1_DQ[33] DDR1_DQ[17]
AT37 DDR1_DQ[34] DDR1_DQ[18]
AU37 DDR1_DQ[35] DDR1_DQ[19] TABLE
AR40 DDR1_DQ[36] DDR1_DQ[20]
AP40 DDR1_DQ[37] DDR1_DQ[21] TABLE Pin DDR3L LPDDR3 DDR4
AP37 DDR1_DQ[38] DDR1_DQ[22]
AR37 DDR1_DQ[39] DDR1_DQ[23] Pin Interleave Non-Interleave AY48 DDR1_MA[5] DDR1_CAA[0] DDR1_MA[5]
Block 5 AT33 Vinafix.com DDR1_DQ[40] DDR1_DQ[24] AP50 DDR1_MA[9] DDR1_CAA[1] DDR1_MA[9]
AU33 DDR1_DQ[41] DDR1_DQ[25] AH66 DDR1_DQSN[0] DDR0_DQSN[2] BA48 DDR1_MA[6] DDR1_CAA[2] DDR1_MA[6]
B
AU30 DDR1_DQ[42] DDR1_DQ[26] AH65 DDR1_DQSP[0] DDR0_DQSP[2] BB48 DDR1_MA[8] DDR1_CAA[3] DDR1_MA[8] B
AT30 DDR1_DQ[43] DDR1_DQ[27] Block 1 AG69 DDR1_DQSN[1] DDR0_DQSN[3] AP48 DDR1_MA[7] DDR1_CAA[4] DDR1_MA[7]
AR33 DDR1_DQ[44] DDR1_DQ[28] AG70 DDR1_DQSP[1] DDR0_DQSP[3] AP52 DDR1_BA[2] DDR1_CAA[5] DDR1_BG[0]
AP33 DDR1_DQ[45] DDR1_DQ[29] AN50 DDR1_MA[12] DDR1_CAA[6] DDR1_MA[12]
AR30 DDR1_DQ[46] DDR1_DQ[30] AN48 DDR1_MA[11] DDR1_CAA[7] DDR1_MA[11]
AP30 DDR1_DQ[47] DDR1_DQ[31] AR66 DDR1_DQSN[2] DDR0_DQSN[6] AN53 DDR1_MA[15] DDR1_CAA[8] DDR1_ACT#
AR65 DDR1_DQSP[2] DDR0_DQSP[6] AN52 DDR1_MA[14] DDR1_CAA[9] DDR1_BG[1]
Block 3 AR61 DDR1_DQSN[3] DDR0_DQSN[7]
AR60 DDR1_DQSP[3] DDR0_DQSP[7]
AU27 DDR1_DQ[48] DDR1_DQ[48]
AT27 DDR1_DQ[49] DDR1_DQ[49] BA43 DDR1_MA[13] DDR1_CAB[0] DDR1_MA[13]
AT38 DDR1_DQSN[4] DDR1_DQSN[2] AY43 DDR1_CAS# DDR1_CAB[1] DDR1_MA[15]
AT25 DDR1_DQ[50] DDR1_DQ[50] AR38 DDR1_DQSP[4] DDR1_DQSP[2]
AU25 DDR1_DQ[51] DDR1_DQ[51] AY44 DDR1_WE# DDR1_CAB[2] DDR1_MA[14]
Block 5 AT32 DDR1_DQSN[5] DDR1_DQSN[3] AW44 DDR1_RAS# DDR1_CAB[3] DDR1_MA[16]
AP27 DDR1_DQ[52] DDR1_DQ[52] AR32 DDR1_DQSP[5] DDR1_DQSP[3]
AN27 DDR1_DQ[53] DDR1_DQ[53] BB44 DDR1_BA[0] DDR1_CAB[4] DDR1_BA[0]
AN25 DDR1_DQ[54] DDR1_DQ[54] AY47 DDR1_MA[2] DDR1_CAB[5] DDR1_MA[2]
AP25 DDR1_DQ[55] DDR1_DQ[55] AR25 DDR1_DQSN[6] DDR1_DQSN[6] BA44 DDR1_BA[1] DDR1_CAB[6] DDR1_BA[1]
AT22 DDR1_DQ[56] DDR1_DQ[56] AR27 DDR1_DQSP[6] DDR1_DQSP[6] AW46 DDR1_MA[10] DDR1_CAB[7] DDR1_MA[10]
Block 7 AY46 DDR1_MA[1] DDR1_CAB[8] DDR1_MA[1]
AU22 DDR1_DQ[57] DDR1_DQ[57] Block 7 AR22 DDR1_DQSN[7] DDR1_DQSN[7]
AU21 DDR1_DQ[58] DDR1_DQ[58] AR21 DDR1_DQSP[7] DDR1_DQSP[7] BA46 DDR1_MA[0] DDR1_CAB[9] DDR1_MA[0]
AT21 DDR1_DQ[59] DDR1_DQ[59] BB46 DDR1_MA[3] Not Used DDR1_MA[3]
AN22 DDR1_DQ[60] DDR1_DQ[60] BA47 DDR1_MA[4] Not Used DDR1_MA[4]
AN21 DDR1_DQ[63] DDR1_DQ[63]
LOGIC
A A
LOGIC
LOGIC
Issued Date 2015/09/01 Deciphered Date 2016/12/31 KBL(C)_DDR4 CH.B
Size
Size Document
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DocumentNumber
Document Number
Number Rev
Rev
Rev
Custom
Custom 0.2
0.2
Date:
Date:
Date: Monday,
Monday, October
October 30,
30, 2017
2017 Sheet
Sheet
Sheet 77 of 99
99
5 4 3 2 1
5 4 3 2 1
+VCC_ST +VCC_ST <15,16,18,21,71,86>
+VCC_STG +VCC_STG <16,18,71>
+3VALW_PCH +3VALW_PCH <9,10,11,12,19>
D D
+VCC_STG
1
R0801
1K_0402_5%
R0802
2 499_0201_1%
<40,83,86> VR_HOT# VR_HOT# 1 2
+VCC_ST
1
UC1D SKL_ULT
R0803 +VCC_STG
1K_0201_1% 1 CATERR# D63
T1 CATERR#
H_PECI A54
C <40> H_PECI PECI C
VR_HOT#_R C65 JTAG
PROCHOT#
2
THERMTRIP# C63
A65 THERMTRIP# B61 XDP_TCLK R0817 1 2 51_0201_5%
+3VALW_PCH SKTOCC# PROC_TCK D60 XDP_TDI
CPU MISC PROC_TDI
1 XDP_BPM#0 C55 A61 XDP_TDO
T4 BPM#[0] PROC_TDO
1 XDP_BPM#1 D55 C60 XDP_TMS
T6 BPM#[1] PROC_TMS
1
1 XDP_BPM#2 B54 B59 XDP_TRST#

T8 BPM#[2] PROC_TRST#
1 XDP_BPM#3 C56
T10 BPM#[3]
R0806 B56 PCH_JTAG_TCK R0818 1 @ 2 51_0201_5%
10K_0402_5% A6 PCH_JTAG_TCK D59 PCH_JTAG_TDI
R0805 GPP_E3/CPU_GP0 PCH_JTAG_TDI
A7 A56 PCH_JTAG_TDO R0816 1 2 100_0201_5%
GPP_E7/CPU_GP1 PCH_JTAG_TDO
2
1 2 EC_WAKE#_SUS BA5 C59 PCH_JTAG_TMS

<40> EC_WAKE# AY5 GPP_B3/CPU_GP2 PCH_JTAG_TMS C61 PCH_JTAG_TRST#
0_0402_5%_SM GPP_B4/CPU_GP3 PCH_TRST# A59 PCH_JTAGX
R0807 1 2 49.9_0402_1% PROC_POPIRCOMP AT16 JTAGX
R0808 1 2 49.9_0402_1% PCH_OPIRCOMP AU16 PROC_POPIRCOMP
R0809 1 2 49.9_0402_1% OPCE_RCOMP H66 PCH_OPIRCOMP
R0810 1 2 49.9_0402_1% OPC_RCOMP H65 OPCE_RCOMP XDP_TCLK R0811 1 DCI@ 2 0_0201_5% PCH_JTAGX
OPC_RCOMP
XDP_TDI R0812 1 DCI@ 2 0_0201_5% PCH_JTAG_TDI
XDP_TDO R0813 1 DCI@ 2 0_0201_5% PCH_JTAG_TDO
XDP_TMS R0814 1 DCI@ 2 0_0201_5% PCH_JTAG_TMS
XDP_TRST# R0815 1 DCI@ 2 0_0201_5% PCH_JTAG_TRST#
B
Vinafix.com [KBL PDG FOR DCL DEBUG]
B
A A

Issued Date 2015/01/12 Deciphered Date 2016/01/12 KBL(D)_MISC/ JTAG
Size
Document Number
Number Rev
Rev
Custom 0.2
Date:
Sheet 8 of 99
5 4 3 2 1
5 4 3 2 1
+3VALW_PCH +3VALW_PCH <8,10,11,12,19>

20121218
+3V_SPI +3V_SPI <19>
GPP_C5, Internal PD 20K
Functional Strap Definitions
+3VS +3VS <5,6,10,11,12,14,15,23,25,30,32,37,39,40,47,50,51,57,58,59,60,61,63,65,66,67,69,72,85,86> L:Disable Intel ME Crypto TLS cipher suite
+3VALW_PCH *L: LPC (no confidentiality).
R0951 H: eSPI
PCH_SMB_CLK 1 8
*H:Enable Intel ME Crypto Transport Layer
PCH_SMB_DATA 2 7 Security (TLS) cipher
PCH_SML1CLK 3 6 suite (with confidentiality).Support Intel
To TPM IC PCH_SML1DATA 4 5 AMT with TLS and Intel
Mirror Code, Close to SPI ROM (UC8M1). SBA (Small Business Advantage) with TLS.
FSCE# R0924 1 2 0_0402_5%_SM SPI_CS0#_8MB SPI_CLK 10K_0804_8P4R_5%
<40> FSCE# <58> SPI_CLK
SPI_FMOSI# R0925 1 2 0_0402_5%_SM SPI_SI_8MB SPI_SI +3VALW_PCH GPP_C2, Internal PD 20K
<40> SPI_FMOSI# <58> SPI_SI
SPI_FMISO R0926 1 2 0_0402_5%_SM SPI_SO_8MB <58> SPI_SO SPI_SO
<40> SPI_FMISO
SPI_FSCK R0927 1 2 0_0402_5%_SM SPI_CLK_8MB SPI_CS2#_TPM +3VALW_PCH +3VALW_PCH
<40> SPI_FSCK <58> SPI_CS2#_TPM
D PCH_SML0_DAT R0907 1 2 499_0201_1% D
PCH_SML0_CLK R0908 1 2 499_0201_1%
1
Reverse internal 1K PU high
1
R0912
+3VS R0918 1K_0402_5%
+3V_SPI +3V_SPI 1K_0402_5%
+3VS SUS_STAT# R0952 1 @ 2 10K_0402_5% @
2
R0950 SKL_ULT
2
1
1
1 8 SERIRQ UC1E GPP_C5 GPP_C2
2 7 KBRST# R0928 R0902
SPI - FLASH
1
3 6 EC_SCI# 1K_0402_1% 1K_0402_1% SMBUS, SMLINK
1
4 5 SPI_CLK AV2 R7 PCH_SMB_CLK R0919
SPI_SO AW3 SPI0_CLK GPP_C0/SMBCLK R8 PCH_SMB_DATA 20K_0402_5% R0913
SPI0_MISO GPP_C1/SMBDATA
2
2
10K_0804_8P4R_5% SPI_SI AV3 R10 GPP_C2 @ 20K_0201_5%
SPI_IO2 AW2 SPI0_MOSI GPP_C2/SMBALERT# @
SPI0_IO2
2
SPI_IO3 AU4 R9 PCH_SML0_CLK
SPI0_IO3 GPP_C3/SML0CLK
2
SPI_CS0#_8MB_R AU3 W2 PCH_SML0_DAT LAN PHY
SPI0_CS0# GPP_C4/SML0DATA
2
2
JTAG ODT SPI_CS1#_4MB_R AU2
SPI0_CS1# GPP_C5/SML0ALERT#
W1 GPP_C5 +3VALW_PCH
SPI0_MOSI R0947 R0946 SPI_CS2#_TPM AU1
SPI0_CS2#
1K_0402_1% 1K_0402_1% W3 PCH_SML1CLK
+3V_SPI +3V_SPI @ @ GPP_C6/SML1CLK V3 PCH_SML1DATA
SPI - TOUCH GPP_C7/SML1DATA AM7 GPP_B23 R0909 1 2 150K_0402_5%
GPP_B23/SML1ALERT#/PCHHOT#
1
1
M2
GPP_D1/SPI1_CLK
1
M3
R0914 R0916 J4 GPP_D2/SPI1_MISO FOR DCI USE
1K_0402_5% 1K_0402_5% V1 GPP_D3/SPI1_MOSI
@ @ V2 GPP_D21/SPI1_IO2
EC_SCI# M1 GPP_D22/SPI1_IO3 AY13 LPC_AD0
EC and TPM Module debug port
<40> EC_SCI# LPC LPC_AD0 <40>
GPP_D0/SPI1_CS# GPP_A1/LAD0/ESPI_IO0
2
SPI_SI SPI_SO BA13 LPC_AD1 LPC_AD1 <40>

GPP_A2/LAD1/ESPI_IO1 BB13 LPC_AD2
GPP_A3/LAD2/ESPI_IO2 LPC_AD2 <40>
1
C LINK
1
C-LINK AY12 LPC_AD3 LPC_AD3 <40>

R0915 R0917 CL_CLK_WLAN G3 GPP_A4/LAD3/ESPI_IO3 BA12 LPC_FRAME#
<63> CL_CLK_WLAN CL_CLK GPP_A5/LFRAME#/ESPI_CS# LPC_FRAME# <40>
20K_0402_5% 20K_0402_5% CL_DATA_WLAN G2 BA11 SUS_STAT# 1
<63> CL_DATA_WLAN CL_DATA GPP_A14/SUS_STAT#/ESPI_RESET# T18
@ @ <63> CL_RST_WLAN# CL_RST_WLAN# G1
Default CL_RST#
C C
2
2
AW9 PCH_PCI_CLK_R R0910 1 EMC@ 2 22_0402_5% CLK_PCI_EC <40>

KBRST# AW13 GPP_A9/CLKOUT_LPC0/ESPI_CLK AY9 +3VS
<40> KBRST# GPP_A0/RCIN# GPP_A10/CLKOUT_LPC1 AW11 CLKRUN# R0911 1 2 8.2K_0402_5% 1
SERIRQ AY11 GPP_A8/CLKRUN# C0903
<40,58> SERIRQ GPP_A6/SERIRQ 22P_0402_50V8-J
EMC_NS@
SKYLAKE-U_BGA1356 REV = 1 5 OF 20 2
+3VS +3VS
SMBus
1
1
R0920 R0921
+3VALW +3V_SPI 4.7K_0402_5% 4.7K_0402_5%
[SKL]SPI0_CS0#: SPI FLASH 0.085 A, 10mils
SPI0_CS1#: SPI FLASH
2
2
SPI0_CS2#: SPI TPM
2
R0905
G
1 2
0_0402_5%_SM
PCH_SMB_CLK 6 1 PM_SMB_CLK
8MB(64Mb) 4MB(32Mb) PM_SMB_CLK <23,25,65>
S
D
Q0901A
+3V_SPI +3V_SPI L2N7002KDW1T1G_SOT363-6
SB000013A00
U0901 U0902
SPI_CS0#_8MB_R R0948 1 2 0_0402_5%_SM SPI_CS0#_8MB 1 8 +3V_SPI SPI_CS1#_4MB_R R0949 1 4M@ 2 0_0402_5% SPI_CS1#_4MB 1 8 +3V_SPI R0953 1 @ 2 0_0402_5%
/CS VCC CS# VCC
SPI_SO_4MB 2 7 SPI_IO3_4MB
DO HOLD#
5
SPI_SO_8MB 2 7 SPI_IO3_8MB 1 SPI_IO2_4MB 3 6 SPI_CLK_4MB 1
G
DO (IO1) IO3 WP# CLK C0901
4 5 SPI_SI_4MB
B SPI_IO2_8MB 3 6 SPI_CLK_8MB C0902 GND DI 0.1U_0402_10V7-K B
IO2 CLK 4M@
0.1U_0402_10V7-K W25Q32JVSSIQ
4 5 2 2 PCH_SMB_DATA 3 4 PM_SMB_DAT
SPI_SI_8MB 4M@ PM_SMB_DAT <23,25,65>
GND DI (IO0)
S
SA000089800
D
Q0901B
W25Q64JVSSIQ L2N7002KDW1T1G_SOT363-6 DIMM1, DIMM2 CP
SA000089Z00 SB000013A00
R0954 1 @ 2 0_0402_5%
R0935,0936,0937,0938,0942 shold be Near U0901 SPI ROM(0.5~1 inch) R0940,0941,0942,0943,0944 shold be Near U0902 SPI ROM(0.5~1 inch) +3VS
SPI_IO3_8MB R0935 1 2 33_0402_5% SPI_IO3 SPI_IO3_4MB R0940 1 4M@ 2 33_0402_5% SPI_IO3

SPI_CLK_8MB R0936 1 2 33_0402_5% SPI_CLK SPI_CLK_4MB R0942 1 4M@ 2 33_0402_5% SPI_CLK
SPI_SI_8MB R0937 1 2 33_0402_5% SPI_SI SPI_SI_4MB R0943 1 4M@ 2 33_0402_5% SPI_SI
SPI_IO2_8MB R0938 1 2 33_0402_5% SPI_IO2 SPI_IO2_4MB R0944 1 4M@ 2 33_0402_5% SPI_IO2
SPI_SO_8MB R0939 1 2 33_0402_5% SPI_SO SPI_SO_4MB R0945 1 4M@ 2 33_0402_5% SPI_SO
2
G
Vinafix.com PCH_SML1CLK 6 1 EC_SMB_CK3 EC_SMB_CK3 <32,40,57,59>
S
D
Q0902A
5
L2N7002KDW1T1G_SOT363-6
G
SB000013A00
PCH_SML1DATA 3 4 EC_SMB_DA3 EC_SMB_DA3 <32,40,57,59>
S
D
Q0902B
SB000013A00
2N7002KDWH GPU, Thermal Sendor,

A Vth= min 1V, max 2.5V A
ESD 2KV Embedded Controller, G sensor

Issued Date 2015/01/12 Deciphered Date 2016/01/12 KBL(E)_SPI/LPC/CLINK/SMBUS
Size
Size Document
Number Rev
Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
Date:
Sheet 9 of 99
5 4 3 2 1
5 4 3 2 1
+3VALW_PCH +3VALW_PCH <8,9,11,12,19>

+3VALW_PCH GPP_B22, Internal PD 20K +3VS +3VS
+3VS +3VS <5,6,9,11,12,14,15,23,25,30,32,37,39,40,47,50,51,57,58,59,60,61,63,65,66,67,69,72,85,86>
GPP_B18, Internal PD 20K
+3VALW +3VALW <6,9,12,15,19,40,50,58,60,63,65,66,67,72,83,84,91,95> *L: SPI
*L: Disable “No Reboot” mode H: LPC
1
H: Enable “No Reboot” mode
1
R1008 R1012
1K_0402_5% R1010 10K_0201_5%
@ 20K_0402_5% @
@
2
+3VALW_PCH +3VS
2
GPP_B18 GPP_B22 DISCRETE_PRESENCE
1
1
D R1003 1 2 10K_0201_5% VGA_ON R1011 R1013 D
+3VALW_PCH R1009 20K_0402_5%
R1001 R1004 1 2 4.7K_0402_5% BT_ON 20K_0402_5% @ 10K_0201_5%
10K_0402_5% @ @
2
1 @ 2 RF_OFF#
2
+3VS R1002
10K_0402_5%
1 2 R1007 1 @ 2 10K_0201_5% DGPU_HOLD_RST#
R1035 1 2 100K_0201_5%
SKL_ULT
UC1F
LPSS ISH
RF_OFF# AN8 P2
<63> RF_OFF# GPP_B15/GSPI0_CS# GPP_D9
AP7 P3 LID_CLOSE#_PCH R1032 1 2 0_0201_5%_SM LID_CLOSE#
GPP_B16/GSPI0_CLK GPP_D10 LID_CLOSE# <65>
AP8 P4 PAD_DISABLE_PCH R1033 1 2 0_0201_5%_SM PAD_DISABLE
GPP_B17/GSPI0_MISO GPP_D11 PAD_DISABLE <65>
GPP_B18 AR7 P1 TP_RESET_PCH R1034 1 2 0_0201_5%_SM TP_RESET
GPP_B18/GSPI0_MOSI GPP_D12 TP_RESET <65>
AM5 M4 DISCRETE_PRESENCE
AN7 GPP_B19/GSPI1_CS# GPP_D5/ISH_I2C0_SDA N3
BT_ON AP5 GPP_B20/GSPI1_CLK GPP_D6/ISH_I2C0_SCL
<63> BT_ON GPP_B21/GSPI1_MISO
GPP_B22 AN5 N1
GPP_B22/GSPI1_MOSI GPP_D7/ISH_I2C1_SDA N2
D_J_CTL AB1 GPP_D8/ISH_I2C1_SCL
<60> D_J_CTL GPP_C8/UART0_RXD
PLANARID1 AB2 AD11
C PLANARID2 W4 GPP_C9/UART0_TXD GPP_F10/I2C5_SDA/ISH_I2C2_SDA AD12 C
PLANARID3 AB3 GPP_C10/UART0_RTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL
GPP_C11/UART0_CTS#
UART2_RX AD1 U1
<52,63> UART2_RX GPP_C20/UART2_RXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA
UART2_TX AD2 U2
<52,63> UART2_TX GPP_C21/UART2_TXD GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL
PLANARID4 AD3 U3
TPNL_EN AD4 GPP_C22/UART2_RTS# GPP_D15/ISH_UART0_RTS# U4
FN, F1, F4 PD 100K, BIOS need output <60> TPNL_EN GPP_C23/UART2_CTS# GPP_D16/ISH_UART0_CTS#/SML0BALERT#
"High" while active
AC1
U7 GPP_C12/UART1_RXD/ISH_UART1_RXD AC2 F1_LED#
GPP_C16/I2C0_SDA GPP_C13/UART1_TXD/ISH_UART1_TXD F1_LED# <65>
VGA_ON U6 AC3 F4_LED#
<37,39> VGA_ON GPP_C17/I2C0_SCL GPP_C14/UART1_RTS#/ISH_UART1_RTS# F4_LED# <65>
AB4 GPP_C15
DGPU_PWROK U8 GPP_C15/UART1_CTS#/ISH_UART1_CTS#
<37> DGPU_PWROK GPP_C18/I2C1_SDA
To VGA_CORE IC, RPC3.7 DGPU_HOLD_RST# U9 AY8
<30> DGPU_HOLD_RST# GPP_C19/I2C1_SCL GPP_A18/ISH_GP0 BA8
AH9 GPP_A19/ISH_GP1 BB7
AH10 GPP_F4/I2C2_SDA GPP_A20/ISH_GP2 BA7
GPP_F5/I2C2_SCL GPP_A21/ISH_GP3 AY7
AH11 GPP_A22/ISH_GP4 AW7
AH12 GPP_F6/I2C3_SDA GPP_A23/ISH_GP5 AP13
GPP_F7/I2C3_SCL GPP_A12/BM_BUSY#/ISH_GP6
AF11 Project/SKU ID
AF12 GPP_F8/I2C4_SDA
GPP_F9/I2C4_SCL
PLANARID3 PLANARID2 PLANARID1 PLANARID4
SKYLAKE-U_BGA1356 REV = 1 6 OF 20 (GPP_C9) (GPP_22)
Vinafix.com SDV 0 0 DIS (R1023) 1 NTPM(R1031) 1
B
FVT 0 1 UMA (R1024) 0 TPM(R1030) 0 B
Vinafix SIT 1 0
1 1 +3VS
SVT
+3VS
1
1
1
R1019 R1021 R1023 DIS@ R1031 NTPM@
R1026 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5%

10K_0402_5%
2
2
2
1 @ 2 GPP_C15
PLANARID1
R1027 PLANARID2
10K_0402_5% PLANARID3
1 @ 2 F1_LED# PLANARID4
1
R1028
1
10K_0402_5% R1020 R1022 R1024 UMA@ R1030 TPM@
1 @ 2 F4_LED#
10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5%
@ @
2
A A

Issued Date 2015/01/12 Deciphered Date 2016/01/12 KBL(F)_GPIO
Size
Document Number
Number Rev
Rev
Custom 0.2
Date:
Sheet 10 of 99
5 4 3 2 1
5 4 3 2 1
+3VALW_PCH +3VALW_PCH <8,9,10,12,19>

GPP_B14, Internal PD 20K
+3VS +3VS <5,6,9,10,12,14,15,23,25,30,32,37,39,40,47,50,51,57,58,59,60,61,63,65,66,67,69,72,85,86> Processor Strapping No Reboot on TCO
+VCC_HDA +VCC_HDA <19> 543016_543016_SKL_PDG_UY_1_0_pub Timer expiration
+VCC_IO +VCC_IO <5,18,21,71>
P780 pull-up to VCC3_3 through a 1~8.2KΩ
resistor to disable this capability
+VCC_HDA +VCC_IO +3VS
1
R1102 R1104 R1106
D 1K_0402_5% 1K_0402_5% 8.2K_0402_5% D
RP1101 @ @ @
1 8
2
PCH_HDA_RST# 2 7 HDA_RST#
<50> PCH_HDA_RST#
PCH_HDA_SDOUT 3 6 HDA_SDOUT HDA_SDOUT PCH_HDA_SDIN0 PCH_BEEP
<50> PCH_HDA_SDOUT
PCH_HDA_SYNC 4 5 HDA_SYNC
<50> PCH_HDA_SYNC
1
33_0804_8P4R_5% R1103 R1105 R1107
SD30000370T 20K_0402_5% 20K_0402_5% 20K_0402_5%
@ @ @
R1101 1 2 0_0402_5%_SM
<40> ME_FLASH
2
PCH_HDA_BCLK R1110 1 EMC@ 2 33_0402_5% HDA_BCLK
<50> PCH_HDA_BCLK
1
C1101
22P_0402_50V8-J
EMC_NS@
2
+3VALW_PCH
WINDU and E470 can't stuff TBD
1
R1108
C 1K_0402_5% C
@
UC1G SKL_ULT
2
AUDIO
HDA_SYNC BA22
HDA_BCLK AY22 HDA_SYNC/I2S0_SFRM
HDA_SDOUT BB22 HDA_BLK/I2S0_SCLK
SDIO/SDXC
PCH_HDA_SDIN0 BA21 HDA_SDO/I2S0_TXD
<50> PCH_HDA_SDIN0 HDA_SDI0/I2S0_RXD
AY21 AB11
HDA_RST# AW22 HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD AB13
J5 HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0 AB12
AY20 GPP_D23/I2S_MCLK GPP_G2/SD_DATA1 W12
AW20 I2S1_SFRM GPP_G3/SD_DATA2 W11
I2S1_TXD GPP_G4/SD_DATA3 W10
AK7 GPP_G5/SD_CD# W8
AK6 GPP_F1/I2S2_SFRM GPP_G6/SD_CLK W7
AK9 GPP_F0/I2S2_SCLK GPP_G7/SD_WP
AK10 GPP_F2/I2S2_TXD BA9
GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7 BB9
GPP_A16/SD_1P8_SEL
H5 AB7 R1109 1 2 200_0402_1%
D7 GPP_D19/DMIC_CLK0 SD_RCOMP
GPP_D20/DMIC_DATA0
D8 AF13
C8 GPP_D17/DMIC_CLK1 GPP_F23
Vinafix.com GPP_D18/DMIC_DATA1
<51> PCH_BEEP PCH_BEEP AW5

GPP_B14/SPKR
B B
A A

Issued Date 2015/01/12 Deciphered Date 2016/01/12 KBL(G)_HDA/ GPIO
Size
Size Document
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number
Number Rev
Rev
Custom 0.2
Date:
Sheet 11 of 99
5 4 3 2 1
5 4 3 2 1
+3VALW_PCH
+3VALW_PCH +3VALW_PCH <8,9,10,11,19>

+3VS R1217
+3VS USB_OC0# 1 8
+3VS <5,6,9,10,11,14,15,23,25,30,32,37,39,40,47,50,51,57,58,59,60,61,63,65,66,67,69,72,85,86>
USB_OC1# 2 7
+3VALW +3VALW <6,9,15,19,40,50,58,60,63,65,66,67,72,83,84,91,95> USB_OC3# 3 6
SATA0_DEVSLP R1201 2 1 10K_0402_5% USB_OC2# 4 5
1
10K_0804_8P4R_5%
R1211 R1210 R1213 R1214
SSD_DEVSLP1 R1202 2 @ 1 10K_0201_5% 15K_0201_5% 15K_0201_5% 15K_0201_5% 15K_0201_5%
@ @ @ @
2
D D
SKL_ULT
UC1H
SSIC / USB3
PCIE/USB3/SATA
H8 USB3P1_RXN
USB3_1_RXN USB3P1_RXN <64>
G8 USB3P1_RXP
USB3_1_RXP USB3P1_RXP <64>
<30> PCIE_CRX_GTX_N0 PCIE_CRX_GTX_N0 H13 C13 USB3P1_TXN USB Port1(Left back AOU)
PCIE1_RXN/USB3_5_RXN USB3_1_TXN USB3P1_TXN <64>
<30> PCIE_CRX_GTX_P0 PCIE_CRX_GTX_P0 G13 D13 USB3P1_TXP
PCIE1_RXP/USB3_5_RXP USB3_1_TXP USB3P1_TXP <64>
C1201 DIS@ 1 2 0.22U_0201_6.3V6-K PCIE1_CTX_DRX_N0 B17
<30> PCIE_CTX_C_GRX_N0 PCIE1_TXN/USB3_5_TXN
C1202 DIS@ 1 2 0.22U_0201_6.3V6-K PCIE1_CTX_DRX_P0 A17 J6 USB3P2_RXN
<30> PCIE_CTX_C_GRX_P0 PCIE1_TXP/USB3_5_TXP USB3_2_RXN/SSIC_1_RXN USB3P2_RXN <42>
H6 USB3P2_RXP
USB3_2_RXP/SSIC_1_RXP USB3P2_RXP <42>
<30> PCIE_CRX_GTX_N1 PCIE_CRX_GTX_N1 G11 B13 USB3P2_TXN USB Port2 (TYPE-C)
PCIE2_RXN/USB3_6_RXN USB3_2_TXN/SSIC_1_TXN USB3P2_TXN <42>
<30> PCIE_CRX_GTX_P1 PCIE_CRX_GTX_P1 F11 A13 USB3P2_TXP
PCIE2_RXP/USB3_6_RXP USB3_2_TXP/SSIC_1_TXP USB3P2_TXP <42>
C1203 DIS@ 1 2 0.22U_0201_6.3V6-K PCIE2_CTX_DRX_N1 D16
<30> PCIE_CTX_C_GRX_N1 PCIE2_TXN/USB3_6_TXN
C1204 DIS@ 1 2 0.22U_0201_6.3V6-K PCIE2_CTX_DRX_P1 C16 J10
<30> PCIE_CTX_C_GRX_P1 PCIE2_TXP/USB3_6_TXP USB3_3_RXN/SSIC_2_RXN H10
GPU <30> PCIE_CRX_GTX_N2 PCIE_CRX_GTX_N2 H16
PCIE3_RXN
USB3_3_RXP/SSIC_2_RXP
USB3_3_TXN/SSIC_2_TXN
B15 USB Port3 (TYPE-C)
<30> PCIE_CRX_GTX_P2 PCIE_CRX_GTX_P2 G16 A15
C1205 DIS@ 1 2 0.22U_0201_6.3V6-K PCIE3_CTX_DRX_N2 D17 PCIE3_RXP USB3_3_TXP/SSIC_2_TXP
<30> PCIE_CTX_C_GRX_N2 PCIE3_TXN
C1206 DIS@ 1 2 0.22U_0201_6.3V6-K PCIE3_CTX_DRX_P2 C17 E10 USB3P4_RXN USB3P4_RXN <64>
<30> PCIE_CTX_C_GRX_P2 PCIE3_TXP USB3_4_RXN F10 USB3P4_RXP USB3P4_RXP <64>
PCIE_CRX_GTX_N3 G15 USB3_4_RXP C15 USB3P4_TXN
<30> PCIE_CRX_GTX_N3
F15 PCIE4_RXN USB3_4_TXN D15 USB3P4_TXP
USB3P4_TXN <64> USB Port4(Left Front)
<30> PCIE_CRX_GTX_P3 PCIE_CRX_GTX_P3 USB3P4_TXP <64>
C1207 DIS@ 1 2 0.22U_0201_6.3V6-K PCIE4_CTX_DRX_N3 B19 PCIE4_RXP USB3_4_TXP
<30> PCIE_CTX_C_GRX_N3 PCIE4_TXN
C1208 DIS@ 1 2 0.22U_0201_6.3V6-K PCIE4_CTX_DRX_P3 A19 AB9 USB20_N1
<30> PCIE_CTX_C_GRX_P3 PCIE4_TXP USB2N_1 USB20_N1 <64>
AB10 USB20_P1 USB20_P1 <64> USB Port1(Left back AOU)
PCIE5_CRX_DTX_N F16 USB2P_1
<67> PCIE5_CRX_DTX_N PCIE5_RXN
<67> PCIE5_CRX_DTX_P PCIE5_CRX_DTX_P E16 AD6 USB20_N2 USB20_N2 <42>
C1209 1 2 0.1U_0201_10V6-K PCIE5_CTX_DRX_N C19 PCIE5_RXP USB2N_2 AD7 USB20_P2
LAN <67> PCIE5_CTX_C_DRX_N
C1210 1 2 0.1U_0201_10V6-K D19 PCIE5_TXN USB2P_2 USB20_P2 <42> USB Port2 (TYPE-C)
<67> PCIE5_CTX_C_DRX_P PCIE5_CTX_DRX_P
PCIE5_TXP AH3 USB20_N3
C USB2N_3 USB20_N3 <64> C
G18 AJ3 USB20_P3 USB20_P3 <64> USB Port3 (Left Front)
F18 PCIE6_RXN USB2P_3
NC D20 PCIE6_RXP
PCIE6_TXN USB2N_4
AD9 USB20_N4 USB20_N4 <67>
C20 AD10 USB20_P4 USB20_P4 <67> USB Port4(IO/B)
PCIE6_TXP USB2P_4
PCIE7_SATA0_CRX_DTX_N F20 AJ1 USB20_N5
HDD <61>
<61>
PCIE7_SATA0_CRX_DTX_N
PCIE7_SATA0_CRX_DTX_P PCIE7_SATA0_CRX_DTX_P E20 PCIE7_RXN/SATA0_RXN
PCIE7_RXP/SATA0_RXP
USB2N_5
USB2P_5
AJ2 USB20_P5
USB20_N5
USB20_P5
<63>
<63> BT
<61> PCIE7_SATA0_CTX_DRX_N PCIE7_SATA0_CTX_DRX_N B21 USB2
PCIE7_SATA0_CTX_DRX_P A21 PCIE7_TXN/SATA0_TXN AF6 USB20_N6
<61> PCIE7_SATA0_CTX_DRX_P PCIE7_TXP/SATA0_TXP USB2N_6 USB20_N6 <60>
AF7 USB20_P6 USB20_P6 <60> CAMERA
G21 USB2P_6
F21 PCIE8_RXN/SATA1A_RXN AH1 USB20_N7
NC D21 PCIE8_RXP/SATA1A_RXP
PCIE8_TXN/SATA1A_TXN
USB2N_7
USB2P_7
AH2 USB20_P7
USB20_N7
USB20_P7
<60>
<60> Touch Panel
C21
PCIE8_TXP/SATA1A_TXP AF8 USB20_N8
USB2N_8 USB20_N8 <66>
<69> PCIE9_CRX_DTX_N PCIE9_CRX_DTX_N E22 AF9 USB20_P8 USB20_P8 <66> Finger Printer
PCIE9_CRX_DTX_P E23 PCIE9_RXN USB2P_8
<69> PCIE9_CRX_DTX_P PCIE9_RXP
<69> PCIE9_CTX_DRX_N PCIE9_CTX_DRX_N B23 AG1
PCIE9_CTX_DRX_P A23 PCIE9_TXN USB2N_9 AG2
<69> PCIE9_CTX_DRX_P PCIE9_TXP USB2P_9 NC
M.2 SSD <69> PCIE10_CRX_DTX_N PCIE10_CRX_DTX_N F25 AH7
PCIE10_CRX_DTX_P E25 PCIE10_RXN USB2N_10 AH8
<69> PCIE10_CRX_DTX_P PCIE10_RXP USB2P_10
<69> PCIE10_CTX_DRX_N PCIE10_CTX_DRX_N D23 NC
PCIE10_CTX_DRX_P C23 PCIE10_TXN AB6 R1218 1 2 113_0402_1% +3VALW
<69> PCIE10_CTX_DRX_P USBCOMP
PCIE10_TXP USB2_COMP AG3 R1215 1 @ 2 1K_0402_5%
R1208 1 2 100_0201_1% PCIE_RCOMP F5 USB2_ID AG4 R1216 1 @ 2 1K_0402_5%
E5 PCIE_RCOMPN USB2_VBUSSENSE
PCIE_RCOMPP A9 USB_OC0#
GPP_E9/USB2_OC0# USB_OC0# <64> (Left back AOU)
@ 1 XDP_PRDY_N D56 C9 USB_OC1# (TYPE-C)
TP3 PROC_PRDY# GPP_E10/USB2_OC1#
2
2
@ 1 XDP_PREQ_N D61 D9 USB_OC2# USB_OC2# <64> (Left Front)
TP4 PROC_PREQ# GPP_E11/USB2_OC2#
BB11 B9 USB_OC3# USB_OC3# <67> (IO/B) R1207 R1206
GPP_A7/PIRQA# GPP_E12/USB2_OC3#
B
10K_0201_5% 10K_0201_5% M2_CARD_DET B
<63> PCIE11_CRX_DTX_N PCIE11_CRX_DTX_N E28 J1 SATA0_DEVSLP SATA0_DEVSLP <61> @
PCIE11_CRX_DTX_P E27 PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0 J2 SSD_DEVSLP1
0 -W/CARD ==>GND
WLAN <63> PCIE11_CRX_DTX_P PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1 1 -W/O CARD ==>PU
1
1
<63> PCIE11_CTX_C_DRX_N C1213 1 2 0.1U_0201_10V6-K PCIE11_CTX_DRX_N D24 J3 1 @
C1214 1 2 0.1U_0201_10V6-K PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2 TP948
<63> PCIE11_CTX_C_DRX_P PCIE11_CTX_DRX_P C24
E30 PCIE11_TXP/SATA1B_TXP H2 1 @
<67> PCIE12_CRX_DTX_N PCIE12_CRX_DTX_N TP947
F30 PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0 H3 R1221 1 2 0_0201_5%_SM
<67> PCIE12_CRX_DTX_P PCIE12_CRX_DTX_P M2_CARD_DET_R M2_CARD_DET <69>
C1211 1 2 0.1U_0201_10V6-K A25 PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1 G4 R1222 1 2 0_0201_5%
PCIE12_CTX_DRX_N SSD_DET_PCH_R
Card Reader <67>
<67>
PCIE12_CTX_C_DRX_N
PCIE12_CTX_C_DRX_P C1212 1 2 0.1U_0201_10V6-K PCIE12_CTX_DRX_P B25 PCIE12_TXN/SATA2_TXN
PCIE12_TXP/SATA2_TXP
GPP_E2/SATAXPCIE2/SATAGP2 @
SSD_DET_PCH <69>
H1
GPP_E8/SATALED#
Vinafix.com
2
2
SSD_DET#
SKYLAKE-U_BGA1356 REV = 1 8 OF 20 R1219 R1220
10K_0201_5%
0- SATA
10K_0201_5%
@ @ 1- PCIE
1
1
A A

Issued Date 2015/01/12 Deciphered Date 2016/01/12 KBL(H)_PCIE/ SATA/ USB30
Size
DocumentNumber
Number Rev
Rev
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
!!"#$%&'()"*+ 0.2
Date:
Sheet 12 of 99
5 4 3 2 1
5 4 3 2 1
D D
SKL_ULT
UC1I
CSI-2
A36 C37
B36 CSI2_DN0 CSI2_CLKN0 D37
C38 CSI2_DP0 CSI2_CLKP0 C32
D38 CSI2_DN1 CSI2_CLKN1 D32
C36 CSI2_DP1 CSI2_CLKP1 C29
D36 CSI2_DN2 CSI2_CLKN2 D29
A38 CSI2_DP2 CSI2_CLKP2 B26
B38 CSI2_DN3 CSI2_CLKN3 A26
CSI2_DP3 CSI2_CLKP3
C31 E13
D31 CSI2_DN4 CSI2_COMP B7
C33 CSI2_DP4 GPP_D4/FLASHTRIG
D33 CSI2_DN5
C C
A31 CSI2_DP5 EMMC
B31 CSI2_DN6 AP2
A33 CSI2_DP6 GPP_F13/EMMC_DATA0 AP1
B33 CSI2_DN7 GPP_F14/EMMC_DATA1 AP3
CSI2_DP7 GPP_F15/EMMC_DATA2 AN3
A29 GPP_F16/EMMC_DATA3 AN1
B29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN2
C28 CSI2_DP8 GPP_F18/EMMC_DATA5 AM4
D28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM1
A27 CSI2_DP9 GPP_F20/EMMC_DATA7
B27 CSI2_DN10 AM2
C27 CSI2_DP10 GPP_F21/EMMC_RCLK AM3
D27 CSI2_DN11 GPP_F22/EMMC_CLK AP4 R1301
CSI2_DP11 GPP_F12/EMMC_CMD 200_0402_1%
AT1 1 2
EMMC_RCOMP
REV = 1 9 OF 20
B
Vinafix.com SKYLAKE-U_BGA1356
A A
Issued Date 2015/01/12 Deciphered Date 2016/01/12 KBL(I)_CS12/ EMMC

Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
A4 0.2
Date: Monday, October 30, 2017 Sheet 13 of 99
5 4 3 2 1
5 4 3 2 1
+RTCBATT +RTCBATT <66,80>
+RTCVCC +RTCVCC <15,19>
+3VS +3VS <5,6,9,10,11,12,15,23,25,30,32,37,39,40,47,50,51,57,58,59,60,61,63,65,66,67,69,72,85,86>

+3VS
+1VALW +1VALW <19,71,92>
1
R1406
10K_0402_5%
RTC External Circuit RTC Crystal UMA@
2
D
+RTCBATT, +RTCVCC 1. Space > 15mils CLKREQ_PCIE4_VGA# D
Trace width = 20mils 2. No trace under crystal
3. Place on oppsosit side of
1
MCP for temp influence
PCH_RTCX1 R1407
10K_0402_5%
+RTCBATT +RTCVCC R1404 DIS@
+RTCVCC 10M_0402_5%
2
R1402 JCMOS1 1 2 PCH_RTCX2
20K_0402_5% @
1 2 PCH_RTCRST# 1 2 YC3
R1401 1 2 0_0402_5%_SM 32.768KHZ_9PF_9H03280012
1 C1402 1 2 1U_0402_10V6-K 1 2
near CC59 for layout C1401 R1403 JME1
0.1U_0402_10V6-K 20K_0402_5% @ 1 1
2 1 2 PCH_SRTCRST# 1 2
C1404 C1405
C1403 1 2 1U_0402_10V6-K 6.8P_0201_25V8-C 6.8P_0201_25V8-C +3VS
2 2
RP1401
1 8 CLKREQ_PCIE2_WLAN#
2 7 CLKREQ_PCIE3_LAN#
3 6 CLKREQ_PCIE1_SSD#
4 5 CLKREQ_PCIE5_CR#
10K_0804_8P4R_5%
UC1J SKL_ULT
C C
CLOCK SIGNALS
D42
CLKOUT_PCIE_N0
HDD C42
CLKOUT_PCIE_P0
AR10
GPP_B5/SRCCLKREQ0#
CLK_PCIE_SSD# B42
<69> CLK_PCIE_SSD# CLKOUT_PCIE_N1
M.2 SSD<69> CLK_PCIE_SSD CLK_PCIE_SSD A42
CLKOUT_PCIE_P1 CLKOUT_ITPXDP_N
F43 CLKOUT_ITPXDP_N 1
T56
<69> CLKREQ_PCIE1_SSD# CLKREQ_PCIE1_SSD# AT7 E43 CLKOUT_ITPXDP_P 1
GPP_B6/SRCCLKREQ1# CLKOUT_ITPXDP_P T57
<63> CLK_PCIE_WLAN# CLK_PCIE_WLAN# D41

CLKOUT_PCIE_N2 GPD8/SUSCLK
BA17 SUSCLK_32K SUSCLK_32K <63> to WLAN
WLAN <63> CLK_PCIE_WLAN CLK_PCIE_WLAN C41
CLKOUT_PCIE_P2 +1VALW
<63> CLKREQ_PCIE2_WLAN# CLKREQ_PCIE2_WLAN# AT8 E37 PCH_XTAL24_IN
GPP_B7/SRCCLKREQ2# XTAL24_IN E35 PCH_XTAL24_OUT
CLK_PCIE_LAN# D40 XTAL24_OUT
<67> CLK_PCIE_LAN# CLKOUT_PCIE_N3
LAN <67> CLK_PCIE_LAN CLK_PCIE_LAN C40
CLKOUT_PCIE_P3 XCLK_BIASREF
E42 XCLK_BIASREF 1 2
<67> CLKREQ_PCIE3_LAN# CLKREQ_PCIE3_LAN# AT10
GPP_B8/SRCCLKREQ3# AM18 PCH_RTCX1 R1409
CLK_PCIE_VGA# B40 RTCX1 AM20 PCH_RTCX2 2.71K_0402_0.5%
<30> CLK_PCIE_VGA# CLKOUT_PCIE_N4 RTCX2
GPU <30> CLK_PCIE_VGA CLK_PCIE_VGA A40
CLKOUT_PCIE_P4
SD00001LB1T
<32> CLKREQ_PCIE4_VGA# CLKREQ_PCIE4_VGA# AU8 AN18 PCH_SRTCRST#
GPP_B9/SRCCLKREQ4# SRTCRST# AM16 PCH_RTCRST#
CLK_PCIE_CR# E40 RTCRST#
<67> CLK_PCIE_CR# CLKOUT_PCIE_N5
CR <67> CLK_PCIE_CR CLK_PCIE_CR E38
CLKOUT_PCIE_P5
<67> CLKREQ_PCIE5_CR# CLKREQ_PCIE5_CR# AU7
GPP_B10/SRCCLKREQ5#
B
Vinafix.com SKYLAKE-U_BGA1356 REV = 1 10 OF 20
PCH_XTAL24_IN
Need close CPU
EMC L1414 1
KBL@
For KBL-R U42 and KBL U22 control
SM01000JN0J
FOOTPRINT:R_0402
2 SBY100505T-300Y-N PCH_XTAL24_IN_R
R1412
B
1M_0201_5%
KBL@ KBL@
PCH_XTAL24_OUT EMC L1413 1 2 SBY100505T-300Y-N PCH_XTAL24_OUT_R 1 2
SM01000JN0J YC2 KBL@

24MHZ_10PF_8Y24000011
FOOTPRINT:R_0402
1 3
1 3
GND1 GND2
1 1
C1414 2 4 C1415
12P_0201_25V8-J 12P_0201_25V8-J
2 KBL@ 2 KBL@
A A

Issued Date 2015/01/12 Deciphered Date 2016/01/12 KBL(J)_RTC/ CLK
Size
Document Number
Number Rev
Rev
Custom 0.2
Date:
Sheet 14 of 99
5 4 3 2 1
5 4 3 2 1
+3VALW +3VALW <6,9,12,19,40,50,58,60,63,65,66,67,72,83,84,91,95>
+3VALW_PRIM +3VALW_PRIM <19>
+3VS +3VS <5,6,9,10,11,12,14,23,25,30,32,37,39,40,47,50,51,57,58,59,60,61,63,65,66,67,69,72,85,86>

Reserved for HW control
R1529 1 2 0_0402_5%_SM
+VCC_ST +VCC_ST <8,16,18,21,71,86>
+3VALW +3VS
D +3VALW +VCC_ST D
RP1501 R1528 1 2 20K_0402_1% GPP_A11
1 8 AC_PRESENT
2 7 BATLOW#
1
3 6 PCIE_WAKE#
4 5 R1513
R1505 1 @ 2 10K_0402_5% SYS_RESET# 1K_0402_5%
10K_0804_8P4R_5%
1
SD300002P0T
2
+3VALW For vPRO LAN WAKE# +3VALW_PRIM R1511 R1512 @
100K_0402_5% 100K_0402_5% VCCST_PWRGD
@
R1501 1 2 10K_0402_5% EC_WAKE#_DSW R1506 1 2 10K_0402_5%
3
D
@ R1509 1 @ 2 0_0402_5% 5 Q1501B
<40> VCCST_PG_EC G
R1507 1 2 10K_0402_5% EC_RSMRST# L2N7002KDW1T1G_SOT363-6
SB000013A00
6
R1502 1 @ 2 10K_0402_5% PM_SLP_S5# D S @
4
R1508 1 @ 2 10K_0201_5% H_CPUPWRGD R1510 1 @ 2 0_0402_5% 2 Q1501A
<40,47,71,72,85> SUSP G L2N7002KDW1T1G_SOT363-6
SB000013A00
S @
1
R1525 1 2 10K_0402_5% PCH_PWROK
R1526 1 @ 2 10K_0402_5% PCH_SYSPWROK
R1527 1 @ 2 10K_0402_5% AC_PRESENT
C PM_SLP_S3# 1 C
T1501
PM_SLP_S4# 1
UC1K SKL_ULT T1502
PM_SLP_S5# 1
T1503
SYSTEM POWER MANAGEMENT
AT11 PM_SLP_S0# 1
GPP_B12/SLP_S0# AP15 T1504
PM_SLP_S3# PM_SLP_S3# <40>
AN10 GPD4/SLP_S3# BA16 PM_SLP_S4#
PCH_PLT_RST# PM_SLP_S4# <40>
B5 GPP_B13/PLTRST# GPD5/SLP_S4# AY16 PM_SLP_S5#
SYS_RESET# PM_SLP_S5# <40>
AY17 SYS_RESET# GPD10/SLP_S5#
<40> EC_RSMRST# EC_RSMRST#
RSMRST# AN15 1
PCH_SLP_SUS#
A68 SLP_SUS# T1505
H_CPUPWRGD AW15
B65 PROCPWRGD SLP_LAN# BB17
VCCST_PWRGD R1519 1 2 60.4_0402_1%
VCCST_PWRGD GPD9/SLP_WLAN# AN16 1
PM_SLP_A#
B6 GPD6/SLP_A# T1506
<40> PCH_SYSPWROK PCH_SYSPWROK
R1515 1 2 0_0402_5%_SM BA20 SYS_PWROK BA15
<40> PCH_PWROK PWROK PBTN_OUT# PBTN_OUT# <40>
1 2 0_0402_5%_SM DSW_PWROK BB20 PCH_PWROK GPD3/PWRBTN# AY15
EC_RSMRST# R1520 AC_PRESENT AC_PRESENT <40>
DSW_PWROK GPD1/ACPRESENT AU13
<40,86> VGATE R1516 1 @ 2 0_0402_5% BATLOW#
AR13 GPD0/BATLOW#
R1521 1 2 0_0402_5%_SM SUSWARN#
AP11 GPP_A13/SUSWARN#/SUSPWRDNACK +RTCVCC
SUSACK#
GPP_A15/SUSACK# AU11 GPP_A11
BB15 GPP_A11/PME# AP16 R1522 1 2 1M_0402_5%
<63> PCIE_WAKE# PCIE_WAKE# PCH_INTRUDER#
AM15 WAKE# INTRUDER#
EC_WAKE#_DSW
AW17 GPD2/LAN_WAKE# AM10 EXT_PWR_GATE# 1
GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# T1508
AT15 AM11 VRALERT# 1
GPD7/RSVD GPP_B2/VRALERT# T1507
Vinafix.com SKYLAKE-U_BGA1356 REV = 1 11 OF 20

1. must be always pulled-up to VCCRTC.
2. 1 = Enable DSW 3.3V-to-1.05V Integrated DeepSx Well (DSW) On-Die Voltage Regulator.
This must always be pulled high on production boards.
B B
R1523 1 2 0_0402_5%_SM
+3VALW
U1501 @
1 5
NC VCC
PCH_PLT_RST# 2
IN_A
3 4 PLT_RST# PLT_RST# <30,40,58,63,67,69>
GND OUT_Y
1
R1524 TC7SG17FE_SON5
100K_0402_5%
1
2
C7214 1
0.1U_0402_16V7-K T1509
2
EMC_NS@
A A

Issued Date 2015/01/12 Deciphered Date 2016/01/12 KBL(K)_SYS PM
Size
Document Number
Number Rev
Rev
Custom 0.2
Date:
Sheet 15 of 99
5 4 3 2 1
5 4 3 2 1
+VCC_CORE +VCC_CORE <17,27,87,90>
+VCC_ST +VCC_ST <8,15,18,21,71,86>
D D
+VCC_ST [SKL PDG]VIDSCK

SKL_ULT
+VCC_CORE UC1L +VCC_CORE
CPU POWER 1 OF 4
1
A30 G32 R1605
A34 VCC_A30 VCC_G32 G33 100_0201_1%
A39 VCC_A34 VCC_G33 G35 @
A44 VCC_A39 VCC_G35 G37
VCC_A44 VCC_G37 Rpu1
2
AK33 G38
AK35 VCC_AK33 VCC_G38 G40
AK37 VCC_AK35 VCC_G40 G42 VR_SVID_CLK
VCC_AK37 VCC_G42 VR_SVID_CLK <86>
AK38 J30
AK40 VCC_AK38 VCC_J30 J33
AL33 VCC_AK40 VCC_J33 J37 +VCC_CORE
AL37 VCC_AL33 VCC_J37 J40
AL40 VCC_AL37 VCC_J40 K33
AM32 VCC_AL40 VCC_K33 K35
VCC_AM32 VCC_K35
1
AM33 K37 +VCC_ST [SKL PDG]VIDSOUT
AM35 VCC_AM33 VCC_K37 K38 R1603
AM37 VCC_AM35 VCC_K38 K40 100_0201_1%
VCC_AM37 VCC_K40
1
AM38 K42
G30 VCC_AM38 VCC_K42 K43 R1606
VCC_G30 VCC_K43
2
100_0201_1%
K32 E32 R1601 1 2 0_0201_5%_SM
RSVD_K32 VCC_SENSE VCC_SENSE <86>
VSS_SENSE
E33 R1602 1 2 0_0201_5%_SM
VSS_SENSE <86> Rpu2
2
AK32
RSVD_AK32 B63 VR_SVID_ALRT#_R
VIDALERT# +VCC_STG
1
C AB62 A63 VR_SVID_CLK VR_SVID_DAT C
VCCOPC_AB62 VIDSCK VR_SVID_DAT <86>
P62 D64 VR_SVID_DAT R1604
V62 VCCOPC_P62 VIDSOUT 100_0201_1%
VCCOPC_V62 G20
@ 1 H63 VCCSTG_G20
TP5 VCC_OPC_1P8_H63
2
@ 1 G61
TP6 VCC_OPC_1P8_G61
AC63 +VCC_ST [SKL PDG]VIDALERT#
AE63 VCCOPC_SENSE
VSSOPC_SENSE
1
AE62
VCCEOPIO_AE62 [SKL PDDG]Package Sensing Recommendations
AG62 R1607
VCCEOPIO_AG62
1.Trace Length Match: <25mil 56_0201_5%
AL63 2.Space: >25mil
VCCEOPIO_SENSE
AJ62
VSSEOPIO_SENSE 3.Trace impedance:50ohm R1608 Rpu1
2
220_0201_5%
4.Sense traces should be referenced to a solid ground plane Rs1
SKYLAKE-U_BGA1356 REV = 1 12 OF 20 5.Avoid crossing over plane splits VR_SVID_ALRT#_R 1 2 VR_SVID_ALRT#
VR_SVID_ALRT# <86>
[SKL PDG]SVID
1.Alert signal must be routed between Clk and Data signals to
minimize Cross-Talk.
B
Vinafix.com B
A A

Issued Date 2015/01/12 Deciphered Date 2016/01/12 KBL(L)_PW-VCCCORE
Size
Size Document
Number Rev
Rev
Custom 0.2
Date:
Sheet 16 of 99
5 4 3 2 1
5 4 3 2 1
+VCC_GT +VCC_GT <27,88,90>
+VCC_CORE +VCC_CORE <16,27,87,90>
+VCCCORE_GT2 +VCCCORE_GT2 <27>
+VCCCORE_GT1 +VCCCORE_GT1 <27>
D D
For KBL-R U42 and KBL U22 control
+VCC_CORE +VCCCORE_GT2
Vinafix.com
J1705
1 2 KBLR@
1 2
+VCC_GT JUMP_43X39
@
+VCC_GT
SKL_ULT
UC1M
J1706
1 2 KBL@ +VCCCORE_GT2 CPU POWER 2 OF 4
1 2 N70
C JUMP_43X39 A48 VCCGT_N70 N71 C
+VCC_GT A53 VCCGT_A48 VCCGT_N71 R63
@
A58 VCCGT_A53 VCCGT_R63 R64
A62 VCCGT_A58 VCCGT_R64 R65
+VCC_CORE +VCCCORE_GT1 A66 VCCGT_A62 VCCGT_R65 R66
AA63 VCCGT_A66 VCCGT_R66 R67
AA64 VCCGT_AA63 VCCGT_R67 R68
AA70 VCCGT_AA69 VCCGT_R71 T62
AA71 VCCGT_AA70 VCCGT_T62 U65
AC64 VCCGT_AA71 VCCGT_U65 U68
J1707
1 2 KBLR@ AC65 VCCGT_AC64 VCCGT_U68 U71
1 2 AC66 VCCGT_AC65 VCCGT_U71 W63
AC67 VCCGT_AC66 VCCGT_W63 W64
JUMP_43X39
@
+VCCCORE_GT2 AC71 VCCGT_AC70 VCCGT_W67 W68
J43 VCCGT_AC71 VCCGT_W68 W69
J45 VCCGT_J43 VCCGT_W69 W70
J46 VCCGT_J45 VCCGT_W70 W71
J48 VCCGT_J46 VCCGT_W71 Y62
J50 VCCGT_J48 VCCGT_Y62 +VCCCORE_GT1
+VCC_GT J52 VCCGT_J50
J53 VCCGT_J52 AK42
Vinafix.com J55 VCCGT_J53 VCCGTX_AK42 AK43
J56 VCCGT_J55 VCCGTX_AK43 AK45
J58 VCCGT_J56 VCCGTX_AK45 AK46
+VCCCORE_GT2 J60 VCCGT_J58 VCCGTX_AK46 AK48
K48 VCCGT_J60 VCCGTX_AK48 AK50
B +VCC_GT K50 VCCGT_K48 VCCGTX_AK50 AK52 B
K52 VCCGT_K50 VCCGTX_AK52 AK53
L62 VCCGT_K60 VCCGTX_AK70 AL43
L63 VCCGT_L62 VCCGTX_AL43 AL46
L68 VCCGT_L67 VCCGTX_AL60 AM48
+VCC_GT L69 VCCGT_L68 VCCGTX_AM48 AM50
L70 VCCGT_L69 VCCGTX_AM50 AM52
L71 VCCGT_L70 VCCGTX_AM52 AM53
M62 VCCGT_L71 VCCGTX_AM53 AM56
VCCGT_M62 VCCGTX_AM56
1
N63 AM58
N64 VCCGT_N63 VCCGTX_AM58 AU58
R1701
N66 VCCGT_N64 VCCGTX_AU58 AU63
100_0402_1%
N67 VCCGT_N66 VCCGTX_AU63 BB57
N69 VCCGT_N67 VCCGTX_BB57 BB66
VCCGT_N69 VCCGTX_BB66
2
<86> VCCGT_SENSE R1703 1 2 0_0402_5%_SM J70 AK62

J69 VCCGT_SENSE VCCGTX_SENSE AL61
<86> VSSGT_SENSE R1704 1 2 0_0402_5%_SM
VSSGT_SENSE VSSGTX_SENSE
1
R1702
100_0402_1%
A A
2

Issued Date 2015/01/12 Deciphered Date 2016/01/12 KBL(M)_PW-VCCGT
Size
Size Document
Number Rev
Rev
Custom 0.2
Date:
Sheet 17 of 99
5 4 3 2 1
5 4 3 2 1
+1.2V +1.2V <6,7,23,24,25,26,85> +VCC_STG +VCC_STG <8,16,71>
+VCC_IO +VCC_IO <5,11,21,71> +VCC_ST +VCC_ST <8,15,16,21,71,86>
+VCC_SA +VCC_SA <89,90>
D [KBL-R U4+2/KBL U2+2 ProcessoG]VCCSA D
[KBL-R U4+2/KBL U2+2 Processo]VDDQ BOTTOM [KBL-R U4+2/KBL U2+2 Processo]10uF x6

[KBL-R U4+2/KBL U2+2 Processo]10uF x4, 22uF x3 +VCC_SA
BOTTOM
+1.2V
1 1 1 1 1 1
1 1 1 1 1 1 1
C1803 C1802 C1805 C1804 C1806 C1807
C1830 C1832 C1808 C1827 C1828 C1829 C1831 10U_0402_6.3V6-M 10U_0402_6.3V6-M 10U_0402_6.3V6-M 10U_0402_6.3V6-M 10U_0402_6.3V6-M 10U_0402_6.3V6-M
10U_0402_6.3V6-M 10U_0402_6.3V6-M 10U_0402_6.3V6-M 10U_0402_6.3V6-M 22U_0603_6.3V6-M 22U_0603_6.3V6-M 22U_0603_6.3V6-M 2 2 2 2 2 2
2 2 2 2 2 2 2
[KBL-R U4+2/KBL U2+2 ProcessoG]VCCSA

[KBL-R U4+2/KBL U2+2 Processo]10uF x7, 1uF x7
+VCC_SA TOP
+VCC_SA
1 1 1 1 1 1 1 1 1 1 1 1 1 1
C1813 C1814 C1815 C1816 C1817 C1818 C1819 C1820 C1821 C1822 C1823 C1824 C1825 C1826
C 10U_0402_6.3V6-M 10U_0402_6.3V6-M 10U_0402_6.3V6-M 10U_0402_6.3V6-M 10U_0402_6.3V6-M 10U_0402_6.3V6-M 10U_0402_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M C
2 2 2 2 2 2 2 2 2 2 2 2 2 2
+VCC_SFR +VCC_SFROC +VCC_STG +VCC_ST +1.2V +1.2V +VCC_IO +VCC_SA

Power Rail Description Control
UC1N SKL_ULT
+VCC_IO
VCC Processor IA Cores Power Rail SVID
+VCC_SA
CPU POWER 3 OF 4
VccGT Processor Graphics Power Rails SVID
AU23 AK28
VDDQ_AU23 VCCIO_AK28
AU28
VDDQ_AU28 VCCIO_AK30
AK30 VccGTX Processor Graphics Extended Power Rail
1
1
AU35
VDDQ_AU35 VCCIO_AL30
AL30 SVID
AU42
VDDQ_AU42 VCCIO_AL42
AL42 R1801 R1803 Available only for GT3/GT4 processor SKUs
BB23 AM28 100_0201_1% 100_0201_1%
VDDQ_BB23 VCCIO_AM28
BB32
AM30 VccSA System Agent Power Rail SVID
BB41 AM42
2
2
BB47
VDDQ_BB47 VccIO IO Power Rail Fixed
BB51 AK23 VCCIO_SENSE VCCSA_SENSE
VDDQ_BB51 VCCSA_AK23
VCCSA_AK25
AK25 VSSIO_SENSE VSSSA_SENSE VccST Sustain Power Rail Fixed
G23
VCCSA_G23
1
1
Vinafix.com AM40
VDDQC VCCSA_G25
G25 VccPLL Processor PLLs power rail Fixed
G27 R1802 R1804
VCCSA_G27
A18
VCCST VCCSA_G28
G28 100_0201_1% 100_0201_1% VDDQ Integrated Memory Controller Power Rail Fixed
J22
VCCSA_J22
A22
VCCSTG_A22 VCCSA_J23
J23 VccOPC Processor OPC power rail (available only Fixed
2
2
B J27 B
AL23 VCCSA_J27 K23
in SKU’s with OPC)
VCCPLL_OC VCCSA_K23
VCCSA_K25
K25 VccOPC_1P8 Processor OPC power rail (available only Fixed
K20 K27
K21 VCCPLL_K20 VCCSA_K27 K28
VCCPLL_K21 VCCSA_K28
VCCSA_K30
K30 VccEOPIO Processor OPC power rail (available only Fixed
AM23 VCCIO_SENSE
VCCIO_SENSE AM22 VSSIO_SENSE
VSSIO_SENSE
H21 VSSSA_SENSE_L R1806 1 2 0_0201_5%_SM VSSSA_SENSE <86>
VSSSA_SENSE H20 VCCSA_SENSE_L R1807 1 2 0_0201_5%_SM
VCCSA_SENSE VCCSA_SENSE <86>
[SKL PDG]VCCSTG [SKL PDG]VCCST [SKL PDG]VCCPLL [SKL PDG]VDDQC [SKL PDG]VCCPLL [KBL-R U4+2/KBL U2+2 Processo]VCCIO
[SKL PDG]1uF x1 [SKL PDG]1uF x1
Primary side cap
[SKL PDG]1uF x1
Primary side cap
[SKL PDG]10uF x1 [SKL PDG]1uF x1
Primary side cap
[KBL-R U4+2/KBL U2+2 Processo]1uF x4
+VCC_SFROC +VCC_IO
+1.2V +1.2V
+VCC_STG +VCC_ST +VCC_ST +VCC_SFR
R1809
0_0603_5% BOTTOM
1 2
R1808
1 1 1 2 1 1 1 1 1 1
C1833 C1834 0_0402_5%_SM C1836 C1801 C1809 C1810 C1811 C1812
1
1U_0402_10V6K 1U_0402_10V6K 10U_0402_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M
2 2 2 2 2 2 2 2
C1835
A A
1U_0402_10V6K
2

Issued Date 2015/01/12 Deciphered Date 2016/01/12 KBL(N)_PW-VCCIO & VCCSA
Size
Document Number
Number Rev
Rev
Custom 0.2
Date:
Sheet 18 of 99
5 4 3 2 1
5 4 3 2 1
+1.2V +1.2V <6,7,18,23,24,25,26,85>
+1VALW_PCH +1VALW_PCH <21>
+3VALW_PCH +3VALW_PCH <8,9,10,11,12> +1VALW +1VALW <14,71,92>
+VCC_ST +VCC_ST <8,15,16,18,21,71,86> +VCC_STG +VCC_STG <8,16,18,71>
+3VALW_PRIM +3VALW_PRIM <15> +VCC_HDA +VCC_HDA <11>
+3VALW +3VALW <6,9,12,15,40,50,58,60,63,65,66,67,72,83,84,91,95> +3VALW_PCH

Near AG15 Near Y16 Near T16
1 1 1
D D
C1903 C1904 C1905
1U_0402_10V6K 1U_0402_10V6K 1U_0402_10V6K
2 2 2
+1VALW_PCH +VCC_MPHYGT +1VALW_1P0 +1VALW_PCH +1VALW_SUS +1VALW_SUS
SKL_ULT
UC1O
CPU POWER 4 OF 4
AB19
AB20 VCCPRIM_1P0_AB19 AK15
P18 VCCPRIM_1P0_AB20 VCCPGPPA AG15
VCCPRIM_1P0_P18 VCCPGPPB Y16
VCCPGPPC +1.8VALW_PCH
1
AF18 Y15 +1VALW_SUS +1VALW_PCH

R1901 R1902 AF19 VCCPRIM_CORE_AF18 VCCPGPPD T16
0_0603_5%_SM V20 VCCPRIM_CORE_AF19 VCCPGPPE AF16
0_0603_5%_SM VCCPRIM_CORE_V20 VCCPGPPF
V21 AD15
VCCPRIM_CORE_V21 VCCPGPPG +3VALW_PRIM
2
+DCPDSW AL1 V19

DCPDSW_1P0 VCCPRIM_3P3_V19
+1VALW_PCH K17 T1
L1 VCCMPHYAON_1P0_K17 VCCPRIM_1P0_T1 +1.8VALW_PCH
VCCMPHYAON_1P0_L1 AA1
+1VALW_1P0 N15 VCCATS_1P8 +3VALW_RTCPRIM
N16 VCCMPHYGT_1P0_N15 AK17
N17 VCCMPHYGT_1P0_N16 VCCRTCPRIM_3P3 +RTCVCC
P15 VCCMPHYGT_1P0_N17 AK19
P16 VCCMPHYGT_1P0_P15 VCCRTC_AK19 BB14 +1VALW +VCC_MPHYGT
VCCMPHYGT_1P0_P16 VCCRTC_BB14
+VCC_AMPHYPLL K15 BB10 +DCPRTC
L15 VCCAMPHYPLL_1P0_K15 DCPRTC R1903
VCCAMPHYPLL_1P0_L15 A14 1 2
+1VALW_PLL V15 VCCCLK1
VCCAPLL_1P0 K19 +1VALW_CLK2 R8013 1 2 0_0603_5% 0603 Footprint 0_0805_5%_SM
+VCC_HDA +1VALW_SUS AB17 VCCCLK2
Y18 VCCPRIM_1P0_AB17 L21
VCCPRIM_1P0_Y18 VCCCLK3
+VCC_DSW3P3 AD17 N20 +1VALW_CLK4 R8014 1 2 0_0603_5% 0603 Footprint
AD18 VCCDSW_3P3_AD17 VCCCLK4
AJ17 VCCDSW_3P3_AD18 L19 +1VALW_CLK5 R8015 1 2 0_0603_5%_SM 0603 Footprint
VCCDSW_3P3_AJ17 VCCCLK5
AJ19 A10
+3V_SPI VCCHDA VCCCLK6
1 1 AJ16 AN11 1 T58
+VCC_SRAM VCCSPI GPP_B0/CORE_VID0 AN13 1 T59
C1901 C1902 AF20 GPP_B1/CORE_VID1
C
0.1U_0402_10V6-K 0.1U_0402_10V6-K AF21 VCCSRAM_1P0_AF20 C
2 RF@ 2 RF@ T19 VCCSRAM_1P0_AF21
T20 VCCSRAM_1P0_T19
+3VALW_PRIM VCCSRAM_1P0_T20
AJ21
VCCPRIM_3P3_AJ21
[SKL PDG]The CORE_VID[0:1] signal is used by
LAYOUT near to CPU side +1VALW_SUS
external VRs to indicate the final settling
AK20
+VCC_PLLEBB VCCPRIM_1P0_AK20 voltage for VCCPRIM_CORE rail.
N18
VCCAPLLEBB
[SKL PDG]VccMPHYGT [SKL PDG]DcpDSW [SKL PDG]DcpRTC

[SKL PDG]1uF x1 [SKL PDG]Close AL1, [SKL PDG]Close BB10,
[SKL PDG]47uF x1 Placement type:Edge<3mm(118mil) Placement type:Edge<3mm(118mil)
[SKL PDG]VccSRAM [SKL PDG]Close N15, [SKL PDG]1uF x1 [SKL PDG]0.1uF x1
[SKL PDG]Close AF20, Placement type:Edge<3mm(118mil) Deep Sx Well 1.0 V: This rail is generated by on die DSW RTC de-coupling capacitor only.
Placement type:Edge<10mm(394mil) [SKL PDG]VccAPLLEBB [SKL PDG]Close N15, low dropout (LDO) linear voltage regulator to supply DSW This rail should NOT be driven.
[SKL PDG]1uF x1 [SKL PDG]Close N18, Placement type:Edge<10mm(394mil) GPIOs, DSW core logic and DSW USB2 logic. Board needs to
SRAM Primary Well 1.0 V. Dedicated SRAM rail and can Placement type:Edge<3mm(118mil) VccMPHYGT(Mod PHY Externally Gated Primary 1.0 V: Externally gated connect 1 uF capacitor to this rail and power should NOT
have on board power down gate control. [SKL PDG]1uF x1 primary supply for PCIe/DMI/USB3/SATA/MIPI MPHY logic.) be driven from the board. When primary well power is up,
+VCC_MPHYGT +VCC_PLLEBB +VCC_MPHYGT +1VALW_1P0 this rail is bypassed from VCCPRIM_1p0.
+VCC_MPHYGT +VCC_SRAM +DCPDSW +DCPRTC
R1907 1
R1906 1 2 0_0402_5%_SM 1 2 1
0_0603_5%_SM 1 2 R1905 1 C1909
1
0_0805_5%_SM 1U_0402_10V6K C1910
C1907 C1908 2 0.1U_0402_10V6-K
1 1 2
1U_0402_10V6K 47U_0805_6.3V6-M
2
C1906 CC52 2 @
1U_0402_10V6K
2@ 2
1U_0402_10V6K close to N15
[SKL PDG]VccMPHYAON
[SKL PDG]Close K17,
+VCC_AMPHYPLL
1
C1911
1U_0402_10V6K
Vinafix.com
Placement type:Edge<3mm(118mil)
[SKL PDG]1uF x1
Mod PHY Always On Primary 1.0 V: Always on primary
supply for PCIe/DMI/USB3/SATA/MIPI MPHY logic
+1VALW_PCH
1
C1912
1U_0402_10V6K
[SKL PDG]VccATS
[SKL PDG]Close AA1,
[SKL PDG]1uF x1
Thermal Sensor Primary Well 1.8 V
+1.8VALW_PCH
1
C1913
1U_0402_10V6K
[SKL PDG]VCCPRIM
[SKL PDG]Close AB19,
[SKL PDG]1uF x1
Primary Well 1.0 V: For I/O blocks, ungated ISH SRAM
power, USB AFE Digital Logic, JTAG, Thermal Sensor and
MIPI DPHY.
+1VALW_PCH
1
R1908
0_0402_5%
@ 2
+1VALW_SUS
1
[SKL PDG]VccRTCPRIM
[SKL PDG]Close AK17,
[SKL PDG]1uF x1,0.1uF x2
RTC Logic Primary Well 3.3 V. This
power supplies the RTC internal VRM.
It will be off during Deep Sx mode.
+3VALW_PCH
1
R1909
0_0402_5%_SM
+3VALW_RTCPRIM
2
1
C1915
1
C1916
1
C1917
[SKL PDG]VccRTC
[SKL PDG]Close AK19,
[SKL PDG]1uF x1
RTC Logic Primary Well 3.3 V.
This power supplies the RTC
internal VRM. It will be off
during Deep Sx mode.
+RTCVCC
1
C1918
B
2@ 2 2 C1914 1U_0402_10V6K 0.1U_0402_10V6-K 0.1U_0402_10V6-K 1U_0402_10V6K

1U_0402_10V6K 2 2 2 2
2
[SKL PDG]VccHDA
+1VALW +1VALW_SUS [SKL PDG]Close AJ19, [SKL PDG]VccPRIM_Core
J11 @ Placement type:Edge<10mm(394mil) [SKL PDG]Close AF18, [SKL PDG]VCCPRIM
1 2 [SKL PDG]1uF x1 Placement type:Edge<10mm(394mil) [SKL PDG]Close V19,
1 2 HD Audio Power 3.3 V, 1.8 V, 1.5 V. For Intel High [SKL PDG]1uF x1 Placement type:Edge<3mm(118mil)
JUMP_43X118 Definition Audio. Core Logic Primary Well: This rail [SKL PDG]1uF x1
scales from 0.85 V to 1.0 V. Primary Well 3.3 V
[SKL PDG]VccDSW Reserve for Sense Resistor
Deep Sx Well for GPD GPIOs and USB2 +3VALW_PCH +1.8VALW_PCH +VCC_HDA +1VALW_PCH +1VALW_SUS +3VALW_PCH +3VALW_PRIM
R1917
+1.8VALW +1.8VALW_PCH 0_0402_5%
+3VL +VCC_DSW3P3 1 @ 2 R1918 1 2 0_0402_5%_SM
R1915
R1910 R1912 1 2 0_0402_5%_SM 0_0402_5%
0_0402_5% 1 @ 2 1
A 1 A
1 @ 2
+3VALW +3VALW_PCH C1920 C1921
1U_0402_10V6K 1U_0402_10V6K
+3VALW_PCH R1913 1 2 0_0402_5%_SM R1916 1 2 0_0402_5%_SM 2 2
1
+1VALW R1914 +1VALW_PCH C1919
R1911 1 2 0_0402_5%_SM 0_0805_5% 0.1U_0402_10V6-K
1 2 2

Issued Date 2015/01/12 Deciphered Date 2016/01/12 KBL(O)_PW-OTHERS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize
Size Document
DocumentNumber
Document Number
Number Rev
Rev
Rev
Custom
Custom !!"#$%&'()"*+ 0.2
0.2
Date:
Date: Monday,
Monday, October
October 30,
30, 2017
2017 Sheet
Sheet
Sheet 19
19 of 99
99
5 4 3 2 1
5 4 3 2 1
SKL_ULT UC1Q
SKL_ULT UC1P GND 2 OF 3
GND 1 OF 3 AT63 BA49

AT68 VSS_AT63 VSS_BA49 BA53
@ TP949 1 A5 AL65 AT71 VSS_AT68 VSS_BA53 BA57
@ TP950 1 A67 VSS_A5 VSS_AL65 AL66 AU10 VSS_AT71 VSS_BA57 BA6
D @ TP951 1 A70 VSS_A67 VSS_AL66 AM13 AU15 VSS_AU10 VSS_BA6 BA62 D
AA2 VSS_A70 VSS_AM13 AM21 AU20 VSS_AU15 VSS_BA62 BA66
AA4 VSS_AA2 VSS_AM21 AM25 AU32 VSS_AU20 VSS_BA66 BA71 1 TP957 @
AA65 VSS_AA4 VSS_AM25 AM27 AU38 VSS_AU32 VSS_BA71 BB18
AA68 VSS_AA65 VSS_AM27 AM43 @ TP952 1 AV1 VSS_AU38 VSS_BB18 BB26
AB15 VSS_AA68 VSS_AM43 AM45 AV68 VSS_AV1 VSS_BB26 BB30
AB16 VSS_AB15 VSS_AM45 AM46 AV69 VSS_AV68 VSS_BB30 BB34
AB8 VSS_AB21 VSS_AM60 AM61 AW10 VSS_AV71 VSS_BB43 BB55
AD13 VSS_AB8 VSS_AM61 AM68 AW12 VSS_AW10 VSS_BB55 BB6
AD16 VSS_AD13 VSS_AM68 AM71 AW14 VSS_AW12 VSS_BB6 BB60
AD19 VSS_AD16 VSS_AM71 AM8 AW16 VSS_AW14 VSS_BB60 BB64
AD20 VSS_AD19 VSS_AM8 AN20 AW18 VSS_AW16 VSS_BB64 BB67 1 TP958 @
AD21 VSS_AD20 VSS_AN20 AN23 AW21 VSS_AW18 VSS_BB67 BB70 1 TP959 @
AD62 VSS_AD21 VSS_AN23 AN28 AW23 VSS_AW21 VSS_BB70 C1 1 TP960 @
AD8 VSS_AD62 VSS_AN28 AN30 AW26 VSS_AW23 VSS_C1 C25
AE64 VSS_AD8 VSS_AN30 AW28 VSS_AW26 VSS_C25 C5
AN32
AE65 VSS_AE64 VSS_AN32 AW30 VSS_AW28 VSS_C5 D10
AN33
AE66 VSS_AE65 VSS_AN33 AW32 VSS_AW30 VSS_D10 D11
AN35
AN37
AE68 VSS_AE67 VSS_AN37 AW36 VSS_AW34 VSS_D14 D18 SKL_ULT
AN38 UC1R
AN40
AF1 VSS_AE69 VSS_AN40 AW41 VSS_AW38 VSS_D22 D25
AN42 GND 3 OF 3
AF10 VSS_AF1 VSS_AN42 AW43 VSS_AW41 VSS_D25 D26
AN58 F8 L18
AF15 VSS_AF10 VSS_AN58 AW45 VSS_AW43 VSS_D26 D30 VSS_F8 VSS_L18
AN63 G10 L2
AF17 VSS_AF15 VSS_AN63 AW47 VSS_AW45 VSS_D30 D34 VSS_G10 VSS_L2
AP10 G22 L20
VSS_AF17 VSS_AP10 AW49 VSS_AW47 VSS_D34 D39 VSS_G22 VSS_L20
AF2 AP18 G43 L4
AF4 AP20 G45 L8
AF63 AP23 G48 N10
VSS_AF63 VSS_AP23 AW55 VSS_AW53 VSS_D45 D47 VSS_G48 VSS_N10
AG16 AP28 G5 N13
AG17 VSS_AG16 VSS_AP28 AW57 VSS_AW55 VSS_D47 D48 VSS_G5 VSS_N13
AP32 G52 N19
C VSS_AG17 VSS_AP32 AW6 VSS_AW57 VSS_D48 D53 VSS_G52 VSS_N19 C
AG18 AP35 G55 N21
VSS_AG18 VSS_AP35 AW60 VSS_AW6 VSS_D53 D58 VSS_G55 VSS_N21
AG19 AP38 G58 N6
AG20 AP42 G6 N65
AG21 AP58 G60 N68
AG71 AP63 G63 P17
VSS_AG71 VSS_AP63 AW8 VSS_AW66 VSS_D66 D69 VSS_G63 VSS_P17
AH13 AP68 G66 P19
VSS_AH13 VSS_AP68 AY66 VSS_AW8 VSS_D69 E11 VSS_G66 VSS_P19
AH6 AP70 H15 P20
VSS_AH6 VSS_AP70 B10 VSS_AY66 VSS_E11 E15 VSS_H15 VSS_P20
AH63 AR11 H18 P21
VSS_AH63 VSS_AR11 B14 VSS_B10 VSS_E15 E18 VSS_H18 VSS_P21
AH64 AR15 H71 R13
VSS_AH64 VSS_AR15 B18 VSS_B14 VSS_E18 E21 VSS_H71 VSS_R13
AH67 AR16 J11 R6
VSS_AH67 VSS_AR16 B22 VSS_B18 VSS_E21 E46 VSS_J11 VSS_R6
AJ15 AR20 J13 T15
VSS_AJ15 VSS_AR20 B30 VSS_B22 VSS_E46 E50 VSS_J13 VSS_T15
AJ18 AR23 J25 T17
AJ20 AR28 J28 T18
AJ4 AR35 J32 T2
AK11 AR42 J35 T21
VSS_AK11 VSS_AR42 B48 VSS_B44 VSS_E6 E65 VSS_J35 VSS_T21
AK16 AR43 J38 T4
VSS_AK16 VSS_AR43 B53 VSS_B48 VSS_E65 E71 1 TP961 @ VSS_J38 VSS_T4
AK18 AR45 J42 U10
VSS_AK18 VSS_AR45 B58 VSS_B53 VSS_E71 F1 VSS_J42 VSS_U10
AK21 AR46 J8 U63
VSS_AK21 VSS_AR46 B62 VSS_B58 VSS_F1 F13 VSS_J8 VSS_U63
AK22 AR48 K16 U64
VSS_AK22 VSS_AR48 B66 VSS_B62 VSS_F13 F2 VSS_K16 VSS_U64
AK27 AR5 K18 U66
VSS_AK27 VSS_AR5 @ TP954 1 B71 VSS_B66 VSS_F2 F22 VSS_K18 VSS_U66
AK63 AR50 K22 U67
VSS_AK63 VSS_AR50 BA1 VSS_B71 VSS_F22 F23 VSS_K22 VSS_U67
AK68 AR52 @ TP955 1 K61 U69
VSS_AK68 VSS_AR52 BA10 VSS_BA1 VSS_F23 F27 VSS_K61 VSS_U69
AK69 AR53 K63 U70
VSS_AK69 VSS_AR53 BA14 VSS_BA10 VSS_F27 F28 VSS_K63 VSS_U70
AK8 AR55 K64 V16
VSS_AK8 VSS_AR55 BA18 VSS_BA14 VSS_F28 F32 VSS_K64 VSS_V16
AL2 AR58 K65 V17
VSS_AL2 VSS_AR58 BA2 VSS_BA18 VSS_F32 F33 VSS_K65 VSS_V17
AL28 AR63 K66 V18
VSS_AL28 VSS_AR63 BA23 VSS_BA2 VSS_F33 F35 VSS_K66 VSS_V18
AL32 AR8 K67 W13
VSS_AL32 VSS_AR8 BA28 VSS_BA23 VSS_F35 VSS_K67 VSS_W13
Vinafix.com AL35 AT2 F37 K68 W6
VSS_AL35 VSS_AT2 BA32 VSS_BA28 VSS_F37 VSS_K68 VSS_W6
AL38 AT20 F38 K70 W9
VSS_AL38 VSS_AT20 BA36 VSS_BA32 VSS_F38 F4 VSS_K70 VSS_W9
AL4 AT23 K71 Y17
VSS_AL4 VSS_AT23 VSS_BA36 VSS_F4 VSS_K71 VSS_Y17
AL45 AT28 F68 F40 L11 Y19
AL48 VSS_AL45 VSS_AT28 AT35 BA45 VSS_F68 VSS_F40 F42 VSS_L11 VSS_Y19
L16 Y20
B VSS_AL48 VSS_AT35 VSS_BA45 VSS_F42 BA41 VSS_L16 VSS_Y20 B
AL52 AT4 L17 Y21
VSS_AL52 VSS_AT4 VSS_BA41 VSS_L17 VSS_Y21
AL55 AT42
AL58 VSS_AL55 VSS_AT42 AT56
AL64 VSS_AL58 VSS_AT56 AT58
VSS_AL64 VSS_AT58
SKYLAKE-U_BGA1356 SKYLAKE-U_BGA1356
REV = 1 17 OF 20 REV = 1 18 OF 20
SKYLAKE-U_BGA1356
REV = 1 16 OF 20
A A

Issued Date 2015/01/12 Deciphered Date 2016/01/12 KBL(P/Q/R)_VSS
Size
Size Document
Number Rev
Rev
Custom 0.2
Date:
Date: Monday, October 30,
30, 2017
2017 Sheet
Sheet 20 of 99
5 4 3 2 1
5 4 3 2 1
+VCC_ST +VCC_ST <8,15,16,18,71,86>
+1VALW_PCH +1VALW_PCH <19>
+VCC_IO +VCC_IO <5,11,18,71>
+VCC_IO +VCC_IO
CFG4
CFG0 *L: Embedded DisplayPort Enabled
[SKL EDS] H: Embedded DisplayPort Disabled
1
1
R2101 L:Stall.
D 1K_0402_5% R2103 D
*H:(Default) Normal
@ 1K_0402_5%
Operation; No stall. @
2
2
CFG0 CFG4
1
1
R2102 R2104
1K_0402_1% 1K_0402_1%
@
2
SKL_ULT
UC1S
RESERVED SIGNALS-1
CFG0 E68 BB68 1 TP37 @

TABLE
B67 CFG[0] RSVD_TP_BB68 BB69 1 TP39 @
CFG[1] RSVD_TP_BB69
D65
D67 CFG[2] AK13 1 TP43 @
CFG0 : Stall Reset Sequence
C CFG4 E70 CFG[3]
CFG[4]
RSVD_TP_AK13
RSVD_TP_AK12
AK12 1 TP45 @ after PCU PLL Lock until de-asserted C
C68
D68 CFG[5] BB2 1 TP49 @ 1 : No Stall
C67 CFG[6]
CFG[7]
RSVD_BB2
RSVD_BA3
BA3 1 TP51 @ 0 : Stall
[SKL CRB] F71
CFG[8]
G69
CFG[9]
[SKL PDG]Route F70
CFG[10] TP5
AU5 1 TP59 @
HOOK[6] to G68
H70 CFG[11] TP6
AT5 1 TP60 @ CFG4 : eDP Enable
Skylake G71 CFG[12] 1 : Disabled
ITP_PMODE. H69 CFG[13] D5 1 TP22 @
Termination: G70 CFG[14] RSVD_D5 D4 1 TP23 @ 0 : Enabled
CFG[15] RSVD_D4
Resistor value RSVD_B2
B2 1 TP25 @
from 1K ohm to 3K E63 C2 1 TP27 @
CFG[16] RSVD_C2
ohm pull up to F63
CFG[17] B3 1 TP64 @
CFG9 : SVID Bus Communication
PCH_V1.0A Rail. E66
CFG[18]
RSVD_B3
RSVD_A3
A3 1 TP66 @ 1 : Enabled
F66
+1VALW_PCH CFG[19] AW1 1 TP29 @
0 : Disabled
R2105 2 1 49.9_0402_1% CFG_RCOMP E60 RSVD_AW1
CFG_RCOMP E1 1 TP31 @
RSVD_E1
R2106 2 1 1.5K_0402_5% ITP_PMODE E8
ITP_PMODE RSVD_E2
E2 1 TP33 @ [SKL EDS]Zero Voltage Mode:VCCOPC is fixed OPC VR output voltage of 1V, the
processor can drive VR to LPM (Low Power Mode) which sets VR output to 0V using
@ TP24 1 AY2 BA4 1 TP34 @
@ TP26 1 AY1 RSVD_AY2 RSVD_BA4 BB4 1 TP35 @ ZVM# signal as shown below:
RSVD_AY1 RSVD_BB4
@ TP74 1 D1 A4 1 TP67 @
RSVD_D1 RSVD_A4
Vinafix.com @ TP30 1 D3
RSVD_D3 RSVD_C4
C4 1 TP68 @ ZVM# state VCCOPC
@ TP86 1 K46 BB5 1 TP54 @
RSVD_K46 TP4
@ TP85 1 K45
RSVD_K45
0V 0V
A69 1 TP927 @
B @ TP88 1 AL25 RSVD_A69 B69 B
1 TP928 @
RSVD_AL25 RSVD_B69
@ TP87 1 AL27
RSVD_AL27
1V 1V
AY3 R2107 1 2 0_0402_5%_SM
@ TP90 1 C71 RSVD_AY3
RSVD_C71
@ TP89 1 B70
RSVD_B70 RSVD_D71
D71 1 TP929 @ [SKL EDS]Minimum Speed Mode: VCCEOPIO can be connected to OPC VR in this
C70 1 TP930 @ case VCCEOPIO is fixed to 1V. The processor can drive VR to LPM (Low Power
F60 RSVD_C70
@ TP32 1 Mode) which sets VR output to 0V using ZVM# signal .
RSVD_F60 C54 1 TP931 @
@ TP91 1 A52 RSVD_C54 D54 1 TP932 @ In order to achieve better power/performance it is recommended to use a
RSVD_A52 RSVD_D54 +VCC_ST separate VR for VCCEOPIO in this case VCCEOPIO is configurable to 0.8V/1V.
@ TP92 1 BA70
RSVD_TP_BA70 TP1
AY4 1 TP933 @ The processor drives the VR to set VCCEOPIO value(0.8V/1V) using MSM#
@ TP93 1 BA68 BB3 1 TP934 @ signal, based on the required bandwidth for the EOPIO interface as shown
RSVD_TP_BA68 TP2
@ TP94 1 J71 AY71 R2108 1 2 0_0402_5%_SM
below:
@ TP95 1 J68 RSVD_J71 VSS_AY71
AR56 1 TP935 @
RSVD_J68 ZVM#
F65 AW71 1 TP936 @
VSS_F65 RSVD_TP_AW71
G65
VSS_G65 RSVD_TP_AW70
AW70 1 TP937 @ ZVM# state MSM# state VCCEOPIO
R2109
@ TP96 1 F61 AP56 1 TP938 @ 100K_0201_1%
RSVD_F61 MSM#
@ TP97 1 E61
RSVD_E61 PROC_SELECT#
C64 2 1 0V X 0V
1V 0V 0.8V
1V 1V 1V
A A

Issued Date 2015/01/12 Deciphered Date 2016/01/12 KBL(S)_CFG/ RSVD
Size
Document Number
Number Rev
Rev
Custom 0.2
Date:
Sheet 21 of 99
5 4 3 2 1
5 4 3 2 1
Need close CPU For KBL-R U42 and KBL U22 control
D D
KBLR@
PCH_XTAL24_IN_NEW EMC L2202 1 2 SBY100505T-300Y-N PCH_XTAL24_IN_NEW_R
SM01000JN0J
FOOTPRINT:R_0402 R2808
1M_0201_5%
KBLR@ KBLR@
PCH_XTAL24_OUT_NEW EMC L2203 1 2 SBY100505T-300Y-N PCH_XTAL24_OUT_NEW_R 1 2
SM01000JN0J YC1 KBLR@

24MHZ_10PF_8Y24000011
FOOTPRINT:R_0402
1 3
1 3
GND1 GND2
1 1
C2801 2 4 C2802
12P_0201_25V8-J 12P_0201_25V8-J
2 KBLR@ 2 KBLR@
C C
Vinafix.com
B B
UC1T SKL_ULT
Vinafix.com
@
@
@
@
@
@
@
TP98
TP99
TP100
TP101
TP103
TP104
TP105
1
1
1
1
1
1
1
PCH_XTAL24_OUT_NEW
AW69
AW68
AU56
AW48
C7
U12
U11
H11
RSVD_AW69
RSVD_AW68
RSVD_AU56
RSVD_AW48
RSVD_C7
RSVD_U12
RSVD_U11
RSVD_H11
SPARE
RSVD_F6
RSVD_E3
RSVD_C11
RSVD_B11
RSVD_A11
RSVD_D12
RSVD_C12
RSVD_F52
F6
E3
C11
B11
A11
D12
C12
F52
PCH_XTAL24_IN_NEW
1
1
1
1
1
1
1
TP106
TP108
TP109
TP110
TP111
TP112
TP113
@
@
@
@
@
@
@
SKYLAKE-U_BGA1356
REV = 1 20 OF 20
A A
Issued Date 2015/01/12 Deciphered Date 2016/01/12 KBL(T)_RSVD

Size
B 0.2
0.2
30, 2017
2017 Sheet 22 of 99
99
5 4 3 2 1
5 4 3 2 1
+3VS +3VS <5,6,9,10,11,12,14,15,25,30,32,37,39,40,47,50,51,57,58,59,60,61,63,65,66,67,69,72,85,86> <6,7> M_A_DQ[63:0]
+2.5V +2.5V <6,24,25,26,94> <6,7> -M_A_DQS[7:0]
+1.2V +1.2V <6,7,18,24,25,26,85> <6,7> M_A_DQS[7:0]
+0.6VS +0.6VS <24,25,26,85> <6> M_A_A[16:0]
+1.2V
+2.5V +1.2V +1.2V +0.6VS
+1.2V +1.2V
2
+1.2V
R2301
D JDIMM1B 240_0402_1% D
JDIMM1A
1
M_A_A3 131 132 M_A_A2
133 A3 A2 134 EVENT_n_1
M_A_A1
1 2 135 A1 EVENT_n/NF 136
M_A_DQ1 3 VSS_1 VSS_2 4 137 VDD_9 VDD_10 138
M_A_DQ4 <6> M_A_DDRCLK0_1066M M_A_DDRCLK0_1066M M_A_DDRCLK1_1066M M_A_DDRCLK1_1066M <6>
5 DQ5 DQ4 6 139 CK0_t CK1_t/NF 140
<6> -M_A_DDRCLK0_1066M -M_A_DDRCLK0_1066M -M_A_DDRCLK1_1066M -M_A_DDRCLK1_1066M <6>
M_A_DQ0 7 VSS_3 VSS_4 8 141 CK0_c CK1_c/NF 142
M_A_DQ5
9 DQ1 DQ0 10 143 VDD_11 VDD_12 144
<6> M_A_PARITY M_A_PARITY M_A_A0
-M_A_DQS0 11 VSS_5 VSS_6 12 Parity A0
M_A_DQS0 13 DQS0_C DM0_n/DBl0_n 14
15 DQS0_t VSS_7 16 M_A_DQ3 M_A_BS1 145 146
<6> M_A_BS1 M_A_A10
17 VSS_8 DQ6 18 147 BA1 A10/AP 148
M_A_DQ6
19 DQ7 VSS_9 20 149 VDD_13 VDD_14 150
M_A_DQ7 <6> -M_A_CS0 -M_A_CS0 M_A_BS0 M_A_BS0 <6>
21 VSS_10 DQ2 22 151 CS0_n BA0 152
M_A_DQ2 M_A_A14 M_A_A16
23 DQ3 VSS_11 24 153 A14/WE_n A16/RAS_n 154
M_A_DQ29
25 VSS_12 DQ12 26 155 VDD_15 VDD_16 156
M_A_DQ24 <6> M_A_ODT0 M_A_ODT0 M_A_A15
27 DQ13 VSS_13 28 157 ODT0 A15/CAS_n 158
M_A_DQ28 <6> -M_A_CS1 -M_A_CS1 M_A_A13
29 VSS_14 DQ8 30 159 CS1_n A13 160
M_A_DQ25
31 DQ9 VSS_15 32 161 VDD_17 VDD_18 162
-M_A_DQS3 <6> M_A_ODT1 M_A_ODT1
33 VSS_16 DQS1_c 34 163 ODT1 C0/CS2_n/NC 164
M_A_DQS3 M_VREF_CA_DIMMA
35 DM1_n/DBl_n DQS1_t 36 165 VDD_19 VREFCA 166 SA2_CHA_P
37 VSS_17 VSS_18 38 167 C1/CS3_n/NC SA2 168
M_A_DQ26 M_A_DQ27
39 DQ15 DQ14 40 169 VSS_53 VSS_54 170
M_A_DQ48 M_A_DQ51
41 VSS_19 VSS_20 42 171 DQ37 DQ36 172 +1.2V
M_A_DQ31 M_A_DQ30
43 DQ10 DQ11 44 173 VSS_55 VSS_56 174
M_A_DQ49 M_A_DQ52
45 VSS_21 VSS_22 46 175 DQ33 DQ32 176
M_A_DQ9 M_A_DQ8
47 DQ21 DQ20 48 177 VSS_57 VSS_58 178
-M_A_DQS6
49 VSS_23 VSS_24 50 179 DQS4_c DM4_n/DBl4_n 180
M_A_DQ13 M_A_DQ12 M_A_DQS6
51 DQ17 DQ16 52 181 DQS4_t VSS_59 182 M_A_DQ50
53 VSS_25 VSS_26 54 183 VSS_60 DQ39 184
-M_A_DQS1 M_A_DQ54 1 2
55 DQS2_c DM2_n/DBl2_n 185 DQ38 VSS_61 186
M_A_DQS1 56 M_A_DQ53
57 DQS2_t VSS_27 187 VSS_62 DQ35 188 C2302
58 M_A_DQ15 M_A_DQ55 C2301
VSS_28 DQ22 DQ34 VSS_63
M_A_DQ10 59 60 189 190 M_A_DQ33 2.2U_0402_6.3V6-M 0.1U_0402_10V7-K
C
61 DQ23 VSS_29 191 VSS_64 DQ45 192 2@ 1@ C
62 M_A_DQ14 M_A_DQ32
VSS_30 DQ18 193 DQ44 VSS_65 194
M_A_DQ11 63 64 M_A_DQ37
65 DQ19 VSS_31 195 VSS_66 DQ41 196
67 VSS_32 DQ28 197 DQ40 VSS_67 198
M_A_DQ21 68 -M_A_DQS4
69 DQ29 VSS_33 199 VSS_68 DQS5_c 200
70 M_A_DQ16 M_A_DQS4
71 VSS_34 DQ24 201 DM5_n/DBl5_n DQS5_t 202
M_A_DQ20 72
73 DQ25 VSS_35 203 VSS_69 VSS_70 204
74 -M_A_DQS2 M_A_DQ35 M_A_DQ39
75 VSS_36 DQS3_c 205 DQ46 DQ47 206
76 M_A_DQS2
77 DM3_n/DBl3_n DQS3_t 207 VSS_71 VSS_72 208
VSS_37 VSS_38 209 DQ42 DQ43 210
M_A_DQ18 79 80 M_A_DQ19
81 DQ30 DQ31 211 VSS_73 VSS_74 212 +1.2V
VSS_39 VSS_40 213 DQ52 DQ53 214
M_A_DQ22 83 84 M_A_DQ23
DQ26 DQ27 215 VSS_75 VSS_76 216
85 86 M_A_DQ43 M_A_DQ45
VSS_41 VSS_42 217 DQ49 DQ48 218
87 88
CB5/NC CB4/NC 219 VSS_77 VSS_78 220
89 90 -M_A_DQS5
VSS_43 VSS_44 221 DQS6_c DM6_n/DBl6_n 222
91 92 M_A_DQS5
CB1/NC CB0/NC 223 DQS6_t VSS_79 224
93 94 M_A_DQ41
VSS_45 VSS_46 225 VSS_80 DQ54 226
95 96 M_A_DQ47
DQS8_c DM8_n/DBl_n/NC 227 DQS5 VSS_81 228
97 98 M_A_DQ46
DQS8_t VSS_47 229 VSS_82 DQ50 230
99 100 M_A_DQ42
VSS_48 CB6/NC 231 DQ51 VSS_83 232
101 102 M_A_DQ61
CB2/NC VSS_49 233 VSS_84 DQ60 234
103 104 M_A_DQ56
VSS_50 CB7/NC 235 DQ61 VSS_85 236
105 106 M_A_DQ60
CB3/NC VSS_51 +3VS 237 VSS_86 DQ57 238
107 108 -DRAMRST -DRAMRST <7,25> M_A_DQ57
VSS_52 RESET_n 239 DQ56 VSS_87 240
<6> M_A_CKE0 M_A_CKE0 109 110 M_A_CKE1 M_A_CKE1 <6> -M_A_DQS7
CKE0 CKE1 241 VSS_88 DQS7_c 242
111 112 M_A_DQS7
VDD_1 VDD_2 DM7_n/DBl7_n DQS7_t
1
<6> M_A_BG1 M_A_BG1 113 114 -M_A_ACT -M_A_ACT <6> 243 244
BG1 ACT_n R2302 245 VSS_89 VSS_90 246
<6> M_A_BG0 M_A_BG0 115 116 -M_A_ALERT -M_A_ALERT <6> M_A_DQ63 M_A_DQ58
BG0 ALERT_n 247 DQ62 DQ63 248
117 118 0_0402_5%_SM
VDD_3 VDD_4 249 VSS_91 VSS_92 250
M_A_A12 119 120 M_A_A11 M_A_DQ62 M_A_DQ59
Vinafix.com A12 A11 251 DQ58 DQ59 252
M_A_A9 121 122 M_A_A7 VSS_93 VSS_94
2
123 A9 A7 124 PM_SMB_CLK 253 254 PM_SMB_DAT
VDD_5 VDD_6 <9,25,65> PM_SMB_CLK SCL SDA PM_SMB_DAT <9,25,65>
M_A_A8 125 126 M_A_A5 VDDSPD_1 255 256 SA0_CHA_P
A8 A5 257 VDDSPD SA0 258
M_A_A6 127 128 M_A_A4
A6 A4 259 VPP_1 VTT 260
B 129 130 SA1_CHA_P B
VDD_7 VDD_8 [KBL PDG]VDDSPD VPP_2 SA1
1 1
1
261 262
[KBL PDG] EE 0.1uF x1, C2303 GND_1 GND_2
C2307 C2304 RF
ARGOS_D4AR0-26005-1P40 0.1U_0402_16V7-K 2.2uF x1. 0.1U_0402_10V7-K 2.2U_0402_6.3V6-M ARGOS_D4AR0-26005-1P40
2
2
EMC_NS@ 2 ME@
ME@
Place
decoupling cap
close to DIMM
+1.2V
+3VS +3VS +3VS

1
R2309
1
1
1
1K_0402_1%
R2303 R2305 R2307
10K_0402_5% 10K_0402_5% 10K_0402_5%
2
@ @ @
R2310
2
2
2_0402_1%
<6> M_A_VREF_CA_CPU 1 2 M_VREF_CA_DIMMA SA0_CHA_P SA1_CHA_P SA2_CHA_P
1
1
C2305 R2304 R2306 R2308

1
0.022U_0402_25V7-K 0_0402_5%_SM 0_0402_5%_SM 0_0402_5%_SM

2
1
R2312
1
1K_0402_1% C2306
2
2
R2311 0.1U_0402_16V7-K
2
A 24.9_0402_1% @ A
2
2
SPD Address = 0H
Issued Date 2015/09/01 Deciphered Date 2016/12/31 DDR4 CH-A PRIMARY
Size
Document Number
Number Rev
Rev
Custom 0.2
Date:
Sheet 23 of 99
5 4 3 2 1
5 4 3 2 1
+2.5V +2.5V <6,23,25,26,94>
+1.2V +1.2V <6,7,18,23,25,26,85>
+0.6VS +0.6VS <23,25,26,85>
D D
[KBL PDG]VDDQ
[KBL PDG] EE 10uF x16, 1uF x16. 330uF x1
Place 10uF/1uF decoupling cap, 4
near each side of the DIMM
connector close to VDD pins.
330uF placeholder
+1.2V
1 1
1
1
1
1
1
1
C2401 C2402 C2403 C2404 C2405 C2406 C2407 C2408
10U_0603_6.3V6-M 10U_0603_6.3V6-M 10U_0603_6.3V6-M 10U_0603_6.3V6-M 10U_0603_6.3V6-M 10U_0603_6.3V6-M 10U_0603_6.3V6-M 10U_0603_6.3V6-M
2 2
2
2
2
2
2
2
+1.2V
1
1 1
+ C2419
C C2409 C2410 C2411 C2412 C2413 C2414 C2415 C2416 C2417 C2418 330U_D1_2VM_R6M C
0.1U_0402_10V7-K 100P_0402_50V8J 1U_0402_6.3V6-K 1U_0402_6.3V6-K 1U_0402_6.3V6-K 1U_0402_6.3V6-K 1U_0402_6.3V6-K 1U_0402_6.3V6-K 1U_0402_6.3V6-K 1U_0402_6.3V6-K
2 RF@ 2 RF@ 2
[KBL PDG]VPP
[KBL PDG] EE 10uF x2, 1uF x2.
Place decoupling cap on DRAM side.
+2.5V
1 1
1
1
C2420 C2421 C2422 C2423 C2424 C2425

0.1U_0402_10V7-K 100P_0402_50V8J 10U_0603_6.3V6-M 10U_0603_6.3V6-M 1U_0402_6.3V6-K 1U_0402_6.3V6-K
2 RF_NS@
2
2 RF_NS@
2
B
Vinafix.com
[KBL PDG]VTT
+0.6VS
1 1
B
1
C2426 C2427 C2428 C2429 C2430 C2431 C2432 C2433

0.1U_0402_10V7-K 100P_0402_50V8J 10U_0603_6.3V6-M 10U_0603_6.3V6-M 1U_0402_6.3V6-K 1U_0402_6.3V6-K 1U_0402_6.3V6-K 1U_0402_6.3V6-K
2 RF_NS@
2
2 RF_NS@
Place decoupling on the VTT plane close to SODIMM
A A

Issued Date 2015/01/12 Deciphered Date 2016/01/12 DDR4 CH-A PRIMARY_POWER
Size
Document Number
Number Rev
Rev
Custom 0.2
Date:
Sheet 24 of 99
5 4 3 2 1
5 4 3 2 1
+3VS +3VS <5,6,9,10,11,12,14,15,23,30,32,37,39,40,47,50,51,57,58,59,60,61,63,65,66,67,69,72,85,86> <6,7> M_B_DQ[63:0]
+2.5V +2.5V <6,23,24,26,94> <6,7> -M_B_DQS[7:0]
+1.2V +1.2V <6,7,18,23,24,26,85> <6,7> M_B_DQS[7:0]
+0.6VS +0.6VS <23,24,26,85> <7> M_B_A[16:0]
+1.2V
+2.5V +1.2V +1.2V +0.6VS
+1.2V +1.2V
D Layout Node: D
1
Place Close DIMMs +1.2V
JDIMM2B
R2501
240_0402_1%
JDIMM2A
2
M_B_A3 131 132 M_B_A2
1 2 M_B_A1 133 A3 A2 134 EVENT_n_2
M_B_DQ1 3 VSS_1 VSS_2 4 135 A1 EVENT_n/NF 136
M_B_DQ4
5 DQ5 DQ4 6 137 VDD_9 VDD_10 138
<7> M_B_DDRCLK0_1066M M_B_DDRCLK0_1066M M_B_DDRCLK1_1066M M_B_DDRCLK1_1066M <7>
M_B_DQ0 7 VSS_3 VSS_4 8 139 CK0_t CK1_t/NF 140
M_B_DQ5 <7> -M_B_DDRCLK0_1066M -M_B_DDRCLK0_1066M -M_B_DDRCLK1_1066M -M_B_DDRCLK1_1066M <7>
9 DQ1 DQ0 10 141 CK0_c CK1_c/NF 142
11 VSS_5 VSS_6 12 143 VDD_11 VDD_12 144
-M_B_DQS0 <7> M_B_PARITY M_B_PARITY M_B_A0
13 DQS0_C DM0_n/DBl0_n 14 Parity A0
M_B_DQS0
15 DQS0_t VSS_7 16 M_B_DQ3
17 VSS_8 DQ6 18 145 146
M_B_DQ6 <7> M_B_BS1 M_B_BS1 M_B_A10
19 DQ7 VSS_9 20 147 BA1 A10/AP 148
M_B_DQ2
21 VSS_10 DQ2 22 149 VDD_13 VDD_14
M_B_DQ7 <7> -M_B_CS0 -M_B_CS0 150 M_B_BS0 M_B_BS0 <7>
23 DQ3 VSS_11 24 151 CS0_n BA0
M_B_DQ9 M_B_A14 152 M_B_A16
25 VSS_12 DQ12 26 153 A14/WE_n A16/RAS_n
M_B_DQ13 154
27 DQ13 VSS_13 28 155 VDD_15 VDD_16 156
M_B_DQ8 <7> M_B_ODT0 M_B_ODT0 M_B_A15
29 VSS_14 DQ8 30 157 ODT0 A15/CAS_n
M_B_DQ12 <7> -M_B_CS1 -M_B_CS1 158 M_B_A13
31 DQ9 VSS_15 32 159 CS1_n A13
-M_B_DQS1 160
33 VSS_16 DQS1_c 34 161 VDD_17 VDD_18
M_B_DQS1 <7> M_B_ODT1 M_B_ODT1 162
35 DM1_n/DBl_n DQS1_t 36 163 ODT1 C0/CS2_n/NC 164 M_VREF_CA_DIMMB
37 VSS_17 VSS_18 38 165 VDD_19 VREFCA
M_B_DQ15 M_B_DQ10 166 SA2_CHB_P
39 DQ15 DQ14 40 167 C1/CS3_n/NC SA2 168
41 VSS_19 VSS_20 42 169 VSS_53 VSS_54 +1.2V
M_B_DQ14 M_B_DQ11 M_B_DQ52 170 M_B_DQ48
43 DQ10 DQ11 44 171 DQ37 DQ36 172
45 VSS_21 VSS_22 46 VSS_55 VSS_56
M_B_DQ20 M_B_DQ21 M_B_DQ49 173 174 M_B_DQ53
47 DQ21 DQ20 48 175 DQ33 DQ32 176
49 VSS_23 VSS_24 50 VSS_57 VSS_58
M_B_DQ17 M_B_DQ16 -M_B_DQS6 177 178
51 DQ17 DQ16 52 DQS4_c DM4_n/DBl4_n
M_B_DQS6 179 180
53 VSS_25 VSS_26 54 DQS4_t VSS_59
-M_B_DQS2 181 182 M_B_DQ54
55 DQS2_c DM2_n/DBl2_n 56 VSS_60 DQ39
M_B_DQS2 M_B_DQ50 183 184 1 1
C
57 DQS2_t VSS_27 58 DQ38 VSS_61 C
M_B_DQ19 185 186 M_B_DQ55
59 VSS_28 DQ22 60 VSS_62 DQ35 CD61 CD62
M_B_DQ18 M_B_DQ51 187 188
61 DQ23 VSS_29 62 DQ34 VSS_63 2.2U_0402_6.3V6-M 0.1U_0402_10V7-K
M_B_DQ22 189 190 M_B_DQ32
63 VSS_30 DQ18 64 VSS_64 DQ45 2@ 2@
M_B_DQ23 M_B_DQ33 191 192
65 DQ19 VSS_31 66 DQ44 VSS_65
M_B_DQ40 193 194 M_B_DQ37
67 VSS_32 DQ28 68 VSS_66 DQ41
M_B_DQ44 M_B_DQ36 195 196
69 DQ29 VSS_33 70 DQ40 VSS_67
M_B_DQ41 197 198 -M_B_DQS4
71 VSS_34 DQ24 72 VSS_68 DQS5_c
M_B_DQ45 199 200 M_B_DQS4
73 DQ25 VSS_35 74 DM5_n/DBl5_n DQS5_t
-M_B_DQS5 201 202
75 VSS_36 DQS3_c 76 VSS_69 VSS_70
M_B_DQS5 M_B_DQ34 203 204 M_B_DQ39
77 DM3_n/DBl3_n DQS3_t 78 DQ46 DQ47
205 206
79 VSS_37 VSS_38 80 VSS_71 VSS_72
81 DQ30 DQ31 82 DQ42 DQ43
209 210
83 VSS_39 VSS_40 84 VSS_73 VSS_74 +1.2V
85 DQ26 DQ27 86 DQ52 DQ53
213 214
87 VSS_41 VSS_42 88 VSS_75 VSS_76
M_B_DQ60 215 216 M_B_DQ57
89 CB5/NC CB4/NC 90 DQ49 DQ48
217 218
91 VSS_43 VSS_44 92 VSS_77 VSS_78
-M_B_DQS7 219 220
93 CB1/NC CB0/NC 94 DQS6_c DM6_n/DBl6_n
M_B_DQS7 221 222
95 VSS_45 VSS_46 96 DQS6_t VSS_79
223 224 M_B_DQ63
97 DQS8_c DM8_n/DBl_n/NC 98 225 VSS_80 DQ54
M_B_DQ58 226
99 DQS8_t VSS_47 100 DQS5 VSS_81
227 228 M_B_DQ62
101 VSS_48 CB6/NC 102 229 VSS_82 DQ50
M_B_DQ59 230
103 CB2/NC VSS_49 104 231 DQ51 VSS_83 232 M_B_DQ29
105 VSS_50 CB7/NC 106 +3VS 233 VSS_84 DQ60
M_B_DQ24 234
107 CB3/NC VSS_51 108 235 DQ61 VSS_85
-DRAMRST -DRAMRST <7,23> 236 M_B_DQ28
109 VSS_52 RESET_n 110 237 VSS_86 DQ57
<7> M_B_CKE0 M_B_CKE0 M_B_CKE1 M_B_CKE1 <7> M_B_DQ25 238
111 CKE0 CKE1 112 239 DQ56 VSS_87 240 -M_B_DQS3
VDD_1 VDD_2 VSS_88 DQS7_c
1
<7> M_B_BG1 M_B_BG1 113 114 -M_B_ACT -M_B_ACT <7> 241 242 M_B_DQS3
115 BG1 ACT_n 116 R2502 243 DM7_n/DBl7_n DQS7_t
<7> M_B_BG0 M_B_BG0 -M_B_ALERT -M_B_ALERT <7> 244
Vinafix.com 117 BG0 ALERT_n 118 245 VSS_89 VSS_90
0_0402_5%_SM M_B_DQ27 246 M_B_DQ30
119 VDD_3 VDD_4 120 247 DQ62 DQ63
M_B_A12 M_B_A11 248
121 A12 A11 122 249 VSS_91 VSS_92
M_B_A9 M_B_A7 M_B_DQ26 250 M_B_DQ31
A9 A7 DQ58 DQ59
2
123 124 251 252
B 125 VDD_5 VDD_6 126 253 VSS_93 VSS_94
M_B_A8 M_B_A5 <9,23,65> PM_SMB_CLK PM_SMB_CLK 254 PM_SMB_DAT PM_SMB_DAT <9,23,65>
B
127 A8 A5 128 255 SCL SDA
M_B_A6 M_B_A4 VDDSPD_2 256 SA0_CHB_P
129 A6 A4 130 257 VDDSPD SA0 258
VDD_7 VDD_8 259 VPP_1 VTT 260 SA1_CHB_P
VPP_2 SA1
1
C2501 [KBL PDG]VDDSPD 1 1 261 262

ARGOS_D4AR0-26005-1P40 0.1U_0402_16V7-K GND_1 GND_2
2
ME@ EMC_NS@ [KBL PDG] EE 0.1uF CD63 CD64 ARGOS_D4AR0-26005-1P40

x1, 2.2uF x1. 0.1U_0402_10V7-K 2.2U_0402_6.3V6-M ME@
2 2
Place decoupling
cap close to DIMM
+1.2V
+3VS +3VS +3VS
1
R2510 R2512 1 R2514

R2503 10K_0402_5% 10K_0402_5% 10K_0402_5%
1K_0402_1% @ @
2
2
2
R2504 SA0_CHB_P SA1_CHB_P SA2_CHB_P

2_0402_1%
<6> M_B_VREF_CA_CPU 1 2 M_VREF_CA_DIMMB
1
1
1 R2511 R2513 R2515

0_0402_5%_SM 0_0402_5% 0_0402_5%_SM
CD65
1
A 0.022U_0402_25V7-K @ A
2
2
2
2
1
R2507
1
1K_0402_1% CD66
R2506 0.1U_0402_16V7-K
2
24.9_0402_1%
@
2
SPD Address = 2H
2

Issued Date 2015/09/01 Deciphered Date 2016/12/31 DDR4 CH-B PRIMARY
Size
Document Number
Number Rev
Rev
Custom 0.2
Date:
Sheet 25 of 99
5 4 3 2 1
5 4 3 2 1
+2.5V +2.5V <6,23,24,25,94>
+1.2V +1.2V <6,7,18,23,24,25,85>

D D
+0.6VS +0.6VS <23,24,25,85>
[KBL PDG]VDDQ
[KBL PDG] EE 10uF x16, 1uF x16. 330uF x1
Place 10uF/1uF decoupling cap, 4
near each side of the DIMM
connector close to VDD pins.
330uF placeholder
+1.2V
1 1
1
1
1
1
1
C2601 C2602 C2603 C2604 C2605 C2606 C2607 C2608

10U_0603_6.3V6-M 10U_0603_6.3V6-M 10U_0603_6.3V6-M 10U_0603_6.3V6-M 10U_0603_6.3V6-M 10U_0603_6.3V6-M 10U_0603_6.3V6-M 10U_0603_6.3V6-M
2 2
2
2
2
2
2
C C
+1.2V
1 1
C2609 C2610 C2611 C2612 C2613 C2614 C2615 C2616 C2617 C2618
0.1U_0402_10V7-K 100P_0402_50V8J 1U_0402_6.3V6-K 1U_0402_6.3V6-K 1U_0402_6.3V6-K 1U_0402_6.3V6-K 1U_0402_6.3V6-K 1U_0402_6.3V6-K 1U_0402_6.3V6-K 1U_0402_6.3V6-K
2 RF@ 2 RF@
[KBL PDG]VPP
Place decoupling cap on DRAM side.
+2.5V
Vinafix.com
1 1
1
C2619 C2620 C2621 C2622 C2623 C2624

0.1U_0402_10V7-K 100P_0402_50V8J 10U_0603_6.3V6-M 10U_0603_6.3V6-M 1U_0402_6.3V6-K 1U_0402_6.3V6-K
2 RF_NS@
2
2 RF_NS@
2
B B
[KBL PDG]VTT
+0.6VS
1 1
1
1
C2625 C2626 C2627 C2628 C2629 C2630 C2631 C2632

0.1U_0402_10V7-K 100P_0402_50V8J 10U_0603_6.3V6-M 10U_0603_6.3V6-M 1U_0402_6.3V6-K 1U_0402_6.3V6-K 1U_0402_6.3V6-K 1U_0402_6.3V6-K
2 RF_NS@ 2 RF_NS@
2
2
Place decoupling on the VTT plane close to SODIMM
A A

Issued Date 2015/01/12 Deciphered Date 2016/01/12 DDR4 CH-B PRIMARY_POWER
Size
Document Number
Number Rev
Rev
Custom 0.2
Date:
Sheet 26 of 99
5 4 3 2 1
5 4 3 2 1
+VCC_CORE +VCC_CORE <16,17,87,90> +VCC_GT +VCC_GT <17,88,90> +VCCCORE_GT2 +VCCCORE_GT2 <17> [KBL-R U4+2/KBL U2+2 Processor]VCCGT
[KBL-R U4+2/KBL U2+2 Processor]VCC +VCCCORE_GT1 +VCCCORE_GT1 <17> [KBL-R U4+2/KBL U2+2 Processor]10uF x10,1uF x12
[KBL-R U4+2/KBL U2+2 Processor]22uF x9,10uF x8,1uF,47uF x8
+VCC_CORE +VCC_GT TOP
BOTTOM
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
D D
C2719 C2701 C2702 C2703 C2704 C2705 C2706 C2707 C2708 C2752 C2753 C2754 C2755 C2756 C2792
22U_0603_6.3V6-M 22U_0603_6.3V6-M 22U_0603_6.3V6-M 22U_0603_6.3V6-M 22U_0603_6.3V6-M 22U_0603_6.3V6-M 22U_0603_6.3V6-M 22U_0603_6.3V6-M 22U_0603_6.3V6-M 10U_0402_6.3V6-M 10U_0402_6.3V6-M 10U_0402_6.3V6-M 10U_0402_6.3V6-M 10U_0402_6.3V6-M 10U_0402_6.3V6-M
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
+VCC_GT
+VCC_CORE
1 1 1 1 1 1
1 1 1 1 1 1 1 1
C2757 C2758 C2759 C2760 C2761 C2791
C2781 C2775 C2776 C2777 C2778 C2779 C2780 C2782 10U_0402_6.3V6-M 10U_0402_6.3V6-M 10U_0402_6.3V6-M 10U_0402_6.3V6-M 10U_0402_6.3V6-M 10U_0402_6.3V6-M
10U_0402_6.3V6-M 10U_0402_6.3V6-M 10U_0402_6.3V6-M 10U_0402_6.3V6-M 10U_0402_6.3V6-M 10U_0402_6.3V6-M 10U_0402_6.3V6-M 10U_0402_6.3V6-M 2 2 2 2 2 2
2 2 2 2 2 2 2 2
+VCC_GT
+VCC_CORE
1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
C2762 C2763 C2764 C2765 C2766 C2767 C2793
C2783 C2784 C2785 C2786 C2787 C2788 C2789 C2790 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M
22U_0603_6.3V6-M 22U_0603_6.3V6-M 22U_0603_6.3V6-M 22U_0603_6.3V6-M 22U_0603_6.3V6-M 22U_0603_6.3V6-M 22U_0603_6.3V6-M 22U_0603_6.3V6-M 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2
C C
[KBL-R U4+2/KBL U2+2 Processor]10uF x7,1uF x31 +VCC_GT

+VCC_CORE +VCC_CORE
TOP
1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
C2768 C2769 C2770 C2771 C2773 C2774 C2794
C2720 C2721 C2722 C2723 C2724 C2725 C2726 C2747 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M
10U_0402_6.3V6-M 10U_0402_6.3V6-M 10U_0402_6.3V6-M 10U_0402_6.3V6-M 10U_0402_6.3V6-M 10U_0402_6.3V6-M 10U_0402_6.3V6-M 1U_0201_6.3V6-M 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2
+VCC_CORE
[KBL-R U4+2/KBL U2+2 Processor]10uF x7,47uF x3
BOTTOM
1 1 1 1 1 1 +VCC_GT
1 1 1 1
C2709 C2710 C2711 C2712 C2713 C2714 C2715 C2716 C2717 C2718
1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2
B +VCC_CORE
2
C2727
1U_0201_6.3V6-M
1
2
Vinafix.com
C2728
1U_0201_6.3V6-M
1
2
C2729
1U_0201_6.3V6-M
1
2
C2730
1U_0201_6.3V6-M
1
2
C2731
1U_0201_6.3V6-M
1
2
C2732
1U_0201_6.3V6-M
1
2
C2733
1U_0201_6.3V6-M
1
2
C2734
1U_0201_6.3V6-M
1
2
C2735
1U_0201_6.3V6-M
1
2
C2736
1U_0201_6.3V6-M
2
+VCC_GT
C27101
22U_0603_6.3V6-M
2
C27100
22U_0603_6.3V6-M
2
C2799
22U_0603_6.3V6-M
2
C2795
22U_0603_6.3V6-M
2
C2798
22U_0603_6.3V6-M
2
C2796
22U_0603_6.3V6-M
2
C2797
22U_0603_6.3V6-M
1 1 1
C27102 C27103 C27104
22U_0603_6.3V6-M 22U_0603_6.3V6-M 22U_0603_6.3V6-M
+VCC_CORE 2 2 2
1 1 1 1 1 1 1 1 1 1
+VCCCORE_GT2 [KBL-R U4+2/KBL U2+2 Processor]1uF X5
C2737 C2738 C2739 C2740 C2741 C2742 C2743 C2744 C2745 C2746
BOTTOM
1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M
2 2 2 2 2 2 2 2 2 2
1 1 1 1 1
C27107 C27105 C27108 C27106 C27109
1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M
2 2 2 2 2
A
[KBL-R U4+2/KBL U2+2 Processor]1uF X5
BOTTOM A
+VCCCORE_GT1
1 1 1 1 1 1
C27113 C27112 C27115 C27114 C27116 C27117 Title

1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M
Security Classification LC Future Center Secret Data
2 2 2 2 2 2
Issued Date 2015/01/12 Deciphered Date 2016/01/12 VCC_CORE & VCC_GT CAP
Size
Document Number
Number Rev
Rev
Custom 0.2
0.2
Date:
Sheet 27 of 99
99
5 4 3 2 1
5 4 3 2 1
D D
C C
B
Vinafix.com B
A A

Issued Date 2015/01/12 Deciphered Date 2016/01/12 BLANK
Size
Size Document
Number Rev
Rev
Custom 0.2
Date:
30, 2017
2017 Sheet
Sheet 28 of 99
5 4 3 2 1
5 4 3 2 1
D D
C C
B
Vinafix.com B
A A

Size
Size Document
Number Rev
Rev
Custom 0.2
Date:
30, 2017
2017 Sheet
Sheet 29 of 99
5 4 3 2 1
5 4 3 2 1
+3VS +3VS <5,6,9,10,11,12,14,15,23,25,32,37,39,40,47,50,51,57,58,59,60,61,63,65,66,67,69,72,85,86>
+3VS_VGA +3VS_VGA <32,37,38,39,91>

TABLE of GPU (UV3001)
+1.8VS_VGA +1.8VS_VGA <32,34,38>
Vendor LCFC P/N Description
AMD(R17M-P1-70) SA00008ED00 S IC 216-0905004 C0 FCBGA 769P GPU
AMD(R17M-P1-50) SA00008DT00 S IC 216-0905018 C3 FCBGA 769P GPU
D D
DIS@ support GEN3

UV3001B @
symbol2
PCIE_CTX_C_GRX_N[0..3] PCIE_CTX_C_GRX_P0 AT41 AV35 PCIE_CRX_C_GTX_P0 C3008 DIS@ 1 2 0.22U_0402_10V6-K PCIE_CRX_GTX_P0
<12> PCIE_CTX_C_GRX_N[0..3] PCIE_RX0P PCIE_TX0P
PCIE_CTX_C_GRX_N0 AT40 AU35 PCIE_CRX_C_GTX_N0 C3001 DIS@ 1 2 0.22U_0402_10V6-K PCIE_CRX_GTX_N0
PCIE_CTX_C_GRX_P[0..3] PCIE_RX0N PCIE_TX0N
<12> PCIE_CTX_C_GRX_P[0..3]
PCIE_CTX_C_GRX_P1 AR41 AU38 PCIE_CRX_C_GTX_P1 C3002 DIS@ 1 2 0.22U_0402_10V6-K PCIE_CRX_GTX_P1
PCIE_CTX_C_GRX_N1 AR40 PCIE_RX1P PCIE_TX1P AU39 PCIE_CRX_C_GTX_N1 C3003 DIS@ 1 2 0.22U_0402_10V6-K PCIE_CRX_GTX_N1
PCIE_CRX_GTX_N[0..3] PCIE_RX1N PCIE_TX1N
<12> PCIE_CRX_GTX_N[0..3]
PCIE_CTX_C_GRX_P2 AP41 AR37 PCIE_CRX_C_GTX_P2 C3004 DIS@ 1 2 0.22U_0402_10V6-K PCIE_CRX_GTX_P2
PCIE_CRX_GTX_P[0..3] PCIE_CTX_C_GRX_N2 AP40 PCIE_RX2P PCIE_TX2P AR38 PCIE_CRX_C_GTX_N2 C3005 DIS@ 1 2 0.22U_0402_10V6-K PCIE_CRX_GTX_N2
<12> PCIE_CRX_GTX_P[0..3] PCIE_RX2N PCIE_TX2N
PCIE_CTX_C_GRX_P3 AM41 AN37 PCIE_CRX_C_GTX_P3 C3006 DIS@ 1 2 0.22U_0402_10V6-K PCIE_CRX_GTX_P3
PCIE_CTX_C_GRX_N3 AM40 PCIE_RX3P PCIE_TX3P AN38 PCIE_CRX_C_GTX_N3 C3007 DIS@ 1 2 0.22U_0402_10V6-K PCIE_CRX_GTX_N3
PCIE_RX3N PCIE_TX3N
AL41 AL37
AL40 PCIE_RX4P PCIE_TX4P AL38
PCIE_RX4N PCIE_TX4N
AK41 AJ37 +3VS_VGA
AK40 PCIE_RX5P PCIE_TX5P AJ38
PCIE_RX5N PCIE_TX5N
AJ41 AG37
PCIE_RX6P PCIE_TX6P
1
AJ40 AG38
PCIE_RX6N PCIE_TX6N R3005
AH41 AE37 10K_0402_5%
AH40 PCIE_RX7P PCIE_TX7P AE38 @
PCIE_RX7N PCIE_TX7N
2
CLK_PCIE_VGA AV33 AV41 PLT_RST_VGA#
C <14> CLK_PCIE_VGA PCIE_REFCLKP PERSTB C
CLK_PCIE_VGA# AU33
<14> CLK_PCIE_VGA# PCIE_REFCLKN AC41 PX_EX R3006 2 DIS@ 1 1K_0402_5%
PX_EN
1
R3007
100K_0402_5%
DIS@
2
AU41 PCIE_ZVSS R3001 1 DIS@ 2 200_0402_1%
PCIE_ZVSS
REV 0.91
216-0905018-C3_FCBGA769
+1.8VS_VGA
JTAG
2
2
R3016 R3015 +3VS_VGA

10K_0402_5%
Vinafix.com 10K_0402_5%
DIS@ DIS@
UV3001A @
1
1
1
symbol1
TV52 1 R3014 1 DIS@ 2 33_0402_5% AA38 AF41 JTAG_TDO 1 TV48 R3009
B R3013 1 DIS@ 2 33_0402_5% AA37 BP_0 JTAG_TDO AD40 1 TV49 1K_0402_5% B
TV53 1 JTAG_TDI
BP_1 JTAG_TDI AD41 1 TV50
JTAG_TMS @
JTAG_TMS AE41 1 TV51
JTAG_TCK
JTAG_TCK
2
B2 AE40 TESTEN
TEST6 TESTEN AF40 JTAG_TRSTB
JTAG_TRSTB
1
R3002
2
REV 0.91 R3008 0_0402_5%

R3012 1K_0402_5% 1 @ 2
216-0905018-C3_FCBGA769
10K_0402_5% DIS@
DIS@
2
1
+3VS
U3003
<15,40,58,63,67,69> PLT_RST# R3004 1 2 0_0402_5%_SM 1 5

+3VS_VGA B VCC
<10> DGPU_HOLD_RST# DGPU_HOLD_RST# 2
A
PD 10K at GPU Pin
3 4 PLT_RST_VGA# <32,91>
GND Y
1
R3010
10K_0402_5% 74LVC1G08GW_SOT353-1-5
DIS@ DIS@
SA00005U300
2
1
R3011
A A
1K_0402_5%
@
2

Issued Date 2015/01/12 Deciphered Date 2016/01/12 R17M-P1-50(A)_PCIE
Size
Size Document
Number Rev
Rev
Custom 0.2
Date:
Sheet 30 of 99
5 4 3 2 1
1 2 3 4 5
+1.35VS_VGA +1.35VS_VGA <34,36,95>
UV3001C @
symbol3 UV3001D @
<36> DQA0_<0> DQA0_<0> L34 B27 DQA1_<0> DQA1_<0> <36> symbol4
DQA0_<1> L37 DQA0_0 DQA1_0 A27 DQA1_<1> C2 AH1
<36> DQA0_<1> DQA0_1 DQA1_1 DQA1_<1> <36> DQB0_0 DQB1_0
<36> DQA0_<2> DQA0_<2> L38 B26 DQA1_<2> DQA1_<2> <36> C1 AH2
DQA0_<3> J35 DQA0_2 DQA1_2 A26 DQA1_<3> D2 DQB0_1 DQB1_1 AJ2
<36> DQA0_<4> DQA0_<4> G37 A24 DQA1_<4> DQA1_<4> <36> D1 AK1
DQA0_<5> E38 DQA0_4 DQA1_4 B23 DQA1_<5> F1 DQB0_3 DQB1_3 AL2
<36> DQA0_<6> DQA0_<6> E35 A23 DQA1_<6> DQA1_<6> <36> G2 AM1
DQA0_<7> D35 DQA0_6 DQA1_6 B22 DQA1_<7> G1 DQB0_5 DQB1_5 AM2
A <36> DQA0_<8> DQA0_<8> H41 B20 DQA1_<8> DQA1_<8> <36> H2 AN2 A
DQA0_<9> H40 DQA0_8 DQA1_8 A20 DQA1_<9> K2 DQB0_7 DQB1_7 AR1
<36> DQA0_<10> DQA0_<10> G41 B19 DQA1_<10> DQA1_<10> <36> K1 AR2
DQA0_<11> G40 DQA0_10 DQA1_10 A19 DQA1_<11> L2 DQB0_9 DQB1_9 AT1
<36> DQA0_<12> DQA0_<12> E40 B17 DQA1_<12> DQA1_<12> <36> L1 AT2
DQA0_<13> D41 DQA0_12 DQA1_12 A16 DQA1_<13> N2 DQB0_11 DQB1_11 AV2
<36> DQA0_<14> DQA0_<14> D40 B16 DQA1_<14> DQA1_<14> <36> P2 AW1
C41 DQA0_14 DQA1_14 A15 DQA1_<15> P1 DQB0_13 DQB1_13 AW2
<36> DQA0_<15> DQA0_<15> DQA1_<15> <36>
DQA0_<16> C40 DQA0_15 DQA1_15 B15 DQA1_<16> R2 DQB0_14 DQB1_14 AY3
<36> DQA0_<17> DQA0_<17> B39 A14 DQA1_<17> DQA1_<17> <36> R1 BA3
A39 DQA0_17 DQA1_17 B14 DQA1_<18> T2 DQB0_16 DQB1_16 AY4
<36> DQA0_<18> DQA0_<18> DQA1_<18> <36>
B38 DQA0_18 DQA1_18 B13 DQA1_<19> T1 DQB0_17 DQB1_17 BA4
<36> DQA0_<19> DQA0_<19> DQA1_<19> <36>
B36 DQA0_19 DQA1_19 A11 DQA1_<20> U2 DQB0_18 DQB1_18 AY5
<36> DQA0_<20> DQA0_<20> DQA1_<20> <36>
A36 DQA0_20 DQA1_20 B11 DQA1_<21> W1 DQB0_19 DQB1_19 BA7
<36> DQA0_<21> DQA0_<21> DQA1_<21> <36>
B35 DQA0_21 DQA1_21 A10 W2 DQB0_20 DQB1_20 AY7
<36> DQA0_<22> DQA0_<22> DQA1_<22> DQA1_<22> <36>
A35 DQA0_22 DQA1_22 B10 DQA1_<23> Y1 DQB0_21 DQB1_21 AY8
<36> DQA0_<23> DQA0_<23> DQA1_<23> <36>
B33 DQA0_23 DQA1_23 B8 Y2 DQB0_22 DQB1_22 BA8
<36> DQA0_<24> DQA0_<24> DQA1_<24> DQA1_<24> <36>
B32 DQA0_24 DQA1_24 A7 AB2 DQB0_23 DQB1_23 AR4
<36> DQA0_<25> DQA0_<25> DQA1_<25> DQA1_<25> <36>
A32 DQA0_25 DQA1_25 B7 AC1 DQB0_24 DQB1_24 AR5
<36> DQA0_<26> DQA0_<26> DQA1_<26> DQA1_<26> <36>
B31 DQA0_26 DQA1_26 AC2 DQB0_25 DQB1_25 AU4
<36> DQA0_<27> DQA0_<27> A6 DQA1_<27> DQA1_<27> <36>
A30 DQA0_27 DQA1_27 AD1 DQB0_26 DQB1_26 AU7
<36> DQA0_<28> DQA0_<28> A4 DQA1_<28> DQA1_<28> <36>
B29 DQA0_28 DQA1_28 AF1 DQB0_27 DQB1_27 AN8
<36> DQA0_<29> DQA0_<29> B4 DQA1_<29> DQA1_<29> <36>
B28 DQA0_29 DQA1_29 AF2 DQB0_28 DQB1_28 AV11
<36> DQA0_<30> DQA0_<30> A3 DQA1_<30> DQA1_<30> <36>
A28 DQA0_30 DQA1_30 AG1 DQB0_29 DQB1_29 AU11
<36> DQA0_<31> DQA0_<31> B3 DQA1_<31> DQA1_<31> <36>
DQA0_31 DQA1_31 AG2 DQB0_30 DQB1_30 AP11
DQB0_31 DQB1_31
MAA0_<0> G25 E15 MAA1_<0> MAA1_<0> <36>
<36> MAA0_<0> MAA0_0 MAA1_0
MAA0_<1> H25 H15 MAA1_<1> R5 AE7
<36> MAA0_<1> MAA0_1 MAA1_1 MAA1_<1> <36> MAB0_0 MAB1_0
MAA0_<2> E27 G13 MAA1_<2> MAA1_<2> <36> R8 AE8
<36> MAA0_<2> MAA0_2 MAA1_2 MAB0_1 MAB1_1
MAA0_<3> D27 D13 MAA1_<3> MAA1_<3> <36> N7 AG5
MAA0_<4> D29 H11 MAA1_<4> MAA1_<4> <36> N4 AG4
MAA0_<5> H27 H13 MAA1_<5> MAA1_<5> <36> L8 AJ4
MAA0_<6> H23 H17 MAA1_<6> MAA1_<6> <36> N8 AG8
MAA0_<7> E23 G17 MAA1_<7> MAA1_<7> <36> U8 AC8
MAA0_<8> D25 D15 MAA1_<8> MAA1_<8> <36> U7 AC5
B <36> MAA0_<8> MAA0_8 MAA1_8 MAB0_7 MAB1_7 B
H29 E11 R4 AE4
MAA0_9 MAA1_9 L5 MAB0_8 MAB1_8 AJ8
MAB0_9 MAB1_9
<36> WCKA0_0 WCKA0_0 D33 A22 WCKA1_0 WCKA1_0 <36>

E33 WCKA0_0 WCKA1_0 B21 WCKA1b_0 H1 AP1
<36> WCKA0b_0 WCKA0b_0 WCKA1b_0 <36>
WCKA0B_0 WCKA1B_0 J2 WCKB0_0 WCKB1_0 AP2
WCKB0B_0 WCKB1B_0
<36> WCKA0_1 WCKA0_1 A34 A8 WCKA1_1 WCKA1_1 <36>

B34 WCKA0_1 WCKA1_1 B9 AB1 AN4
<36> WCKA0b_1 WCKA0b_1 WCKA1b_1 WCKA1b_1 <36>
WCKA0B_1 WCKA1B_1 AA2 WCKB0_1 WCKB1_1 AN5
WCKB0B_1 WCKB1B_1
<36> EDCA0_0 EDCA0_0 G38 B24 EDCA1_0 EDCA1_0 <36>

F41 EDCA0_0 EDCA1_0 A18 F2 AL1
<36> EDCA0_1 EDCA0_1 EDCA1_1 EDCA1_1 <36>
B37 EDCA0_1 EDCA1_1 B12 M2 EDCB0_0 EDCB1_0 AU2
A31 EDCA0_2 EDCA1_2 B6 V1 EDCB0_1 EDCB1_1 BA6
EDCA0_3 EDCA1_3 AD2 EDCB0_2 EDCB1_2 AV7
EDCB0_3 EDCB1_3
<36> DDBIA0_0 DDBIA0_0 J38 B25 DDBIA1_0 DDBIA1_0 <36>

F40 DDBIA0_0 DDBIA1_0 B18 E2 AK2
<36> DDBIA0_1 DDBIA0_1 DDBIA1_1 DDBIA1_1 <36>
A38 DDBIA0_1 DDBIA1_1 A12 M1 DDBIB0_0 DDBIB1_0 AV1
B30 DDBIA0_2 DDBIA1_2 B5 V2 DDBIB0_1 DDBIB1_1 AY6
DDBIA0_3 DDBIA1_3 AE2 DDBIB0_2 DDBIB1_2 AV9
DDBIB0_3 DDBIB1_3
<36> ADBIA0 ADBIA0 H21 H19 ADBIA1 ADBIA1 <36>
ADBIA0 ADBIA1 W8 AA8
ADBIB0 ADBIB1
<36> CSA0b_0 CSA0b_0 H31 E7 CSA1b_0 CSA1b_0 <36>

CSA0B_0 CSA1B_0 G5 AL8
CSB0B_0 CSB1B_0
C
Vinafix.com <36>
<36>
<36>
CASA0b
RASA0b
WEA0b
CASA0b
RASA0b
WEA0b
D23
D21
G29
CASA0B
RASA0B
WEA0B
CASA1B
RASA1B
WEA1B
D17
D19
D11
CASA1b
RASA1b
WEA1b
CASA1b
RASA1b
WEA1b
<36>
<36>
<36>
+1.35VS_VGA
U4
W4
L4
CASB0B
RASB0B
WEB0B
CASB1B
RASB1B
WEB1B
AC4
AA4
AJ7
C
1
<36> CKEA0 CKEA0 G21 E19 CKEA1 CKEA1 <36>
CKEA0 CKEA1 R3105 W5 AA7
CKEB0 CKEB1
<36> CLKA0 CLKA0 E31 D7 CLKA1 CLKA1 <36> 40.2_0402_1%
D31 CLKA0 CLKA1 D9 DIS@ G4 AL5
<36> CLKA0b CLKA0b CLKA1b CLKA1b <36> CLKB0 CLKB1
CLKA0B CLKA1B J4 AL4
CLKB0B CLKB1B
2
R3101 1 DIS@ 2 120_0402_1% MEM_CALRA K15 K17 MVREFDA
MEM_CALRA MVREFDA R10 U10
MEM_CALRB MVREFDB
2
1
<36> DRAM_RST_A R3113 2 DIS@ 1 51.1_0402_1% R3103 1 DIS@ 2 10_0402_1% DRAM_RST_A_R L32 C3114 R3106
DRAM_RSTA REV 0.91 1U_0402_10V6-K 100_0402_1% AM11
1 DIS@ DIS@ DRAM_RSTB
1 216-0905018-C3_FCBGA769
REV 0.91
1
216-0905018-C3_FCBGA769
2
C3101 R3104
120P_0402_50V8-J 4.99K_0402_1%
2 DIS@ DIS@
2
D D

Issued Date 2015/01/12 Deciphered Date 2016/01/12 R17M-P1-50(B)_VRAM I/F
Size
DocumentNumber
Number Rev
Rev
Custom !!"#$%&'()"*+ 0.2
Date:
Sheet 31 of 99
1 2 3 4 5
5 4 3 2 1
+3VS_VGA
+VDDIO_GPU +VDDIO_GPU <91>
+1.8VS_VGA +1.8VS_VGA <30,34,38>
1
+3VS +3VS <5,6,9,10,11,12,14,15,23,25,30,37,39,40,47,50,51,57,58,59,60,61,63,65,66,67,69,72,85,86>
R32106
+3VS_VGA 10K_0402_5%
+3VS_VGA <30,37,38,39,91> +3VS_VGA
DIS@
2
+3VS_VGA
DV2 R3241 1 @ 2 5.1K_0402_1% GPU_GPIO0
RB751V-40_SOD323-2
DIS@ R3243 1 @ 2 5.1K_0402_1% GPU_GPIO5 R3280 1 @ 2 5.1K_0402_1% DBGDATA[15:0] Debug bus output data
R3276 UV3001E @ 2 1 VGA_AC_DC# VGA_AC_DC# <40>
2 1 +VDDR3 AM31 symbol5 W40 GPU_GPIO0 UV3001K
VDD_33 GPIO_0 AA40 symbol11
0_0402_5%_SM GPIO_1 AA35 GPU_GPIO2 L40 DBGDATA_0 1 @ TV32 PAD
GPIO_2 DBGDATA_0 L41 DBGDATA_1 1 @ TV33 PAD
C3207 DBGDATA_1 M40 DBGDATA_2 1 @ TV34 PAD
D 1U_0402_6.3V6-K AA34 GPU_GPIO5 GPU_GPIO5 DBGDATA_2 M41 DBGDATA_3 1 @ TV35 PAD D
GPIO_5_REG_HOT_AC_BATT GPU_GPIO5 <83> DBGDATA_3
DIS@ U35 GPU_GPIO6_R R32105 2 @ 1 0_0402_5% GPU_GPIO6 GPIO22_ROMCSB R3231 1 2 5.1K_0402_1% N40 DBGDATA_4 1 @ TV36 PAD
GPIO_6_TACH DBGDATA_4 N41 DBGDATA_5 1 @ TV37 PAD
AP25 R3287 1 @ 2 100K_0402_5% R3288 1 @ 2 100K_0402_5% DBGDATA_5 P40 DBGDATA_6 1 @ TV38 PAD
WAKEB#
GPIO_8_ROMSO AM25 DBGDATA_6 P41 1 @ TV39 PAD
DBGDATA_7
GPIO_9_ROMSI AM27 R3232 1 DIS@ 2 5.1K_0402_1% DBGDATA_7 R40
GPU_HSYNC 1 @ TV24 PAD
GPIO_10_ROMSCK W41 DBGDATA_8 R41 1 @ TV25 PAD
GPU_GPIO11
GPIO_11 Y40 R3281 1 DIS@ 2 5.1K_0402_1% DBGDATA_9 T40
GPU_GPIO12 GPU_VSYNC 1 @ TV26 PAD
GPIO_12 Y41 DBGDATA_10 T41 1 @ TV27 PAD
GPU_GPIO13
GPIO_13 AU21 R3249 1 DIS@ 2 5.1K_0402_1% DBGDATA_11 U40 1 @ TV28 PAD
GPIO_14_HPD2 GPU_GPIO11
GPIO_14_HPD2 AA41 DBGDATA_12 U41 1 @ TV29 PAD
GPU_GPIO15
GPIO_15 U34 DBGDATA_13 V40 1 @ TV30 PAD
GPU_GPIO16 GPU_GPIO12 R3235 1 DIS@ 2 5.1K_0402_1%
GPIO_16_8P_DETECT R37 DBGDATA_14 V41 1 @ TV31 PAD
GPU_GPIO17
GPIO_17_THERMAL_INT AV25 R3234 1 DIS@ 2 5.1K_0402_1% DBGDATA_15
GPIO_18_HPD3 GPU_GPIO13
GPIO_18_HPD3 R38 GPIO_19_CTF REV 0.91
GPIO_19_CTF AB40 R3283 1 @ 2 10K_0402_5% 216-0905018-C3_FCBGA769
GPU_GPIO20 GPIO_19_CTF
AC35 GPIO_20 AB41 @
GPU_SCL GPU_GPIO21 GPU_GPIO21 <37>
AC34 SCL GPIO_21 AP27 R3224 1 2 0_0402_5% R3284 1 @ 2 10K_0402_5%
GPU_SDA GPIO22_ROMCSB_R GPIO22_ROMCSB GPU_GPIO30
SDA GPIO_22_ROMCSB W37 GPU_GPIO29
AW40 GPIO_29 W38 R3255 1 DIS@ 2 5.1K_0402_1%
SMBCLK GPU_GPIO30 GPU_GPIO29
AW41 SMBCLK GPIO_30 BA38 1 @ TV44 PAD +1.8VS_VGA
SMBDAT GENERICA
SMBDAT AV29 1 @ TV45 PAD R3237 1 @ 2 5.1K_0402_1%
GPU_GPIO2
GENERICB AU31 1 @ TV46 PAD
GENERICC AV31 1 R3256 1 DIS@ 2 5.1K_0402_1%
@ TV47 PAD GPU_GPIO20
GENERICD AU25 1
GENERICE_HPD4 R3201 DIS@ 2 5.1K_0402_1% DBGDATA_0
AU17 GENERICE_HPD4 AV23 1 2 5.1K_0402_1%
<91> GPU_SVC GPU_SVC GENERICF_HPD5 R3264 @ GPU_GPIO15 R3267 1 @ 2 5.1K_0402_1%
AV17 GPIO_SVC GENERICF_HPD5 AM29
<91> GPU_SVD GPU_SVD GENERICG_HPD6 R3202 1 DIS@ 2 5.1K_0402_1% DBGDATA_1
+1.8VS_VGA +1.8VS_VGA AR17 GPIO_SVD GENERICG +3VS_VGA +3VS_VGA R3263 1 @ 2 5.1K_0402_1%
<91> GPU_SVT GPU_SVT GPU_GPIO16 R3266 1 @ 2 5.1K_0402_1%
GPIO_SVT AV21 R3203 1 DIS@ 2 5.1K_0402_1%
GPU_HPD1 DBGDATA_2
TV40 PAD @ 1 AN34 HPD1 R3265 1 @ 2 5.1K_0402_1% GPU_GPIO21 R3268 1 @ 2 5.1K_0402_1%
TV41 PAD @ 1 AP31 DDCVGACLK R3212 1 X76@ 2 5.1K_0402_1%
R3204 1 X76@ 2 5.1K_0402_1% DBGDATA_3
DDCVGADATA
1
R3285 1 DIS@ 2 4.7K_0201_1% GPU_SCL
2
If VBOS can control,Q3204 can reserves
2
2
R3278 R3205 1 X76@ 2 5.1K_0402_1% DBGDATA_4 R3213 1 X76@ 2 5.1K_0402_1%
G
R3274 R3275 R3279 10K_0402_5% R3286 1 DIS@ 2 4.7K_0201_1% GPU_SDA
10K_0402_5% 10K_0402_5% 0_0402_5% @ R3206 1 X76@ 2 5.1K_0402_1% DBGDATA_5 R3214 1 X76@ 2 5.1K_0402_1%
2
DIS@ DIS@ @ GPU_HPD1 R3257 1 DIS@ 2 10K_0201_5%

G
2
AV40 CLKREQ_PCIE4_VGA#_R 2 1 3 1 CLKREQ_PCIE4_VGA# CLKREQ_PCIE4_VGA# <14> R3207 1 DIS@ 2 5.1K_0402_1% DBGDATA_6
CLKREQB
1
VR_VGA_PWRGD 1 3 AY13 AU40
D
<37,91> VR_VGA_PWRGD WAKEB# GPIO_14_HPD2 R3258 1 DIS@ 2 10K_0201_5%
TEST_PG WAKEB
2
BA13 Q3204 DBGDATA_7 R3216 1 DIS@ 2 5.1K_0402_1%
D
TEST_PG_BACO R3277 2N7002KW_SOT323-3

1 1 GPIO_18_HPD3 R3259 1 DIS@ 2 10K_0201_5%
Q3203 10K_0402_5% @
LBSS139WT1G_SC70-3 C3205 C3206 AC40 @ SB000009Q8J GENERICE_HPD4 R3260 1 DIS@ 2 10K_0201_5%
C @ DIGON C
0.1U_0402_10V6-K 0.1U_0402_10V6-K
1
SB00001FR00 2@ 2@ AC37 GENERICF_HPD5 R3261 1 DIS@ 2 10K_0201_5%
K41 BL_ENABLE AC38
R34 RSVD#K41 BL_PWM_DIM 1 DIS@ 2 10K_0201_5%
RSVD#R34 GENERICG_HPD6 R3262
W34 GPU_HSYNC
HSYNC W35
VSYNC GPU_VSYNC
TABLE of VRAM (UV3201 UV3202)
SWAPLOCKA
AG34
AE34
Vendor P/N LCFC P/N Config need Mount
SWAPLOCKB
GENLK_CLK
AR29
AP29
Samsung K4G80325FB-HC28 SA000081C10 R3212 R3213 R3214
GENLK_VSYNC
Micron MT51J256M32HF-70:A SA000081710 R3204 R3213 R3214
REV 0.91
Synix H5GC8H24MJR-R0C SA000081610 R3212 R3205 R3214
216-0905018-C3_FCBGA769
+3VS_VGA +3VS_VGA
+3VS +1.8VS_VGA +VDDIO_GPU
2
1
R3296 R32102 R32104
10K_0402_5% R3289 47K_0402_1%
GPU_GPIO6 0_0402_5%_SM
@ 2 1 DIS@
1
2
0_0402_5%_SM
2
1
2
2
D Q3205
2 2N7002KW_SOT323-3 1 R3290 R3292 R3294 R3272 @
VGA_AC_DC#
G SB000009Q8J 10K_0402_5% 10K_0402_5% 10K_0402_5% 0_0402_5%
C3211 @ 2 1
2
@ @ DIS@ PLT_RST_VGA# PLT_RST_VGA# <30,91>

R3299 S 47P_0402_50V8-J
1
2@
3
1
1
100K_0402_5% 1
@
C3210 GPU_SVD GPU_SVC GPU_SVT
1
2
0.1U_0201_10V6-K
SVC SVD Output Voltage (V) 2@
G1
2
2
2
B 0 0 1.1 R3291 R3293 R3295 1 6
B
SMBCLK EC_SMB_CK3 <9,40,57,59>
10K_0402_5% 10K_0402_5% 10K_0402_5% S1 D1
0 1 1.0 DIS@ @ @
+3VS_VGA
Q3201A
1
1 0 0.9
1
DIS@ R3270
R3298 1 1 0.8 SB000013A00 0_0402_5%
R3297 +3VS_VGA
10K_0402_5% 0_0402_5% @
@ @ 2 1
2 1 2 1
GPU_GPIO17 GPU_GPIO6
1
R32103
47K_0402_1%
5
DIS@
G2
2
+1.8VS_VGA
SMBDAT 4 3 EC_SMB_DA3 <9,40,57,59>
S2 D2
L3201 Q3201B
U3201 BLM18PG121SN1D_2P L2N7002KDW1T1G_SOT363-6
DIS@ DIS@ DIS@ R3269
6 1 1 2 SB000013A00 0_0402_5% PU AT EC SIDE, +3VS AND 4.7K
VSS VDD
@
5 2 1 2 1
SS_SET SSCLK2/REFCLK_D/OE1/FSEL/SSEL/SSON#/PD#XIN/CLKIN XTALIN 1
UV3001F
+1.8VS_VGA BA39 R3273 1 2 0_0402_5%_SM 4 3 C3209
symbol6 GPU_XTALIN SSCLK1/REFCLK/FSEL/SSEL/SSON#/OE2 XOUT XTALOUT C3208
XTALIN 10U_0402_6.3V6-M 0.1U_0402_10V6-K
SI51214-A1FAGMR_TDFN6_1P2X1P4 2 DIS@ 2 DIS@
1
R3218
+1.8VS_VGA
5.1K_0402_1%
DIS@
Thermal Management
2
UV3001J @
SS_SET symbol10
AY39 GPU_XTALOUT AM13 N35 1 @ TV15 PAD
XTALOUT TSVDD DPLUS GPU_DPLUS
1
R3219 R3271 PAD TV17 @ 1 J8

TEMPIN0 N34 1 @ TV16 PAD
5.1K_0402_1% 1M_0402_5% GPU_DMINUS
AV15 1 TV42 PAD @ DMINUS
@ PLLCHARZ_L PLLCHARZ_L DIS@
AU15 1 TV43 PAD @ PAD TV18 @ 1 J7
A PLLCHARZ_H PLLCHARZ_H 1 2 TEMPINRETURN A
2
R32100
C3201 U38
R32101 0_0402_5% GPIO_28_FDO GPIO_28_FDO
Vinafix.com Y3201 DIS@ 1U_0402_6.3V6-K PAD TV19 @ 1 N38
0_0402_5% @ TS_A
AY38 4 3 DIS@
REV 0.91 NC2 OSC2 XTALIN 1 2 GPU_XTALIN
1
ANALOGIO @ REV 0.91
216-0905018-C3_FCBGA769 1 2 1 2 R3217
GPU_XTALOUT XTALOUT OSC1 NC1 216-0905018-C3_FCBGA769
1
@ 10K_0402_5%
R3220 27MHZ_16PF_7V27000011 @
1 1
16.2K_0402_1%
2
@ C3203 C3204
22P_0402_50V8-J 22P_0402_50V8-J
2
2 DIS@ 2 DIS@
Issued Date 2015/01/12 Deciphered Date 2016/01/12 R17M-P1-50(C/D)_GPIO
Size
Size Document
Number Rev
Rev
Date:
Sheet 32 of 99
5 4 3 2 1
5 4 3 2 1
D D
UV3001G @
symbol7 UV3001H @
AY32 symbol8
TX2P_DPB0P AY22 UV3001O @
BA32 TX2P_DPD0P symbol15
TX2M_DPB0N BA22 AY18
AY31 TX2M_DPD0N TX2P_DPE0P
TX1P_DPB1P AY21 BA18
BA31 TX1P_DPD1P TX2M_DPE0N
TX0P_DPB2P AY20 BA16
BA30 TX0P_DPD2P TX1M_DPE1N
TXCBP_DPB3P AY19 BA15
BA28 TXCDP_DPD3P TX0M_DPE2N
TXCBM_DPB3N BA19 AY14
TXCDM_DPD3N TXCEP_DPE3P
AY11 BA14
AUX1P TXCEM_DPE3N
BA11
AUX1N
C C
AM21
DDCAUX3P AY10
AP21 DDC1CLK
DDCAUX3N BA10 AU27
DDC1DATA DDCAUX5P
AV27
DDCAUX5N
REV 0.91
216-0905018-C3_FCBGA769
AY36
TX5P_DPA0P AY27
BA36 TX5P_DPC0P
TX5M_DPA0N BA27
AY35 TX5M_DPC0N
TX4P_DPA1P AY26
BA35 TX4P_DPC1P
TX4M_DPA1N BA26
AY34 TX4M_DPC1N
TX3P_DPA2P AY25
BA34 TX3P_DPC2P
TX3M_DPA2N BA25
Vinafix.com AY33 TX3M_DPC2N
TXCAP_DPA3P AY24
BA33 TXCCP_DPC3P
TXCAM_DPA3N BA24
TXCCM_DPC3N
B AP19 B
AUX2P
BA12 AM19
AUX_ZVSS AUX2N
1
R3301 DIS@
150_0402_1% AR23
DDCAUX4P AV19
AP23 DDC2CLK
REV 0.91 DDCAUX4N
2
AU19
REV 0.91 DDC2DATA
216-0905018-C3_FCBGA769
216-0905018-C3_FCBGA769
If this interface is not used, all signal outputs can be unconnected. AUX_ZVSS
should always be connected.
Vinafix.com
A A

Issued Date 2015/01/12 Deciphered Date 2016/01/12 R17M-P1-50(E)_DIGITAL OUT
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Rev
Custom
Custom 0.2
0.2
Date: Monday,
Monday, October
October 30,
30, 2017
2017 Sheet
Sheet 33
33 of 99
99
5 4 3 2 1
1 2 3 4 5
+VDDC +VDDC <91>
+VDDCI +VDDCI <91>
+1.35VS_VGA +1.35VS_VGA <31,36,95>
+1.8VS_VGA +1.8VS_VGA <30,32,38>
+VDDC
+VDDCI
A UV3001I @ A
N13 symbol9 L13
N15 VDDC#0 VDDCI#0 L17
1 1 1 1 1 VDDC#1 VDDCI#1
N21 L21 1 1 1 1 1 1
C3407 C3408 C3409 C3410 C3411 N23 VDDC#2 VDDCI#2 L25
1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M N29 VDDC#3 VDDCI#3 L29 C3401 C3402 C3403 C3404 C3405 C3406
2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@ N31 VDDC#4 VDDCI#4 N11 1U_0201_6.3V6-K 1U_0201_6.3V6-K 1U_0201_6.3V6-K 1U_0201_6.3V6-K 22U_0603_6.3V6-M 22U_0603_6.3V6-M
R13 VDDC#5 VDDCI#5 U11 2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@
R15 VDDC#6 VDDCI#6 AA11
R21 VDDC#7 VDDCI#7 AE11
R23 VDDC#8 VDDCI#8
R29 VDDC#9
R31 VDDC#10
U13 VDDC#11
1 1 1 1 1 VDDC#12
U15
C3412 C3413 C3414 C3415 C3416 U21 VDDC#13
1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M U23 VDDC#14
2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@ U29 VDDC#15
U31 VDDC#16
W13 VDDC#17
W15 VDDC#18
W21 VDDC#19
W23 VDDC#20
W29 VDDC#21
W31 VDDC#22
1 1 1 1 1 VDDC#23
AA13
C3417 C3419 C3418 C3421 C3420 AA15 VDDC#24
1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M AA21 VDDC#25
2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@ AA23 VDDC#26
AA29 VDDC#27
AA31 VDDC#28
AC13 VDDC#29
AC15 VDDC#30
AC21 VDDC#31
AC23 VDDC#32
B 1 1 1 1 1 VDDC#33 B
AC29
C3422 C3424 C3423 C3426 C3425 AC31 VDDC#34
1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M AE13 VDDC#35
2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@ AE15 VDDC#36
AE21 VDDC#37
AE23 VDDC#38
AE29 VDDC#39
AE31 VDDC#40
AG13 VDDC#41
AG15 VDDC#42
AG21 VDDC#43
AG23 VDDC#44
1 1 1 1 1 VDDC#45
AG29
C3451 C3450 C3452 C3454 C3453 AG31 VDDC#46
47U_0603_6.3V6-M 47U_0603_6.3V6-M 47U_0603_6.3V6-M 47U_0603_6.3V6-M 47U_0603_6.3V6-M AJ13 VDDC#47
2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@ AJ15 VDDC#48
AJ17 VDDC#49
AJ19 VDDC#50
AJ21 VDDC#51
AJ23 VDDC#52
AJ25 VDDC#53
AJ27 VDDC#54
1 1 1 VDDC#55
AJ29
C3449 C3456 C3455 AJ31 VDDC#56
47U_0603_6.3V6-M 47U_0805_6.3V6-M 47U_0805_6.3V6-M AL13 VDDC#57
2 DIS@ 2 DIS@ 2 DIS@ AL15 VDDC#58
AL17 VDDC#59
AL19 VDDC#60
AL21 VDDC#61
AL23 VDDC#62
Vinafix.com AL25 VDDC#63 C3 FBVDD_VCC_SENSE 1 PAD TV54 @
AL27 VDDC#64 FB_VMEMIO AV13 GPU_VDDCI_SENSE
VDDC#65 FB_VDDCI GPU_VDDCI_SENSE <91>
AL29 AR13 GPU_VDDC_SENSE GPU_VDDC_SENSE <91>
VDDC#66 FB_VDDC AU13 GPU_VSSC_SENSE
AL31 GPU_VSSC_SENSE <91>
C VDDC#67 FB_VSS C
REV 0.91
216-0905018-C3_FCBGA769
+1.35VS_VGA
+1.8VS_VGA
UV3001N @
symbol14
K11 AM15
K13 VMEMIO#0 VDD_18#0 AP15
1 1 1 1 1 VMEMIO#1 VDD_18#1
K19 AR15 1 1 1
C3434 K23 VMEMIO#2 VDD_18#2
C3435 C3436 C3437 C3438
1U_0201_6.3V6-M K27 VMEMIO#3
1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M C3446 C3448 C3447
2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@ K31 VMEMIO#4
1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M
L10 VMEMIO#5 2 DIS@ 2 DIS@ 2 DIS@ +VDDCI
N10 VMEMIO#6
W10 VMEMIO#7
AC10 VMEMIO#8
AG10 VMEMIO#9
VMEMIO#10 AC32
VDD_08#0 AG32
1 1 1 1 1 VDD_08#1 AG35 1 1 1 1 1
VDD_08#2 1 1
C3439 C3441 C3440 C3443 C3442 AJ32
1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M VDD_08#3 AJ34
1U_0201_6.3V6-M 1U_0201_6.3V6-M C3427 C3428 C3429 C3430 C3431 C3432 C3433
2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@ VDD_08#4 AL34 1U_0201_6.3V6-K
1U_0201_6.3V6-K 1U_0201_6.3V6-K 1U_0201_6.3V6-K 1U_0201_6.3V6-K 1U_0201_6.3V6-K 1U_0201_6.3V6-K
VDD_08#5 2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@
W32
VDD_08
AM23
VSS#227 AM17
VSS#228
1 1 REV 0.91
C3444 C3445
216-0905018-C3_FCBGA769
22U_0603_6.3V6-M 22U_0603_6.3V6-M
D 2 DIS@ 2 DIS@ D

Issued Date 2015/01/12 Deciphered Date 2016/01/12 R17M-P1-50(F)_PWR
Size
Document Number
Number Rev
Rev
Custom 0.2
Date:
Sheet 34 of 99
1 2 3 4 5
1 2 3 4 5
A A
UV3001L @ UV3001M @
symbol12 symbol13
A2 J39 AA5 AN40
A5 VSS#0 VSS#58 J40 AA10 VSS#115 VSS#171 AN41
A9 VSS#1 VSS#59 J41 AA17 VSS#116 VSS#172 AP13
A13 VSS#2 VSS#60 K21 AA19 VSS#117 VSS#173 AP17
A17 VSS#3 VSS#61 K25 AA25 VSS#118 VSS#174 AR3
A29 VSS#6 VSS#64 L3 AA39 VSS#121 VSS#177 AR19
A33 VSS#7 VSS#65 L7 AC3 VSS#122 VSS#178 AR21
B1 VSS#10 VSS#68 L19 AC17 VSS#125 VSS#181 AR31
C5 VSS#13 VSS#71 L31 AC27 VSS#128 VSS#184 AU1
C7 VSS#14 VSS#72 L35 AC39 VSS#129 VSS#185 AU3
C9 VSS#15 VSS#73 L39 AE1 VSS#130 VSS#186 AU9
C11 VSS#16 VSS#74 N1 AE3 VSS#131 VSS#187 AU23
C13 VSS#17 VSS#75 N3 AE5 VSS#132 VSS#188 AU29
B C15 VSS#18 VSS#76 N5 AE10 VSS#133 VSS#189 B
AW3
C17 VSS#19 VSS#77 N17 AE17 VSS#134 VSS#190 AW5
C27 VSS#24 VSS#82 N37 VSS#139 VSS#195
AE35 AW15
C29 VSS#25 VSS#83 N39 VSS#140 VSS#196
AE39 AW17
C31 VSS#26 VSS#84 R3 VSS#141 VSS#197
AG3 AW19
C33 VSS#27 VSS#85 R7 VSS#142 VSS#198
AG7 AW21
C35 VSS#28 VSS#86 R11 VSS#143 VSS#199
AG11 AW23
C37 VSS#29 VSS#87 R17 VSS#144 VSS#200
AG17 AW25
C39 VSS#30 VSS#88 R19 VSS#145 VSS#201
AG19 AW27
E1 VSS#31 VSS#89 R25 VSS#146 VSS#202
AG25 AW29
E3 VSS#32 VSS#90 R27 VSS#147 VSS#203
AG27 AW31
E4 VSS#33 VSS#91 R32 VSS#148 VSS#204
AG39 AW33
E9 VSS#34 VSS#92 R35 VSS#149 VSS#205
AG40 AW35
E13 VSS#35 VSS#93 R39 VSS#150 VSS#206
AG41 AW37
E17 VSS#36 VSS#94 U1 VSS#151 VSS#207
AJ1 AW39
E21 VSS#37 VSS#95 U3 VSS#152 VSS#208
AJ3 AY1
E25 VSS#38 VSS#96 U5 VSS#153 VSS#209
AJ5 AY2
E29 VSS#39 VSS#97 U17 VSS#154 VSS#210
AJ10 AY9
E39 VSS#40 VSS#98 U19 VSS#155 VSS#211
AJ11 AY12
E41 VSS#41 VSS#99 U25 VSS#156 VSS#212
AJ35 AY17
G3 VSS#42 VSS#100 U27 VSS#157 VSS#213
AJ39 AY23
G7 VSS#43 VSS#101 U32 VSS#158 VSS#214
AL3 AY29
G11 VSS#44 VSS#102 U37 VSS#159 VSS#215
AL7 AY37
G15 VSS#45 VSS#103 U39 VSS#160 VSS#216
Vinafix.com AL10 AY40
G19 VSS#46 VSS#104 W3 VSS#161 VSS#217
AL11 AY41
G23 VSS#47 VSS#105 W7 VSS#162 VSS#218
AL32 BA2
G27 VSS#48 VSS#106 W11 VSS#163 VSS#219
AL35 BA5
G31 VSS#49 VSS#107 W17 VSS#164 VSS#220
AL39 BA9
C G35 VSS#50 VSS#108 W19 VSS#165 VSS#221 C
AN1 BA17
G39 VSS#51 VSS#109 W25 VSS#166 VSS#222
AN3 BA23
J1 VSS#52 VSS#110 W27 VSS#167 VSS#223
AN7 BA29
J3 VSS#53 VSS#111 VSS#168 VSS#224
W39 AN35 BA37
J5 VSS#54 VSS#112 VSS#169 VSS#225
AA1 AN39 BA40
J34 VSS#55 VSS#113 VSS#170 VSS#226
AA3
J37 VSS#56 VSS#114
VSS#57
REV 0.91
REV 0.91
216-0905018-C3_FCBGA769
216-0905018-C3_FCBGA769
D D

Issued Date 2015/01/12 Deciphered Date 2016/01/12 R17M-P1-50(G)_VSS
Size
Size Document
Number Rev
Rev
Custom 0.2
Date:
30, 2017
2017 Sheet
Sheet 35 of 99
1 2 3 4 5
1 2 3 4 5
+1.35VS_VGA +1.35VS_VGA <31,34,95>

+1.35VS_VGA
R3619 1 DIS@ 2 60.4_0402_1% CLKA0
R3620 1 DIS@ 2 60.4_0402_1% CLKA0b
R3622 1 DIS@ 2 60.4_0402_1% CLKA1b
R3621 1 DIS@ 2 60.4_0402_1% CLKA1
+1.35VS_VGA
1
UV3601
R3607 UV3602
A 2.37K_0402_1% MF=0 MF=1 MF=1 MF=0 A
@ +1.35VS_VGA MF=0 MF=1 MF=1 MF=0
A4 DQA0_<8> DQA0_<8> <31>
DQ24 DQ0
2
VREFD1_A0 EDCA0_1 C2 A2 DQA0_<9> DQA0_<9> <31> A4 DQA1_<5> DQA1_<5> <31>

<31> EDCA0_1 EDC0 EDC3 DQ25 DQ1 DQ24 DQ0
EDCA0_0 C13 B4 DQA0_<11> DQA0_<11> <31> EDCA1_0 C2 A2 DQA1_<3> DQA1_<3> <31>
<31> EDCA0_0 EDC1 EDC2 DQ26 DQ2 <31> EDCA1_0 EDC0 EDC3 DQ25 DQ1
1
<31> EDCA0_2 EDCA0_2 R13
EDC2 EDC1 DQ27 DQ3
B2 DQA0_<10> DQA0_<10> <31> BYTE0 <31> EDCA1_1 EDCA1_1 C13
EDC1 EDC2 DQ26 DQ2
B4 DQA1_<4> DQA1_<4> <31>
1 <31> EDCA0_3 EDCA0_3 R2
EDC3 EDC0 DQ28 DQ4
E4 DQA0_<14> DQA0_<14> <31> R3615 <31> EDCA1_2 EDCA1_2 R13
EDC2 EDC1 DQ27 DQ3
B2 DQA1_<2> DQA1_<2> <31> BYTE4
1
E2 DQA0_<12> DQA0_<12> <31> 2.37K_0402_1% EDCA1_3 R2 E4 DQA1_<7> DQA1_<7> <31>

DQ29 DQ5 <31> EDCA1_3 EDC3 EDC0 DQ28 DQ4
R3608 C3635 F4 DQA0_<15> DQA0_<15> <31> @ E2 DQA1_<1> DQA1_<1> <31>
DQ30 DQ6 DQ29 DQ5 F4
5.49K_0402_1% 1U_0201_6.3V6-M <31> DDBIA0_1 DDBIA0_1 D2 F2 DQA0_<13> DQA0_<13> <31> DQA1_<6> DQA1_<6> <31>
2@ DBI0# DBI3# DQ31 DQ7 DQ30 DQ6
2
@ DDBIA0_0 D13 A11 DQA0_<0> DQA0_<0> <31> VREFD1_A1 DDBIA1_0 D2 F2 DQA1_<0> DQA1_<0> <31>
<31> DDBIA0_0 DBI1# DBI2# DQ16 DQ8 <31> DDBIA1_0 DBI0# DBI3# DQ31 DQ7
DDBIA0_2 P13 A13 DQA0_<2> DQA0_<2> <31> <31> DDBIA1_1 DDBIA1_1 D13 A11 DQA1_<9> DQA1_<9> <31>
<31> DDBIA0_2 DBI2# DBI1# DQ17 DQ9 DBI1# DBI2# DQ16 DQ8
2
<31> DDBIA0_3 DDBIA0_3 P2 B11 DQA0_<1> DQA0_<1> <31> <31> DDBIA1_2 DDBIA1_2 P13 A13 DQA1_<10> DQA1_<10> <31>
DBI3# DBI0# DQ18 DQ10 DBI2# DBI1# DQ17 DQ9
DQ19 DQ11
B13 DQA0_<3> DQA0_<3> <31> BYTE1 1 <31> DDBIA1_3 DDBIA1_3 P2
DBI3# DBI0# DQ18 DQ10
B11 DQA1_<8> DQA1_<8> <31>
BYTE5
1
CLKA0 J12 E11 DQA0_<7> DQA0_<7> <31> B13 DQA1_<11> DQA1_<11> <31>
<31> CLKA0 CK DQ20 DQ12 DQ19 DQ11
CLKA0b J11 E13 DQA0_<4> DQA0_<4> <31> R3616 C3639 CLKA1 J12 E11 DQA1_<14> DQA1_<14> <31>
<31> CLKA0b CK# DQ21 DQ13 <31> CLKA1 CK DQ20 DQ12
CKEA0 J3 F11 DQA0_<6> DQA0_<6> <31> 5.49K_0402_1% 1U_0201_6.3V6-M CLKA1b J11 E13 DQA1_<12> DQA1_<12> <31>
+1.35VS_VGA <31> CKEA0 CKE# DQ22 DQ14 2@ <31> CLKA1b CK# DQ21 DQ13
F13 DQA0_<5> DQA0_<5> <31> @ CKEA1 J3 F11 DQA1_<15> DQA1_<15> <31>
DQ23 DQ15 <31> CKEA1 CKE# DQ22 DQ14
U11 DQA0_<23> DQA0_<23> <31> F13 DQA1_<13> DQA1_<13> <31>
DQ8 DQ16 DQ23 DQ15
2
MAA0_<2> H11 U13 DQA0_<21> DQA0_<21> <31> U11 DQA1_<21> DQA1_<21> <31>
<31> MAA0_<2> BA0/A2 BA2/A4 DQ9 DQ17 DQ8 DQ16
MAA0_<5> K10 T11 DQA0_<22> DQA0_<22> <31> MAA1_<4> H11 U13 DQA1_<23> DQA1_<23> <31>
<31> MAA0_<5> BA1/A5 BA3/A3 DQ10 DQ18 <31> MAA1_<4> BA0/A2 BA2/A4 DQ9 DQ17
BYTE2 K10
1
<31> MAA0_<4> MAA0_<4> K11 T13 DQA0_<20> DQA0_<20> <31> <31> MAA1_<3> MAA1_<3> T11 DQA1_<20> DQA1_<20> <31>
BA2/A4 BA0/A2 DQ11 DQ19 K11 BA1/A5 BA3/A3 DQ10 DQ18 T13
R3609 <31> MAA0_<3> MAA0_<3> H10 N11 DQA0_<19> DQA0_<19> <31> <31> MAA1_<2> MAA1_<2> DQA1_<22> DQA1_<22> <31>
BA3/A3 BA1/A5 DQ12 DQ20 BA2/A4 BA0/A2 DQ11 DQ19
2.37K_0402_1%
DQ13 DQ21
N13 DQA0_<18> DQA0_<18> <31> +1.35VS_VGA <31> MAA1_<5> MAA1_<5> H10
BA3/A3 BA1/A5 DQ12 DQ20
N11 DQA1_<16> DQA1_<16> <31> BYTE6
@ M11 DQA0_<16> DQA0_<16> <31> N13 DQA1_<18> DQA1_<18> <31>
DQ14 DQ22 DQ13 DQ21 M11
<31> MAA0_<7> MAA0_<7> K4 M13 DQA0_<17> DQA0_<17> <31> DQ14 DQ22 DQA1_<17> DQA1_<17> <31>
A8/A7 A10/A0 DQ15 DQ23
2
VREFD2_A0 <31> MAA0_<1> MAA0_<1> H5 U4 DQA0_<26> DQA0_<26> <31> <31> MAA1_<0> MAA1_<0> K4 M13 DQA1_<19> DQA1_<19> <31>
A9/A1 A11/A6 DQ0 DQ24 H5 A8/A7 A10/A0 DQ15 DQ23 U4
<31> MAA0_<0> MAA0_<0> H4 U2 DQA0_<28> DQA0_<28> <31> <31> MAA1_<6> MAA1_<6> A9/A1 A11/A6 DQ0 DQ24 DQA1_<30> DQA1_<30> <31>
A10/A0 A8/A7 DQ1 DQ25
1
<31> MAA0_<6> MAA0_<6> K5 T4 DQA0_<27> DQA0_<27> <31> <31> MAA1_<7> MAA1_<7> H4 U2 DQA1_<29> DQA1_<29> <31>
A11/A6 A9/A1 DQ2 DQ26 R3617 K5 A10/A0 A8/A7 DQ1 DQ25 T4
1 <31> MAA0_<8> MAA0_<8> J5 T2 DQA0_<29> DQA0_<29> <31> <31> MAA1_<1> MAA1_<1> A11/A6 A9/A1 DQ2 DQ26 DQA1_<28> DQA1_<28> <31>
A12/RFU/NC DQ3 DQ27 BYTE3 J5 T2
1
N4 DQA0_<25> DQA0_<25> <31> 2.37K_0402_1% <31> MAA1_<8> MAA1_<8> DQA1_<31> DQA1_<31> <31>
DQ4 DQ28 A12/RFU/NC DQ3 DQ27
R3610 C3636 A5
VPP/NC1 DQ5 DQ29
N2 DQA0_<30> DQA0_<30> <31> @
DQ4 DQ28
N4 DQA1_<24> DQA1_<24> <31> BYTE7
5.49K_0402_1% 1U_0201_6.3V6-M U5 M4 DQA0_<24> DQA0_<24> <31> A5 N2 DQA1_<27> DQA1_<27> <31>
VPP/NC2 VPP/NC1 DQ5 DQ29
2
@ 2@ DQ6 DQ30 M2 DQA0_<31> U5 M4
DQA0_<31> <31> VREFD2_A1 VPP/NC2 DQ6 DQ30 DQA1_<25> DQA1_<25> <31>
DQ7 DQ31 +1.35VS_VGA M2
DQ7 DQ31 DQA1_<26> DQA1_<26> <31>
+1.35VS_VGA
2
R3603 2 DIS@ 1 1K_0402_1% J1

R3601 2 DIS@ 1 1K_0402_1% MF J1 +1.35VS_VGA
J10 1 R3606 2 DIS@ 1 1K_0402_1% MF
R3602 2 DIS@ 1 121_0402_1% SEN R3604 2 DIS@ 1 1K_0402_1% J10
1
J13 B1
ZQ VDDQ1 J13 SEN B1
D1 R3618 C3640 R3605 2 DIS@ 1 121_0402_1%
VDDQ2 ZQ VDDQ1 D1
F1 5.49K_0402_1% 1U_0201_6.3V6-M
VDDQ3 2@ VDDQ2 F1
<31> ADBIA0 ADBIA0 J4 M1 @
+1.35VS_VGA ABI# VDDQ4 J4 VDDQ3 M1
<31> RASA0b RASA0b G3 P1 <31> ADBIA1 ADBIA1
RAS# CAS# VDDQ5 G3 ABI# VDDQ4 P1
2
<31> CSA0b_0 CSA0b_0 G12 T1 <31> CASA1b CASA1b
CS# WE# VDDQ6 G12 RAS# CAS# VDDQ5 T1
<31> CASA0b CASA0b L3 G2 <31> WEA1b WEA1b
CAS# RAS# VDDQ7 L3 CS# WE# VDDQ6 G2
<31> WEA0b WEA0b L12 L2 <31> RASA1b RASA1b
WE# CS# VDDQ8 CAS# RAS# VDDQ7
1
B3 CSA1b_0 L12 L2
VDDQ9 <31> CSA1b_0 WE# CS# VDDQ8
R3611 D3 B3
2.37K_0402_1% VDDQ10 VDDQ9 D3
B F3 VDDQ10 B
DIS@ D5 VDDQ11 H3 +1.35VS_VGA F3
<31> WCKA0b_0 WCKA0b_0 WCK01# WCK23# VDDQ11
D4 VDDQ12 K3 D5 H3
<31> WCKA0_0 WCKA0_0 <31> WCKA1b_0 WCKA1b_0 WCK01# WCK23# VDDQ12
2
WCK01 WCK23 VDDQ13 M3 D4 K3

VREFC_A0 <31> WCKA1_0 WCKA1_0 WCK01 WCK23 VDDQ13
P5 VDDQ14 P3 M3
<31> WCKA0b_1 WCKA0b_1 WCK23# WCK01# VDDQ14
VDDQ15 P5 P3
1
<31> WCKA0_1 WCKA0_1 P4 T3 <31> WCKA1b_1 WCKA1b_1 WCK23# WCK01#
WCK23 WCK01 VDDQ16 P4 VDDQ15 T3
1 E5 R3613 <31> WCKA1_1 WCKA1_1 WCK23 WCK01 VDDQ16
VDDQ17 E5
1
N5 2.37K_0402_1% VDDQ17
A10 VDDQ18 E10 N5
R3612 C3637 VREFD1_A0 VREFD1 DIS@ VDDQ18
U10 VDDQ19 N10 A10 E10
5.49K_0402_1% 1U_0201_6.3V6-M VREFD2_A0 VREFD2 VREFD1_A1 VREFD1 VDDQ19
2 DIS@ VDDQ20 U10 N10
2
DIS@ VREFC_A0 J14 B12 VREFC_A1 VREFD2_A1 VREFD2 VDDQ20
VREFC VDDQ21 D12 J14 B12
VDDQ22 VREFC_A1 VREFC VDDQ21 D12
2
F12 VDDQ22
VDDQ23 H12 F12
VDDQ24 1 VDDQ23 H12
J2
1
<31> DRAM_RST_A DRAM_RST_A K12 VDDQ24
RESET# VDDQ25 J2 K12
M12 R3614 C3638 DRAM_RST_A RESET# VDDQ25
VDDQ26 P12 M12
5.49K_0402_1% 1U_0201_6.3V6-M VDDQ26
VDDQ27 T12 2 DIS@ P12
VDDQ28 DIS@ VDDQ27
G13 T12
VDDQ29 VDDQ28 G13
2
H1 L13 VDDQ29
K1 VSS1 VDDQ30 B14 H1 L13
VSS2 VDDQ31 K1 VSS1 VDDQ30 B14
B5 D14 VSS2 VDDQ31
G5 VSS3 VDDQ32 F14 B5 D14
VSS4 VDDQ33 G5 VSS3 VDDQ32 F14
L5 M14 VSS4 VDDQ33
T5 VSS5 VDDQ34 P14 L5 M14
VSS6 VDDQ35 T5 VSS5 VDDQ34 P14
B10 T14 VSS6 VDDQ35
D10 VSS7 VDDQ36 B10 T14
VSS8 D10 VSS7 VDDQ36
G10 VSS8
L10 VSS9 A1 G10
VSS10 VSSQ1 L10 VSS9 A1
P10 C1 VSS10 VSSQ1
T10 VSS11 VSSQ2 E1 P10 C1
VSS12 VSSQ3 T10 VSS11 VSSQ2 E1
H14 N1 VSS12 VSSQ3
VSS13 VSSQ4 R1 H14 N1
+1.35VS_VGA K14 VSS13 VSSQ4
VSS14 VSSQ5 U1 K14 R1
VSSQ6 +1.35VS_VGA VSS14 VSSQ5 U1
H2 VSSQ6
G1 VSSQ7 K2 H2
VDD1 VSSQ8 G1 VSSQ7 K2
L1 A3 VDD1 VSSQ8
G4 VDD2 VSSQ9 L1 A3
C3 VDD2 VSSQ9
L4 VDD3 VSSQ10 G4 C3
E3 VDD3 VSSQ10
C5 VDD4 VSSQ11 L4 E3
N3 VDD4 VSSQ11
R5 VDD5 VSSQ12 C5 N3
R3 VDD5 VSSQ12
C10 VDD6 VSSQ13 R5 R3
U3 VDD6 VSSQ13
R10 VDD7 VSSQ14 C10 U3
C4 VDD7 VSSQ14
D11 VDD8 VSSQ15 R10 C4
R4 VDD8 VSSQ15
VDD9 VSSQ16 D11 R4
G11 F5 VDD9 VSSQ16
L11 VDD10 VSSQ17 M5 G11 F5
VDD11 VSSQ18 L11 VDD10 VSSQ17 M5
P11 F10 VDD11 VSSQ18
C G14 VDD12 VSSQ19 M10 P11 F10 C
VDD13 VSSQ20 G14 VDD12 VSSQ19 M10
L14 C11 VDD13 VSSQ20
VDD14 VSSQ21 R11 L14 C11
VSSQ22 VDD14 VSSQ21 R11
A12 VSSQ22
VSSQ23 C12 A12
VSSQ24 VSSQ23 C12
E12 VSSQ24
VSSQ25 N12 E12
VSSQ26 VSSQ25 N12
R12 VSSQ26
Vinafix.com 170-BALL VSSQ27 U12 R12
VSSQ28 170-BALL VSSQ27 U12
H13 VSSQ28
SGRAM GDDR5 VSSQ29 K13 H13
VSSQ30 SGRAM GDDR5 VSSQ29 K13
A14 VSSQ30
VSSQ31 C14 A14
VSSQ32 VSSQ31 C14
E14 VSSQ32
VSSQ33 N14 E14
VSSQ34 VSSQ33 N14
R14 VSSQ34
VSSQ35 U14 R14
VSSQ36 VSSQ35 U14
VSSQ36
X76@
H5GQ1H24AFR-T2L_BGA170
H5GQ1H24AFR-T2L_BGA170 X76@
<Part Number>
<Part Number>
+1.35VS_VGA
+1.35VS_VGA
UV3601 SIDE UV3602 SIDE
1 1
1 1 1 1 1 1 1
C3633 C3634
1 C3606 C3601 C3602 C3603 C3604 C3605 C3632
1 1 1 1 1 1 1 1 1U_0201_6.3V6-M 1U_0201_6.3V6-M
10U_0402_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M2 DIS@ 2 DIS@
C3616 2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@
C3622 C3612 C3613 C3614 C3615 C3626 C3628 C3627
10U_0402_6.3V6-M
2 DIS@ 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M
2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@
+1.35VS_VGA +1.35VS_VGA
UV3602 SIDE
UV3601 SIDE
D D
1 1 1 1
1 1 1 1
1 1 C3608 C3609 C3610 C3611
1 1 1 C3607 C3629 C3630 C3631
1 1 1 0.1U_0201_10V6-K 0.1U_0201_10V6-K 0.1U_0201_10V6-K 0.1U_0201_10V6-K
C3617 C3623 0.1U_0201_10V6-K 2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@ 0.1U_0201_10V6-K 0.1U_0201_10V6-K 0.1U_0201_10V6-K
C3618 C3619 C3624 2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@
0.1U_0201_10V6-K C3620 C3621 0.1U_0201_10V6-K 0.1U_0201_10V6-K C3625
0.1U_0201_10V6-K 0.1U_0201_10V6-K
2 DIS@ 2 DIS@ 2 DIS@ 0.1U_0201_10V6-K 0.1U_0201_10V6-K 2
DIS@ 2 DIS@ 0.1U_0201_10V6-K
2 DIS@ 2 DIS@ 2 DIS@

Issued Date Deciphered Date 2016/01/12 DDR5
DDR5 VRAM
VRAM
2015/01/12
2015/01/12 2016/01/12
Size
Document Number
Size Document
Document Number
Number
Rev
Rev
Rev
Custom
Custom !!"#$%&'()"*+ 0.2
0.2
Date: Sheet of
1 2 3 4 Date:
Date: 5 Monday,
Monday, October
October 30,
30, 2017
2017 Sheet
Sheet 36
36 99
99
1 2 3 4 5
+3VS_VGA +3VS_VGA <30,32,38,39,91> +3VS +3VS <5,6,9,10,11,12,14,15,23,25,30,32,39,40,47,50,51,57,58,59,60,61,63,65,66,67,69,72,85,86>

+3VS
2
R3707 @
10K_0402_5%
1
VGA_ON R3705 2 DIS@ 1 1K_0402_1% 1.8V_EN
<10,39> VGA_ON 1.8V_EN <38>
1
1
R3703 C3703
10K_0402_5% 0.1U_0402_25V6-K
@ 2 DIS@
A A
2
D3701
RB751V-40_SOD323-2
@
1 2
R3706 1 DIS@ 2 1K_0402_1% VDDCI_EN

VDDCI_EN <91>
1
R3702 C3701
10K_0402_5% 0.1U_0402_25V6-K
@ 2 DIS@
2
R3704 1 DIS@ 2 30K_0402_1% FB_PWR_EN
FB_PWR_EN <95>
1
1
R3701 C3702
10K_0402_5% 0.1U_0402_25V6-K
@ DIS@
2
2
B +3VS_VGA +3VS_VGA +3VS_VGA B
2
R3709 R3710 R3708
100K_0402_5% 100K_0402_5% 10K_0402_5%
DIS@ DIS@ DIS@
1
1
VR_VGA_PWRGD 2
<32,91> VR_VGA_PWRGD 1 DGPU_PWROK DGPU_PWROK <10>
+1.35VSP_PWRGD 3
<95> +1.35VSP_PWRGD
D3703
+3VS_VGA BAT54AW_SOT323-3
DIS@
1
R3711
100K_0402_5%
DIS@
2
+1.8V_PGOOD 1 2
<38> +1.8V_PGOOD
D3704
RB751V-40_SOD323-2
DIS@
<91>
Vinafix.com
VDDC_IMON_PCC
R3717 1 @
0_0402_5%
2 VDDC_IMON_PCC_R 1
3
U3703
+IN
V-
V+
5
4
1
C3704
.01U_0402_16V7-K
2@
R3712 1 @
+3VS_VGA
2
C3705
0.1U_0402_10V7-K
@
2 649K_0402_1% R3715 1 @ 2 10M_0402_5%

R3718 1 @
1
U3702
2 0_0402_5%
5
GPU_GPIO21
+3VS_VGA
<32> PCC circuit
C
1 -IN OUT OUT VCC

C3708
100P_0201_50V8-J 2
@ OPA348AIDCKR_SO5 R3714 GND
2 @ 1 2 3 4
IN+ IN- +3VS_VGA
280K_0402_1% TLV3201AIDBVR_SOT23-5 C3707
@ 1U_0402_6.3V6-K
@ @
1
R3713
R3719 1 @ 2 0_0402_5% 13.3K_0402_1%
@
2
1
1
PCC 60A >> R3213 = 13.3K ohm, R3216 = 10.2K ohm R3716
10.2K_0402_1% C3706
PCC 72A >> R3213 = 11.5K ohm, R3216 = 10.2K ohm @ 1000P_0201_50V7-K
2 @
2
D D

Issued Date 2015/01/12 Deciphered Date 2016/01/12 DDR5 VRAM BLANK
Size Document
Document Number
Number Rev
Rev
C 0.2
Date:
Sheet 37 of 99
1 2 3 4 5
5 4 3 2 1
+3VS_VGA +3VS_VGA <30,32,37,39,91>
+5VALW +5VALW <39,42,43,47,64,66,67,71,72,84,85,86,87,88,89,91,93,94>
+1.8VALW +1.8VALW <19,93>
+1.8VS_VGA +1.8VS_VGA <30,32,34>
D D
+1.8VALW to +1.8VS_VGA
+3VS_VGA +5VALW +1.8VALW +1.8VS_VGA +3VS_VGA +3VS_VGA
2
R3804
2
4.7K_0402_5%
1
R3806 DIS@
PJ5904 @ 100K_0402_5%
1
JUMP_43X39 DIS@
1
+1.8V_PGOOD
2
+1.8V_PGOOD <37>
2
C D C
1
Q3803
2 2N7002WT1G_1N_SC-70-3
G DIS@
R3805 S SB00000YY00
3
2.2K_0402_5%
1
1
C
R3803 R3801
40 mils 3 1
40 mils 1
DIS@
2 2
A. Vth = 2.5V (MAX)
D
10K_0402_5% 47K_0402_5% B Q3804 B. Id = 340 mA (MAX)
@ DIS@ R3802 Q3801 E MLMBT3904WT1G NPN SOT323-3
C. Vth in schematic = 3.3V
3
10K_0402_5% AO3413_SOT23-3 DIS@
G
2
2
DIS@ DIS@
1.8V_EN# 1 2 SB93413000J !"#$#%&'(#)#*&*+#$#,&,,,'-
1
!"#.#/01#$#,&,,,'#.#%*,##$#,&,23-
D
1
1
!4#$#5(67(61589:;;#)#<6#$#5=&=7,&*>;#)#%,,,,,#$#,&,,,,,=,>
1.8V_EN 2 Q3802 C3801 R3807
<37> 1.8V_EN G 2N7002WT1G_1N_SC-70-3 .01U_0402_16V7-K 100K_0402_5% !"#.#/01#?#!4#777#@AB######5C+#;#
S DIS@ 2 DIS@ @
3
SB000019400
2
B B
A
Vinafix.com Security Classification LC Future Center Secret Data Title
A
Issued Date 2015/01/12 Deciphered Date 2016/01/12 DC V TO 1.5VS_VGA/1.8VS_VGA

Size
Document Number
Number Rev
Rev
Custom 0.2
Date:
Sheet 38 of 99
5 4 3 2 1
1 2 3 4 5
+3VS_VGA +3VS_VGA <30,32,37,38,91>
+5VALW +5VALW <38,42,43,47,64,66,67,71,72,84,85,86,87,88,89,91,93,94>
+3VS +3VS <5,6,9,10,11,12,14,15,23,25,30,32,37,40,47,50,51,57,58,59,60,61,63,65,66,67,69,72,85,86>
A A
B +3VS to +3VS_VGA B
+5VALW +3VS
+3VS_VGA
1
JV3
R3901 3 1 +3VS_VGA_D 1 2
D
47K_0402_5% 1 2
DIS@ Q3901 JUMP_43X39
AO3413_SOT23-3 @
G
2
2
DIS@
SB93413000J
2
2
R3902 C3901 R3911
10K_0402_5% .01U_0402_16V7-K 150K_0402_1%
DIS@ 2 DIS@ DIS@
1
1
R3903
DGPU_PWREN# 10K_0402_5%
D
3
Vinafix.com DIS@
5 2 1 DGPU_PWREN#
G
R3904 D
6
S Q3902B
4
<10,37> VGA_ON VGA_ON 1 2 2 Q3902A L2N7002KDW1T1G_SOT363-6
C G L2N7002KDW1T1G_SOT363-6 DIS@ C
0_0402_5%_SM S DIS@ SB000013A00
1
1
SB000013A00
R3905
100K_0402_5% VDS=60
Discharge Circuit
@
VGS=20
Id=320mA
2
D D

Issued Date 2015/01/12 Deciphered Date 2016/01/12 DC V TO 3VS_VGA/0.95VS_VGA
Size
Size Document
Number Rev
Rev
Custom 0.2
Date:
Sheet 39 of 99
1 2 3 4 5
5 4 3 2 1
+3VL_EC
+3VL +3VL <19,42,50,67,72,80,82,83,84> +3VL +3VL_EC +3VL_AVCC
PM_SLP_S3# 1 TP939 @
+3VALW +3VALW <6,9,12,15,19,50,58,60,63,65,66,67,72,83,84,91,95> All capacitors close to EC +3VALW
+3VS L4001 PM_SLP_S4# 1 TP940 @
+3VS <5,6,9,10,11,12,14,15,23,25,30,32,37,39,47,50,51,57,58,59,60,61,63,65,66,67,69,72,85,86> R4004
BLM18PG121SN1D_2P
1 2 1 2 PM_SLP_S5# 1 TP941 @
1
1 1 1 1 1 1
0_0603_5%_SM 1 1 PBTN_OUT# 1 TP942 @ R4001
C4001 C4002 C4003 C4004 C4005 C4006 10K_0402_1%
C4007 C4008 0.1U_0402_25V6-K 0.1U_0402_25V6-K 0.1U_0402_25V6-K 0.1U_0402_25V6-K 0.1U_0402_25V6-K 0.1U_0402_25V6-K KSI6 1 TP4304 @
1000P_0402_50V7-K 0.1U_0402_25V6-K 2 2 2 2 2@ 2@ R4002
2 2
2
KSI7 1 TP4302 @ 15K_0402_1%
TEMBER_DETECT# 1 2
HDD_DETECT# <61>
R4003
EC_AGND 33K_0402_1%
1 2
D SSD_DET_EC# <69> D
20160127
1. Add TEMBER_DETECT# circuit
2. Change Resistor value
+3VL_EC
+3VL_AVCC
+3VALW
+3VL_EC
+3VS
minimum trace width 12 mil
Close to EC
C4009
0.1U_0402_25V6-K Un-stuff if not necessary.
+VCOREVCC 1 2
<8,83,86> VR_HOT# VR_HOT#

D
1
1
H_PROCHOT_EC 2
106
114
121
127
112
UE4001 G C4013
11
26
50
92
74
12
S Q4002 47P_0402_50V8-J
3
2N7002WT1G_SC-70-3 2
VSTBY_FSPI
VCC
VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5
VSTBY(PLL)
AVCC
VSTBY0
VCORE
<9> LPC_AD0 LPC_AD0 10 24 LOGO_LED LOGO_LED <60>
9 EIO0/LAD0/GPM0(3) PWM0/GPA0 25
<9> LPC_AD1 LPC_AD1 KB_BLK_PWM KB_BLK_PWM <65>
8 EIO1/LAD1/GPM1(3) PWM1/GPA1 28 R4042 1 2 0_0402_5%_SM
<9> LPC_AD2 LPC_AD2 EC_ON2_EC EC_ON2 EC_ON2 <92,93>
7 EIO2/LAD2/GPM2(3) PWM2/GPA2 29
<9> LPC_AD3 LPC_AD3 PWRBTN_LED# PWRBTN_LED# <67>
EIO3/LAD3/GPM3(3) PWM3/GPA3 R4045 1 2 0_0402_5%_SM
<15,30,58,63,67,69> PLT_RST# PLT_RST# 22
ERST#/LPCRST#/GPD2 PWM PWM4/GPA4
30 VR_ON_EC VR_ON VR_ON <86>
<9> CLK_PCI_EC CLK_PCI_EC 13 31 EC_FAN_PWM EC_FAN_PWM <66>
6 ESCK/LPCCLK/GPM4(3) PWM5/GPA5
WRST# KBRST# <9> LPC_FRAME# LPC_FRAME#
ECS#/LFRAME#/GPM5(3) 47 EC_FAN_SPEED EC_FAN_SPEED <66>
TACH0A/GPD6(3) 48 AOU_CTL3
1 1 TACH1A/TMA1/GPD7(3) AOU_CTL3 <64>
C4010 C4011 <15> VCCST_PG_EC VCCST_PG_EC 126
10P_0402_50V8-J 5 GA20/GPB5(3) R4033 +3VL_EC
1U_0402_10V6-K <9,58> SERIRQ SERIRQ 66 TEMBER_DETECT#
2 2 EMC_NS@ 15 ALERT#/SERIRQ/GPM6(3) ADC0/GPI0(3) 10K_0402_5%
PLTRST#/ECSMI#/GPD4(3) LPC
<43> PD_VBUS_C_CTRL1_EC PD_VBUS_C_CTRL1_EC 67 NUMLOCK_LED# NUMLOCK_LED# <65>
C 23 ADC1/GPI1(3) 68 BATT_TEMP MIRROR@ C
<9> EC_SCI# EC_SCI# ECSCI#/GPD3 BATT_TEMP <82>
14 ADC2/GPI2(3) 69 EC_ON 1 2
WRST# KB_BLK_DTCT# KB_BLK_DTCT# <65>
4 WRST# ADC3/GPI3(3)
<9> KBRST# KBRST# 70 FAN_ID FAN_ID <66>
KBRST#/GPB6(3) ADC4/GPI4(3)
R4034 +3VL_EC
A/D D/A
10K_0402_5%
+3VALW T4001
1 GPC0 113
IT8996 TACH2/GPJ0(3)
GPJ1(3)
76
77
78
INT#_TYPEC_EC R4046
PM_SLP_S5#_EC R4038
VGATE_EC R4049
1
1
1
2 0_0402_5%_SM
2 0_0402_5%_SM
2 0_0402_5%_SM
INT#_TYPEC
PM_SLP_S5#
VGATE
INT#_TYPEC
PM_SLP_S5#
VGATE
<42>
<15>
<15,86>
EC_MUTE# 1
MIRROR@
2
LQFP
CRX0/GPC0 DAC2/TACH0B/GPJ2(3)
R4008 1 2 10K_0402_5%
<64> AOU_DET# AOU_DET# 123
CTX0/TMA0/GPB2(3) CIR DAC3/TACH1B/GPJ3(3)
79 MAINPWON_EC MAINPWON_EC <80,82,84>
R4035
AOU_DET#
10K_0402_5%
R4009 1 2 10K_0402_5% KB_FN 94 EC_SMB_CK3 1 @ 2
CRX1/SIN1/SMCLK3/GPH1/ID1 EC_SMB_CK3 <9,32,57,59>
95 EC_SMB_DA3 EC_SMB_DA3 <9,32,57,59>
R4010 1 2 10K_0402_5% <65> KSO[0..17] KSO[0..17] 36 CTX1/SOUT1/GPH2/SMDAT3/ID2 122
KSO1 KSO0
KSO1 37 KSO0/PD0 DTR1#/SBUSY/GPG1/ID7 34
GSENSE_INT
GPU_VR_HOT#
GSENSE_INT
GPU_VR_HOT#
<57>
<91>
For Mirror Code
KSO1/PD1 PWM7/RIG1#/GPA7
R4011 1 2 10K_0402_5% KSO2 KSO2 38
KSO2/PD2 RTS1#/GPE5
35 FN_LED# FN_LED# <65> "H" --> Enable
KSO3 39 UART port ADC7/CTS1#/GPI7(3) 73
R4012 1 2 10K_0402_5% FAN_ID KSO4 40 KSO3/PD3
72 VGA_AC_DC# VGA_AC_DC# <32>
"L" --> Disable (Default)
41 KSO4/PD4 ADC6/DSR1#/GPI6(3)
KSO5 71 ADP_I ADP_I <83>
R4013 1 2 10K_0402_5% 42 KSO5/PD5 ADC5/DCD1#/GPI5(3)
LAN_WAKE# KSO6
20160307 43 KSO6/PD6
KSO7 16 EC_RX EC_RX <63>
R4014 1 @ 2 10K_0402_5% 44 KSO7/PD7 RXD/SIN0/PWUREQ#/BBO/SMCLK2ALT/GPC7(3) 17
EC_WAKE# Stuff CE11 for WRST singal KSO8 KSO8/ACK# TXD/SOUT0/LPCPD#/GPE6 EC_TX EC_TX <63>
KSO9 45
R4007 1 @ 2 100K_0402_5% 46 KSO9/BUSY
HDD_DETECT# KSO10 81 ENBKL ENBKL <5>
51 KSO10/PE DAC5/RIG0#/GPJ5(3)
2 1 10K_0402_5%
KSO11 KSO11/ERR# KBMX
R4029 USB_ON# KSO12 52 33 USB_ON# USB_ON# <64,67>
53 KSO12/SLCT GINT/CTS0#/GPD5 +3VL_EC
KSO13 119 BKOFF# BKOFF# <60>
R4036 2 @ 1 4.7K_0402_5% 54 KSO13 DSR0#/GPG6 R4027
PBTN_OUT# KSO14 80 H_PROCHOT_EC
55 KSO14 DAC4/DCD0#/GPJ4(3) 10K_0402_5%
+3VS KSO15 KSO15
KSO16 56 ACIN_EC 1 2
57 KSO16/SMOSI/GPC3(3)
KSO17 KSO17/SMISO/GPC5(3)
<65> KSI[0..7] KSI[0..7] 85 AOU_EN AOU_EN <64> R4028
R4022 1 2 2.2K_0402_5% 58 PS2CLK0/CEC/TMB0/GPF0 86
EC_SMB_DA3 KSI0 PBTN_OUT# PBTN_OUT# <15>
59 KSI0/STB# PS2DAT0/TMB1/GPF1 R4054 1 2 0_0402_5%_SM 1 2
R4023 1 2 2.2K_0402_5%
KSI1 KSI1/AFD# PS/2 PS2CLK2/GPF4
89 CP_CLK_EC
R4055 1 2 0_0402_5%_SM
CP_CLK CP_CLK <65>
EC_SMB_CK3 KSI2 60 90 CP_DATA_EC CP_DATA CP_DATA <65>
61 KSI2/INIT# PS2DAT2/GPF5 0_0402_5%_SM
KSI3 KSI3/SLIN#
R4015 1 2 10K_0402_5% LPC_FRAME# KSI4 62 D4001
63 KSI4 RB751V-40_SOD323-2
KSI5 125
64 KSI5 SSCE1#/GPG0 100 @
B R4016 1 2 10K_0402_5% EC_FAN_SPEED KSI6 KSI6 SPI ENABLE SSCE0#/GPG2 EC_MUTE# EC_MUTE# <50>
2 1
B
KSI7 65 ACIN <83>
R4030 2 1 4.7K_0402_5% KSI7
CP_CLK 32 BEEP# BEEP# <51> 1
<67> LAN_WAKE# 118 PWM6/SSCK/GPA6
LAN_WAKE# SMDAT2/PECIRQT#/GPF7(3)
R4031 2 1 4.7K_0402_5% CP_DATA <8> H_PECI R4026 1 2 43_0402_5% 117 C4012
PECI SMCLK2/PECI/GPF6(3)
<82,83> EC_SMB_DA1 116 120 OTP_RESET OTP_RESET <80> 100P_0402_50V8-J
EC_SMB_DA1 SMDAT1/GPC2 TMRI0/GPC4(3) 2
R4056 1 @ 2 10K_0402_5% CAPSLK_LED# <82,83> EC_SMB_CK1 EC_SMB_CK1 115 SM BUS 124 SUSP_EC R4043 1 2 0_0402_5%_SM SUSP <15,47,71,72,85>
SMCLK1/GPC1 TMRI1/GPC6(3) SUSP
<42> EC_SMB_DA2 R4047 1 2 0_0402_5%_SM EC_SMB_DA2_R 88
EC_SMB_DA2 SMDAT0/GPF3
<42> EC_SMB_CK2 R4048 1 2 0_0402_5%_SM EC_SMB_CK2_R 87
EC_SMB_CK2 SMCLK0/GPF2 110 ON/OFF# ON/OFF# <67>
+3VL_EC PWRSW/GPB3 111
XLP_OUT/GPB4 109 LID_SW# LID_SW# <67>
R4039 1 2 0_0402_5%_SM 21 LID_SW#/GPB1 108
<15> PM_SLP_S4# PM_SLP_S4# PM_SLP_S4#_EC ACIN_EC
R4017 1 2 10K_0402_5% R4040 1 2 0_0402_5%_SM RI2#/GPD1 AC_IN#/GPB0
LID_SW# <15> PM_SLP_S3# PM_SLP_S3# PM_SLP_S3#_EC 18
RI1#/GPD0(3) WAKE UP
<71,85,94> SYSON SYSON R4044 1 2 0_0402_5%_SM SYSON_EC 107
R4018 1 2 100K_0402_5% GPE4/BTN#
WRST#
R4019 1 2 2.2K_0402_5% EC_SMB_CK1 <9> SPI_FSCK 105 84 AOU_CTL1 AOU_CTL1 <64>
SPI_FSCK FSCK/GPG7 EGCLK/GPE3
<9> FSCE# FSCE# 101 83 EC_ON EC_ON <84>
R4020 1 2 2.2K_0402_5% FSCE#/GPG3 EGCS#/GPE2 R4037 1 2 0_0402_5%_SM
EC_SMB_DA1 <9> SPI_FMOSI# SPI_FMOSI# 102
FMOSI/GPG4
EXTERNAL SERIAL FLASH EGAD/GPE1
82 PCH_SYSPWROK_EC PCH_SYSPWROK PCH_SYSPWROK <15>
<9> SPI_FMISO SPI_FMISO 103
FMISO/GPG5
<15> AC_PRESENT R4041 1 2 0_0402_5%_SM AC_PRESENT_EC 128 19 CAPSLK_LED# CAPSLK_LED# <65>
AC_PRESENT GPJ6/THERMTRIP_SHUTDOWN# L80HLAT/BAO/GPE0
<8> EC_WAKE# EC_WAKE# 2 20 KB_FN KB_FN <65>
GPJ7 L80LLAT/GPE7
CLOCK
3 ME_FLASH ME_FLASH <11>
GPH7
GPIO ID6/GPH6
99 PCH_PWROK PCH_PWROK <15>
98 ACOFF ACOFF <83>
ID5/GPH5 97 PWR_STATUS_LED# <66> R4024
PWR_STATUS_LED#
ID4/GPH4 96 BATT_CHG_LED# <66> 100K_0402_5%
+3VL BATT_CHG_LED#
ID3/GPH3 93 R4052 1 2 0_0402_5%_SM EC_RSMRST# <15> 1 2
Vinafix.com EC_RSMRST#_EC EC_RSMRST# SUSP
CLKRUN#/ID0/GPH0
VSS5
AVSS
VSS1
VSS2
VSS3
VSS4
R4025
100K_0402_5%
@ JSW2 1 2 SYSON
104
R4053 1 2 100K_0402_5%
1
27
75
49
91
ON/OFF#
2 1 Please don't place any PU Resistor on GPG[7:2]
IT8996E-256-DX_LQFP128_14X14 (Reserve hardware strapping)
SHORT PADS
IT8586E/FX LQFP EC_AGND
A L4002 A
BLM18PG121SN1D_2P
1 2

Issued Date 2015/01/12 Deciphered Date 2016/01/12 EC_IT8996E-256/DX
Size
DocumentNumber
Number Rev
Rev
Custom !!"#$%&'()"*+ 0.2
Date:
Sheet 40 of 99
5 4 3 2 1
5 4 3 2 1
D D
C C
B
Vinafix.com B
A A

Issued Date 2015/01/12 Deciphered Date 2016/01/12 EC_IT8996E-256/DX
Size
Size Document
Number Rev
Rev
Custom 0.2
Date:
30, 2017
2017 Sheet
Sheet 41 of 99
5 4 3 2 1
5 4 3 2 1
+LDO_3V3
+5VALW +5VALW <38,39,43,47,64,66,67,71,72,84,85,86,87,88,89,91,93,94>
+VBUS_CONN U4202
+VBUS_CONN <43>
+VCON_IN 10
+VCON_IN <43> VPWR
+5V_IN USBC_DPAUX1 15 1 USBC_DPAUX1_CONN
+5V_IN <43> SBU1 C_SBU1
USBC_DPAUX2 14 2 USBC_DPAUX2_CONN +LDO_3V3
SBU2 C_SBU2
+LDO_3V3 +LDO_3V3 <43>
USBC_CC1 12 4 USBC_CC1_CONN 1
CC1 C_CC1
1
USBC_CC2 11 5 USBC_CC2_CONN
CC2 C_CC2 R4246 C4227
20 7 10K_0402_1% 1U_0201_6.3V6-K
+5V_IN 19 D1 RPD_G1 2
17 D2 6
D3 RPD_G2
2
+LDO_3V3 +5VALW C4226 16
D 0.1U_0603_50V7-K D4 9 -FLT_REPORT D
1 2 3 FLT
VBIAS 8
+LDO_3V3 GND1 13
+VCON_IN GND2 18
R4231 2 @ 1 0_0603_5% GND3 21
1 1 THERMAL_PAD
2
C4204
R4206 R4232 10U_0603_10V6-K C4205 TPD8S300_QFN20_3X3
100K_0402_5% 0_0603_5%
@ 2 2
0.1U_0201_10V6-K
+VBUS_CONN SA000086810
2 1 +VCON_IN_R
1
DDIP2_AUXN_C
1
DDIP2_AUXP_C
1 R4233
1
High enable discharge 150_0603_1% +VBUS_CONN

R4207 C4203 L4207 +VBUS_CONN_L
100K_0402_5% 10U_0603_10V6-K Low disable discharge BLM18KG300TN1D_2P
2
2 EMC@
+LDO_3V3 R4203 1 2 20160414
2
1
0_0402_5%_SM 1. Delete D30,D37 and add D72~D80
1 3 VBUS_DSCHG 1 2 2 Q4202 L4202
S
2N7002WT1G_1N_SC-70-3 BLM18KG300TN1D_2P
for layout placement
G
Q4203 2. Add U20 (OVP protection circuit)
VDS=-20 S SB000019400 EMC@
3
AO3413_SOT23-3 +VBUS_CONN 1 2
VGS=+-8V
G
2
SB93413000J R4204 VDS=60 20160419
Id=3A
1
R4230 100K_0402_5% 1. Co-lay F11
VGS=20
Vth=-1v 47K_0402_5% 1 1 2 2 2 D4209
1
+VBUS_CONN Id=320mA UCLAMP2271P.TNT SGP1610N2
1
TYPEC_GPIO9 2 1 C4206 C4231 C4232 C4233 C4234 EMC_NS@ JUSB3
4.7U_0603_10V6-K 1000P_0402_50V7-K 100P_0402_50V8J 100P_0402_50V8J 1000P_0402_50V7-K 21 17 USBC_CC2_CONN
2 2 EMC@ 1 EMC@ 1 EMC@ 1 EMC@ 16 Vbus4 CC2 5 USBC_CC1_CONN
Vbus3 CC1
2
USBC_CC1 USBC_CC2 9
4 Vbus2
Vbus1
2
1
10
25
26
1
1
C
R4208 U4201 USB20_N2_CON 19 C
200K_0402_1% C4212 C4214 18 Dn2
VCON_IN
5V_IN
LDO_3V3
220P_0402_50V7-J 220P_0402_50V7-J 7 Dp2
Dn1
2
2
USB20_P2_CON 6
Dp1
2
34
10 GND14 33
VMON TYPEC_CON_RXN2
Zdiff=90ohm No via If D4201 change to asm, 11 SSRXn2 GND13 32
TYPEC_CON_RXP2
SSRXp2 GND12 31
PD Controller please pay attention to GND11
1
<12> USB3P2_TXN C4230 1 2 0.22U_0201_6.3V6-K USB3P2_TXN_C 41 4 USBC_DPAUX2 the diodes voltage of the D4201 . TYPEC_CON_TXN2 15 30
R4209 42 SSTX_1P/2N SBU2/MGPIO7 3 14 SSTXn2 GND10 29
<12> USB3P2_TXP C4207 1 2 0.22U_0201_6.3V6-K USB3P2_TXP_C USBC_DPAUX1 TYPEC_CON_TXP2
10K_0402_1% SSTX_1N/2P SBU1/MGPIO6 SSTXp2 GND9 28
39 8 GND8
10Gbps MUX System Side
Type-C Port side

<12> USB3P2_RXN C4208 1 2 0.22U_0201_6.3V6-K USB3P2_RXN_C VBUS_DSCHG TYPEC_CON_RXN1 22 27
C4210 1 2 0.22U_0201_6.3V6-K 40 SSRX_1P/2N C_DM/BB_DM 7 D4210 23 SSRXn1 GND7 26
<12> USB3P2_RXP USB3P2_RXP_C TYPEC_CON_RXP1
SSRX_1N/2P C_DP/BB_DP SSRXp1 GND6
2
25
Zdiff=90ohm 11 1 3 GND5 24
USBC_CC2 TYPEC_CON_TXN1 TYPEC_CON_TXN1
C4213 1 2 0.1U_0201_10V6-K 38 CC2 9 CH1 2 SSTXn1 GND4 13
<5> CPU_DDI2_P3 CPU_DDI2_P3 CPU_DDI2_P3_C USBC_CC1 TYPEC_CON_TXP1
37 DP3_1N/2P CC1 2 9 SSTXp1 GND3 12
<5> CPU_DDI2_N3 CPU_DDI2_N3 C4216 1 2 0.1U_0201_10V6-K CPU_DDI2_N3_C TYPEC_CON_TXP1 TYPEC_CON_TXN1
46 DP3_1P/2N 18 CH2 NC_4 GND2 1
<5> CPU_DDI2_P2 CPU_DDI2_P2 C4217 1 2 0.1U_0201_10V6-K CPU_DDI2_P2_C TYPEC_RXP2
C4219 1 2 0.1U_0201_10V6-K 45 DP2_1N/2P C_RX2_1N/2P 19 8 20 GND1
<5> CPU_DDI2_N2 CPU_DDI2_N2 CPU_DDI2_N2_C TYPEC_RXN2 TYPEC_CON_TXP1 USBC_DPAUX2_CONN
C4222 1 2 0.1U_0201_10V6-K 44 DP2_1P/2N C_RX2_1P/2N 14 C4220 1 2 0.1U_0201_10V6-K NC_3 8 SBU2
<5> CPU_DDI2_P1 CPU_DDI2_P1 CPU_DDI2_P1_C TYPEC_TXP2 TYPEC_C_TXP2 USBC_DPAUX1_CONN
C4223 1 2 0.1U_0201_10V6-K 43 DP1_1N/2P C_TX2_1N/2P 15 C4221 1 2 0.1U_0201_10V6-K 3 SBU1
<5> CPU_DDI2_N1 CPU_DDI2_N1 CPU_DDI2_N1_C TYPEC_TXN2 TYPEC_C_TXN2
C4224 1 2 0.1U_0201_10V6-K 36 DP1_1P/2N C_TX2_1P/2N 16 VN
<5> CPU_DDI2_P0 CPU_DDI2_P0 CPU_DDI2_P0_C TYPEC_RXP1
C4225 1 2 0.1U_0201_10V6-K 35 DP0_1N/2P C_RX1_1N/2P 17 7 HIGHS_UB11126-A5A0B-1H
<5> CPU_DDI2_N0 CPU_DDI2_N0 CPU_DDI2_N0_C TYPEC_RXN1 TYPEC_CON_RXN1
DP0_1P/2N C_RX1_1P/2N 12 C4215 1 2 0.1U_0201_10V6-K NC_2 ME@
C_TX1_1N/2P TYPEC_TXP1 TYPEC_C_TXP1
+LDO_3V3 +5VALW 13 C4218 1 2 0.1U_0201_10V6-K 4 6
C_TX1_1P/2N TYPEC_TXN1 TYPEC_C_TXN1 TYPEC_CON_RXN1 TYPEC_CON_RXP1
CH3 NC_1
+3VL D4201 D4202
TYPEC_CON_RXP1 5
R4226 1 2 4.7K_0402_1% CH4 1 2 2 1
INT#_TYPEC USB20_P2_CON USB20_N2_CON
1 2 2 1
2
Zdiff=100ohm
1
R4229 1 2 4.7K_0402_1% EC_SMB_DA2

R4210 @ R4212 <5> DDIP2_AUXN C4209 1 2 0.1U_0201_10V6-K DDIP2_AUXN_C 2 R4227 1 2 4.7K_0402_1% EC_SMB_CK2 AOZ8808DI-05_DFN-10-10-9_2P5X1
C4211 1 2 0.1U_0201_10V6-K 1 AUX_N/MGPIO5 EMC@ PESD5V0H1BSF SOD962 PESD5V0H1BSF SOD962
0_0402_5% 590K_0402_1% <5> DDIP2_AUXP DDIP2_AUXP_C
AUX_P/MGPIO4 EMC@ EMC@
@ TP4301 1 MGPIO3 6 33 INT#_TYPEC
H_DM/DCI_CLK/MGPIO3 SM_INT/GPIO4 INT#_TYPEC <40>
1
SNK_PS_ACK 5
<43> SNK_PS_ACK H_DP/DCI_DATA/MGPIO2 31 D4205
LOC_PWR_MON SM_SDA/GPIO6 EC_SMB_DA2 EC_SMB_DA2 <40> D4211 D4206
B B
27 32 1 2
<43> SRC_PS_EN
SRC_PS_EN I2C_EN/GPIO10
RTS5455 SM_SCL/GPIO5 EC_SMB_CK2 EC_SMB_CK2 <40> TYPEC_CON_TXP2 1
CH1
USBC_CC2_CONN 1 2 2
2 1
1 USBC_CC1_CONN
1
TYPEC_GPIO9 28 TYPEC_CON_TXN2 2 9 TYPEC_CON_TXP2

R4211 I2C_INT/GPIO9 CH2 NC_4 PESD5V0H1BSF SOD962
R4213 PESD5V0H1BSF SOD962
10K_0402_1% 10K_0402_1% SRC_PS_FO 29 24 8 TYPEC_CON_TXN2 EMC_NS@ EMC_NS@
<43> SRC_PS_FO I2C_SDA/GPIO8 REXT NC_3
SNK_PS_EN# 30 20 3
<43> SNK_PS_EN# I2C_SCL/GPIO7 DB_CFG
2
VN
2
D4207 D4208
34 DDIP2_HPD <5> 7 TYPEC_CON_RXP2
HPD/GPIO3 NC_2 2 1
USBC_DPAUX2_CONN1 1 2
2
2 1 USBC_DPAUX1_CONN
1
TYPEC_CON_RXP2 4 6 TYPEC_CON_RXN2
R4245 R4244 CH3 NC_1
LOC_PWR_MON 23 0_0402_5% 6.2K_0402_1% PESD5V0H1BSF SOD962 PESD5V0H1BSF SOD962
LOC_PWR_MON @ EMC_NS@ EMC_NS@
TYPEC_CON_RXN2 5
SRC_PS_FLT 22 47 CH4
IMON
2
<43> SRC_PS_FLT E_PAD
2
VMON 21 AOZ8808DI-05_DFN-10-10-9_2P5X1
VMON
EMC@
RTS5455-GR_QFN46_6P5X4P5 R4218 1 @ 2 0_0402_5% R4222 1 @ 2 0_0402_5%

R4214 1 @ 2 0_0402_5% R4220 1 @ 2 0_0402_5% R4223 1 @ 2 0_0402_5%
EXC24CH900U_4P L4203 L4205 L4204 L4206

<12> USB20_P2 4 3 TYPEC_RXP1 4 3 TYPEC_C_TXP1 4 3 TYPEC_RXP2 1 2 TYPEC_CON_RXP2 TYPEC_C_TXP2 1 2 TYPEC_CON_TXP2
USB20_P2 4 3 USB20_P2_CON 4 3 TYPEC_CON_RXP1 4 3 TYPEC_CON_TXP1 1 2 1 2
<12> USB20_N2 1 2 TYPEC_RXN1 1 2 TYPEC_C_TXN1 1 2 TYPEC_RXN2 4 3 TYPEC_CON_RXN2 TYPEC_C_TXN2 4 3 TYPEC_CON_TXN2

USB20_N2 1 2 USB20_N2_CON 1 2 TYPEC_CON_RXN1 1 2 TYPEC_CON_TXN1 4 3 4 3
L4201 EMC@ EXC24CH900U_4P EXC24CH900U_4P EXC24CH900U_4P EXC24CH900U_4P
EMC@ EMC@ EMC@ EMC@
R4215 1 @ 2 0_0402_5%
R4219 1 @ 2 0_0402_5% R4228 1 @ 2 0_0402_5% R4221 1 @ 2 0_0402_5% R4224 1 @ 2 0_0402_5%
A A

Issued Date 2015/01/12 Deciphered Date 2016/01/12 RTS5455/USB TYPE-C
Size
Size Document
Number Rev
Rev
Date:
Sheet 42 of 99
5 4 3 2 1
Vinafix.com
A B C D E
+5VALW +5VALW <38,39,42,47,64,66,67,71,72,84,85,86,87,88,89,91,93,94>
+VBUS_CONN +VBUS_CONN <42>

+5VALW +VCON_IN
VSYSTEM2 VSYSTEM2 <80,83>
+VCON_IN +VCON_IN <42>
+5V_IN +5V_IN <42>
+LDO_3V3 R4339 2 1 0_0603_5%

+LDO_3V3 <42>
1 +5V_IN 1
D4310
1SS355VMTE-17
2 1
+VBUS_CONN Vr=80V
Ifm=225mA
D4311
1SS355VMTE-17
U4305
2 1 3 4
IN OUT
1
6 1
ADJ
2
Vr=80V C4306 R4342 1 2 100K_0402_5% 1
2.2U_0603_50V6-K EN R4305 C4305 C4302
Ifm=225mA 2 5 2 73.2K_0402_1% 47P_0402_50V8-J 2.2U_0402_10V6-K
GND NC 2
1
SYV634DEC_DFN6_2X2
2
SA00008EQ00
1
D
2
<40> PD_VBUS_C_CTRL1_EC G Q4304 vref0.6V
2
2N7002KW_SOT323-3
2
S SB000009Q8J R4338
3
R4316 10K_0402_1%
100K_0402_5%
2 2
1
1
+5VALW
1 1
C4308 C4307 +VBUS_CONN
100U_1206_6.3V6-M 1U_0603_25V7-K +LDO_3V3
2 2
1
J9
1
JUMP_43X118
@
1
3A
2
R4348 R4351
2
+LDO_3V3 10K_0402_1% 10K_0402_1%
NEED PN R4347
D4312
2
2
@ PTVS24VS1UR_SOD123W2 1M_0402_5%
R4346 U4301 @
3 10K_0402_1% A1 B1 2 1 2 1 3
VIN1 VCP1 2 1
A2 B2
Vinafix.com VIN2 VCP2 C1 U4302
VCP3
1
<42> SRC_PS_FLT VSYSTEM2
1
SRC_PS_FLT A4 C2 B2 B3
FLT# VBUS1 J13 @ C2 VBUS1 OVLO A2 SNK_PS_ACK
D1
1
<42> SRC_PS_EN SRC_PS_EN VBUS2 D2 VBUS2 ACK SNK_PS_ACK <42>
B4 D2 JUMP_43X118
EN VBUS3 E1 VBUS3 C3
<42> SRC_PS_FO !"#$ VBUS4 GND1
2
SRC_PS_FO C4 A3 E2 D3
FO ILIM VBUS5 GND2 E3
1 GND3
2
1
B3 A1
GND1 VINT1
1
1
C3 R4343 C4312 B1 A3 SNK_PS_EN#

R4315 R4345 GND2 D3 16K_0402_1% 4.7U_0805_50V6-K C1 VINT2 EN# SNK_PS_EN# <42>
100K_0402_5% 100K_0402_5% GND3 2 D1 VINT3
D4
CAP close U4301.D2 VINT4
2
2
NX5P3290UKZ_WLCSP16 1 R4349 R4350

2
2
NX20P5090UK_WLCSP15 100K_0402_5% 0_0402_5%_SM

SA00008BS00 C4311 @
1000P_0201_50V7-K SA00007JY00
1
2
2
1 1
C4310 C4309
1U_0603_25V7-K 4.7U_0805_50V6-K
2 2
close U4302.B2
4 4
Vinafix.com
Issued Date 2015/01/12 Deciphered Date 2016/01/12 RTS5455/POWER SWITCH
Size
Document Number
Number Rev
Rev
Custom 0.2
Date:
Sheet 43 of 99
A B C D E
A B C D E
1 1
2 2
3 3
Vinafix.com
4 4

Issued Date 2015/01/12
2015/01/12 Deciphered Date 2016/01/12
2016/01/12 BLANK
Size Document
Document Number
Number Rev
Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
Custom 0.2
0.2
Date:
Date: Monday,
Monday, October
October 30,
30, 2017
2017 Sheet
Sheet 44
44 of 99
99
A B C D E
5 4 3 2 1
D D
C C
B B
Vinafix.com
A A

2015/01/12 Deciphered Date 2016/01/12
2016/01/12 BLANK
Size Document
Document Number
Number Rev
Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D
D 0.2
0.2
Date:
Date: Monday,
Monday, October
October 30,
30, 2017
2017 Sheet
Sheet 45
45 of 99
99
5 4 3 2 1
A B C D E
1 1
2 2
3
Vinafix.com 3
4 4

Size
Size Document
Number Rev
Rev
Custom 0.2
Date:
30, 2017
2017 Sheet
Sheet 46 of 99
A B C D E
A B C D E
+3VS +3VS <5,6,9,10,11,12,14,15,23,25,30,32,37,39,40,50,51,57,58,59,60,61,63,65,66,67,69,72,85,86>
+5VS +5VS <50,51,60,61,65,66,72>
B+ B+ <60,72,80,83,84,85,86,87,88,89,91,92,95>
+5VALW +5VALW <38,39,42,43,64,66,67,71,72,84,85,86,87,88,89,91,93,94>
<5> CPU_DDI1_P0 CPU_DDI1_P0 C4705 1 2 0.1U_0201_10V6-K HDMI_TX0+
1 <5> CPU_DDI1_N0 CPU_DDI1_N0 C4704 1 2 0.1U_0201_10V6-K HDMI_TX0- 1
<5> CPU_DDI1_N1 CPU_DDI1_N1 C4707 1 2 0.1U_0201_10V6-K HDMI_TX1-
<5> CPU_DDI1_N2 CPU_DDI1_N2 C4709 1 2 0.1U_0201_10V6-K HDMI_TX2-
+5VS_HDMI
<5> CPU_DDI1_P3 CPU_DDI1_P3 C4711 1 2 0.1U_0201_10V6-K HDMI_TXC+
L4701 EMC@
<5> CPU_DDI1_N3 CPU_DDI1_N3 C4710 1 2 0.1U_0201_10V6-K HDMI_TXC- HDMI_TX0- 1 2 HDMI_TX0-_CON
1 2
HDMI CONN.
HDMI_TX0+ 4 3 HDMI_TX0+_CON
4 3 JHDMI1 ME@
EXC24CH900U_4P HDMI_HPD_CON 19
HP_DET
1
1
1
1
18
R4701 R4702 R4703 R4704 R4709 R4705 R4708 R4706 L4703 EMC@ 17 +5V
470_0201_5% 470_0201_5% 470_0201_5% 470_0201_5% 470_0201_5% 470_0201_5% 470_0201_5% 470_0201_5% HDMI_TX1- 1 2 HDMI_TX1-_CON HDMI_DAT_CON 16 DDC/CEC_GND
1 2 HDMI_CLK_CON 15 SDA
14 SCL
Reserved
2
2
2
2
HDMI_TX1+ 4 3 HDMI_TX1+_CON 13 20
4 3 HDMI_TXC-_CON 12 CEC GND1
EXC24CH900U_4P 11 CK- 21
+5VS HDMI_TXC+_CON 10 CK_shield GND2
L4704 EMC@ HDMI_TX0-_CON 9 CK+ 22
HDMI_TX2- 1 2 HDMI_TX2-_CON 8 D0- GND3
1 2 HDMI_TX0+_CON 7 D0_shield 23
D0+ GND4
1
D HDMI_TX1-_CON 6
2
2 HDMI_TX2+ 4 3 HDMI_TX2+_CON 5 D1- 2
G 4 3 HDMI_TX1+_CON 4 D1_shield
EXC24CH900U_4P HDMI_TX2-_CON 3 D1+
S Q4703 2 D2-
D2_shield
3
2N7002KW_SOT323-3 SB000009Q8J L4702 EMC@ HDMI_TX2+_CON 1

HDMI_TXC- 1 2 HDMI_TXC-_CON D2+
1 2
Need to confirm if 2n7002 can be used here.
SINGA_2HE3Y62-000111F
HDMI_TXC+ 4 3 HDMI_TXC+_CON
4 3
EXC24CH900U_4P
+5VS_HDMI +5VS_HDMI
D4701 RCLAMP0524PATCT_SLP2510P8-10-9 D4703 RCLAMP0524PATCT_SLP2510P8-10-9 D4702 RCLAMP0524PATCT_SLP2510P8-10-9
+3VS
HDMI_DAT_CON 9 1 HDMI_DAT_CON HDMI_TXC-_CON 9 1 HDMI_TXC-_CON HDMI_TX1-_CON 9 1 HDMI_TX1-_CON
HDMI_CLK_CON 8 2 HDMI_CLK_CON HDMI_TXC+_CON 8 2 HDMI_TXC+_CON HDMI_TX1+_CON 8 2 HDMI_TX1+_CON
HDMI_HPD_CON 7 4 HDMI_HPD_CON HDMI_TX0-_CON 7 4 HDMI_TX0-_CON HDMI_TX2-_CON 7 4 HDMI_TX2-_CON
6 5 HDMI_TX0+_CON 6 5 HDMI_TX0+_CON HDMI_TX2+_CON 6 5 HDMI_TX2+_CON Vgs(th) Max >=2.5V
1
R4713
1M_0201_5%
Q4702
2
EMC@ EMC@ EMC@ 2N7002KW_SOT323-3
G
3
2
3
3
SB00000YY00
<5> DDIP1_HPD DDIP1_HPD 3 1 HDMI_HPD_CON
D
3
Vinafix.com +3VS
Vgs(th) Max >=2.0V

+5VS_HDMI B+ +5VALW
+5VS
PMOS ?Id?=< 2A; Vgs(th)<-1.2V
+5VS_HDMI_F
1
F4701
2
0.5A_6V_1206L050YRHF
+5VS_HDMI
1
3
5
G
Q4701B 200mA C4712

0.1U_0201_6.3V6-K
1
2
1
DDIP1_CTRLCLK 4 3 HDMI_CLK_CON R4714 1 3 Q4704
S
S
<5> DDIP1_CTRLCLK
100K_0201_5%
D
HDMI_CLK_CON 1.8K_0201_5% 2 1 R4711 R4716 @

L2N7002KDW1T1G_SOT363-6 1K_0201_5% LP2301ALT1G_SOT23-3
2
HDMI_DAT_CON 1.8K_0201_5% 2 1 R4712

G
G
2
2
Q4701A
2
HDMI_HPD_CON 100K_0201_5% 1 2 R4710 SUSP#
DDIP1_CTRLDATA 1 6 HDMI_DAT_CON
S
<5> DDIP1_CTRLDATA
1
D
L2N7002KDW1T1G_SOT363-6 R4715
133K_0402_1%
AC:9V-->5.1V
2
D
AC+DC:13V-->7.4V
1
<15,40,71,72,85> SUSP 2
G Q4705
S 2N7002WT1G_SC-70-3
3
4 4

Issued Date 2015/01/12 Deciphered Date 2016/01/12 HDMI CONN
Size
Size Document
Number Rev
Rev
Custom 0.2
Date:
Sheet 47 of 99
A B C D E
A B C D E
1 1
2 2
3 3
Vinafix.com
4 4

2015/01/12 Deciphered Date 2016/01/12
2016/01/12 BLANK
Size Document
Document Number
Number Rev
Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D
D 0.2
0.2
Date:
Date: Monday,
Monday, October
October 30,
30, 2017
2017 Sheet
Sheet 48
48 of 99
99
A B C D E
A B C D E
1 1
2 2
3
Vinafix.com 3
4 4

Size
Size Document
Number Rev
Rev
Custom 0.2
Date:
30, 2017
2017 Sheet
Sheet 49 of 99
A B C D E
5 4 3 2 1
+5VS +5VS <47,51,60,61,65,66,72>
+3VL +3VL <19,40,42,67,72,80,82,83,84>
+3VALW +3VALW <6,9,12,15,19,40,58,60,63,65,66,67,72,83,84,91,95>
Close to Pin13,16 Please Close Pin28 CA20 close Pin7 CA12 close Pin2
+5VS +3VALW +3VS_VDDIO +3VS +3VS_VDDO
+5VS +5VS_AVDD
1
D D
R5009
0_0805_5%_SM
R5004 R5005 R5001

2
+5VS_CLASSD 1 2 1 2 1 2
1 1 1 1
0_0402_5%_SM 1 0_0402_5%_SM 1 0_0402_5%_SM 1
C5001 C5002 C5003 C5004 C5014
4.7U_0603_10V6-K 4.7U_0603_10V6-K 0.1U_0402_10V7-K 0.1U_0402_10V7-K 0.1U_0402_10V7-K C5015 C5011
2 2 2 2 0.1U_0402_10V7-K 0.1U_0402_10V7-K
2 2 2
X5R CAP, Please Close Pin18 CA13 close Pin24 LDO 1V8 VREF 1V65 LDO 3V3 CA10 close Pin7
+3VS +3VS_DVDD +3VL +3V_AVDD_HP +1.8V_LDO +1.65V_LDO +3V_LDO +3VS
R5003
1 2 R5002
1 2
0_0805_5%_SM 1 1 1 1 1 1 1 1
0_0805_5%_SM
C5013 C5012 C5005 C5006 C5007 C5008 C5009 C5010
1U_0402_6.3VA-K 1U_0402_6.3VA-K 4.7U_0603_10V6-K 0.1U_0402_10V7-K 1U_0402_6.3VA-K 0.1U_0402_10V7-K 2.2U_0402_6.3V6-M 0.1U_0402_10V7-K
C 2 2 2 S CER CAP 4.7U 10V K X5R 0603 2 2 S CER CAP 1U 6.3V K X6S 0402 2 2 2 C
X5R CAP X5R CAP
GNDA GNDA
+3VS_VDDO
1
R5006
47K_0402_5%
D5001
2
RB751V-40_SOD323-2
SCS00006S00
EC_MUTE# 1 2 +1.8V_LDO+3VS_VDDIO +3VS_VDDO +3VS_DVDD +3V_LDO +1.65V_LDO +5VS_AVDD
<40> EC_MUTE#
UA5001
<11> PCH_HDA_RST# PCH_HDA_RST# 9 3

Vinafix.com RESET# FILT_1.8V 7
VDD_IO 2
PCH_HDA_BCLK 5 VDDO_3.3 18
<11> PCH_HDA_BCLK BIT_CLK DVDD_3.3
<11> PCH_HDA_SYNC PCH_HDA_SYNC 8 27

SYNC AVDD_3.3 29
B
<11> PCH_HDA_SDIN0 PCH_HDA_SDIN0 R5008 1 2 33_0402_5% PCH_HDA_SDIN0_R 6
SDATA_IN
CX11852 VREF_1.65V
AVDD_5V
28 B
<11> PCH_HDA_SDOUT PCH_HDA_SDOUT 4
SDATA_OUT +MICBIASB +3V_AVDD_HP
<51> PC_BEEP PC_BEEP 10 12 SPK_L2+
PC_BEEP LEFT+ SPK_L2+ <51>
SPKR_MUTE# 39 14 SPK_L1-
SPKR_MUTE# LEFT- SPK_L1- <51>
<51> JSENSE JSENSE 38 17 SPK_R2+

JSENSE RIGHT+ SPK_R2+ <51>
37 15 SPK_R1-
GPIO1/PORTC_R_MIC RIGHT- SPK_R1- <51>
36 35
R5007 1 EMC@ 2 33_0402_5% 40 MUSIC_REQ/GPIO0/PORTC_L_MIC MICBIASC 34
<60> DMIC_CLK DMIC_CLK MIC_CLK_R
1 DMIC_CLK/MUSIC_REQ/GPIO0 MICBIASB
<60> DMIC_DATA DMIC_DATA
DMIC_DAT/GPIO1 33 PORTB_R PORTB_R <51>
+5VS_CLASSD W= 80mils PORTB_R_LINE 32
1 PORTB_L PORTB_L <51>
11 PORTB_L_LINE
C5017 1 2 0.1U_0402_10V7-K CLASSD_REF
C5016 CLASS-D_REF 30 EXT_MIC_A EXT_MIC_A <51>
150P_0402_50V8-J 13 PORTD_A_MIC 31 EXT_MIC_B EXT_MIC_B <51>
2 EMC@ 16 LPWR_5.0 PORTD_B_MIC
RPWR_5.0 25 HGNDA HGNDA <51,52>
+AVEE C5018 1 2 1U_0402_6.3V6-K FLY_P 19 HGNDA 26 Apple --> EXT_MIC_A, HGNDB
HGNDB HGNDB <51,52> Nokia --> EXT_MIC_B, HGNDA
20 FLY_P HGNDB
FLY_N
FLY_N 24
21 AVDD_HP
AVEE 23
1 HP_OUTR HP_OUTR <51>
41 PORTA_R 22 HP_OUTL HP_OUTL <51>
C5022 GND PORTA_L
Should be
2.2U_0402_6.3V6-M
2 connect to
HP indicate GNDA CX11852-11Z_QFN40_5X5 SA00007B100
W= 300mils C5019
0.1U_0402_10V7-K
EMC@
1 2
A
C5020 LAYOUT GND/AGND RECOMMEND A
0.1U_0402_10V7-K
EMC_NS@
1 2 38 31
1 AGND
C5021
0.1U_0402_10V7-K
EMC_NS@
1 2 DGND
21
11 Security Classification LC Future Center Secret Data Title
Issued Date 2015/01/12 Deciphered Date 2016/01/12 CODEC-CX11852
GNDA THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
Document Number
Number Rev
Rev
Date:
Sheet 50 of 99
5 4 3 2 1
2 1
+3VS +3VS <5,6,9,10,11,12,14,15,23,25,30,32,37,39,40,47,50,57,58,59,60,61,63,65,66,67,69,72,85,86>
Apple --> EXT_MIC_A, HGNDB

EXT. MIC/LINE IN Nokia --> EXT_MIC_B, HGNDA
PC Beep
R5101 1 2 4.7K_0402_5% C5101 1 2 0.1U_0402_10V7-K
EXT_MIC_A R5111 1 2 100_0402_5% EXT_MIC_A_R C5104 1 2 2.2U_0402_6.3V6-K HGNDB
<50> EXT_MIC_A HGNDB <50,52>
EXT_MIC_B R5112 1 2 100_0402_5% EXT_MIC_B_R C5105 1 2 2.2U_0402_6.3V6-K HGNDA

<50> EXT_MIC_B HGNDA <50,52>
D5101 R5103 C5102
RB521CS-30GT2RA_VMN2-2 33_0402_5% 0.1U_0402_10V7-K
EC Beep @ @ @
2 1 BEEP_D 1 2 1 2 PC_BEEP
<40> BEEP# PC_BEEP <50>
D5102 +3VS
PCH Beep RB521CS-30GT2RA_VMN2-2
1
@
1
2 1 R5118
B <11> PCH_BEEP B
10K_0402_5% R5113
@ 1K_0402_1% +5VS
1
JSENSE R5114 2 1 2.49K_0402_1% R5119
<50> JSENSE
10K_0402_5%
R5115 2 @ 1 39.2K_0402_1%
D
2
1
2 JSENSE_CON JSENSE_CON <52>
R5102 1 2 4.7K_0402_5% C5103 1 2 0.1U_0402_10V7-K G
S Q5101
3
2N7002WT1G_1N_SC-70-3
SB00000YY00
R5120 1 @ 2 0_0402_5%
HeadPhone/LINE OUT +MICBIASB

SPK CONN.
2
EMC@
R5106 L5101 1 2 BLM18PG221SN1D_2P SPK_L-_CON
<50> SPK_L1-
3K_0402_5% EMC@
<50> SPK_L2+ L5102 1 2 BLM18PG221SN1D_2P SPK_L+_CON
EMC@
1
<50> SPK_R1- R5116 1 2 0_0805_5%_SMSPK_R-_R L5103 1 2 BLM18PG221SN1D_2P SPK_R-_CON

EMC@
<50> HP_OUTL HP_OUTL R5107 1 2 75_0402_5% HP_OUTL_CON HP_OUTL_CON <52> <50> SPK_R2+ R5117 1 2 0_0805_5%_SMSPK_R+_R L5104 1 2 BLM18PG221SN1D_2P SPK_R+_CON
<50> PORTB_L
Vinafix.com
PORTB_L R5105 1 2 100_0402_5% C5106 1 2 10U_0603_6.3V6-M
+MICBIASB
2
R5108
3K_0402_5%
1
A A
EMC@
<50> HP_OUTR HP_OUTR R5109 1 2 75_0402_5% HP_OUTR_CON C5108 1 2 1000P_0402_50V7-K SPK_L-_CON JSPK1
HP_OUTR_CON <52>
EMC@ SPK_L-_CON 1
C5109 1 2 1000P_0402_50V7-K 2 1
SPK_L+_CON SPK_L+_CON
PORTB_R R5110 1 2 100_0402_5% C5107 1 2 10U_0603_6.3V6-M EMC@ SPK_R-_CON 3 2
<50> PORTB_R 3
C5110 1 2 1000P_0402_50V7-K SPK_R-_CON SPK_R+_CON 4
EMC@ 4
C5111 1 2 1000P_0402_50V7-K SPK_R+_CON 5
6 GND1
GND2
EMI parts Close to connector
HIGHS_WS33040-S0351-HF
ME@

Issued Date 2015/01/12 Deciphered Date 2016/01/12 HP/MIC JACK/Speaker
Size
Document Number
Number Rev
Rev
Custom 0.2
Date:
Sheet 51 of 99
2 1
5 4 3 2 1
D D
0_0402_5% 2 @ 1 R5202
<10,63> UART2_TX
<10,63> UART2_RX 0_0402_5% 2 @ 1 R5201
JAUHP1
HGNDB 4
<50,51> HGNDB 4
HGNDA 3
<50,51> HGNDA 3
HP_OUTL_CON 1
<51> HP_OUTL_CON 1
7
7
HP_OUTR_CON 2
<51> HP_OUTR_CON 2
5
5
JSENSE_CON 6
<51> JSENSE_CON 6
SINGA_2SJ3092-003111F
C
ME@ C
1 1
C5201 C5202
100P_0402_50V8-J 100P_0402_50V8-J
2 EMC@ 2 EMC@
NEED CHECK PIN DEFINE

GNDA GNDA
Vendor suggestion. Reserve for EMI.

Close to JAUHP.
ESD request C5203

0.1U_0402_10V7-K
EMC@
HGNDA GNDA JSENSE_CON 1 2
HP_OUTL_CON HP_OUTR_CON HGNDB
C5204
Vinafix.com 0.1U_0402_10V7-K
3
2
3
2
EMC@
D5201 D5202 D5203 1 2
PESD5V0U2BT_SOT23-3 PESD5V0U2BT_SOT23-3 PESD5V0U2BT_SOT23-3
EMC@ EMC@ EMC@
B B
1
1
1
GNDA
GND GND GND
A A

Issued Date 2015/01/12 Deciphered Date 2016/01/12 AUDIO JACK
Size
Document Number
Number Rev
Rev
Custom 0.2
Date:
Sheet 52 of 99
5 4 3 2 1
5 4 3 2 1
D D
C C
B
Vinafix.com B
A A

Issued Date 2015/01/12 Deciphered Date 2016/01/12 GBE LAN PHY(BLANK)
Size
Size Document
Number Rev
Rev
Custom 0.2
Date:
Date: Monday, October 30, 2017
2017 Sheet
Sheet 53 of 99
5 4 3 2 1
5 4 3 2 1
D D
C C
B
Vinafix.com B
A A

Issued Date 2015/01/12 Deciphered Date 2016/01/12 GBE LAN SWITCH(BLANK)
Size
Size Document
Number Rev
Rev
Custom 0.2
Date:
30, 2017
2017 Sheet
Sheet 54 of 99
5 4 3 2 1
5 4 3 2 1
D D
C C
B
Vinafix.com B
A A

Issued Date 2015/01/12 Deciphered Date 2016/01/12 RJ45 CONN.(BLANK)
Size
Size Document
Number Rev
Rev
Custom 0.2
Date:
30, 2017
2017 Sheet
Sheet 55 of 99
5 4 3 2 1
5 4 3 2 1
D D
C C
B
Vinafix.com B
A A

Issued Date 2015/01/12 Deciphered Date 2016/01/12 CARDREADER/CONN.(BLANK)
Size
Size Document
Number Rev
Rev
Custom 0.2
Date:
30, 2017
2017 Sheet
Sheet 56 of 99
5 4 3 2 1
A B C D E
+3VS +3VS <5,6,9,10,11,12,14,15,23,25,30,32,37,39,40,47,50,51,58,59,60,61,63,65,66,67,69,72,85,86>
+3VS
TABLE
R5704
10K_0402_5%
TABLE of G-Sersor (UG5701)
@
P/N ADDR_SEL Address
1 2 GSENSE_INT Vendor P/N LCFC P/N
1 1
BOSCH BMA255 SA00005YJ00
H 32h (W) & 33h (R)
+3VS Kionix KX022-1020 SA000081E00 BMA255
2 L 30h (W) & 31h (R)
R5705 H 3Eh (W) & 3Fh (R)

@ 10K_0402_5% KX022-1020
L 3Ch (W) & 3Dh (R)
1
ADDR_SEL
2
R5706
10K_0402_5% +3VS
1
2
R5703
0_0402_5%_SM
1
UG5701
ADDR_SEL 1 12 EC_SMB_CK3_G R5702 1 2 0_0402_5%_SM EC_SMB_CK3 <9,32,40,59>
R5701 1 2 0_0402_5%_SM EC_SMB_DA3_G 2 SDO SCL 11 +3VS_GS
<9,32,40,59> EC_SMB_DA3 SDA PS
+3VS_GS 3 10
4 VDDIO CSB 9
R5707 1 2 0_0402_5%_SM GSENSE_INT_R 5 NC GND 8
2
<40> GSENSE_INT INT1 GNDIO 2
1 Test_Point_12MIL 6 7
TP151 INT2 VDD
2
2 BMA255_LGA12_2X2
SA00005YJ00 C5701
C5702 0.1U_0402_10V6-K
0.1U_0402_10V6-K 1
1
CLOSE VDDIO CLOSE VDD
3
Vinafix.com 3
4 4
Vinafix.com Title
Issued Date 2015/01/12 Deciphered Date 2016/01/12 G SENSOR
Size
Size Document
Number Rev
Rev
Custom 0.2
Date:
Sheet 57 of 99
A B C D E
5 4 3 2 1
TABLE of TPM (UT5801)

Infineon SA000075L40 S IC SLB9670VQ2.0FW7.61 VQFN 32P TPM
ST SA000089E10 S IC ST33HTPH2E32AHB4 VQFN 32P TPM
+3VS +3VS <5,6,9,10,11,12,14,15,23,25,30,32,37,39,40,47,50,51,57,59,60,61,63,65,66,67,69,72,85,86>
+3VALW +3VALW <6,9,12,15,19,40,50,60,63,65,66,67,72,83,84,91,95>
D NOTE: D
Check timing sequence in SDV phase.
5 ms < t
NOTE:
1) It is recommended to connect the TPM to the system's
standby voltage to improve performance.
0 < t 2) SPI_RST# must be asserted for at least 5 msec after
VSB VSB power-up.
3) VSB may come up anytime before VDD power-up,
but not after VDD power-up.
+3VS +3VS_TPM 4) SPI_RST# may be asserted together with VDD power
VDD negation, but should not at any point exceed 0.5V
1 ms < t above the VDD power level.
R5807 1 @ 2 0_0402_5%
SPI_RST#
+3VALW +3VS_TPM
R5808 1 TPM@ 2 0_0402_5%
1 1
C5801 C5802
0.1U_0402_10V6-K 10U_0603_6.3V6-M
2 TPM@ 2 TPM@
+3VS_TPM
NOTE:
Place 0.1 uF capacitors as close as +3VS_TPM
C possible to the device power pins. C
1 1 1 1
C5803 C5804 C5805 C5806
10U_0603_6.3V6-M 0.1U_0402_10V6-K 0.1U_0402_10V6-K 0.1U_0402_10V6-K +3VS
2 TPM@ 2 TPM@ 2 TPM@ 2 TPM@
2
2
R5801 R5811
10K_0402_5% 10K_0402_5%
TPM@ TPM@
2
1
1
R5810
22
14
1
UT5801 10K_0402_5%
@
VDD
VHIO1
VHIO2
VSB
1
15 4 PP 1 @
LAD3 PP TP946
SERIRQ R5802 1 TPM@ 2 0_0402_5% SERIRQ_R 18 3 GPIO2
<9,40> SERIRQ LAD2/SPI_IRQ GPX/GPIO2
SPI_SI R5803 1 TPM@ 2 33_0402_5% SPI_SI_R 21 30 GPIO01 1 @
<9> SPI_SI LAD1/MOSI SCL/GPIO1 TP943
SPI_SO R5804 1 TPM@ 2 33_0402_5% SPI_SO_R 24
<9> SPI_SO LAD0/MISO
SPI_CS2#_TPM R5809 1 TPM@ 2 33_0402_5% SPI_CS2_R 20
<9> SPI_CS2#_TPM LFRAME/SCS
27
SPI_CLK R5805 1 TPM@ 2 33_0402_5% SPI_CLK_L 19 SERIRQ 29
<9> SPI_CLK LCLK/SCLK SDA/GPIO0 6 GPIO03 1 @
13 GPIO3/BADD 5 TP944
@ 1 GPIO04
TP945 CLKRUN/GPIO04/SINT TEST
PLT_RST# 17
<15,30,40,63,67,69> PLT_RST# LRESET/SPI_RST/SRESET
Vinafix.com NOTE:
Follow the SPI topology layout guidelines 28 2
in the relevant Intel Platform Design Guide. LPCPD NC1 7
NC2 10
NC3 11
B 12 NC4 25 B
Reserved NC5 26
NC6
2
31
R5806 NC7
GND1
GND2
GND3
GND4
10K_0402_5% 33
TPM@ EX-PAD
1
TPM@ SLB9670VQ1P2_VQFN32_5X5
9
16
32
23
SA000075L40
A A
Follow THP1_SWG_SIT_EC005, update TPM table

Issued Date 2015/01/12 Deciphered Date 2016/01/12 TPM
Size
Size Document
Number Rev
Rev
Custom 0.2
Date:
Sheet 58 of 99
5 4 3 2 1
+3VS +3VS <5,6,9,10,11,12,14,15,23,25,30,32,37,39,40,47,50,51,57,58,60,61,63,65,66,67,69,72,85,86>
Thermal Sensor Close to CPU

+3VS U5901
1 10 EC_SMB_CK3
VDD SMCLK EC_SMB_CK3 <9,32,40,57>
REMOTE1+ 2 9 EC_SMB_DA3
DP1 SMDATA EC_SMB_DA3 <9,32,40,57>
1
REMOTE1- 3 8
C5901 DN1 ALERT#
0.1U_0402_10V6-K REMOTE2+ 4 7 R5902 1 @ 2 10K_0402_5% +3VS
2 DP2 THERM#
REMOTE2- 5 6
DN2 GND
1. Address 1001_101xb
F75303M_MSOP10 2. Internal pull up 1.2K to 1.5V
SA000046C0J R for initial thermal shutdown temp
Close to CHARGER Close to GPU

REMOTE1+ REMOTE2+
REMOTE1+ REMOTE2+
1 1 1 1
1
C C
C5903 C5904 C5905 @ 2 Q5901 C5906 @ 2 Q5902
2200P_0402_50V7-K 2200P_0402_50V7-K 100P_0402_50V8-J B MMST3904-7-F_SOT323-3 100P_0402_50V8-J B MMST3904-7-F_SOT323-3
2 2 2 E SB000010U00 2 E SB000010U00
3
REMOTE1- REMOTE2-
REMOTE1- REMOTE2-
Trace width/space:10/10 mil

Trace length:<8"
Vinafix.com
Issued Date 2015/01/12 Deciphered Date 2016/01/12 THERMAL SENSOR
Custom 0.2
5 4 3 2 1
+3VS +3VS <5,6,9,10,11,12,14,15,23,25,30,32,37,39,40,47,50,51,57,58,59,61,63,65,66,67,69,72,85,86>
B+ B+ <47,72,80,83,84,85,86,87,88,89,91,92,95>
LOGO_LED
+3VALW
+3VS
LCDVDD Circuit +LCDVDD_CON
1
2
2.2K_0402_1%
R6017 R6015
0_0603_5%_SM @
2
D U6001 D
W= 60 mil W= 60 mil
1
5 1
IN OUT
1
D
2 <40> LOGO_LED LOGO_LED 2 Q6001
R6002 GND G 2N7002KW_SOT323-3
1 From PCH 1 2 PCH_ENVDD_R 4 3
1 1
@
<5> PCH_ENVDD EN OC
2
C6001 C6002 C6022 S
3
1U_0402_6.3V6-K 0_0402_5%_SM G524B1T11U_SOT23-5 4.7U_0603_6.3V6-K 2200P_0402_50V7-K
2 2 2 EMC_NS@
1
SA000074R00
R6001 D6001 R6014
100K_0402_5% PESD5V0U2BT_SOT23-3 1 2 LOGO_LED_CON
@
1
2.7K_0402_1%
2
+3VS +5VS
TABLE of POWER SWITCH (U6001)
R6008 1 @ 2 0_0402_5%
GMT SA000074R00 S IC G524B1T11U SOT23 5P POWER SWITCH
R6009 1 2 0_0402_5%_SM TPNL_VDD
SILERGY SA000074P00 S IC SY6288C20AAC SOT23 5P POWER SWITCH
R6016 2 1 100K_0402_5% D_J_CTL
C C
B+
1
R6003
0_0805_5%_SM
eDP/CMOS/LOGO-LED CONN.
2
+LEDVDD
1
C6003
4.7U_0805_25V6-K JLCD1
2 1
2 1
W= 80 mil 2
3
4 3
5 4
6 5
7 6
<10> D_J_CTL D_J_CTL
8 7
Vinafix.com <5> PCH_EDP_PWM PCH_EDP_PWM
9 8
<40> BKOFF# BKOFF#
10 9
11 10
USB20_N7_TPNL
12 11
USB20_P7_TPNL
B 13 12 B
L6001
14 13
<12> USB20_N7 USB20_N7 4 3 USB20_N7_TPNL <5> CPU_EDP_HPD CPU_EDP_HPD
4 3 15 14
TPNL_EN R6010 1 2 0_0402_5%_SM TPNL_EN_R
Touch Panel <10> TPNL_EN
TPNL_VDD 16 15
+LCDVDD_CON 17 16
<12> USB20_P7 USB20_P7 1 2 USB20_P7_TPNL
1 2 18 17
+LCDVDD_CON W= 60 mil
19 18
SM070003X00
20 19
EXC24CH900U_4P
21 20
<5> CPU_EDP_AUX# CPU_EDP_AUX# C6004 1 2 0.1U_0402_10V7-K CPU_EDP_AUX#_CON
C6005 1 2 0.1U_0402_10V7-K CPU_EDP_AUX_CON 22 21
L6002 <5> CPU_EDP_AUX CPU_EDP_AUX
23 22
<12> USB20_N6 USB20_N6 4 3 USB20_N6_CAMERA
4 3 1 2 24 23
CPU_EDP_TX0+ C6007 0.1U_0402_10V7-K CPU_EDP_TX0+_CON
CAMERA <5> CPU_EDP_TX0+
CPU_EDP_TX0- C6006 1 2 0.1U_0402_10V7-K CPU_EDP_TX0-_CON 25 24
<5> CPU_EDP_TX0- 25
<12> USB20_P6 USB20_P6 1 2 USB20_P6_CAMERA 26
1 2 C6009 1 2 0.1U_0402_10V7-K CPU_EDP_TX1+_CON 27 26
<5> CPU_EDP_TX1+ CPU_EDP_TX1+
C6008 1 2 0.1U_0402_10V7-K CPU_EDP_TX1-_CON 28 27
SM070003X00 <5> CPU_EDP_TX1- CPU_EDP_TX1-
29 28
EXC24CH900U_4P
30 29 41
31 30 GND1 42
<50> DMIC_DATA DMIC_DATA
32 31 GND2 43
<50> DMIC_CLK DMIC_CLK
33 32 GND3 44
34 33 GND4 45
USB20_N6_CAMERA
35 34 GND5 46
USB20_P6_CAMERA
36 35 GND6 47
+3VS 37 36 GND7 48
LOGO_LED_CON
38 37 GND8 49
39 38 GND9 50
R6005 1 2 0_0603_5%_SM +3VS_DMIC W= 40 mil
R6006 1 2 0_0603_5%_SM 40 39 GND10 51
+3VS_CMOS
40 GND11
1
R6012 R6011 ME@
100K_0402_5% 100K_0402_5%
A A
RF
2
+LEDVDD +3VS_CMOS +LCDVDD_CON LOGO_LED_CON
1 1 1 1 1
1
1
C6014 C6015 C6016 C6017 C6018 C6019 C6020 C6021

0.1U_0402_16V7-K 47P_0402_50V8-J 0.1U_0402_16V7-K 100P_0402_50V8J 100P_0402_50V8J 47P_0402_50V8-J 0.1U_0402_16V7-K 100P_0402_50V8J Title
RF@ RF@ RF@ RF@ RF@ RF_NS@ RF@ RF@
2
2
2 2 2 2 2
Issued Date 2015/01/12 Deciphered Date 2016/01/12 eDP/CMOS/LOGO-LED CONN.
Size
Document Number
Number Rev
Rev
Custom 0.2
Date:
Sheet 60 of 99
5 4 3 2 1
5 4 3 2 1
+5VS
+5VS
+5VS +5VS <47,50,51,60,65,66,72>
+3VS +3VS <5,6,9,10,11,12,14,15,23,25,30,32,37,39,40,47,50,51,57,58,59,60,63,65,66,67,69,72,85,86> SATA HDD CONN.

1 1 1 1
1
C6101 C6102 C6103 C6104 R6102
10U_0805_10V6-K 10U_0805_10V6-K 1U_0402_10V6-K 0.1U_0402_25V6-K 0_0805_5%_SM
2 2@ 2@ 2@
2
JHDD1
D 14 16 D
PCIE7_SATA0_CTX_DRX_P_CONN 13 14 GND16 15
PCIE7_SATA0_CTX_DRX_N_CONN 12 13 GND15
11 12
PCIE7_SATA0_CRX_DTX_N_CONN 10 11
PCIE7_SATA0_CRX_DTX_P_CONN 9 10
8 9
SATA0_DEVSLP R6101 1 2 0_0402_5%_SM -CLKREQ_DEVSLP 7 8
<12> SATA0_DEVSLP 7
HDD_DETECT# 6
<40> HDD_DETECT# 6
5
4 5
3 4
2 3
1 2
1
HIGHS_FC5AF141-3181H
ME@
PCIE7_SATA0_CTX_DRX_P R6114 1 2 NSATA_RE@ 0_0201_5% PCIE7_SATA0_CTX_R_DRX_P C6112 1 2 NSATA_RE@ 0.01U_0201_6.3V7-K PCIE7_SATA0_CTX_DRX_P_CONN
PCIE7_SATA0_CTX_DRX_N R6115 1 2 NSATA_RE@ 0_0201_5% PCIE7_SATA0_CTX_R_DRX_N C6113 1 2 NSATA_RE@ 0.01U_0201_6.3V7-K PCIE7_SATA0_CTX_DRX_N_CONN
C PCIE7_SATA0_CRX_DTX_P R6116 1 2 NSATA_RE@ 0_0201_5% PCIE7_SATA0_CRX_R_DTX_P C6114 1 2 NSATA_RE@ 0.01U_0201_6.3V7-K PCIE7_SATA0_CRX_DTX_P_CONN C
PCIE7_SATA0_CRX_DTX_N R6117 1 2 NSATA_RE@ 0_0201_5% PCIE7_SATA0_CRX_R_DTX_N C6115 1 2 NSATA_RE@ 0.01U_0201_6.3V7-K PCIE7_SATA0_CRX_DTX_N_CONN
SATA REDRIVER
+3VS +3VS +3VS
U6101
7 10
EN VDD1
1
20
R6103 PCIE7_SATA0_CTX_DRX_P SATA_RE@ C6108 1 2 0.01U_0201_6.3V7-K PCIE7_SATA0_CTX_C_DRX_P 1 VDD2
<12> PCIE7_SATA0_CTX_DRX_P AI+
@ 100K_0402_5% PCIE7_SATA0_CTX_DRX_N SATA_RE@ C6109 1 2 0.01U_0201_6.3V7-K PCIE7_SATA0_CTX_C_DRX_N 2 6
<12> PCIE7_SATA0_CTX_DRX_N AI- NC1 16
PCIE7_SATA0_CRX_DTX_P SATA_RE@ C6106 1 2 0.01U_0201_6.3V7-K PCIE7_SATA0_CRX_C_DTX_P 5 NC2
<12> PCIE7_SATA0_CRX_DTX_P BO+
2
2
PCIE7_SATA0_CRX_DTX_N SATA_RE@ C6105 1 2 0.01U_0201_6.3V7-K PCIE7_SATA0_CRX_C_DTX_N 4 9 A_EM
<12> PCIE7_SATA0_CRX_DTX_N BO- A_EM 8 B_EM R6126 R6127
3 B_EM 0_0402_5% 0_0402_5%
13 TDet_B# 15 PCIE7_SATA0_CTX_C_DRX_P_CONN C6116 1 2 SATA_RE@ 0.01U_0201_6.3V7-KPCIE7_SATA0_CTX_DRX_P_CONN @ @
TDet_A# AO+ 14 PCIE7_SATA0_CTX_C_DRX_N_CONN C6117 1 2 SATA_RE@ 0.01U_0201_6.3V7-KPCIE7_SATA0_CTX_DRX_N_CONN
AO-
1
TDetT_EN 18
A_EQ 17 TDetT_EN 11 PCIE7_SATA0_CRX_C_DTX_P_CONN C6118 1 2 SATA_RE@ PCIE7_SATA0_CRX_DTX_P_CONN
0.01U_0201_6.3V7-K
A_EQ BI+
2
B_EQ 19 12 PCIE7_SATA0_CRX_C_DTX_N_CONN C6119 1 2 SATA_RE@ PCIE7_SATA0_CRX_DTX_N_CONN

0.01U_0201_6.3V7-K
R6128 21 B_EQ BI-
R6129
0_0402_5% 0_0402_5% PAD
@ @ PI3EQX6741STZDEX_TQFN20_4X4
SATA_RE@
1
B B
+3VS
1
Vinafix.com
1 2
+3VS
2
2
2
2
2
C6110 C6111 C6107

.01U_0402_50V7-K .01U_0402_50V7-K 1U_0402_6.3V6-K R6104 R6105 R6106 R6107 R6108
2 SATA_RE@ 2 SATA_RE@ 1 SATA_RE@ 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
@ @ @ SATA_RE@ @
1
1
1
1
1
TDetT_EN A_EQ B_EQ A_EM B_EM

2
2
2
2
R6109 R6110 R6111 R6112 R6113

10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
SATA_RE@ SATA_RE@ SATA_RE@ @ SATA_RE@
1
1
1
A A

Issued Date 2015/01/12 Deciphered Date 2016/01/12 SATA HDD CONN/REDRIVER
Size
Size Document
Number Rev
Rev
Custom 0.2
Date:
Sheet 61 of 99
5 4 3 2 1
5 4 3 2 1
D D
C C
B
Vinafix.com B
A A

Issued Date 2015/01/12 Deciphered Date 2016/01/12 SATA(BLANK)
Size
Size Document
Number Rev
Rev
Custom 0.2
Date:
30, 2017
2017 Sheet
Sheet 62 of 99
5 4 3 2 1
+5VALW +5VALW <38,39,42,43,47,64,66,67,71,72,84,85,86,87,88,89,91,93,94>
+3VS +3VS <5,6,9,10,11,12,14,15,23,25,30,32,37,39,40,47,50,51,57,58,59,60,61,65,66,67,69,72,85,86>
+3VALW +3VALW <6,9,12,15,19,40,50,58,60,65,66,67,72,83,84,91,95>
TYPE-A NGFF SLOT FOR WLAN

3.2H CONNECTOR
+3VS +3VALW_WLAN
R6301 1 2 0_0805_5%_SM +3VALW_WLAN

+3VALW
1 1
R6321 1 @ 2 0_0805_5% C6301 C6302
100P_0402_50V8J 100P_0402_50V8J
2 RF@ 2 RF@
+3VS
R6316 1 @ 2 10K_0402_5% EC_WLAN_WAKE#

+3VALW_WLAN +3VS
+3VALW
R6322 1 @ 2 10K_0402_5%
JWLBT2
1 2
GND1 3.3VAUX1
1
1
USB20_P5 3 4
<12> USB20_P5 USB_D+ 3.3VAUX2
5 R6318
<12> USB20_N5 USB20_N5
7 USB_D- KEY A LED1#
8
6
1
R6317
49.9K_0402_1% 49.9K_0402_1%
GND2 NC
9 10 @ @
NC NC
11 12 C6304 @
NC NC
2
2
13 14 4.7U_0603_10V6-K
NC NC 2
15 16
NC LED2#
17 18
19 MLDIR_SENSE GND16 20
21 DP_ML3N DP_AUXN 22
23 DP_ML3P DP_AUXP 24
25 GND3 GND13 26 R6320 1 @ 2 0_0402_5% UART2_RX <10,52>
27 DP_ML2N DP_ML1N 28
29 DP_ML2P DP_ML1P 30 R6319 1 @ 2 0_0402_5% UART2_TX <10,52>
31 GND4 GND14 32
33 DP_HPD DP_ML0N 34
<12> PCIE11_CTX_C_DRX_P PCIE11_CTX_C_DRX_P 35 GND5 DP_ML0P 36
PCIE11_CTX_C_DRX_N 37 PETP0 GND15 38 CL_RST_WLAN#
<12> PCIE11_CTX_C_DRX_N CL_RST_WLAN# <9>
39 PETN0 RESERVED1 40 CL_DATA_WLAN CL_DATA_WLAN <9>
PCIE11_CRX_DTX_P 41 GND6 RESERVED2 42 CL_CLK_WLAN
<12> PCIE11_CRX_DTX_P CL_CLK_WLAN <9>
PCIE11_CRX_DTX_N 43 PERP0 RESERVED3 44
<12> PCIE11_CRX_DTX_N
45 PERN0 COEX3 46
CLK_PCIE_WLAN 47 GND7 COEX2 48
<14> CLK_PCIE_WLAN
CLK_PCIE_WLAN# 49 REFCLKP0 COEX1 50 SUSCLK_32K
<14> CLK_PCIE_WLAN# SUSCLK_32K <14>
51 REFCLKN0 SUSCLK 52 R6311 1 2 0_0402_5%_SM PLT_RST# PLT_RST# <15,30,40,58,67,69>
CLKREQ_PCIE2_WLAN# 53 GND8 PERST0# 54 BT_ON_R
<14> CLKREQ_PCIE2_WLAN#
EC_WLAN_WAKE# R6303 1 2 0_0402_5%_SM WLAN_WAKE# 55 CLKREQ0# W_DISABLE2# 56 RF_OFF# RF_OFF# <10>
57 PEWAKE0# W_DISABLE1# 58
PU +3VALW, To EC 59 GND9 I2C_DATA 60
PU +3VALW, To PCH PCIE_WAKE#
Vinafix.com 61 PETP1 I2C_CLK 62
63 PETN1 ALERT# 64 EC_TX_R R6313 1 2 100_0402_1% EC_TX EC_TX <40>
<15> PCIE_WAKE# R6304 1 @ 2 0_0402_5% 65 GND10 RESERVED4 66
67 PERP1 PERST1# 68 NEED CHECK SPEC
69 PERN1 CLKREQ1#
1
70 R6314 1 2 1K_0402_5% BT_ON BT_ON <10>
71 GND11 PEWAKE1# 72 R6312
73 REFCLKP1 3.3VAUX4 74 100K_0402_5% R6315 1 2 100_0402_1% EC_RX EC_RX <40>
75 REFCLKN1 3.3VAUX5
GND12
2
76 77
PEG1 PEG2
DEREN_40-42191-06701RHF
ME@

Issued Date 2015/01/12 Deciphered Date 2016/01/12 WWAN/WLAN NGFF CONN.
Size
Size Document
Number Rev
Rev
Custom 0.2
Date:
Sheet 63 of 99
5 4 3 2 1
+5VALW +5VALW <38,39,42,43,47,66,67,71,72,84,85,86,87,88,89,91,93,94>
+3VS +3VS <5,6,9,10,11,12,14,15,23,25,30,32,37,39,40,47,50,51,57,58,59,60,61,63,65,66,67,69,72,85,86>

On Board (LEFT-Front)
+5VALW USB POWER SWITCH +USB_PWR_S2
U6401
W=80mils 5 1
W=80mils
D IN OUT Vendor LCFC P/N Description D
2
GND SILERGY SA000074Q00 S IC SY6288D20AAC SOT23 5P POWER SWITCH
1
USB_ON# 4 3
C6401
<40,67> USB_ON# ENB OCB
USB_OC2#
USB_OC2# <12> GMT SA000079400 S IC G517F2T11U SOT-23 5P POWER SWITCH
0.1U_0402_10V6-K SY6288D20AAC_SOT23-5
2 SA000074Q00
+USB_PWR_S2
D6401
1 USB3P4_TXP_CON
L6401 CH1
USB3P4_TXN C6403 1 2 0.1U_0402_10V7-K USB3P4_TXN_C 4 3 USB3P4_TXN_CON USB3P4_TXP_CON 9 2 USB3P4_TXN_CON 1 1 1
<12> USB3P4_TXN 4 3 NC_4 CH2
USB3P4_TXN_CON 8 + C6404 C6405 @ C6406 EMC@
USB3P4_TXP C6402 1 2 0.1U_0402_10V7-K USB3P4_TXP_C 1 2 USB3P4_TXP_CON NC_3 150U_D2_6.3VM_R15M 470P_0402_50V7-K
<12> USB3P4_TXP 1 2 0.1U_0402_10V7-K
3 2 2
EXC24CH900U_4P VN 2 SGA00007F00
EMC@ USB3P4_RXP_CON 7
SM070003X00 NC_2
USB3P4_RXN_CON 6 4 USB3P4_RXP_CON C51, C50 near JUSB1
L6402 NC_1 CH3
USB3P4_RXN 4 3 USB3P4_RXN_CON
<12> USB3P4_RXN 4 3 5 USB3P4_RXN_CON
CH4
USB3P4_RXP 1 2 USB3P4_RXP_CON
<12> USB3P4_RXP 1 2 +USB_PWR_S2 +USB_PWR_S2
AOZ8808DI-05_DFN-10-10-9_2P5X1
EXC24CH900U_4P EMC@
EMC@ JUSB2
SM070003X00 USB3P4_TXP_CON 9
D6404 1 StdA_SSTX+
USB20_N3_CON 1 6 USB20_P3_CON USB3P4_TXN_CON 8 VBUS
USB20_P3_CON 3 StdA_SSTX-
L6403 7 D+
USB20_N3 4 3 USB20_N3_CON USB20_N3_CON 2 GND_1 10
<12> USB20_N3 4 3 D- GND_2
2 5 USB3P4_RXP_CON 6 11
4 StdA_SSRX+ GND_3 12
C USB20_P3 1 2 USB20_P3_CON USB3P4_RXN_CON 5 PGND GND_4 13 C
<12> USB20_P3 1 2 StdA_SSRX- GND_5
EXC24CH900U_4P 3 4 SINGA_2UB2306-000111F
EMC@ ME@
SM070003X00 CM1293A-04SO_SC-74-6
EMC@
On Board (LEFT-Back)
+5VALW +USB_PWR_S1
L6404
<12> USB3P1_TXN USB3P1_TXN C6407 1 2 0.1U_0402_10V7-K USB3P1_TXN_C 4 3 USB3P1_TXN_CON
4 3
U6402
1 12 <12> USB3P1_TXP USB3P1_TXP C6408 1 2 0.1U_0402_10V7-K USB3P1_TXP_C 1 2 USB3P1_TXP_CON
IN OUT 10 USB20P1 1 2
USB20_P1 3 DP_IN 11 USB20N1 EXC24CH900U_4P
<12> USB20_P1 DP_OUT DM_IN
<12> USB20_N1 USB20_N1 2 14 SM070003X00
DM_OUT GND EMC@
9 AOU_DET# AOU_DET# <40> L6405

STATUS# USB3P1_RXN 4 3 USB3P1_RXN_CON
<12> USB3P1_RXN 4 3
4
USB_OC0# 13 ILIM_SEL
<12> USB_OC0# FAULT#
<40> AOU_EN
Vinafix.com AOU_EN 5 <12> USB3P1_RXP USB3P1_RXP 1 2 USB3P1_RXP_CON
EN 15 ILIM_LO R6403 1 @ 2 20K_0402_1% 1 2
AOU_CTL1 6 ILIM_LO 16 ILIM_HI R6402 1 2 20K_0402_1% EXC24CH900U_4P
<40> AOU_CTL1 CLT1 ILIM_HI
7 SM070003X00
AOU_CTL3 8 CLT2 17 EMC@
<40> AOU_CTL3 CLT3 GND_Pad
B 1 B
TPS2546RTER_QFN16_4X4
C6409 L6406
0.1U_0402_10V7-K TI TPS2546 USB20P1 4 3 USB20_P1_CON
2@ 4 3
SA00005TD00
USB20N1 1 2 USB20_N1_CON
1 2
EXC24CH900U_4P
EMC@
SM070003X00
+USB_PWR_S1
D6402
TABLE of POWER SWITCH (U6401) 1 USB3P1_TXP_CON
CH1
Vendor LCFC P/N Description USB3P1_TXP_CON 9 2 USB3P1_TXN_CON
1
NC_4 CH2 1
+ C6410
TI SA00005TD00 S IC TPS2546RTER QFN 16P USB CHARGING USB3P1_TXN_CON 8
C6411
NC_3
Pericom SA000066I00 S IC PI5USB2546ZHEX TQFN 16P CONTROLLER 3 2
150U_B2_6.3VM_R35M
2
470P_0402_50V7-K
VN
USB3P1_RXP_CON 7
NC_2
USB3P1_RXN_CON 6 4 USB3P1_RXP_CON
NC_1 CH3
CLT1 CLT2 CLT3 ILIM_SEL MOD 5 USB3P1_RXN_CON +USB_PWR_S1

CH4
JUSB1
0 0 0 X DCH OUT held low AOZ8808DI-05_DFN-10-10-9_2P5X1 1
EMC@ 2 VBUS
USB20_N1_CON
3 D-
USB20_P1_CON
1 1 1 1 Data Connected and Port Power Mgt. Function Active D+
*
CDP D6403 4
1 6 5 GND
USB20_N1_CON USB20_P1_CON USB3P1_RXN_CON
Stda_SSRX-
* USB3P1_RXP_CON 6 10
1 1 1 0 SDP2 Data Connected +USB_PWR_S1 7 Stda_SSRX+ GND2 11
8 GND_DRAIN GND3 12
USB3P1_TXN_CON
Stda_SSTX- GND4
*
A 2 5 USB3P1_TXP_CON 9 13 A
1 1 0 X SDP1 Data Connected Stda_SSTX+ GND5
FOX_UEA111Y-R1001A-7H
*
ME@
0 1 0 X SDP1 Data Connected 3 4
CM1293A-04SO_SC-74-6
1 0 0 X DCP_Short Device Forced to stay in DCP BC 1.2 charging mode EMC@
1 0 1 X DCP_Divider Device Forced to stay in DCP Divider 1 Charging Mode

0 1 1 X Data Disconnected and Port Power Mgt. Function Active
*
DCP_Auto Issued Date 2015/01/12 Deciphered Date 2016/01/12 USB3 P1/2 CONN.
0 0 1 X DCP_Auto Data Disconnected and Power Wake Function Active Size
Size Document
Number Rev
Rev
Custom 0.2
Date:
Sheet 64 of 99
5 4 3 2 1
5 4 3 2 1
KSI[0..7]
<40> KSI[0..7]
+5VS +5VS <47,50,51,60,61,66,72> KSO[0..17]
Keyboard CONN
<40> KSO[0..17]
+3VS +3VS <5,6,9,10,11,12,14,15,23,25,30,32,37,39,40,47,50,51,57,58,59,60,61,63,66,67,69,72,85,86>
+3VALW +3VALW <6,9,12,15,19,40,50,58,60,63,66,67,72,83,84,91,95>

<40> KB_FN
+3VALW +3VS +3VALW +3VS

NUMLOCK_LED CAPSLK_LED +3VS +3VALW
1
1
1
+3VS +3VALW
1
R6543 R6523 R6542 R6525
R6548 R6549
10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5%
0_0402_5% 0_0402_5%
@ @ @ @ @ @
2
2
2
D D
2
R6520 1 2 100_0402_1% NUMLOCK_LED R6521 1 2 100_0402_1% CAPSLK_LED
<40> NUMLOCK_LED# <40> CAPSLK_LED#
JKB1
2
2
2
1
2
2
2
1
40 42
40 GND2
1
1 1 R6509 R6510 R6511 R6512 R6513 R6514 R6515 R6516 R6507 R6547 39 41
39 GND1
1
R6524 15K_0402_5% 15K_0402_5% 15K_0402_5% 15K_0402_5% 15K_0402_5% 15K_0402_5% 15K_0402_5% 15K_0402_5% 0_0603_5%_SM 0_0402_5% NUMLOCK_LED 38
C6503 R6522 C6504 100K_0402_5% @ @ @ @ @ @ @ @ KSO17 37 38
100P_0402_50V8J 100K_0402_5% 100P_0402_50V8J @ @ KSO16 36 37
2 EMC@ 36
1
1
2
2 EMC@
1
1
2
@ TP4MIDDLE 35
35
2
TP4RIGHT 34
34
2
TP4LEFT 33
32 33
CAPSLK_LED 31 32
30 31
KB_FN 29 30
F4_LED 28 29
F1_LED 27 28
FN_LED 26 27
+3VS_KB 25 26
KSO15 24 25
+3VALW +3VS +3VALW +3VS 24
F4_LED F1_LED KSO10
KSO11
23
22 23
KSO14 21 22
KSO13 20 21
20
1
1
1
KSO12 19
R6544 R6527 R6545 R6529 KSO3 18 19
KSO6 17 18
10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 17
KSO8 16
@ @ @ @ KSO7 15 16
15
2
2
2
KSO4 14
KSO2 13 14
KSI0 12 13
R6517 1 2 100_0402_1% F4_LED R6518 1 2 100_0402_1% F1_LED KSO1 11 12
<10> F4_LED# <10> F1_LED# 11
KSO5 10
KSI3 9 10
1 9
1
1
1 KSI2 8
R6526 C6506 R6528 KSO0 7 8
C6505 100K_0402_5% 100P_0402_50V8J 100K_0402_5% KSI5 6 7
100P_0402_50V8J @ 2 EMC@ @ KSI4 5 6
2 EMC@ KSO9 4 5
4
2
2
KSI6 3
KSI7 2 3
KSI1 1 2
1
2
D6503 ME@
PESD5V0U2BT_SOT23-3
EMC@
C C
FnLock_LED
1
+3VALW +3VS
1
R6546 R6531
10K_0201_5% 10K_0201_5%
@ @
2
<40> FN_LED# R6519 1 2 100_0402_1% FN_LED

1
1
R6530
C6507 100K_0402_5%
100P_0402_50V8J @
2 EMC@
2
Click Pad +3VS
Track Point B
1
R6553
Vinafix.com 0_0603_5%_SM
+5VS +VS_BL +5VS +VS_TPCP
ME@
2
HIGHS_FC5AF121-2121H R6551 1 2 0_0402_5%_SM R6508 1 @ 2 0_0201_5%
1
2 1 +3VS +3VS
<9,23,25> PM_SMB_CLK PM_SMB_CLK
3 2
TP_DATA2 4 3 R6552 1 @ 2 0_0201_5% R6541 1 2 0_0402_5%_SM
TP_CLK2 5 4
5 JTP1
<9,23,25> PM_SMB_DAT PM_SMB_DAT 6
6
7 +VS_TPCP 1 1
LID_CLOSE# 8 7 TP_DATA2 2
<10> LID_CLOSE# 8 2
<40> CP_CLK CP_CLK 9 TP_RESET_R 3
9 4 3
<40> CP_DATA CP_DATA 10 TP4MIDDLE
10 5 4
11 13 TP4RIGHT
11 GND1 6 5
<10> PAD_DISABLE PAD_DISABLE 12 14 TP4LEFT
12 GND2 7 6
+3VS +VS_TPCP 8 7
TP_CLK2 8
JCP1 +VS_BL 9
10 9
<40> KB_BLK_PWM KB_BLK_PWM 10
<40> KB_BLK_DTCT# KB_BLK_DTCT# 11 13
12 11 GND1 14
12 GND2
1
1
R6506 R6505
10K_0402_5% 10K_0402_5%
JAE_FL10F012HA1R3000
@
ME@
2
2
R6504 1 2 100K_0402_5% PAD_DISABLE TP_RESET_R +VS_TPCP
+3VS
C6508 1 2 0.1U_0402_10V7-K LID_CLOSE# R6537 1 2 100K_0402_5%
3
D R6501 1 2 4.7K_0402_5% TP_CLK2 +VS_TPCP
TP_RESET# 5 Q6504B
G R6502 1 2 4.7K_0402_5% 1
L2N7002KDW1T1G_SOT363-6 TP_DATA2
@ C6509
S 22U_0603_6.3V6-M
+3VALW
4
2
6
D
<10> TP_RESET 2 Q6504A
G L2N7002KDW1T1G_SOT363-6
SB000013A00 R6539 2 1 100K_0402_5% KB_BLK_DTCT#
S @
A A
1
TP_CLK2 CP_DATA +VS_BL
R6538 1 2 100K_0402_5% KB_BLK_PWM 1
TP_DATA2 CP_CLK
C6510
22U_0603_6.3V6-M
1 1 2
2
C6501 C6502 D6501 R6540 1 2 0_0402_5%_SM

100P_0402_50V8J 100P_0402_50V8J PESD5V0U2BT_SOT23-3
2 EMC_NS@ 2 EMC_NS@ EMC@
1
R6550
10K_0402_5%
1
2
Issued Date 2015/01/12 Deciphered Date 2016/01/12 CP/TPOINT/KB CONN.
Size Document
DocumentNumber
Number Rev
Rev
Date:
Sheet 65 of 99
5 4 3 2 1
5 4 3 2 1
+RTCBATT +RTCBATT <14,80>
+5VS +5VS <47,50,51,60,61,65,72>
FAN CONN.
+3VS +3VS <5,6,9,10,11,12,14,15,23,25,30,32,37,39,40,47,50,51,57,58,59,60,61,63,65,67,69,72,85,86>
+3VALW +3VALW <6,9,12,15,19,40,50,58,60,63,65,67,72,83,84,91,95>
RTC CONN. +5VS
40mil
JFAN1
1
D 7 D
R6602 6 GND2
GND1
0_0603_5%_SM
5
+RTCBATT <40> EC_FAN_PWM 5
4
4
2
3
<40> EC_FAN_SPEED 3
D6601 R6601 JRTC1 +5VS_FAN 2
1 2 RTC_CONN_1 1 2 RTC_CONN 1 1 2
1 <40> FAN_ID 1
2
RB751V-40_SOD323-2 1K_0603_5% 3 2 HIGHS_WS33050-S0351-HF
SCS00006S00 4 GND1 ME@
GND2
ME@
+3VALW
POWER ADAPTER Bi-COLOR(ORANGE/WHITE)
1
R6608
300_0402_5%
@
R6612
LED66
2
1 2 BATT_CHG_LED R6605 1 2 0_0402_5%_SM BATT_CHG_LED_R A1 C
C ORG C
300_0402_5% R6604 1 2 0_0402_5%_SM PWR_STATUS_LED_R A2
6
D WHI
BATT_CHG_LED# 2 Q6603A +5VALW 1222A-S2ST3D-C30-2C-FTK_ORG_WHI
<40> BATT_CHG_LED#
G L2N7002KDW1T1G_SOT363-6 SC50000GM00
2
1 @ S LED LTW-327DSKF-5A 3X1 ORANGE/WHITE
1
1
S
1 R6614
C6602 R6610 R6609 0_0402_5%_SM
100P_0402_50V8J 100K_0402_5% 300_0402_5%
2 EMC@ @ @
1
R6613
2
2
1 2 PWR_STATUS_LED
300_0402_5%
3
D
PWR_STATUS_LED# 5
<40> PWR_STATUS_LED# G Q6603B
1
1 L2N7002KDW1T1G_SOT363-6
R6611 S @
4
C6603 100K_0402_5%
100P_0402_50V8J @
2 EMC@
2
B
Vinafix.com FingerPrint CONN.
+3VS
B
JFPB1
R6606 1 EMC@2 0_0402_5% R6603 1 2 0_0603_5%_SM+3VS_FP 1
2 1
USB20_N8_R
3 2
USB20_P8_R
EXC24CH900U_4P 4 3
5 4
<12> USB20_P8 USB20_P8 4 3 USB20_P8_R
4 3 6 5
6
2
3
1 7
1 2 D6602 8 7
<12> USB20_N8 USB20_N8 USB20_N8_R
2
3
1 2 AZC199-02S.R7G_SOT23-3 C6601 8
L6607 EMC_NS@ 0.1U_0402_10V6-K 9
2 10 GND1
1
GND2
R6607 1 EMC@2 0_0402_5%
1
ME@
A A

Issued Date 2015/01/12 Deciphered Date 2016/01/12 RTC/LED /FAN ,FPR CONN.
Size
Size Document
Number Rev
Rev
Custom 0.2
Date:
Sheet 66 of 99
5 4 3 2 1
5 4 3 2 1
+3VL +3VL <19,40,42,50,72,80,82,83,84>
+3VALW +3VALW <6,9,12,15,19,40,50,58,60,63,65,66,72,83,84,91,95>
+5VALW +5VALW <38,39,42,43,47,64,66,71,72,84,85,86,87,88,89,91,93,94>
+3VS +3VS <5,6,9,10,11,12,14,15,23,25,30,32,37,39,40,47,50,51,57,58,59,60,61,63,65,66,69,72,85,86>

D D
IO_40_Pin conn
+3VL +3VS +5VALW +3VALW
JIOB1
1
2 1
3 2
C 4 3 C
5 4
6 5
7 6
8 7
9 8
10 9
PLT_RST# 11 10
<15,30,40,58,63,69> PLT_RST# 11
<40> LAN_WAKE# LAN_WAKE# 12
CLKREQ_PCIE3_LAN# 13 12
<14> CLKREQ_PCIE3_LAN# 13
CLKREQ_PCIE5_CR# 14
<14> CLKREQ_PCIE5_CR# 14
PWRBTN_LED# 15
<40> PWRBTN_LED# 15
ON/OFF# 16
<40> ON/OFF# 16
USB_ON# 17
<40,64> USB_ON# 17
USB_OC3# 18
<12> USB_OC3# 18
LID_SW# 19
<40> LID_SW# 19
20
20
USB2.0
USB20_P4 21
<12> USB20_P4 21
USB20_N4 22
<12> USB20_N4 22
23
PCIE5_CRX_DTX_N 24 23
<12> PCIE5_CRX_DTX_N 24
PCIE5_CRX_DTX_P 25
<12> PCIE5_CRX_DTX_P 25
26
26
GBE LAN PHY
PCIE5_CTX_C_DRX_N 27
<12> PCIE5_CTX_C_DRX_N 27
PCIE5_CTX_C_DRX_P 28
<12> PCIE5_CTX_C_DRX_P 28
29
CLK_PCIE_LAN 30 29
<14> CLK_PCIE_LAN 30
Vinafix.com CLK_PCIE_LAN# 31
<14> CLK_PCIE_LAN# 31
32
<12> PCIE12_CRX_DTX_N 33
PCIE12_CRX_DTX_P 34
<12> PCIE12_CRX_DTX_P 34
Card Reader
35
B PCIE12_CTX_C_DRX_N 36 35 B
<12> PCIE12_CTX_C_DRX_N 36
<12> PCIE12_CTX_C_DRX_P 37
38
CLK_PCIE_CR# 39 38 41
<14> CLK_PCIE_CR# 39 GND1
CLK_PCIE_CR 40 42
<14> CLK_PCIE_CR 40 GND2
I-PEX_20374-040E-31
ME@
A A

Issued Date 2015/01/12 Deciphered Date 2016/01/12 IO BOARD CONN.
Size
Document Number
Number Rev
Rev
Custom 0.2
Date:
Sheet 67 of 99
5 4 3 2 1
5 4 3 2 1
D D
C C
B
Vinafix.com B
A A

Issued Date 2015/01/12 Deciphered Date 2016/01/12 DOCKING CONN.
Size
Size Document
Number Rev
Rev
Custom 0.2
Date:
30, 2017
2017 Sheet
Sheet 68 of 99
5 4 3 2 1
5 4 3 2 1
+3VS +3VS <5,6,9,10,11,12,14,15,23,25,30,32,37,39,40,47,50,51,57,58,59,60,61,63,65,66,67,72,85,86>
D D
M.2 SSD(M TYPE)
C +3VS +3VS C
1
1
R6901 R6902
10K_0402_5%
0_0805_5%_SM @
2
2
JSSD1
1 2 +3VS_SSD
3 GND_1 3.3V_1 4
5 GND_2 3.3V_2 6
7 PERN3 N/C_2 8
9 PERP3 N/C_3 10
11 GND_3 DAS/DSS#/LED1# 12
13 PETN3 3.3V_3 14
15 PETP3 3.3V_4 16
17 GND_4 3.3V_5 18
19 PERN2 3.3V_6 20
21 PERP2 N/C_4 22
23 GND_5 N/C_5 24
25 PETN2 N/C_6 26
27 PETP2 N/C_7 28
<40>
Vinafix.com
SSD_DET_EC# SSD_DET_EC#
PCIE9_CRX_DTX_N 29 GND_6 N/C_8 30
<12> PCIE9_CRX_DTX_N PERN1 N/C_9
PCIE9_CRX_DTX_P 31 32
<12> PCIE9_CRX_DTX_P PERP1 N/C_10
33 34
C6904 2 1 0.22U_0402_10V6-K PCIE9_CTX_C_DRX_N 35 GND_7 N/C_11 36
<12> PCIE9_CTX_DRX_N PCIE9_CTX_DRX_N
B C6903 2 1 0.22U_0402_10V6-K PCIE9_CTX_C_DRX_P 37 PETN1 N/C_12 38 B
<12> PCIE9_CTX_DRX_P PCIE9_CTX_DRX_P
39 PETP1 DEVSLP 40
PCIE10_CRX_DTX_N 41 GND_8 N/C_13 42
<12> PCIE10_CRX_DTX_N PERN0/SATA-B+ N/C_14
PCIE10_CRX_DTX_P 43 44
<12> PCIE10_CRX_DTX_P PERP0/SATA-B- N/C_15
45 46
PCIE10_CTX_DRX_N C6906 2 1 0.22U_0402_10V6-K PCIE10_CTX_C_DRX_N 47 GND_9 N/C_16 48
<12> PCIE10_CTX_DRX_N PETN0/SATA-A- N/C_17
PCIE10_CTX_DRX_P C6905 2 1 0.22U_0402_10V6-K PCIE10_CTX_C_DRX_P 49 50 PLT_RST#
<12> PCIE10_CTX_DRX_P PETP0/SATA-A+ PERST# PLT_RST# <15,30,40,58,63,67>
51 52 CLKREQ_PCIE1_SSD#
GND_10 CLKREQ# CLKREQ_PCIE1_SSD# <14>
<14> CLK_PCIE_SSD# CLK_PCIE_SSD# 53 54
CLK_PCIE_SSD 55 REFCLKN PEWAKE# 56
<14> CLK_PCIE_SSD REFCLKP N/C_18
57 58
GND_11 N/C_19
59 NC NC 60
61 NC NC 62
63 NC NC 64
65 NC NC 66
67 68
SSD_DET_PCH 69 N/C_1 SUSCLK 70
<12> SSD_DET_PCH PEDET 3.3V_7 72
M2_CARD_DET 71
<12> M2_CARD_DET GND_12 3.3V_8 74
73
75 GND_13 3.3V_9
GND_14
2 1
1
77 76
R6903 PEG1 PEG2 C6902 C6901
0_0201_5% 10U_0402_6.3V6-M .01U_0402_50V7-K
@ ARGOS_NASM0-S6705-TSH4 1 2
ME@
2
A A

Issued Date 2015/01/12 Deciphered Date 2016/01/12 M.2 SLOT CONN.
Size
Size Document
Number Rev
Rev
Custom 0.2
Date:
Sheet 69 of 99
5 4 3 2 1
5 4 3 2 1
D D
C C
Vinafix.com
B
Vinafix.com B
A A

Size
Size Document
Number Rev
Rev
Custom 0.2
Date:
30, 2017
2017 Sheet
Sheet 70 of 99
5 4 3 2 1
5 4 3 2 1
+1VALW +1VALW <14,19,92>
+VCC_STG +VCC_STG <8,16,18>
+VCC_IO +VCC_IO <5,11,18,21>
+5VALW +5VALW <38,39,42,43,47,64,66,67,72,84,85,86,87,88,89,91,93,94>
+VCC_ST +VCC_ST <8,15,16,18,21,86>

D D
+1VALW to +VCC_IO_AP & +VCC_ST
Unstaff C7102 and C7103 for the fastest sequence.

+1VALW +VCC_IO
3 A
U7101 J10 @
1 14 +VCC_IO_AP 1 2
2 IN1_1 OUT1_2 13 1 2
IN1_2 OUT1_1 @ JUMP_43X118
1 1
C +5VALW SUSP 3 12 C7102 1 2 1000P_0402_25V7-K C
<15,40,47,72,85> SUSP EN1 CT1
C7106 C7104
1U_0402_6.3V6-K 4 11 0.1U_0402_10V7-K
2 VBIAS GND @ 2 +VCC_ST
+1VALW
<40,85,94> SYSON
5
EN2 CT2
10 C7103 1 2 100P_0402_50V8-J
60mA
6 9
7 IN2_1 OUT2_2 8 +VCC_ST_OUT R7103 1 2 0_0402_5%_SM
IN2_2 OUT2_1
1 15 1
GPAD
C7107 G5016KD1U_TDFN14_2X3 C7105
1U_0402_6.3V6-K SA000067600 0.1U_0402_10V7-K
2 2
S IC G5016KD1U TDFN 14P LOAD SWITCH

Vendor LCFC P/N Description +VCC_IO +VCC_STG
Vinafix.com GMT SA000067600 S IC G5016KD1U TDFN 14P LOAD SWITCH
TI SA00008C900 S IC TPS22976DPUR WSON 14P LOAD SWITCH
R7104 1 2 0_0402_5%_SM
B B
Slew Rate=10uS<TR<65us
A A

Issued Date 2015/01/12 Deciphered Date 2016/01/12 VCCIO/VCCSTG/VCCST/+VCC
Size
Size Document
Number Rev
Rev
Custom 0.2
Date:
Sheet 71 of 99
5 4 3 2 1
5 4 3 2 1
+5VALW +5VALW <38,39,42,43,47,64,66,67,71,84,85,86,87,88,89,91,93,94>
+5VS +5VS <47,50,51,60,61,65,66>
+3VALW +3VALW <6,9,12,15,19,40,50,58,60,63,65,66,67,83,84,91,95>
+3VS +3VS <5,6,9,10,11,12,14,15,23,25,30,32,37,39,40,47,50,51,57,58,59,60,61,63,65,66,67,69,85,86>
+3VALW_PCH +3VALW_PCH <8,9,10,11,12,19>
+3VL +3VL <19,40,42,50,67,80,82,83,84>

D D
+1VALW_SUS +1VALW_SUS <19>
+3VL
R7201 1 @ 2 SUSP 10K_0402_5%
Smart Switch
1. MIRROR code, is correct????
2. After reset EC, EC control "Low", not High or Disable. +5VALW To +5VS
+3VALW To +3VS
+5VALW +5VS
VIN 5V and 3.3V (VBIAS=5V), IMAX(per channel)=6A, Rds=18mohm
U7201 J5 @
1 14 +5VS_LS 1 2
2 VIN1_1 VOUT1_2 13 1 2
+5VALW VIN1_2 VOUT1_1 JUMP_43X118
C SUSP 3 12 C7203 1 2 1000P_0402_25V7-K C
<15,40,47,71,85> SUSP ON1 CT1
1
4 11 +3VS
VBIAS GND 1
C7201
1U_0402_6.3V6-K SUSP 5 10 C7204 1 2 100P_0402_50V8-J C7205
2 +3VALW ON2 CT2 0.1U_0402_10V7-K
6 9 J6 @ 2
7 VIN2_1 VOUT2_2 8 +3VS_LS 1 2
VIN2_2 VOUT2_1 1 2
1 15 JUMP_43X118 1
GPAD
C7202 TPS22966DPUR_WSON14_2X3 C7206
1U_0402_6.3V6-K SA00008C900 0.1U_0402_10V7-K
2 2
S IC TPS22976DPUR WSON 14P LOAD SWITCH
+5VS, C159 --> 1.5ms
+3VS, C160 --> 2.5ms
B
Vinafix.com Vendor
TI
GMT
LCFC P/N
SA00008C900
SA000067600
Description
S IC TPS22976DPUR WSON 14P LOAD SWITCH
S IC G5016KD1U TDFN 14P LOAD SWITCH
B
+5VALW
1
1
1
C7207 C7208 C7209

0.1U_0402_16V7-K 0.1U_0402_16V7-K 0.1U_0402_16V7-K
2
2
2
EMC_NS@ EMC_NS@ EMC_NS@
B+
A A
1
1
1
C7210 C7211 C7212 C7213

0.1U_0402_16V7-K 0.1U_0402_16V7-K 0.1U_0402_16V7-K 0.1U_0402_16V7-K Title
2
2
2
EMC_NS@ EMC_NS@ EMC_NS@ EMC_NS@

Issued Date 2015/01/12 Deciphered Date 2016/01/12 DC V TO VS/ V-PCH
Size
Size Document
Number Rev
Rev
Custom 0.2
Date:
Sheet 72 of 99
5 4 3 2 1
5 4 3 2 1
D D
C C
B
Vinafix.com B
A A

Size
Size Document
Number Rev
Rev
Custom 0.2
Date:
30, 2017
2017 Sheet
Sheet 73 of 99
5 4 3 2 1
5 4 3 2 1
D D
C C
B
Vinafix.com B
A A

Size
Size Document
Number Rev
Rev
Custom 0.2
Date:
30, 2017
2017 Sheet
Sheet 74 of 99
5 4 3 2 1
5 4 3 2 1
D D
C C
Vinafix.com
B
Vinafix.com B
A A

Size
Size Document
Number Rev
Rev
Custom 0.2
Date:
30, 2017
2017 Sheet
Sheet 75 of 99
5 4 3 2 1
Vinafix.com
Custom 0.2
5 4 3 2 1
D D
C C
B
Vinafix.com B
A A

Size
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document
Document Number
Number Rev
Rev
C 0.2
0.2
Date:
Date: Monday,
Monday, October
October 30,
30, 2017
2017 Sheet
Sheet 77
77 of 99
99
5 4 3 2 1
5 4 3 2 1
Screw Hole
H1 H2 H3 H4
PAD_C5P0D3P4 PAD_C6P0D3P4 PAD_C6P0D3P4 PAD_C6P0D3P4
D
CPU @ @ @ @
D
1
H24
PAD_CB6P0D3P2
WLNN @
H5 H6 H7 H8 H9 H10
PAD_C3P0D2P4 PAD_C6P0D2P8 PAD_CT6P0B8P0D2P3 PAD_C8P0D2P3 PAD_O2P6X3P2D2P6X3P2 PAD_C2P8D2P3
C C
@ @ @ @ @ @
1
1
1
1
H11 H12 H14 H15 H16 H17
PAD_O2P6X3P65D2P6X3P65 PAD_O2P3X2P8D2P3X2P8 PAD_C8P0D2P3 PAD_C2P8D2P3 PAD_C2P8D2P3 PAD_C5P0D2P3
@ @ @ @ @ @
1
1
1
H18 H19 H20
PAD_C6P0D2P3 PAD_C2P8D2P3 PAD_C6P0D2P3
@ @ @
1
Vinafix.com H21
PAD_CT6P0B5P0D3P3
1
B B
H23 H22
PAD_C2P4D2P4N PAD_O2P4X2P9D2P4X2P9N
PCB Fedical Mark PAD @ @
1
1
FD1 FD2 FD3 FD4 FD5 FD6

1
1
1
1
1
1
A A

Issued Date 2015/01/12 Deciphered Date 2016/01/12 SCREW HOLE
Rev
Custom
Custom 0.2
0.2
Date: Monday,
Monday, October
October 30,
30, 2017
2017 Sheet
Sheet 78
78 of 99
99
5 4 3 2 1
5 4 3 2 1
D D
VRAM GPU
ZZZ UV3001
X7644801001 AMD(R17M-P1-50)
S8G@ SA00008DT10
P50@
ZZZ2
UV3001
X7644801002
H8G@
AMD(R17M-P1-70)
ZZZ3
SA00008ED10
P70@
C X7644801003 C
M8G@
CPU PCB
UC1 UC1 UC1 UC1 UC1
ZZZ4
I3-7130U KBL I5-7200U KBL I5-7300 KBLV I5-8250U KBLR I7-8550U KBLR
PCB NM-B041
SA00008LM20 SA000080350 SA000086M10 SA00008J520 SA00008J620
KBLI3@ KBLI5@ KBLI5V@ KBLRI5@ KBLRI7@ DAZ16600100
B
Vinafix.com B
A A

Issued Date 2013/11/04 Deciphered Date 2014/12/31 PLM BOM
Size
Size Document
Number Rev
Rev
Custom 0.2
Date:
30, 2017
2017 Sheet
Sheet 79 of 99
5 4 3 2 1
5 4 3 2 1
D D
PD1 1SS355VMTE-17
PD2 1 2
1SS355VMTE-17 PR1 PR2 VSYSTEM2
@ PR6 0_0402_5%_SM 100K_0402_1% 10K_0402_1%
1 2 2 1 1 2 1 2 1 2
[57,66,68] MAINPWON_EC B+
20170905 PD3
1SS355VMTE-17
2
3
E
PQ1
2
B PR3
PMBT3906 750K_0402_5%
1
C
1
VCCGT VCORE1 VCORE2 VCCSA
540_0402NEW_30% 540_0402NEW_30% 540_0402NEW_30% 540_0402NEW_30%
1
C PRT1 PRT2 PRT3 PRT4
PQ2 2 2 1 2 1 2 1 2 1
PMBT3904 B
E 2
C
3 D C
1
PC1 2 OTP_RESET [57]
1U_0603_25V7K G
1 S PQ3 2N7002WT1G
3
2 1 2 1 2 1 2 1
PRT9 PRT8 DIS@ PRT6 DIS@ PRT5

540_0402NEW_30% 540_0402NEW_30% 540_0402NEW_30% 540_0402NEW_30%
Charger
1.2VS VGA_VDDCI VGA
2 1 2 1
UMA@ PR10 UMA@ PR7
0_0402_5% 0_0402_5%
Vinafix.com RTC Battery
B +3VL B
2
PR4
3.01K_0402_1%
+RTCBATT
1
<10,50> 1 2
PD6
2
CUS357_SOD323-2
PR5
43K_0402_1%
1
A A
Issued Date 2013/08/05 Deciphered Date 2014/12/31 VIN Detector

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Number Rev
Rev
Custom 2.0
Sheet 80 of 99
5 4 3 2 1
5 4 3 2 1
D D
C C
BLANK
B
Vinafix.com B
A A

Issued Date 2015/09/01 Deciphered Date 2016/12/31 XXXX
Size
Size Document
Number Rev
Rev
Custom 2.0
2.0
Date:
Date: Monday,
Monday, October
October 30,
30, 2017
2017 Sheet
Sheet 81
81 of 99
99
5 4 3 2 1
5 4 3 2 1
D D
PL3 EMC@
MURATA BLM18KG300TN1D
PRT7 under CPU bottom side for CPU thermal protection.
ME@ VMB2 VMB 1 2
JBATT1 PF2 This is for thermal team request.
HIGHS_WS33081-S0201-HF 12A_32V_0501012.WRS PL4 EMC@
1 2 1 MURATA BLM18KG300TN1D
1 2 BATT+
9
PTH1 2 3 EC_SMCA 1 2
10 3 4 EC_SMDA
PTH2 4 5
5 6 EMC@ EMC@
2
11
PTH3 6 7 PC9 PC10
12 7 8 1000P_0402_50V 0.01U_0402_25V
PTH4 8
1
2
PESD5V0U2BT_SOT23-3
+VL_3.3V
1
EMC_NS@
C C
2
PR15
PR14 PR11
1
PD7
100_0402_1% 16.5K_0402_1%
1
100_0402_1% PC2
2
0.1U_0603_16V7K PU1
1
1 8 NTC_V_1
VCC TMSNS1
2 7 OTP_N_002 2 1
GND RHYST1
EC_SMB_CK1 [57,67] [57,65,68] MAINPWON_EC 1 2 OTP_N_003 3 6 PR12
@ PR13 0_0402_5%_SM OT1 TMSNS2 10K_0402_1%
1
4 5
EC_SMB_DA1 [57,67] OT2 RHYST2
20170905 PRT7
G718TM1U_SOT23-8 100K_0402_1%_NCP15WF104F03RC
PR16 1M_0402_5%
2 1 +3VL
2
B
1 2
A/D B
BATT_TEMP [57,67]
PR17
10K_0402_1%
BATT_OUT [57,67]
A A

Issued Date 2013/08/05 Deciphered Date 2014/12/31 BATTERY CONN/OTP
Size Document
Document Number
Number Rev
Rev
Custom 2.0
Vinafix.com Date:
Sheet 82 of 99
5 4 3 2 1
5 4 3 2 1
PJ101
2 1
2 1
@ JUMP_43X79
D D
VSYSTEM2
EMC_NS@
PL101
1UH_PCMB053T-1R0MS_7A_20% PR102 PQ102 PL102 PQ101
0.01_1206_1% BSC0923NDI_PG-TISON-8-7 EMC@ 2.2UH_CMLE063T-2R2MS_10A_20% SIZ340DTT1_POWERPAIR_3X3-9-10
EMC_NS@ EMC_NS@ 1 2 VSYSTEM3 1 2 VBUS PR106 56_0402_5% 1 2 EMC@ EMC@ EMC@
B+
9
7
EMC@
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
33U_D2_25VM_R40M
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
2 2
1
1
1
1
PC101 PC102
10_0201_1%
1000P_0201_50V7-K
10U_0805_25V6K
0.1U_0402_25V6-K
0.01U_0201_25V7-K
0.1U_0402_25V6-K
1
1
1
1
1
1
2
1
PR104 5 0.047U_0402_25V7K 0.047U_0402_25V7K 7 10
PC123
PC116
PC112
PC115
PC106
PC110
PR103
PC111
PC113
PC114
0.1U_0402_25V6-K
0.1U_0402_25V6-K
EMC@
1
1
1
1
1
+ 2 4 PR105 6 4
PC109
10_0201_1%
EMC@
PC144
PC143
1 1
1
1
1
3 56_0402_5% 5 3
330P_0402_50V7-K
@ PC117
PC139
PC105
PC104
PC107
PC140
PC108
2
2
2
2
2
1
2
2
2
0.1U_0402_25V7K PR107 2
PC103 EMC@
12
2
1 2
2
2
2
2
2
2
2 1 2.2_0603_5% PR108
2
2
2
2.2_0603_5% PC119
PC118
0.01U_0402_25V7K
2 330P_0402_50V7-K PQ103
2
AON7401
0_0201_5%_SM
30 25
0_0201_5%_SM
2 @ @
BTST1 BTST2
1
1
1
6
1
1
1
PC121
PC120 LX1_CHG 32 23 LX2_CHG 2 PR111
PR110
PR109
0.01U_0402_25V7K 1 SW1 SW2 3 0.01_1206_1%
1
1
DL1_CHG 29 26 DL2_CHG 5 1 2
LODRV1 LODRV2 BATT+
2
2
PC122 DH1_CHG 31 24 DH2_CHG PC125
10U_0805_25V6K
0.1U_0402_25V7K
HIDRV1 HIDRV2 1 1
4
2
1
20170905 0.47U_0603_25V6-K 1 2
1U_0402_25V6-K
1U_0402_25V6-K
@ PC146
0.1U_0402_25V7K
1 22
PC126
PC124
VBUS VSYS
1
1
0.1U_0402_25V7K
PC128
PC127
2 2
2
C @ PC129 2 21 BATDRV# C
1U_0402_25V6-K ACN BATDRV#
2
2
1 2 3 20
ACP SRP
1 2 VDDA 7 PU101 19
BQ25700_VDD VDDA SRN PR113 10_0603_5% 1 2
BQ25700ARSNR_QFN32_4X4 BQ25700_VDD
1
PR112 6 28 1 2 PR114 10_0603_5% 1 2
10_0402_1% PR115 PR116 40.2K_0201_1% ILIM_HIZ REGN PC130 2.2U_0402_10V6-K
255K_0201_1% 1 2 1 2 PC132 680P_0201_25V7-K
1 PC131 1800P_0201_25V7-K 16 17 1 2 1 2
2 1 PC133 COMP1 COMP2 PR117 20K_0201_1%
2
PC134 100P_0201_50V7-K 1 2
1U_0402_25V6-K VR_HOT#_P 1 2 11 18 PC135 15P_0201_25V8-J
2 PROCHOT# CELL_BATPRES
1
@ PR119 0_0201_5%_SM
1 2 20170905 13 20170905
220K_0201_5%
PD101 <40,82> EC_SMB_CK1 SCL @1 2
@ PR120 0_0402_5%_SM 8
PR118
IADPT ADP_I <40>
<8,40,86> VR_HOT# 2 1 VR_HOT#_P 1 2 12 20170905 PR121 0_0402_5%_SM
<40,82> EC_SMB_DA1 @ PR122 0_0402_5%_SM SDA 9 @1 2
IBAT
2
<40> ACIN 1 2 4 PR124 0_0201_5%_SM
1SS355VMTE-17 @ PR125 0_0402_5%_SM CHRG_OK 10 @1 2
PSYS PSYS <86>
1 2 5 PR126 0_0201_5%_SM
PD103 @ PR127 0_0201_5%_SM ENZ_OTG 27 VDDA
PGND
1
2 1 15
100P_0201_50V7-K
100P_0201_50V7-K
100P_0201_50V7-K
<32> GPU_GPIO5 CMPOUT
1
PR128 33
PAD
1
2
2
2
14 PR129
1SS355VMTE-17 D 100K_0201_1% CMPIN +3VALW
1
20170905 137K_0402_1% PR123
PC138
PC136
PC137
1 2 2 PQ105 82K_0201_1%
<40> ACOFF
1
2
@ PR131 0_0402_5%_SM G 2N7002WT1G_SC-70-3
1
B
S B
2
3
2
PR135
300K_0201_1%
PR133 VSYSTEM2
1
10K_0201_1% PD102 D
1
2
PR130
2
1
1 2 2 100K_0201_1%
@ PR150 <82> BATT_OUT G PQ104
100K_0201_1% S
+3VALW +3VL 1SS355VMTE-17
3
1
2
2N7002WT1G_SC-70-3
PR132
1
1M_0201_5%
10K_0201_1%
2
1
2
@ PR154
2
1
@ PR153 @ PC145 PR151 @
10K_0201_1% 0.1U_0402_25V7K 0_0201_5%_SM
@ PR152
2
0_0201_5% 20170905
2
1
@ POUT PAD 1 1 2
A A
Vinafix.com 5 4 3
Security Classification
LC Future Center Secret Data
Deciphered Date
2
Size
Size Document
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
Date:
Date:
Document Number
Number
Monday,
Monday, October
October 30,
30, 2017
2017
2014/12/31
Title
CHARGER
1
!!"#$%&'()"*+
Sheet
Sheet 83 of 99
Rev
Rev
2.0
5 4 3 2 1
+3VALW
1
@ PR210 +3VALW
100K_0402_5%
FSW=750 KHz
B+
PU201
TDC:8A
2
@ SYX198BQNC_QFN10_3X3
2
PJ201
1 EMC@ EMC@ RF_NS@ +3V_VIN 7 2 +3V_PWRGD
OCP:11A
2 1 EN2 PG
2200P_0402_25V7-K
D @ PR202 PC203 D
1
47P_0402_50V8-J
10U_0805_25V6-K
0_0603_5%_SM 0.1U_0603_25V7-M
0.1U_0402_25V6-K
1
+3VALW
1
1
1
JUMP_43X79 PR201 8 6 +3VBS 1 2 1 2
PC232
PC201
IN BS
PC202
1M_0402_5% PL201
8A
PC230
2.2UH_PCMB063T-2R2MS_8A_20% PJ202
2 EMC@ EMC@
2
2
2
9 10 +3VLX 1 2 +3VALW_P 2 1
GND LX 2 1
2
@ PR203
0_0402_5%_SM @ JUMP_43X118
EMC_NS@
2200P_0402_25V7-K
3V5V_ON 1 4 +3VALW_OUT 1 2 +3VALW_P
EN1 OUT
22U_0805_6.3V6-M
22U_0805_6.3V6-M
@ PR205
22U_0805_6.3V6-M
PR204
22U_0805_6.3V6-M
0.1U_0402_25V6
100mA 0_0402_5%_SM 4.7_0603_5% 1 1 1 1
1
1
PR206 +3VALW_FB 3 5 1 2
PC206
PC211
PC207
PC210
PC205
PC204
20K_0402_1% FB LDO +3VL
2 1
[57] EC_ON EC_ON 1 2 1
EMC_NS@ 2
2
2 2
2
PC208 2
4.7U_0603_6.3V6-K PC209
1 2 680P_0402_50V7K
2
1
@ PR231 0_0201_5%
1
2
@ PC213 PR208
+3VL 0.1U_0402_25V6-K 1M_0402_5%
1
47K_0402_1%
PC212 PR207
2
1
0.01U_0402_25V7-K 1K_0402_1%
PR216
47K_0402_1%
1 2 1 2
PR217
D
6
2 2
2
G
D
3
C C
47K_0201_5%
S
1
5 NTJD5121NT1G
PR230
[57,65,66] MAINPWON_EC
G
4 S PQ201A
1
NTJD5121NT1G @
PQ201B
+5VALW
+3VALW
FSW=750 KHz
TDC:8A
1
@ PR209
100K_0402_5%
OCP:12A
B+ @
PJ203 PR212 PC217
RF_NS@ EMC@ EMC@
2
2 1 +5V_VIN 10_0603_5% 0.1U_0603_25V7-M
2 1
2200P_0402_25V7-K
+5V_PWRGD 1 2 1 2
47P_0402_50V8-J
+5VBS
10U_0805_25V6-K
10U_0805_25V6-K
0.1U_0402_25V6-K
1
1
1
1
JUMP_43X79 PU202
PC215
PC214
PC216
PC233
PC231
+5VALW
1
7
PL202
8A
PGOOD
BOOT
2
2
2
2 1UH_PCMC063T-1R0MN_11A_20% PJ204
5 2 +5VLX 1 2 +5VALW_P EMC@ EMC@ 2 1
VIN LX1 2 1
2
B 3 @ JUMP_43X118 B
LX2 EMC_NS@PR214
2200P_0402_25V7-K
10P_0402_50V8-J
1
22U_0805_6.3V6-M
22U_0805_6.3V6-M
4.7_0603_5%
22U_0805_6.3V6-M
22U_0805_6.3V6-M
0.1U_0402_25V6
1
LV6228CGQUF_UQFN12_3X3 @ PR224
PC234
1 1
1
1
1
6 10
PC224
PC223
PC228
3V5V_ON +5VOUT
PC221
PC222
PC227
EN VOUT 0_0402_5%_SM
1
20170905
@ PR222 2
0.1U_0402_25V6-K
Vinafix.com @
2
2
2
2 2
2
1
2
12 100mA 0_0402_5%_SM 20170905
PC219
+5VALW CLK 11 1 2
LDO EMC_NS@
1
1K_0402_1%
+VL_3.3V
2
PR226
PC226
1
4.7U_0603_6.3V6-K
@ 1 2 680P_0402_50V7K
VCC
PGND
AGND
PR220 1 +5VALW_P
+5V_VCC
@
PC225
0_0402_5% @ PR223
2
0_0402_5%
LV6228C RT6228A 2
4
8
2
1U_0402_6.3V6-K
2
1
PR220 NC 0 @
1
PC218 PR225
PC229
1
PR221 0 NC 1U_0603_25V6M 15K_0402_5%

1
@ PR221
2
PC225 4.7U 1U 0_0402_5%_SM
2
PR222 0 NC
2
20170905
PR223 NC 0
PR224 0 115K
PR225 NC 15K
A
PC234 NC 10P A
PR226 NC 1K

Issued Date 2013/08/08 Deciphered Date 2013/08/05 3VALWP/5VALWP
Size
Size Document
Number Rev
Rev
Custom 2.0
Date:
Sheet 84 of 99
5 4 3 2 1
A B C D
PJ301
2 1
2 1
@ JUMP_43X118
PJ302 +1.2V
+1.2VP 2 1
2 1
1
@ JUMP_43X118 1
+1.2VP PJ303
2 1
PJ304 +0.6VSP 2 1 +0.6VS
B+ EMC@ EMC@ RF_NS@ RF_NS@
1
2 1 B+_1.2V
2 1 PC301 @ JUMP_43X39
2200P_0402_25V
@ JUMP_43X79
47P_0402_50V8-J
10U_0603_6.3V6M
68P_0402_50V8J
0.1U_0402_25V6
2
10U_0805_25V6-K
10U_0805_25V6-K
1 1
1
1
1
PC302
PC305
PC304
PC307
PC306
PC303
2 +0.6VS
2
2
2
2
TDC: 1.5A
133K_0402_1%
PR301
100K_0402_1% +0.6VSP
PR302
+0.6VSP
1 2
+1.2VP
1.2V
10U_0603_6.3V6M
0.1U_0402_6.3V7-K
TDC: 8A
1
PC308
PC309
OCP: 10A
Fsw: 300KHz
14
11
13
20
19
2
PQ301
PGND
CS
VID
VTT
VLDOIN
AON7408L PR303 21
2.2_0603_5% PAD
4 1 2 1 2 18 1
BOOT VTTGND
PC310
0.22U_0603_25V7K DH_1.2V 17
UGATE VTTSNS
2 +0.6VSP
PL301
3
2
1
2
1UH_PCMC063T-1R0MN_+-20% 2
PU301 3 VTTREF_0.6V
EMC@ EMC@ 1 2 LX_1.2V 16 RT8231AGQW
GND
+1.2VP PHASE
4 VTTREF_0.6V
EMC_NS@ VTTREF
2
PR306
2200P_0402_25V7-K
PR304 DL_1.2V 15 5.1_0603_5%

LGATE
2
470P_0402_50V7K
4.7_0603_5% 12 2 1
0.1U_0402_25V6
330U_D2_2V_R9M
1 VDD +5VALW
1
PR305
PGOOD
1
1
+
PC312
@ PC314
5 PC315
PC313
PC311
6.04K_0402_1% VDDQ 1
TON
1
5
PQ302 0.033U_0402_16V7K
FB
S5
S3
2
AON7380 PC316
2
2
2
1
1U_0402_10VA-K
EMC_NS@ 2
10
7
9
4
2
PC317
680P_0402_50V7K
2 TON_1.2V
1
3
2
S5_1.2V
S3_1.2V
@ PR308
1
2
100K_0402_1%
1 2 +3VS
PR307
887K_0402_1%
10K_0402_1%
@ PR310 0_0402_5%_SM
1
1 2
PR309
SM_PG_CTRL [7]
FB_1.2V
20170905
@ PR311
1
B+_1.2V 0_0402_5%
Vinafix.com 1 2 SUSP [50,57]
@ PR312 0_0402_5%_SM
1 2
[50,57,78] SYSON
1
3 20170905 3
@ PC318
2
0.1U_0402_6.3V7-K
2
1
@ PR313 @PC319
47K_0402_5% 0.1U_0402_16V
2
1
4 4

Issued Date 2013/08/05 Deciphered Date 2014/12/31 +1.2V/+0.6VS
Size
Size Document
Number Rev
Rev
Custom 2.0
Date:
Sheet 85 of 99
A B C D
5 4 3 2 1
B+ +5VALW
+VCC_ST 20170904
1
1 +3VS
1
1
PC401 PR401 PR402 PC402
0.01U_0402_25V7-K 1K_0402_5% 2_0402_5% 1U_0402_6.3V6-K PR470 @
1 1K_0402_1%
2
PC403 2
2
D 0.1U_0402_6.3V6-K D
2
1
1
PR403 PR404 2
100_0402_5% 47_0402_5%
2
12
13
PR406
2
10K_0402_1%
VRMP
VCC
1
20170905
@ PR407
0_0402_5%_SM
[57] VR_ON VR_ON 1 2 37 38 VGATE VGATE [57]
@ PR408 EN VR_RDY PR409
0_0402_5%_SM 75_0402_5%
VR_SVID_ALRT# 1 2 33 31 1 2 VR_HOT# VR_HOT# [6,57,67]
[16] VR_SVID_ALRT# ALERT# VR_HOT#
PR410 51_0402_5%
[16] VR_SVID_CLK VR_SVID_CLK 1 2 34 35 DRVON DRVON [71,72,73]
PR411 SCLK DRVON
10_0402_5%
[16] VR_SVID_DAT VR_SVID_DAT 1 2 32 22 PWM_1A
SDIO PWM_1A PWM_1A [71]
[67] PSYS PSYS 46 29 PR412 1 2 7.5K_0603_1% SW_1A SW_1A [71]

PSYS CSP_1A
1
2 1 PC441 PR405
PR413 1U_0402_6.3V6-K 12K_0402_1%
PC404 16.5K_0402_1% 1 2
2
1000P_0402_25V7-K PR414
[16] VCCGT_SENSE VCCGT_SENSE 1 2 1 2 20170905
1
4.42K_0402_1%
1000P_0402_50V7-K
0.033U_0402_25V7K
PU401 1 PRT401
2
PR415 PC405 PC440 MURAT_NCP15WF104F03RC
1 2 24 NCP81218MNTXG_QFN48_6X6 PC467
4.12K_0402_1% VSP_1A
2200P_0402_25V7-K
2 PLACE CLOSE TO
2
2
1
2
PC406
PR464
10_0402_1%
VCCGT PL403
1000P_0402_25V7-K 28 1 2 CSN_1A CSN_1A [71]
CSN_1A
1
PR416
910_0402_1%
1 2 25 23 1 2
VSN_1A TSENSE_1PH
PC407 @ PR417
3300P_0402_50V7-K 0_0402_5%_SM
1
[16] VSSGT_SENSE VSSGT_SENSE 1 2
2
1
20170905 PRT402
PC409 150P_0402_50V8-J PC408 PR418 MURAT_NCP15WF104F03RC
1 2 26 0.1U_0402_25V6-K 61.9K_0402_1%
COMP_1A
2
C C
PLACE CLOSE TO
2
PR419 PC410
1
1 2
2.15K_0402_1%
1 2 VCCGT PU402
0.015U_0402_25V7-K
PR420 47K_0402_1%
2 1 27
ILIM_1A
PR421 16 PWM1_2PH PWM1_2PH [72]
95.3K_0402_1% PWM1_2PH
1 2 30
IOUT_1A 17
PWM2_2PH PWM2_2PH PWM2_2PH [72]
PC411 1 2 270P_0402_50V7-M
PC412 1 21000P_0402_50V7-K PR422

10 1 2 CSP1 CSP1 [72]
47 CSP1_2PH 2K_0402_1% U42@ PR461
[16] VCC_SENSE VCC_SENSE
VSP_2PH 9 1 2
CSP2_2PH CSP2 [72]
U22@ PR468 2K_0402_1%
750_0402_1% U22@ PR462
1
1 2 U42@ 1 2 +5VALW
1
2
PC465 1K_0402_5%
PC413 U42@ PR424 PC414 0.1U_0402_25V6-K
2
1000P_0402_25V7-K 1.05K_0402_1% 0.1U_0402_25V6-K PR423
2
1
1 2 48 10_0402_1%
VSN_2PH 8 1 2
CSREF_2PH CSN1 [72]
PC415 U42@ PR425 1
3300P_0402_50V7-K 26.1K_0402_1% PC417 U42@ PR451
[16] VSS_SENSE VSS_SENSE 1 2 1 2 1 0.1U_0402_16V7-K 10_0402_1%
IOUT_2PH 1 2 CSN2 [72]
U22@ PR465 2
32.4K_0402_1% U42@ PR452
1 2 80.6K_0603_1%
1 2 CSP2
1 2 PR426
PC416 470P_0402_50V8-J 80.6K_0603_1%
2 7 1 2 CSP1
DIFFOUT_2PH CSSUM_2PH
U42@ PR469 3
FB_2PH
2
845_0402_1%
1 2 PC418 PC419
PR429 PC420 100P_0402_50V7-K 1000P_0402_25V7-K
1
U22@ PR428 4.75K_0402_1% 2200P_0402_25V7-K PR427 PR430
1 2 1 2 1 2 4 73.2K_0402_1% 165K_0402_1%
PR431 PC421 PC422 COMP_2PH 6 1 2
510_0402_1% 1 2
49.9_0402_1% 33P_0402_50V8-J CSCOMP_2PH U42@ PR432
470P_0402_50V8-J
1 2 1 2 1 2 16.9K_0402_1%
B
PC423 PR433
ILIM_2PH
5 1 2 PLACE CLOSE TO B
1000P_0402_25V7-K 2.94K_0402_1%
1 2 1 2 1 2 PRT403 1 2 VCCCPUCORE PL406
U22@ PR467 10K_0402_1% MURAT_NCP15WM224J03RC
[16] VCCSA_SENSE 1 2 45
PR434 VSP_1B
2.61K_0402_1% 20170905
Vinafix.com 11 1 2 PRT404 1 2
TSENSE_2PH
2
2
MURAT_NCP15WF104F03RC
PC425
1
@ PR435 PR436
1000P_0402_25V7-K 0_0402_5%_SM 61.9K_0402_1% PLACE CLOSE TO
1
PR437 PC424
VCCCPUCORE PU403
2
1K_0402_1% 0.1U_0402_25V6-K
[16] VSSSA_SENSE
1
1 2 44
VSN_1B
PC427 36 PWM_1B
PWM_1B PWM_1B [73]
15P_0402_50V8-J PC426 1 2 3300P_0402_50V7-K
1 2 43 40 PR438 1 2 7.5K_0603_1% SW_1B [73]
COMP_1B CSP_1B SW_1B
PC428
0.01U_0402_25V7K 1 2 PRT405 1 2
1 2 1 2 PR441 MURAT_NCP15WF104F03RC
35.7K_0402_1% 12K_0402_1%
ROSC_COREGT
PR440 PR439 PLACE CLOSE TO
1
1 2 42 PC429 PC439
ADDR_VBOOT
ILIM_1B
ICCMAX_2PH
ROSC_SAUS
1.5K_0402_1%
0.018U_0402_50V7-J
3300P_0402_50V7-K
VCCSA PL408
ICCMAX_1B
ICCMAX_1A
PC431
2
1000P_0402_50V7-K
1 2 39 41 1 2 CSB_1B CSB_1B [73]
IOUT_1B CSN_1B
TAB
1
PC466 PR463
2200P_0402_25V7-K 10_0402_1%
21
20
14
15
49
19
18
2
24K_0402_1%
PR442
24K_0402_1%
49.9K_0402_1%
97.6K_0402_1%
100K_0402_1%
90.9K_0402_1%
19.1K_0402_1%
1 2
35.7K_0402_1%
PC430
270P_0402_50V7-M
2
1 2
2
2
1
1
2
PR447
1
1
1
1
2
2
PR443
U22@ PR466
PR444
PR446
PR448
U42@ PR445
A A

Issued Date 2013/08/05 Deciphered Date 2014/12/31 IMVP8
Size Document
DocumentNumber
Number Rev
Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 2.0
Date:
Sheet 86 of 99
5 4 3 2 1
5 4 3 2 1
PL404
BLM18KG300TN1D
EMC@EMC@RF_NS@ 1 2
B+
EMC@
PC446 PC447 PC448 PC449 PC450 PC451 PL405
BLM18KG300TN1D
47P_0402_50V8-J
1
1
1
1
1
1 2
2200P_0402_25V7-K
10U_0805_25V6-K
10U_0805_25V6-K
10U_0805_25V6-K
10U_0805_25V6-K
PC452
0.1U_0402_25V6
D EMC@ For U42 D
2
2
2
2
2
2.2_0603_1% +VCC_CORE
5
PR453
2 1 PQ404 TDC= 42A
TPCA8065-H
IccMAX=64A
2
PC453
0.22U_0603_25V7-K
HG_B1 4 OCP=70A
1
PU403
NCP81151MNTBG_DFN8_2X2
1 8 PL406
BST DRVH 0.15UH_CMLE064T-R15MS0R725-88_35A_20%
3
2
1
2 7 SW_B1 1 4
[70] PWM1_2PH PWM SW
+VCC_CORE For U22
2
3 6 2 3 1
[70,71,73] DRVON EN GND PR454 PC454
+5VALW
4
VCC DRVL
5 4.7_0603_5% + +VCC_CORE
330U_D2_2VM_R9M
FLAG
EMC@ 2
TDC= 21A
2 1
1
PC455 LG_B1 4 4
1U_0402_10V IccMAX=31A
9
PC456
OCP = 36A
2
680P_0402_50V7K
1
3
2
1
3
2
1
PQ405 PQ406 EMC@
C TPCA8057-H TPCA8057-H C
CSN1 [70]
20170922
CSP1 [70]
For U42
PL409
U42_EMC@ U42_EMC@ U42_RF_NS@ BLM18KG300TN1D
1 2
U42_EMC@ B+
U42@ U42@ U42@ U42@
PC530 PC531 PC532 PC533 PC534 PC535 PL410
BLM18KG300TN1D
47P_0402_50V8-J
1
1
1
1
1 2
2200P_0402_25V7-K
10U_0805_25V6-K
10U_0805_25V6-K
PC536
0.1U_0402_25V6
10U_0805_25V6-K
10U_0805_25V6-K
U42_EMC@
2
2
2
U42@
2.2_0603_1%
5
PR459 U42@
2 1 PQ409
B
TPCA8065-H B
2
U42@ PC537
Vinafix.com 0.22U_0603_25V7-K
HG_B2 4
1
U42@ PU405
NCP81151MNTBG_DFN8_2X2 U42@
1 8 PL411
BST DRVH
0.15UH_CMLE064T-R15MS0R725-88_35A_20%
2
1
3
[70] PWM2_2PH 2 7 SW_B2 1 4

PWM SW
+VCC_CORE
5
5
2
DRVON 3 6 2 3 U42@ 1
EN GND PC540
PR460
4 5 +
4.7_0603_5%
+5VALW VCC DRVL
330U_D2_2VM_R9M
FLAG
U42@ U42_EMC@
2
2 1
1
PC538 LG_B2 4 4
1U_0402_10V
9
PC539
2
680P_0402_50V7K
1
U42@ U42@
3
1
2
U42_EMC@
3
1
2
PQ410 PQ411
TPCA8057-H TPCA8057-H
CSN2 [70]
20170922
A CSP2 [70] A
Issued Date 2013/08/05 Deciphered Date 2014/12/31 +VCC_CORE

Size
Document Number
Number Rev
Rev
Custom 2.0
Date:
Sheet 87 of 99
5 4 3 2 1
5 4 3 2 1
D D
PL401
BLM18KG300TN1D
EMC@ EMC@ RF_NS@ 1 2
B+
EMC@
PC432 PC433 PC434 PC435 PC436 PC437 PL402
BLM18KG300TN1D
33U_D2_25VM_R40M
33U_D2_25VM_R40M
33U_D2_25VM_R40M
47P_0402_50V8-J
1
1
1
1
1
1
1
2200P_0402_25V7-K
1 2
10U_0805_25V6-K
10U_0805_25V6-K
10U_0805_25V6-K
10U_0805_25V6-K
PC438
0.1U_0402_25V6
1 1 1
EMC@ + + +
PC528
PC529
PC527
2
2
2
2
2
2
2
2.2_0603_1%
2 2 2 +VCC_GT
5
PR449
2 1 @ @ @
C
TDC= 18A C
2
PC442
0.22U_0603_25V7-K IccMAX=31A
PU402 HG_A1 4 PQ401
OCP min = 40A
1
NCP81253MNTBG_DFN8_2X2 TPCA8065-H
1 8 PL403
BST DRVH 0.15UH_CMLE064T-R15MS0R725-88_35A_20%
3
2
1
2 7 SW_A1 1 4
[70] PWM_1A PWM SW
+VCC_GT
2
5
3 6 2 3
[70,72,73] DRVON EN GND PR450 1
4 5
FLAG
4.7_0603_5%
+5VALW VCC DRVL + PC443
EMC@ 330U_D2_2VM_R9M
1 1
1
PC444 LG_A1 4 4
2
9
1U_0402_10V
PC445
2
680P_0402_50V7K
2
3
2
1
3
2
1
PQ402 PQ403 EMC@
TPCA8057-H TPCA8057-H
CSN_1A [70]
B 20170922 SW_1A [70] B
Vinafix.com
A A
Issued Date 2013/08/05 Deciphered Date 2014/12/31 +VCC_GT

Size
Size Document
Number Rev
Rev
Custom 2.0
Date:
Sheet 88 of 99
5 4 3 2 1
5 4 3 2 1
D D
PL407
BLM18KG300TN1D
EMC@EMC@ RF_NS@ 1 2
B+
PC457 PC458 PC459 PC460 EMC@
47P_0402_50V8-J
1
1
2200P_0402_25V7-K
10U_0805_25V6-K
10U_0805_25V6-K
PC461
0.1U_0402_25V6
2
2
2
2
2
2.2_0603_1%
5
PR457
2 1
+VCC_SA
2
PC462
0.22U_0603_25V7-K
PU404 HG_1PH4 PQ407 TDC= 4A
1
C NCP81253MNTBG_DFN8_2X2 AON7408L C
IccMAX=6A
1 8 PL408
BST DRVH 0.47UH_PCMB063T-R47MS3R675_18A_20% OCP = 9A
3
2
1
2 7 SW_1PH 1 4
[70] PWM_1B PWM SW
+VCC_SA
5
3 6 2 3
[70,71,72] DRVON EN GND
4 5
FLAG
+5VALW VCC DRVL
2
PR458
1
PC463 LG_1PH 4 PQ408 4.7_0603_5%

9
1U_0402_10V AON7408L
EMC_NS@
2
1 1
3
2
1
PC464
680P_0402_50V7K
2
CSB_1B [70]
B
EMC_NS@ B
SW_1B [70]
Vinafix.com
A A
Issued Date 2013/08/05 Deciphered Date 2014/12/31 +VCC_SA

Size
Size Document
Number Rev
Rev
Custom 2.0
Date:
Sheet 89 of 99
5 4 3 2 1
5 4 3 2 1
+VCC_CORE
+VCC_CORE
5pcs 22uF for +VCC_CORE
D D
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
2 2 2 2 2 2
@ PC543
@ PC470
PC473
PC477
@ PC469
@ PC472
2 2 2 2 2 2 2
@ PC482
PC486
@ PC484
@ PC481
PC485
@ PC483
PC487
1 1 1 1 1 1
1 1 1 1 1 1 1
5pcs 22uF for +VCC_GT

+VCC_GT +VCC_GT
C C
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
2 2 2 2 2 2 2 2 2 2 2 2 2
@ PC488
PC491
@ PC492
PC493
@ PC508
@ PC495
@ PC503
@ PC512
PC502
PC504
PC494
@ PC496
@ PC509
1 1 1 1 1 1 1 1 1 1 1 1 1
B B
Vinafix.com
+VCC_SA 6pcs 22uF for +VCCSA
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
2 2 2 2 2 2
PC515
PC524
PC520
PC513
PC514
PC523
1 1 1 1 1 1
A A
Issued Date 2013/08/05 Deciphered Date 2014/12/31

PROCESSOR DECOUPLING
Size
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document
Document Number
Number Rev
Rev
B 2.0
Date:
Sheet 90 of 99
5 4 3 2 1
5 4 3 2 1
DIS_EMC@
PL601
BLM18KG300TN1D_2P
1 2
PL602
DIS_RF_NS@ DIS_EMC@ DIS_EMC@ DIS@ DIS@ BLM18KG300TN1D_2P
VIN_+VDDC_1 1 2
B+
DIS_EMC@
2200P_0402_25V7-K
PRE-PWROK METAL VID CODES
47P_0402_50V8-J
10U_0805_25V6-K
10U_0805_25V6-K
0.1U_0402_25V6
1
1
1
1
1
SVC SVD Boot Voltage
PC602
PC605
PC606
PC604
PC603
DIS@
DIS@ PQ602
0 0 1.1V PQ601 AON7380
2 +VDDC
2
2
2
2
5
5
AON7380
0 1 1.0V
1 0 0.9V(Default) VDDC_UGATE1 4 4 TDC=30A
EDC=60A
1 1 0.8V OCP=78A
1
2
3
1
2
3
20170905 DIS@ PL603
D @ PR602 0.24UH_PCME063T-R24MS1R145_35A_20% DIS@ DIS@ DIS@ DIS_EMC@ D
0_0201_5%_SM VDDC_PHASE1 1 4 +VDDC
1 2
28 GPU_VSSC_SENSE
DIS@ PR604 2 3
330U_D2_2VM_R9M
330U_D2_2VM_R9M
0.1U_0402_10V6K
DIS@ DIS@ DIS_EMC_NS@ 1 1
2
2.2_0603_5%
22U_0603_6.3V6-M
PQ603 PQ604
2
1
20170905 VDDC_BOOT11 2 1 2 + +
PC608
PC612
PR605
PC609
PC611
AON7508
5
AON7508
5
2 1
0_0201_5%_SM
@ PR667 4.7_0603_5%
0_0201_5%_SM
1
1
DIS@ PC614 0_0402_5%_SM DIS@ PC607
PC613 2
1
VR_VGA_PWRGD 37 2
2
DIS@ PR603 68P_0201_25V8-J 0.1U_0603_25V7-M
PR662
DIS@ 1 2
PR661
1
100_0201_5% 1 2 1 2 VDDC_LGATE1 4 4
+VDDC 2 1 DIS_EMC_NS@
2
330P_0201_25V7-K @ @
1
2
3
2
1
2
3
2
DIS@ PR606 DIS@ PR609 PC615
100_0201_5% 78.7K_0201_1% 680P_0402_50V7K 20170905
1
28 GPU_VDDC_SENSE 1 2 1 2 1 2
DIS@ PR610
@ PR607 DIS@ PR608 10K_0201_1%
0_0201_5%_SM
@
PC616
10K_0201_1% 1 2
+3VALW
20170905 1 2 2 1
1
@ PR611
3662_VREF 330P_0201_25V7-K
0_0201_5%_SM
DIS@
PC617 DIS@ PR612
0.1U_0201_25V6-K 1.18K_0201_1%
2
20170905 VDDC_ISEN1P 1 2
1
+3VS_VGA
VDDC_ISEN1N
VDDC_ISEN1P
VDDC_ISEN2P
1
@ PR613
3662_PGOOD
DIS@
VDDC_COMP
VDDC_VSEN
3662_RGND
402_0402_1% PC618
VDDC_FB
VDDC_BOOT2 0.47U_0201_25V6-K
2
DIS@ DIS@
2
1
1
DIS@ VDDC_UGATE2
2
PR614 PR615 PR616 VDDC_ISEN1N 1 2
1
105K_0201_1% 316K_0201_1% DIS@ DIS@
64.9K_0201_1% PR601 PC601 DIS@ PR618
10
PR617
1
7
2
8
4.7K_0201_5% 0.1U_0201_25V6-K 1_0201_1% 1.18K_0201_1%
2
1
2
DIS@ VDDC_ISEN2P 1 2
ISEN1P
FB
ISEN1N
COMP
RGND
ISEN2P
UGATE2
PGOOD
BOOT2
VSEN
DIS@
1
20170905 PC619
@ PR619 40 VDDC_PHASE2 0.1U_0201_25V6-K
PHASE2
2
0_0201_5%_SM DIS_EMC@
DIS@ DIS@ GPU_VR_HOT# 1 2 11 39 VDDC_LGATE2
26 GPU_VR_HOT# VRHOT_L LGATE2
1
PL604
PR620 PR621 VDDC_TSEN 12 38 VDDC_BOOT1 BLM18KG300TN1D_2P
3.01K_0201_1% TSEN BOOT1 1 2
1.65K_0201_1%
@ PR668 3662_SET1 13 37 VDDC_UGATE1
SET1 UGATE1
0_0201_5% PL605
2
14 PU601 36 BLM18KG300TN1D_2P
<37> VDDC_IMON_PCC 1 2 VDDC_IMON IMON PHASE1 VDDC_PHASE1
20170905
DIS_RF_NS@ DIS_EMC@DIS_EMC@ DIS@ DIS@
1 2
20170905 3662_VREF 15
RT3662ACGQW_WQFN40_5X5
35 VDDC_LGATE1
VIN_+VDDC_2 B+
VREF_PINSET LGATE1
@ PR622 0_0402_5%_SM DIS_EMC@
2200P_0402_25V7-K
VDDCI_IMON 16
IMON_NB PVCC
34 3662_PVCC 1 2 +5VALW
10U_0805_25V6-K
10U_0805_25V6-K
47P_0402_50V8-J
0.1U_0402_25V6
3662_SET1 24 PLT_RST_VGA# PLT_RST_VGA# 1 2 GPU_POK_R18 PWROK VCC
17 3662_VCC 1 2 1
1
1
1
PC624
PC621
PC622
@ PR623 0_0201_5%_SM
1
PC620
PC623
DIS@ PR626 61.9K_0201_1%
26 GPU_SVC 1 2 GPU_SVC_R19 SVC LGATE_NB
33 VDDCI_LGATE PR624
1 2 @ PR625 0_0402_5%_SM 4.7_0402_1%
VDDC_TSEN
2
2
GPU_SVD_R20 32
2
C 26 GPU_SVD 1 2 VDDCI_PHASE C
SVD PHASE_NB DIS@ PQ605
2
@ PR627 0_0402_5%_SM PQ606
5
AON7380
5
PRT601 26 GPU_SVT 1 2 GPU_SVT_R 21 31 VDDCI_UGATE PC625 PC626 AON7380
SVT UGATE_NB
ISENN_NB
DIS@
ISENP_NB
COMP_NB
@ PR628 0_0402_5%_SM
BOOT_NB
TSEN_NB
2.2U_0402_10V6-K 2.2U_0402_10V6-K
1
1 2 DIS@ DIS@
FB_NB
VDDIO
20170905 VDDC_UGATE2 4 4
GND
VIN
EN
100K_0402_1%_NCP15WF104F03RC
3
2
3
2
1 2 VDDCI_TSEN
22
23
24
25
26
27
28
29
30
41
DIS@ DIS@
DIS@ PR629 61.9K_0201_1%
1
DIS@ PRT602 DIS@ PL606

PR630 DIS@ 0.24UH_PCME063T-R24MS1R145_35A_20% DIS@ DIS_EMC@
32.4K_0201_1% DIS@ DIS@ DIS@ DIS@ DIS@
3662_VDDIO
1 2 +VDDC
VDDCI_COMP
PR631 1 4
VDDCI_BOOT
VDDC_PHASE2
VDDCI_TSEN
VDDCI_ISEN1N
VDDCI_EN_1
VDDCI_ISEN1P
23.7K_0201_1%
VDDCI_FB
470U_D2_2VM_R4.5M
1
330U_D2_2VM_R9M
0.1U_0402_10V6K
3662_VIN
PR633 DIS_EMC_NS@ 2 3
330U_D2_2VM_R9M
PR632 1 1
2
100K_0402_1%_NCP15WF104F03RC
2
2
PQ607 PQ608
22U_0603_6.3V6-M
22U_0603_6.3V6-M
2.2_0603_5% +
2
1
+VDDIO_GPU
PC630
1
1 2 21 2 AON7508 AON7508 PR634 +
PC633
PC631
+
PC610
PC632
VDDC_BOOT2 1
PC628
1
20170905
5
1
4.7_0603_5%
1
DIS@ DIS@
PR635 DIS@ PR637 2.2_0201_5% @ PR666 PC627
DIS@ 0.1U_0603_25V7-M 2
1
2
2
2
18.2K_0201_1% PR636 280_0201_1% DIS@ DIS@ 0_0402_5%_SM 2 @
VDDCI_EN
2 1
PC634 2 1 4
0_0201_5%_SM
1.15K_0402_1% 4 DIS_EMC_NS@
0_0201_5%_SM
34 VDDC_LGATE2 DIS@
1
1U_0201_6.3V6-K
1
2
2
PC635
2
PR664
PR663
1
2
3
3
2
680P_0402_50V7K
1
DIS@ DIS@
1 2
VIN_+VDDC_1 @ @
2
2
DIS@ PR638
4.7_0402_1%
1
20170905
DIS@ PC638 DIS@ PC636
PC637 0.1U_0201_25V6-K
DIS@ PR639 DIS@ 68P_0201_25V8-J
2
100_0201_5% 1 2 1 2
+VDDCI 2 1
330P_0201_25V7-K
PR642
DIS@ PR643
49.9K_0201_1%
1.18K_0201_1%
28 GPU_VDDCI_SENSE @1 2 1 2 1 2
VDDCI_FB_R VDDC_ISEN2P 1 2
PR640 0_0201_5%_SM
DIS@ PR641 DIS@
20170905
1
10K_0201_1%
3662_VREF
1
3662_VREF DIS@
DIS@ PR645 @ PR644 PC639
10K_0201_1% 402_0402_1% 0.47U_0201_25V6-K
1
2
1 2 @
PC640
1
DIS@
2
PR646 DIS@ PR648 DIS@ PR649 330P_0201_25V7-K 1 2
PRT603 VDDC_ISEN1N
2
3.9_0201_1% DIS@ 16.9K_0201_1% 604_0402_1%

1 2 1 2 1 2 @1 2 VDDC_IMON DIS@ PR647 DIS@ PR651
PR650 0_0201_5%_SM 1_0201_1% 1.18K_0201_1%
2
1 2
100K_0402_1%_NCP15WF104F03RC 20170905 VDDC_ISEN1P
1
DIS@ DIS@ PR652

PC642 24.9K_0201_1%
0.47U_0201_25V6-K 1 2
2
PRT604
DIS@ PR654 PR655
1 2
1 2 1 2 1 2 VDDCI_IMON DIS_EMC@
B B
100K_0402_1%_NCP15WF104F03RC PL607
PR653 40.2K_0201_1% 1.4K_0201_1%
Vinafix.com BLM18KG300TN1D_2P
1.69K_0201_1% DIS@ DIS@ 1 2
DIS@
PL608
DIS_RF_NS@ DIS_EMC@ DIS@ DIS@ BLM18KG300TN1D_2P
DIS_EMC@
VIN_+VDDCI
1 2 B+
DIS_EMC@
2200P_0402_25V7-K
10U_0805_25V6-K
10U_0805_25V6-K
47P_0402_50V8-J
0.1U_0402_25V6
1
1
PC647
1
PC646
PC649
1
PC643
PC644
5
2
2
2
2
2
4
+VDDCI
VDDCI_UGATE
PQ609
AON7408L
TDC=5A
DIS@ EDC=7.5A
2
1
3
PL609 OCP=10A
0.36UH_PDME064TR36MS1_24A_20% DIS@ DIS_EMC@
DIS@ @ DIS@
VDDCI_PHASE
1 4
+VDDCI +VDDCI
DIS_EMC_NS@ 2 3
0.1U_0402_10V6K
DIS@ PR657
330U_D2_2VM_R9M
330U_D2_2VM_R9M
2
1 1
5
2.2_0603_5%
22U_0603_6.3V6-M
22U_0603_6.3V6-M
2
1 2 PR658
PC655
1
1 2 + +
PC653
DIS@
PC652
PC654
PC651
VDDCI_BOOT 4.7_0603_5%
DIS@ PC650
1
0.1U_0603_25V7-M
2
2 2
2
1
VDDCI_LGATE 4 PQ610
AON7408L
DIS@ DIS_EMC_NS@
2
PC656
3
2
1
680P_0402_50V7K
1
DIS@
PR659
1.5K_0201_1%
VDDCI_ISEN1P 1 2
1
DIS@
1
PR660
DIS@
PC657
1.5K_0201_1% 0.47U_0201_25V6-K
2
2
VDDCI_ISEN1N
A A
1
DIS@
PC658
0.1U_0201_25V6-K
2
<Variant Name>

Issued Date 2013/08/15 Deciphered Date 2013/08/15 VDDC/VDDCI
Size
DocumentNumber
Number Rev
Rev
Date:
Sheet 91 of 99
5 4 3 2 1
5 4 3 2 1
+1VALW
D
FSW=700KHz D
TDC:6.5A
NB691_VCC OCP:7.2A
NB691_VCC
PJ702
2 1
2 1
@ PR703 @ JUMP_43X118
2
PC713 0_0402_5%_SM
1U_0402_10V6-K 1 2 PJ703
2 1
+1VALWP 2 1 +1VALW
1
20170905
@ JUMP_43X118
1
+1VALWP_BST
PJ701 EMC@ EMC@ RF_NS@ PC702
2 1 0.22U_0402_25V6-K
B+ 2 1
2
8
7
@ JUMP_43X79 PU702 PL701
2200P_0402_25V7-K
0.68UH_PCMC063T-R68MN_15.5A_20%
10U_0805_25V6-K
10U_0805_25V6-K
VCC
BST
C C
47P_0402_50V8-J
0.1U_0402_25V6-K
1 EMC@ EMC@
1
1
PC703
PC701
6 +1VALWP_SW 1 2
PC704
+1VALWP
PC705
1 SW
PC719
VIN
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
2
2
2
2
2200P_0402_25V7-K
10 +1VALWP_FB PC712
0.1U_0402_25V6-K
11 FB PR711 220P_0201_25V7-K
PC711
EN
1
1
1
1
1
1 2
PC715
PC710
PC708
PC716
PC709
4.7_0603_5%
EMC_NS@
2
2
2
1
2
1
5 9
@ PR701 PG AGND @
PGND1
PGND2
PGND3
0_0402_5%_SM PR707
1 2 0_0402_5%_SM
52,56,83 EC_ON2
1
EMC_NS@
2
1
20170905 NB691GG-Z_QFN11_2X2 PR708 20170905
4
1
PC677 PC718 499_0201_1%
1
0.1U_0402_16V7-K 680P_0402_50V7K
PR704
2
PR709
2
2
NB691_VCC 1 2 40.2K_0201_1%
NB691_VCC
100K_0201_1%
2
B B
1
PR710
60.4K_0402_1%
2
A
Vinafix.com A

Issued Date 2013/08/05 Deciphered Date 2014/12/31 +1V
Size
Size Document
Number Rev
Rev
Custom 0.1
0.1
Date:
Date: Monday,
Monday, October
October 30,
30, 2017
2017 Sheet
Sheet 92
92 of 99
99
5 4 3 2 1
5 4 3 2 1
D
+1.8VALW D
TDC: 2A
OCP: 4A
Fsw: 1MHz
@ PJ802
PL801 JUMP_43X39
4
PJ801 1UH_PH041H-1R0MS_20%
2 1 VIN_+1.8VSP 10 1 1.8VSP_LX 1 2 +1.8VSP 2 1 +1.8VALW
+5VALW
PG
2 1 PVIN2 LX1 2 1
2
9 2
@ JUMP_43X39 PVIN1 LX2
1
PR803
1
PC801 PC802 8 3 4.7_0603_5%
C
10U_0603_10V 10U_0603_10V SVIN1 LX3 EMC_NS@ PR804 PC805
C
EMC@ EMC@
2
2
PU801 20K_0402_1% 22P_0402_50V
2
2 1
2200P_0402_25V7-K
RT8068AZQW
22U_0805_6.3VAM
22U_0805_6.3VAM
0.1U_0402_25V6
2
1
1
1
20170905 5 6 PC804
PC842
GND
EN FB
PC806
PC807
PC808
NC
[57,76] EC_ON2 @ PR801 0_0402_5%_SM EMC_NS@ 680P_0402_50V
2
1
2
1 2EN_1.8VSP
7
11
2
1 2
1
@ PR802 @ PC803
@ PD801 1M_0402_5% 0.22U_0402_10V6-K
2
CUS357_SOD323-2 PR805
1
10K_0402_1%
B B
2
A Vinafix.com Security Classification LC Future Center Secret Data Title A
Issued Date 2013/08/05 Deciphered Date 2014/12/31 +1.8VALW

Size Document
Number Rev
Rev
Custom 2.0
Sheet 93 of 99
5 4 3 2 1
5 4 3 2 1
D D
+2.5V
TDC: 2A
OCP: 4A
Fsw: 1MHz
@ PJ804
@ PJ803 PL802 JUMP_43X39
4
JUMP_43X39 1UH_PH041H-1R0MS_20%
2 1 VIN_+2.5VSP 10 1 2.5VSP_LX 1 2 +2.5VSP 2 1 +2.5V
+5VALW
PG
2 1 PVIN2 LX1 2 1
2
9 2
PVIN1 LX2
1
PR808
1
PC809 PC810 8 3 4.7_0603_5%
C
SVIN1 LX3 EMC_NS@ C
1
10U_0603_10V 10U_0603_10V
EMC@ EMC@
2
PU802 PR809 PC813
2 1
2200P_0402_25V7-K
RT8068AZQW 31.6K_0402_1% 22P_0402_50V
22U_0805_6.3VAM
22U_0805_6.3VAM
0.1U_0402_25V6
2
1
1
20170901 5 6 PC812
GND
EN FB
2
@
PC814
PC816
PC843
PC815
NC
PR806 0_0402_5%_SM EMC_NS@ 680P_0402_50V
2
2
1 2 EN_2.5VSP
[50,57,69] SYSON
11
7
2
1
@ PR807 @ PC811
1M_0402_5% 0.22U_0402_10V6-K
2
PR810
1
10K_0402_1%
B B
2
A Vinafix.com Security Classification LC Future Center Secret Data Title A
Issued Date 2013/08/05 Deciphered Date 2014/12/31 +2.5V

Size Document
Number Rev
Rev
Custom 2.0
Sheet 94 of 99
5 4 3 2 1
5 4 3 2 1
D D
+1.35VS_VGA +1.35VS_VGA
TDC: 8A
OCP: 13A
Fsw: 700KHz
1
@ PJ602
1
JUMP_43X118
2
1
DIS@ DIS@
2
PR671 PL610
150K_0201_5% 20170905 0.68UH_PCMC063T-R68MN_15.5A_20% DIS_EMC@ DIS_EMC@
1 2 +1.35VSP
@ PR670
2
0_0402_5%_SM
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
22U_0603_6.3V6-M
2
1 2
2200P_0402_25V7-K
0.1U_0402_25V6-K
PR672
DIS@ PC663
DIS@ PC667
DIS@ PC666
DIS@ PC662
DIS@ PC664
DIS@ PC665
PC669
1
1
1
1
1
1
1
+1.35VSP_BST 4.7_0603_5%
PC668
2
2
DIS@ DIS_EMC_NS@ DIS@
11
10
10_0201_1%
PC660 PC661
2
1
2
2
2
2
220P_0201_25V7-K
PR673
DIS@
0.22U_0402_25V6-K
CLM
BST
1
C PJ601 DIS_EMC@DIS_EMC@ C
DIS_RF_NS@
1
2 1 +1.35VSP_VIN 1 9 +1.35VSP_SW PC670
B+ 2 1 VIN SW 680P_0402_50V7K
1
@ JUMP_43X79 DIS@ PR811 DIS_EMC_NS@
2
10K_0402_1%
2200P_0402_25V7-K
10U_0805_25V6-K
10U_0805_25V6-K
0.1U_0402_25V6-K
1
1 2 +1.35VSP_EN 15 DIS@
47P_0402_50V8-J
1 EN
1
1
1
1
DIS@ PC818
DIS@ PC819
PR675
PC844
PC674
DIS@ DIS@ 13 499_0201_1%

PC845
FB
1
PC817 PU602 DIS@
2
2
2
2
2
0.1U_0402_16V7-K PR677
2
NB693GQ-Z_QFN16_3X3 100K_0201_1%
2
12 2 1
PG +3VALW
1
20170905 DIS@
@ PR679 1 2 +1.35VSP_PWRGD PR678
0_0201_5%_SM 12.4K_0201_1%
1 2 14 16 +1.35VSP_VIN @ PR812
52,56,83 FB_PWR_EN MODE NC2
2
0_0402_5%_SM
20170905
DIS@ PR680 1 2 5.1_0402_5% 3 8 +1.35VSP_SW
+3VALW 3V3 NC1
1
DIS@
PGND5
PGND2
PGND1
PGND4
PGND3
PR681
10K_0402_1%
1
DIS@ PC676
1U_0402_10V6-K
2
7
2
6
5
Pin 8 and Pin16
2
B B
follow MPS suggestion
A
Vinafix.com Security Classification
LC Future Center Secret Data
Deciphered Date 2014/12/31
Title
+1.35VS_VGA
A
Size
Size Document
Size
Document Number
Number Rev
Rev
Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
Custom 2.0
2.0
Date:
Date:
Date: Monday,
Monday, October
October 30,
30, 2017
2017 Sheet
Sheet
Sheet 95
95 of 99
99
5 4 3 2 1
5 4 3 2 1
D D
+VL/ 100mA
Richtek Richtek
LV6228C RT8068A
PWM +5VALW/8A
FOR 1.8VALW
1.8VALW/2A
FOR SYSTEM EC_ON2 EN

EC_ON EN PGOOD +VL_3.3V
+3VLP/ 100mA Richtek

Power Path TI SILERGY RT8068A
BQ25700A SYX198BQNC 2.5V/2A
NX20P5090UK B+ PWM
FOR 2.5V
+3VALW/8A SYSON EN
Battery Charger FOR SYSTEM
EC_ON EN PGOOD +3V_PWRGD
Buck-Boost
Richtek +1.2V/8A
RT8231A
C C
FOR DDR4 +0.6V/1.5A

TYPE-C PD SMBus SYSON S5
SM_PG_CTRL S3 PGOOD
For U42
ON NCP81151
VCORE/TDC 42A/EDC 64A
Batt. MOSFET NCP81218 NCP81151
VR_ON EN
For KBL CPU
NCP81253 VCCGT/TDC 18A/EDC 31A
NCP81253 VCCSA/TDC 4A/EDC 6A
B B
Vinafix.com Battery
VGA_PWM_VID
VDDCI_EN
VIDs
EN
Richtek
RT3662AC
For AMD R17M GPU
PGOOD
+VDDC TDC 30A /EDC 60A
+VDDCI TDC 5A /EDC 7.5A
MPS +1VALWP/6.5A
NB691
FOR +1VALWP
EC_ON2 EN
MPS FOR VRAM /8A

NB693
A
VRAM GDDR5 1.35V A
FB_PWR_EN EN

Issued Date Deciphered Date Power Block Diagram
Custom 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EE480 NM-B421
5 4 3 2 1
5 4 3 2 1
D D
PRTC2
BATT CR2032 3V 210MAH
RTC@
EE480
C C
B
Vinafix.com B
A A
Title
<Title>
Size Document Number Rev

A <Doc> <RevCode>

5 4 3 2 1
5 4 3 2 1
D D
C C
BLANK
B
Vinafix.com B
A A

Issued Date 2015/09/01 Deciphered Date 2016/12/31 XXXX
Size
Size Document
Number Rev
Rev
Custom 2.0
2.0
Date:
Date: Monday,
Monday, October
October 30,
30, 2017
2017 Sheet
Sheet 98
98 of 99
99
5 4 3 2 1
5 4 3 2 1
B+ B+ <47,60,72,80,83,84,85,86,87,88,89,91,92,95>
+VCCCORE_GT2 +VCCCORE_GT2 <17,27>
+VCCCORE_GT1 +VCCCORE_GT1 <17,27>
+5VALW +5VALW <38,39,42,43,47,64,66,67,71,72,84,85,86,87,88,89,91,93,94> +VCC_SFROC +VCC_SFROC <18>
+5VS +5VS <47,50,51,60,61,65,66,72> +VCC_SFR +VCC_SFR <18>
+VCC_DSW3P3 +VCC_DSW3P3 <19>
D D
+3V_SPI +3V_SPI <9,19>
+VCC_CORE +VCC_CORE <16,17,27,87,90>
+3VALW_RTCPRIM +3VALW_RTCPRIM <19>
+1.2V +1.2V <6,7,18,23,24,25,26,85>
+3VL_AVCC +3VL_AVCC <40>
+3VL_EC +3VL_EC <40>
+0.6VS +0.6VS <23,24,25,26,85> +VCON_IN +VCON_IN <42,43>
+VCC_GT +VCC_GT <17,27,88,90>

+5V_IN +5V_IN <42,43>
+VCC_SA +VCC_SA <18,89,90>
+VDDCI +VDDCI <34,91>

+LDO_3V3 +LDO_3V3 <42,43>
+VDDC +VDDC <34,91>
+1.8VALW +1.8VALW <19,38,93> +5VS_HDMI +5VS_HDMI <47>
+1.8VS_VGA +1.8VS_VGA <30,32,34,38>

+3VS_VDDO +3VS_VDDO <50>
+1.8VALW_PCH +1.8VALW_PCH <19>
+2.5V +2.5V <6,23,24,25,26,94>
+3V_LDO +3V_LDO <50>
+USB_PWR_S2 +USB_PWR_S2 <64>
+USB_PWR_S1 +USB_PWR_S1 <64> +3V_AVDD_HP +3V_AVDD_HP <50>
+3VALW +3VALW <6,9,12,15,19,40,50,58,60,63,65,66,67,72,83,84,91,95> +3VS_VDDIO +3VS_VDDIO <50>
+3VALW_PCH +3VALW_PCH <8,9,10,11,12,19>

+3VS_DVDD +3VS_DVDD <50>
C +3VALW_PRIM C
+3VALW_PRIM <15,19>
+VCC_HDA +VCC_HDA <11,19> +5VS_AVDD +5VS_AVDD <50>
+1.8V_LDO +1.8V_LDO <50>
+1.65V_LDO +1.65V_LDO <50>
+VS_TPCP +VS_TPCP <65>
+3VS +3VS <5,6,9,10,11,12,14,15,23,25,30,32,37,39,40,47,50,51,57,58,59,60,61,63,65,66,67,69,72,85,86>
+3VS_VGA +3VS_VGA <30,32,37,38,39,91>
+1VALW +1VALW <14,19,71,92>
+1VALW_PCH +1VALW_PCH <19,21>
B
Vinafix.com +VCC_IO
+VCC_ST
+VCC_STG
+1VALW_SUS
+VCC_IO
+VCC_ST
+VCC_STG
+1VALW_SUS
<5,11,18,21,71>
<8,15,16,18,21,71,86>
<8,16,18,71>
<19>
B
+VCC_MPHYGT +VCC_MPHYGT <19>
+1VALW_1P0 +1VALW_1P0 <19>
+VCC_SRAM +VCC_SRAM <19>
+1.35VS_VGA +1.35VS_VGA <31,34,36,95> +VCC_PLLEBB +VCC_PLLEBB <19>
+3VL +3VL <19,40,42,50,67,72,80,82,83,84>
+RTCBATT +RTCBATT <14,66,80>
A A
+RTCVCC +RTCVCC <14,15,19>
+VBUS_CONN +VBUS_CONN <42,43>

Issued Date 2013/11/08 Deciphered Date 2013/11/08 LOAD BOM ONLY
Size
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
5 4 3 2 1
A B C D E
1
LCFC Confidential 1
Dooku
2
E480 2
NS-B421 Rev1.0 Schematic

Intel KBL-R Processor with DDR4
Vinafix.com
3 AMD R17M-P1-50/70 3
2017-09-27 Rev1.0
4 4

Issued Date 2017/03/17 Deciphered Date 2017/12/31 COVER PAGE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. E480_NS-B421
Date: Wednesday, September 27, 2017 Sheet 1 of 7
A B C D E
A B C D E
IO_Board
1 1
power botton
PWRBT
Giga LAN PCIe x 1

RJ45 Conn. MDI
2 Page 5 Realtek 2
R8111GUS
Card Reader PCIe x 1

Micro SD Conn. Secure Digital
Page 6 Bayhub
OZ711LV1LN
3
JUSB3 (USB2.0)
Page 3
Vinafix.com USB 2.0 x 1
3
4 4

Issued Date 2017/03/17 Deciphered Date 2017/12/31 BLOCK DIAGRAM
Custom 1.0
Date: Wednesday, September 27, 2017Sheet 2 of 7
A B C D E
5 4 3 2 1
+3VALW +3VALW 4
+3VS +3VS 4,6

PWRBTN IO_40_Pin conn +3VL +3VS +5VALW +3VALW
+5VALW
JIOB2 ME@
1
1
1
@ 2
R0303 3 2
300_0402_5% 4 3
5 4
6 5
LED1 R0301 6
2
100_0402_5% 7
1 2 PWRBTN_LED 1 2 8 7
D 9 8 D
10 9
LTW-C191UC5_WHITE D 10
1
PLT_RST# 11
SC50000GN00 PWRBTN_LED# 4,6 PLT_RST# LAN_WAKE# 11
2 12
4 LAN_WAKE# CLKREQ_PCIE3_LAN# 12
G 13
4 CLKREQ_PCIE3_LAN# CLKREQ_PCIE5_CR# 13
S Q0301 14
6 CLKREQ_PCIE5_CR# 14
1
2N7002WT1G_1N_SC-70-3 PWRBTN_LED# 15
1 15
SB000019400 R0302 ON/OFF# 16
@ 100K_0402_5% C6507 USB_ON# 17 16
100P_0402_50V8J USB_OC3# 18 17
@ 2 EMC_NS@ LID_SW# 19 18
19
2
20
USB20_P4 21 20
USB2.0 USB20_N4 22
23
21
22
4 PCIE5_CRX_DTX_N PCIE5_CRX_DTX_P 24
25
4 PCIE5_CRX_DTX_P 25
SW1 26
PCIE5_CTX_C_DRX_N 27 26
Power Button SW_NTC017-DA1J-D160T_4P
EVQPLDA15 SPST PANAS H1.5 4P
GBE LAN PHY 4
4
PCIE5_CTX_C_DRX_N
PCIE5_CTX_C_DRX_P
29
27
28
1 2 CLK_PCIE_LAN 30 29
4 CLK_PCIE_LAN CLK_PCIE_LAN# 30
31
4 CLK_PCIE_LAN# 31
3 4 32
G
G
6 PCIE12_CRX_DTX_N PCIE12_CRX_DTX_P 33
34
6 PCIE12_CRX_DTX_P 34
6
5
35
JSW1
SHORT PADS
Card Reader 6 PCIE12_CTX_C_DRX_N
PCIE12_CTX_C_DRX_N
PCIE12_CTX_C_DRX_P
36
37
35
36
6 PCIE12_CTX_C_DRX_P 37
Bottom Side @ 38
1 2 ON/OFF# CLK_PCIE_CR# 39 38 41
6 CLK_PCIE_CR# CLK_PCIE_CR 39 GND1
40 42
C 6 CLK_PCIE_CR 40 GND2 C
PU +3VL at EC side.
I-PEX_20374-040E-31
3
D0302
PESD5V0U2BT_SOT23-3
EMC@
1
JUSB4(USB2.0)
+5VALW +USB_VCCA
W=80mils U0302 W=80mils

Lid Switch 1
C0305
5
IN OUT
GND
1
2 +USB_VCCA
0.1U_0402_10V6-K USB_ON# 4 3 USB_OC3#

2 ENB OCB
Vinafix.com SY6288D20AAC_SOT23-5 1
SA000074Q00 1
+
C0301 C0302
150U_B2_6.3VM_R35M 470P_0402_50V7-K
2 2
B B
SILERGY SA000074Q00 S IC SY6288D20AAC SOT23 5P POWER SWITCH
GMT SA000079400 S IC G517F2T11U SOT-23 5P POWER SWITCH
+3VL
+USB_VCCA
L0301
U0301 USB20_N4 1 2 USB20_N4_CON JUSB4
2 1 2 1
1 VCC VBUS
3 LID_SW# USB20_N4_CON 2
C0303 1 VOUT USB20_P4 4 3 USB20_P4_CON USB20_P4_CON 3 D-
0.1U_0402_10V7-K GND 4 3 4 D+
2@ 1 GND1
TCS40DLR_SOT23-3 EXC24CH900U_4P 5
C0304 EMC@ 6 GND2
0.1U_0402_10V7-K 7 GND3
2 EMC_NS@ D0301 8 GND4
1 6 GND5
ALLTO_C147M7-10435-L
+USB_VCCA
ME@
2 5
USB20_P4_CON 3 4 USB20_N4_CON
A A
CM1293A-04SO_SC-74-6
EMC@

Issued Date 2017/03/17 Deciphered Date 2017/12/31 PBTN/FAN CONN.
Custom 1.0
5 4 3 2 1
5 4 3 2 1
+3VALW +3VALW 3
+3VS
+3VALW TO +3VALW_LAN
+3VS 3,6
+3VALW_LAN rising time (10%~90%):
0.5ms＜spec＜ 100m s
+3VALW +3VALW_LAN
+3VALW_LAN +3VS
R0402
0_0805_SM
width : 40 mils
1
1 2
2
R0404
G
D D
@ 10K_0402_5%
@
2
LAN_CLKREQ#_R 1 3
1 1 1 1 CLKREQ_PCIE3_LAN# 3
S
C0402 C0403 C0404 C0405 Q0401
4.7U_0603_6.3V6-K 4.7U_0603_6.3V6-K 0.1U_0402_10V7-K 0.1U_0402_10V7-K 2N7002KW_SOT323-3
2@ 2@ 2 2 @
R0405 1 2 0_0402_SM
@
Close to Pin11 Close to Pin32 Close to Pin11 Close to Pin32
+3VALW_LAN
1
R0407 CL10 close to Pin18
10K_0402_5% UL0401
@ CL9 close to Pin17
@ +3VALW_LAN 11 3 +LAN_VDD10
AVDD33_1 AVDD10_1
2
+3VALW_LAN 32 8 +LAN_VDD10
R0408 1 2 0_0402_SM LAN_WAKE#_R AVDD33_2 AVDD10_2 30 +LAN_VDD10
3 LAN_WAKE# PCIE5_CRX_DTX_P C0409 PCIE5_CRX_C_DTX_P 17 AVDD10_3 +LAN_VDD10
1 2 0.1U_0402_10V7-K 22
3 PCIE5_CRX_DTX_P PCIE5_CRX_DTX_N C0410 1 2 0.1U_0402_10V7-K PCIE5_CRX_C_DTX_N 18 HSOP DVDD10
3 PCIE5_CRX_DTX_N HSON 1 MDI_0+
C C
PLT_RST# 19 MDIP0 2 MDI_0- MDI_0+ 5
3,6 PLT_RST# PERSTB MDIN0 MDI_0- 5
4 MDI_1+
ISOLATE# 20 MDIP1 5 MDI_1- MDI_1+ 5
LAN_WAKE#_R 21 ISOLATEB MDIN1 MDI_1- 5
+3VS +3VALW_LAN LANWAKEB 6 MDI_2+
+LAN_VDDREG 23 MDIP2 7 MDI_2- MDI_2+ 5
+LAN_REGOUT 24 VDDREG MDIN2 MDI_2- 5
REGOUT MDI_3+
1
9
RJ45_LINKUP# 25 MDIP3 10 MDI_3- MDI_3+ 5
R0409 R0412
5 RJ45_LINKUP# LED1 26 LED2 MDIN3 MDI_3- 5
1K_0402_5% 10K_0402_5%
@ RJ45_ACTIVITY# 27 LED1/GPO 13 PCIE5_CTX_C_DRX_P
5 RJ45_ACTIVITY# LED0 HSIP 14 PCIE5_CTX_C_DRX_N PCIE5_CTX_C_DRX_P 3
HSIN PCIE5_CTX_C_DRX_N 3
2
LAN_XTALO 28 12 LAN_CLKREQ#_R
ISOLATE# LED1 CKXTAL1 CLKREQB
LAN_XTALI 29 15 CLK_PCIE_LAN
CKXTAL2 REFCLK_P 16 CLK_PCIE_LAN# CLK_PCIE_LAN 3
REFCLK_N CLK_PCIE_LAN# 3
1
R0411 TL2 1 RJ45_LINKUP# 33 31 RSET

15K_0402_5% GND RSET
1
TL3 1 LED1
RTL8111GUS-CG_QFN32_4X4 R0406
2
TL4 1 RJ45_ACTIVITY# 2.49K_0402_1%

Vinafix.com
2
B B
+3VALW_LAN +LAN_VDDREG
0_0603_SM 1 2 R0403
@ +LAN_VDD10
1 1 L0401
2.2UH_EP-22AM05B02_2A_20%
C0401 C0406 +LAN_REGOUT 1 2
4.7U_0603_6.3V6-K 0.1U_0402_10V7-K
2 2
1 1 1 1 1 1 1
Layout Note: L0401 must be C0414 C0415 C0416 C0417 C0418 C0419 C0420
4.7U_0603_6.3V6-K 0.1U_0402_10V7-K 0.1U_0402_10V7-K 0.1U_0402_10V7-K 0.1U_0402_10V7-K 0.1U_0402_10V7-K 1U_0402_10V6-K
within 200mil to Pin24, 2 2 2 2 2 2 2@
C0414,C0415 must be within
200mil to LL1
+LAN_REGOUT: Width =60mil Close to Pin3, 8, 22, 30 LAYOUT NEED CHECK Close to Pin22(Reserved)
LAN_XTALI
Y0401 LAN_XTALO
1 4
OSC1 GND2
A 2 3 A
GND1 OSC2
1 1
25MHZ_10PF_7V25000014
C0411 C0412
12P_0402_50V8-J 10P_0402_50V8-J
2 2
Change from 12PF to 10PF as
vendor suggest on 20170508 Issued Date 2017/03/17 Deciphered Date 2017/12/31 GBE LAN PHY
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 1.0
5 4 3 2 1
5 4 3 2 1
T0501
1:1 24 RJ45_TXD0P
MDI_0+ 1 T1/B MX1+
4 MDI_0+ TD1+
23 RJ45_TXD0N
MX1-
D MDI_0- 2 D
4 MDI_0- TD1- EMC@
TDCT 3 22 MCT1 R0513 2 1 75_0805_5% RJ45_GND
TCT1 T1/A MCT1 D0501 @
EMC@ MCT1 2 1
4 21 MCT2 R0514 2 1 75_0805_5%
TCT2 1:1 MCT2 20 RJ45_TXD1P
T1/B MX2+
MDI_1+ 5 LSE-200NX3216TRLF_1206-2
4 MDI_1+ TD2+
D0502 @
MCT2 2 1
19 RJ45_TXD1N
MDI_1- 6 MX2-
4 MDI_1- TD2- LSE-200NX3216TRLF_1206-2
T1/A D0503 @
MCT3 2 1
1:1 RJ45_TXD2P
18
MDI_2+ 7
T1/B MX3+
4 MDI_2+ TD3+ LSE-200NX3216TRLF_1206-2
17 RJ45_TXD2N D0504 @
MX3- MCT4 2 1
MDI_2- 8
4 MDI_2- TD3- EMC@
9 16 MCT3 R0515 2 1 75_0805_5% LSE-200NX3216TRLF_1206-2
TCT3 T1/A MCT3
EMC@
10 15 MCT4 R0516 2 1 75_0805_5%
TCT4 1:1 MCT4 14 RJ45_TXD3P
T1/B MX4+
MDI_3+ 11
1U_0402_10V6-K
0.1U_0402_25V6-K
4 MDI_3+ TD4+
1 1
C0501 C0502 13 RJ45_TXD3N
C MDI_3- 12 MX4- C
2 EMC@ 2 EMC@ 4 MDI_3- TD4-
T1/A
BOTH_NA0069R-LF SP050008B00
C0501, C0502 close to LAN Chip Table of X-FORM (U0501)
Vendor LCFC PN Description
BOTHHAND SP050008B00 S X'FORM_ NA0069R LF LAN
RJ-45 Conn.
D0505 RCLAMP0524PATCT_SLP2510P8-10-9
Vinafix.com JRJ1 ME@

+3VALW_LAN A2
MDI_0+ 9 1 MDI_0+ AMBER_LED+
MDI_0- 8 2 MDI_0- R0517 1 2 510_0402_1% RJ45_ACTIVITY#_R A1
MDI_1+ MDI_1+ 4 RJ45_ACTIVITY# AMBER_LED-
7 4 GND1
MDI_1- 6 5 MDI_1- RJ45_TXD3N 8 GND_1
PR4- GND2
RJ45_TXD3P 7 GND_2
PR4+
B B
RJ45_TXD1N 6
EMC@ PR2-
3
RJ45_TXD2N 5
1 PR3-
C0526 RJ45_TXD2P 4
220P_0402_50V7-K PR3+
2 EMC_NS@ RJ45_TXD1P 3
PR2+
RJ45_TXD0N 2
PR1-
RJ45_TXD0P 1
PR1+
+3VALW_LAN B2
D0506 RCLAMP0524PATCT_SLP2510P8-10-9 Green_LED+
R0518 1 2 510_0402_1% RJ45_LINKUP#_R B1
4 RJ45_LINKUP# Green_LED-
SINGA_2RJ3103-108211F
MDI_2+ 9 1 MDI_2+ EMC@
MDI_2- 8 2 MDI_2-
MDI_3+ 7 4 MDI_3+ RJ45_GND C0523 1 2 1000P_1808_3KV7k~D LANGND
MDI_3- 6 5 MDI_3-
1 1
C0524 C0525
1 0.1U_0402_10V6-K .01U_0402_16V7-K
2 EMC_NS@ 2 EMC@
EMC@ C0527
3
220P_0402_50V7-K
2 EMC_NS@ LANGND
A A

Issued Date 2017/03/17 Deciphered Date 2017/12/31 RJ45 CONN
Custom 1.0
5 4 3 2 1
5 4 3 2 1
+3VS +3VS 3,4
1
1
C0604
D C0614 0.1U_0402_10V7-K D
4.7U_0603_6.3V6-K 2
+3VS 2
1
C0609
4.7U_0603_6.3V6-K
2@
+3VS
1 1 1 C0603
1U_0402_10V6-K
C0601 C0608 C0606 2
4.7U_0603_6.3V6-K 0.1U_0402_10V7-K 0.1U_0402_10V7-K
All of cap. close to chip 2 2 2
1 1
18
10
12
26
32
31
11
19
1
9
U0601 C0615 C0602
4.7U_0603_6.3V6-K 0.1U_0402_10V7-K
CORE_12VCCD
PE_33VCCAIN
PE_12VCCAIN
AUX _33VIN
MAIN_LDO_12VOUT
MAIN_LDO_VIN
SD_IO_SKT_33VIN
AUX_LDO_CAP
PLL_DLL_12VCCAIN
SD_IO_LDO_CAP
2 2
R0608 1 2 191_0402_1% SD_RREF 4
PE_REXT
C
Close to chip C
PCIE12_CTX_C_DRX_N 5
3 PCIE12_CTX_C_DRX_N PCIE12_CTX_C_DRX_P PE_RXM
6
3 PCIE12_CTX_C_DRX_P PE_RXP
+CRD_POWER
C0611 1 2 0.1U_0402_10V7-K PCIE12_CRX_C_DTX_P 7
3 PCIE12_CRX_DTX_P PE_TXP
C0613 1 2 0.1U_0402_10V7-K PCIE12_CRX_C_DTX_N 8 17
3 PCIE12_CRX_DTX_N PE_TXM SD_SKT_33VOUT
1
CLK_PCIE_CR# 2 @ C0616
3 CLK_PCIE_CR# CLK_PCIE_CR PE_REFCLKM SD_WP
3 21 R0616 1 2 0_0402_SM 1U_0402_10V6-K
3 CLK_PCIE_CR PE_REFCLKP SD_WPI 2
20 SD_CD#
SD_CD# @
27 SD_CLK_MS_DATA0 R0610 1 2 0_0402_SM SD_CLK_MS_DATA0_R
PLT_RST# 14 SD_CLK @
3,4 PLT_RST# PE_RST#_GATE# SD_CMD_MS_DATA2 SD_CMD_MS_DATA2_R
28 R0611 1 2 0_0402_SM
SD_CMD @
13 29 SD_MS_DATA3 R0612 1 2 0_0402_SM SD_MS_DATA3_R
+3VS MAIN_LDO_EN SD_D3 @ 1
30 SD_DATA2_MS_CLK R0613 1 2 0_0402_SM SD_DATA2_MS_CLK_R
R0605 1 @ 2 10K_0402_5% SD_WAKE# 15 SD_D2 @ C0605
+3VS DEV_WAKE# SD_DATA1 SD_DATA1_R
24 R0614 1 2 0_0402_SM 5P_0402_50V9-C
SD_D1 @ 2 EMC_NS@
25 SD_DATA0_MS_DATA1 R0615 1 2 0_0402_SM SD_DATA0_MS_DATA1_R
CLKREQ_PCIE5_CR# 23 SD_D0
3 CLKREQ_PCIE5_CR# CLKREQ#
Vinafix.com 20170712
22 Change R0610, R0611, R0612, R0613,
LED#_IO1
16
R0614, R0615, R0616 to short pad for EMI
+3VS IO0_MAIN_LDOSEL
GND
OZ621FJ1LN_QFN32_4X4 33 S IC OZ711LV1LN-B-0-TR QFN CONTROLLER
B SA00008DP00 B
+CRD_POWER
1
R0617
0_0603_5%_SM
40 mils JREAD1
2
SD_DATA2_MS_CLK_R 1
SD_MS_DATA3_R 2 DAT2
SD_CMD_MS_DATA2_R 3 CD/DAT3
4 CMD
SD_CLK_MS_DATA0_R 5 VDD
6 CLK
1 1 VSS
SD_DATA0_MS_DATA1_R 7
C0612 C0610 SD_DATA1_R 8 DAT0
0.1U_0402_10V7-K 10U_0603_6.3V6-M DAT1
2 2 SD_CD# 9 11
10 SD_CD# GND_1 12
GND GND_2 13
GND_3 14
GND_4 15
GND_5
A A
T-SOL_5-251411003000-6
Close to JREAD1. ME@
Vinafix.com Security Classification LC Future Center Secret Data Title

Issued Date 2017/03/17 Deciphered Date 2017/12/31 Card Reader
Custom 1.0
5 4 3 2 1
5 4 3 2 1
+5VALW +5VALW 3
+3VALW +3VALW 3,4
+3VS +3VS 3,4,6

D +3VL D
+3VL 3
H1 H2 H3 H4
PAD_C3P6D2P6 PAD_C6P0D2P3 PAD_C8P0D2P3 PAD_C3P0D2P3
@ @ @ @
1
H5 H6 NH1
PAD_C6P0D3P3 PAD_C6P0D2P8 PAD_O2P7X3P3D2P7X3P3N
@ @ @
1
H7 H8
PAD_C6P0D3P5 PAD_C5P0D2P3
@ @
1
C C
B
Vinafix.com B
A A

Issued Date 2017/03/17 Deciphered Date 2017/12/31 Screw Hole
Custom 1.0
5 4 3 2 1

Thinkpad E580 LCFC Nm-b421 Dis E480 E580 r1.0

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Thinkpad E580 LCFC Nm-b421 Dis E480 E580 r1.0

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Vinafix.

+3VS +3VS <6,9,10,11,12,14,15,23,25,30,32,37,39,40,47,50,51,57,58,59,60,61,63,65,66,67,69,72,85,86>

+VCC_IO +VCC_IO <11,18,21,71>

R0502 1 2 2K_0402_5% DDIP1_CTRLCLK DDIP1_HPD R0506 1 @ 2 100K_0402_5%

R0503 1 2 2K_0402_5% DDIP1_CTRLDATA DDIP2_HPD R0507 1 2 100K_0201_1%

R0505 1 2 2.2K_0402_5% DDIP2_CTRLDATA ENBKL R0509 1 2 100K_0201_1%

DP port Enable Disable

DDPB_CTRLDATA pull-high no connect

DDPC_CTRLDATA pull-high no connect

CPU_DDI1_N2 E55 C47 CPU_EDP_TX0-

Security Classification LC Future Center Secret Data Title

+2.5V +2.5V <23,24,25,26,94>

Block 2 BA61 DDR0_DQ[24] DDR0_DQ[40] M_B_DQ39 BB29 DDR0_DQ[54]/DDR1_DQ[38]

AY39 DDR0_DQ[32] DDR1_DQ[0]

Security Classification LC Future Center Secret Data Title

M_A_DQ16 AF65 AN45 -M_B_DDRCLK0_1066M

Block 1 AF70 DDR1_DQ[8] DDR0_DQ[24] M_A_DQ58 AP60 DDR1_DQ[25]/DDR0_DQ[57]

AN60 DDR1_DQ[27] DDR0_DQ[59] M_B_DQ60

AT60 DDR1_DQ[30] DDR0_DQ[62] [KBL PDG]for DDR4 COMPENSATION

AU40 DDR1_DQ[32] DDR1_DQ[16]

+VCC_ST +VCC_ST <15,16,18,21,71,86>

+VCC_STG +VCC_STG <16,18,71>

+3VALW_PCH +3VALW_PCH <9,10,11,12,19>

1 XDP_BPM#2 B54 B59 XDP_TRST#

1 2 EC_WAKE#_SUS BA5 C59 PCH_JTAG_TMS

XDP_TMS R0814 1 DCI@ 2 0_0201_5% PCH_JTAG_TMS

XDP_TRST# R0815 1 DCI@ 2 0_0201_5% PCH_JTAG_TRST#

Security Classification LC Future Center Secret Data Title

+3VALW_PCH +3VALW_PCH <8,10,11,12,19>

SPI_SI SPI_SO BA13 LPC_AD1 LPC_AD1 <40>

C-LINK AY12 LPC_AD3 LPC_AD3 <40>

AW9 PCH_PCI_CLK_R R0910 1 EMC@ 2 22_0402_5% CLK_PCI_EC <40>

SPI_IO3_8MB R0935 1 2 33_0402_5% SPI_IO3 SPI_IO3_4MB R0940 1 4M@ 2 33_0402_5% SPI_IO3

PCH_SML1DATA 3 4 EC_SMB_DA3 EC_SMB_DA3 <32,40,57,59>

2N7002KDWH GPU, Thermal Sendor,

Security Classification LC Future Center Secret Data Title

+3VALW_PCH +3VALW_PCH <8,9,11,12,19>

R1026 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5%

Security Classification LC Future Center Secret Data Title

+3VALW_PCH +3VALW_PCH <8,9,10,12,19>

WINDU and E470 can't stuff TBD

<51> PCH_BEEP PCH_BEEP AW5

Security Classification LC Future Center Secret Data Title

+3VALW_PCH +3VALW_PCH <8,9,10,11,19>

Security Classification LC Future Center Secret Data Title

Security Classification LC Future Center Secret Data Title

Issued Date 2015/01/12 Deciphered Date 2016/01/12 KBL(I)_CS12/ EMMC

+RTCBATT +RTCBATT <66,80>

+RTCVCC +RTCVCC <15,19>

+3VS +3VS <5,6,9,10,11,12,15,23,25,30,32,37,39,40,47,50,51,57,58,59,60,61,63,65,66,67,69,72,85,86>

<63> CLK_PCIE_WLAN# CLK_PCIE_WLAN# D41

SM01000JN0J YC2 KBL@

Security Classification LC Future Center Secret Data Title

+3VALW +3VALW <6,9,12,19,40,50,58,60,63,65,66,67,72,83,84,91,95>

+3VALW_PRIM +3VALW_PRIM <19>

+3VS +3VS <5,6,9,10,11,12,14,23,25,30,32,37,39,40,47,50,51,57,58,59,60,61,63,65,66,67,69,72,85,86>

R1526 1 @ 2 10K_0402_5% PCH_SYSPWROK

R1527 1 @ 2 10K_0402_5% AC_PRESENT

Vinafix.com SKYLAKE-U_BGA1356 REV = 1 11 OF 20

Security Classification LC Future Center Secret Data Title

+VCC_CORE +VCC_CORE <17,27,87,90>

+VCC_ST +VCC_ST <8,15,18,21,71,86>

+VCC_ST [SKL PDG]VIDSCK