Design of RF to DC conversion circuit

for energy harvesting in CMOS 0.13-μm

technology
Cite as: AIP Conference Proceedings 2045, 020089 (2018); https://doi.org/10.1063/1.5080902
Published Online: 06 December 2018

M. A. Rosli, S. A. Z. Murad, M. N. Norizan, et al.

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AIP Conference Proceedings 2045, 020089 (2018); https://doi.org/10.1063/1.5080902 2045, 020089

© 2018 Author(s).
 Design of RF to DC Conversion Circuit for Energy
Harvesting in CMOS 0.13-μm Technology
M A Roslia), S A Z Muradb), M N Norizanc) and M M Ramlid)

School of Microelectronic Engineering, Universiti Malaysia Perlis, Pauh Putra Campus,

02600 Arau, Perlis, Malaysia.
b)
Corresponding author: sohiful@unimap.edu.my
a)
anuar_ee87@yahoo.com
c)
mohdnatashah@unimap.edu.my
d)
mmahyiddin@unimap.edu.my

Abstract.The demand of a long life battery unit to supply the power for wireless application devices show
significant grows. The radio frequency is one of the sources that can harvest the surrounding energy to a
desired voltage due to availability to find everywhere with free cost. This paper presents a design of RF to
DC conversion circuit for energy harvesting. The proposed circuit consists of rectifier, ring oscillator, charge
pump and regulator is implemented in 0.13 μm CMOS technology. The rectifier is rectified the RF input
signal to a DC voltage. The combination of charge pump and the ring oscillator act as a DC to DC converter
to boost a low input voltage to higher output voltage. Finally the DC output voltage will be regulated to a
desired 1.2 V DC. The simulations result shows that the RF signal of 900 MHz to 2400 MHz, -16.48 dBm is
converted to DC regulated voltage of 1.25 V DC at 50 kΩ load.

INTRODUCTION
The increment demand of wireless devices such as mobile phones and computers shows that the important of
wireless application in whole world [1]. However, the usage of these devices in order to maintain the system
required continuous supply or long battery life. Nevertheless, the batteries have a limited life time and hazardous
chemicals concern to safety matters. Here comes the importance of RF energy harvesting system.

This is because among all energy harvest sources, the RF is available and very easily found at any places at any
time. In other words, unlike other sources the RF energy is independent from the time limitation, geographical or
weather conditions [2]. The RF is an electrical oscillation, with a frequency ranging from 3 kHz to 300 GHz and
carrying an alternating current. Some prominent electronic devices such as radio system (Frequency Modulation and
Amplitude Modulation), wireless router (Internet and Bluetooth) and television transmission transmitted the radio
frequency signal for data transferring. The idea is to harvest those RF energy sources and store it for our use in
certain application.

Based on this concept, the devices such as mobile phones can be used to call or access the internet connection
while charging the battery at same time [3]. Therefore, the study of power energy harvesting now become a
highlight topic in order to optimize the supply of these technology devices. This outcome power can make the
wireless application become more low cost maintenance and have longer battery life by implanted the device
module that have ability to receive and convert the energy and store in storage device [4].

The design of RF to DC conversion circuit for energy harvesting is discussed in this paper. In section II, the
overview of energy harvesting is briefly discussed. Section III presents the proposed circuit of RF to DC conversion.

4th Electronic and Green Materials International Conference 2018 (EGM 2018)
AIP Conf. Proc. 2045, 020089-1–020089-9; https://doi.org/10.1063/1.5080902
Published by AIP Publishing. 978-0-7354-1771-7/$30.00

020089-1
The simulation results of the proposed circuit and discussion is presented in Section IV. Finally, conclusion is given
in Section V.

Circuit Implementation

The proposed RF to DC conversion circuit consist of rectifier, ring oscillator, charge pump and regulator is
implemented in 0.13 μm CMOS technology. Every sub-circuit is explained as follows.

A. Rectifier

The multi-stage NMOS RF to DC converter is chosen as a converter to convert the AC signal to DC signal.
Figure 1 shows the proposed multilevel NMOS RF to DC. Each stage of the circuit consists of NMOS transistors, a
coupling capacitor and multiplying capacitor. The circuit rectifies the AC input in both positive and negative cycle.
When AC signal come in negative half cycle period, the drain-to-source voltage (VDS) is in a negative value; making
NM1 is in a reverse biased condition and therefore is turned off. While NM 2 is a forward biased and it is turned on.
This allows the current going through NM2 and charge in C1. As the negative cycle ends, NM1 becomes forward
biased and turned on, allowing the charged current from C1 to flow through C9. As more stages cascaded, each
capacitor charged will provide a bias voltage, therefore increasing the corresponding charged current at the end until
the AC signal is saturated and the ripples is minimal. Thus, if more stage of NMOS RF to DC converter is used in
the circuit, more DC output voltage will be generated. The transistors NM1-NM17 use N-channel MOSFET with the
size of 40 μm / 0.13 μm. While the decoupling capacitors C1 – C17 value is 10 pF.

C1 C2 C3 C4 C5 C6 C7 C8 C9

NM2 NM4 NM6 NM8 NM10 NM12 NM14 NM16

RF
NM1 NM3 NM5 NM7 NM9 NM11 NM13 NM15 NM17
NM18

C10 C11 C12 C13 C14 C15 C16 C17 CLOAD RLOAD

C18

FIGURE 1. Schematic of multilevel NMOS RF to DC converter

B. Oscillator

The purpose of ring oscillator is to generate the pulse with calculated frequency level for charge pump to
operate. Ring oscillator can easily design by using CMOS and it can provide oscillation with low power dissipation,
hence help optimizing the efficiency of overall circuit [9]. Ring oscillator can be designed with two types of
topologies, that is single-ended or differential structures. Figure 2 shows the basic structure of both single-ended and
differential ring oscillator structures.

(a) (b)

FIGURE 2. Basic structure of ring oscillator (a) Single-ended and (b) Differential ring oscillator

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 The equation of the frequency oscillation, fosc is defined as [5]:

1 (1)
f osc
2 NTP
where: N = Odd number of inverter
TP = Propagation delay

From Equation (1), the frequency generated is indirectly proportional to the number of the inverter and also the
delay of the transition. The frequency can be adjusted by varying the delay time. Higher delay time will lead to low
frequency oscillation. However a single-ended ring oscillation design typically has a pairs of PMOS and NMOS
transistors.

The ring oscillator generates pulse signal which desired frequency to charge pump circuit to operate. As per
advance, the range of the desired frequency needed to be in the range of kHz for the charge pump operates in
optimum condition. Considering this, the frequency can said to be low compare to common generated frequency by
ring oscillator. Hence, to obtain the kHz frequency pulse, the number of inverter and the timing delay of each
transition should be calculated carefully. The propagation delay, T p is defines as a total of rise time, T r and fall time,
Tf as stated in Equation (2)

T T T (2)
P r f
The rise time and fall time are defined as:
CL (3)
Tr | k u
E pVDD

CL (4)
Tf | k u
E nVDD
where: CL = Capacitive loading at next stage
β = Transistor gain factor
VDD = MOSFET supply voltage

From Equation (3) and Equation (4), the delay time can be decrease by increasing the supply voltage. However,
by increasing supply voltage, the power consumption of ring oscillator circuit might also increase and this will lead
to high heat dissipation. The worst case in real application is the device might be broken due to over temperature.
The other way to vary the delay time is by adjusting the value of the transistor gain factor. The transistor gain factor,
β is defined by [6]:

P H
p §W · (5)
E ¨ ¸
p t
ox © ¹
L

where: μ = mobility of holes in the channel

tox = Thickness of the gate insulator

From Equation (5), the transistor gain factor is directly proportional to the ratio of W/L. So it can be conclude
that the time delay can be decreased either by increasing the width of the device or decreasing the length of the
device. Moreover, with greater gain, the components can supply more current to the next stage, which will allow the
device to be faster when switching the gate. Figure 3 shows schematic of the proposed common single-ended ring
oscillator. The transistors’ size of PMOS and NMOS used in ring oscillator circuit are 40 μm / 0.13 μm and 16 μm /
0.13 μm, respectively. The value of decoupling capacitors is 0.8 pF.

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 PM1 PM2 PM3 PM4 PM5

VDD

NM1 NM2 NM3 NM4 NM5

C1 C2 C3 C4 C5

FIGURE 3. Basic single-ended ring oscillator schematic

C. Charge Pump

Most common charge pump type used in low-voltage application is cross-coupled charge pump. Figure 4 shows
schematic of cross-couple charge pump.

Φ1
C1
N1 P1

Vout
VDD
CC

N2 P2
C2

Φ2

Φ1

Φ2

FIGURE 4. Cross-coupled charge pump circuit

As can be seen in Figure 5; cross-couple charge pump consists of a pair of NMOS and PMOS device as a
switching component and also capacitor as storage components. Initially we assume that N1 is turn on and C1 is
charged by VDD. When entering first phase, the clock Φ1 swing the signal with VDD amplitude at C1. The voltage
level at top plate of C1 now becomes 2 VDD. The high voltage level will turn on N2 and turn off P2. At the same
time, low signals Φ2 force capacitor C2 produce low level voltage at top plate, turning off N1 and turn on P1. Hence
the potential voltage 2 VDD at C1 plate will discharge to the load. In the second phase, the clock Φ1 charged to
ground forcing N2 to turn off and turn on P2. Meanwhile, the clock Φ2 swing VDD voltage to turn on N1 and turn
off P1. Therefore the current at plate C2 will discharge to load. This process will run continuously as long as the
clock input is available. The NMOS element provides a junction bias while PMOS element creates an output
switches to the output load. In the application design, the clock is generated by ring oscillator circuit.

The ring oscillator generates two mirror signals, θ1 and θ2. Both signals have same 50 % duty cycle and
frequency but with different phases. The small DC voltage from rectifier circuit will be biased by these pulses. The
frequency of the pulse should be considered to minimize the external power resources. As the DC input voltage from
rectifier increases, the current needed to bias the voltage will be saturated hence the efficiency of the charge pump
circuit will be increased. The circuits are cascaded to ensure the output voltage can be optimized as much as
possible. The capacitor value should be small to allow oscillation clock from ring oscillator to go through. In this

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charge pump circuit, the transistors’ size used for PMOS and NMOS are 20 μm / 0.13 μm and 20 μm / 0.13 μm,
respectively. The value of decoupling and load capacitors is 1 nF.

D. Regulator

The output voltage from charge pump circuit may have large variation, depending on the effected parameters
such as load condition, the power and frequency of the RF input signal. The changes of the output voltage levels
might not suitable for the battery in real application. All battery or power supply input should have specific input
voltage. Therefore, the devices can have long life time hence reliable for any usage condition. In this circuit, the
regulator is designed to have a constant 1.2 V DC output with maximum 100 μA current load. The reason of 1.2 V
been selected as the targeted output voltage due to the RF front end block in CMOS 0.13 μm process commonly use
1.2 V as a voltage supply.

An error amplifier is a circuit use to amplify the error signal. The input of error amplifier consists of two signals,
which are reference voltage and the feedback voltage. Since the reference voltage is fixed to a certain voltage level,
the feedback resistors will play total role to generate output from error amplifier [7-11]. When input voltage
approaches desired output voltage, the error amplifier will drive gate-to-source voltage.

Figure 5 shows a schematic of voltage regulator circuit. As can be seen in Fig. 5, the regulator circuit consists of
error amplifier, a pass element and feedback resistors. The P-channel MOSFET PM1 with a size of 1 μm / 0.13 μm
size and PM2 – PM5 with a size of 4μm / 0.13 μm is employed. Meanwhile, N-channel NM1- NM2 with a size of 1
μm/ 0.13 μm, NM4, NM6 with a size of 0.15 μm / 0.13 μm, NM3 and NM5 with a size of 4 μm / 0.13 μm and 3 μm
/ 0.13 μm is used, respectively. The feedback resistor, R1 is 30 kΩ and R2 is 100 kΩ. The capacitance load, C LOAD
is 0.47 nF. In this regulator design, the reference voltage VREF of 1.2 V is used.

PM1
PM2 PM3

Pass element
Error amplifier

VIN
PM4 NM7
PM5

NM3
NM4
CLOAD

RLOAD
R2
Feedback resistors

NM1 NM2

VREF

NM5 NM6
R3

FIGURE 5. Schematic of voltage regulator circuit

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E. Complete RF to DC Conversion Circuit

Figure 6 shows a complete schematic of the proposed RF to DC conversion circuit. The RF input is applied
at the rectifier circuit, the DC voltage is boost up by charge pump, and finally the regulator will regulate the input
from the charge pump to obtain 1.2 V output voltage.

FIGURE 6. Complete schematic of the proposed RF to DC conversion circuit

SIMULATION RESULTS
The proposed RF to DC circuit is simulated using Cadence Virtuoso software. The complete circuit is simulated
with the integration of all circuits together to verify the performance.

Figure 7 shows the simulation results of the proposed rectifier output voltage versus input voltage. The AC input
voltage from 50 mV to 500 mV is applied with RF frequencies of 900 MHz and 2400 MHz at 10 kΩ load. The
output voltage is increased when the input voltage is increased for both frequencies. Figure 8 shows resistance loads
of 10 kΩ, 50 kΩ and 100 kΩ corresponding to the input voltage at 2.4 GHz. As can be seen, the resistance load is
proportional with the input voltage.

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 900
800
700 F= 900 MHz
600 F= 2.4 GHz

Vout (mV)
500
400
300
200
100
0
50 100 150 200 250 300 350 400 450 500
Vin (mV)
FIGURE 7. Simulation result of rectifier output with 900 MHz and 2.4 GHz frequencies at 10 kΩ load

1600
1400
1200
RL = 10 kΩ
Vout (mV)

1000 RL = 50 kΩ
800 RL = 100 kΩ

600
400
200
0
50 100 150 200 250 300 350 400 450 500
Vin (mV)

FIGURE 8. Simulation result of rectifier output at 10 kΩ, 50 kΩ and 100 kΩ load

The simulation results of the proposed charge pump with the pulse of 40 MHz from ring oscillator is shown in
Figure 9. The input voltage of 100 mV, 500 mV and 1000 mV is applied to the charge pump with resistance load of
10 kΩ, 50 kΩ and 100 kΩ. As can be seen, the output voltage significantly boost up to 1.7 V, 3.67 V and 3.99 V at
input voltage of 100 mV with resistance load of 10 kΩ, 50 kΩ and 100 kΩ, respectively. The similar behavior can
be seen when the input voltage is increased.

5
4.5
4
3.5
Vout (V)

3
2.5
2
1.5
1 Rload = 10 kΩ
Rload = 50 kΩ
0.5 Rload = 100 kΩ
0
100 500 1000
Vin (mV)
FIGURE 9. Simulation result of charge pump

Finally, Figure 10 shows the output voltage from rectifier, charge pump and regulator. The simulation result
shows that with the input voltage of 150 mV, a low output voltage of 370 mV from rectifier stage is boost up to 1.75
V at charge pump stage. Further, the output voltage is regulated at 1.25 V in regulator stage.

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 2
Charge pump output
1.8
1.6
1.4 Regulator output

VOUT (V)
1.2
1
0.8
0.6
Rectifier output
0.4
0.2
0
0 5 10 15 20 25 30 35 40 45 50
time (μs)

FIGURE 10. Output voltage from rectifier, charge pump and regulator

Table 1 shows the comparison between this works with previously published works. In [12], a cross-coupled
charge pump topology is employed which required a high input power to obtain 2.05 V output voltage at 900 MHz
frequency. While in [13], a 5-stage CMOS rectifier topology successfully generates a 2.6 V that achieve the highest
output voltage. However, the output voltage is obtained with very high load impedance of 150 kΩ at 900 MHz
frequency. A sensitive differential drive CMOS RF-DC has been proposed in [14]. The proposed design is able to
convert RF to DC 1.25 V output voltage with high resistance load at low frequency of 350 MHz. As compared to
this work, the proposed design can convert the lowest RF input voltage of -16.5 dBm to 1.25 V DC at 900 MHz to
2400 MHz frequencies range.

TABLE 1. Comparison of the proposed RF to DC conversion with other previous works

Reference [12] [13] [14] This work
Technology (CMOS) 0.13 μm 0.18 μm 0.18 μm 0.13 μm
Sensitive
5-stage Multi-stage NMOS
Cross-coupled differential drive
Topology CMOS rectifier with cross-
charge pump CMOS RF-DC
rectifier coupled charge pump
converter
Load (kΩ) 100 150 1000 50
Input Power (dBm) -6 -10 -10 -16.5
Frequency (MHz) 900 900 350 900-2400
Output Voltage (V) 2.05 2.60 1.25 1.25

CONCLUSION
The RF to DC converter circuit using 0.13 μm CMOS technology for RF energy harvesting is presented. The
circuit consists of rectifier to convert the RF input signal to a DC voltage. The DC voltage is connected with a
charge pump to boost the input DC voltage to higher output voltage. Finally, the output voltage will be regulated by
a regulator to generate a required DC voltage. The simulation results show that the proposed design able to convert
RF input signal of -16.5 dBm to 1.25 V DC at frequencies range of 900 MHz to 2400 MHz.

ACKNOWLEDGMENTS
The authors would like to acknowledge the financial support obtained from the School of Microelectronic
Engineering, Universiti Malaysia Perlis (UniMAP) in completing this research project.

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