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1 Instituto de Plasmas e Fusão Nuclear, Instituto Superior Técnico, Universidade de Lisboa, Av. Rovisco Pais 1, 1049-001 Lisboa, Portugal
2 ENEA C. R. Frascati, Dipartimento FSN, via E. Fermi 45, 00044 Frascati (Roma), Italy.
3 LIBPhys-UC, Department of Physics, University of Coimbra, P-3004 516 Coimbra, Portugal
This contribution presents the architecture, implementation and test of a different device driver
approach using the polling mechanism which improves the performance and reliability.
System Architecture Each built data DMA block have multiple channel packets which can be from different ADCs.
The kernel thread separates the data from different ADCs into independent memory buffers,
The Host Computer runs Scientific Linux 7 as using the channel packet tag, which identifies the source ADC.
Operating System with kernel 3.10-rt
The DMA #n buffers stores the
Intel® Core TM i7-5930K@3.50 GHz
non-separated data that is
256 GB SSD and 64 GB of RAM available for test purposes (only)
The FPGA sent event data through two data paths [1]: during the prototype phase.
DMA#0 - Event base raw data path The high-level applications,
reads the data from the driver
DMA#1 - Processed data path
memory buffers, based on the
Each data DMA has 8 KB. In case of the raw data path, write and read pointers.
the driver transfers data in blocks of 32 KB (4 DMAs). Error counters were implemented
The DMA#2 is a special DMA containing 32 bits with to provide real-time information
the FPGA status information about data transmission. about data packages losses.
Some validation bits and also a counter flag are added to improve the reliability of the DMA
status information Results & Conclusions
The COUNT_DMA#n and DMA#n CYCLE on the status information gives the number of sent The tests show a stable solution during 60 minutes acquisitions with data acquisition rates up
DMAs for each data path and the last memory address written by the FPGA in the kernel space. to 1.5 GB/s.
The DMA#0 has 16 memory addresses and DMA#1 has 4, and each memory address has 8 KB of Using the interrupt approach
memory space. (implemented and tested in a previous
phase of the prototype), there are
missing packets above 512 MB/s for
single DMA #0 acquisitions, and above
64 MB/s for acquisitions from two DMAs
at same time.
The packets recovered is a relevant issue to guarantee the data integrity, despite small impact.
The usage of data transmission information can be a valuable contribution to solve problems when
a traditional implementation of a Linux device driver based on interrupt handling or polling
mechanisms cannot be used.
The presented architecture is scalable and adjustable. Also, is data-agnostic because only
the status information is considered to trigger the data to transfer.
The presented solution implements an internal data transmission recovery algorithm, enabling
the device driver to automatically check and recover missing data blocks in a transparent way
for the host applications. Using a traditional approach, in which a block is transferred in each status
changed, if some transition was missed the data would be lost.
Main References:
[1] A. Fernandes et al., FPGA code for the data acquisition and real-time processing prototype of the ITER Radial Neutron Camera, 21st IEEE Real Time Conference, 2018
[2] N. Cruz et al., The design and performance of the real time software architecture for the ITER Radial Neutron Camera, 21st IEEE Real Time Conference, 2018
[3] B. Santos et al., Real-time data compression for data acquisition systems applied to the ITER Radial Neutron Camera, 21st IEEE Real Time Conference, 2018
[4] R.C. Pereira et al., Real-Time data acquisition Prototype proposal of the ITER radial neutron camera and gamma-ray spectrometer , Fusion Eng. Des. 123 (2017) 901-905