2.5gbe Mac and Phy Megacore: Swip Functional Description

2.
5GbE MAC and PHY Megacore

SWIP Functional Description
swsoo
13 January 2012
Altera Corporation Confidential

2.5GbE MAC and PHY Megacore FD
Table of Contents
1 OVERVIEW............................................................................................................................ 4
2 BACKGROUND..................................................................................................................... 4
2.1 ALTERA ETHERNET 2.5GB DESIGN EXAMPLE....................................................................4
2.1.1 2.5GMAC................................................................................................................... 5
2.2 2.5GPHY....................................................................................................................... 6
3 FEATURE DESCRIPTION..................................................................................................... 7
3.1 ALTERA ETHERNET 2.5GB DESIGN EXAMPLE SYSTEM.......................................................7
3.1.1 2.5GMAC Core.......................................................................................................... 8
3.1.2 Avalon-ST Dual Clock Fifo........................................................................................ 8
3.1.3 Avalon MM Pipeline Bridge.......................................................................................8
3.1.4 2.5GPHY................................................................................................................... 8
3.2 FAMILY SUPPORT............................................................................................................ 8
3.3 GUI................................................................................................................................ 8
3.4 SIMULATION..................................................................................................................... 9
3.5 BACKWARD COMPATABILITY.............................................................................................. 9
3.6 QUARTUS SUPPORT......................................................................................................... 9
3.6.1 Time Quest................................................................................................................ 9
3.6.2 Pin Planner................................................................................................................ 9
3.6.3 QIC compliant............................................................................................................ 9
3.6.4 Design assistant........................................................................................................ 9
3.6.5 QIS Warning.............................................................................................................. 9
3.6.6 Metastability.............................................................................................................. 9
3.6.7 QIP file...................................................................................................................... 9
3.7 OPEN CORE PLUS........................................................................................................... 9
3.8 CLOCK DOMAIN CROSSING............................................................................................ 10
3.9 DEPENDENCIES............................................................................................................. 10
4 INTERFACE......................................................................................................................... 10
4.1 ALTERA ETHERNET 2.5GB DESIGN EXAMPLE INTERFACE.................................................10
4.2 2.5GPHY INTERFACE.................................................................................................... 18
4.3 REGISTER INTERFACE.................................................................................................... 25
4.3.1 2.5GPHY Register Description................................................................................25
4.4 2.5GMAC REGISTER DESCRIPTION................................................................................28
4.4.1 Register Description.............................................................................................. 28
5 DOCUMENTATION............................................................................................................. 46
6 IMPLEMENTATION DETAILS.............................................................................................47
7 TESTING.............................................................................................................................. 47
7.1 FUNCTIONAL VERIFICATION............................................................................................. 47
7.1.1 PHY Layer............................................................................................................... 47
7.1.2 MAC+PHY Verification............................................................................................48
7.1.3 Micro Core............................................................................................................... 50
8 References.......................................................................................................................... 51
FIGURE 1: ALTERA ETHERNET 2.5GB DESIGN EXAMPLE COMPONENTS...............................................4

FIGURE 2 : 2.5GBPS ETHERNET MAC............................................................................................... 5
FIGURE 3 : 2.5GBPS ETHERNET PHY................................................................................................ 7
Altera Corporation Confidential Page 2 of 51

FIGURE 4 : 2.5GBE INTERFACE....................................................................................................... 10
FIGURE 5 : 2.5GPHY INTERFACE.................................................................................................... 18
FIGURE 8 SV-VMM SETUP USING VIP’S TESTBENCH & ENVIRONMENT..............................................47
FIGURE 9 PHY EXTENDED VERIFICATION ENVIRONMENT...................................................................48
FIGURE 10 MAC+PHY VERIFICATION SOLUTION..............................................................................49
FIGURE 11 MAC STANDALONE VERIFICATION ENVIRONMENT.............................................................50
FIGURE 12 LANE DECODER SV VMM VERIFICATION ENVIRONMENT...................................................50
Figure 13 Lane Encoder SV-VMM verification environment.........................................................51
Revision History
Version Author Date Changes
1.0 Azad Affif Ishak 14th April 2011 2.5G Ethernet productisation
Shi Weei Soo
Tien Hee Goh
2.0 Shi Weei Soo 26th May 2011 Arria V and Stratix V support
Tien Hee Goh Detail on backward compatability
3.0 Shi Weei Soo 22th June 2012 Cyclone V, Cyclone V SOC and Arria V
SOC support
Detail of GUI

1 Overview
This document contains information on the productization and verification of the
2.5 Gigabit Ethernet Solutions (GbE). Two mega cores and one design example
will be created by end of this release. They are :
1) 2.5GMAC Megacore
2) 2.5GPHY Megacore
3) Altera Ethernet 2.5Gb Design Example( 2.5GMAC+2.5GPHY+Avalon-ST

Dual Clock Fifo+Avalon MM Pipeline Bridge) which will be the same
design Altera has delivered to Ericsson in Duxi project.
Supported flow is Megawizard only.
2 Background
2.1 Altera Ethernet 2.5Gb Design Example
Figure 1: Altera Ethernet 2.5Gb Design Example Components
This design example will be written in composed hardware tcl. The components
are 2.5GMAC, Altera Avalon Dual Clock Fifo, Altera Merlin Master Translator
(Pipeline Bridge) and 2.5GPHY.

2.1.1 2.5GMAC
The 2.5-Gbps Ethernet MAC IP core implements the IEEE 802.3 2005 and
802.1Q Ethernet standards. The IP core has the following interfaces: an Avalon
Streaming (Avalon-ST) interface on the client side, a 16-bit wide gigabit media
independent interface (GMII) on the network side, and an Avalon Memory-
Mapped (Avalon-MM) programming interface that provides access to 32-bit
registers and statistics counters.
Figure 2 : 2.5Gbps Ethernet MAC
2.5GMAC is a composed hardware tcl component and most of the sub-

components are shared with 10GMAC.
The 2.5GMAC supports the following features:
 Virtual local area network(VLAN) and stacked VLAN tagged frames

support as specified by IEEE 802.IQ and 802.1ad (Q-in-Q) standards
respectively

 Optional cyclic redundancy code (CRC)-32 computation and insertion on

the transmit datapath; CRC checking on the receive datapath with optional
forwarding of the frame check sequences(FCS) field to the client
application
 Checking of received frames for CRC error,undersized and oversized

frames and payload length error
 Programmable maximum length of receive frames up to 64Kbytes(KB)
 Programmable promiscuous (transparent) mode
 Optional padding termination on the receive datapath and insertion on the

transmit datapath
2.2 2.5GPHY
The 2.5-Gbps Ethernet PHY IP core consists of a PCS function and an
embedded PMA. The design of the PCS function is based on clause 36 of the
IEEE 802.3 Ethernet standards. The IP core has the following interfaces: a 16-bit
wide GMII on the client side, a 3.125 Gbps serial interface on the network side,
and an Avalon-MM programming interface that provides access to 32-bit
registers.

Figure 3 : 2.5Gbps Ethernet PHY
2.5GPHY is derived from Triple Speed Ethernet (TSE) PCSPMA 1000 Base X
variation.
3 Feature Description
3.1 Altera Ethernet 2.5Gb Design Example System
This Megacore is a composition of four major cores which are Avalon-ST Dual
Clock Fifo, 2.5GMAC, 2.5GPHY and Avalon Merlin Master Translator(Avalon MM
Pipeline Bridge).
Supported parameter option for this design example includes:
(1) Configuration types of “MAC and PHY” or “PHY only”
(2) Starting Channel number (Available for Arria II GX and Stratix IV GX/GT.
No longer needed for Transceiver PHY IP with different architecture)
(3) Transmiter DC FIFO depth

(4) Receiver DC FIFO depth
Transmiter and Reiceiver DC FIFO size setting is available for MAC and PHY
configuration only with configurable depth range from minimum requirement of 16
to 131072 and default value set to 16. This core will be hidden in 12.10
3.1.1 2.5GMAC Core
This core is a composition of smaller components and most of the components

are shared with 10GMAC core. To reduce core maintenance effort and promote
reusability, the core will still share majority of the components with 10GMAC.
Two components have been identified and couldn’t be shared due to recent
enhancement of 10GMAC. The modules are
(1) altera_eth_frame_decoder
(2) altera_eth_pause_controller_and_generator
We do not support any parameter option for this core and it will remain hidden in
12.10.
3.1.2 Avalon-ST Dual Clock Fifo
For details, please refer to document.
We do not support any parameter option for this core.
3.1.3 Avalon MM Pipeline Bridge
For details, please refer to document. Since the design example will be deployed
using Qsys, the Avalon MM Pipeline Bridge may have to be substituted with
Merlin Master Translator component.
3.1.4 2.5GPHY
For details, please refer to section 4.2 of this document.
3.2 Family Support

2.5GbE Megacore supports following families:
(1) Stratix IV GX/GT

(2) Arria II GX
(3) Arria V GX/GT
(4) Arria V SOC
(5) Stratix V GX/GT
(6) Cyclone V GX/GT
(7) Cyclone V SOC
Stratix IV GX/GT and Arria II GX in 11.1, Arria V support in 11.1sp2 and Stratix V
support in 12.0.
GUI
The name of 2.5GbE GUI is “Altera Ethernet 2.5Gb Design Example”.Megacore

GUI consist of following category:
(1) General Configuration which shows the selected device family(not

editable) and configuration types
(2) PHY Configuration to edit starting channel number.
(3) DC FIFO configuration
3.3 Simulation
2.5GbE solutions provides functional simulation in verilog. Customer flow
simulation supports NCSIM, Modelsim and VCS simulators.
This core will not support post-fit gate level simulation.
3.4 Backward compatability

Following steps need to be taken to upgrade from duxi design example (version
2.3):
(1) Remove existing file list for 2.5G MAC and PHY in duxi design example.
(2) Remove defparam for starting_channel_number in top.v file. This

parameter is defined using megawizard.
(3) Regenerate design using qmegawizard into same directory.The name of

generated design should be “altera_eth_2_5GbE”

(4) Generated IP files has different location compare to duxi design example.
There will be no impact by using generated QIP file for compilation.
(5) Simulation uses IEEE encryption. The impact will be minimum by utilizing
generated simulation scripts for simulation. More information on generated
script available in User Guide
(6) Upgrading to Arria V, Stratix V or Cyclone V require interface changes.

Refer to Section 4.1 for more information.
3.5 Quartus Support

3.5.1 Time Quest
This core should meet timing closure. Timing checks is covered in flow test.
3.5.2 Pin Planner
2.5GbE Megacore does not support pin planner.
3.5.3 QIC compliant
Strecth Goal
3.5.4 Design assistant
Clean from Critical and High design assistant warning. Device test template is
used to capture reported DA warnings.
3.5.5 QIS Warning
Target is to get zero QIS warning. Device test template is used to capture
reported warning.
3.5.6 Metastability
Will be ensured free from metastability issue.
3.5.7 QIP file
qip file is generated by hw_tcl
3.6 Open Core Plus

Support Open Core Plus by providing OCP file. OCP test template will be used to
ensure time_limited.sof file generation. Board test will be tested manually.
Automation plan depend on board resource availability.

3.7 Clock Domain Crossing

Manual verification with SpyGlass.
3.8 Dependencies
2.5GbE Megacore is greatly tie with PHY IP support on GiGE mode and
simulation script generation on customer flow simulation.
4 Interface
4.1 Altera Ethernet 2.5Gb Design Example Interface
Figure 4 : 2.5GbE Interface
NOTE: The SERDES control signals—gxb_cal_blk_clk, gxb_pwrdn, pll_pwrdwn, reconfig_clk, and reconfig_busy—are not
present in designs targeting Arria V, and Stratix V and Cyclone V devices.For designs targeting Arria V devices, the bus
width for reconfig_fromgxb and reconfig_togxb are [91:0] and [139:0] respectively.
Table 1 : Avalon-ST Transmit Signal
Avalon-ST Transmit Signals (Part 1 of 2)

Signal Direction Width Description

Assert this signal to indicate the beginning
avalon_st_tx_sop Input 1
of the transmit packet.
Assert this signal to indicate the end of the

avalon_st_tx_eop Input 1
transmit packet.
Assert this signal to qualify the transmit

avalon_st_tx_valid Input 1
data on the avalon_st_tx_data bus.
When asserted, this signal indicates that

avalon_st_tx_ready Output 1
the IP core is ready to accept data.
Carries the transmit data from the user

avalon_st_tx_data Input 64
application.
Use this signal to specify the number of

avalon_st_tx_empty Input 3 bytes that are empty during cycles that
contain the end of a packet.
Assert this signal to indicate the current

avalon_st_tx_error Input 1
receive packet contains errors.

Table 2 : Avalon ST Receive Signals
Avalon-ST Receive Signals

When asserted, this signal indicates
avalon_st_rx_sop Output 1
the beginning of the receive packet.
When asserted, this signal indicates

avalon_st_rx_eop Output 1
the end of the receive packet.
When asserted, this signal qualifies

avalon_st_rx_valid Output 1 the receive data on
the avalon_st_rx_data bus.
Assert this signal when the user

avalon_st_rx_ready Input 1
application is ready to accept data.
Carries the receive data to the user

avalon_st_rx_data[] Output 64
application.
avalon_st_rx_empty[] Output 3 Contains the number of bytes that are

empty during cycles that contain the

end of a packet.
When set to 1, the respective bits in

this signal indicate an error type in
the receive frame:
Bit 0: PHY error
avalon_st_rx_error[] Output 6 Bit 1: CRC error
Bit 2: Undersized frame
Bit 3: Oversized frame
Bit 4: Payload length error
Bit 5: Overflow error

Table 3: Avalon-MM CSR Signals
Avalon-MM CSR Interface Signals

Use this bus to specify
the register address you
avalon_mm_csr_address[] Input 19
want to read from or
write to.
Assert this signal to

avalon_mm_csr_read Input 1
request a read.
Carries the data read

avalon_mm_csr_readdata[] Output 32 from the specified
register.
Assert this signal to

avalon_mm_csr_write Input 1
request a write.
Carries the data to be

avalon_mm_csr_writedata[] Input 32 written to the specified
register.
When asserted, this

signal indicates that the
avalon_mm_csr_waitrequest Output 1 IP core is busy and not
ready to accept any
read or write requests.

Use the Avalon-ST status interface to obtain information and error status on
receive frames only when the option to remove CRC and/or padding is disabled
and no overflow occurs. When CRC and/or padding removal is enabled (see See
MAC Registers) or when an overflow occurs ( avalon_st_rx_ready is deasserted),
obtain the same information using the statistics counters.
Table 4: Avalon-ST Status Signals
Avalon-ST Status Interface Signals (Part 1 of 2)

When asserted, this signal
indicates
that avalon_st_rxstatus_data[
] contains valid information
about the receive frame.
avalon_st_rxstatus_valid Output 1
The IP core asserts this
signal in the same clock cycle
it receives the end of packet
( avalon_st_rx_eop is
asserted).
avalon_st_rxstatus_data[] Output 39 Contains information about
the receive frame:
Bits 0 to 15: Payload length.
Bits 31:16: Packet length.
Bit 32: When set to 1,
indicates an SVLAN frame.
indicates a VLAN frame.
indicates a control frame.
indicates a pause frame.
indicates a broadcast frame.
indicates a multicast frame.
indicates a unicast frame.
The IP core presents the
valid information on this bus
in the same clock cycle it

asserts avalon_st_rxstatus_v
alid . The information on this
data bus is invalid when an
overflow occurs or when CRC
and/or padding removal is
enabled.
When set to 1, each bit of this
signal indicates an error type
in the receive frame.
Bit 0: Undersized frame
Bit 1: Oversized frame
Bit 2: Payload length error
Bit 3: CRC error
Bit 4: Underflow
Bit 5: Unused.
avalon_st_rxstatus_error[] Output 7
Bit 6: PHY error
The IP core presents the
error status on this bus in the
same clock cycle it
asserts avalon_st_rxstatus_v
alid . The error status is
invalid when an overflow
occurs or when CRC and/or
padding removal is enabled.

Table 5 : Clock and Reset Signals
Clock and Reset Signals (Part 1 of 2)

Signal Name Direction Width Description
Active-high reset signal.
reset_n Input 1 Resets the 2.5-Gbps
Ethernet wrapper.
156.25 MHz GMII transmit

eth_2_5g_phy_tx_clk_out Output 1
clock.
122-MHz transmit clock.

Provides the timing
clk_122 Input 1
reference for the Avalon-
MM interface.
clk_39 Input 1 39.0625-MHz transmit

clock. Provides the timing
reference for the Avalon-

ST interface.

Table 6 : MDI Interface Signals
2.5-Gbps MDI Interface Signals

Signal
Direction Width Description
Name
ref_clk Input 1 125-MHz local reference clock.
Serial receive signal. Must be connected to a

rxp Input 1
differential pin.
Serial transmit signal. Must be connected to a

txp Output 1
differential pin.
Status Interface Signals

Directio
Signal Name Width Description
n
10-bit character error. Asserted
for
led_char_err[] Output 2 1 eth_2_5g_phy_tx_clk_out cycl
e when an erroneous 10-bit
character is detected.
10-bit running disparity error.

Asserted for
1 eth_2_5g_phy_tx_clk_out cycl
e when a disparity error is
led_disp_err[] Output 2 detected. A running disparity
error indicates that more than
the previous and perhaps the
current received group had an
error.
led_link[] Output 2 Asserted when the link

synchronization is successful.
Indicates
that eth_2_5g_phy_tx_clk_out P
eth_2_5g_phy_tx_pll_locked Output 1
LL is stable and in phase
with ref_clk .
Table 7:SERDES Control Signal
SERDES Control Signal (Part 1 of 2)

Calibration block clock for the
ALT2GXB module (SERDES). This
clock is typically tied to the 125 MHz
ref_clk. Only implemented when you
gxb_cal_blk_clk Input 1
use an internal SERDES.
This signal is not present in designs
targeting Arria V and, Stratix V and
Cyclone V devices
Power-down enable. Assert this
signal to power down the transceiver
quad block. This signal is
implemented only when you use an
gxb_pwrdwn Input 1 internal SERDES with the option to
export the power-down signal.
targeting Arria V, and Stratix V and
Cyclone V devices
This signal powers down a single
clock generation circuit. Assert this
signal to power down the CMU PLLs
that provide high-speed serial and
pll_pwrdwn Input 1 low-speed parallel clocks to the
transceiver channels.
targeting Arria V and, Stratix V and
Cyclone V devices

Reference clock for the dynamic

reconfiguration controller. If you use
a dynamic reconfiguration controller
in your design to dynamically control
the transceiver, both the
reconfiguration controller and the
MegaCore function require this clock.
reconfig_clk Input 1
This clock must operate between
37.5–50 MHz. Tie this clock low if
you are not using an external
reconfiguration controller.
Cyclone V devices
Connects to an external dynamic
reconfiguration controller. The bus
identifies the transceiver channel
whose settings are being transmitted
to the reconfiguration controller.
reconfig_fromgxb[] Output 17 Leave this bus disconnected if you
are not using an external
For designs targeting Arria V, and
Stratix V and Cyclone V devices, the
bus width is [91:0].
Driven from an external dynamic
reconfiguration controller. Supports
the selection of multiple transceiver
channels for dynamic reconfiguration.
Tie this bus to 3’b010 if you are not
reconfig_togxb[] Input 4
using an external reconfiguration
controller.
For designs targeting Arria V, and
Stratix V and Cyclone V devices, the
bus width is [139:0].
reconfiguration controller. This signal
indicates the busy status of the
dynamic reconfiguration controller
during offset cancellation. Tie this
reconfig_busy Input 1
signal to 1'b0 if you are not using an
external reconfiguration controller.
Cyclone V devices

4.2 2.5GPHY Interface
Figure 5 : 2.5GPHY Interface
NOTE: The SERDES control signals—gxb_cal_blk_clk, gxb_pwrdn, pll_powerdown, reconfig_clk, and reconfig_busy—are
not present in designs targeting Arria V, and Stratix V and Cyclone V devices.For designs targeting Arria V devices, the
bus width for reconfig_fromgxb and reconfig_togxb are [91:0] and [139:0] respectively.

Table 8: Reset Signals
Reset Signals
rx_clk Output 1 156.25 MHz GMII receive clock.
Active-high reset signal. Resets the logic

reset_rx_clk Input 1
synchronized by rx_clk .
tx_clk Output 1 156.25 MHz GMII transmit clock.

reset_tx_clk Input 1
synchronized by tx_clk .
clk Input 1 156.25-MHz Avalon-MM interface clock.

reset Input 1
synchronized by clk .

Table 9: GMII Signals
GMII Transmit Interface
GMII transmit data bus. When the gmii_tx_en signal

gmii_tx_d[] Input 16 is asserted, the PCS function expects the first valid
byte in the most significant byte on this data bus.
Assert this signal to indicate that the data

on gmii_tx_d[] is valid; gmii_tx_en[0] qualifies the
gmii_tx_en[] Input 2
lower byte of gmii_tx_d[] and gmii_tx_en[1] qualifies
the upper byte of gmii_tx_d[] .
Assert this signal to indicate that the current frame

sent is invalid;. gmii_tx_err[0] indicates error in the
gmii_tx_err[] Input 2 lower byte
of gmii_tx_d[] and gmii_tx_err[1] indicates error in
the upper byte of gmii_tx_d[] .
GMII Receive Interface
GMII receive data bus. The first byte of the data can
gmii_rx_d[] Output 16
reside in any byte.
gmii_rx_dv[] Output 2 When asserted, this signal indicates that the data
on gmii_rx_d[] is valid; gmii_rx_dv[0] qualifies the
lower byte of gmii_rx_d[] and gmii_rx_dv[1] qualifies
the upper byte of gmii_rx_d[] .

This signal stays asserted during the frame

reception, from the first preamble byte until the last
byte in the CRC field is received.
When asserted, this signal indicates that the current

transmit frame is invalid; gmii_rx_err[0] indicates
gmii_rx_err[] Output 2 error in the lower byte
of gmii_rx_d[] and gmii_rx_err[1] indicates error in
the upper byte ofgmii_rx_d[] .
Table 10:MDI Interface Signals
2.5-Gbps MDI Interface Signals
Signal
Name
ref_clk Input 1 125-MHz local reference clock.
Serial receive signal. Must be connected to a

rxp Input 1
differential pin.
Serial transmit signal. Must be connected to a

txp Output 1
differential pin.
Table 11: Avalom MM Signals
Signal
Name
address[] Input 5 Use this bus to specify the register address you want

to read from or write to.
read Input 1 Assert this signal to request a read.
Carries the data to be read from the specified

readdata[] Output 32 register. The register is 16 bits wide; the data read
occupies the lower 16 bits of this bus.
write Input 1 Assert this signal to request a write.
Carries the data to be written to the register. The

writedata[] Input 32 register is 16 bits wide; use the lower 16 bits of this
bus.
When asserted, indicates that the Avalon-MM

interface is unable to respond to a read or write
waitrequest Output 1
request. When asserted, control signals to the
Avalon-MM interface must remain constant.
Table 12: Status Control Signals
Status Control Interface Signals (Part 1 of 2)
10-bit character error. Asserted for 1 rx_clk cycle

led_char_err[] Output 2
when an erroneous 10-bit character is detected.
Asserted when the link synchronization is

led_link[] Output 2
successful.

10-bit running disparity error. Asserted for

1 rx_clk cycle when a disparity error is detected. A
led_disp_err[] Output 2 running disparity error indicates that more than the
previous and perhaps the current received group
had an error.
led_an Output 1 Not used.
Asserted when the tx_clk PLL is stable and in

tx_pll_locked Output 1
phase with the ref_clk .

Table 13: SERDES Control Signals
Calibration block clock for the ALT2GXB

module (SERDES). This clock is typically tied
to the 125 MHz ref_clk. Only implemented
gxb_cal_blk_clk Input 1 when you use an internal SERDES.
This signal is not present in designs targeting

Arria V, and Stratix V and Cyclone V devices
Power-down enable. Assert this signal to

power down the transceiver quad block. This
signal is implemented only when you use an
internal SERDES with the option to export the
gxb_pwrdwn_in Input 1
power-down signal.

pll_powerdown Input 1 This signal powers down a single clock

generation circuit. Assert this signal to power
down the CMU PLLs that provide high-speed
serial and low-speed parallel clocks to the
transceiver channels.


Reference clock for the dynamic

reconfiguration controller. If you use a
dynamic reconfiguration controller in your
design to dynamically control the transceiver,
both the reconfiguration controller and the
MegaCore function require this clock.
reconfig_clk Input 1
This clock must operate between 37.5–50
MHz. Tie this clock low if you are not using an
external reconfiguration controller.

Connects to an external dynamic

reconfiguration controller. The bus identifies
the transceiver channel whose settings are
being transmitted to the reconfiguration
controller. Leave this bus disconnected if you
reconfig_fromgxb[] Output 17 are not using an external reconfiguration
controller.
For designs targeting Arria V, and Stratix V

and Cyclone V devices, the bus width is
[91:0].

reconfiguration controller. Supports the
selection of multiple transceiver channels for
dynamic reconfiguration. Tie this bus to
3’b010 if you are not using an external
reconfig_togxb [] Input 4
For designs targeting Arria V, and Stratix V

and Cyclone V devices, the bus width is
[139:0].
reconfig_busy Input 1 Driven from an external dynamic

reconfiguration controller. This signal

indicates the busy status of the dynamic
reconfiguration controller during offset
cancellation. Tie this signal to 1'b0 if you are
not using an external reconfiguration
controller.

4.3 Register Interface

2.5GMAC register is not revised to cater for future feature enhancement because
the requirement received by engineering group is to maintain the address space
in the design example version 2.3. We have seen 10GMAC had to break the
address space compatibility to support new feature(e.g Priority flow control) and
foresee we would face the same issue with 2.5GMAC in future.
4.3.1 2.5GPHY Register Description

Table 14:PHY IP Register Description
Byte
Register Name Access Description
Offset
Control register. Use the bits in this register to

control and configure the IP core. For the
0x000 control RW
register bits description, see See PCS Control
Register Bit Descriptions.
Status register. Provides information on the

0x004 status RO
operation of the IP core.
0x008 phy_identifier RO 32-bit PHY identification register.

0x00C
0x010 –
Reserved — —
0x03C
Extended Registers
Scratch register. Provides a memory location to

0x040 scratch RW
test register read and write operations.
The IP core revision. Always set to the current

0x044 rev RO
version of the MegaCore function.
0x048 –
Reserved — —
0x04C
0x050 Reserved — —
0x054 –
Reserved — —
0x07C
The upper 16 bits for the databus, readdata and writedata , are always set to

zero.

Table 15:PCS Control Register
Bit(s) Name Access Description
0 to 5 Reserved — —
6 and Reserved — —

13
7 Reserved — —
8 Reserved — —
9 Reserved — —
10 Reserved — —
11 Reserved — —
12 Reserved — —
14 Reserved — —
Setting this bit to 1 generates a synchronous reset pulse

which resets all the IP core state machines, comma
15 RESET RWC detection function and 8B/10B encoder and decoder.
For normal operation, set this bit to 0 (asynchronous
reset value).

Table 16:Status Register Bit Desscription
Status Register Bit Descriptions (Part 1 of 2)
Bit
Name Description
Number
0 Reserved —

1 Reserved —
A value of 1 indicates that a valid link is established. A

2 LINK_STATUS value of 0 indicates an invalid link.
If the link synchronization is lost, a 0 is latched.
3 Reserved —
4 Reserved —
5 Reserved —
6 Reserved —
7 Reserved —
8-15 Reserved —
4.4 2.5GMAC Register Description
4.4.1 Register Description

Table 17: MAC Register Description
Byte
Register Name Access Reset Value Description
Offset
RX Packet Transfer (0x000:0x00F)

Receive path enable.
Bit 0 configures the receive path.

rx_transfer_co 0—Enables the receive path.
0x000 RW 0x0
ntrol 1—Disables the receive path and
drops all receive frames.
Bits 1 to 31 are not used.
Indicates the status of the

rx_transfer_sta receive path.
0x004 RO 0x0
tus 0—The receive path is enabled.
1—The receive path is disabled.
0x008
– Reserved — — Reserved for future use.
0x00F
RX Pad/CRC Remover (0x010:0x01F)
Padding and CRC removal.
Bit 0 configures CRC removal.

0—Retains the CRC field in
receive packets.
1—Removes the CRC field from
receive packets.
rx_padcrc_con Bit 1 configures padding and

0x010 RW 0x1
trol CRC removal.
0—Retains the padding bytes
and CRC field.
1—Removes the padding bytes
and CRC field from receive
packets. The setting of this bit
takes precedence over bit 0.
0x014 Reserved — — Reserved for future use.

–
0x01F
RX CRC Checker (0x020:0x0FF)
CRC checking:
Bit 0—Always set this bit to 0.

rx_crccheck_c
0x020 RW 0x2 Bit 1 configures CRC checking.
ontrol 0—Ignores the CRC field.
1—Checks the CRC field.
0x024
0x0FF
RX Frame Decoder (0x100:0x17F)
Specifies valid frame types,

pause frames handling, use of
supplementary addresses, and
rx_frame_contr
0x100 RW 0x3 length checking.
ol
See See Rx_frame_control
Register for the bit description.
Specifies the maximum allowable

frame length. The IP core
rx_frame_maxl assertsavalon_st_rx_error[3] w
0x104 RW 1518
ength hen the length of the receive
frame exceeds the value of this
register.
0x108 rx_frame_addr RW 0x0 6-byte primary MAC address.

0 You must map the address to the

registers in the following manner:
rx_frame_addr0 = Last four

bytes of the address
Bits 0 to 15 of rx_frame_addr1 =
First two bytes of the address
Example:
If the primary MAC address is
00-1C-23-17-4A-CB,
rx_frame_addr set rx_frame_addr0 to
0x10C RW 0x0
1 0x23174ACB
and rx_frame_addr1 to
0x0000001C.
The IP core uses the primary

MAC address to filter unicast
frames when theen_allucast bit
of the rx_frame_control register
is set to 0.
rx_frame_spad You can specify up to four 6-byte

0x110 RW 0x0
dr0_0 supplementary addresses:
rx_framedecoder_spaddr0_0/1
rx_frame_spad
0x114 RW 0x0 rx_framedecoder_spaddr1_0/1
dr0_1
rx_framedecoder_spaddr2_0/1
rx_frame_spad rx_framedecoder_spaddr3_0/1
0x118 RW 0x0
dr1_0
You must map the
supplementary addresses to the
rx_frame_spad respective registers in the same
0x11C RW 0x0
dr1_1 manner as the primary MAC
address. See the description
of rx_frame_ addr0
rx_frame_spad andrx_frame_ addr1.
0x120 RW 0x0
dr2_0
The IP core uses the
supplementary addresses to filter
0x124 rx_frame_spad RW 0x0 unicast frames when the

dr2_1
rx_frame_spad
0x128 RW 0x0
dr3_0
following conditions are set:

rx_frame_spad The use of the supplementary
0x12C RW 0x0
dr3_1 addresses are enabled using the
respective bits in
therx_frame_control register
0x130
0x17F
RX Packet Overflow (0x180:0x1FF)
0x180 36-bit error counter that collects

0x0 the number of receive frames
that are truncated when FIFO
buffer overflow persists:
rx_pktovrflow_
RO The first 32 bits occupy the
error
register at offset 0x180.
0x184 0x0 The last 4 bits occupy the first
four bits of the register at offset
0x184. Bits 4 to 31 are unused.
0x188 rx_pktovrflow_ RO 0x0 36-bit error counter that collects

etherStatsDrop the number of receive frames
Events that are dropped when FIFO
0x18C 0x0 buffer overflow persists:
The first 32 bits occupy the

register at offset 0x188
The last 4 bits occupy the first


0x18C. Bits 4 to 31 are unused.

0x190
0x1FF
TX Packet Transfer (0x200:0x20F)
Backpressure enable.
Bit 0 configures backpressure.

0—Disables backpressure.
tx_transfer_co 1—Enables backpressure on the
0x200 RW 0x0
ntrol Avalon-ST transmit interface.
The IP core deasserts
the avalon_st_tx_ready signal.
Indicates if backpressure is
enabled on the Avalon-ST
tx_transfer_sta
0x204 RO 0x0 transmit interface.
tus
0—Backpressure is disabled.
1—Backpressure is enabled.
0x208
0x20C
TX Pad Inserter (0x210:0x21F)
0x210 tx_padins_cont RW 0x1 Padding insertion.

rol 0—No effect on transmit frames.
1—Inserts padding bytes into
transmit frames until the frame
length reaches 60 bytes. To
achieve the minimum 64 bytes,
ensure that the CRC field is

inserted
(seetx_crcins_control ).
TX CRC Inserter (0x220:0x25F)
CRC insertion.
Bit 0—Always set this bit to 1.
tx_crcins_cont Bit 1 configures CRC insertion.

0x220 RW 0x3
rol 0—Disables CRC insertion.
1—Computes CRC and inserts it
into transmit frames.
TX Pause Frame Control and Generator (0x260:0x27F)
0x260 tx_pauseframe RW 0x0 Pause frame generation.

_control
Bit 0 configures the generation of
XON pause frames.
0—Disables pause frame
generation.
1—Generates a pause frame
with a pause quanta value of 0.
Bit 1 configures the generation of

XOFF pause frames.
0—Disables pause frame
generation.
1—Generates a pause frame
using the pause quanta specified
in
thetx_pauseframe_quanta regis
ter.
If both bits 0 and 1 are set to 1,

the IP core does not generate

any pause frames.
16-bit pause quanta. The IP core

tx_pauseframe uses this value when it generates
0x264 RW 0x0
_quanta XON pause frames. Bits 16 to 31
are reserved.
0x268
0x27C
TX Address Inserter (0x280:0x29F)
Address insertion on transmit.
Bit 0 configures address

insertion.
0—Disables address insertion on
transmit.
tx_addrins_co
0x280 RW 0x0 1—Overwrites the source
ntrol
address field of transmit frames
with the address configured in
the tx_addrins_macaddr0 and t
x_addrins_macaddr1 registers.
tx_addrins_ma 6-byte MAC address. You must

0x284 RW 0x0
caddr0 map the address to the registers
in the following manner:
0x288 tx_addrins_ma RW 0x0 tx_addrins_ macaddr0 = Last

caddr1 four bytes of the address
Bits 0 to 15
of tx_addrins_ macaddr1 = First
two bytes of the address
Example:
If the primary MAC address is

00-1C-23-17-4A-CB,
set tx_addrins_ macaddr0 to
0x23174ACB
and tx_addrins_ macaddr1 to
0x0000001C.
The IP core writes this address

TX Frame Decoder (0x304)
16-bit maximum length for

transmit frames. The IP core
tx_frame_maxl
0x304 RW 1518 uses this value to determine
ength
oversized frames on the transmit
path for statistics collection only.
TX Packet Underflow (0x380:0x39F)
0x380 36-bit error counter that collects

the number of transmit frames
that are truncated when FIFO
buffer underflow persists.
tx_pktunderflo
RO 0x0 The first 32 bits occupy the
w_error
register at offset 0x380.
0x384
The last 4 bits occupy the first
0x384. Bits 4 to 31 are not used.
0x388
0x39F

RX Statistics Counters (0x400:0x5FF)—Collect statistics on the receive path.

Prefixed with rx_.
TX Statistics Counters (0x600:0x7FF)—Collect statistics on the transmit path.
Prefixed with tx_.
Set this register to 1 to clear all

0x400 rx_stats_clr RWC 0x0 statistics counters for the receive
path.
Set this register to 1 to clear all

0x600 tx_stats_clr RWC 0x0 statistics counters for the
transmit path.
0x404
Reserved — Reserved for future use.
0x604
rx_stats_frame
0x408
sOK The number of frames that are
successfully transmitted or
RO 0x0
received, including control
tx_stats_frame frames.
0x608
sOK
rx_stats_frame
0x410
sErr(1)
The number of errored frames
RO 0x0 that are transmitted or received,
including control frames.
tx_stats_frame
0x610
sErr(1)
rx_stats_frame RO 0x0 The number of transmit or

0x418
sCRCErr receive frames with only CRC
error.
0x618 tx_stats_frame

sCRCErr
rx_stats_octets
0x420
OK The number of data and padding
octets that are successfully
RO 0x0
transmitted or received, including
tx_stats_octets control frames.
0x620
OK
rx_stats_pause
0x428 MACCtrl
Frames
The number of valid pause
RO 0x0
frames transmitted or received.
tx_stats_pause
0x628 MACCtrl
Frames
rx_stats_ifErro
0x430
rs
The number of errored and
RO 0x0 invalid frames transmitted or
received.
tx_stats_ifErro
0x630
rs
rx_stats_unica
0x438
st FramesOK The number of good unicast
frames that are successfully
RO 0x0
transmitted or received,
tx_stats_unica excluding control frames.
0x638
st FramesOK
rx_stats_unica RO 0x0 The number of errored unicast

0x440 st frames transmitted or received,
FramesErr(1) excluding control frames.
0x640 tx_stats_unica
st

FramesErr(1)
rx_stats_multic
0x448
ast FramesOK The number of good multicast
frames that are successfully
RO 0x0
transmitted or received,
tx_stats_multic excluding control frames.
0x648
ast FramesOK
rx_stats_multic
0x450 ast
FramesErr(1)
The number of errored multicast
RO 0x0 frames transmitted or received,
excluding control frames.
tx_stats_multic
0x650 ast
FramesErr(1)
rx_stats_broad
0x458
cast FramesOK
The number of good broadcast
tx_stats_broad
0x658
cast FramesOK
rx_stats_broad
0x460 cast
FramesErr(1)
The number of errored broadcast
tx_stats_broad
0x660 cast
FramesErr(1)
rx_stats_ether RO 0x0 The total number of octets

0x468
Stats Octets transmitted or received. This
count includes good, errored,
and invalid frames.
0x668 tx_stats_ether

Stats Octets
rx_stats_ether
0x470
StatsPkts
The total number of good,
RO 0x0 errored, and invalid frames
transmitted or received.
tx_stats_ether
0x670
StatsPkts
rx_stats_ether
0x478 Stats
UndersizePkts The number of undersized
frames (frame length less than
RO 0x0
64 bytes) transmitted or
tx_stats_ether received.
0x678 Stats
UndersizePkts
rx_stats_ether
0x480 Stats
OversizePkts The number of oversized frames
(frame length more
RO 0x0
than rx_frame_maxlength )
tx_stats_ether transmitted or received.
0x680 Stats
OversizePkts
rx_stats_ether
0x488 Stats The number of 64-byte transmit
Pkts64Octets or receive frames, including the
CRC field but excluding the
RO 0x0
preamble and SFD bytes. This
tx_stats_ether count includes good, errored,
0x688 Stats and invalid frames.
Pkts64Octets
0x490 rx_stats_ether RO 0x0 The number of transmit or

Stats receive frames between the
Pkts65to127Oc length of 65 and 127 bytes,

tets
including the CRC field but
excluding the preamble and SFD
tx_stats_ether
bytes. This count includes good,
Stats
0x690 errored, and invalid frames.
Pkts65to127Oc
tets
rx_stats_ether
Stats
0x498 The number of transmit or
Pkts128to255O
receive frames between the
ctets
length of 128 and 255 bytes,
RO 0x0 including the CRC field but
tx_stats_ether
Stats
0x698 errored, and invalid frames.
Pkts128to255O
ctets
rx_stats_ether
Stats
0x4A0 The number of transmit or
Pkts256to511O
ctets
tx_stats_ether
Stats
0x6A0 errored, and invalid frames.
Pkts256to511O
ctets
rx_stats_ether
Stats
0x45A8 The number of transmit or
Pkts512to1023
Octets
tx_stats_ether
Stats
0x6A8 errored, and invalid frames.
Pkts512to1023
Octets

rx_stats_ether
Stat
0x4B0 The number of transmit or
Pkts1024to151
8Octets
tx_stats_ether
Stat
0x6B0 errored, and invalid frames.
Pkts1024to151
8Octets
rx_stats_ether
The number of transmit or
Stats
0x4B8 receive frames between the
Pkts1519toXOc
length of 1519 and the value
tets
configured
RO 0x0 in rx_frame_maxlength ,
including the CRC field but
tx_stats_ether
Stats
0x6B8 bytes. This count includes good,
Pkts1519toXOc
errored, and invalid frames.
tets
rx_stats_ether
0x4C0 Stats
The total number of transmit or
Fragments
receive frames with length less
RO 0x0 than 64 bytes and CRC error.
This count includes errored and
tx_stats_ether
invalid frames.
0x6C0 Stats
Fragments
rx_stats_ether The number of oversized

0x4C8
Stats Jabbers transmit or receive frames (frame
length more
RO 0x0
thanrx_frame_maxlength ) with
tx_stats_ether CRC error. This count includes
0x6C8
Stats Jabbers invalid frame types.
0x4D0 rx_stats_ether RO 0x0 The number of transmit or

Stats CRCErr receive frames between the

length of 64 and the value
configured in
the rx_frame_maxlength registe
tx_stats_ether r with CRC error. This count
0x6D0
Stats CRCErr includes errored and invalid
frames.
rx_stats_unica
0x4D8 stMAC
CtrlFrames
The number of valid unicast
RO 0x0 control frames transmitted or
received.
tx_stats_unica
0x6D8 stMAC
CtrlFrames
rx_stats_multic
0x4E0 astMAC
CtrlFrames
The number of valid multicast
received.
tx_stats_multic
0x6E0 astMAC
CtrlFrames
rx_stats_broad
0x4E8 castMAC
CtrlFrames
The number of valid broadcast
received.
tx_stats_broad
0x6E8 castMAC
CtrlFrames
0x47C Reserved — — Reserved for future use.

–
0x5FF

0x67C
–
0x7FF
(1) The number of undersized frames received or transmitted in not

incremented for this register. This is due to the limited processing time
when undersized frames are received or transmitted.

Table 18: FrameDecoder Control Register
Reset
Bit Field Name Width Access Description
Value
0—Filters unicast receive frames

using the primary MAC addresses.
0 EN_ALLUCAST 1 RW 0x1
1—Accepts all unicast receive
frames.
0—Drops all multicast frames.

1 EN_ALLMCAST 1 RW 0x1
1—Accepts all multicast frames.
2 Reserved 1 — — Reserved for future use.
This bit affects all control frames

except pause frames.
FWD_CONTRO
3 1 RW 0x0 0—Drops control frames.
L
1—Forwards control frames to the
user application.
4 FWD_PAUSE 1 RW 0x0 0—Drops pause frames after

processing them.

1—Forwards pause frames to the

user application.
0—Suspends transmission for the

value specified by the pause quanta
IGNORE_PAUS
5 1 RW 0x0 in the pause frame received.
E
1—Ignores pause frames.
0—Checks the actual payload length

of receive frames against the
length/type field. If the length does
NO_LGTH_CHC
6 1 RW 0x0 not match the field, the IP core
K
asserts avalon_st_rx_error[4] .
1—Skips payload length checking.
7–
Reserved — — — Reserved for future use.
15
0—Disables the use of

supplementary address 0.
16 EN_SUPP0 1 RW 0x0
1—Enables the use of




20 –
Reserved — — — Reserved for future use.
31
5 Documentation
Refer to reference section.
6 Implementation Details
Will be updated while development in progress
7 Testing
7.1 Functional verification
7.1.1 PHY Layer
SV-VMM methodology will be used to verify the 2.5Gbps Ethernet together with
the Nsys VIP SV-VMM environment verification setup. Refer to Figure 6.

Figure 6 SV-VMM setup using VIP’s testbench & Environment
Address swapper and CRC inserter module will work to swap the destination
address of the packets from BFM into the source address, and the destination
address of the transmitted packet will be hardcoded value of the address that we
set for the VIP. This module will work to discard the the FCS CRC from the BFM
and append wit h the correct value to be send back to the BFM.
Verification will be run using testcases that are provided by VIP, included
compatibility tests, error tests and basic tests.
Functional coverage in various cover group will be covered in a VMM planner.
Packets that are to be transmitted are as the following:-
i) Data packets.
ii) VLAN packets
iii) Stacked Vlan packets
iv) Pause Frame packets.
v) Jumbo Packets.
Packets should conform to the specifications of MAC frame format.
Verification for PHY layer will need to be pass the Random tests and also
Directed tests provided by the VIP.
A SV-VMM using Altera VIP also will be used to cover functional coverage that
may not be covered in the Nsys setup. Refer to Figure 7.
Figure 7 PHY extended verification environment.

As 2.5Gbps is not an industry standard, Nsys will provide us with a solution in

configuring its’ core to work in 2.5Gbps.
7.1.2 MAC+PHY Verification
To verify the MAC+PHY solution, the VIP SV vmm verification environment will
be used. Refer to Figure 8.
Figure 8 MAC+PHY Verification solution
A loopback mechanism will be used to verify the MAC+PHY layer. Packets that
are transmitted by the BFM needs to be received by the BFM to check for
correctness of the packets transmitted.
Verification for PHY layer will need to be pass the Random tests and also
Directed tests provided by the VIP.
Packets that are to be transmitted and tested are as the following:-
i) Data packets.
ii) VLAN packets
iii) Stacked Vlan packets
iv) Pause Frame packets.
v) Jumbo Packets.
If the functional coverage using the VIP setup is not sufficient to cover all the
functional coverage of the DUT, an extra environment consists of self-developed
VMM utilities will be used to cover those areas. Figure 9 shows the environment
setup.

Figure 9 MAC Standalone verification environment.
7.1.3 Micro Core
There are two micro cores in the 2.5Gbps Etherenet that will be verified using
SV-VMM methodology.
7.1.3.1 Lane Decoder
Lane decoder will be tested and verified using the SV-VMM verification
environment. The current setup/environment to test this module will be as in
Figure 10.
Figure 10 Lane decoder SV VMM verification environment

7.1.3.2 Lane Encoder
Lane Encoder inside the MAC layer will be tested using the SV-VMM
methodology as well. The setup of the environment will be as in Figure 11.
Figure 11 Lane Encoder SV-VMM verification environment.
Describe the high-level test methodology and test support you’ll create, which is
also an important design consideration. This is not the test plan, which is
detailed in a separate test-plan document.
8 References
//depot/users/aishak/duxi_new_deliverable/design_example_sopc_2_5GbE/
design_example_sopc_2_5GbE_1_9/2.5GbpsEthernetIP.pdf
http://www.altera.com/literature/ug/10Gbps_MAC.pdf

2.5gbe Mac and Phy Megacore: Swip Functional Description

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2.5gbe Mac and Phy Megacore: Swip Functional Description

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5GbE MAC and PHY Megacore

Altera Corporation Confidential

FIGURE 1: ALTERA ETHERNET 2.5GB DESIGN EXAMPLE COMPONENTS...............................................4

Altera Corporation Confidential Page 2 of 51

Altera Corporation Confidential Page 3 of 51

3) Altera Ethernet 2.5Gb Design Example( 2.5GMAC+2.5GPHY+Avalon-ST

Supported flow is Megawizard only.

Figure 1: Altera Ethernet 2.5Gb Design Example Components

Altera Corporation Confidential Page 4 of 51

Figure 2 : 2.5Gbps Ethernet MAC

2.5GMAC is a composed hardware tcl component and most of the sub-

The 2.5GMAC supports the following features:

 Virtual local area network(VLAN) and stacked VLAN tagged frames

Altera Corporation Confidential Page 5 of 51

 Optional cyclic redundancy code (CRC)-32 computation and insertion on

 Checking of received frames for CRC error,undersized and oversized

 Programmable maximum length of receive frames up to 64Kbytes(KB)

 Programmable promiscuous (transparent) mode

 Optional padding termination on the receive datapath and insertion on the

Altera Corporation Confidential Page 6 of 51

Figure 3 : 2.5Gbps Ethernet PHY

Supported parameter option for this design example includes:

(1) Configuration types of “MAC and PHY” or “PHY only”

(3) Transmiter DC FIFO depth

Altera Corporation Confidential Page 7 of 51

(4) Receiver DC FIFO depth

3.1.1 2.5GMAC Core

This core is a composition of smaller components and most of the components

3.1.2 Avalon-ST Dual Clock Fifo

For details, please refer to document.

We do not support any parameter option for this core.

3.1.3 Avalon MM Pipeline Bridge

We do not support any parameter option for this core.

For details, please refer to section 4.2 of this document.

We do not support any parameter option for this core.

3.2 Family Support

(1) Stratix IV GX/GT

Altera Corporation Confidential Page 8 of 51

(3) Arria V GX/GT

(4) Arria V SOC

(5) Stratix V GX/GT

(6) Cyclone V GX/GT

(7) Cyclone V SOC

The name of 2.5GbE GUI is “Altera Ethernet 2.5Gb Design Example”.Megacore

(1) General Configuration which shows the selected device family(not

(2) PHY Configuration to edit starting channel number.

(3) DC FIFO configuration

This core will not support post-fit gate level simulation.

3.4 Backward compatability

(2) Remove defparam for starting_channel_number in top.v file. This

(3) Regenerate design using qmegawizard into same directory.The name of

Altera Corporation Confidential Page 9 of 51

(6) Upgrading to Arria V, Stratix V or Cyclone V require interface changes.

3.5 Quartus Support

3.5.2 Pin Planner

2.5GbE Megacore does not support pin planner.

3.5.3 QIC compliant

3.5.4 Design assistant

3.5.5 QIS Warning

Will be ensured free from metastability issue.

3.5.7 QIP file

qip file is generated by hw_tcl