UuM_Mc ®ume UM6114 1K X 4 CMOS SRAM Features 1 Single +5 volt power supply = Access time: 90 ns (max.) = Current . Operating: 30 mA (max.) Standby: 5 WA (max.) ‘= Fully static operation, no clock or refreshing required Directly TTL compatible: All inputs and outputs ‘Common 1/0 using three-state output Data retention voltage: 2V (min,) ‘Available in 18 pin DIP package ee General Description The UMG114 is a 4,096 bit static random access memory The UM6114 SRAM is a full CMOS SRAM, making it organized as 1,024 words by 4 bits and operates on a single S.volt power supply. It is built using UMC’s high performance CMOS process suitable for use in low power applications where battery ‘operation and battery back up for nonvolatiity are re- quires Inputs and three-state outputs are TTL compatible and Data retention is guaranteed at @ power supply voltage allow for direct interfacing with common system bus as low as 2V, structures Pin Configuration Block Diagram = aUM6114 Recommended DC Operating Conditions (7, 20°C 10 70°CI es ‘Symbol | Parameter | Min.| Typ. | Max. | Unit \ddress Input ‘Suppl | Ns * Voc | SuPY | a5 | 50 | 5 v weir Rel Conia uh ao seme | o 7 z Ch Erabe = Gs ; moreno} mw | ae | 22 | 38 v 0; WO, | Oss ireulOue | we, | Vee owe pp 8 = t— ve | tee [os] o Jos] v cND Grond en, ~[ Output 7. lace Load oe ® Daina | we | -[-[[ - Absolute Maximum Ratings * *Comments Vee 6ND -a5vws70v —Suenes wove tose lied under “Abrlute Nexium Raneauevneene osvievecasy aime” ay case gue eimge te tne. Operating Temperature. Top, ocr" | The a ie P this device at these or any other conditions above those Storage Temperature, Teg 58°C 10 #125°C indicated in the operational sections of this specification Temperature Under Bias, Tyise =10°C10 486°C is not implied and exposure 10 absolute maximum rating Power Dissipation, Py raw conditions for extended periods may affect device re- liability DC Electrical Characteristics (T., V + 10%, GND = OV) ‘Symbol Parameter ‘Min. | Max Unit | Test Conditions hu Input Leakage Current = 1 HA Vin IND 10 Veg GE = Vy oF RAT Vy, hol Output Leakage Current 1 A Von eNO Ion ‘Active Power tcc Supply Current z cu ee [ Ira] Dynamic Operating Current 300) oma eon nee Oma 'ss - 1 mA | Standby Powe! rT ‘ses Supply Current 5 uA Output Low Voitage 04 v Output High Voltage 24 : v 2-10Oume um6114 Truth Table Mode cE aw WO Operation Veo Current Standby H x High Z | gg. 'sa1 ead L 4 Pour Nees tees ws L 7 Di Ice leer Note: X:H or t Capacitance (T., = 28°C. f= 10MHe Symbol Parameter Min Max. Unit "Test Conditions Cw Input Capacitance 6 oF Vin =O Gio? __|_IapuviOutput Capacitance 8 PF Vig = 0 "This parameter is sampled and not 100% tested (Tq = 0°C 10 470°C, Voc = BV # 10%) ‘Symbol I Parameter Min. ‘Max. Unit es = RsaoeaTis a : i vee cera aca : a i = Chip Ena accu Tr : 5 a a Chip Erb wo outpin ow 5 = cour | eR Dib Ouutin RZ a z a = Cut Hae Pom Aon Chee n : = aon tue Write Cycle Time 20 7 ns ce cn Saueipeaie wr 5 = 5 [tas | Address Setup Time Loe = ns a Fs Vato Eo of We i : we _=a Write Pulse Width — = . oon nS ° D — naam ORT 7 7 a [tow | Data to Write Time Overlap 20 = 7s = ‘Dane oid trom Wrie Tine 7 = ve [eu oe 3 = os Notes: touiz and twuz ate defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage fevelsume ume114 Timing Waveforms Feead Cycle 1!) Across Pour Read Cycle 27-3) Notes: 1 RAVIs High for ac Cycle 2 Device is continuously selacted, TE * V1. 4. Address valid prior to or coincident with TE transition low 4 This parameter is sampled ana not 100% tested ‘Timing Waveforms Write Cycle ite Cycle 1 — Cr AcrossOume um6114 Wie Cycle 2 —— _ oe = ae SSS vow eles 6 oy ————— rere Nowe 1. tag is measured from the address valid to the beginning of write A write occurs during the overlap (twp) of alow CE and 2 low RIV. 2 3. tym ismeasured from the earlier of CE or RM acing high to the and of write cycle 4 During this period, 1/0 pins are in the output state £0 that the input signals of apposite phase ta the outputs must not be applied, 5. If the CE low transition occurs simultaneously with the RAW low transition or atter the RAV transition, outputs re ‘main in a high impedance state 6. Dout is the same phase of write data for this write cycle. 7. Doutiis the read data of noxt address 8. 11 CE is low during this period, 1/0 pins are in the output sta the data input signals of opposite phase to the outputs ‘must not be applied 10 1/0 pin, 9. This parameter is sampled and not 100% tested : AC Test Conditions oy vy $re00 & reco Input Pulse Levee av w22v Input Rise and Fal Times [Ss c “— Input and Ousput ales al Stoop zon 2 50F° Timing Reference Levels | _1.5¥ e200 x08 Ourut Load Seo Fig 1,2 dt ieee "Including scope and jig "Including scope and jig Figure 1. Output Load Figure 2. Output Load for texz: tone: twne- tow Data Retention Characteristics (1, - 0°C 10 70°C) Symbol Parameter Max. ] Unit st Conditions Von Veg for Bata Retention = v 3 Veo = 020 ‘econ Data Retention Current - aA Neo © 30N. CE > Voc ~02V Vin ® Voc ~0.2V or Vig © 02 Chip Disable to Data ‘con Retention Time ° as ns a Retention Waveform ‘a Operation Recovery Time | tact = | tae = Read Cycle TimeOume um6114 Low Voc Data Retention Waveform ata tention Mode 14] 3 108] i ¥ 13] 4 | a 00}— 0 ra E _ | | | vasl 1 o |