MICROCONTROLLER MODULE

MODULE 5
CST 307 : Microprocessors &

Microcontrollers
Syllabus- Module 5 2
Microcontrollers
 8051 • Arithmetic instructions
• Logical instructions
o Architecture
• Boolean instructions
o Register Organization
• Control transfer instructions
o Memory and I/O addressing
 Simple programs.
o Interrupts and Stack
o 8051 Addressing Modes
o Instruction Set
• Data transfer instructions
MICROCOMPUTERS 3
 A microcomputer is a circuit or VLSI core that functions as a computer and

consists of at least the following sections. It consists of the following:
o Microprocessor
o Memory for the data (bits, bytes and words) and stack
o Memory for storing the dedicated programs and subprograms
o Interfacing circuit between the external memories and IO devices
o Interrupt handling circuit or unit to handle the system interrupts
o Timing circuit or unit for the system clock and other timing-related functions
Inside the Computer 4
Inside the Computer 5
Inside the CPU 6
MICROCONTROLLERS 7
 A microcontroller is a microcomputer with few other application-

specific devices on a single chip or VLSI core.
 It has the specified computational capabilities as well as the enhanced
IO operation and control capabilities.
 It is an integrated part in a real-time control or communication system.
 Henceforth, a microcontroller will also be referred to as MCU.
o An MCU consists of a microcomputer circuit or unit may have a provision to
run in a power-down or idle mode.
MICROCONTROLLERS 8
 An MCU also consists a few or many of the following devices.

o Port devices: There may be bit-manipulation instructions which process by CPU of
the MCU. This enables control of the interfaced relays and switches
o Devices for the synchronous and asynchronous serial IO
o Timer device. This enables the functioning of the system clock, real-time clock and
software timer(s). It enables real-time detection of an event or signal (compare the
time or capture the time on an event). A timer device can function also as a
watchdog timer device
o Device pulse width modulation (PWM). This enables digital to analog conversion
(DAC).
MICROCONTROLLERS 9
o Device for analog to digital conversion (ADC)
o Modem which is a device to enable external communication
o Digital signal processing (DSP) [DSP instructions may be at the CPU]
o Ports which can enable processing by non-linear control instructions
o Ports can have network interface and the CPU can process instructions
related to the network processing
o Ports can have wireless interface.
o USB/ PCI/ I2C/ CAN/ JTAG/ SDIO (Secure Data IO) interfacing devices
10
Microprocessors vs. Microcontrollers 11
 General-purpose microprocessors
o Must add RAM, ROM, I/O ports, and timers externally to make them functional
o Make the system bulkier and much more expensive
o Have the advantage of versatility on the amount of RAM, ROM, and I/O ports
 Microcontroller
o The fixed amount of on-chip ROM, RAM, and number of I/O ports makes them
ideal for many applications in which cost and space are critical
o In many applications, the space it takes, the power it consumes, and the price per
unit are much more critical considerations than the computing power
MICROPROCESSORS AND MICROCONTROLLERS 12
MICROPROCESSORS AND MICROCONTROLLERS 13
MICROPROCESSORS MICROCONTROLLERS
Microprocessor contains ALU, General purpose Microcontroller contains the circuitry of 14
registers, stack pointer, program counter, clock microprocessor, and in addition it has built in
timing circuit, interrupt circuit ROM, RAM, I/O Devices, Timers/Counters etc.
It has many instructions to move data between It has few instructions to move data between
memory and CPU memory and CPU
Few bit handling instruction It has many bit handling instructions
Less number of pins are multifunctional More number of pins are multifunctional
Single memory map for data and code (program) Separate memory map for data and code
(program)
Access time for memory and IO are more Less access time for built in memory and IO.
Microprocessor based system requires additional It requires less additional hardwares
hardware
More flexible in the design point of view Less flexible since the additional circuits which is
residing inside the microcontroller is fixed for a
particular microcontroller
Large number of instructions with flexible Limited number of instructions with few
addressing modes addressing modes
15
16
Characteristics and Resources of a

microcontroller
On Chip Resources of a microcontroller 17
1. Basic processing unit, internal buses and interrupt handler
2. On-chip program memory, Internal EEPROM and Flash
3. On-chip RAM
4. Interfacing capability to external program memory
5. Interfacing capability to external data memory
6. Ports
7. On-chip registers
8. Special function registers-SFR
9. UART
10. Serial synchronous
11. Timers/counters
12. Pulse width modulator (PWM)
13. On-chip ADC

14. Watchdog timer
15. Bitwise manipulation capability
16. Power-down mode
17. Real-time clock

MODULE 5

Microcontrollers
Microcontrollers
o Architecture
o Instruction Set
22
8051 23
Characteristics of 8051 microcontroller 24
 8 bit CPU:ALU can perform arithmetic and logic functions on 8 bit variables.
 On chip clock oscillator
 4Kbytes of internal program memory (code memory) [ROM]
 128 bytes of internal data memory [RAM]
 64 Kbytes of external program memory address space.
 64 Kbytes of external data memory address space.
 32 bi-directional I/O lines
o can be used as four 8 bit ports or 32 individually addressable I/O lines
 Two 16 Bit Timer/Counter :T0, T1
 Full Duplex serial data receiver/transmitter
 4 Register banks with 8 registers in each bank.
 16 bit Program counter (PC) and a data pointer (DPTR)
 8 Bit Program Status Word (PSW)
 8 Bit Stack Pointer
 5 vector interrupt structure (RESET not considered as an interrupt.)

 8051 CPU consists of 8 bit ALU with associated registers like

o accumulator ‘A’
o B register
o PSW
o SP
o 16 bit program counter
 8051 has 128 bytes of internal RAM which is divided into

o Working registers [00 – 1F]
o Bit addressable memory area [20 – 2F]
o General purpose memory area (Scratch pad memory) [30-7F]

MODULE 5

Microcontrollers
Microcontrollers
o Architecture
o Instruction Set
8051 Architecture 29
 The 8031 and 8051 microcontrollers are similar in their architecture.

• 8031 does not have internal program memory.
• All the program memory needed is interfaced to external ROM/flash in 8031.
 Ports P0 and P2 are used for interfacing to the external memory.

 8051 has internal program memory.
o 4 kB of internal program memory is present in Classic 8051 family MCUs.
 New variants of the classic 8051 are 8052, extended and MX variants.
They have additional resources.
 The characteristic features of a  The 8051 has

microcontroller are the existence of o The processor
o Internal memory devices o ROM (read only memory)
o Serial interface device o Interrupt control circuit
o Timing device o Internal timing devices (timers TO and T1)
o Interrupt-handling circuit and o Serial interface (SI)
o Other application-specific devices. o RAM
o Special function registers (SFRs) and
o Four ports, P0, P1, P2 and P3.

Features of 8051 31
 An 8051 can be used as a single-chip microcomputer with embedded program in ROM or flash.
o The ROM is 4 kB in 8051 (it is 8 kB or 16 kB in certain variants).
• An 8031 core does not have ROM.
 An 8051 can be used in the expanded mode also.

o Expanded mode means use of address and data bus signals.
o Single-chip mode means use of internal devices and circuitry only.
 Each program needs the temporary variables.

o 8051 has 128 B RAM.
o Also there are a number of special function registers (SFRs).
 Each program needs a stack. The 8051 has a stack pointed out by the byte at a special function
register. SP (stack-pointer) is 8-bit register.
Features of 8051 32
 Each program needs a stack.

o The 8051 has a stack pointed out by the byte at a special function register.
o SP (stack-pointer) is 8-bit register.
 There is a program counter (PC) lower byte of it is sent at the bus A0–A7.
o The A0–A7 bus pins are also common to the data bus D0–D7.
o These 8 pins are used in the expanded mode.
o The pins are also common to that of the Port P0 latch and these pins have signals of
Port P0 in single-chip mode.
Features of 8051 33
 There is a program counter (PC) higher byte at bus A8–A15.
o The A8– A15 bus pins are used in the expanded chip mode.
o These are common with the Port P2.
o The same pins are used as port P2 in the single-chip mode and A8–A15
bus signals in the expanded mode.
 A microcontroller can be connected to I/O devices (using ports).

Features of 8051 34
 There are 2 external pins for interrupts INT0 and INT1.

o There is interrupt control circuit for the 8051 interrupt service mechanism.
o Two SFR are used for priorities and masks.

• IP (interrupt priority) and
• IE (interrupt enable)
 There are 2 programmable timers/event counters to do real-time

control of events and tasks
o T0 and T1.
1. 8051 processes instructions and has an 8-bit ALU. 8. Special function registers are
2. Extended and single-chip modes. i. PSW
3. ROM 4 kB in 8351 ii. A, B
o EPROM 4 kB in 8751 and iii. IE, IP
o EEPROM/flash 4 kB in 8951 iv. SCON
4. RAM 128 B. v. TCON
vi. SMOD
5. Two external interrupts through INT0#, INT1# and
pins. vii. SBUF
6. Two timer/event counters, T0 and T1. viii. PCON
ix. TL0, TH0, TL1, TH1

7. Serial interface.
x. P0, P1, P2, P3 and SP.
 8051 processing unit has following circuits

1. Control and sequencing logic
2. Oscillator for generating clock
3. Reset circuit
4. ALU
• ALU does arithmetic and logic operations on the operands.
• Operand means a number on which the operations are done.

• For example in add operation A + B, A and B are the operands.
- The uses of Subunits and signals
Symbol Full Form Use
• 16-bit
• address pointer
• holds the program memory address of the instruction currently being fetched.
PC Program counter • Increments continuously to point to the next instruction.
• The PC consists of 2 bytes
• PCH (higher) and
• PCL (lower).
• 16-bit address pointer

• holds the external data memory address of the data being currently fetched or
to be fetched.
Data pointer • The data is fetched using DPTR in indirect addressing mode
DPTR
register • points to the memory address from where data can be accessed
• The DPTR consists of two bytes
• DPH (higher) and
• DPL (lower).
• 8-bit register
• Saves an operand for operations by ALU.
A Accumulator
• Act as an operand in data transfer operation using the A.
• important function is to accumulate the result after an ALU operation.
• 8-bit register
B B register • Saves a second operand for the ALU
• Also accumulates part of the result of multiplication or division.
• A unit to perform an arithmetic or logic operation at an instance as per

Arithmetic logic
ALU instruction executed.
unit
• It gives the result(s).
• 8-bit register to save the status and state flags (bits).

Processor status
PSW • For example, the flag carry
word
• 8-bit port P0 is for the I/Os in a single-chip mode

P0 Port P0 • For the data bus-cum-lower order address signals AD0- AD7 in the expanded
mode.
• 8-bit port P2 is for the I/Os in a single-chip mode and

P2 Port P2
• For the higher order address signals A8-A15 in the expanded mode.
• 8-bit port P2 is for the I/Os in a single-chip mode.

P1 Port P1 • Its pins are also used for few interfacing signals in certain 8051 family variants
in the expanded mode.
• 8-bit port P3 is for the I/Os in a single-chip mode.

• It is also used for the serial interface (SI) signals.
• P3 pins are also used for the timer T0 and T1 inputs, and interrupts INT0# and
P3 Port P3
INT1# inputs.
• P3 pins are also used for sending RD# and WR signals for the memory read-
write in the expanded mode
• Serial device is for the serial I/O operations

• One bit is present in one pre-fixed time slot.
• A mode is full-duplex UART- input as well as output using 2 pins at an instance.
SI Serial interface • Set of two pins of P3 are used as, RxD and TxD.
• Alternatively, SI is used for the half duplex synchronous communication of bits
through same set of pins. Input or output at an instance.
• Two pins of P3 used for DATA and CLOCK.
• Timing devices in 8051 family.

TO and T1 Timers T0 and T1
• It has four registers
• TH1, TH0, TL1 and TL0.
• Registers SP, PSW, A, B, IE, IP, P0, P1, P2, P3, SCON, TCON, SMOD, SBUF, PCON,
Special function • TL0,TH0,TL1,TH1 are called SFRs.
SFRs
registers • These are at directly addressable memory.
• SFR address must be directly specified in the instruction and not through a pointer
register.
Read only • Masked ROM, EPROM or flash EEPROM of 4 kB in 8051 classic family
• (or 8 kB or 16 kB in 8051 family variants).
ROM program
• Internally connects to PC by bus of 12
memory • (or 13 or 14) bits in 4 or 8 or 16 kB versions, respectively.
Internal random • RAM is 128 B memory for the read and write
Internal RAM
access memory • Indirectly as well as directly addressable.
• A RAM address is between 0x00 and 0x7F.
Register Four set of

• Four register banks each of 8 registers and these are also part of the internal
banks registers
RAM.
XTAL1 and Pins to the • Pins to the crystal in the oscillator circuit
XTAL2 crystal • about 12 MHz crystal used in classic 8051
• To enable use of external memory addresses to external ROM in place of the

ones inside.
EA# External enable
• The use is during development phase of the codes for the internal program
memory
• Reset circuit input

RST Reset Pin • Reset few output cycles to the external peripheral devices to let processor reset
and synchronize with the devices.
• Two external interrupts.

INT0# and
Interrupt Pins • These pins are active low ie, active when 0.
INT1#
• An Interrupt signals by the pin becoming 0 from 1.
Voltage supply • VDD and VSS for 5V supply and ground connections, respectively.
VCC or VDD and
pin and ground • When 8051version is based on CMOS circuits (in 80C51 version).
VSS (GND)
pin • VCC and GND when based on other circuits
Program store • Activates for reading the external program memory byte.
PSEN#
enable • The read is active when PSEN becomes 0.
• Activates when reading a byte from external data memory address.

RD# Read
• The read is active when becomes RD# 0.
• Activates when a byte is written (sent) to external data memory address.

WR# Write
• The write is active when WR# becomes 0.
Special Function Registers (SFR) 47
 The SFRs are at directly addressable space.
 Each SFR can be addressed by an address of 8-bits.

o Each bit can be addressed in specific SFRs and bit can be cleared to 0 or set to
1 or moved to another bit address.
o The addresses of these bits are used in Boolean processing logical operation on
the bits.
 Specific SFRs can only be addressed for the byte in them not individual
bits
Special 48
Function
Registers
PSW Register Bits And Flags 49
 A flag or a set of flags can reflect status of the processor.
 A flag is a bit that may be set or reset after an ALU operation.
o A bit is also set or reset after a bit-set, bit-reset, or bit-complement

operation or a bit transfer operation.
 The PSW register byte, being an SFR is directly addressable.
o PSW individual bits are directly addressable also.

 These addresses are used in a Boolean-processing logical-operation on

the bits.
o There is a convention that the right most least significant bit is denoted by b0.
o Therefore, the leftmost maximum significance bit is denoted by b7.
o Further, b7 of PSW is denoted by PSW.7 or PSW^7 and
o b0 of PSW by PSW.0 or PSW^7.
o Similar convention will be henceforth used for referring to the bits of PSW and
other SFRs.
 Z flag indicates the result of an ALU operation on A,

o whether A has all bits cleared and equals 0s or not. 80x86 and 8085 processors have Z flag.
o Z flag is used in loops and other conditional branch or call instructions.
 However, there is no Z flag. This is because of the fact that PSW design limits it to
only 8 bits.
o It is providing for two-user flags and two register bank select in 8051. (A bank is a set of 8
registers).
 Z flag is internally accessible to the condition test and branch logic circuit and
instruction like JZ. But to programmer
8051 Pin Diagram 53
8051 Pins 54
8051 Pins 55
8051 Pins 56
Microcontrollers
o Architecture
o Instruction Set
MODULE 5

Microcontrollers
Microcontrollers
o Architecture
o Instruction Set
8051 Memory Mapping 60
External Memory 61
Memory Mapping Addresses 62
Internal and External ROM 63
On Chip Memory- Internal RAM 64
Internal RAM 65
 The RAM IDATA/DATA is between 0x00 and 0x7F.
 The IDATA/ DATA RAM between 0x00 and 0x7F has 128 bytes
o Accessible by the address indirectly pointed by R0 and R1 in an

instruction or directly pointed address in an instruction.
 8052 has 256 B IDATA.

66
Internal RAM 67
Detailed Diagram
 4 Memory Banks
 128 bit addressable

memory
 General Purpose RAM
 Special Purpose Registers

Internal RAM 68
Detailed Diagram
 4 Memory Banks
 128 bit addressable memory
 General Purpose RAM

4 Register Banks 69
 The RAM DATA between 0x00 and 0x1F
 Define 4 register sets (called banks in 8051 terminology).

o Each having 8 registers within
 Each bank is selected by first assigning the RS0 and RS1 bits
b3 and b4 in the PSW.
 During an instruction only 3 bits can specify the addresses

register (RAM) in place of the 8 bits needed otherwise.
 These 32 bytes are not used for the bit operations with
Boolean processor and bit transfers
 Register Bank 0 is the default Register Bank

Memory Bank Selection 70
Bit Addressable Locations 71
 RAM between 0x20 and

0x2F has 16 bytes
 Define 128 bits with bit-
addresses 0x00 to 0xFF.
 A bit address is used in bit
operations with Boolean
processor and for bit
transfers
General Purpose RAM 72
 80 bytes
 Only accessible by the address
of the byte
 Not used in bit operations with
Boolean processor and bit

transfers.
Special Function Registers 73
74
75
76
77
Direct Address 78
 A flag is a bit that may be set or reset after an ALU operation.
 A flag or a set of flags can reflect status of the processor.
 A bit is also set or reset after a bit-set, bit-reset, or bit-
complement operation or a bit transfer operation.

 The PSW register byte, being an SFR is directly addressable.
o PSW individual bits are directly addressable also.

• b7 of PSW is denoted by PSW.7 or PSW^7 and b0 of PSW by PSW.0 or PSW^7.
Program Status Word 80
 Parity Flag
 User Flag1
 Overflow Flag
 Register Set Bit 0
 Register Set Bit 1
 User Flag0
 Auxiliary Carry Flag
 Carry Flag
Individual bit addresses of PSW 81
Port Address 82
Ports in Single-chip Mode Operations 83
Alternative Functions of Port 3 84
MODULE 5

Microcontrollers
Microcontrollers
o Architecture
o Instruction Set
8051 Interrupts 87
 An interrupt means an interruption of the current sequence of instructions

(current program).
 A set of instructions called interrupt service routine runs on occurrence of an

interrupt.
 Interrupt handling mechanism is essential feature in a processor or

microcontroller.
 Using interrupts, there is handling and servicing of the various devices such as
timers, serial interface and external source interrupt, such as keypad.
8051 Interrupts 88
 There is provision for programming whether an interrupt service for a

given interrupt is enabled (not masked) or masked.
 If the interrupt service for a given interrupt is enabled (not masked),

o The program counter of a currently executing program saves on the stack
o Another sequence of instructions called interrupt service routine (ISR)

executes.
o When there is return from the ISR, the saved program counter is loaded back
and the interrupted program runs again.
Instructions of Interrupt Service Routine 89
 ISR services a set of instructions after each interrupt event from the
interrupt source.
 Interrupt is a call event arising from a signal of another internal or
external process, device, circuit or action.
o for example, timeout message (timer overflow.)
• (A corresponding flag indicates overflow message.)
 The instant when an interrupt occurs (after which instruction of the

user current program or routine) is not known previously.
Interrupt service routine (ISR) 90
 An interrupt service routine (ISR) is a program that executes because

of an interrupt from another internal or external process, device,
circuit, or action.
 An action on interrupt occurs only whenever the processing unit has
been enabled previously to respond to that interrupt.
 When a call initiates following the interrupt, the calling program
parameters push on to the stack, and on return, these parameters pop
from the stack
Interrupt service routine (ISR) 91
 An ISR instructions are stored at some prefixed addresses for a

given interrupt source.
o ISR executes from a start address.
o The new program counter contents should point to that address for the
interrupt service to run the ISR.
o That address is called the ‘Vector Address’ for the given interrupt source.
INTERRUPTS IN 8051 92
 There are two SFRs for interrupt handing

o IE (interrupt enable) and
o IP (interrupt priority).
 The IE has the bit addressable bits.

o A bit in IE when reset disables (masks) an interrupt source, which may be the
requirement during a specific time critical action(s) and when set, enables the
interrupt source.
o Bit at IE.7 disables all interrupt services when it is reset to 0.

Special Function Registers Related to the Interrupt- 93
handling
IE- Bits 94
IP- Bits 95
Actions on an 96
Interrupt of a
Program by a
Source
Interrupt Vector Address 97
Addresses Available Default Priority Explanation of the Function

Interrupt vector address for external interrupt at pin
0x0003-0A 1 (highest)
INT0.
0x000B-12 2 Timer T0 overflow interrupt vector address.
Interrupt vector address for external interrupt at pin
0x0013-1A 3
INT1.
0x001B-22 4 Timer T1 overflow interrupt vector address.
Serial UART Interface interrupt vector address
0x0023-2A 5 (common for TxD serial outputs and RxD serial input
frames).
Interrupt vector address Timer T2 overflow cum
0x002B-32 6 T2EX pin negative transition for the time capture or
reload at T2.
Serial synchronous SI mode interrupt (available in a few
0x0053-5A 7
family variants).
Servicing of interrupts- 5 stages 98
 Stage 1: An interrupt occurs for the processor to interrupt the current

process (program) in 8051.
 Stage 2: Completes the current instruction.
 Stage 3: Checks if EA bit is 0

o Processing unit does not recognize any of the maskable interrupts.
o It continues with the existing program.

• Maskable interrupt means an interrupt source, which can be enabled or disabled for the
service.
 Stage 4: If EA is equal to 1, processor checks whether interrupt for the given source is enabled
(not masked) and if yes, then does the following actions:
1. Pushes PCH and PCL on to the memory stack. Fetches the corresponding ISR_VECTADDR for the
source among the 7 vector addresses.
2. Makes EA bit = 0 temporarily until first instruction within an ISR corresponding to the source
executes.
• The further interrupts from any lower priority interrupt are the only ones disabled until
return from the ISR.
• The higher priority ones are polled at the end of each instruction in the ISR
• If EA is reset to 0 in any ISR instruction then all interrupts disable.
• Before the return or after the end of critical section in the ISR the EA must be set again to 1 if
future interrupts are to be recognized.
0
 Stage 5: Loads into PCL and PCH (program counter address) the start
address of ISR (ISR_VECTAD-DR address) and executes the ISR for the
interrupting source.
o The ISR can call another routine.
o If the 8 bytes ISR space available between two routines (two vector addresses) is
insufficient, another location routine can be executed by jump instruction to vector to
address of remaining ISR.
Sources of interrupts 10
1
 Intel 8051 family microcontroller has 7 interrupt sources, that can
be masked using the bits in IE

EXTERNAL INTERRUPTS 10
2
 Control and Status Bits for the External Sources of Interrupts INT1 and INT0
1. External hardware interrupts INT1 and INT0 use the four lower bits of TCON. When IT1
(INT1 type bit) TCON.2 is reset to 0 the interrupt INT1 is level activated and set to 1, it is
edge triggered. It triggers by negative edge (1 to 0 transition) at INT1 pin.
2. When IT0 (INT0 type bit) TCON.0 is reset to 0 the interrupt INT0 is level activated and set to
1, it is edge triggered. It triggers by negative edge (1 to 0 transition) at INT0 pin.
3. When IE1 (INT1 event flag) TCON.3 sets to 1, the ISR starts and on start of ISR for INT1
service, it resets to 0.
4. When IE0 (INT0 event flag) TCON.1 is sets to 1, the ISR starts and on start of ISR for INT0
service, it resets to 0.
8051 Stack 10
3
 Stack is an important data structure.

o Data when saved (pushed) are stored in a manner that can be retrieved
(popped) as last in first out (LIFO).
o The stack facilitates a programmer to save LIFO retrievable data.
 A stack is accessed from the memory in the LIFO mode, while a row of
data in the queue is accessed in a FIFO (first in last out) mode.
 The SP points to a current stack top address

Stack Pointer 10
4
 Suppose, the processor saves the current program counter (calling
program code address) onto the stack top, on return from the
routine where the processor pushed that address earlier can be
popped from the stack top and the program will switch back from
the called program (routine) to the calling program.
10
5
MODULE 4

Microcontrollers
7
Microcontrollers
o Architecture
o Instruction Set
Assembly Programming basics 10
8
 Prefix 0x or Postfix H is used to indicate a hexa-decimal number, b
to indicate a binary number and none to indicate a decimal

number when writing an instruction.
 Destination operand in 8051 is written first after the operation
specification.
 Prefix # is used to specify an operand, which is called immediate
and is the succeeding byte(s) within an instruction.

Addressing Modes 10
9
 An addressing mode is a method of specifying the data source or destination in an instruction.
 The modes in the 8051 family instructions are as follows:

o Immediate
o Register
o Direct
o Indirect Register
o Indexed (Type of Indirect)
 3 other Addressing Modes related to branching instructions. They are

o Relative, Absolute, Long
11
0
1. Immediate Addressing Mode 11
1
 This mode of addressing uses either an 8- or 16-bit constant value as the source operand
 This constant is specified in the instruction, rather than in a register or a memory location
 The destination register should hold the same data size which is specified by the source operand
 The data bits for instruction are a part of the instruction and are the next byte after the opcode.
 E.g.
o ADD A, #030H ;Add 8-bit value of 30H to the accumulator register ;(which is an 8-bit register).
o MOV DPTR, #0FE00H ;Move 16-bit data constant ;FE00H into the 16-bit Data ;Pointer Register.
2. Register Addressing Modes 11
2
 The register addressing instruction involves information transfer

between registers
 Example:
o MOV R0, A
• The instruction transfers the accumulator content into the R0 register. The register
bank (Bank 0, 1, 2 or 3) must be specified prior to this instruction.
3. Direct Addressing Modes 11
3
 This mode allows you to specify the operand by giving its actual memory address
(typically in hexadecimal) or by giving its abbreviated name (e.g. P3)
 The address of 8-bits is directly specified in the instruction.
o Instructions for the SFRs have only the direct addressing mode in 8051.
o Internal RAM between 0x00 and 0x7F is also accessible by direct addressing.
 Example
o MOV R5, 90H ;(MOV R5, P1 for source at the SFR for P1 port. P1 has the address 90H)
o MOV A, P3 ;Transfer the contents of Port 3 to the accumulator
o MOV A, 020H ;Transfer the contents of RAM location 20H to the accumulator
4. Indirect register Addressing Mode 11
4
 This mode uses a pointer to hold the effective address of the operand
 Only registers R0, R1 and DPTR can be used as the pointer registers
o The R0 and R1 registers can hold an 8-bit address whereas DPTR can hold a 16-bit address
 The address is indirectly specified in the instruction by the contents of a pointer.

 Example
o MOV A, R1 ; MOV into A register the byte from the address pointed by contents of R1.
o MOV @R0, A ;Store the content of accumulator to the memory location pointed to by
register R0.
o MOVX A, @DPTR ;Transfer the contents from memory location pointed by DPTR into
accumulator.
5. Indexed Addressing Mode 11
5
 The Indexed addressing is useful when there is a need to retrieve data from a look-up table
 A 16-bit register (data pointer) holds the base address and the accumulator holds an 8-bit
displacement or index value
 The sum of these two registers forms the effective address for a JMP or MOVC instruction
 Example:
o MOV A, #08H ;Offset from table start
o MOV DPTR, #01F00H ;Table start address
o MOVC A, @A+DPTR ;Gets target value from the table start address + offset and puts it in A.
 After the execution of the above instructions, the program will branch to address 1F08H
(1F00H+08H) and the data byte retrieved from that location is transferred into the
accumulator (Code Memory- that’s why MOVC)
Relative Addressing 11
6
 This mode of addressing is used with some type of jump instructions, like SJMP
(short jump) and conditional jumps like JNZ
 These instructions transfer control from one part of a program to another
 The destination address must be within -128 and +127 bytes from the current
instruction address because an 8-bit offset is used (28 = 256)
 Example:
o GoBack: DEC A ;Decrement A
JNZ GoBack ;If A is not zero, loop back

Absolute Addressing 11
7
 Two instructions associated with this mode of addressing are ACALL and AJMP instructions
 These are 2-byte instructions where the 11-bit absolute address is specified as the operand
 The upper 5 bits of the 16-bit PC address are not modified. The lower 11 bits are loaded from
this instruction. So, the branch address must be within the current 2K byte page of program
memory (211 = 2048)
 Example:
o ACALL PORT_INIT ;PORT_INIT should be located within 2k bytes.
o PORT_INIT: MOV P0, #0FH ;PORT_INIT subroutine

Long Addressing 11
8
 This mode of addressing is used with the LCALL and LJMP instructions
 It is a 3-byte instruction and the last 2 bytes specify a 16-bit destination location where the
program branches
 It allows use of the full 64 K code space
 The program will always branch to the same location no matter where the program was
previously
 Example:
o LCALL TIMER_INIT ;TIMER_INIT address (16-bits long) is specified as the
operand. In C, this will be a function call: Timer_Init().
o TIMER_INIT: ORL TMOD, #01H ;TIMER_INIT subroutine

MODULE 5

Microcontrollers
0
Microcontrollers
o Architecture
o Instruction Set
PROGRAMMING BASICS 12
1
 A program means a set of instructions, which executes in an order.

o The order of execution of instructions defined in the program, which may be in a
sequential order.
 Each program has a start address.

o There is always the first executable instruction at the start address of a program.
o An end instruction can be for reset or halt or jump back to the same instruction or
return
 Machine codes mean bytes that are fetched and executed by the CPU.
 Each memory address has 1 byte.

Register 12
2
Functions
Program Counter 12
3
12
Stack 4
Pointer
Program Status Word 12
5
 A bit of PSW shows a certain condition of the process and so it is also called a
flag.
o Carry , Auxiliary carry and zero flags are examples.
 Carry flag is used in all processors to implement use of carry (or borrow) in
addition and subtraction.
 An auxiliary carry flag is used in all processors to implement BCD additions.
o A condition that a carry/ borrow results by addition/subtraction of the lower

nibble is saved in a bit called the auxiliary carry flag.
PSW 12
6
 The logic operation instructions, AND, OR, XOR, INC and DEC do not affect the flags.
o Only RLC(rotate left through carry) & RRC (rotate right through carry) affect carry flag.
 Parity P flag shows whether the number of bits in register A are odd or even (= 1 if odd).
 There is no zero flag.
 The programmer uses the PSW. 1 bit as the user flag F1 and PSW.5 bit as the user flag F0.
o F0 and F1 can be used in the program to reflect the task statuses.
 PSW.4 and PSW.3 are RS1 and RS0 (register set bits)- Used to select Register Banks
o To select a Register Bank, we can use Instructions like
• CLR PSW.4 and CLR PSW.3 (Register Bank 0) or
• SETBPSW.4 and SETBPSW.3 (Register Bank 3)

Types of 8051 programming 12
7
 x = (a + b + c) × d  3 different ways
 Exemplary 9 machine codes, 7 assembly codes and single high-level C language expression
CLASSIFICATION OF THE INSTRUCTIONS 12
8
1. Data Transfer Instructions 4. Logic Instructions
2. Boolean Variable Manipulation 5. Program Flow Control (Processor and
Instructions Machine Control) Instructions
3. Arithmetic Instructions 6. Interrupt Flow Control Instructions

MODULE 5

Microcontrollers
0
Microcontrollers
o Architecture
o Instruction Set
DATA TRANSFER INSTRUCTIONS 13
1
 MOV Instructions
 MOVC-type Instructions
 MOVX-type Instructions
 PUSH and POP Instructions
 XCH-type Instructions
MOV Instructions 13
2
13
3
Notations used in previous table 13
a. n is 0 or 1 or … or 6 or 7 for a register in the register bank. 4
o The bank is defined by RS0 and RS1 bits at PSW.

b. Data bits of the byte to be moved.
c. Direct is the byte for the address from where the byte at that address is to be moved.
o The address should be valid (existing SFR) in the SFR area or should be between 0x00 and 007F.
d. i = 0 or 1.
o Byte to be moved from the address pointed by the contents of R .
o Prefix @ implies a pointer register.
o R0 or R1 can be a pointer register in a bank.
o The bank is defined by the bits RS0 and RS1 at PSW.
e. Data of 16-bits to be moved into the DPTR.
o The DPTR is in two SFRs at the addresses 83H for DPL and 84H for DPH.
o Two direct addressing instructions will be needed if both are independently written.
Important Uses of MOV 13
5
 One of the most important uses of MOV instructions are programming of the SFRs.
 Some examples are MOV into
i. TMOD and TCON for timer
ii. SCON for the serial interface device
iii. setting the interrupt masks in IE
iv. set interrupt servicing priorities in IP
 The second most important advantage is

i. reading (moving) SBUF serial input bits into a register
ii. moving the bits at the port into specified register(R )
iii. reading internal RAM.

MOV Examples 13
6
 Write the control bits 0100 0000 (40H) into the TCON.
o MOV TCON, #40H
 Load the external memory address pointer DPTR with 0x1000 (1000H).
o MOV DPTR, 1000H.
 Load 0x1000 (1000H) in DPTR

o MOV DPTR, #0x1000
• MOV DPH, #10H and MOV DPL, #00H OR
• MOV 83H, #10H and MOV 82H, #00H

MOV @R1, A. 13
7
How can a byte be transferred from the address 13
8
pointed by R0 to the register R2?

 MOV @Ri , Rn is not an instruction present in 8051
o MOV Rn , A and MOV A, @Ri are available
o Hence, the byte pointed by R0 can first be moved into A and then to R2.
 The instructions are as follows:

o MOV A, @R0
o MOV R2, A
MOVC-type Instructions 13
9
 An MOVC instruction means move (copy) the 8-bit code from one source at the program
memory (internal or external) to the register A destination.
MOVX-type Instructions 14
0
 A MOVX instruction means move (copy) the 8-bit data into A and from A
using the external data memory addresses using DPTR or R as the pointer.
MOVX Instructions 14
1
PUSH and POP Instructions for Using the Stack 14
2
Area Employing the SP

 PUSH instruction means move (copy) the 8-bit data into the stack
after incrementing SP.
 The data are at a direct address.
 The address is of either an SFR or internal RAM between 00H and
7FH.
Use of Stack 14
3
 The values in the registers, RAM or SFRs can be saved for the LIFO operations later.
o Some array values can be dumped on the stack and can be retrieved later as LIFO. For
 Another advantage is that a variable of 1 byte can be saved at the stack

temporarily by a PUSH.
 When using an ISR sometimes, there is need to save A and PSW on the stack.
o This is to make A and PSW available for use in the ISR.
o Before the last instruction return from the ISR, there is need to get the saved A and PSW
back.
XCH-type Instructions 14
4
 An XCH instruction is for exchanging the A register with a source using the register
(direct or indirect addressing) mode.
 An XCHD instruction is to exchange the lower hex-digit (nibbles) between the A
and RAM using indirect addressing.
Advantages of XCHG 14
5
 The accumulator can be temporarily saved at an address and the
value used from that address for arithmetic or logical operations.

o Later, the old value of A can be retrieved and the result after the
operation will be back to that address by repeating the exchange
instruction.
o Similarly, the lower digits can be operated and upper digits can be kept
intact using the XCHD.
XCHG Example 14
6
 Swap the contents (bytes) at P0 and P1.

o The exchange instructions between the bytes at the direct addresses are not available in
8051.
• However, XCH A, direct is available.
 The following instructions will swap P0 and P1:

1. XCH A, P0 (exchange A and P0 contents).
2. XCH A, P1 (when exchanging A and P1 contents, P1 gets contents of original value of P0

through the A. Then, A gets the contents of P1).
3. XCH A, P0 (when exchanging A and P0 contents, P0 gets contents of original contents of P1.
A gets the contents of P0, which has A’s original value after the first instruction).
MODULE 5

Microcontrollers
8
Microcontrollers
o Architecture
o Instruction Set
DATA AND BIT-MANIPULATION INSTRUCTIONS 14
9
 Data Byte Manipulate Instructions

o Clear, Complement, Rotate and Swap
 Boolean Variable (Bit) Manipulate and Boolean Processing Instructions

15
0
Data Byte Manipulate Instructions 15
1
 The source and destination operand addresses are the same and it is only the A
(accumulator) that can be manipulated in 8051.
1. A CLR instruction makes all bits 0s. A=0000 0000 after CLR A.
2. A CPL instruction complements all 1s to 0s and vice versa. For example, if
A=A5H=10100101 then after CPL the A=01011010b.
3. An RL instruction rotates left. For example, bits 10001010b become 00010101b, and the
C flag of PSW also becomes 1 after rotate left.
4. An RLC instruction rotates left through the carry flag. For example, consider bits,
A=10001010b and C=0. RLC makes A=00010100b and the C flag also becomes 1. After
the rotate left through carry the C flag shifts to LSB (least significant bit) at A and MSB
(maximum significance bit) to C.
Data Byte Manipulate Instructions 15
2
5. RR and RRC are similar to RL and RLC instructions and are for the rotate
right and rotate right through carry.
6. RR rotates right and thus shifts LSB to MSB and also to C.
7. The C flag shifts to MSB and the LSB to C in RRC after rotation.
8. SWAP is for swapping between the upper hex-digit with the lower hex-
digit. For example, 89H will become 98H after SWAP.
Excercises 15
3
 What will be the effect of RRC A, assuming A = 02H and C = 1?
 What will now be the effect of CPL A? Assume that it executes
after the RRC in previous Example.

 Complement the port P2 bits
o XCH A, P2
o CPL A and
o XCH A, P2
Boolean Variable (Bit) Manipulate and Boolean 15
4
Processing Instructions
 The bit-manipulation instructions are also called Boolean processing instructions.
o The source or destination operand is either C or bit.
o The C or bit is clear, set, complement.
o There can be transfer (copy) or ANDing and ORing using bit and C.
o C acts like the Boolean accumulator like the A in byte-manipulating instructions.
 The bit means bit at a bit address. (between the 80H and FFH in select SFRs like
P0, P1, …) and bit addresses between 00H and 7FH for 16 bytes at the internal
RAM between 20H and 2FH.
15
5
Boolean Variable (Bit) Manipulate and Boolean Processing 15
6
Instructions
1. A MOV instruction transfers the bit between C and bit.
2. A CLR instruction makes C or bit = 0.
3. A CPL instruction complements C or bit. For example, the bit at bit address 93H will be 0, if 1. Note
that 93H is for the bit 3 in byte at P1.
4. A SETB instruction sets C or bit. For example, the bit at bit address BAH = 1 after the SETB. Note that
BAH is the address of bit 2 in SFR IP (Table 3.19).
5. An ANL instruction does ANDing between C and bit or complement of the bit, . For example, assume
bit at P2 bit 3 (address = B3H) = 1 and C = 0. After ANDing C and bit P2.3, C becomes 0.
6. An ORL instruction does ORing between C and bit or complement of the bit, . For example, consider
bit at RS0 = 0 (address D3H). It is a PSW bit. And C=0. After ORing C and bit PSW.3, C becomes 1.
Examples 15
7
 Complement the bit 3 of internal RAM at 21H.

o CPL 0BH.
o It complements the bit at the bit address 0BH, which is bit 3 at 21H
 Write instructions (i) P1 port bit 0 = 0, (ii) IE bit 7 = 1 and (iii) Complement TCON bit 6.
1. CLR P1.0 or CLR 90H to clear the bit at the bit address 90H,which is P1.0.
2. SETB IE.7 or SETB 0AFH to set the bit at the bit address AFH, which is IE.7.
3. CPL TCON.6 or CPL 08EH to complement the bit at the bit address 8EH, which is TCON.6
4. CPL 0BH to complement the bit at the bit address 0BH, which is bit 3 at 21H (remember 00H to 07H
are the bit addresses for RAM at 20H and 08H to 0FH, the bit addresses for RAM at 21H).
MODULE 5

Microcontrollers
9
Microcontrollers
o Architecture
o Instruction Set
ARITHMETIC INSTRUCTIONS 16
0
 The instructions are for 8-bit addition, subtraction, increment, decrement, multiply and
division instructions.
 There is a 16-bit DPTR increment (without affecting the flags) instruction.
1. Add and subtract and increment and decrement instructions.

o The instruction uses one of the four addressing modes each—register, immediate,
direct and indirect.
2. There are two sets of addition instructions—add without carry and add with carry.
o Both use one of the 4 models of addressing.
3. There is only one set of subtract instruction—subtract with borrow (C). Subtract without
borrow can be done in two steps—CLR C and then SBB B.
4. C, OV and AC are affected as follows
16
o C is set when the addition results in answer > FFH and set when subtraction results in the answer < 00H. 1
o AC is set when an addition or subtraction in the lower-nibble operation changes the value of the upper-nibble.
o AC is used for decimal adjusting the result by DA A instruction after the addition.
o OV is useful in addition or subtraction of the signed numbers.
5. Multiplication and division instructions use only the register addressing mode and use only A and B.
o OV is affected and is useful in determining whether 8 bits multiplied by 8 bits results in an 8 bit (when OV0) or in 16-
bit (when OV 1) number.
o OV is also useful in determining that denominator was 0 earlier (OV = 1) or not (OV 0) during the division.
6. DA A (decimal adjust accumulator) instruction use only the register addressing mode and uses A.
7. INC DPTR instruction has only one addressing mode—16-bit register (pair) addressing mode and uses DPL
and DPH.
16
2
16
3
16
4
16
5
MODULE 5

Microcontrollers
7
Microcontrollers
o Architecture
o Instruction Set
INSTRUCTIONS FOR LOGICAL OPERATIONS ON 16
8
BYTES AT THE REGISTERS, INTERNAL RAM AND

SFRS
16
9
17
0
17
1
MODULE 5

Microcontrollers
3
Microcontrollers
o Architecture
o Instruction Set
PROGRAM-FLOW CONTROL INSTRUCTIONS 17
4
 Delay-cycle (NOP) Instructions
 Long, Absolute and Short Jumps
 Conditional Short Relative Jumps
 Decrement and Conditional Jump on Zero
 Jump After Comparison
 Call to a Routine and Return from Routine

PROGRAM-FLOW CONTROL INSTRUCTIONS 17
5
 Program-flow instructions change the program flow from sequential order.
 The instructions for jump, call and reset instructions are called program flow instructions.
o They change the program counter to a value other than the one present after the increment of program counter just after an
instruction fetch.
 A program may have the while or for loop.

o It may have the conditions for executing a specific section of the instructions.
o A program may jump to another address in case of executing a conditional instruction or while-loop or repeat loop.
o The program may call other routine(s) in between the instructions.
o The routine may return to calling routine or program at the end of the instructions.
o These actions warrant a change in the program-flow path.
o The program counter after steadily incrementing after each code of the instruction acquires a new value to start another program-
flow path.
Delay-cycle (NOP) Instructions 17
6
 The 8051 has NOP instruction.
o It means no operation, just spent one instruction cycle time
 Example : How can we toggle the bits at Port 2 and again toggle after a delay of 10 μs?
[Make the bits = 1s as 0s and 0s as 1s. Delay 10 μs. Again make 1s as 0s and 0s as 1s.]
o Assume that XTAL oscillation frequency = 12 MHz.
o We introduce the delay of 10 us using 8 NOPs.
o Then repeat XOR operation with P2 after the NOPs.
o Instructions will be as follows:

• XRL 0A0H, #FFH (XRL with all bits = 1s)
• (equivalent to XRL P2, #11111111b as direct address of P2 is A0H)
• NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
• XRL P2, #FFH.

Long, Absolute and Short Jumps 17
7
 The 8051 has three jump instructions

o Long Jump: jump to any 16-bit address
o Absolute Jump: Jump to address within the 2 kB space and
o Short Jump: jump to the address within 128 bytes above or below the present address.
Conditional Short Relative Jumps 17
8
Decrement and Conditional Jump on Zero 17
9
Jump After Comparison 18
0
Call to a Routine and Return from Routine 18
1
 The 8051 has two call instructions
o Call to any 16-bit address and
o Call to address within the 2 kB.
 These are useful for the call long and absolute to a routine.
Operations in LCALL 18
2
Steps for return from a routine 18
3
Long, absolute call and return instructions in 8051 18
4
INTERRUPT CONTROL FLOW (RETI INSTRUCTION) 18
5
ASCII-RELATED APPLICATION PROGRAM 18
6
 It uses the table of ASCII codes for the numbers between 0 and 9.
 It shows creating of a new array of ASCII codes.
 The codes rearrange as per the sequence of 10 characters which

were input from a telephone dialing keypad.
BCD-RELATED APPLICATION PROGRAM 18
7
 Write a program to add BCD numbers 91 and 79 in R8 and R7. What is the result at R5 after the
addition? What are the flags effected in ADD and DA A?
1. MOV R6, #91
2. MOV R7, #79
3. MOV A, R6
4. ADD A, R7 ; Effects AC, AC =0; Effect C, C = 1. [91 + 79 generate auxiliary carry as well as carry].
Auxiliary carry because lower BCD digits addition 1001 + 0001 cause auxiliary carry AC = 1 upper
BCD digits 1001 + 0111 also cause carry. A is now 0A. It is to be adjusted for BCD addition.
5. DA A; decimal adjust by adding 6 in A because the lower digit exceeds 9. A + 6 = 0 and new inter AC = 1.
Add 6 and AC = 1 to higher digit 0 because the higher digit exceeds 9. Result is A = 70. C need not change
if previous carry = 1. Read with C = 1, the result is 170.
6. MOV R5, A ; MOV result in A to R5.
 The flag, which affects after DA A, is C only and it is 1.

SERIAL PORT-RELATED APPLICATION PROGRAMS 18
8
 With the help of moving data to SBUF register

MODULE 4

Microcontrollers
0
Microcontrollers
o Architecture
o Instruction Set
Benefits of Assembly Language Program (ALP) 19
1
1. There is efficient use of the memory.
o Machine codes generated from the ALP are compact.
o The ALP codes need smaller memory than in machine codes for the same function in memory after the
compilation of a high level language program.
2. Features of processor instruction set are kept in full view when program is done using ALP.
3. Only few assembly instructions are needed for driving the devices.
o Driving a device means configuring of device by writing control or command words, and writing or reading the
bytes at registers or ports of device.
4. System operations are speeded by the use of ALP.
5. There is full understanding of the process that is taking place at each instance of program execution.
o Time critical codes are therefore programmed in ALP.
6. The code size and code execution speed of the program are known.
Assembler 19
2
 Assembler is a program that gives an ease in assembly language programming and
that is used to prepare the machine codes using an input file for the source code
o Assembler is a part of an integrated in a development tool.
o The assembler generates machine codes, assigns addresses to the SFRs, bit addresses to
the bits in the SFRs and code-addresses to the labels.
o The assembler allows use of the macros.
 The assembler also prepares a source code (ALP) listing with the addresses.
o The assembler provides for faster development of the ALP. This is because of the
following:
1. The assembler has a large number of assembler directives and
2. The assembler provides for structured programming.

Assembler 19
3
 The structured programming is done by

o the use of structured code segments (blocks)
o use of the program with decision blocks (if then else and looping statements
like C) and
o use of a hierarchical design (nesting of decision blocks, loops and routines).

• [Use of the loops and decision blocks and structures is like C. This means use of pseudo
C in the assembler. Pseudo C means C-like statements.]
o A structured hierarchical design gives a program with single entry and exit
addresses.
Assembly Language Program 19
4
 Write an assembly language program to find

whether a given byte is available in the given
sequence or not. If it is available, write FF in R3.
Otherwise write 00 in R3
o A program for finding a number in array of numbers
stored in data memory for example in memory
locations (20H,21 H,22H,23H,24H) the contents are
[15,04,06,45,55]
5
 Write an assembly language program to count the

number of 1s and 0s in a given 8-bit number
o Program to compute number of 1s and 0s in 8 bit
number
 logic: initialize R1 and R2 with OOH

o initialize R3 as a counter
o clear carry flag (C ) and rotate A along with carry

• if C=1, increment R1, else increment R2 and decrement
the counter
o if counter=0, store the contents of R1 and R2 and end

the program
6
 Write an assembly language program to compute x to the power n where both x and n are
8-bit numbers given by user and the result should not be more than 16 bits.
7
 Write an assembly language program to perform

addition of two 2 x 2 matrices.
o Let the Contents of A be [5,6;7,8] stored at memory
locations (20H,21H,22H,23H).
o Let contents of B are [3,2;1,0] stored in Memory

locations (30H,31H,32H,33H].
o The result of the addition is to be stored in matrix

C=A+B in Memory locations {20H,21 H,22H,23H}, i.e.
by overwriting the addresses of Matrix A.
o R0 handles A and R1handles B.

8
 Write an assembly language program

for finding transpose of a 2x2 matrix.
o a program to find transpose of a matrix
stored in data memory of 8051
o content of matrix is a = [10,20;30,50] (2

rows and r columns [A00,A01
;A10,A11]) stored sequentially at
20H,21H,22H,23H
o store result at 30H,31H,32H,33H

9
 Interface 8 LEDs with 8051 Port 0

and write assembly language
programs to
a) glow all the LEDs continuously.
b) Flash all the LEDs on and off for

1 second each.
c) Glow alternate LEDs for 1 second

and then shift the glowing
pattern left continuously
20
0

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MODULE 5

CST 307 : Microprocessors &

 A microcomputer is a circuit or VLSI core that functions as a computer and

o Memory for storing the dedicated programs and subprograms

o Interfacing circuit between the external memories and IO devices

o Interrupt handling circuit or unit to handle the system interrupts

 A microcontroller is a microcomputer with few other application-

 An MCU also consists a few or many of the following devices.

o Devices for the synchronous and asynchronous serial IO

o Device for analog to digital conversion (ADC)

o Modem which is a device to enable external communication

o Digital signal processing (DSP) [DSP instructions may be at the CPU]

o Ports which can enable processing by non-linear control instructions

o Ports can have wireless interface.

o Make the system bulkier and much more expensive

Characteristics and Resources of a

1. Basic processing unit, internal buses and interrupt handler

2. On-chip program memory, Internal EEPROM and Flash

4. Interfacing capability to external program memory

5. Interfacing capability to external data memory

8. Special function registers-SFR

10. Serial synchronous

12. Pulse width modulator (PWM)

13. On-chip ADC

14. Watchdog timer

15. Bitwise manipulation capability

16. Power-down mode

17. Real-time clock

CST 307 : Microprocessors &

 Two 16 Bit Timer/Counter :T0, T1

 Full Duplex serial data receiver/transmitter

 4 Register banks with 8 registers in each bank.

 16 bit Program counter (PC) and a data pointer (DPTR)

 8 Bit Program Status Word (PSW)

 8 Bit Stack Pointer

 5 vector interrupt structure (RESET not considered as an interrupt.)

 8051 CPU consists of 8 bit ALU with associated registers like

o 16 bit program counter

 8051 has 128 bytes of internal RAM which is divided into

o Bit addressable memory area [20 – 2F]

o General purpose memory area (Scratch pad memory) [30-7F]

CST 307 : Microprocessors &

 The 8031 and 8051 microcontrollers are similar in their architecture.

• All the program memory needed is interfaced to external ROM/flash in 8031.

 Ports P0 and P2 are used for interfacing to the external memory.

 The characteristic features of a  The 8051 has

o Special function registers (SFRs) and

o Four ports, P0, P1, P2 and P3.

 An 8051 can be used in the expanded mode also.

o Single-chip mode means use of internal devices and circuitry only.

 Each program needs the temporary variables.

o Also there are a number of special function registers (SFRs).

 Each program needs a stack.

o SP (stack-pointer) is 8-bit register.

o These 8 pins are used in the expanded mode.

 There is a program counter (PC) higher byte at bus A8–A15.

o These are common with the Port P2.

 A microcontroller can be connected to I/O devices (using ports).

 There are 2 external pins for interrupts INT0 and INT1.

o Two SFR are used for priorities and masks.

 There are 2 programmable timers/event counters to do real-time

2. Extended and single-chip modes. i. PSW

3. ROM 4 kB in 8351 ii. A, B