[ea CAREER ENDEAVOUR Best fi ute for IT-JAM, NET & GATE CSIR-UGC-NETIJRF | GATE PHYSICS ASSIGNMENT — \/\1O A digital-to-analog converter with a full scale output voltage of 3.5 V has a resolution close to 14 mY. Its bits sizeis An8-bit unipolar successive approxi ionregistertype ADC is used to convert 3.5 V to digital equivalent ‘output. The reference voltage is +5 V. The output of ADC at the end of 3" clock pulse after the start of conversion is (@) 10100000 (b) 1000 0000 (©) 0000 0001 (@) 00000011 A digital system is requited to amplifya binary-encoded audio signal. The user should be able to control the ‘gain ofthe amplifier from a minimum toa maximurs in 100 increments. The minimum numberof bits required to encode, in straight binary,is @s ) 6 (5 (7 ‘The resolution of a 4-bit counting ADCis 0.5 volts, Foran analog input oF 6.6 V, the digital oatput of the ADC willbe (@) 1011 (b) Lor (©) 1100 @ 110 A student has made a 3-bi inary down counter and connected to the R-2R ladder type DAC [Gain = (—1k/2R)] as shownin figure to generate a staircase waveform. The output achieved is different as shown in figure, What could be the possible cause of this error ” & KR £ Lko +2V Counter viliz lock 01234567 —+ rms) (@) Theresistance values are incorrect, (b) The counter is not working properly (©) The connection from the counter 1o DAC is not proper. (@) The Rand 22 resistance are interchanged. (ea South Det: 26-A/11, Tia Sara, Near TTT Metro Station, New Delhi-t6, Ph: O11-26851008, 26861009 ‘North Delhi: 33-35, Mall Road, GTB. Nagar (Opp. Metro Gate No. 3), Delli-D9, Ph: OLL-276S3355, 276544558 10, @ "An 8-bit successive approximation analog to digital Converter has fll scale weading of 2.55 V and is conver- sion time for an analog input of IV is 20 us. The conversion time for a 2V input will be (@) 1s (b) 20s (©) 40 ps (@) 50ps ADVA converter has 5 V full-scale output voltage and an accuracy of 0.2% "The maximum error for any ‘output voltage will be (a) SmV () 10mv © 20mv (@) LOmv An8.-bit D/A converter has a full-scale output voltage of 20 V. The output voltage when the inputis 11011011, i (a) 160mv (b) 78mV (© 20V (@ itv ‘The number of comparator circuits required to build a three-bit simultaneous A/D converter is @7 b) 8 1S (@ 16 ‘Which of the following ADCs uses over sampling in its operation (a) Sigma—delta ADC (b) Counter ramp convertor (c) Successive Approximation RegisterADC (dl) Flash convertor (eA Sout Del: 28-71, Sia Sarai, Near-ITF Metro Station, New Delbi-16, Pi = O11-26851008, 26861000 SSS “North Delhi 35-35, Mall Road, GTB, Nagar (Opp: Metro Gate No, 3), Delli-OO, Ph: O11-27653358, 27654455