DATA SHEET FT8006S-AN v05 麦博韦尔

DATA SHEET
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Super In-Cell IC Integrates TFT LCD

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Driver and Touch Panel Controller

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Into a Single Chip for Amorphous

TFT-LCDs and Touch Controller
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Support Real Multi-Touch

Capability.
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Preliminary
JUL. 27, 2021
Version 0.5
FocalTech Systems reserves the right to change this documentation without prior notice. Information provided by FocalTech Systems is believed to be accurate
and reliable. However, FocalTech Systems makes no warranty for any errors which may appear in this document. Contact FocalTech Systems to obtain the
latest version of device specifications before placing your order. No responsibility is assumed by FocalTech Systems for any infringement of patent or other
rights of third parties which may result from its use. In addition, FocalTech Systems products are not authorized for use as critical components in life support
devices/ systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user,
without the express written approval of FocalTech Systems.
Preliminary
FT8006S-AN
Table of Contents
PAGE
TABLE OF CONTENTS .......................................................................................................................................................................................... 2
1. GENERAL DESCRIPTION ....................................................................................................................................................................... 6
2. FEATURES ............................................................................................................................................................................................... 6
2.1. Touch ................................................................................................................................................................................................ 6
2.2. Display .............................................................................................................................................................................................. 7
3. BLOCK DIAGRAM ................................................................................................................................................................................... 8
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3.1. Block Function ................................................................................................................................................................................ 8
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3.1.1. System interface ................................................................................................................................................................. 9
3.1.2. SX driver circuit .................................................................................................................................................................. 9
3.1.3. AFE Controller ..................................................................................................................................................................... 9
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3.1.4. Embedded MCU .................................................................................................................................................................. 9
3.1.5. I2C serial interface .............................................................................................................................................................. 9
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3.1.6. External Flash ..................................................................................................................................................................... 9
3.1.7. Watch Dog ........................................................................................................................................................................... 9

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3.1.8. Timing Controller ................................................................................................................................................................ 9
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3.1.9. Source driver circuit ........................................................................................................................................................... 9
3.1.10. Gate driver circuit ............................................................................................................................................................. 10

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3.1.11. Grayscale voltage generating circuit .............................................................................................................................. 10

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3.1.12. Oscillator (OSC) ................................................................................................................................................................ 10
3.1.13. LCD driving power supply circuit.................................................................................................................................... 10
4. PIN DESCRIPTIONS .............................................................................................................................................................................. 11

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4.1. Pin Definition ................................................................................................................................................................................... 11

4.2. Power Block Diagram...................................................................................................................................................................... 14
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4.3. Power Supply Configuration............................................................................................................................................................ 15

4.4. Application Circuit ........................................................................................................................................................................... 16
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5. INSTRUCTION ........................................................................................................................................................................................ 17
5.1 Outline ............................................................................................................................................................................................. 17
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5.1.1 System function command list and description ............................................................................................................................... 17

5.1.2 System function command list ........................................................................................................................................................ 18
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5.2 System Function Command Description ......................................................................................................................................... 19

5.2.1 SWRESET (01h): Software Reset ...................................................................................................................................... 19
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5.2.2 BIST_MODE (02H): Enter BIST mode ................................................................................................................................ 20
5.2.3 RDDPM (0AH): Read Display Power Mode ........................................................................................................................ 21
5.2.4 SLPIN (10H) & SLPOUT (11H) : Sleep-In & Sleep-Out ...................................................................................................... 22
5.2.5 DEEP_STBY (17H/18H) : Enter Deep Standby Mode ........................................................................................................ 24
5.2.6 DISPLAY_CTRL (28H/29H) : Display Control ..................................................................................................................... 25
5.2.7 OTP_STOP_RELOAD (41H/4EH): OTP Stop Reload Enable ............................................................................................ 27
5.2.8 EXT_ADR (42H): Extended Address of Command Interface ............................................................................................. 28
5.2.9 OTP_CTRL_STATUS (48H): OTP Control & Status ........................................................................................................... 29
5.2.10 FSC_CTRL (4AH/4BH) : MIPI FSC Function Control ......................................................................................................... 30
© FocalTech Technology Co., Ltd. 2 JUL. 27, 2021

Proprietary & Confidential Preliminary Version: 0.5
Preliminary
FT8006S-AN
5.2.11 DISBV_SET (51H/52H): Display Brightness Value Setting ................................................................................................. 31
5.2.12 DISBV_RD (52H/53H): Read Display Brightness Value ..................................................................................................... 32
5.2.13 DISBV_CTRL (53H): Display Brightness Value Control...................................................................................................... 33
5.2.14 RDDISBV_CTRL (54H): Read Display Brightness Value Control ....................................................................................... 34
5.2.15 WRFCC_CABC (55H): Write Focal CleverColor – Content Adaptive Brightness Control .................................................. 35
5.2.16 RDFCC_CABC (56H): Read Focal CleverColor – Content Adaptive Brightness Control ................................................... 36
5.2.17 OTP_PROG (58H/59H/5AH) : OTP Program ..................................................................................................................... 37
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5.2.18 WRCABC_MDISBV (5EH/5FH) : Focal CleverColor – Write CABC Minimum Display Brightness Value .......................... 38
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5.2.19 RDCABC_MDISBV (5FH/60H) : Focal CleverColor – Read CABC Minimum Display Brightness Value ........................... 39
5.2.20 RDDDB (A1H/A8H) : Read DDB Start & Read DDB Continue ........................................................................................... 40
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5.2.21 RDID_DA (DAH) : Read ID_DA in OTP .............................................................................................................................. 42
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5.2.22 RDID_DB (DBH) : Read ID_DB in OTP .............................................................................................................................. 43
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5.2.23 RDID_DC (DCH) : Read ID_DC in OTP ............................................................................................................................. 44
6. FUNCTIONS ........................................................................................................................................................................................... 45
6.1. Interface Architecture ................................................................................................................................................................... 45
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6.2. MIPI-DSI Interface.......................................................................................................................................................................... 46
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6.2.1 General description ............................................................................................................................................................. 46
6.2.2 Interface level communication ............................................................................................................................................ 46

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6.2.3 DSI data lanes .................................................................................................................................................................... 52

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6.2.4 Packet level communication ............................................................................................................................................... 62
6.2.5 Customer-defined generic read data type format ............................................................................................................... 73
6.3. I2C-Bus Interface ............................................................................................................................................................................ 74

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6.3.1. Characteristics of I2C-bus................................................................................................................................................... 74
6.3.2. System configuration .......................................................................................................................................................... 74

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6.3.3. Bit transfer ........................................................................................................................................................................... 74

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6.3.4. START and STOP conditions .............................................................................................................................................. 75
6.3.5. Acknowledgment ................................................................................................................................................................. 75

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6.4. Power Level Definition.................................................................................................................................................................. 76

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6.4.1. Power level ......................................................................................................................................................................... 76
6.4.2. Power flow chart ................................................................................................................................................................. 76

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6.5. Tear Effect Information ................................................................................................................................................................. 77

6.5.1. General ............................................................................................................................................................................... 77
6.5.1.1. Tearing effect line models ................................................................................................................................................... 77
6.5.1.2. Tearing effect line timing ..................................................................................................................................................... 78
6.5.1.3. Example 1 MCU write is faster then panel read .................................................................................................................. 79
6.5.1.4. Example 1 MCU write is slower then panel read ................................................................................................................ 80
6.5.2. Tearing effect bus trigger .................................................................................................................................................... 81
6.5.2.1. Tearing effect bus trigger enable ......................................................................................................................................... 82
6.5.2.2. Tearing effect bus trigger disable ........................................................................................................................................ 83
6.5.2.3. Tearing effect bus trigger sequences .................................................................................................................................. 84

Preliminary
FT8006S-AN
6.6 NVM Programming Procedure ........................................................................................................................................................... 89
6.6.1 NVM program flow chart with internal Power ...................................................................................................................... 89
7. TP FUNCTION DESCRIPTION ...................................................................................................................................................................... 91

7.1 TP Architecture .................................................................................................................................................................................. 91
7.2 MCU 92
7.3 Operation Mode ................................................................................................................................................................................. 92
7.4 Microprocessor Interface................................................................................................................................................................. 93
7.5 Touch Controller Boots Firmware With External Flash ...................................................................................................................... 93
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7.6 I2C Interface to Host .......................................................................................................................................................................... 93
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7.7 I2C Read/Write Interface Description ................................................................................................................................................ 94
7.7.1 Host Write Data to Slave ....................................................................................................................................................... 94
7.7.2 Host Read Data from Slave................................................................................................................................................... 94
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7.8 SPI nterface to Host ........................................................................................................................................................................ 94
7.9 SPI Read/Write Interface Description ................................................................................................................................................ 95
7.9.1 SPI Transmission Packet .................................................................................................................................................... 95
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7.9.2 Host Write Data to Slave ..................................................................................................................................................... 96
7.9.3 Host Read Data from Slave ................................................................................................................................................ 96

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7.10 Interrupt signal form FT8006S_AN to Host ...................................................................................................................................... 96
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7.11 CTPM Register Map ...................................................................................................................................................................... 97

7.11.1 Working Mode ..................................................................................................................................................................... 97
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7.11.2 DEVICE_MODE .................................................................................................................................................................. 98

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7.11.3 TD_STATUS........................................................................................................................................................................ 98
7.11.4 Pn_XH (n:1-10) ................................................................................................................................................................... 99
7.11.5 Pn_XL (n:1-10) .................................................................................................................................................................... 99

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7.11.6 Pn_YH (n:1-10) ................................................................................................................................................................... 99
7.11.7 Pn_YL (n:1-10) .................................................................................................................................................................... 99

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7.11.8 Pn_WEIGHT (n:1-10) .......................................................................................................................................................... 99

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7.11.9 Pn_MISC (n:1-10) ............................................................................................................................................................... 99
7.11.10 PWR_MODE ....................................................................................................................................................................... 99

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7.11.11 FW_VER ............................................................................................................................................................................. 99

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8. ELECTRICAL SPECIFICATION ........................................................................................................................................................... 100

8.1. Absolute Maximum Ratings ....................................................................................................................................................... 100
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8.2. DC Characterisitics ..................................................................................................................................................................... 101

8.2.1. Basic DC characteristic ..................................................................................................................................................... 101
8.2.2. MIPI DC characteristic ...................................................................................................................................................... 102
8.3. AC Characterisitics ..................................................................................................................................................................... 103

8.3.1. Reset timing characteristics .............................................................................................................................................. 103
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8.3.2. I C interface characteristics .............................................................................................................................................. 104
8.3.3. SPI interface characteristics ( mode 0 ) ............................................................................................................................ 105
8.3.4. MIPI-DSI characteristics ................................................................................................................................................... 106
8.3.5. Power On Off Sequence .................................................................................................................................................... 111
9. CHIP INFORMATION ........................................................................................................................................................................... 114

Preliminary
FT8006S-AN
9.1 PAD Assignment ........................................................................................................................................................................... 114
9.2 PAD Dimension ............................................................................................................................................................................. 114
9.3 PAD Location ................................................................................................................................................................................ 115
9.4 Alignment Mark ............................................................................................................................................................................. 142
10 DISCLAIMER ........................................................................................................................................................................................ 143
11 REVISION HISTORY ............................................................................................................................................................................ 144
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Preliminary
FT8006S-AN
1. GENERAL DESCRIPTION In addition, the external Flash of FT8006S-AN can store not
FT8006S-AN highly integrates a-Si TFT LCD driver and Super only the firmware used for Touch controller, but also the Initial
in-cell Touch controller into single chip. Combined with Super code of LCD driver. After loading the initial code through the
in-cell panel technology, FT8006S-AN provides high external Flash, the HOST only needs to send out "Sleep out" and
performance and high-quality human-machine interactive "Display on" to turn on the LCD. This will greatly simplify the
solutions for tablet display terminals. In addition, the LCD driver operation of the HOST to LCD, making the configuration process
uses RGB colors each with independently adjustable Gamma both flexible and simple. Furthermore, when ESD occurs, HOST
correction, 1-dot / 2-dot / column / Zigzag liquid crystal reversion reloads Initial code directly from Flash, greatly improving the IC's
mode and CABC / CE / SRE image processing technology, so ESD capability.
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that it can achieve high resolution, multi-color, high-quality
display characteristics. 2. FEATURES
The Touch panel controller of FT8006S-AN uses a 16-bit 2.1. Touch
high-performance MCU. With its built-in high-speed  16-bit embedded MCU
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high-performance hardware-accelerated computing modules, it  Built-in hardware acceleration module
provides superior data processing capabilities. FT8006S-AN  Program storage size: 64KByte SRAM
AFE can scan and detect 576 channels simultaneously.  Data storage size: 40KByte SRAM
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Combined with Time-Division Area-Division scanning technology,  Super self-capacitance detection technology
it greatly reduces the scanning time of Touch panel, so that it  576 channels
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reaches point reporting rate over 180Hz. With Focaltech's  10 -point Real Touch
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patented drive technology and algorithms, the touch controller  Anti-floating
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has excellent waterproof performance, strong  Anti-power interference

anti-noise-and-interference ability and high signal to noise ratio.  Anti-stress from external
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Its touch experience can achieve up to 10 points.  Point reporting rate up to 180Hz
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 I2C & SPI data communication interface

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Preliminary
FT8006S-AN
2.2. Display
 Support up-to HD a-Si TFT LCD driver without GRAM  Provide OTP to store VCOM/ID0~9 and ID_DA/ID_DB/
 Supports Flash initialization with initial code inside ID_DC
 Resolution  Save Command Setting in External Flash Memory
 720RGB x (1280, others)  Built-in Oscillator for Display Clock generation
 720RGB x 1680 max resolution  Built-in 22 GOUT signals (GOUT1 ~ GOUT22) on each
 Colors Display side of the chip, providing directly the drive signals to the
 Full color mode: 16.7M-colors (24-bit,8(R):8(G):8(B)) GIP circuit on the LCD panel
 Supports the features that refresh the display function  Temperature Compensation for VGHO/VGLO/VCOM
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for N-lines with a pause of 0 ~ 250us (for touch scan) and  Power modes:
then continue to refresh the display function for N lines  Support Three power mode: VDDI, AVDD, AVEE
 Display features  Supply voltage range
 supports Independently adjustable RGB Gamma  I/O supply voltage range for VDDI: 1.65V ~ 1.95V
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Correction  Analog supply voltage range for AVDD : 4.5V to 6.5V
 Support 1-dot/2-dot and Column/Zigzag LCD reversion  Analog supply voltage range for AVEE:-4.5V to -6.5V
modes  Output voltage levels
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 Built-in Focaltech CleverColor Image Processing  Source output voltage level: (GVDD~+0.2V) and
Function (-0.2V ~ NGVDD)
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 CleverColor – Color Enhancement3.0  Gamma voltage range: GVDD: 3.5V ~ 6.0V, NGVDD:
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 CleverColor – Color CABC4.0 -3.5v ~ -6.0V
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 CleverColor – AIE2.0  Positive gate driver voltage range for VGH:

 CleverColor – DGamma2.0 AVDD–AVEE, 2xAVDD-AVEE, 2AVDD-2xAVEE
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 CleverColor – Contrast Enhancement3.0  Negative gate driver voltage range for VGL: 2xAVEE,
2xAVEE-AVDD
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 Interface
 MIPI interface (DSI V1.2 and D-PHY V1.0, 2/3/4 lane)  Common electrode voltage range for VCOM:
+0.3V ~ ( VCL + 0.5V )
 On Chip Function
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 Built-in VCOM Generator

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Preliminary
FT8006S-AN
3. BLOCK DIAGRAM
3.1. Block Function
SX[576:1] S[2160:1]
GIP Driver GIP Driver

TP AFE
GOUT_L[22:1] (Left) (Right) GOUT_R[22:1]
LCD Source Driver
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AFE Digital
OSC GIP_Ctrl
Ctrl Gamma
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CleverColor
TP_SOC TCON
AIE WA CABC CE
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VGHO/VGHO1/VGHO2
VGLO/VGLO1/VGLO2
LCD Power Regfile Power Ctrl
VCL
Ctrl Core
VDD/LVDSVDD
Power
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VDD_TP
OTP
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Generator VDD5
VCOM_OPT
LCD_GPIO MIPI I/F
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I2C/SPI
TP_GPIO
I/F
PHY
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VDDI_TP
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AVDD
OTP_PWR
AVEE
I2C/SPI
VDDI
MIPI
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Preliminary
FT8006S-AN
3.1.1. System interface
FT8006S-AN supports the video data transmitted through the high-speed system interface, MIPI (Mobile Industry Processor Interface), and
I2C interface for the Touch point-reporting interface.
In normal operating mode, Touch controller scans the screen, and detects the touch actions. The defaults point-reporting Rate is set as
60Hz/120Hz, 90Hz/180Hz and can be adjusted up or down.
In touch detection mode, Touch controller enters low-power mode, and detects and scans touch-screen body. Detection scanning frequency
is 30Hz, can also be adjusted up or down. When into touch detection mode, majority of the algorithm will be terminated, and only a simple
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detection algorithm is retained to detect if there is a touch action happened. Whenever a touch is detected, Touch controller will immediately
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enter the normal operating mode.
In sleep mode, Touch controller enters ultra low-power standby mode, HOST can only wake-up Touch controller via "RESET" or "WAKEUP"
signal to enter the normal operating mode. The power consumption in this mode is extremely small, can greatly extend the standby time of
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mobile portable devices.
3.1.2. SX driver circuit
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Supply VCOM level when LCD driving. Generates TP sensing pulse when TP driving
3.1.3. AFE Controller

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AFE controller completes the driving and scanning of the sensors in the touch panel, and sends the data of touch sensors after scanning to
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the MCU for data processing.
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3.1.4. Embedded MCU

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MCU and SOC subsystems complete the control, data processing, LCD operation and coordination, HOST communication and other
functions of the whole touch systems. Firmware, stored in external flash memory, can be loaded into the internal SRAM by MCU via the SPI
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interface. Firmware can also be download from HOST through SPI interface without external FLASH required
3.1.5. I2C serial interface

FT8006S-AN supports I2C or SPI interface for touch communication with HOST. The control interface consists of two signals, INT and
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TP_EXT_RSTN. Whenever there is effective touch sensed on the touch screen, touch controller will send data transfer request to the HOST
via INT port, HOST can communicate with FT8006S-AN via I2C or SPI interface and gets the touch point report data. HOST can also reset
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Touch controller through TP_EXT_RSTN port.

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3.1.6. External Flash

External Flash, used to store the Firmware, and LCD initialization code, can be added into the Touch controller. Internal voltage regulator
generates 1.8V power supply, which is to provide power to an external 1.8V Flash
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3.1.7. Watch Dog

Watchdog clock is used to ensure the stability of the chip when in operation.
3.1.8. Timing Controller

FT8006S-AN has a timing controller, which can generate a timing signal for internal circuit operation such as gate/source/vcom output
timing, touch scan timing, etc.
3.1.9. Source driver circuit

FT8006S-AN consists of a 2160-output source driver circuit (S[1:2160]) and several source dummy outputs (SDUM[0:3]). Data transmitted
through MIPI video mode are latched when a single line data has been accumulated. And, then the latched data controls the source driver
and generates a drive waveform.

Preliminary
FT8006S-AN
3.1.10. Gate driver circuit

FT8006S-AN consists of output gate driver control circuit. The gate driver circuit outputs gate driver signals at either VGHO or VGLO level
3.1.11. Grayscale voltage generating circuit

FT8006S-AN has true 8-bit resolution D/A converter, which generates 256 Gamma-corrected values and cooperates with OP-AMP
structure to enhance display quality. The grayscale voltage can be adjusted by grayscale data set in the γ-correction register and RGB can
be adjusted separately.
3.1.12. Oscillator (OSC)
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FT8006S-AN also features an internal oscillator to generate RC oscillation with an internal resistor. In standby mode, RC oscillation is
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halted to reduce power consumption.
3.1.13. LCD driving power supply circuit
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The LCD driving power supply circuit generates the voltage levels AVDD, AVEE, VGH, VGL and VCOM for driving an LCD. All this voltages
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can be adjusted by register setting.
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Preliminary
FT8006S-AN
4. PIN DESCRIPTIONS
4.1. Pin Definition
PAD Type
Signal I/O Function
(Voltage Level)
Power Supply Pad
4.5V~6.5V.
AVDD P Analog Power
Connect a capacitor for stabilization
-4.5V~-6.5V.
AVEE P Analog Power
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Connect a capacitor for stabilization
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VDDI P Digital Power Power Supply for IO, 1.65V~1.95V.
VDDAM P Digital Power Power Supply for MIPI LDO, 1.65V~1.95V
AVSS P Analog Ground Ground for source, AFE.
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VSS P Digital Ground Ground for Digital Circuits
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LVDSVSS P Digital Ground Ground for Analog Circuits
VSSR P Analog Ground Ground for Reference & Regulator Blocks
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OTP_PWR P I/O Power Used for external power input for OTP program
DC-DC Convereter Pad
Positive Charge Pump Power.
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VGH O Internal Power
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Connect a capacitor for stabilization.
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Negative Charge Pump Power.

VGL O Internal Power
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VCI1 X Internal Power Dummy PAD

Negative Charge Pump Power.
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VCL O Internal Power

C21P/C21N Flying cap for VGH Charge Pump.
O Step-up capacitor
C22P/C22N Connected to a capacitor as requirement.
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Flying cap for VGL Charge Pump.

C31P/C31N O Step-up capacitor
Connected to a capacitor as requirement.
Short to VCI1 - Dummy PAD
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C41P/C41N X Step-up capacitor
C42P/C42N O Step-up capacitor IC internal short to VCL

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Regulator Pad
VGHO O Internal Power Switch output voltage generated from VGHO1/VGHO2 FPC Connect together
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Regulator output voltage generated from VGH.

VGHO1 O Internal Power
Regulator output voltage generated from VGH.
VGHO2 O Internal Power
VGLO O Internal Power Switch output voltage generated from VGLO1/VGLO2 FPC Connect together
Regulator output voltage generated from VGL.
VGLO1 O Internal Power
Regulator output voltage generated from VGL.
VGLO2 O Internal Power
Regulator output voltage, FPC Connect together
VDD O Internal Power
Regulator output voltage generate, FPC Connect together
LVDSVDD O Internal Power
Regulator output voltage. FPC Connect together
VDD_TP O Internal Power

Preliminary
FT8006S-AN
PAD Type
Signal I/O Function
(Voltage Level)
Regulator output voltage.
VREF O Internal Power
Connect a capacitor for stabilization. [Optional Capacitor for stabilization]
Regulator output voltage. FPC Connect together.
VREF_TP O Internal Power
VDD5 O Internal Power
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VCOM O Internal Power
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Connect a capacitor for stabilization. Capacitor must be in the middle of FPC.
VCOM_FB I Internal Power Feedback for VCOM circuit. Always short to VCOM
VCOM_OPT O Internal Power VCOM Optional Buffer Output.
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VCOMPASS_L
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-- -- Pass line for VCOM from ILB to OLB
VCOMPASS_R
GVDD O Internal Power Regulator output voltage (for positive gamma high voltage generator).
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NGVDD O Internal Power Regulator output voltage (for negative gamma high voltage generator).
LCD Interface Logic Pad
Global Reset Signal. Active Low.
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RESX I Digital (VDDI)
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IC Internal pull High
MIPI Lane Swap & Polarity control .
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MIPI Data Lane swap and polarity swap table

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PSWAP DSWAP[1:0] DSI-D2+ DSI-D2- DSI-D1+ DSI-D1- DSI-CLK+ DSI-CLK- DSI-D0+ DSI-D0- DSI-D3+ DSI-D3-
00 D3- D3+ D2- D2+ CLK- CLK+ D1- D1+ D0- D0+
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01 D3- D3+ D0- D0+ CLK- CLK+ D1- D1+ D2- D2+
0
PSWAP 10 D0- D0+ D1- D1+ CLK- CLK+ D2- D2+ D3- D3+
I Digital (VDDI)
DSWAP[1:0] 11 D2- D2+ D1- D1+ CLK- CLK+ D0- D0+ D3- D3+
00 D3+ D3- D2+ D2- CLK+ CLK- D1+ D1- D0+ D0-
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01 D3+ D3- D0+ D0- CLK+ CLK- D1+ D1- D2+ D2-
1
10 D0+ D0- D1+ D1- CLK+ CLK- D2+ D2- D3+ D3-
11 D2+ D2- D1+ D1- CLK+ CLK- D0+ D0- D3+ D3-
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IC Internal pull high

Interface Selection
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LANSEL[1:0] Interface Selection

00 Reserved
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LANSEL[1:0] I Digital (VDDI) 01 MIPI-2 Lane

10 MIPI-3 Lane
11 MIPI-4 Lane
IC Internal pull high
BIST mode enable, High Active
BIST_EN I Digital (VDDI)
IC Internal pull Low
LCD_GPIO can be set as TP_SYNC, LEDPWM,…etc
LCD_GPIO[8:0] I/O Digital (VDDI)
IC Internal pull Low
MIPI-DSI Interface input Signals
MIPI-DSI CLOCK differential signal input pins.
HISSI_CLK_P/N I MIPI (LVDSVDD)
If not used, Please connect to LVDSVSS.
MIPI-DSI Data differential signal input pins. (Data lane 0)
HISSI_D0_P/N I/O MIPI (LVDSVDD)
if not used , Please connect to LVDSVSS.
HISSI_D1_P/N I/O MIPI (LVDSVDD) MIPI-DSI Data differential signal input pins. (Data lane 1)

Preliminary
FT8006S-AN
PAD Type
Signal I/O Function
(Voltage Level)
TP Interface Logic Pad
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TP External reset signal., active LOW.
TP_EXT_RSTN I Digital (VDDI_TP)
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IC Internal pull High
Interface select . IC Internal pull Low.
BOOT_DEVICE I Digital (VDDI_TP)
0: I2C (boot with flash) ; 1: SPI (boot without flash)
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Global debug pin
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XI_TEST I/O Digital (VDDI_TP)
If not used, leave this pin open.
GPIO[0]: I2C_SCL / SPI_SCL clock pin, open drain@I2C mode, IC Internal pull
O en
High
GPIO[1]: I2C_SDA / SPI_MOSI pin, open drain@I2C mode, IC Internal pull High
TP_GPIO[4:0] I/O Digital (VDDI_TP)
GPIO[2]: SPI_MISO pin
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GPIO[3]: SPI SS (Chip Select) pin
GPIO[4]: INT/Wake pin
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CS O Digital (VDDI_TP) SPI Chip select signal to Flash

SCLK O Digital (VDDI_TP) SPI serial clock to Flash, MAX = 6MHz
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MOSI I/O Digital (VDDI_TP) SPI data output to Flash

尔 hC
MISO I/O Digital (VDDI_TP) SPI data input from Flash.

HOLD I/O Digital (VDDI_TP) HOLD signal to Flash, active LOW
WP I/O Digital (VDDI_TP) write protect signal to Flash, active LOW
韦 ec
Test Pad
POR12_T O Analog Power POR PAD, for test only, leave it open.
POR18_T O Analog Power POR PAD, for test only, leave it open.
博 lT
AFE_TEST[1:0] O Analog (AVDD) Analog Test Pin, not accessible to user. Must be left open.
麦 ca
VGH1 This pin is used to discharge function.

I Power Input
VGH2 If not used, please let this pin short to VGHO.
For gate signal(Group1) slope control usage. If user wants to use, please connect
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DCHG1_L/ DCHG1_R O Analog output

a resister. If not used, please tie it to VSS or open.
For gate signal(Group2) slope control usage. If user wants to use, please connect
DCHG2_L/ DCHG2_R O Analog output
a resister. If not used, please tie it to VSS or open.
LCD testmode, external clock input
LCD_EXT_OSC I Digital (VDDI)
IC Internal pull low
LCD_TSPO[7:0] O Digital (VDDI) LCD testmode output measurement for digital circuit
LCD testmode selection for digital circuit
LCD_TSPI_DEN[14:0] I Digital (VDDI)
IC Internal pull low.
LCD testmode selection for analog circuit
LCD_TSPI_AEN[2:0] I Digital (VDDI)
IC Internal pull low.
LCD_TEST_P O Analog output LCD testmode output measurement for analog circuit
LCD_TEST_N O Analog output LCD testmode output measurement for analog circuit
Driving Pad
S[2160:1] O Analog (AVDD) Source Output

Preliminary
FT8006S-AN
PAD Type
Signal I/O Function
(Voltage Level)
SDUM[3:0] O Analog (AVDD) Source Dummy Pin ( For ZigZag Panel)
SX[576:1] O Analog (AVDD) Seperate COM Electrode (TP Sensor Pins)
SXDUM1/
O Analog (AVDD) TP Dummy Pin
SXDUM2
GOUT_L[22:1] / Analog
O GOA Output. Please use GOUT[13:6] for CLK application.
GOUT_R[22:1] (VGH/VGL)
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Cascade Pad
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EXT_VCOM_EN I Digital (VDDI) External VCOM Enable, “H”=Using external VCOM, ‘L’=Using internal VCOM
4.2. Power Block Diagram
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Preliminary
FT8006S-AN
4.3. Power Supply Configuration
VGH = 7.3V ~ 20.0V (0.1V/Step)

VGHO2 = 7.3V ~ 20V
VGHO1 = VGHO2 - VTP
AVDD = External Power (4.5~6.5V)
VDD5 = 4.5V
GVDDP = 3.5V ~ 6.0V (10mV/Step)
VREF_TP = 3.5V
VDDI = VDDAM =1.65V ~ 1.95V
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VREF = 2.0V
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VDD_TP VDD LVDSVDD
VSS = AVSS = LVDSVSS = VSSINT = VSSDIS = 0V
VCOM = 0.3V~-2.5V (10mV/Step)

VCL = -2V ~-4.5V
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GVDDN = -3.5V ~ -6.0V (10mV/Step)
AVEE = External Power (-4.5~-6.5V)

VGLO2 = -5.3V ~ -18V
O en
VGLO1 = VGLO2 - VTP
VGL = -5.3V ~ -18.0V (0.1V/Step)
VTP can setting from 1.5V to 5V by the register setting.
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Preliminary
FT8006S-AN
4.4. Application Circuit
Note: It‟s for design reference only! User should contact our sales or FAE for suitable circuit design in actual case.
VD D
LVDSVDD
VD D_TP
VR EF_TP
VD D5
VC OM
VGLO
VGL
VGHO
VGH
VD DI_TP
VD DAM
AVEE
AVDD
X1
MIPI Input
FPC (F T8006SAN)
RESX
LEDPW M_1
TP_EXT_R STN
IN T
SD A
SC L
TE
VD DI
AVDD
AVEE
LEDK3
LEDK2
LEDK1
26 7
26 6 DUMMY
26 5 DUMMY
26 4 DUMMY
26 3 DUMMY
26 2 DUMMY
VDDI 26 1 DUMMY
C0 402 26 0 DUMMY
4.7uF/ 10V 4.7uF/ 10V 4.7uF/ 10V 1uF/25V

25 9 DUMMY
C1
38
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
DUMMY
CN 1
GN D
RESX
LEDPW M
TP_EXT_R STN GN D
IN T
SD A
SC L
TE
GN D
VD DI
NC
AVDD
NC
AVEE
RT
LEDK3
LEDK2
LEDK1
GN D
AV DD
C0 402 25 8
25 7 DUMMY
C2
25 6 DUMMY
25 5 DUMMY
AV EE 25 4 DUMMY
C0 402 25 3 VS S_2
CLKN
CLKP
LEDA
GN D
GN D
GN D
GN D
GN D
GN D
VDDI_2
D3N
D0N
D1N
D2N
D3P
D0P
D1P
D2P
25 2
C3
NC
25 1 DUMMY [3]
25 0 DUMMY [3]
SY NC_ TP_ DAT_R6_ 2
37
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
36
C2 1N C2 1P 24 9
GN D
C0 402 24 8 DCHG2 _R
24 7 DCHG1 _R
C4 24 6 VG HO_ 3
24 5 VG H2
D3_N
D3_P
D0_N
D0_P
CLK_N
CLK_P
D1_N
D1_P
D2_N
D2_P
LEDA
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C2 2N C2 2P 24 4 VG H1_ 3
C0 402 24 3 GND
1uF/25V
24 2 GND
C5
24 1 GND
24 0 GND
GND
Fo
VG H 23 9
C0 402 23 8 GND
1uF/25V
23 7 GND
C6
23 6 AV SS_ 8
23 5 AV SS_ 8
C3 1N C3 1P 23 4 AV DD_ 7
C0 402 23 3 AV DD_ 7
1uF/25V
23 2 VDD5_ 3
LEDPW M
VD DI
C7
23 1 VREF_ TP_ 5
23 0 VDD_TP_3
Flash
VG L 22 9 VS S_3
C0 402 22 8 VCOM_ PAS S_R_4
1uF/25V
22 7 VCOM_ 3
C8
22 6 VCOM_ 6
R1
22 5 VCOM_ 6
WP
MI SO
CS
C4 1N C4 1P 22 4 VCOM_ OP T_4
C0 402 22 3 VCOM_ OP T_4
R0402
1k ohm
1uF/25V
22 2 AV EE_ 6
C9
22 1 AV EE_ 6
22 0 AV SS_ 6
VCI1 21 9 AV SS_ 6
LEDPW M_1
VD DAM
VD DI_TP
AFE_TEST4
4
3
2
1
C0 402 21 8
U1
1uF/6. 3V
21 7 AFE_TEST3
C10
GN D
/W P(IO2)
DO(IO1)
/C S
AFE_TEST2
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21 6
21 5 AFE_TEST1
MX25R2035FZUIL0
21 4 AFE_TEST0
C4 2N C4 2P 21 3 VG LO_ 6
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C0 402 21 2 VG LO_ 6
MX25R 2035FZ UIL0
1uF/25V
VG LO1 21 1 VG LO1 _6
C11
Capacitance
21 0 VG LO1 _6
/H OLD (IO3) 6
VG LO2 20 9 VG LO2 _6
VCL 20 8 VG LO2 _6
USON 8-8PIN
DI (IO0)
C0 402 20 7 VG L_6
1uF/6. 3V 1uF/6. 3V 2.2uF/ 6.3V
VC C 7
VG L_6
CLK 5
20 6
C12
C3 1N 20 5 C3 1N_ 6
20 4 C3 1N_ 6
C3 1P_ 6
8
VREF C3 1P 20 3
C0 402 20 2 C3 1P_ 6
20 1 AV DD_ 3
C13
20 0 AV SS_ 3
19 9 AV EE_ 8
SC LK
MOSI
HOLD
VD DI
VDD 19 8 AV EE_ 8
C0 402 C4 2N 19 7 VCL(C4 2N) _6
19 6 VCL(C4 2N) _6
C14
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C4 2P 19 5 VCL(C4 2P) _6
19 4 VCL(C4 2P) _6
19 3 AV SS_ 6
LV DSV DD 19 2 AV SS_ 6
GN D
C0 402 VCL 19 1 VCL_6

2.2uF/ 6.3V
19 0 VCL_6
C15
C0 402 18 9 VDDI_TP_1 2
1uF/6. 3V
18 8 VDDI_TP_1 2
C29
18 7 VS S_6
VG HO1 18 6 VS S_6
C0 402 NG VDD 18 5 DUMMY _3
1uF/25V
GV DD 18 4 NG VDD_3
C16
VREF 18 3 GV DD_ 3
18 2 VREF_ 5
VG HO2 18 1 VS SR_ 5
C0 402 18 0 VS SR_ 5
1uF/25V
17 9 VREF_ TP_ 7
C17
17 8 AV SS_ 6
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17 7 AV SS_ 6
VG LO1 17 6 AV DD_ 7
C0 402 17 5 AV DD_ 7
LED Connector
1uF/25V
y
17 4 VCOM_ 7
C18
17 3 VCOM_ 7
17 2 VDDI_6
VG LO2 17 1 VDDI_6
C0 402 17 0 VDD_TP_6
LED_C N
1uF/25V
16 9 VDD_TP_6
C19
16 8 VS S_6
INT 16 7 VS S_6
CN 2
VCOM TP _GP IO3 16 6 TP _GP IO[4 ]_2

TP _GP IO[3 ]_2
4
3
2
1
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C0 402 TP _GP IO2 16 5
10uF/6.3V 2.2uF/ 10V
SDA 16 4 TP _GP IO[2 ]_2

C20
SCL 16 3 TP _GP IO[1 ]_2

TP _EX T_RSTN 16 2 TP _GP IO[0 ]_2
LEDK1
LEDK2
LEDK3
LEDA
VDD5 WP 16 1 TP _EX T_RSTN

C0 402 HO LD 16 0 FL ASH_WP
MISO 15 9 FL ASH_HO LD
C21
MO SI 15 8 FL ASH_MIS O
SCLK 15 7 FL ASH_MO SI
View
FT8006SAN Panel TOP
CS 15 6 FL ASH_SCLK
VREF_ TP 15 5 FL ASH_CS
C0 402 BO OT_ DEV ICE 15 4 X1 _TE ST
2.2uF/ 10V
15 3 BO OT_ DEV ICE

C22
15 2 PO R18 _T
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15 1 PO R12 _T
15 0 DUMMY
VDD_TP 14 9 VDDI_2
C0 402 14 8 VS S_2
2.2uF/ 6.3V
14 7 VDDI_2
C23
RE SX 14 6 DUMMY
14 5 RE SX
14 4 EX T_V COM_EN
RB 521 CS-3 0 GV DD 14 3 DUMMY
Protection
尔 hC
C0 402 14 2 LA NSE L[1]

1uF/10V
AV EE VG L 14 1 LA NSE L[0]
C24
14 0 PS WAP
13 9 DS WAP [1]
D1
NG VDD 13 8 DS WAP [0]

C0 402 13 7 BIS T_E N
1uF/10V
13 6 LCD_G PIO [7]_2

C25
13 5 LCD_G PIO [6]_2

13 4 LCD_G PIO [5]_2
LE DPWM 13 3 LCD_G PIO [4]_2
VDDI_TP TE 13 2 LCD_G PIO [3]_2
C0 402 LCD_S DA 13 1 LCD_G PIO [2]_2
2.2uF/ 6.3V
LCD_S CL 13 0 LCD_G PIO [1]_2

C26
12 9 LCD_G PIO [0]_2

12 8 VDDI_2
12 7 VDDI_2
VG HO 12 6 VS S_2
C0 402 12 5 VS S_2
(N C)
12 4 AV EE_ 6
C27
12 3 AV EE_ 6
12 2 AV DD_ 6
Setting Pin(VDDI/GND)
VG LO 12 1 AV DD_ 6
C0 402 12 0 AV SS_ 6
GN D
VD DI
(N C)
11 9 AV SS_ 6
C28
11 8 VDDI_6
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11 7 VDDI_6
11 6 VDD_6
R0 201 R0 201 11 5 VDD_6
11 4 VS S_6
BOOT_DEVICE
VS S_6
0R
R3
N. C.
R2
11 3
11 2 VDDAM_4
11 1 LV DSV DD_ 3
11 0 LV DSV SS_ 3
D3 _N 10 9 LV DSV SS_ 3
D3 _P 10 8 DA TA3 N_6
10 7 DA TA3 P_6
D0 _N 10 6 LV DSV SS_ 2
D0 _P 10 5 DA TA0 N_6
10 4 DA TA0 P_6
CL K_N 10 3 LV DSV SS_ 2
CL K_P 10 2 CL KN_ 6
CL KP_ 6
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10 1
10 0 LV DSV SS_ 2
D1 _N 99 LV DSV SS_ 2
D1 _P 98 DA TA1 N_6
97 DA TA1 P_6
D2 _N 96 LV DSV SS_ 2
D2 _P 95 DA TA2 N_6
94 DA TA2 P_6
93 LV DSV SS_ 3
92 LV DSV DD_ 3
91 VDDAM_4
90 DUMMY _3
89 VS S_6
88 VS S_6
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87 VDD_6
86 VDD_6
85 VDDI_1 0
84 VDDI_1 0
83 VDD_6
82 VDD_6
81 VS S_6
80 VS S_6
79 AV SS_ 5
78 AV SS_ 5
C4 1N 77 C4 1N_ 6
76 C4 1N_ 6
C4 1P 75 C4 1P_ 6
74 C4 1P_ 6
VCI1 73 VCI1_6
72 VCI1_6
71 AV DD_ 5
Fo
70 AV DD_ 5
C2 2N 69 C2 2N_ 6
68 C2 2N_ 6
C2 2P 67 C2 2P_ 6
66 C2 2P_ 6
ESD Protection
65 AV SS_ 3
LE SD9 D5.0 CT5 G 64 AV EE_ 3
RE SX 63 AV DD_ 6
SO D-9 23 62 AV DD_ 6
C2 1N 61 C2 1N_ 6
TVS1
60 C2 1N_ 6
C2 1P 59 C2 1P_ 6
LE SD9 D5.0 CT5 G 58 C2 1P_ 6
VDDI 57 VG H_6
SO D-9 23 56 VG H_6
55 AV DD_ 6
TVS2
54 AV DD_ 6
VG HO2 53 VG HO2 _6
RClamp 082 1P 52 VG HO2 _6
AV DD VG HO1 51 VG HO1 _6
SL P10 06P2 50 VG HO1 _6
49 VG HO_ 6
TVS3
OTP_P WR 48 VG HO_ 6
47 OTP_P WR
RClamp 082 1P 46 OTP_P WR
AV EE 45 AV SS_ 6
SL P10 06P2 44 AV SS_ 6
43 AV EE_ 6
TVS4
42 AV EE_ 6
41 VCOM_ OP T_4
相關接腳請參考上圖
BOOT_DEVICE= 1：non-Flash IC/ SPI 接腳
BOOT_DEVICE= 0：Flash IC/ I2C 接腳
40 VCOM_ OP T_4
39 VCOM_ 6
38 VCOM_ 6
37 VCOM_ PAS S_L _4
36 VS S_3
35 VDD_TP_3
34 VREF_ TP_ 5
TEST PAD
33 VDD5_ 3
32 AV DD_ 7
OTP_PWR
TP_RSTN
TP_GPIO2
TP_GPIO3
31 AV DD_ 7
30 AV SS_ 8
29 AV SS_ 8
28 GND
27 GND
26 GND
25 GND
24 GND
Date:
Size
Tit le
23 GND
Custom<D oc>
GND
1 OTP_PWR
1TP_GPIO2
1TP_GPIO3
22
21 VG H1_ 3
VG H2
TP_EXT_R STN
20
Docum ent Num ber
19 VG LO_ 3
Monday , May 24, 2021
18 DCHG1 _L
17 DCHG2 _L
16 SY NC_ TP_ DAT_L6_ 2
15 DUMMY
14 DUMMY
13 VDDI_2
12 VS S_2
LC D_SCL
LC D_SDA
VGLO
VGHO
11 DUMMY
10 DUMMY
9 DUMMY
DUMMY
8
7 DUMMY
Sheet
6 DUMMY
DUMMY
1 LC D_SCL
1 LC D_SDA
1VGLO
1VGHO
5
4 DUMMY
3 DUMMY
2 DUMMY
1
1 DUMMY
0 DUMMY
DUMMY
of
GN D
1
Rev
<V04>

Preliminary
FT8006S-AN
5. INSTRUCTION
5.1 Outline
FT8006S-AN supports high speed serial interface, MIPI, to configure system via accessing command register. When the command
register is executed, sending the command information to specify which index register would be accessed and following the data to that
control register. The MIPI-DSI is compliant with MIPI Alliance Standard for Display Serial Interface (DSI), Version 1.2 and D-PHY Version
1.1.
FT8006S-AN has the following major categories of instructions:

(1). System function instructions (User Command Set).
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(2). Customer Command List and Description (Manufacturer Command Set / Command 2).
These instructions are asynchronous to the FT8006S-AN internal clock, requiring no wait cycles. Because the writing of instruction data
does not interfere with the host controller processing, instructions can be handles smoothly and efficiently. The following describes details of
instruction settings.
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5.1.1 System function command list and description
After the H/W reset by RESX pin or S/W reset by SWRESET command, each internal register becomes default state (Refer “RESET
O en
TABLE” section). Commands 28h and 29h are updated during V-Blanking to avoid abnormal visual effects. By the way, all commands in
master and slave side can be updated concurrently during V-Blanking via MIPI DSI v1.2 FSC function.
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System function command access flow is described as following example.
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Example 1: Sleep Out

Address 0x11
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Example 2: Display On
Address 0x29
Example 3: Bypass Mode

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Address 0x09
DATWR 0x01
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Preliminary
FT8006S-AN
5.1.2 System function command list
BankSel Write/Read Paramter
Command (Hex) Function MIPI Transmission
[5:0] /Command Number
SWRESET - 01h C Software reset 0 LPDT/HSDT
BIST_MODE - 02h W/R Enter BIST Mode 1 LPDT/HSDT
RDDPM - 0Ah R Read Display Power Mode 1 LPDT/HSDT
SLPIN - 10h C Sleep-In 0 LPDT/HSDT
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SLPOUT - 11h C Sleep-Out 0 LPDT/HSDT
DEEP_STBY 17h W/R Enter Deep Standby Mode 1 LPDT/HSDT
DISP_OFF - 28h C Display off 0 LPDT/HSDT
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DISP_ON - 29h C Display on 0 LPDT/HSDT
OTP_STOP_RELOAD - 41h W/R OTP Stop Reload Enable 1 LPDT/HSDT
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EXT_ADR - 42h W/R Extended Address of Command Interface 1 LPDT/HSDT
OTP_CTRL_STATUS - 48h W/R OTP Control & Status 1 LPDT/HSDT

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FSC_CTRL - 4Ah W MIPI FSC Function Control 1 LPDT/HSDT
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DISBV_SET - 51h W Display Brightness Value Setting 1 LPDT/HSDT
DISBV_RD - 52h W/R Read Display Brightness Value 1 LPDT/HSDT

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DISBV_CTRL - 53h W/R Display Brightness Value Control 1 LPDT/HSDT

尔 hC
RDDISBV_CTRL - 54h R Read Display Brightness Value Control 1 LPDT/HSDT
WRFCC_CABC - 55h W Write Content Adaptive Brightness Control 1 LPDT/HSDT
RDFCC_CABC - 56h R Read Content Adaptive Brightness Control 1 LPDT/HSDT

韦 ec
OTP_PROG - 58h W/R OTP Program 1 LPDT/HSDT

博 lT
WRCABC_MDISBV - 5Eh W Write CABC Minimum Brightness 1 LPDT/HSDT
RDCABC_MDISBV - 5Fh W/R Read CABC Minimum Brightness 1 LPDT/HSDT

麦 ca
13
RDDDB 2F A1h R Read DDB Start LPDT/HSDT
*Note2
Fo
RDID_DA 2F DAh R Read ID_DA in OTP 1 LPDT/HSDT
RDID_DB 2F DBh R Read ID_DB in OTP 1 LPDT/HSDT
RDID_DC 2F DCh R Read ID_DC in OTP 1 LPDT/HSDT
Note: LPDT (Low Power Mode), HSDT (High Speed Mode)

Note 2: The maximum number for the sum of RDDDBS‟s and RDDDBC‟s parameter length is 13. For example, RDDDBS‟s parameter
length is 5, and RDDDBC‟s parameter length is 8.

Preliminary
FT8006S-AN
5.2 System Function Command Description
5.2.1 SWRESET (01h): Software Reset
Bank -
Parameter Address D7 D6 D5 D4 D3 D2 D1 D0 Default
01H (SWRST) No Parameter -
Description
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SWRST：Software Reset
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Address = „01H‟
- When the Software Reset command is written, it causes a software reset to display only.
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- It resets the commands and parameters to their reset default values and all source & gate outputs are set to VSS (display off).
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(See default tables in each command description)
Restriction：
O en
- It will be necessary to wait 100msec before sending new command following software reset.
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- The display module loads all display supplier‟s factory default values to the registers during 100msec.
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韦 ec
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Preliminary
FT8006S-AN
5.2.2 BIST_MODE (02H): Enter BIST mode
Bank-
02H reg_bist_en[7:0] A5h
Description
reg_bist_en[7:0]：
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- This command is used to set BIST Mode function
„5Ah‟ = Enter BIST Mode.
„Others‟ = Exit BIST Mode.
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Restriction：
O en
- Both register software setting and I/O hardware pin can enter BIST Mode function. (Control ORed)
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Preliminary
FT8006S-AN
5.2.3 RDDPM (0AH): Read Display Power Mode
Bank-
0AH BSTON 0 0 SLPOUT 1 DISON 0 0 08h
Description
This command indicates the current status of the display as described in the table below:
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Fo
Bit Description Value
BSTON Booster Voltage Status “1”=Booster On
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“0”=Booster Off
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D6 Not Used 0
D5 Not Used 0
O en
SLPOUT Sleep In/Out “1” = Sleep Out,
“0” = Sleep In
D3 Not Used 1
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DISON Display On/Off “1” = Display On,
“0” = Display Off
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D1 Not Used 0
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D0 Not Used 0
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Preliminary
FT8006S-AN
5.2.4 SLPIN (10H) & SLPOUT (11H) : Sleep-In & Sleep-Out
Bank-
10H (SLPIN) No Parameter -
11H (SLPOUT) No Parameter -
Description
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SLPIN：Sleep-In (Enter Standby Mode)
Address = „10H‟
- This command causes the LCD module to enter the power consumption reduced mode.
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- In this mode, internal display oscillator is stopped, and panel scanning is stopped.
- Only the command path are still working to support the exit from Standby Mode.
O en Sleep In
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Internal Oscillator Stop
U nf
Gate Output Stop Stop

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尔 hC
Source Output Stop Stop

韦 ec
博 lT
Restriction：
麦 ca
- This command has no effect when module is already in sleep in mode. Standby Mode can only be exit by the SLPOUT Command (11H).
Fo

Preliminary
FT8006S-AN
SLPOUT：Sleep-Out (Exit Standby Mode)
Address = „11H‟
- This command causes the LCD module to exit the power consumption reduced mode.
- In this mode, internal display oscillator is started, and panel scanning is started.
Sleep Out
Internal Oscillator Stop Start
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Gate Output Stop Stop
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Source Output Stop Stop
O en
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Restriction：
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- This command has no effect when module is already in sleep out mode.
o
- Sleep Out Mode can only be exit by the SLPIN Command (10H).
尔 hC
韦 ec
博 lT
麦 ca
Fo

Preliminary
FT8006S-AN
5.2.5 DEEP_STBY (17H/18H) : Enter Deep Standby Mode
Bank-
17H DEEP_STBY0[7:0] 00h
18H DEEP_STBY1[7:0] 00h
Description
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- These two command are used to set Deep Standby Mode function.
- There are 2 methods that can enter Deep Standby State：
Method 1 : Set DEEP_STBY0[7:0] = 5Ah and DEEP_STBY1[7:0] = 5Ah in any state.
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Method 2 : Set DEEP_STBY0[7:0] = A5h and DEEP_STBY1[7:0] = A5h when Sleep In Mode.
O en
Restriction：
- Only Hardware Reset can exit Deep Standby Mode, and it will be necessary to wait 100msec before sending new command following
se id
hardware reset.
y
- The display module loads all display supplier‟s factory default values to the registers during 100msec.
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o
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韦 ec
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Preliminary
FT8006S-AN
5.2.6 DISPLAY_CTRL (28H/29H) : Display Control
Bank-
28H (DISPOFF) No Parameter -
29H (DISPON) No Parameter -
Description
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DISPOFF：Display Off
Address = „28H‟
- This command is used to enter into DISPLAY OFF mode. In this mode, the output from the Memory is disables and blank page is
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inserted.
- This command does not change any other status.
O en
- There will be no abnormal visible effect on the display.
- Exit from this command by Display On (29H)

se id
y
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(Example)
Memory Display
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尔 hC
韦 ec
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麦 ca
Restriction：
-This command has no effect when module is already in Display Off mode.
Fo

Preliminary
FT8006S-AN
DISPON：Display On
Address = „29H‟
- This command is used to recover from DISPLAY OFF mode. Output from the Memory is enabled.
- This command does not change any other status.
(Example)
Memory Display
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Restriction：
y
- This command has no effect when module is already in Display On mode.
U nf
o
尔 hC
韦 ec
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麦 ca
Fo

Preliminary
FT8006S-AN
5.2.7 OTP_STOP_RELOAD (41H/4EH): OTP Stop Reload Enable
Bank-
41H OTP_STOP_RELOAD_MIPI[7:0] 00h
4EH OTP_STOP_RELOAD_MCU[7:0] 00h
Description
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OTP_STOP_RELOAD_MIPI：OTP Stop Reload Enable for MIPI used.
- This command is used to enable OTP stop reload function
„5Ah‟ : Stop OTP reload and switch bus to external interface.
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„Others‟ : Enable OTP reload and switch bus to reload controller.
O en
OTP_STOP_RELOAD_MCU：OTP Stop Reload Enable for MCU used.
- This command is used to enable OTP stop reload function

se id
„5Ah‟ : Stop OTP reload and switch bus to external interface.
y
„Others‟ : Enable OTP reload and switch bus to reload controller.
U nf
o
尔 hC
韦 ec
博 lT
麦 ca
Fo

Preliminary
FT8006S-AN
5.2.8 EXT_ADR (42H): Extended Address of Command Interface
Bank-
42H Bank_Sel[5:0] 2Fh
Description
Bank_Sel[5:0]：Bank Selection of following command groups for I2C, MIPI and SYSTEM interface.
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- This command is used to set extended address of I2C, MIPI and SYSTEM interface.
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韦 ec
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Preliminary
FT8006S-AN
5.2.9 OTP_CTRL_STATUS (48H): OTP Control & Status
Bank-
OTP_LOAD OTP_RELO SPI_LOAD_

48H Reserved Reserved OTP_OP_MODE[2:0] 00h
_FINISH AD_FINISH FINISH
Description
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OTP_LOAD_FINISH (Read-Only)：OTP Initial Load Finish Flag
„1‟ = OTP initial load finish
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OTP_RELOAD_FINISH (Read-Only)：OTP Reload Finish Flag
„1‟ = OTP reload finish
O en
SPI_LOAD_FINISH (Read-Only)：SPI Flash Load Finish Flag
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„1‟ = SPI flash load finish
y
U nf
OTP_OP_MODE：OTP Operation Mode

o
„000‟ = Normal Mode

尔 hC
„001‟ = Room Temp. Initial Margin Read
„010‟ = Program Mode
„011‟ = High Temp. Initial Margin Read

韦 ec
„100‟ = Room Temp. PGM Margin Read
„110‟ = High Temp. PGM Margin Read

博 lT
麦 ca
Fo

Preliminary
FT8006S-AN
5.2.10 FSC_CTRL (4AH/4BH) : MIPI FSC Function Control
Bank-
4AH FSC_IN_EN[7:0] 00h
4BH FSC_STOP_LOAD[7:0] 00h
Description
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Fo
FSC_IN_EN：MIPI FSC Input Duration Enable
- This command is used to enable MIPI FSC input duration.
- When this function is enable, the following MIPI commands will be placed in internal FIFO queue until receiving an Execute Queue
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Command.
„5Ah‟ = Enable MIPI FSC input duration.
O en
„Others‟ = Disable MIPI FSC input duration.
se id
y
FSC_STOP_LOAD：Stop load MIPI FSC from FIFO
U nf
- This command is used to stop load MIPI FSC from internal FIFO queue.
o
„5Ah‟ = Stop load MIPI FSC from FIFO.

尔 hC
„Others‟ = Normal operation that follow MIPI DSI v1.2 FSC definition.
韦 ec
博 lT
麦 ca
Fo

Preliminary
FT8006S-AN
5.2.11 DISBV_SET (51H/52H): Display Brightness Value Setting
Bank-
51H DBV[11:4] FFh
52H Reserved DBV[3:0] FFh
Description
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- This command is used to adjust the brightness value of the display.
- It should be checked what is the relationship between this written value and output brightness of the display.
This relationship is defined on the display module specification.
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- In principle relationship is that 000h value means the lowest brightness and FFFh value means the highest brightness.
O en
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Preliminary
FT8006S-AN
5.2.12 DISBV_RD (52H/53H): Read Display Brightness Value
Bank-
52H DBV[11:4] FFh
53H Reserved DBV[3:0] FFh
Description
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- This command returns the brightness value of the display.
- This command can be used to read the brightness value of the display also when Display brightness control is in automatic mode.
- It should be checked what the relationship between this returned value and output brightness of the display. This relationship is defined on
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the display module specification.
- In principle the relationship is that 000h value means the lowest brightness and FFFh value means the highest brightness.
O en
- DBV[11:0] is reset when display is in sleep-in mode.
- DBV[11:0] is „0‟ when bit BCTRL of “Display Brightness Value Control (53H)” command is „0‟.
se id
- DBV[11:0] is manual set brightness specified with “Display Brightness Value Control (53H)” command when bit BCTRL is „1‟.
y
- See command “Display Brightness Value Setting (51H)”.
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o
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韦 ec
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Fo

Preliminary
FT8006S-AN
5.2.13 DISBV_CTRL (53H): Display Brightness Value Control
Bank-
53H Reserved BCTRL Reserved DD BL Reserved 00h
Description
- This command is used to control ambient light, brightness and gamma settings.
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BCTRL：Brightness Control Block On/Off. This bit is always used to switch brightness for display and keyboard.
„0‟ = Off (Brightness registers are 00h)
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„1‟ = On (Brightness registers are active, according to the other parameters.)
O en
DD：Display Dimming
- Dimming function is adapted to the brightness registers for display and keyboard when bit BCTRL is changed at DD=1,
se id
e.g. BCTRL: 0 -> 1 or 1-> 0.
y
„0‟ = Display Dimming is off
U nf
„1‟ = Display Dimming is on

o
尔 hC
BL：Backlight On/Off
- When BL bit change from “On” to “Off”, backlight is turned off
„0‟ = Off (Completely turn off backlight circuit. Control lines must be low. )
韦 ec
„1‟ = On
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Fo

Preliminary
FT8006S-AN
5.2.14 RDDISBV_CTRL (54H): Read Display Brightness Value Control
Bank-
54H Reserved BCTRL Reserved DD BL Reserved 00h
Description
- This command returns ambient light and brightness control values, see command “Display Brightness Value Control (53H) ”.
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BCTRL: Brightness Control Block On/Off. This bit is always used to switch brightness for display.
„0‟ = Off
„1‟ = On
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...
DD: Display Dimming
O en
„0‟ = Display Dimming is off
„1‟ = Display Dimming is on

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...
y
BL: Backlight On/Off, This bit is always controlled by the user
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„0‟ = Off (completely turn off backlight circuit)

o
„1‟ = On
尔 hC
韦 ec
博 lT
麦 ca
Fo

Preliminary
FT8006S-AN
5.2.15 WRFCC_CABC (55H): Write Focal CleverColor – Content Adaptive Brightness Control
Bank-
55H Reserved CABC_MODE[1:0] 00h
Description
- This command is used to set parameters for power functionality.
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- There is possible to use 3 different modes for content adaptive image functionality, which are defined on a table below.
CABC_MODE Function Note
0h Power Save Off CABC Off
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1h Power Save Low User Interface Image(UI)
2h Power Save Medium Still Picture(ST)
O en
3h Power Save High Moving Image(MV)
CABC = Content Adaptive Brightness Control

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Fo

Preliminary
FT8006S-AN
5.2.16 RDFCC_CABC (56H): Read Focal CleverColor – Content Adaptive Brightness Control
Bank-
56H Reserved CABC_MODE[1:0] 00h
Description
- This command returns for power functionality see command “Write Focal CleverColor – Content Adaptive Brightness Control (55H) ”.
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韦 ec
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Fo

Preliminary
FT8006S-AN
5.2.17 OTP_PROG (58H/59H/5AH) : OTP Program
Bank-
58H OTP_PROG_START[7:0] 00h
5AH OTP_PROG_UNLOCK[7:0] 00h
Description
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OTP_PROG_UNLOCK：OTP Programming Function Unlock
- This command is used to set OTP programming function unlock.
„96h‟ = Unlock OTP programming function.
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„Others‟ = Lock OTP programming function.
O en
OTP_PROG_START：OTP Bank Programming Start
se id
- This command is used to set OTP bank programming start.
y
- When OTP bank programming is done, register value will be set to EDh.
U nf
„AAh‟ = Start OTP bank programming.

o
„Others‟ = Not programming.

尔 hC
韦 ec
博 lT
麦 ca
Fo

Preliminary
FT8006S-AN
5.2.18 WRCABC_MDISBV (5EH/5FH) : Focal CleverColor – Write CABC Minimum Display Brightness Value
Bank-
5EH CMB[11:4] 00h
5FH Reserved CMB[3:0] 00h
Description
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Fo
- This command is used to set the minimum brightness value of the display for CABC function.
- In principle relationship is that 000h value means the lowest brightness for CABC and FFFh value means the highest brightness for
CABC.
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Preliminary
FT8006S-AN
5.2.19 RDCABC_MDISBV (5FH/60H) : Focal CleverColor – Read CABC Minimum Display Brightness Value
Bank-
5FH CMB[11:4] 00h
60H Reserved CMB[3:0] 00h
Description
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Fo
- This command returns the minimum brightness value of CABC function.
- In principle the relationship is that 000h value means the lowest brightness and FFFh value means the highest
brightness.
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- See command “Write CABC Minimum Brightness (5EH)”.
O en
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y
U nf
o
尔 hC
韦 ec
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麦 ca
Fo

Preliminary
FT8006S-AN
5.2.20 RDDDB (A1H/A8H) : Read DDB Start & Read DDB Continue
Bank2F (Default Bank)
A1H (RDDDBSTR) No Parameter -
A8H (RDDDBCNT) No Parameter -
Description
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RDDDBSTR：Read DDB Start
Address = „A1H‟
- The RDDDBSTR command reads identifying and descriptive information from the peripheral. This information is organized in the Device
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Descriptor Block (DDB) stored on the peripheral.
O en
RDDDBCNT：Read DDB Continue
Address = „A8H‟
se id
- This RDDDBCNT command returns supplier‟s identification and display module model/revision information from the point where
y
RDDDBSTR command was interrupted by another command.
U nf
o
RDDDBSTR & RDDDBCONT should cooperate with MIPI short packet : Set Maximum Return Packet Size. Before these two commands,
尔 hC
the Set Maximum Return Packet Size packet should be sent in advance to set the numbers of returned reading data.
- The content of returned data is as follows:

韦 ec
Parameter 1: ID0 in OTP.

博 lT

麦 ca

Fo
Parameter 11: ID_DA in OTP.
Parameter 12: ID_DB in OTP.
Parameter 13: ID_DC in OTP.

Preliminary
FT8006S-AN
Restriction：
- RDDDBSTR & RDDDBCONT commands are supported through MIPI interface only.
- A RDDDBSTR command should be executed at least once before a RDDDBCONT command to define the read location. Otherwise, data
read with a RDDDBCONT command is undefined.
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Preliminary
FT8006S-AN
5.2.21 RDID_DA (DAH) : Read ID_DA in OTP
DAH ID_DA[7:0] 00h
Description
- This read byte identifies the display module‟s manufacturer.
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Preliminary
FT8006S-AN
5.2.22 RDID_DB (DBH) : Read ID_DB in OTP
DBH ID_DB[7:0] 00h
Description
- This read byte is used to track the display module/driver version. It is defined by display supplier (with agreement) and
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changes each time a revision is made to the display, material or construction specifications.
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Preliminary
FT8006S-AN
5.2.23 RDID_DC (DCH) : Read ID_DC in OTP
DCH ID_DC[7:0] 00h
Description
- This read byte is used to track the display module/driver version. It is defined by display supplier (with agreement) and
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changes each time a revision is made to the display, material or construction specifications.
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Preliminary
FT8006S-AN
6. FUNCTIONS
6.1. Interface Architecture
FT8006S-AN can support direct mode architecture for MIPI interface.
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Preliminary
FT8006S-AN
6.2. MIPI-DSI Interface
6.2.1 General description
The communication can be separated 2 different levels between the MCU and the display module:
- Interface Level : Low level communication
- Packet level : High level communication
6.2.2 Interface level communication
General
The display module uses data and clock lane differential pairs for DSI . Both clock lane and data lane0 can be driven Low Power (LP) or
High Speed (HS) mode. Data lane1 can be driven High Speed mode only.
r
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- Lane support mode MPU(Host) FT8006S-AA (Slave)
Unidirectional lane
Clock
• High-Speed Clock only
Lane
• Simplified Escape Mode (ULPS Only)
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Bi-directional lane
Data • Forward high-speed only
Lane0 • Bi-directional Escape Mode
O en
• Bi-direction LPDT
Unidirectional lane
Data
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• Forward high-speed only
y
Lane1
• Simplified Escape Mode (ULPS Only)
U nf
Table: Lane types and support mode

Low Power mode means that each line of the differential pair is used in single end mode and a differential receiver is disable (A termination
o
resistor of the receiver is disable) and it can be driven into a low power mode.
尔 hC
High Speed mode means that differential pairs (The termination resistor of the receiver is enable) are not used in the single end mode.
There are used different modes and protocols in each mode when there are wanted to transfer information from the MCU to the display
module and vice versa.
韦 ec
The State Codes of the High Speed (HS) and Low Power (LP) lane pair are defined below.
Lane Pair Line DC Voltage Levels High Speed (HS) Low-Power (LP)
博 lT
State Code Dn+ Line Dn- Line Burst Mode Control Mode Escape Mode
HS-0 Low (HS) High (HS) Differential-0 Note 1 Note 1

麦 ca
HS-1 High (HS) Low (HS) Differential-1 Note 1 Note 1

LP-00 Low (LP) Low (LP) Not Defined Bridge Space
Fo
LP-01 Low (LP) High (LP) Not Defined HS-Request Mark-0

LP-10 High (LP) Low (LP) Not Defined LP-Request Mark-1
LP-11 High (LP) High (LP) Not Defined Stop Note 2
Table: High Speed and Low-Power Lane Pair State Descriptions

Preliminary
FT8006S-AN
DSI-CLK lanes
DSI-CLK+/- lanes can be driven into three different power modes: Low Power Mode (LPM LP-11), Ultra Low Power Mode (ULPM) or High
Speed Clock Mode (HSCM).
Clock lanes are in a single end mode (LP = Low Power) when there is entering or leaving Low Power Mode(LPM) or Ultra Low Power Mode
(ULPM).
Clock lanes are in the single end mode (LP = Low Power) when there is entering in or leaving out High Speed Clock Mode (HSCM).
These entering and leaving protocols are using clock lanes in the single end mode to generate an entering or leaving sequences.
The principal flow chart of the different clock lanes power modes is illustrated below.
r
SW Reset
Fo
HW Reset
Power ON Sequence
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LPM
LP-01 LP-10
LP-11
O en LP-00 LP-10 LP-00

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y
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HS-0 HS-0 ULPM

LP-00
o
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HS-1 HS-0
HSCM (HS
Clocking)
韦 ec
Figure: Clock Lanes Power Modes

Notes:
博 lT
1. Low-Power Receivers (LP-Rx) of the lane pair are checking the LP-00 state code, when the Lane Pair is in the High Speed (HS) mode.
2. If Low-Power Receivers (LP-Rx) of the lane pair recognizes LP-11 state code, the lane pair returns to LP-11 of the Control Mode.
麦 ca
Fo

Preliminary
FT8006S-AN
Low Power Mode (LPM)
DSI-CLK+/- lanes can be driven to the Low Power Mode (LPM), when DSI-CLK lanes are entering LP-11 State Code, in three different ways:
1) After SW Reset, HW Reset or Power On Sequence =>LP-11
2) After DSI-CLK+/- lanes are leaving Ultra Low Power Mode (ULPM, LP-00 State Code) =>LP-10 =>LP-11 (LPM). This sequence is
illustrated below.
ULPM LPM
LP-00 LP-11
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Fo
LP-00 LP-10 LP-11
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Time
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Figure: From ULPM to LPM
3) After DSI-CLK+/- lanes are leaving High Speed Clock Mode (HSCM, HS-0 or HS-1 State Code) =>HS-0 =>LP-11 (LPM). This sequence
O en
is illustrated below.
LPM
LP-11
se id
HSCM Termination Resistor
y
is disable
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DSI-CLK+
o
DSI-CLK-
HS-0 or HS-1 HS-0 LP-11

尔 hC
Time
Figure: From HSCM to LPM

All three mode changes are illustrated a flow chart below.
韦 ec
SW Reset
HW Reset
Power ON Sequence
博 lT
麦 ca
LPM
LP-01 LP-10
LP-11
Fo
LP-00 LP-10 LP-00
HS-0 HS-0 ULPM

LP-00
Mode Change
HS-1 HS-0
HSCM (HS
Clocking)
Figure: All three mode changes to LPM

Ultra Low Power Mode (ULPM)
DSI-CLK+/- lanes can be driven to the High Speed Clock Mode (HSCM), when DSI-CLK lanes are starting to work between HS-0 and HS-1
State Codes.
The only entering possibility is from the Low Power Mode (LPM, LP-11 State Code) =>LP-01 =>LP-00 =>HS-0 =>HS-0/1 (HSCM).
This sequence is illustrated below.

Preliminary
FT8006S-AN
ULPM
LPM LP-00
LP-11
r
LP-11 LP-10 LP-00
Fo
Time
Figure: From LPM to UPLM
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The mode change is also illustrated below:
O en
SW Reset
HW Reset
Power ON Sequence
se id
y
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LPM
LP-01 LP-10
LP-11
o
尔 hC
LP-00 LP-10 LP-00

韦 ec
HS-0 HS-0 ULPM

LP-00
博 lT
麦 ca
Mode Change
HS-1 HS-0
Fo
HSCM (HS
Clocking)
Figure: The mode change from LPM to UPLM

Preliminary
FT8006S-AN
High-speed Clock Mode (HSCM)
DSI-CLK+/- lanes can be driven to the High Speed Clock Mode (HSCM), when DSI-CLK lanes are starting to work between HS-0 and HS-1
State Codes.
The only entering possibility is from the Low Power Mode (LPM, LP-11 State Code) =>LP-01 =>LP-00 =>HS-0 =>HS-0/1 (HSCM).
This sequence is illustrated below.
LPM Termination
LP-11 Resistor is
enable HSCM
HS-0
DSI-CLK+ HS-1
DSI-CLK-
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LP-11 LP-01 LP-00 HS-0 HS-0 / 1
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Time
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Figure: From LPM to HSCM
The mode change is also illustrated below:

se id
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SW Reset
U nf
HW Reset
Power ON Sequence
o
尔 hC
LPM
LP-01 LP-10
LP-11
韦 ec
LP-00 LP-10 LP-00

博 lT
麦 ca
HS-0 HS-0 ULPM

LP-00
Fo
Mode Change
HS-1 HS-0
HSCM (HS
Clocking)
Figure: Mode change from LPM to HSCM

Preliminary
FT8006S-AN
The high speed clock (DSI-CLK+/-) is started before high speed data is sent via DSI-Dn+/- lanes. The high speed clock continues clocking
after the high speed data sending has been stopped
The burst of the high speed clock consists of:

- Even number of transitions
- Start state is HS-0
- End state is HS-0
Termination
Termination
r
Resistor
LPM Resistor LPM
Is disable
Is enable HSCM LP-11
Fo
LP-11
DSI-CLK+
DSI-CLK-
LP-11 LP-01 LP-00 HS-0 HS-0 LP-11
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Data Lanes in High Speed Mode
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DSI-D0+
DSI-D0-
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LP-11
LP-11
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Preparation from Low Power Mode to High Speed Mode (TSOT = Start of the Transmission) HSDT
DSI-CLK+
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DSI-CLK-
DSI-D0+
o
DSI-D0-
尔 hC
0 0 0 1 1 1 0 1
LP-11 LP-01 LP-00 HS-0 Rx Synchronized
Tx Synchronization
韦 ec
Low Power Mode, Disable Rx

Line Termination High Speed Mode, Enable Rx Line Termination
博 lT
High Speed Data TEOT LP-11

Transmission
DSI-CLK+
麦 ca
DSI-CLK-
Note
Fo
DSI-D0+
DSI-D0-
The last load bit HS-0 or HS-1

Low power Mode,
Disable Rx Line
High Speed Mode, Enable Rx Line Termination Termination
Note :
If the last load bit is HS-0, the transmitter changes from HS-0 to HS-1.
Figure: High speed clock burst

Preliminary
FT8006S-AN
6.2.3 DSI data lanes
General
DSI-Dn+/- Data Lanes can be driven in different modes which are:
- Escape Mode (only support DSI_D0 data lane pair)
- High-Speed Data Transmission (support all data lane pairs)
- Bus Turnaround Request (only support DSI_D0 data lane pair)
These modes and their entering codes are defined on the following table.
r
Mode Entering Mode Sequence Leaving Mode Sequence
Fo
Escape Mode LP-11 =>LP-10 =>LP-00 =>LP-01 =>LP-00 LP-00 =>LP-10 =>LP-11 (Mark-1)
High-Speed Data Transmission LP-11 =>LP-01 =>LP-00 =>HS-0 (HS-0 or HS-1) =>LP-11
Bus Turnaround Request LP-11 =>LP-10 =>LP-00 =>LP-10 =>LP-00 High-Z, Note
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Table: Entering and leaving sequences
O en
Escape modes
Escape mode is a special mode of operation for Data Lanes using Low-Power states. With this mode some additional functionality becomes
available. Escape mode operation shall be supported in the Forward direction and Reverse direction.
se id
y
The basic sequence of the Escape Mode is as follow
• Start: LP-11
U nf
• Escape Mode Entry : LP-11 =>LP-10 =>LP-00 =>LP-01 =>LP-00

• Escape Command , which is coded, when one of the data lanes is changing from low-to-high-to-low then this changed data lane is
o
presenting a value of the current data bit.

尔 hC
• A payload stream if it is needed

• Exit Escape (Mark-1) LP-00 =>LP-10 =>LP-11
• End: LP-11
韦 ec
For Data Lane0, once Escape mode is entered, the transmitter shall send an 8-bit entry command to indicate the requested action.
All currently available Escape mode commands and actions are list below.
博 lT
• Send or receive “Low-Power Data Transmission” (LPDT)

• Drive data lanes to “Ultra-Low Power State” (ULPS)
麦 ca
• Indicate “Remote Application Reset” (RAR), which is resetting the display module (same as S/W Reset function)
• Indicate “Tearing Effect” (TEE), which is used for a TE line event from the display module to the MCU,
• Indicate “Acknowledge” (ACK), which is used for a non-error event from the display module to the MCU.
Fo

Preliminary
FT8006S-AN
The Stop state shall be used to exit Escape mode and cannot occur during Escape mode operation because of the Spaced-One-Hot
encoding. Stop state immediately returns the Lane to Control mode. If the entry command doesn‟t match a supported command, that
particular Escape mode action shall be ignored and the receive side waits until the transmit side returns to the Stop state.
For Data Lane1 and 2, only support ULPS Escape mode commands.
• Drive data lanes to “Ultra-Low Power State” (ULPS)
The basic construction is illustrated below:
EME (Escape Mode Entry) Escape Load If
Mark-1
Command needed
DSI-D0+
r
DSI-D0-
Fo
LP-11 LP-10 LP-00 LP-01 LP-00 LP-00 LP-10 LP-11
l
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Figure: General Escape mode sequence
The number of the different Escape Commands is eight. These eight different Escape Commands can be divided 2 different groups: Mode or
O en
Trigger. Escape command groups are defined below.
Command Type Entry Command Pattern

Escape Command
se id
Mode/Trigger (First Bit => Last Bit Transmitted)
y
Low-Power Data Transmission Mode 1110 0001bin
U nf
Ultra-Low Power Mode Mode 0001 1110bin

o
Remote Application Reset Trigger 0110 0010 bin

尔 hC
Tearing Effect Trigger 0101 1101 bin
Table: Escape Acknowledge Trigger 0010 0001 bin commands

The MCU is informing to the
display module that it is controlling data lanes (DSI-D0+/-) with the mode e.g. The MCU can inform to the display module that it can put data
韦 ec
lanes in the low power mode.

The MCU is waiting from the display module event information, which has been set by the MCU, with the trigger e.g. when the display
博 lT
module reaches a new V-synch, the display module sent to the MCU a TE trigger (TEE), if the MCU has been requested it.
麦 ca
Low-Power Data Transmission (LPDT)

The MCU can send data to the display module in Low-Power Data Transmission (LPDT) mode when data lanes are entering in Escape
Mode and Low-Power Data Transmission (LPDT) command has been sent to the display module. The display module is also using the same
Fo
sequence when it is sending data to the MCU.

The Low Power Data Transmission (LPDT) is using a following sequence:
• Start: LP-11
• Low-Power Data Transmission (LPDT) command in Escape Mode: 1110 0001 (First to Last bit)
• Payload (Data):
- One or more bytes
- Data lanes are in pause mode when data lanes are stopped (Both lanes are low) between bytes
- One Packet only (Short Packet or Long Packet) in one Low Power Data Transmission.
• Mark-1: LP-00 =>LP-10 =>LP-11
• End: LP-11
This sequence is illustrated for reference purposes below:

Preliminary
FT8006S-AN
EME (Escape Mode Entry) Mark-1
DSI-D0+
DSI-D0-
EME (Escape
Mode Entry) Low-power Data Transmission (LPDT) Load (Data) Mark-1
DSI-D0+
DSI-D0-
LP-11 1 1 1 0 0 0 0 1 LP-11
r
Time Note
Fo
Note: Load (Data) is presenting that the first bit is logical“1”in this example
Figure: Low-power data transmission
l
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Load (Data)
O en
Load Load
Pause
Byte n Byte n+1
se id
y
DSI-D0+
U nf
DSI-D0-
1 1 1
o
Time
尔 hC
Figure: Pause (example)

韦 ec
博 lT
麦 ca
Fo
Figure: Two Data Byte Low-Power Data Transmission Example
LP-11 LP-11 LP-11 LP-11

Packet #1 Packet #2 Packet #3
Send packets sequentially but separate with LP-11
Figure: Sequential Packets Transmission Example

Preliminary
FT8006S-AN
Ultra-Low Power State (ULPS)
The MCU can force data lanes in Ultra-Low Power State (ULPS) mode when data lanes are entering in Escape Mode.
The Ultra-Low Power State (ULPS) is using a following sequence:
• Start: LP-11
• Ultra-Low Power State (ULPS) command in Escape Mode: 0001 1110 (First to Last bit)
• Ultra-Low Power State (ULPS) when the MCU is keeping data lanes low
• Mark-1: LP-00 =>LP-10 =>LP-11
• End: LP-11
r
Fo
EME (Escape Mode Entry) Mark-1
DSI-D0+
DSI-D0-
l
LP-00 LP-10 LP-11
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LP-11 LP-10 LP-00 LP-01 LP-00
EME (Escape
Ultra-Low
Mode Entry) Ultra-Low Power State (ULPS) Mark-1
Power State
DSI-D0+
O en
DSI-D0-
LP-11 0 0 0 1 1 1 1 0 LP-11
se id
Time
y
U nf
Figure: Ultra-low power state (ULPS)

Remote Application Reset (RAR)
o
The MCU can inform to the display module that it should be reseted in Remote Application Reset (RAR) trigger when data lanes are entering
in Escape Mode. The Remote Application Reset is using a following sequence:
尔 hC
• Start: LP-11
• Remote Application Reset (RAR) command in Escape Mode: 0110 0010 (First to Last bit)
韦 ec
• Mark-1: LP-00 =>LP-10 =>LP-11

• End: LP-11
博 lT
EME (Escape Mode Entry)

DSI-D0+ Mark-1
DSI-D0-
麦 ca

Fo
EME (Escape
Mode Entry) Remote Application Reset (RAR) Mark-1
DSI-D0+
DSI-D0-
LP-11 0 1 1 0 0 0 1 0 LP-11
Time
Figure: Remote Application Reset (RAR)

Preliminary
FT8006S-AN
Tearing Effect (TEE)
The display module can inform to the MCU when a tearing effect event (New V-synch) has been happen on the display module by Tearing
Effect (TEE).
The Tearing Effect (TEE) is using a following sequence:
• Start: LP-11
• Escape Mode Entry: LP-11 =>LP-10 =>LP-00 =>LP-01 =>LP-00
• Tearing Effect (TEE) trigger in Escape Mode: 0101 1101 (First to Last bit)
• Mark-1: LP-00 =>LP-10 =>LP-11
• End: LP-11
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Fo
DSI-D0+ Mark-1
DSI-D0-
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EME (Escape
Mode Entry) Tearing Effect Trigger (TEE)
O en
Mark-1
DSI-D0+
DSI-D0-
se id
y
LP-11 0 1 0 1 1 1 0 1 LP-11
Time
U nf
o
Figure: Tearing effect (TEE)

尔 hC
Acknowledgement (ACK)
The display module can inform to the MCU when an error has not recognized on it by Acknowledge (ACK).
The Acknowledge (ACK) is using a following sequence:
韦 ec
• Start: LP-11
• Escape Mode Entry: LP-11 =>LP-10 =>LP-00 =>LP-01 =>LP-00
博 lT
• Acknowledge (ACK) command in Escape Mode: 0010 0001 (First to Last bit)
• Mark-1: LP-00 =>LP-10 =>LP-11
麦 ca
• End: LP-11
DSI-D0+ Mark-1
Fo
DSI-D0-
EME (Escape
Mode Entry) Acknowledge (ACK)
Mark-1
DSI-D0+
DSI-D0-
LP-11 0 0 1 0 0 0 0 1 LP-11
Time
Figure: Acknowledgement (ACK)

Preliminary
FT8006S-AN
High-Speed Data Transmission (HSDT)
Entering High-Speed Data Transmission (Tsot of HSDT)
The display module is entering High-Speed Data Transmission (HSDT) when Clock lanes DSI-CLK+/- have already been entered in the
High-Speed Clock Mode (HSCM) by the MCU. See more information on chapter “High-Speed Clock Mode (HSCM)”.
Data lanes DSI-D0+/- of the display module are entering (TSOT) in the High-Speed Data Transmission(HSDT) as follows
• Start: LP-11
• HS-Request: LP-01
• HS-Settle: LP-00 => HS-0 (Rx: Lane Termination Enable)
• Rx Synchronization: 011101 (Tx (= MCU) Synchronization: 0001 1101)
r
Fo
• End: High-Speed Data Transmission (HSDT) – Ready to receive High-Speed Data Load
This same entering High-Speed Data Transmission (TSOT of HSDT) sequence is illustrated below.
Preparation from Low Power Mode to High Speed Mode (TSOT = Start of the Transmission) HSDT
l
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DSI-CLK+
DSI-CLK-
DSI-D0+
O en
DSI-D0-
0 0 0 1 1 1 0 1
se id
LP-11 LP-01 LP-00 HS-0 Rx Synchronized
y
Tx Synchronization
U nf
Low Power Mode, Disable Rx

Line Termination High Speed Mode, Enable Rx Line Termination
o
尔 hC
Figure: Tsot of HSDT

韦 ec
博 lT
麦 ca
Fo

Preliminary
FT8006S-AN
Leaving High-Speed Data Transmission (TEOT of HSDT)
The display module is leaving the High-Speed Data Transmission (TEOT of HSDT) when Clock lanes DSI- CLK+/- are in the High-Speed
Clock Mode (HSCM) by the MCU and this HSCM is kept until data lanes
DSI-D0+/- are in LP-11 mode. See more information on chapter “7.2.2 High-Speed Clock Mode (HSCM)”.
Data lanes DSI-D0+/- of the display module are leaving from the High-Speed Data Transmission (TEOT of HSDT) as follows
• Start: High-Speed Data Transmission (HSDT)
• Stops High-Speed Data Transmission
- MCU changes to HS-1, if the last load bit is HS-0
- MCU changes to HS-0, if the last load bit is HS-1
r
Fo
• End: LP-11 (Rx: Lane Termination Disable)
This same leaving High-Speed Data Transmission (TEOT of HSDT) sequence is illustrated below
High Speed Data TEOT LP-11
Transmission
DSI-CLK+
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DSI-CLK-
Note
O en
DSI-D0+
DSI-D0-
se id
y
The last load bit HS-0 or HS-1
Low power Mode,
U nf
Disable Rx Line
High Speed Mode, Enable Rx Line Termination Termination
Note :
o
尔 hC
Figure: TEOT of HSDT

Burst of the High-Speed Data Transmission (HSDT)
The burst of the high-speed data transmission (HSDT) can consist of one data packet or several data packets.
韦 ec
These data packets can be Long (Lpa) or Short (Spa) packets. These packets are defined on chapter “Short Packet (Spa) and Long Packet
(Lpa) Structures“.
These different burst of the High-Speed Data Transmission (HSDT) cases are illustrated for reference purposes below.
博 lT
麦 ca
DSI-D0+/- LP-11
SOT LPa EOT LP-11
Fo
DSI-D0+/- LP-11
SOT SPa EOT LP-11
Figure: Single packet in HSDT
LP-11
DSI-D0+/- SOT LPa SPa EOT LP-11
DSI-D0+/- LP-11
SOT SPa SPa SPa EOT LP-11
Figure: Multiple packets in HSDT

Preliminary
FT8006S-AN
Figure: Packets with EoT package in HSDT
Moreover, FT8006S-AN has some multi-packets transmission limits in HSDT shown as following figure:
• The maximum word count of a CMD Long packet is 4. (1 Address + 3 Parameter)
• Pause 4us between any two HS CMD packets. It can be reached by one of the following methods.
r
- Insert Stop state LP-11
Fo
- Insert Null(0x09) or Blanking(0x19) packet
LP-11 LP-11 LP-11
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Packet #1 Packet #2 Null Packet Packet #3
HSDT
>=4us >=4us
O en
Figure: Multi-packets in HSDT
se id
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Abbreviation Explanation
LP-11
U nf
Low Power Mode, Data lanes are „1‟s (Stop Mode)
SOT Start of the Transmission
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Lpa Long Packet

Spa Short Packet
尔 hC
EOT End of the Transmission

Table: Abbreviations
Bus Turnaround (BTA)
韦 ec
The MCU or display module, which is controlling DSI-D0+/- Data Lanes, can start a bus turnaround procedure when it wants information
from a receiver, which can be the MCU or display module.
The MCU and display module are using the same sequence when this bus turnaround procedure is used.
博 lT
This sequence is described for reference purposes, when the MCU wants to do the bus turnaround procedure to the display module, as
follows.
麦 ca
• Start (MCU): LP-11

• Turnaround Request (MCU): LP-11 =>LP-10 =>LP-00
Fo
• The MCU waits until the display module is starting to control DSI-D0+/- data lanes and the MCU stops to control DSI-D0+/- data lanes
(= High-Z)
• The display module changes to the stop mode: LP-00 =>LP-10 =>LP-11

Preliminary
FT8006S-AN
The same bus turnaround procedure (From the MCU to the display module) is illustrated below.
Bus Turnaround (BTA)
The MCU wait until the Display Module Controls

MCU Controls Data lanes
display module start to control Data Lanes
data lanes (its output drivers)
when thr MCU can put output
Turnaround Request (TAR) drives in the high-Z mode LP-Request
DSI-D0+
DSI-D0-
r
Fo
LP-11 LP-10 LP-00 LP-10 LP-00 LP-10 LP-11
Time
l
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Figure: Bus turnaround procedure
O en
Two Data-lane High Speed Transmission
Since a HS transmission is composed of an arbitrary number of bytes that may not be an integer multiple of the number of lanes, one lane
se id
y
may run out of data before the other. Therefore, the lane management layer, as it buffers up the final set of less-than-2 bytes, de-asserts its
“valid data” signal into all lanes for which there‟s no further data.
U nf
Although all lanes start simultaneously with parallel SoTs, each lane operates independently and may complete the HS transmission before
the other lane, sending an EoT one cycle (byte) earlier.
o
The two PHYs on the receiving end of the link collect bytes in parallel and feed them into the lane management layer. The lane management
尔 hC
layer reconstructs the original sequence of bytes in the transmission.

Figure 6.2.3.5.1 shows the way a HS transmission can terminate for two data-lane HS transmission.
韦 ec
博 lT
麦 ca
Fo
Figure: Two data-lane HS transmission example

Preliminary
FT8006S-AN
Three data-lane high speed transmission (skipped in FT8006S-AN )
Since a HS transmission is composed of an arbitrary number of bytes that may not be an integer multiple of the number of Lanes, some
Lanes may run out of data before others. Therefore, the Lane Management layer, as it buffers up the final set of less-than-N bytes,
de-asserts its “valid data” signal into all Lanes for which there is no further data.
Although all Lanes start simultaneously with parallel SoTs, each Lane operates independently and may complete the HS transmission before
the other Lanes, sending an EoT one cycle (byte) earlier.
The N PHYs on the receiving end of the Link collect bytes in parallel and feed them into the Lane Management layer. The Lane Management
layer reconstructs the original sequence of bytes in the transmission.
Below Figure illustrate a variety of ways a HS transmission can terminate for different number of Lanes and packet lengths.
r
l Fo
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O en
se id
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U nf
o
尔 hC
韦 ec
博 lT
麦 ca
Fo

Preliminary
FT8006S-AN
6.2.4 Packet level communication
Short Packet (Spa) and Long Packet (Lpa) structures
Short Packet (Spa) and Long Packet (Lpa) are always used when data transmission is done in Low Power Data Transmission (LPDT) or
High-Speed Data Transmission (HSDT) modes.
The lengths of the packets are
- Short Packet (Spa): 4 bytes
- Long Packet (Lpa): From 6 to 65,541 bytes
The type (Spa or Lpa) of the packet can be recognized from their package headers (PH).
r
l Fo
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O en
se id
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U nf
Figure: Short packet structure

o
尔 hC
韦 ec
博 lT
麦 ca
Fo
Figure:. Long packet structure

Note: Short Packet (Spa) Structure” and Long Packet (Lpa) Structure” are presenting a single packet sending (= Includes LP-11, SoT and
EoT for each packet sending).
The other possibility is that there is not needed SoT, EoT and LP-11 between packets if packets have sent in multiple packet format. E.g.:
• LP-11 =>SoT =>Spa =>Lpa =>Spa =>Spa =>EoT =>LP-11
• LP-11 =>SoT =>Spa =>Spa =>Spa =>EoT =>LP-11
• LP-11 =>SoT =>Lpa =>Lpa =>Lpa =>EoT =>LP-11

Preliminary
FT8006S-AN
Bit Order of the Byte on Packets
All packet data traverses the interface as bytes. Sequentially, a transmitter shall send data LSB first, MSB last. For packets with multi-byte
fields, the least significant byte shall be transmitted first unless otherwise specified.
The below figure shows a complete Long packet data transmission. Note, the figure shows the byte values in standard positional notation,
i.e. MSB on the left and LSB on the right, while the bits are shown in chronological order with the LSB on the left, the MSB on the right and
time increasing left to right.
DI WC (Least Significant Byte) WC (Most Significant Byte) ECC Data CRC (LS Byte) CRC (MS Byte)
39hex 01hex 00hex 15hex 01hex 0Ehex 1Ehex
1 0 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0
L M L M L M L M L M L M L M
S S S S S S S S S S S S S S
B B B B B B B B B B B B B B
r
Fo
Time
Figure: Bit order of the byte on packets
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Byte Order of the Multiple Byte Information on Packets
Byte order of the multiple bytes information, what is used on packets, is that the Least Significant (LS) Byte of the information is sent in the
O en
first and the Most Significant (MS) Byte of the information is sent in the last.
e.g. Word Count (WC) consists of 2 bytes (16 bits) when the LS byte is sent in the first and the MS byte is sent in the last.
This same order is illustrated for reference purposes below.
se id
y
WC (Least Significant Byte) WC (Most Significant Byte)
01hex 00hex
U nf
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
B B B B B B B B B B B B B B B B
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
o
L M L M
S S S S
尔 hC
B B B B
Time
Figure: Byte order of the multiple byte information on packets

韦 ec
Packet Head (PH)

博 lT
The packet header is always consisting of 4 bytes. The content of these 4 bytes are different if it is used to Short Packet (Spa) or Long
Packet (Lpa).
麦 ca
Short Packet (Spa):

st
• 1 byte: Data Identification (DI) => Identification that this is Short Packet (Spa)
nd rd
• 2 and 3 bytes: Packet Data (PD), Data 0 and 1
Fo
th
• 4 byte: Error Correction Code (ECC)
Packet Header (PH)
DI Data 0 Data 1 ECC

15hex 3Ahex 07hex 18hex
1 0 1 0 1 0 0 0 0 1 0 1 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0
B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
L M L M L M L M
S S S S S S S S
B B B B B B B B
Time
Figure: Packet head on short packet
Long Packet (Lpa):

st
• 1 byte: Data Identification (DI) => Identification that this is Long Packet (Lpa)

Preliminary
FT8006S-AN
nd rd
• 2 and 3 bytes: Word Count (WC)
th
• 4 byte: Error Correction Code (ECC)
Packet Header (PH)
DI WC (Least Significant Byte) WC (Most Significant Byte) ECC

39hex 01hex 00hex 15hex
1 0 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
r
L M L M L M L M
Fo
S S S S S S S S
B B B B B B B B
Time
l
Figure: Packet head on long packet
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O en
Data Identification
Data Identification (DI) is a part of Packet Header (PH) and it consists of 2 parts:
• Virtual Channel (VC), 2 bits, DI[7...6]
se id
y
• Data Type (DT), 6 bits, DI[5…0]
The Data Identification (DI) structure is illustrated on a table below.
U nf
o
尔 hC
Table: Data identification structure

韦 ec
博 lT
Data Identification (DI) is illustrated on Packet Header (PH) for reference purposes below.
Packet Header (PH)
麦 ca

Fo
1 0 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
L M L M L M L M
S S S S S S S S
B B B B B B B B
Time
Figure: Data identification of the packet head
Virtual Channel (VC)

A processor may service up to four peripherals with tagged commands or blocks of data, using the Virtual Channel ID field of the header for
packets targeted at different peripherals.
Virtual Channel (VC) is a part of Data Identification (DI[7…6]) structure and it is used to address where a packet is wanted to send from the
MCU. Bits of the Virtual Channel (VC) are illustrated for reference purposes below.

Preliminary
FT8006S-AN
FT8006S only support VC code=00, package with other VC code(01/10/11) will be filter out.
Packet Header (PH)

1 0 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
L M L M L M L M
r
S S S S S S S S
Fo
B B B B B B B B
Time
Figure: Virtual channel on the packet head
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Figure: Virtual channel block diagram (receiver case)

尔 hC
Data Type (DT)

Data Type (DT) is a part of Data Identification (DI[5…0]) structure and it is used to define a type of the used data on a packet.
Bits of the Data Type (DT) are illustrated for reference purposes below.
韦 ec

博 lT

1 0 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0
麦 ca
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
L M L M L M L M
S S S S S S S S
B B B B B B B B
Fo
Time
Figure: Data type on the packet head
This Data Type (DT) also defines what the used packet is: Short Packet (Spa) or Long Packet (Lpa). Data Types (DT) are different from the
MCU to the display module (or other devices) and vice versa. These Data Type (DT) are defined on tables below.

Preliminary
FT8006S-AN
From the MCU to the Display module
Data Type (HEX) Data Type (Binary) Description
01h 00 0001 Sync Event, V Sync Start
11h 01 0001 Sync Event, V Sync End
21h 10 0001 Sync Event, H Sync Start
31h 11 0001 Sync Event, H Sync End
08h 00 1000 End of Transmission (EoT) packet
02h 00 0010 Color Mode (CM) Off Command
12h 01 0010 Color Mode (CM) On Command
r
22h 10 0010 Shut Down Peripheral Command
Fo
32h 11 0010 Turn On Peripheral Command
03h 00 0011 Generic Short WRITE, no parameters
13h 01 0011 Generic Short WRITE, 1 parameters
23h 10 0011 Generic Short WRITE, 2 parameters
l
04h 00 0100 Generic READ, no parameters
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14h 01 0100 Generic READ, 1 parameters
24h 10 0100 Generic READ, 2 parameters
O en
05h 00 0101 DCS WRITE, no parameters
15h 01 0101 DCS WRITE, 1 parameters
06h 00 0110 DCS READ, no parameters
se id
37h 11 0111 Set Maximum Return Packet Size
y
09h 00 1001 Null Packet, no data
U nf
19h 01 1001 Blanking Packet, no data

29h 10 1001 Generic Long Write
o
39h 11 1001 DCS Long Write/Write_LUT Command packet

0Eh 00 1110 Packet Pixel Stream, 16-bit RGB, 5-6-5 Format
尔 hC
2Eh 10 1110 Loosely Packet Pixel Stream, 18-bit RGB, 6-6-6 Format
3Eh 11 1110 Packet Pixel Stream, 24-bit RGB, 8-8-8 Format
Table: Data type from the MCU to the display module

韦 ec
From the Display Module to the MCU

Data Type (HEX) Data Type (Binary) Description
02h 00 0010 Acknowledge & Error Report
博 lT
1Ch 01 1100 DCS Long READ Response

麦 ca
DCS Short READ Response, 1 byte

21h 10 0001
returned
DCS Short READ Response, 2 byte
22h 10 0010
returned
Fo
Table: Data type from the display module to the MCU
The receiver is ignored other Data Type (DT) if they are not defined on tables above. Host send “Generic Read” data type, FT8006S will
return DCS Read package to Host.
Packet data on the short packet

Packet Data (PD) of the Short Packet (Spa) is defined after Data Type (DT) of the Data Identification (DI) has indicated that Short Packet
(Spa) is wanted to send.
Packet Data (PD) of the Short Packet (Spa) consists of 2 data bytes: Data 0 and Data 1.
Packet Data (PD) sending order is that Data 0 is sent in the first and the Data 1 is sent in the last.
Bits of Data 1 are set to 00h, if the information length is 1 byte.
Packet Data (PD) of the Short Packet (Spa), when the length of the information is 1 or 2 bytes are illustrated for reference purposes below.

Preliminary
FT8006S-AN
Packet Header (PH)

15hex 35hex 01hex 1Ehex
1 0 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
L M L M L M L M
S S S S S S S S
B B B B B B B B
r
Time
Fo
Figure: Packet data on the short packet, 2 bytes information
l
Packet Data (PD) information:
nl tia
• Data 0: 10hex
• Data 1: 00hex (Null)
O en
Packet Header (PH)

se id
y
05hex 10hex 00hex 2Chex
1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0
U nf
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
o
L M L M L M L M
S S S S S S S S
B B B B B B B B
尔 hC
Time
Figure: Packet data on the short packet, 1 bytes information

韦 ec
Word count on the long packet

Word Count (WC) of the Long Packet (Lpa) is defined after Data Type (DT) of the Data Identification (DI)has indicated that Long Packet (Lpa)
博 lT
is wanted to send.
Word Count (WC) indicates a number of the data bytes of the Packet Data (PD) what is wanted to send after Packet Header (PH) versus
麦 ca
Packet Data (PD) of the Short Packet (Spa) is placed in the Packet Header (PH).
Word Count (WC) of the Long Packet (Lpa) consists of 2 bytes.
Fo
These 2 bytes of the Word Count (WC) sending order is that the Least Significant (LS) Byte is sent in the first and the Most Significant (MS)
Byte is sent in the last.
Word Count (WC) of the Long Packet (Lpa) is illustrated for reference purposes below.
Packet Header (PH)

1 0 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
L M L M L M L M
S S S S S S S S
B B B B B B B B
Time
Figure: Word count on the long packet

Preliminary
FT8006S-AN
Error Correction Code (ECC)
Error Correction Code (ECC) is a part of Packet Header (PH) and its purpose is to identify an error or errors:
• Short Packet (Spa): Data Identification (DI) and Packet Data (PD) bytes (24 bits: D[23…0])
• Long Packet (Lpa): Data Identification (DI) and Word Count (WC) bytes (24 bits: D[23…0])
D[23…0] is illustrated for reference purposes below.
Packet Header (PH)

05hex 10hex 00hex 2Chex
r
1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0
Fo
D D D D D D D D D D D D D D D D D D D D D D D D P P P P P P P P
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
l
L M L M L M L M
nl tia
S S S S S S S S
B B B B B B B B
Time
O en Figure: D[23:0] and P[7:0] on the short packet

se id
y
Packet Header (PH)
U nf

o
1 0 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0
尔 hC
D D D D D D D D D D D D D D D D D D D D D D D D P P P P P P P P
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
L M L M L M L M
韦 ec
S S S S S S S S
B B B B B B B B
Time
博 lT
麦 ca
Figure: D[23:0] and P[7:0] on the long packet

Error Correction Code (ECC) can recognize one error or several errors and makes correction in one bit error case.
Bits (P[7…0]) of the Error Correction Code (ECC) are defined, where the symbol „^‟ is presenting XOR function (Pn is „1‟ if there is odd
Fo
number of „1‟s and Pn is „0‟ if there is even number of „1‟s), as follows.

• P7 = 0
• P6 = 0
• P5 = D10^D11^D12^D13^D14^D15^D16^D17^D18^D19^D21^D22^D23
• P4 = D4^D5^D6^D7^D8^D9^D16^D17^D18^D19^D20^D22^D23
• P3 = D1^D2^D3^D7^D8^D9^D13^D14^D15^D19^D20^D21^D23
• P2 = D0^D2^D3^D5^D6^D9^D11^D12^D15^D18^D20^D21^D22
• P1 = D0^D1^D3^D4^D6^D8^D10^D12^D14^D17^D20^D21^D22^D23
• P0 = D0^D1^D2^D4^D5^D7^D10^D11^D13^D16^D20^D21^D22^D23
P7 and P6 are set to „0‟ because Error Correction Code (ECC) is based on 64 bit value ([D63…0]), but this implementation is based on 24 bit
value (D[23…0]). Therefore, there is only needed 6 bits (P[5…0]) for Error Correction Code (ECC).

Preliminary
FT8006S-AN
r
l Fo
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O en
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Figure: 24-bit ECC generation on TX side (Example)
U nf
o
尔 hC
韦 ec
博 lT
麦 ca
Fo

Preliminary
FT8006S-AN
Packet footer on the long packet
Packet Footer (PF) of the Long Packet (Lpa) is defined after the Packet Data (PD) of the Long Packet (Lpa). The Packet Footer (PF) is a
checksum value what is calculated from the Packet Data of the Long Packet (Lpa).
The checksum is using a 16-bit Cyclic Redundancy Check (CRC) value which is generated with a polynomial X16+X12+X5+X0 as it is
illustrated below.
r
Fo
Figure: 16-bit cyclic redundancy check (CRC) calculation
l
The 16-bit Cyclic Redundancy Check (CRC) generator is initialized to FFFFh before calculations.
nl tia
The Most Significant Bit (MSB) of the data byte of the Packet Data (PD) is the first bit what is inputted into the 16-bit Cyclic Redundancy
Check (CRC).
O en
The receiver is calculated own checksum value from received Packet Data (PD). The receiver compares own checksum and the Packet
Footer (PF) what the transmitter has sent.
The received Packet Data (PD) and Packet Footer (PF) are correct if the own checksum of the receiver and Packet Footer (PF) are equal
se id
y
and vice versa the received Packet Data (PD) and Packet Footer (PF) are not correct if the own checksum of the receiver and Packet Footer
U nf
(PF) are not equal.

o
尔 hC
韦 ec
博 lT
麦 ca
Fo

Preliminary
FT8006S-AN
Packet transmissions
Packet from the MCU to the display module
Display Command Set (DCS), which is defined on chapter “Instructions” is used from the MCU to the display module.
This Display Command Set (DCS) is always defined on the Data 0 of the Packet Data (PD), which is included in Short Packet (Spa) and
Long packet (Lpa) as these are illustrated below.
LP-11 : Low Power – Stop State
SoT : Start of Transmission
Packet Header (PH)
DI : Data Identification (8 bit)
Data 0 and Data 1 : Packet Data (8+8 bit)
ECC : Error Correction Code (8 bit)
Packet Data (PD) EoT : End of Transmission
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Short Packet (SPa)
Fo
LP-11 SoT DI Data 0 Data 1 ECC EoT LP-11
Time
LP-11 : Low Power – Stop State
l
SoT : Start of Transmission
nl tia
DI : Data Identification (8 bit)
WC : Word Count (16 bit)
Packet Header (PH) ECC : Error Correction Code (8 bit)
Data 0, …WC-1 : Packet Data (0-65,535 byte)
CS : Checksum (16bit) = Packet Footer (PF)
O en
Long Packet (LPa) EoT : End of Transmission
LP-11 SoT DI Word Count (WC) ECC Data 0

se id
y
Data 1 Data WC-2 Data WC-1 Checksum (CS) EoT LP-11
U nf
Time
o
Packet Data (PD)

尔 hC
Display Command Set (DCS)
Figure: DCS on the short packet and long packet
Packet from the display module to the MCU

韦 ec
Used packet types

The display module is always using Short Packet (Spa) or Long Packet (Lpa), when it is returning information to the MCU after the MCU has
博 lT
requested information from the Display Module. This information can be a response of the Display Command Set (DCS).
The used packet type is defined on Data Type (DT).
麦 ca
Return Bytes
Fo
LP-11 LPa LP-11
Return Bytes
LP-11
SPa LP-11
Figure: Return bytes on single packet

Acknowledge with Error Report (AwER)
“Acknowledge with Error Report” (AwER) is always using a Short Packet (Spa), what is defined on Data Type (DT, 00 0010b), from the
display module to the MCU.
The Packet Data (PD) can include bits, which are defining the current error, when a corresponding bit is set to 1 , as they are defined on the
following table.

Preliminary
FT8006S-AN
Bit Description
0 SoT Error
1 SoT Sync Error
2 EoT Sync Error
3 Escape Mode Entry Command Error
4 Low-Power Transmit Sync Error
5 Protocol Timer Rime-Out
6 False Control Error
7 Contention is Detected on the Display Module
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8 ECC Error, signal-bit (detected and corrected)
9 ECC Error, multi-bit (detected, not corrected)
10 Checksum (CRC) Error (only for Long Packet(LP))
11 DSI Data Type (DT) Not Recognized
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12 DSI Virtual Channel (VC) ID Invaild
13 Invalid Transmission Length
14 Reserved, set to “0” internally
O en
15 DSI Protocol violation
Figure: Acknowledge with error report for long packet response

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Bit Description
0 SoT Error
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1 SoT Sync Error

2 EoT Sync Error
o
3 Escape Mode Entry Command Error

尔 hC
4 Low-Power Transmit Sync Error

5 Protocol Timer Rime-Out
6 False Control Error
7 Contention is Detected on the Display Module
韦 ec
8 ECC Error, signal-bit (detected and corrected)

9 ECC Error, multi-bit (detected, not corrected)
博 lT
10 set to “0” internally

11 DSI Data Type (DT) Not Recognized
麦 ca
12 DSI Virtual Channel (VC) ID Invaild

13 Invalid Transmission Length
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14 Reserved, set to “0” internally

15 DSI Protocol violation
Figure: Acknowledge with error report for short packet response

Preliminary
FT8006S-AN
These errors are only included on the last packet, which has been received from the MCU to the display module, before Bus Turnaround
(BTA).
The display module ignores the received packet which includes error or errors.
Acknowledge with Error Report (AwER) of the Short Packet (Spa) is defined e.g.
• Data Identification (DI)
- Virtual Channel (VC, DI[7…6]): 00b
- Data Type (DT, DI[5…0]): 00 0010b
• Packet Data (PD)
- Bit 8: ECC Error, single-bit (detected and corrected)
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Fo
- AwER: 0100h
• Error Correction Code (ECC)
This is defined on the Short Packet (Spa) as follows.
Packet Header (PH)
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Packet Data (PD)
O en
DI AwER(Least Significant Byte) AwER(Most Significant Byte) ECC
02hex 00hex 01hex 3Ahex
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0
se id
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0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
L M L M L M L M
U nf
S S S S S S S S
B B B B B B B B
o
Time
尔 hC
Figure: Acknowledge with error report – example

6.2.5 Customer-defined generic read data type format
The short packet of Data Type 24h (Generic READ, 2 parameters) specifies the register content for read and the Nth parameter that will
begin reading. After Data Type 24h is received, BTA is executed. Then, the Nth parameter becomes the first data, and the number of data of
韦 ec
WC (word count) value is output.

博 lT
Packet Structure (processor à peripheral)

P0 P1
Data Type Manufacturer Start Parameter
麦 ca
ECC
24h Command N
Low Power Data Transfer (peripheral à processor)

Fo
Data 0 Data 1 Data (WC-1)

Data Type 1th 2th Nth
WC0 WC1 ECC CRC0 CRC1
1Ah Parameter Parameter Parameter
Figure: Generic read data type format

Preliminary
FT8006S-AN
6.3. I2C-Bus Interface
6.3.1. Characteristics of I2C-bus
2
The I C-bus is for bi-directional, two-line communication between different ICs or modules. The two lines compose of a serial data line (SDA)
and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only
when the bus is not busy.
6.3.2. System configuration

(1) Transmitter: the device which sends the data to the bus
(2) Receiver: the device which receives the data from the bus
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Fo
(3) Master: the device which initiates a transfer, generates clock signals and terminates a transfer
(4) Slave: the device addressed by a master
(5) Multi-Master: more than one master attempts to control the bus at the same time without corrupting the message
(6) Arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so and the
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message is not corrupted.
Figure: System configuration
O en
6.3.3. Bit transfer
One data bit is transferred during each clock pulse. The data on SDA line must remain stabilized during the HIGH period of the clock pulse.
se id
As changes in the data line at this time will be interpreted as a control signal.
y
U nf
SDA
o
尔 hC
SCL
韦 ec
data line change

stable; of data
data valid allowed
博 lT
Figure: Bit transfer

麦 ca
Fo

Preliminary
FT8006S-AN
6.3.4. START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition on the data line, while the clock is HIGH, is
defined as the START condition (S). A LOW-to-HIGH transition on the data line is defined as the STOP condition (P) while the clock is HIGH.
SDA SDA
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SCL SCL
S P
START condition STOP condition
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Figure: Definition of START and STOP conditions.
O en
6.3.5. Acknowledgment
Each bit in a byte (8 bits) is followed by an acknowledgment bit. The acknowledgment bit is a HIGH signal placed on the bus by the
se id
y
transmitter during the master generating an extra acknowledgment related clock pulse.
U nf
An addressed slave receiver must generate an acknowledgment after the reception of each byte. Also a master receiver must generate an
acknowledgment after the reception of each byte that has been clocked out of the slave transmitter.
o
The acknowledged device must pull-down the SDA line during the acknowledgment clock pulse, so that the SDA line remains LOW during
the HIGH period of the acknowledgment related clock pulse (setup and hold times must be considered).
尔 hC
A master receiver must signal an end of data to the transmitter by not generating an acknowledgment on the last byte that has been clocked
out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
DATA OUTPUT
韦 ec
BY TRANSMITTER
博 lT
DATA OUTPUT not acknowledge

麦 ca
BY RECEIVER
acknowledge
Fo
SCL FROM
MASTER 1 2 8 9
START clock pulse for

condition acknowledgement
2
Figure: Acknowledgement on the I C-bus

Preliminary
FT8006S-AN
6.4. Power Level Definition
6.4.1. Power level
There are 4 level modes are defined they are in order of Maximum Power consumption to Minimum Power Consumption:
1. Normal Mode On (full display), Sleep Out.
In this mode, the display is able to show maximum 16,777,216 colors.
2. Sleep Out.
In this mode part of the display is used with maximum 16,777,216 colors.
3. Sleep In Mode
In this mode, the DC: DC converter, Internal oscillator and panel driver circuit are stopped. Only the MCU interface and memory works
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with VDDI power supply. Contents of the memory are safe.
4. Power Off Mode
In this mode, both AVDD, AVEE and VDDI are removed.
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6.4.2. Power flow chart
Normal display mode on = NORON

Partial mode on = PTLON
O en
Sleep out = SLPOUT Power on sequence
Sleep in = SLPIN HW Reset
se id
SW reset
y
U nf
SLPIN
Sleep out Sleep in
o
Normal display mode on SLPOUT Normal display mode on

尔 hC
Sleep out Sleep in

韦 ec
Note 1: There is not any abnormal visual effect when there is changing from one power mode to another power mode.
Note 2: There is not any limitation, which is not specified by this spec, when there is changing from one power mode to another power mode.
博 lT
麦 ca
Fo

Preliminary
FT8006S-AN
6.5. Tear Effect Information
6.5.1. General
The MCU is updating the frame memory of the display module via its interface (DSI).
The display module is refreshing the display panel from the frame memory independently and it does not know what is happening on the
interface of the display module (The MCU is sending image information to the display module). It is possible that this asynchronous updating
is causing an abnormal visual effect on the display panel of the display module.
Therefore, the display module is sending a synchronous information (= Tearing Effect Information), which is telling the position of the
refreshing on the display panel, to the MCU which can decide when it can send image information to the display module (Mainly used for a
moving image e.g. video clips) that there can avoid the abnormal visual effect on the display panel of the display module.
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This Tearing Effect information can be sent in two different ways:
• Separated Line, which is so-called Tearing Effect (TE) line
• Bus, which is so-called Tearing Effect (TEE) Bus Trigger, when the display module is sending a trigger to the MCU
The TE line can be used in DSI case if the Tearing Effect (TEE) bus trigger is not possible to use and the Tearing Effect (TEE) Bus Trigger is
l
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only used in DSI case.
6.5.1.1. Tearing effect line models
O en
The Tearing Effect line supplies to the MCU a Panel ynchronization signal and this signal can be enabled or disabled by the Tearing
Effect Line Off & On commands.
se id
The mode of the Tearing Effect Signal is defined by the Parameter of the Tearing Effect Line On command.
y
U nf
Mode 1：The Tearing Effect Output signal consists of V-Sync information only:
tvdl tvdh
o
Vertical
尔 hC
Time Scale
tvdh = The display panel is not updated from the Frame Memory.
韦 ec
Tvdl = The display panel is updated from the Frame Memory (except Invisible Line – see below).
博 lT
Mode 2：The Tearing Effect Output signal consists of V-Sync and H-Sync information; There is one V-sync and 864 H-sync pulses per field:
thdh
麦 ca
thdl thdl
V-Sync V-Sync
Fo
Invisible
1st Line 1280th Line
Line
tvdh = The display panel is not updated from the Frame Memory.
Tvdl = The display panel is updated from the Frame Memory (except Invisible Line – see below).

Preliminary
FT8006S-AN
TE Line mode1 and Mode2 is shown as below graph:
Bottom Line
Top Line
2nd Line
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TE (Mode 2)
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TE (Mode 1)
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O en
Note: During Sleep In Mode, the Tearing Effect Output Pin is active Low.
6.5.1.2. Tearing effect line timing

se id
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The Tearing Effect signal is described below:
tvdl tvdh
U nf
Vertical Time
o
尔 hC
thdh
Horizontal Time
韦 ec
thdl
博 lT
麦 ca
Idle Mode Off/On

Fo
The TE signal rising and falling timing is described below:
tr tf
80% 80%
20% 20%

Preliminary
FT8006S-AN
6.5.1.3. Example 1 MCU write is faster then panel read
MCU to
Memory
1st 864th Time
TE Output
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Signal
Fo
Time
Memory to
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Display Panel
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Image on 1st 864th Time
Display Panel a b c d
O en MCU write is faster than panel read

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Data write to Frame Memory is now ynchronizat to the Panel Scan. It should be written during the vertical sync pulse of the Tearing Effect
U nf
Output Line. This ensures that data is always written ahead of the panel scan and each Panel Frame refresh has a complete new image:
o
尔 hC
韦 ec
博 lT
麦 ca
Example 1 – Image on the display panel

Fo

Preliminary
FT8006S-AN
6.5.1.4. Example 1 MCU write is slower then panel read
MCU to
Memory
1st 864th Time
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Fo
TE Output
Signal
Time
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Memory to
Display Panel
Image on 1st 864th Time
O en
Display Panel a b c d e f
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y
MCU write is slower than panel read
U nf
The MCU to Frame Memory write begins just after Panel Read has commenced i.e. after one horizontal sync pulse of the Tearing Effect
Output Line. This allows time for the image to download behind the Panel Read pointer and finishing download during the subsequent frame
o
before the Read Pointer “catches” the MCU to frame memory write position.
尔 hC
韦 ec
博 lT
麦 ca
Fo
Example 2 – Image on the display panel

Preliminary
FT8006S-AN
6.5.2. Tearing effect bus trigger

A Tearing Effect Bus Trigger information supplies to the MCU a Panel ynchronization trigger and this Tearing Effect Bus Trigger information
can be enabled or disabled by commands “Tearing Effect Line Off (34h)” and “Tearing Effect Line On (35h)” when the only mode of the
Tearing Effect Signal is Vsync. Information.
The display module is sending this trigger information in Escape Mode after the Bus Turnaround (BTA). The Tearing Effect Bus Trigger can
only use in DSI case without the TE line.
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O en
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A rising edge of the V-Sync and DSI-D0
U nf
o
尔 hC
韦 ec
博 lT
麦 ca
Fo

Preliminary
FT8006S-AN
6.5.2.1. Tearing effect bus trigger enable

The MCU can enable the Tearing Effect Bus Trigger on the display module in 2 different ways when a Short Packet (Spa) or Long Packet
(Lpa) is used. These cases are illustrated below.
r
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Tearing effect bus trigger enable (DCSW1-S) – short packet (Spa)
O en
se id
y
U nf
o
尔 hC
韦 ec
博 lT
麦 ca
Fo
Tearing effect bus trigger enable (DCSW-L) – long packet (Lpa)

Preliminary
FT8006S-AN
6.5.2.2. Tearing effect bus trigger disable

The MCU can enable the Tearing Effect Bus Trigger on the display module in 2 different ways when a Short Packet (Spa) or Long Packet
(Lpa) is used. These both possibilities are illustrated below.
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Tearing effect bus trigger disable (DCSWN-S) – short packet (Spa)
O en
se id
y
U nf
o
尔 hC
韦 ec
博 lT
麦 ca
Tearing effect bus trigger disable (DCSW-L) – long packet (Lpa)

Fo

Preliminary
FT8006S-AN
6.5.2.3. Tearing effect bus trigger sequences

Tearing effect bus trigger enable sequence – DCSW-L and HSDT
MCU Display Module
Interface Information Interface
Line Packet Packet Comment
Mode Direction Mode
Sender Sender
Control Control
1 - LP-11 => - - Start
2 DCSW-L HSDT => - - Tearing Effect Bus Trigger Enable
3 EoTP HSDT => - - End of Transmission Packet
4 - LP-11 => - - .
r
5 - BTA <=> BTA - Interface Control Change from the MCU to the display module
Fo
If No Error => Goto Line 8
6 - - <= LP-11 - If Error is Corrected by ECC => Goto Line 19
If Error => Goto Line 30
7 . . . . . .
8 - - <= ACK - No Error
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9 - - <= LP-11 - .
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10 - BTA <=> BTA - Interface Control Change from the display module to the MCU
11 - LP-11 => - - .
O en
13 - - <= LP-11 - .
14 - - <= TEE - TE(Escape Trigger) on the next V-Synch
15 - - <= LP-11 - .
se id
16 - BTA <=> BTA - Interface Control Change from the the display module to the MCU
y
17 - LP-11 => - - End
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18 . . . . . .
19 - - <= LPDT AwER Error Report(Error is Corrected by ECC)
20 - - <= LP-11 - .
o
尔 hC
22 - LP-11 => - - .
24 - - <= LP-11 - .
26 - - <= LP-11 - .
韦 ec
28 - LP-11 => - - End
29 . . . . . .
博 lT
30 - - <= LPDT AwER Error Report

31 - - <= LP-11 - .
麦 ca
If the MCU is not forcing BTA => Goto Line 34
33 - LP-11 => - -
If the MCU is forcing BTA => Goto Line 36
34 - LP-11 => - - End
Fo
35 . . . . . .
37 - - <= LP-11 - Dead-Lock (no TE information) See Note 2
The MCU is forced to start to control the interface
38 - LP-11 => - -
The display module detects Bus Connection Error (BCE
40 - - <= LP-11 - .
Error Report (Bus Connection Error (BCE) is reported)
41 - - <= LPDT AwER
See Note 2
42 - - <= LP-11 - .
44 - LP-11 => - - End
Notes:
1. Lines 1 – 17 are needed for every frame..
2. Bits 5 and 7 of the AwER are applied.

Preliminary
FT8006S-AN
Tearing effect bus trigger enable sequence – DCSW-L and LPDT

MCU Display Module
Mode Direction Mode
Sender Sender
Control Control
1 - LP-11 => - - Start
2 DCSW-L LPDT => - - Tearing Effect Bus Trigger Enable
3 - LP-11 => - - .
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Fo
6 . . . . . .
8 - - <= LP-11 - .
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10 - LP-11 => - - .
12 - - <= LP-11 - .
O en
14 - - <= LP-11 - .
se id
16 - LP-11 => - - End
y
17 . . . . . .
U nf
19 - - <= LP-11 - .
o
21 - LP-11 => - - .
尔 hC
23 - - <= LP-11 - .
25 - - <= LP-11 - .
韦 ec
27 - LP-11 => - - End

28 . . . . . .
博 lT

30 - - <= LP-11 - .
麦 ca

32 - LP-11 => - -
33 - LP-11 => - - End
Fo
34 . . . . . .
37 - LP-11 => - -
The display module detects Bus Connection Error (BCE)
39 - - <= LP-11 - .
40 - - <= LPDT AwER
See Note 2
41 - - <= LP-11 - .
43 - LP-11 => - - End
Notes:
1. Lines 1 – 16 are needed for every frame.

Preliminary
FT8006S-AN
Tearing effect bus trigger enable sequence – DCSW1-S and HPDT

MCU Display Module
Mode Direction Mode
Sender Sender
Control Control
1 - LP-11 => - - Start
2 DCSW1-S HSDT => - - Tearing Effect Bus Trigger Enable
4 - LP-11 => - - .
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Fo
7 . . . . . .
9 - - <= LP-11 - .
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11 - LP-11 => - - .
13 - - <= LP-11 - .
O en
15 - - <= LP-11 - .
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17 - LP-11 => - - End
18 . . . . . .
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20 - - <= LP-11 - .
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22 - LP-11 => - - .
尔 hC
24 - - <= LP-11 - .
26 - - <= LP-11 - .
韦 ec
28 - LP-11 => - - End
29 . . . . . .
博 lT

31 - - <= LP-11 - .
麦 ca
33 - LP-11 => - -
34 - LP-11 => - - End
Fo
35 . . . . . .
38 - LP-11 => - -
40 - - <= LP-11 - .
41 - - <= LPDT AwER
See Note 2
42 - - <= LP-11 - .
44 - LP-11 => - - End
Notes:

Preliminary
FT8006S-AN
Tearing effect bus trigger enable sequence – DCSW1-S and LPDT

MCU Display Module
Mode Direction Mode
Sender Sender
Control Control
1 - LP-11 => - - Start
2 DCSW1-S LPDT => - - Tearing Effect Bus Trigger Enable
3 - LP-11 => - - .
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6 . . . . . .
8 - - <= LP-11 - .
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10 - LP-11 => - - .
12 - - <= LP-11 - .
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14 - - <= LP-11 - .
se id
16 - LP-11 => - - End
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17 . . . . . .
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19 - - <= LP-11 - .
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21 - LP-11 => - - .
尔 hC
23 - - <= LP-11 - .
25 - - <= LP-11 - .
韦 ec
27 - LP-11 => - - End

28 . . . . . .
博 lT

30 - - <= LP-11 - .
麦 ca

32 - LP-11 => - -
33 - LP-11 => - - End
Fo
34 . . . . . .
37 - LP-11 => - -
39 - - <= LP-11 - .
40 - - <= LPDT AwER
See Note 2
41 - - <= LP-11 - .
43 - LP-11 => - - End
Notes:

Preliminary
FT8006S-AN
Tearing effect bus trigger enable sequence – DCSWN-S and HPDT

MCU Display Module
Mode Direction Mode
Sender Sender
Control Control
1 - LP-11 => - - Start
2 DCSWN-S HSDT => - - Tearing Effect Bus Trigger Disable
4 - LP-11 => - - End
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Tearing effect bus trigger enable sequence – DCSWN-S and LPDT
MCU Display Module
Mode Direction Mode
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Sender Sender
Control Control
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1 - LP-11 => - - Start
2 DCSWN-S LPDT => - - Tearing Effect Bus Trigger Disable
O en
3 - LP-11 => - - End
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尔 hC
韦 ec
博 lT
麦 ca
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Preliminary
FT8006S-AN
6.6 NVM Programming Procedure
6.6.1 NVM program flow chart with internal Power
Here is an example of OTP program ID and VCOM with internal power:
Power On Sequence SPI_LoadFinish Set OTP Wait 1 second

Apply VDDI/AVDD/AVEE CMD=0x42, DAT=0x24 initial/program Bank for OTP Program done
CMD=0x90, DAT=0x10 CMD=0x42, DAT=0x00
CMD=0x80, DAT=DAT1
Hardware Reset CMD=0x85, DAT=DAT2 Sleep In
Sleep Out CMD=0x70, DAT=DAT3 CMD=0x10,DAT=0x02
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CMD=0x11, DAT=0x10
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SPI_Not_LoadFinish
CMD=0x41, DAT=0x5A Wait 150ms
Set OTP Mode
CMD=0x42, DAT=0x24 Wait 150ms CMD=0x48, DAT=0x02
CMD=0x90, DAT=0x5A
OTP Program Start Hardware Reset

OTP Program Unlock
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CMD=0x58 DAT=0xAA
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CMD=0x5A, DAT=0x96
Check ID,VCOM & TCON
OTP StopReload Registers
CMD=0x41, DAT=0x5A
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Write ID,VCOM & TCON
Registers
DAT1 = 8'b1111_0010 ( bank 7 ~ 0 )
se id
set bit to 0: OTP bank initial load
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Check ID,VCOM & TCON
Registers
set bit to 1: OTP bank initial NOT load
U nf
DAT2 = 8'b1111_0010 ( bank 7 ~ 0 )
set bit to 0: OTP bank always reload
Set VGH Clamp set bit to 1: OTP bank NOT reload
CMD=0x42, DAT=0x09
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CMD=0xC7, DAT=0x00 DAT3 = 8'b0000_1101 ( bank 7 ~ 0 )

Set OTP Mode set bit to 0: OTP bank NOT program
尔 hC
CMD=0x48, DAT=0x00 set bit to 1: OTP bank program
Here is an example of OTP program TCON with internal power:

韦 ec
CMD=0x80, DAT=DAT4
博 lT

CMD=0x11, DAT=0x10 CMD=0x83, DAT=DAT7
SPI_Not_LoadFinish CMD=0x70, DAT=DAT8
麦 ca
CMD=0x41, DAT=0x5A CMD=0x71, DAT=DAT9 Wait 150ms

CMD=0x42, DAT=0x24 Wait 150ms CMD=0x72, DAT=DAT10
CMD=0x90, DAT=0x5A CMD=0x73, DAT=DAT11
Hardware Reset
Fo
OTP Program Unlock Set OTP Mode

CMD=0x5A, DAT=0x96 CMD=0x48, DAT=0x02
Check TCON Registers

OTP StopReload OTP Program Start
CMD=0x41, DAT=0x5A CMD=0x58 DAT=0xAA
Write TCON Registers
Check TCON Registers
DAT4 = 8'b1111_1110 ( bank 7 ~ 0 ) DAT8 = 8'b0000_0001 ( bank 7 ~ 0 )

Set VGH Clamp DAT5 = 8'b0000_0000 ( bank 15 ~ 8 ) DAT9 = 8'b1111_1111 ( bank 15 ~ 8 )
CMD=0x42, DAT=0x09
CMD=0xC7, DAT=0x00
Set OTP Mode DAT7 = 8'b0000_1111 ( bank 31 ~ 24 ) DAT11 = 8'b1111_0000 ( bank 31 ~ 24 )
CMD=0x48, DAT=0x00 set bit to 0: OTP bank initial load set bit to 0: OTP bank NOT program
set bit to 1: OTP bank initial NOT load set bit to 1: OTP bank program

Preliminary
FT8006S-AN
Here is an example of OTP program ID , VCOM and TCON with internal power:

CMD=0x80, DAT=DAT4
CMD=0x11, DAT=0x10 CMD=0x83, DAT=DAT7
SPI_Not_LoadFinish CMD=0x85, DAT=DAT8
CMD=0x41, DAT=0x5A CMD=0x70, DAT=DAT9 Wait 150ms
CMD=0x42, DAT=0x24 Wait 150ms CMD=0x71, DAT=DAT10
r
CMD=0x90, DAT=0x5A CMD=0x72, DAT=DAT11
CMD=0x73, DAT=DAT12
Fo
Hardware Reset
OTP Program Unlock
CMD=0x5A, DAT=0x96 Set OTP Mode
CMD=0x48, DAT=0x02 Check ID,VCOM & TCON
OTP StopReload Registers
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CMD=0x41, DAT=0x5A OTP Program Start
nl tia
CMD=0x58 DAT=0xAA
Write ID,VCOM & TCON
Registers DAT4 = 8'b1111_0010 ( bank 7 ~ 0 )
O en
DAT5 = 8'b0000_0000 ( bank 15 ~ 8 )
Check ID,VCOM & TCON DAT6 = 8'b0000_0000 ( bank 23 ~ 16 )
Registers DAT7 = 8'b0000_1111 ( bank 31 ~ 24 )
DAT9 = 8'b0000_1101 ( bank 7 ~ 0 )
set bit to 0: OTP bank initial load
se id
DAT10 = 8'b1111_1111 ( bank 15 ~ 8 )
y
Set VGH Clamp set bit to 1: OTP bank initial NOT load
DAT11 = 8'b1111_1111 ( bank 23 ~ 16 )
CMD=0x42, DAT=0x09
U nf
CMD=0xC7, DAT=0x00
Set OTP Mode set bit to 0: OTP bank always load set bit to 0: OTP bank NOT program
CMD=0x48, DAT=0x00 set bit to 1: OTP bank NOT load set bit to 1: OTP bank program
o
尔 hC
韦 ec
博 lT
麦 ca
Fo

Preliminary
FT8006S-AN
7. TP Function Description
FT8006S-AN is an integrated display touch controller IC with built-in 16-bit enhanced Micro-controller unit (MCU). FT8006S-AN adopts
self-capacitance technology and supports mult- touch.
7.1 TP Architecture
TP architecture is shown as below
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尔 hC
 AFE Controller
韦 ec
AFE controller completes the driving and scanning of the sensors in the touch panel, and sends the data of touch sensors after
scanning to the MCU for data processing.

博 lT
 16bit MCU
麦 ca
MCU and SOC subsystems complete the control, data processing, LCD operation and coordination, HOST communication and
other functions of the whole touch systems. Firmware, stored in external flash memory, can be loaded into the internal SRAM
Fo
by HOST via the I2C/SPI interface.
 I2C/SPI serial interface
Touch communication with HOST supports I2C/SPI interface. The control interface consists of two signals INT and
TP_EXT_RSTN. Whenever there is effective touch sensed on the touch screen, Touch controller will send data transfer request
to the HOST via INT port, and complete the point report to the HOST.HOST can communicate with FT8201AB via I2C/SPI.
HOST can also reset Touch controller through TP_EXT_RSTN port.
 External Flash
External Flash, used to store the Firmware, and LCD initialization code, can be added into the Touch controller.

Preliminary
FT8006S-AN
 Watchdog
Watchdog clock is used to ensure the stability of the chip when in operation
7.2 MCU
This section describes some critical features and operations supported by the MCU.
Figure below shows the overall structure of the MCU block. In addition to the MCU core, we have added the following circuits.
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Program Data
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Memory Memory
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Enhanced
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Clock
Manager MCU Core
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Master Clock Timer

尔 hC
韦 ec
 Program Memory: 64KB SRAM
 Data Memory: 40KB SRAM

博 lT
 Real Time Clock (RTC): 32KHz from a RC Oscillator
 Timer: A number of timers are available to generate different clocks

麦 ca
 Master Clock: 50MHz from a RC Oscillator
 Clock Manager: To control various clocks under different operation conditions of the system
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7.3 Operation Mode

Touch controller has the following three operation modes:

Preliminary
FT8006S-AN
 Active mode
In this mode, touch controller scans the screen, and detects the touch actions. The mode is normal operating mode, touch
controller will be in this mode after reset or power on automatically.
 Monitor mode
In this mode, touch controller enters low-power mode, and detects and scans touch-screen body. When into touch detection
mode, majority of the algorithm will be terminated, and only a simple detection algorithm is retained to detect if there is a touch
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action happened. Whenever a touch is detected, touch controller will immediately enter the normal operating mode.
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In this mode, host can write 0x00 to register 0xA5 to force touch controller enter active mode
How to enter monitor mode, writes 0x01 to register 0xA5, please refers to register 0xA5 for detail descriptions.
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 Sleep Mode
O en
In this mode, touch controller enters ultra low-power standby mode, HOST can only wake-up touch controller via "RESET" to
enter the normal operating mode.

se id
How to enter sleep mode, writes 0x03 to register 0xA5, please refers to register 0xA5 for detail descriptions.
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7.4 Microprocessor Interface

o
It supports external flash for TP loading firmware.

尔 hC
7.5 Touch Controller Boots Firmware With External Flash

It supports two ways for TP loading firmware. The one is TP booting with external flash.
韦 ec
LCD
博 lT
麦 ca
Flash IC
Fo
Firmware TP
7.6 I2C Interface to Host

I2C interface supported by FT8006S-AN that is two-wire serial bus consisting of data line (TP_SPI_MOSI) and clock line

Preliminary
FT8006S-AN
(TP_SPI_ SCL), used for serial data transferring between host and slave device.
The TP_INT port controlled by FT8006S-AN will send out an interrupt request signal to the host when there is a valid touch.
Host can send the reset signal via TP_EXT_RSTN port to reset the FT8006S-AN if needed.
7.7 I2C Read/Write Interface Description

It is important to note that the TP_SPI_MOSI and TP_SPI_ SCL must connect with a pull-high resistor respectively before you
read/write I2C data.
7.7.1 Host Write Data to Slave
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Slave_Addr Data_Addr[X] Data[X] Data[X+N-1]
S A[6:0] W A R[7:0] A D[7:0] A …... D[7:0] A P
Start R/W ACK ACK ACK ACK Stop
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7.7.2 Host Read Data from Slave
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Step1: Write Data Address
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Slave_Addr Data_Addr[X]
S A[6:0] W A R[7:0] A P
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Start R/W ACK ACK Stop

尔 hC
Step2: Read Data

韦 ec
Slave_Addr Data[N] Data[X+N-1]

S A[6:0] R A D[7:0] A …... D[7:0] A P
博 lT
Start R/W ACK ACK ACK Stop

麦 ca
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7.8 SPI nterface to Host

SPI interface supported by FT8006S-AN that is four-wire serial bus consisting of chip-select line (TP_SPI_CS), clock line
(TP_SPI_ SCL), data input line(TP_SPI_MOSI) and data output line(TP_SPI_MISO), used for serial data transferring between host and

Preliminary
FT8006S-AN
slave device.
The TP_INT port controlled by FT8006S-AN will send out an interrupt request signal to the host when there is a valid touch.
Host can send the reset signal via TP_EXT_RSTN port to reset the FT8006S-AN if needed.
7.9 SPI Read/Write Interface Description
7.9.1 SPI Transmission Packet

A transmission packet of SPI protocol consists of following fields:
CMD + WRCL + LENH/L + DUMMY + DATA + CRC
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Figure 7.1 shows a complete SPI communication protocol. You can find all the fields described above.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
CS
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CLK
MOSI CMD WRCL LENH LENL DUMMY0 DUMMY1 DUMMYn WDATA0 WDATAn WCRCL WCRCH
MISO
O en STATUS RDATA0 RDATAn RCRCL RCRCH

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TimeGen
Figure 7.1: A complete SPI communication protocol

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Here is the detail descriptions of every field:

尔 hC
CMD: Command byte, value range: 0x00~0xFF, generally means register address.
WRCL: Command control byte.
W/R N/A CRCEN N/A N/A N/A N/A N/A

韦 ec
BIT7: W/R, 0 – write, 1 – read
BIT6: N/A, reserved

博 lT
BIT5: CRCEN, 0 – CRC disable of data, 1 – CRC enable of data

麦 ca
BIT4-0: N/A, reserved
LENH: High byte of data length which includes DATA0~DATAn.

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LENL: Low byte of data length which includes DATA0~DATAn.
DUMMY0~DUMMYn: Dummy bytes; by default, n is 2, so host need send 3 dummy bytes.
DATA0~DATAn: Data field of this command.
CRCL(low byte) / CRCH(high byte): CRC of data calculated from DATA0 to DATAn; If CRCEN (bit5) bit of WRCL don‟t set, the command
doesn‟t have these field.
How to calculate CRC, please contact your local FAE.
STATUS: status of SPI communication.
busy N/A sleep N/A N/A N/A appid1 appid0
BIT7: busy, 0 – idle, 1 – busy

Preliminary
FT8006S-AN
BIT6: N/A, reserved
BIT5: sleep, 0 – mcu active, 1 – mcu sleep
BIT4-2: N/A, reserved
BIT1-0: appid, 01 – app, 11 – romboot
Warning: When check bit 7 or bit 5 of status is 1, host need retry this SPI transmission for 3 times.
7.9.2 Host Write Data to Slave
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This is the standard write function of SPI communication protocol. Please refer to figure 7.3 for the detail waveform of SPI write.
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
CS
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CLK
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MOSI CMD WRCL LENH LENL DUMMY0 DUMMY1 DUMMYn WDATA0 WDATAn WCRCL WCRCH
O en
MISO STATUS
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TimeGen
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Figure 7.3: SPI write with data
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7.9.3 Host Read Data from Slave

This is the standard read function of SPI communication protocol. Please refer to figure 7.4 for the detail waveform of SPI read.
尔 hC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
CS
韦 ec
CLK
MOSI CMD WRCL LENH LENL DUMMY0 DUMMY1 DUMMYn

博 lT
MISO STATUS RDATA0 RDATAn RCRCL RCRCH

麦 ca
TimeGen
Figure 7.4: SPI read data

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7.10 Interrupt signal form FT8006S_AN to Host

As for standard CTPM (Capacitive touch panel module), host needs to use both interrupt signal and I2C/SPI interface to get
the touch data. FT8006S-AN will output an interrupt request signal to the host when there is a valid touch. Then host can get the touch data
via I2C/SPI interface. If there is no valid touch detected, the TP_INT will output high level, and the host does not need to read the touch data.

Preliminary
FT8006S-AN
The interrupt trigger mode is the falling-edge trigger mode.
Touch Start Touch End
TP_INT
DATA DATA DATA

I2C DATA Blank ……. Blank
Packet 0 Packet 1 Packet N
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While for interrupt trigger mode, TP_INT signal will be set to low if there is a touch detected. But whenever an update of valid touch
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data, FT8006S-AN will produce a valid pulse on TP_INT port for TP_INT signal, and host can read the touch data periodically according to
the frequency of this pulse. In this mode, the pulse frequency is the touch data updating rate.
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While detect the falling edge of TP_INT port, host can read touch data from register 0x01 of work mode, then parse and
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combine touch data into X/Y coordinates and other attributes, please refers to the register map for details.
O en
7.11 CTPM Register Map
The next describes the standard CTPM (Capacitive touch panel module) communication registers in address order for working
se id
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mode.
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7.11.1 Working Mode

The CTPM is fully functional as a touch screen controller in working mode. The access address to read and write is just logical
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address which is not enforced by hardware. Here is the working mode register map.
尔 hC
Working Mode Register Map

Default Host
Address Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Value Access
0x00 DEV_MODE 0x00 [2:0]Device Mode R/W
韦 ec
0x01 Reserved 0x00 Reserved R

0x02 TD_STATUS 0x00 [3:0] Number of touch points R
[3:0] 1st Touch
0x03 P1_XH 0xFF [7:6]1st Event Flag R
博 lT
X Position[11:8]
0x04 P1_XL 0xFF [7:0] 1st Touch X Position R
[3:0] 1st Touch
0x05 P1_YH 0xFF [7:4] 1st Touch ID R
麦 ca
Y Position[11:8]
0x06 P1_YL 0xFF [7:0] 1st Touch Y Position R
0x07 P1_WEIGHT 0xFF [7:0] 1st Touch Weight R
0x08 P1_MISC 0xFF [7:4] 1st Touch Area R
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[3:0]2nd Touch
0x09 P2_XH 0xFF [7:6]2nd Event Flag R
X Position[11:8]
0x0A P2_XL 0xFF [7:0] 2nd Touch X Position R
[3:0] 2nd Touch
0x0B P2_YH 0xFF [7:4] 2ndTouch ID R
Y Position[11:8]
0x0C P2_YL 0xFF [7:0] 2nd Touch Y Position R
0x0D P2_WEIGHT 0xFF [7:0] 2nd Touch Weight R
0x0E P2_MISC 0xFF [7:4] 2nd Touch Area R
[3:0] 3rd Touch
0x0F P3_XH 0xFF [7:6]3rd Event Flag R
X Position[11:8]
0x10 P3_XL 0xFF [7:0] 3rd Touch X Position R
[3:0] 3rd Touch
0x11 P3_YH 0xFF [7:4] 3rd Touch ID R
Y Position[11:8]
0x12 P3_YL 0xFF [7:0] 3rd Touch Y Position R
0x13 P3_WEIGHT 0xFF [7:0] 3rd Touch Weight R
0x14 P3_MISC 0xFF [7:4] 3rd Touch Area R
[3:0] 4th Touch
0x15 P4_XH 0xFF [7:6]4th Event Flag R
X Position[11:8]
0x16 P4_XL 0xFF [7:0] 4th Touch X Position R
[3:0]4th Touch
0x17 P4_YH 0xFF [7:4] 4th Touch ID R
Y Position[11:8]
0x18 P4_YL 0xFF [7:0] 4th Touch Y Position R

Preliminary
FT8006S-AN
0x19 P4_WEIGHT 0xFF [7:0] 4th Touch Weight R
0x1A P4_MISC 0xFF [7:4] 4th Touch Area R
[3:0]5th Touch
0x1B P5_XH 0xFF [7:6]5th Event Flag R
X Position[11:8]
0x1C P5_XL 0xFF [7:0] 5th Touch X Position R
[3:0]5th Touch
0x1D P5_YH 0xFF [7:4] 5th Touch ID R
Y Position[11:8]
0x1E P5_YL 0xFF [7:0] 5th Touch Y Position R
0x1F P5_WEIGHT 0xFF [7:0] 5th Touch Weight R
0x20 P5_MISC 0xFF [7:4] 4th Touch Area R
[3:0] 6th Touch
X Position[11:8]
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[3:0] 6th Touch
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Y Position[11:8]
[3:0]7th Touch
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X Position[11:8]
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[3:0] 7th Touch
0x29 P7_YH 0xFF [7:4] 7thTouch ID R
Y Position[11:8]
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0x2A P7_YL 0xFF [7:0] 7th Touch Y Position R
0x2B P7_WEIGHT 0xFF [7:0] 7th Touch Weight R
0x2C P7_MISC 0xFF [7:4] 7th Touch Area R
[3:0] 8th Touch
0x2D P8_XH 0xFF [7:6]8th Event Flag R
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X Position[11:8]
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0x2E P8_XL 0xFF [7:0] 8th Touch X Position R
[3:0] 8th Touch
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0x2F P8_YH 0xFF [7:4] 8th Touch ID R

Y Position[11:8]
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[3:0] 9th Touch
尔 hC

X Position[11:8]
[3:0]9th Touch
Y Position[11:8]
韦 ec

[3:0]10th Touch
X Position[11:8]
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0x3A P10_XL 0xFF [7:0] 10th Touch X Position R

[3:0]10th Touch
0x3B P10_YH 0xFF [7:4] 10th Touch ID R
麦 ca
Y Position[11:8]
0x3C P10_YL 0xFF [7:0] 10th Touch Y Position R
0x3D P10_WEIGHT 0xFF [7:0] 10th Touch Weight R
0x3E P10_MISC 0xFF [7:4] 10th Touch Area R
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...
0xA5 PWR_MODE Power Mode：0 - Active, 1 - Monitor, 3 - Sleep
0xA6 FW_VER - Firmware Version
...
7.11.2 DEVICE_MODE
This is the device mode register, which is configured to determine the current mode of the chip.
Address Bit Address Register Name Description
000b WORKING Mode
0x00 6:4 [2:0]Device Mode
100b TEST Mode
7.11.3 TD_STATUS
This register is the Touch Data status register.

Preliminary
FT8006S-AN
3:0 Number of touch points [3:0] The detected point number, 1-10 is valid.
0x02
7:4 Reserved
7.11.4 Pn_XH (n:1-10)
This register describes MSB of the X coordinate of the nth touch point and the corresponding event flag.
00b: Press Down
01b: Lift Up
7:6 Event Flag
0x03 10b: Contact
+ (n-1)*6 11b: No event
5:4 Reserved
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3:0 Touch X Position [11:8] MSB of Touch X Position in pixels
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7.11.5 Pn_XL (n:1-10)
This register describes LSB of the X coordinate of the nth touch point.
0x04
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7:0 Touch X Position [7:0] LSB of the Touch X Position in pixels
nl tia
+ (n-1)*6
7.11.6 Pn_YH (n:1-10)
This register describes MSB of the Y coordinate of the nth touch point and corresponding touch ID.
O en
Touch ID of Touch Point, this value is 0x0F when the ID is
0x05 7:4 Touch ID[3:0]
invalid
+ (n-1)*6
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3:0 Touch Y Position [11:8] MSB of Touch Y Position in pixels
y
7.11.7 Pn_YL (n:1-10)
U nf
This register describes LSB of the Y coordinate of the nth touch point.
o
0x06
7:0 Touch Y Position [7:0] LSB of the Touch Y Position in pixels
+ (n-1)*6
尔 hC
7.11.8 Pn_WEIGHT (n:1-10)

This register describes weight of the nth touch point.
韦 ec
0x07
7:0 Touch Weight[7:0] Touch pressure value
+ (n-1)*6
7.11.9 Pn_MISC (n:1-10)
博 lT
This register describes the miscellaneous information of the nth touch point.
麦 ca
0x08
7:4 Touch Area[3:0] Touch area value
+ (n-1)*6
Fo
7.11.10 PWR_MODE
This register describes power mode if touch controller
0xA5 7:0 PWR_MODE[7:0] Power Mode：0 - Active, 1 - Monitor, 3 - Sleep
Host writes 0x01 to this register, then touch controller will enter monitor mode.
Host writes 0x03 to this register, then touch controller will enter sleep mode.
7.11.11 FW_VER
This register describes version of TP firmware.
0xA6 7:0 FW_VER[7:0] Version of TP firmware

Preliminary
FT8006S-AN
8. ELECTRICAL SPECIFICATION
8.1. Absolute Maximum Ratings
O O
(AVDD = 4.5V ~ 6.5V, AVEE = -4.5V ~ -6.5V, VDDI = 1.65V ~ 1.95V, Ta = -30 C ~ 70 C)
Parameter Symbol Rating Unit Note
Power Supply Voltage 1 VDDI-VSS -0.3 ~ +4.5 V

Power Supply Voltage 2 VDDAM-VSS -0.3 ~ +4.5 V
Power Supply voltage 3 VDD_TP-VSS -0.3 ~ +4.5 V
Power Supply voltage 4 VDDI_TP-VSS -0.3 ~ +4.5 V
r
Power Supply Voltage 5 MTP_PWR-VSS -0.3 ~ +8.8 V
Fo
Power Supply Voltage 6 AVDD-VSS -0.3 ~ +6.6 V
Power Supply Voltage 7 VSS-AVEE -0.3 ~ +6.6 V
Power Supply Voltage 8 VGH-VGL -0.3 ~ +32 V
l
Input Voltage Vt -0.3 ~ VDDI+0.3 V
nl tia
O
Operating Temperature Topr -30 ~ +70 C
O
Storage Temperature Tstg -55 ~ +110 C
O en
Note1. The maximum applicable voltage on any pin with respect to 0V.
Note2. Device is subject to be damaged permanently if stresses beyond those absolute maximum ratings listed above.
se id
y
U nf
o
尔 hC
韦 ec
博 lT
麦 ca
Fo

Preliminary
FT8006S-AN
8.2. DC Characterisitics
8.2.1. Basic DC characteristic
o o
(AVDD = 4.5V~6.5V,AVEE = -4.5V~-6.5V,VDDI = 1.65V~1.95V, Ta = -30 C ~ 70 C)
Specification
Parameter Symbol Conditions Unit Notes
MIN TYP MAX
Power & Operation Voltage
Analog Operating voltage AVDD Operating Voltage 4.5 5.5 6.5 V
Analog Operating voltage AVEE Operating Voltage -6.5 -5.5 -4.5 V
r
Logic Operating voltage VDDI I/O supply voltage 1.65 1.8 1.95 V
Fo
Digital Operating voltage VDD Digital supply voltage 1.125 1.3 1.5 V
Hissi interface Operating voltage VDDAM MIPI supply voltage 1.65 1.8 1.95 V
Touch Operating voltage VDDI_TP Touch supply voltage 1.65 1.8 1.95 V
l
Input / Output
nl tia
Logic High level input voltage VIH - 0.7VDDI - VDDI V
Logic Low level input voltage VIL - VSS - 0.3VDDI V
O en
Logic High level output voltage VOH IOH = -1.0mA 0.8VDDI - VDDI V
Logic Low level output voltage VOL IOL = +1.0mA VSS - 0.2VDDI V
Logic High level input current IIH Vin = VDDI or VDDAM - - 1 uA
se id
y
Logic Low level input current IIL Vin = VDDI or VDDAM -1 - - uA
U nf
VCOM Operation
VCOMDC output voltage VCOM AVDD=AVEE=+/-5V -2.3 - 0.3 V
o
Source Driver
尔 hC
Gamma positive reference voltage VGMP VGMP<AVDD-0.2V 3.5 - 6.0 V

Gamma negative reference voltage VGMN VGMN>AVEE-0.2V -6.0 - -3.5 V
Source output voltage VSD - VGMN - VGMP -
Sout >=+4.2V,
韦 ec
Output deviation voltage - - 30 mV

V,dev Sout<=+0.8V
(Source positive output channel)
+4.2V>Sout>+0.8V - - 15 mV
博 lT
Sout <=-4.2V,
Output deviation voltage - - 30 mV
V,dev Sout>=-0.8V
(Source negative output channel)
麦 ca
-4.2V<Sout<-0.8V - - 15 mV
Output offset voltage VOFSET - - - 100 mv
Fo
Reference Voltage
Internal reference voltage VREF - 1.94 2.0 2.06 V
Internal reference voltage VREF_TP - 1.5 3.5 5 V
Booster operation
Range=( AVDD-AVEE)
Pump output voltage VGH 7.3 - 20.0 V
~( 3XAVDD-2 AVEE)
Range=(AVDD+AVEE)
Pump output voltage VGL -18.0 - -5.3 V
~( 2AVEE-AVDD)
Regulator output voltage VCL - -4.5 -2.75 -2 V
Note1. The maximum applicable voltage on any pin with respect to 0V.
Note2. Device is subject to be damaged permanently if stresses beyond those absolute maximum ratings listed above.

Preliminary
FT8006S-AN
8.2.2. MIPI DC characteristic
DC characteristics for MIPI-DSI
o o
(AVDD = 5.0V~6.5V,AVEE = -5.0V~-6.5V,VDDI = 1.65V~1.95V, Ta = -30 C ~ 70 C)
Specification
Parameter Symbol Conditions Unit
MIN TYP MAX
Power supply voltage for MIPI Interface
VDDAM - 1.65 1.8 1.95 V
Power supply voltage for MIPI interface
LVDSVDD - 1.125 1.3 1.5 V
r
LPDT Input Characteristics
Fo
Pad signal voltage range VI - -50 - 1350 mV
Ground Shift VGNDSH - -50 - 50 mV
Logic 0 input threshold VIL - 0 - 550 mV
l
Logic 1 input threshold VIH - 880 - LVDSVDD mV
nl tia
Input hysteresis VHYST - 25 - - mV
LPDT Output Characteristics
O en
Output low level VOL - -50 - 50 mV
Output high level VOH - 1.1 1.2 1.3 V
Logic 1 contention threshold VIHCD,MIN - 450 - LVDSVDD mV
se id
y
Logic 0 contention threshold VILCD,MAX - 0 - 200 mV
U nf
Output impedence of LPDT ZOLP - 80 100 125 ohm

Hi-speed Input/Output Characteristics
o
Single-end input low voltage VILHS - -40 - - mV

尔 hC
Single-end input high voltage VIHHS - - - 460 mV

Single-end threshold for HS termination
VTERM-EN - - - 450 mV
enable
Differential input low threshold VIDTL - -70 - - mV
韦 ec
Differential input high threshold VIDTH - - - 70 mV

Common mode voltage VCMRXDC - 70 - 330 mV
博 lT
Differential input impedence ZID - 80 100 125 ohm

麦 ca
Fo

Preliminary
FT8006S-AN
8.3. AC Characterisitics
8.3.1. Reset timing characteristics
tRESW shorter than 75us, Reset will be rejected.

Short than 75us tRESW tREST
RESX
r
Fo
Internal Initial Condition
Normal Operation Reseting
Status (Default for H/W Reset)
l
nl tia
o o
VSS=0V, VDDI=1.65V to 1.95V, Ta = -30 C to 70 C
O en
Symbol Parameter MIN TYP MAX Note Unit
tRESW *1) Reset low pulse minimum width 150 - - Reset signal recognized us
se id
tREST *2) Reset complete time 5 - - Reset action complete ms
y
Table: Reset input timing
U nf
Note 1. RESX low pulse that is too short does not cause irregular system reset according to the table below.
o
尔 hC
RESX Pulse Action

Shorter than 75us Reset Rejected
Longer than 150us Reset Recognized
韦 ec
Reset sequence starts

Between 75us and 150us
(It depends on voltage and temperature condition.)
博 lT
Note 2. Once Reset low pulse is recognized, system requires RESX remaining low for another 5ms to complete H/W reset.
麦 ca
Note 3. During H/W Reset flow, ID1/ID2/ID3 and VCOM value in OTP will be latched to internal register during this period. This loading is
Fo
done every time when H/W reset is complete ; The H/W reset sequence is complete when RESX is remaining low longer than
tRESW + tREST.
Note 4. It is necessary to wait 15msec after releasing RESX before sending commands. Also Sleep Out command cannot be sent for 120
msec.

Preliminary
FT8006S-AN
2
8.3.2. I C interface characteristics
Tf Tr TSU;DAT
SDA
TSU;STA THD;DAT
Tf THIGH Tr
r
SCL
Fo
THD;STA
Start fSCL TLOW
l
nl tia
Table: I2C Interface Characteristics
O en
Symbol Parameter Conditions Min. Typ. Max. Unit
fSCLK SCL clock frequency - 10 - 400 kHz
se id
TLOW SCL clock LOW period - 1.2 - - us
y
THIGH SCL clock HIGH period - 0.6 - - us
U nf
TSU;DATA data set-up time - 250 - - ns

THD;DATA data hold time - 0 - - us
o
Note 2
Tr SCL and SDA rise time 20+0.1Cb - 300 ns
Note 2
尔 hC
Tf SCL and SDA fall time 20+0.1Cb - 300 ns

Tf SDA fall time for read out - 20+0.1Cb - 1000 ns
Cb Capacitive load represented by each bus line - - - 400 pF
TSU;STA Setup time for a repeated START condition - 0.6 - - us
韦 ec
THD;STA START condition hold time - 0.6 - - us

TSU;STO Setup time for STOP condition - 0.6 - - us
博 lT
Note 1
TSW Tolerable spike width on bus - - 50 ns
TBUF BUS free time between a STOP and START condition - 4.7 - - us
麦 ca
Note1: The device inputs SDA and SCL are filtered and will reject spikes on the bus lines of width <tSW(max) .
Note2: The rise and fall times specified here refer to the driver device and are part of the general fast I 2C-bus specification. Cb = capacitive load per bus line.
Fo
Note3: All timing values are valid within the operating supply voltage and ambient temperature ranges and are referenced to VIL and VIH with an input voltage
swing of VSS to VDDI

Preliminary
FT8006S-AN
8.3.3. SPI interface characteristics ( mode 0 )
TCS TLH
TPER
TSET THOL
SPI_SS
TLS1 TLS2
SPI_ SCL
r
Fo
SPI_ MOSI
SPI_ MISO
l
nl tia
TOUT
AC Characteristics of SPI Interface
O en
Parameter Conditions Symbol Min Typ Max Unit
se id
Terminal : SCL and SS
y
U nf
Time from CS(10%) to SCL(90%) TLS1 50 ns

o
Time from SCL(10%) to CS(90%) TLS2 50 ns

尔 hC
Terminal : SCL and MOSI
Data Setup Time : Time from changing

TSET 10 ns
MOSI(10%, 90%) to SCL(90%)
韦 ec
Data Hold Time : Time from changing SCL(90%)

THOL 5 ns
博 lT
to MOSI(10%, 90%)
麦 ca
Terminal : SCL and MISO
Time from SCL(10%) to stable MISO(10%, 90%) 20pF,20Ω TOUT 33 ns

Fo
Terminal : SS
Time between SPI cycles, SS at high level (90%) TLH 30 us
SPI SCL Freq 12 Mhz

Preliminary
FT8006S-AN
8.3.4. MIPI-DSI characteristics
High speed mode
Specification
Parameter Symbol Parameter Unit
MIN TYP MAX
High Speed Mode
DSI-CLK+/- 2xUIINST Double UI instantaneous 2 - 25 ns
DSI-CLK+/- UIINSTA , UIINSTB UI instantaneous Halfs 1 - 12.5 ns
DSI-Dn+/- tDS Data to clock setup time 0.15 - - UI
r
DSI-Dn+/- tDH Data to clock hold time 0.15 - - UI
Fo
DSI-CLK+/- tDRTCLK Differential rise time for clock 150 - 0.3UI ps
DSI-Dn+/- tDRTDATA Differential rise time for data 150 - 0.3UI ps
DSI-CLK+/- tDFTCLK Differential fall time for clock 150 - 0.3UI ps
l
DSI-Dn+/- tDFTDATA Differential fall time for data 150 - 0.3UI ps
nl tia
DSI-CLK+
O en
se id
DSI-CLK-
y
UIINSTA UIINSTB
U nf
2xUIINST
o
尔 hC
DSI-CLK+
韦 ec
DSI-CLK-
博 lT
DSI-Dn+
麦 ca
DSI-Dn-
Fo
tDS tDH tDS tDH

Preliminary
FT8006S-AN
tDFTDATA tDFTDATA
tDFTCLK tDFTCLK
DSI-CLK+/-
DSI-Dn+/- 20%
60%
0V Reference for Differential
Clock / Data input
Full HS swing
r
Voltage
Fo
20%
Figure: AC characteristics for MIPI-DSI High speed mode
l
nl tia
Low power mode
Specification
O en
MIN TYP MAX
Low Power mode
Length of LP-00, LP-01, LP-10 or
se id
y
DSI-D0+/- TLPXM LP-11 periods MP y 50 - - ns
U nf
Module
Length of LP-00, LP-01, LP-10 or
58 - - ns
o
DSI-D0+/- TLPXD LP-11 periods Display Module

尔 hC
Time-out before the MPU start

DSI-D0+/- TTA-SURED TLPXD - 2XTLPXD ns
driving
Time to drive LP-00 by display
DSI-D0+/- TTA-GETD 5XTLPXD - - ns
韦 ec
module
Time to drive LP-00 after
DSI-D0+/- TTA-GOD 4XTLPXD - - ns
turnaround request - MPU
博 lT
Ratio of TLPXM / TLPXD between MCU

DSI-D0+/- Ratio TLPX 2/3 - 3/2 -
and display module
麦 ca
MCU is controlling Control Change Display Module is Controlling

Fo
TLPXM TLPXM TLPXM TLPXD TLPXD

DSI-D0+
DSI-D0- TTA-SUREM
LP-11 LP-10 LP-00 LP-10 LP-00 LP-10 LP-11
TTA-GETD
Figure: BTA from the MCU to the Display Module

Preliminary
FT8006S-AN
Display Module is Controlling Control Change MCU is controlling
TLPXD TLPXD TLPXD TLPXM TLPXM

DSI-D0+
DSI-D0- TTA-SURED
LP-11 LP-10 LP-00 LP-10 LP-00 LP-10 LP-11
TTA-GOD
r
Fo
Figure: BTA from the Display Module to the MCU
Bursts
Specification
l
MIN TYP MAX
nl tia
High Speed Data Transmission Bursts
Length of any low-power state
50 - - ns
O en
DSI-Dn+/- TLPX
period
Time to drive LP-00 to prepare
DSI-Dn+/- THS-PREPARE 40ns + 4UI - 85ns + 6UI ns
for HS transmission
se id
y
THS-PREPARE THS-PREPARE + time to drive HS-0
DSI-Dn+/- 145ns + 10UI - - ns
U nf
+THS-ZERO before the sync sequence

Time to enable Data Lane receiver
Time for Dn to
o
DSI-Dn+/- TD-TERM-EN line termination measured from - 35ns + 4UI ns

reach VTERM-EN
when Dn crosses VIL(max)
尔 hC
Time-out at RX to ignore transition

DSI-Dn+/- THS-SKIP 40 - 55ns + 4UI ns
period of EoT
Time to drive flipped differential
max (8UI,
韦 ec
DSI-Dn+/- THS-TRAIL state after last payload data bit of - - ns

60ns+4UI)
a HS transmission burst
DSI-Dn+/- THS-EXIT Time to drive LP-11 after HS burst 100 - - ns
博 lT
Time from start of THS-TRAIL period

DSI-Dn+/- TEoT - - 105ns + 12UI ns
麦 ca
to start of LP-11 state
DSI-CLK+/-
Fo
TLPX THS-PREPARE THS-ZERO THS-SYNC

Disconnect
DSI-Dn+/- Terminator
-VIH(min)
-VIL(max)
-VTERM-EN(max)
THS-SKIP
TD-TERM-EN
LP-11 LP-01 LP-00 TEOT LP-11
THS-TRAIL THS-EXIT
THS-SETTLE
Figure: High Speed Data Transmission Bursts

Preliminary
FT8006S-AN
Specification
MIN TYP MAX
Switching the clock Lane between clock Transmission and Low Power Mode
Time that the transmitter shall
continue sending HS clock after
DSI-CLK+/- TCLK-POST 60ns + 52UI - - ns
the last associated Data Lane has
transitioned to LP mode
r
Time that the HS clock shall be
Fo
driven prior to any associated
DSI-CLK+/- TCLK-PRE 8 - - UI
Data Lane beginning the transition
from LP to HS mode
l
Time to drive LP-00 to prepare
nl tia
DSI-CLK+/- TCLK-PREPARE 38 - 95 ns
for HS clock transmission
Time to enable Clock Lane
Time for Dn to
O en
DSI-CLK+/- TCLK-TERM-EN receiver line termination measured - 38 ns
reach VTERM-EN
from when Dn crosses VIL(max)
TCLK-PREPARE TCLK-PREPARE + time for lead HS-0
se id
DSI-CLK+/- 300 - - ns
y
+TCLK-ZERO drive period before starting Clock
Time to drive HS differential state
U nf
DSI-CLK+/- TCLK-TRAIL after last payload clock bit of a HS 60 - - ns

transmission burst
o
Time from start of TCLK-TRAIL period

尔 hC
DSI-CLK+/- TEoT - - 105ns + 12UI ns

to start of LP-11 state
Disconnect
Terminator
DSI-CLK+/- TCLK-POST TEoT TCLK-SETTLE
TCLK-MISS TCLK-TERM-EN
韦 ec
-VIH(min)
-VIL(max)
博 lT
TCLK-TRAIL
DSI-Dn+/- TCLK-PREPARE TCLK-ZERO TCLK-PRE
Disconnect
Terminator
麦 ca
-VIH(min)
-VIL(max)
Fo
Figure: Switching the clock Lane between clock Transmission and Low Power Mode
LP-11 between High Speed and Low Power Modes

DSI-D0 High Speed or Low Power modes are starting or finishing from/to Stop State (SS, LP-11) when 4
different combinations, what are listed below, are possible:
1. High Speed Mode => Stop State (SS, LP-11) => High Speed Mode
2. High Speed Mode => Stop State (SS, LP-11) => Low Power Mode
3. Low Power Mode => Stop State (SS, LP-11) => High Speed Mode
4. Low Power Mode => Stop State (SS, LP-11) => Low Power Mode

Preliminary
FT8006S-AN
The Low Power Mode is also including 2 different functions:
1. Escape
2. Bus Turnaround (BTA)
Stop State (SS, LP-11) Timings from Previous mode to Next mode
Next
Escape mode HSDT BTA
Previous
Min Max Min Max Min Max
r
Escape mode 100 ns - 100 ns - 100 ns -
Fo
HSDT 60ns + 52UI - 60ns + 52UI - 60ns + 52UI -
l
nl tia
BTA 100 ns - 100 ns - 100 ns -
LP11
O en Previous Next
se id
y
U nf
o
尔 hC
韦 ec
博 lT
麦 ca
Fo

Preliminary
FT8006S-AN
8.3.5. Power On Off Sequence
1. There will be no damage to the display module if the power sequences are not met.
2. There will be no abnormal visible effects on the display panel during the Power On/Off sequences.
3. There will be no abnormal visible effects on the display between end of Power On sequence and before receiving Sleep Out command.
Also between receiving Sleep In command and Power Off sequence.
4. RESX and TP_RSTN must be held stablely by host during Power On Sequence, otherwise function is not guaranteed.
5. The display module can also initialize and calibrate DSI-CLK +/- and DSI-D0 +/- lanes within 5ms after LP-11 (Clock and Data Channels),
r
VDDI are applied and H/W Reset is not active (5ms is as same as the Reset Cancelling Time).
Fo
6. During Power off, VDDI cab be powered down 5ms after AVDD/AVVEE power down if LCD in Sleep-In Mode.
7. During Abnormal power dropping, VDDI can start power down 5ms after AVDD/AVEE power down.
8. BL Enable timing is for reference only and not restricted ( T8/T9 ).
l
nl tia
O en
Power On/Off Sequence
se id
Power on Sequence Power off Sequence Power On Sequence
y
T14
U nf
VDDI T11
T1
T2 T1
T2
T10
AVDD T4
o
Trw Trw
AVEE
尔 hC
Trf
Trf
T4
TP_RSTN FW Load TP SCAN
T3
T7
T5 Trl T5 T5 Trl T5
RESX OTP
Code
T6
韦 ec
T15 T15
MIPI Interface Initial Display Data Power off
LP11 LP11
Code Code
BL Enable BL OFF T8 BL ON T9 BL OFF

博 lT
LCD
Flash Mode
Code
Power On Display Display Power Off
LCD LCD Display On
Non-Flash Mode
Code
Sequence Off Off Sequence
麦 ca
Fo

Preliminary
FT8006S-AN
Power On/Off Sequence with VDDI in DSTB mode
Power on Sequence Power Off Sequence Power On Sequence
VDDI
T1
T2
T10 T14
AVDD T4
Trw Trw
AVEE
Trf
r
Trf
T4
T12 T13
TP_RSTN TP STOP
FW Load TP SCAN
Fo
T3
T7
T5 Trl T5 T5 Trl T5
OTP
RESX
Code
T6
T15
MIPI Interface Initial DSTB
LP11 Display Data LP11
Code Code
l
nl tia
LCD
Flash Mode
Code
Power On Display Display
LCD LCD Display On DSTB Mode
Non-Flash Mode Code Sequence Off Off
O en
se id
y
Power On/Off Sequence with TP Gesture Mode
U nf
Power on Sequence DSTB Sequence TP Gesture Mode Power On Sequence

o
VDDI
T1
尔 hC
T2
AVDD
Trw Trw
AVEE
Trf
Trf
T4
T12 T13
韦 ec
TP_RSTN TP SCAN
FW Load TP SCAN
T3
T7
T5 Trl T5 T5 Trl T5
RESX OTP
Code T17
T6
博 lT
T15
MIPI Interface Initial DSTB
LP11 Display Data LP11
Code Code
麦 ca
LCD
Flash Mode
Code
Power On Display Display
LCD LCD Display On DSTB Mode
Non-Flash Mode Code
Sequence Off Off
Fo

Preliminary
FT8006S-AN
Power On / Off Sequence Timing
Parameter Description Min. Max. Unit
T1 Rise time from 0.1VDDI to 0.9VDDI 0 5 mS
T2 AVDD power up after VDDI power on 3 mS
T2d AVEE power up after AVDD power up 0 mS
T3 TP reset time after VDDI power on 5 mS
r
Fo
T4 TP Reset release time after AVDD power on 100 uS
T5 TP Reset release to LCD Reset release 0 mS
T6 FLASH download LCD code after LCD Reset 35 mS
l
nl tia
T7 with flash LCD Reset release to TP SCAN Start 220 mS
T7 without flash Between host load APP and TP SCAN Start 220 mS
O en
T8 LED On after Initial Code 150 mS
T9 LED Off after power off code 50 mS

se id
y
T10 AVEE power down after power off code 150 mS
U nf
T10d AVDD power down after AVEE power down 0 mS
T11 VDDI power down after AVDD power off 5 mS

o
T12 TP reset time before LCD reset 5 mS

尔 hC
T13 RESX reset falling to TP reset release 5 120 mS
T14 VDDI rise again after previous VDDI powered down 50 mS

韦 ec
T15 MIPI signals start ( Hi-Z/GND to LP11 ) after VDDI power on 3 mS

nd
Trf 2 LCD Reset time after TP_RST assert 5 mS
博 lT
nd
Trl 2 LCD/TP Reset overlap time 5 mS
nd
Trw TP Reset High Level Width before 2 Reset 5 10 mS
麦 ca
Fo

Preliminary
FT8006S-AN
9. CHIP INFORMATION
All chip information shown here are defined without temperature compensation.
9.1 PAD Assignment

32146um
D1 D4 B3 B1 B1 B3 E4 E1
D2 B4 B4 E2
844
4088
4084
4080
4076
4072
4068
4064
840
836
832
828
824
820
D3 B2 B2 E3
r
D5 E5
Fo
4067
4063
4091
4087
4083
4079
4075
4071
843
831
839
835
827
823
819
816
B7 B5 B5
842
4090
4086
4082
4078
4074
4070
4066
4062
838
834
830
826
822
818
815
Y
1117um
4089
4085
4081
4077
4073
4069
4065
4061
841
837
833
829
825
821
817
814
(0.0) B9
l
nl tia
B8 B6 FT8006S-AN B8 B6
C1
(Face up)
O en
813
812
811
808
807
809
810
A2 A2
1
A4 A4
A5 A1 A3 A3 A1 A6
se id
y
U nf
Symbol Size Symbol Size Symbol Size Symbol Size Symbol Size
A1 24 B1 15 C1 376 D1 115 E1 115

o
A2 92 B2 100 D2 59 E2 59
尔 hC
A3 39 B3 38.8 D3 46.1 E3 46.1

A4 95 B4 94 D4 30.35 E4 78.85
韦 ec
A5 221.5 B5 20 D5 40 E5 40
A6 232.5 B6 23.8
博 lT
B7 162.35
B8 9.7
麦 ca
B9 172.05 Unit=um
Fo
9.2 PAD Dimension

Size
Item PAD No. Unit
X Y
Chip Size - 32146 1117
Chip thickness - 170
1 - 813 24 92
Pad Size
814 - 4091 15 100
1 - 813 39 0
Pad Pitch
814 - 4091 9.7 120
Note1: Chip size includes 62um scribe line before wafer sawing
Note2: Have no Temperature compensation design.

Preliminary
FT8006S-AN
9.3 PAD Location

No. PAD Name X Y No. PAD Name X Y No. PAD Name X Y
1 GOUT_L[1] -15839.5 -417.5 51 DUMMY -13889.5 -417.5 101 VREF_TP -11939.5 -417.5
2 GOUT_L[2] -15800.5 -417.5 52 DUMMY -13850.5 -417.5 102 VREF_TP -11900.5 -417.5
3 GOUT_L[3] -15761.5 -417.5 53 SYNC_DAT_L[0] -13811.5 -417.5 103 VREF_TP -11861.5 -417.5
6 GOUT_L[6] -15644.5 -417.5 56 SYNC_DAT_L[1] -13694.5 -417.5 106 VDD_TP -11744.5 -417.5
r
Fo
9 GOUT_L[9] -15527.5 -417.5 59 SYNC_DAT_L[3] -13577.5 -417.5 109 VSS -11627.5 -417.5
l
12 GOUT_L[12] -15410.5 -417.5 62 SYNC_DAT_L[4] -13460.5 -417.5 112 VCOM_PASS_L -11510.5 -417.5
nl tia
O en
16 GOUT_L[16] -15254.5 -417.5 66 SYNC_DAT_L[6] -13304.5 -417.5 116 VCOM -11354.5 -417.5
17 GOUT_L[17] -15215.5 -417.5 67 DCHG2_L -13265.5 -417.5 117 VCOM -11315.5 -417.5
se id
18 GOUT_L[18] -15176.5 -417.5 68 DCHG1_L -13226.5 -417.5 118 VCOM -11276.5 -417.5
y
19 GOUT_L[19] -15137.5 -417.5 69 VGLO_L -13187.5 -417.5 119 VCOM -11237.5 -417.5
U nf
20 GOUT_L[20] -15098.5 -417.5 70 VGLO_L -13148.5 -417.5 120 VCOM -11198.5 -417.5
21 GOUT_L[21] -15059.5 -417.5 71 VGLO_L -13109.5 -417.5 121 VCOM -11159.5 -417.5
o
22 GOUT_L[22] -15020.5 -417.5 72 VGH2_L -13070.5 -417.5 122 VCOM_OPT_L -11120.5 -417.5
23 DUMMY -14981.5 -417.5 73 VGH1_L -13031.5 -417.5 123 VCOM_OPT_L -11081.5 -417.5
尔 hC
26 DUMMY -14864.5 -417.5 76 AVSS -12914.5 -417.5 126 VCOM_OPT_L -10964.5 -417.5
韦 ec
博 lT
30 DUMMY -14708.5 -417.5 80 AVSS -12758.5 -417.5 130 AVEE -10808.5 -417.5
31 DUMMY -14669.5 -417.5 81 AVSS -12719.5 -417.5 131 AVEE -10769.5 -417.5
32 DUMMY -14630.5 -417.5 82 AVSS -12680.5 -417.5 132 AVEE -10730.5 -417.5
麦 ca
33 DUMMY -14591.5 -417.5 83 AVSS -12641.5 -417.5 133 AVEE -10691.5 -417.5
34 DUMMY -14552.5 -417.5 84 AVSS -12602.5 -417.5 134 AVEE -10652.5 -417.5
Fo
35 DUMMY -14513.5 -417.5 85 AVSS -12563.5 -417.5 135 AVEE -10613.5 -417.5
36 DUMMY -14474.5 -417.5 86 AVSS -12524.5 -417.5 136 VSS -10574.5 -417.5
37 DUMMY -14435.5 -417.5 87 AVSS -12485.5 -417.5 137 VSS -10535.5 -417.5
38 DUMMY -14396.5 -417.5 88 AVSS -12446.5 -417.5 138 VSS -10496.5 -417.5
39 VSS -14357.5 -417.5 89 AVSS -12407.5 -417.5 139 VSS -10457.5 -417.5
40 VSS -14318.5 -417.5 90 AVSS -12368.5 -417.5 140 VSS -10418.5 -417.5
41 VDDI -14279.5 -417.5 91 AVDD -12329.5 -417.5 141 VSS -10379.5 -417.5
42 VDDI -14240.5 -417.5 92 AVDD -12290.5 -417.5 142 OTP_PWR -10340.5 -417.5
43 DUMMY -14201.5 -417.5 93 AVDD -12251.5 -417.5 143 OTP_PWR -10301.5 -417.5
44 DUMMY -14162.5 -417.5 94 AVDD -12212.5 -417.5 144 VGHO -10262.5 -417.5
45 DUMMY -14123.5 -417.5 95 AVDD -12173.5 -417.5 145 VGHO -10223.5 -417.5
46 DUMMY -14084.5 -417.5 96 AVDD -12134.5 -417.5 146 VGHO -10184.5 -417.5
47 DUMMY -14045.5 -417.5 97 AVDD -12095.5 -417.5 147 VGHO -10145.5 -417.5
48 DUMMY -14006.5 -417.5 98 VDD5 -12056.5 -417.5 148 VGHO -10106.5 -417.5
49 DUMMY -13967.5 -417.5 99 VDD5 -12017.5 -417.5 149 VGHO -10067.5 -417.5
50 DUMMY -13928.5 -417.5 100 VDD5 -11978.5 -417.5 150 VGHO1 -10028.5 -417.5

Preliminary
FT8006S-AN
151 VGHO1 -9989.5 -417.5 203 C22P -7961.5 -417.5 255 VDDI -5933.5 -417.5
152 VGHO1 -9950.5 -417.5 204 C22N -7922.5 -417.5 256 VDDI -5894.5 -417.5
153 VGHO1 -9911.5 -417.5 205 C22N -7883.5 -417.5 257 VDDI -5855.5 -417.5
154 VGHO1 -9872.5 -417.5 206 C22N -7844.5 -417.5 258 VDDI -5816.5 -417.5
155 VGHO1 -9833.5 -417.5 207 C22N -7805.5 -417.5 259 VDDI -5777.5 -417.5
156 VGHO2 -9794.5 -417.5 208 C22N -7766.5 -417.5 260 VDD -5738.5 -417.5
157 VGHO2 -9755.5 -417.5 209 C22N -7727.5 -417.5 261 VDD -5699.5 -417.5
158 VGHO2 -9716.5 -417.5 210 AVDD -7688.5 -417.5 262 VDD -5660.5 -417.5
159 VGHO2 -9677.5 -417.5 211 AVDD -7649.5 -417.5 263 VDD -5621.5 -417.5
r
Fo
160 VGHO2 -9638.5 -417.5 212 AVDD -7610.5 -417.5 264 VDD -5582.5 -417.5
161 VGHO2 -9599.5 -417.5 213 AVDD -7571.5 -417.5 265 VDD -5543.5 -417.5
162 AVDD -9560.5 -417.5 214 AVDD -7532.5 -417.5 266 VSS -5504.5 -417.5
163 AVDD -9521.5 -417.5 215 VCI1 -7493.5 -417.5 267 VSS -5465.5 -417.5
l
164 AVDD -9482.5 -417.5 216 VCI1 -7454.5 -417.5 268 VSS -5426.5 -417.5
nl tia
165 AVDD -9443.5 -417.5 217 VCI1 -7415.5 -417.5 269 VSS -5387.5 -417.5
166 AVDD -9404.5 -417.5 218 VCI1 -7376.5 -417.5 270 VSS -5348.5 -417.5
O en
167 AVDD -9365.5 -417.5 219 VCI1 -7337.5 -417.5 271 VSS -5309.5 -417.5
168 VGH -9326.5 -417.5 220 VCI1 -7298.5 -417.5 272 DUMMY -5270.5 -417.5
169 VGH -9287.5 -417.5 221 C41P -7259.5 -417.5 273 DUMMY -5231.5 -417.5
se id
170 VGH -9248.5 -417.5 222 C41P -7220.5 -417.5 274 DUMMY -5192.5 -417.5
y
171 VGH -9209.5 -417.5 223 C41P -7181.5 -417.5 275 VDDAM -5153.5 -417.5
U nf
172 VGH -9170.5 -417.5 224 C41P -7142.5 -417.5 276 VDDAM -5114.5 -417.5
173 VGH -9131.5 -417.5 225 C41P -7103.5 -417.5 277 VDDAM -5075.5 -417.5
o
174 C21P -9092.5 -417.5 226 C41P -7064.5 -417.5 278 VDDAM -5036.5 -417.5
175 C21P -9053.5 -417.5 227 C41N -7025.5 -417.5 279 LVDSVDD -4997.5 -417.5
尔 hC
176 C21P -9014.5 -417.5 228 C41N -6986.5 -417.5 280 LVDSVDD -4958.5 -417.5
177 C21P -8975.5 -417.5 229 C41N -6947.5 -417.5 281 LVDSVDD -4919.5 -417.5
178 C21P -8936.5 -417.5 230 C41N -6908.5 -417.5 282 LVDSVSS -4880.5 -417.5
179 C21P -8897.5 -417.5 231 C41N -6869.5 -417.5 283 LVDSVSS -4841.5 -417.5
韦 ec
180 C21N -8858.5 -417.5 232 C41N -6830.5 -417.5 284 LVDSVSS -4802.5 -417.5
181 C21N -8819.5 -417.5 233 AVSS -6791.5 -417.5 285 HSSI_D2_P -4763.5 -417.5
博 lT
182 C21N -8780.5 -417.5 234 AVSS -6752.5 -417.5 286 HSSI_D2_P -4724.5 -417.5
183 C21N -8741.5 -417.5 235 AVSS -6713.5 -417.5 287 HSSI_D2_P -4685.5 -417.5
麦 ca
184 C21N -8702.5 -417.5 236 AVSS -6674.5 -417.5 288 HSSI_D2_P -4646.5 -417.5
185 C21N -8663.5 -417.5 237 AVSS -6635.5 -417.5 289 HSSI_D2_P -4607.5 -417.5
186 AVDD -8624.5 -417.5 238 VSS -6596.5 -417.5 290 HSSI_D2_P -4568.5 -417.5
Fo
187 AVDD -8585.5 -417.5 239 VSS -6557.5 -417.5 291 HSSI_D2_N -4529.5 -417.5
188 AVDD -8546.5 -417.5 240 VSS -6518.5 -417.5 292 HSSI_D2_N -4490.5 -417.5
189 AVDD -8507.5 -417.5 241 VSS -6479.5 -417.5 293 HSSI_D2_N -4451.5 -417.5
190 AVDD -8468.5 -417.5 242 VSS -6440.5 -417.5 294 HSSI_D2_N -4412.5 -417.5
191 AVDD -8429.5 -417.5 243 VSS -6401.5 -417.5 295 HSSI_D2_N -4373.5 -417.5
192 AVEE -8390.5 -417.5 244 VDD -6362.5 -417.5 296 HSSI_D2_N -4334.5 -417.5
193 AVEE -8351.5 -417.5 245 VDD -6323.5 -417.5 297 LVDSVSS -4295.5 -417.5
194 AVEE -8312.5 -417.5 246 VDD -6284.5 -417.5 298 LVDSVSS -4256.5 -417.5
195 AVSS -8273.5 -417.5 247 VDD -6245.5 -417.5 299 HSSI_D1_P -4217.5 -417.5
196 AVSS -8234.5 -417.5 248 VDD -6206.5 -417.5 300 HSSI_D1_P -4178.5 -417.5
197 AVSS -8195.5 -417.5 249 VDD -6167.5 -417.5 301 HSSI_D1_P -4139.5 -417.5
198 C22P -8156.5 -417.5 250 VDDI -6128.5 -417.5 302 HSSI_D1_P -4100.5 -417.5
199 C22P -8117.5 -417.5 251 VDDI -6089.5 -417.5 303 HSSI_D1_P -4061.5 -417.5
200 C22P -8078.5 -417.5 252 VDDI -6050.5 -417.5 304 HSSI_D1_P -4022.5 -417.5
201 C22P -8039.5 -417.5 253 VDDI -6011.5 -417.5 305 HSSI_D1_N -3983.5 -417.5
202 C22P -8000.5 -417.5 254 VDDI -5972.5 -417.5 306 HSSI_D1_N -3944.5 -417.5

Preliminary
FT8006S-AN
307 HSSI_D1_N -3905.5 -417.5 359 VDDAM -1877.5 -417.5 411 LCD_TSPO[3] 150.5 -417.5
311 LVDSVSS -3749.5 -417.5 363 VSS -1721.5 -417.5 415 LCD_TSPO[7] 306.5 -417.5
312 LVDSVSS -3710.5 -417.5 364 VSS -1682.5 -417.5 416 DUMMY[1] 345.5 -417.5
313 HSSI_CLK_P -3671.5 -417.5 365 VSS -1643.5 -417.5 417 DUMMY[1] 384.5 -417.5
r
Fo
316 HSSI_CLK_P -3554.5 -417.5 368 VSS -1526.5 -417.5 420 LCD_TSPI_DEN[0] 501.5 -417.5
317 HSSI_CLK_P -3515.5 -417.5 369 VDD -1487.5 -417.5 421 LCD_TSPI_DEN[1] 540.5 -417.5
318 HSSI_CLK_P -3476.5 -417.5 370 VDD -1448.5 -417.5 422 LCD_TSPI_DEN[2] 579.5 -417.5
319 HSSI_CLK_N -3437.5 -417.5 371 VDD -1409.5 -417.5 423 LCD_TSPI_DEN[3] 618.5 -417.5
l
nl tia
O en
323 HSSI_CLK_N -3281.5 -417.5 375 VDDI -1253.5 -417.5 427 LCD_TSPI_DEN[7] 774.5 -417.5
324 HSSI_CLK_N -3242.5 -417.5 376 VDDI -1214.5 -417.5 428 LCD_TSPI_DEN[8] 813.5 -417.5
325 LVDSVSS -3203.5 -417.5 377 VDDI -1175.5 -417.5 429 LCD_TSPI_DEN[9] 852.5 -417.5
se id
326 LVDSVSS -3164.5 -417.5 378 VDDI -1136.5 -417.5 430 LCD_TSPI_DEN[10] 891.5 -417.5
y
327 HSSI_D0_P -3125.5 -417.5 379 VDDI -1097.5 -417.5 431 LCD_TSPI_DEN[11] 930.5 -417.5
U nf
328 HSSI_D0_P -3086.5 -417.5 380 VDDI -1058.5 -417.5 432 LCD_TSPI_DEN[12] 969.5 -417.5
329 HSSI_D0_P -3047.5 -417.5 381 AVSS -1019.5 -417.5 433 LCD_TSPI_DEN[13] 1008.5 -417.5
o
330 HSSI_D0_P -3008.5 -417.5 382 AVSS -980.5 -417.5 434 LCD_TSPI_DEN[14] 1047.5 -417.5
331 HSSI_D0_P -2969.5 -417.5 383 AVSS -941.5 -417.5 435 VSS 1086.5 -417.5
尔 hC
332 HSSI_D0_P -2930.5 -417.5 384 AVSS -902.5 -417.5 436 VSS 1125.5 -417.5
333 HSSI_D0_N -2891.5 -417.5 385 AVSS -863.5 -417.5 437 VDDI 1164.5 -417.5
334 HSSI_D0_N -2852.5 -417.5 386 AVSS -824.5 -417.5 438 VDDI 1203.5 -417.5
335 HSSI_D0_N -2813.5 -417.5 387 AVDD -785.5 -417.5 439 LCD_GPIO[8] 1242.5 -417.5
韦 ec
336 HSSI_D0_N -2774.5 -417.5 388 AVDD -746.5 -417.5 440 DUMMY[2] 1281.5 -417.5
博 lT
339 LVDSVSS -2657.5 -417.5 391 AVDD -629.5 -417.5 443 DUMMY[2] 1398.5 -417.5
麦 ca
340 LVDSVSS -2618.5 -417.5 392 AVDD -590.5 -417.5 444 DUMMY[2] 1437.5 -417.5
341 HSSI_D3_P -2579.5 -417.5 393 AVEE -551.5 -417.5 445 DUMMY[2] 1476.5 -417.5
342 HSSI_D3_P -2540.5 -417.5 394 AVEE -512.5 -417.5 446 DUMMY[2] 1515.5 -417.5
Fo
343 HSSI_D3_P -2501.5 -417.5 395 AVEE -473.5 -417.5 447 LCD_EXT_OSC 1554.5 -417.5
346 HSSI_D3_P -2384.5 -417.5 398 AVEE -356.5 -417.5 450 LCD_GPIO[0] 1671.5 -417.5
347 HSSI_D3_N -2345.5 -417.5 399 DUMMY[0] -317.5 -417.5 451 LCD_GPIO[0] 1710.5 -417.5
353 LVDSVSS -2111.5 -417.5 405 LCD_TEST[1] -83.5 -417.5 457 LCD_GPIO[3] 1944.5 -417.5
356 LVDSVDD -1994.5 -417.5 408 LCD_TSPO[0] 33.5 -417.5 460 LCD_GPIO[5] 2061.5 -417.5

Preliminary
FT8006S-AN
463 LCD_GPIO[6] 2178.5 -417.5 515 VDD_TP 4206.5 -417.5 567 NGVDD 6234.5 -417.5
464 LCD_GPIO[7] 2217.5 -417.5 516 VDDI 4245.5 -417.5 568 NGVDD 6273.5 -417.5
465 LCD_GPIO[7] 2256.5 -417.5 517 VDDI 4284.5 -417.5 569 NGVDD 6312.5 -417.5
466 BIST_EN 2295.5 -417.5 518 VDDI 4323.5 -417.5 570 DUMMY 6351.5 -417.5
467 DSWAP[0] 2334.5 -417.5 519 VDDI 4362.5 -417.5 571 DUMMY 6390.5 -417.5
468 DSWAP[1] 2373.5 -417.5 520 VDDI 4401.5 -417.5 572 DUMMY 6429.5 -417.5
469 PSWAP 2412.5 -417.5 521 VDDI 4440.5 -417.5 573 VSS 6468.5 -417.5
470 LANSEL[0] 2451.5 -417.5 522 VCOM 4479.5 -417.5 574 VSS 6507.5 -417.5
471 LANSEL[1] 2490.5 -417.5 523 VCOM 4518.5 -417.5 575 VSS 6546.5 -417.5
r
Fo
472 DUMMY[3] 2529.5 -417.5 524 VCOM 4557.5 -417.5 576 VSS 6585.5 -417.5
473 EXT_VCOM_EN 2568.5 -417.5 525 VCOM 4596.5 -417.5 577 VSS 6624.5 -417.5
474 RESX 2607.5 -417.5 526 VCOM 4635.5 -417.5 578 VSS 6663.5 -417.5
475 DUMMY[3] 2646.5 -417.5 527 VCOM 4674.5 -417.5 579 VDDI 6702.5 -417.5
l
476 VDDI 2685.5 -417.5 528 VCOM 4713.5 -417.5 580 VDDI 6741.5 -417.5
nl tia
477 VDDI 2724.5 -417.5 529 AVDD 4752.5 -417.5 581 VDDI 6780.5 -417.5
478 VSS 2763.5 -417.5 530 AVDD 4791.5 -417.5 582 VDDI 6819.5 -417.5
O en
479 VSS 2802.5 -417.5 531 AVDD 4830.5 -417.5 583 VDDI 6858.5 -417.5
480 VDDI 2841.5 -417.5 532 AVDD 4869.5 -417.5 584 VDDI 6897.5 -417.5
481 VDDI 2880.5 -417.5 533 AVDD 4908.5 -417.5 585 VDDI 6936.5 -417.5
se id
482 DUMMY[3] 2919.5 -417.5 534 AVDD 4947.5 -417.5 586 VDDI 6975.5 -417.5
y
483 POR12_T 2958.5 -417.5 535 AVDD 4986.5 -417.5 587 VDDI 7014.5 -417.5
U nf
484 POR18_T 2997.5 -417.5 536 AVSS 5025.5 -417.5 588 VDDI 7053.5 -417.5
485 BOOT_DEVICE 3036.5 -417.5 537 AVSS 5064.5 -417.5 589 VDDI 7092.5 -417.5
o
486 XI_TEST 3075.5 -417.5 538 AVSS 5103.5 -417.5 590 VDDI 7131.5 -417.5
487 CS 3114.5 -417.5 539 AVSS 5142.5 -417.5 591 VCL 7170.5 -417.5
尔 hC
488 SCLK 3153.5 -417.5 540 AVSS 5181.5 -417.5 592 VCL 7209.5 -417.5
489 MOSI 3192.5 -417.5 541 AVSS 5220.5 -417.5 593 VCL 7248.5 -417.5
490 MISO 3231.5 -417.5 542 VREF_TP 5259.5 -417.5 594 VCL 7287.5 -417.5
491 HOLD 3270.5 -417.5 543 VREF_TP 5298.5 -417.5 595 VCL 7326.5 -417.5
韦 ec
492 WP 3309.5 -417.5 544 VREF_TP 5337.5 -417.5 596 VCL 7365.5 -417.5
493 TP_EXT_RSTN 3348.5 -417.5 545 VREF_TP 5376.5 -417.5 597 AVSS 7404.5 -417.5
博 lT
494 TP_GPIO[0] 3387.5 -417.5 546 VREF_TP 5415.5 -417.5 598 AVSS 7443.5 -417.5
麦 ca
497 TP_GPIO[1] 3504.5 -417.5 549 VSSR 5532.5 -417.5 601 AVSS 7560.5 -417.5
498 TP_GPIO[2] 3543.5 -417.5 550 VSSR 5571.5 -417.5 602 AVSS 7599.5 -417.5
Fo
499 TP_GPIO[2] 3582.5 -417.5 551 VSSR 5610.5 -417.5 603 C42P 7638.5 -417.5
500 TP_GPIO[3] 3621.5 -417.5 552 VSSR 5649.5 -417.5 604 C42P 7677.5 -417.5
501 TP_GPIO[3] 3660.5 -417.5 553 VSSR 5688.5 -417.5 605 C42P 7716.5 -417.5
502 TP_GPIO[4] 3699.5 -417.5 554 VSSR 5727.5 -417.5 606 C42P 7755.5 -417.5
503 TP_GPIO[4] 3738.5 -417.5 555 VSSR 5766.5 -417.5 607 C42P 7794.5 -417.5
504 VSS 3777.5 -417.5 556 VSSR 5805.5 -417.5 608 C42P 7833.5 -417.5
505 VSS 3816.5 -417.5 557 VSSR 5844.5 -417.5 609 C42N 7872.5 -417.5
506 VSS 3855.5 -417.5 558 VSSR 5883.5 -417.5 610 C42N 7911.5 -417.5
507 VSS 3894.5 -417.5 559 VREF 5922.5 -417.5 611 C42N 7950.5 -417.5
508 VSS 3933.5 -417.5 560 VREF 5961.5 -417.5 612 C42N 7989.5 -417.5
509 VSS 3972.5 -417.5 561 VREF 6000.5 -417.5 613 C42N 8028.5 -417.5
510 VDD_TP 4011.5 -417.5 562 VREF 6039.5 -417.5 614 C42N 8067.5 -417.5
511 VDD_TP 4050.5 -417.5 563 VREF 6078.5 -417.5 615 AVEE 8106.5 -417.5
512 VDD_TP 4089.5 -417.5 564 GVDD 6117.5 -417.5 616 AVEE 8145.5 -417.5
513 VDD_TP 4128.5 -417.5 565 GVDD 6156.5 -417.5 617 AVEE 8184.5 -417.5
514 VDD_TP 4167.5 -417.5 566 GVDD 6195.5 -417.5 618 AVEE 8223.5 -417.5

Preliminary
FT8006S-AN
619 AVEE 8262.5 -417.5 671 AVSS 10290.5 -417.5 723 AVDD 12318.5 -417.5
620 AVEE 8301.5 -417.5 672 AVSS 10329.5 -417.5 724 AVSS 12357.5 -417.5
621 AVEE 8340.5 -417.5 673 AVSS 10368.5 -417.5 725 AVSS 12396.5 -417.5
622 AVEE 8379.5 -417.5 674 AVSS 10407.5 -417.5 726 AVSS 12435.5 -417.5
623 AVSS 8418.5 -417.5 675 AVSS 10446.5 -417.5 727 AVSS 12474.5 -417.5
624 AVSS 8457.5 -417.5 676 AVEE 10485.5 -417.5 728 AVSS 12513.5 -417.5
625 AVSS 8496.5 -417.5 677 AVEE 10524.5 -417.5 729 AVSS 12552.5 -417.5
626 AVDD 8535.5 -417.5 678 AVEE 10563.5 -417.5 730 AVSS 12591.5 -417.5
627 AVDD 8574.5 -417.5 679 AVEE 10602.5 -417.5 731 AVSS 12630.5 -417.5
r
Fo
628 AVDD 8613.5 -417.5 680 AVEE 10641.5 -417.5 732 AVSS 12669.5 -417.5
629 C31P 8652.5 -417.5 681 AVEE 10680.5 -417.5 733 AVSS 12708.5 -417.5
630 C31P 8691.5 -417.5 682 VCOM_OPT_R 10719.5 -417.5 734 AVSS 12747.5 -417.5
631 C31P 8730.5 -417.5 683 VCOM_OPT_R 10758.5 -417.5 735 AVSS 12786.5 -417.5
l
632 C31P 8769.5 -417.5 684 VCOM_OPT_R 10797.5 -417.5 736 AVSS 12825.5 -417.5
nl tia
633 C31P 8808.5 -417.5 685 VCOM_OPT_R 10836.5 -417.5 737 AVSS 12864.5 -417.5
634 C31P 8847.5 -417.5 686 VCOM_OPT_R 10875.5 -417.5 738 AVSS 12903.5 -417.5
O en
635 C31N 8886.5 -417.5 687 VCOM_OPT_R 10914.5 -417.5 739 VGH1_R 12942.5 -417.5
636 C31N 8925.5 -417.5 688 VCOM_OPT_R 10953.5 -417.5 740 VGH1_R 12981.5 -417.5
637 C31N 8964.5 -417.5 689 VCOM_OPT_R 10992.5 -417.5 741 VGH1_R 13020.5 -417.5
se id
638 C31N 9003.5 -417.5 690 VCOM 11031.5 -417.5 742 VGH2_R 13059.5 -417.5
y
639 C31N 9042.5 -417.5 691 VCOM 11070.5 -417.5 743 VGHO_R 13098.5 -417.5
U nf
640 C31N 9081.5 -417.5 692 VCOM 11109.5 -417.5 744 VGHO_R 13137.5 -417.5
641 VGL 9120.5 -417.5 693 VCOM 11148.5 -417.5 745 VGHO_R 13176.5 -417.5
o
642 VGL 9159.5 -417.5 694 VCOM 11187.5 -417.5 746 DCHG1_R 13215.5 -417.5
643 VGL 9198.5 -417.5 695 VCOM 11226.5 -417.5 747 DCHG2_R 13254.5 -417.5
尔 hC
644 VGL 9237.5 -417.5 696 VCOM 11265.5 -417.5 748 SYNC_DAT_R[6] 13293.5 -417.5
647 VGLO2 9354.5 -417.5 699 VCOM_PASS_R 11382.5 -417.5 751 SYNC_DAT_R[5] 13410.5 -417.5
韦 ec
博 lT
651 VGLO2 9510.5 -417.5 703 VSS 11538.5 -417.5 755 SYNC_DAT_R[3] 13566.5 -417.5
麦 ca
654 VGLO1 9627.5 -417.5 706 VDD_TP 11655.5 -417.5 758 SYNC_DAT_R[1] 13683.5 -417.5
Fo
657 VGLO1 9744.5 -417.5 709 VREF_TP 11772.5 -417.5 761 SYNC_DAT_R[0] 13800.5 -417.5
658 VGLO1 9783.5 -417.5 710 VREF_TP 11811.5 -417.5 762 DUMMY 13839.5 -417.5
659 VGLO 9822.5 -417.5 711 VREF_TP 11850.5 -417.5 763 DUMMY 13878.5 -417.5
662 VGLO 9939.5 -417.5 714 VDD5 11967.5 -417.5 766 DUMMY 13995.5 -417.5
663 VGLO 9978.5 -417.5 715 VDD5 12006.5 -417.5 767 DUMMY 14034.5 -417.5
664 VGLO 10017.5 -417.5 716 VDD5 12045.5 -417.5 768 DUMMY 14073.5 -417.5
665 AFE_TEST[0] 10056.5 -417.5 717 AVDD 12084.5 -417.5 769 DUMMY 14112.5 -417.5
668 AFE_TEST[3] 10173.5 -417.5 720 AVDD 12201.5 -417.5 772 VDDI 14229.5 -417.5
669 AFE_TEST[4] 10212.5 -417.5 721 AVDD 12240.5 -417.5 773 VDDI 14268.5 -417.5
670 AVSS 10251.5 -417.5 722 AVDD 12279.5 -417.5 774 VSS 14307.5 -417.5

Preliminary
FT8006S-AN
775 VSS 14346.5 -417.5 827 VCOM_PASS_R 15757.65 294.5 879 S[30] 15253.25 294.5
776 DUMMY 14385.5 -417.5 828 DUMMY 15747.95 414.5 880 SX[571] 15243.55 414.5
777 DUMMY 14424.5 -417.5 829 VCOM_PASS_R 15738.25 54.5 881 S[31] 15233.85 54.5
780 DUMMY 14541.5 -417.5 832 DUMMY 15709.15 414.5 884 SX[570] 15204.75 414.5
781 DUMMY 14580.5 -417.5 833 DUMMY 15699.45 54.5 885 S[34] 15195.05 54.5
782 DUMMY 14619.5 -417.5 834 DUMMY 15689.75 174.5 886 S[35] 15185.35 174.5
783 DUMMY 14658.5 -417.5 835 DUMMY 15680.05 294.5 887 S[36] 15175.65 294.5
r
Fo
784 DUMMY 14697.5 -417.5 836 DUMMY 15670.35 414.5 888 SX[569] 15165.95 414.5
785 DUMMY 14736.5 -417.5 837 DUMMY 15660.65 54.5 889 S[37] 15156.25 54.5
786 DUMMY 14775.5 -417.5 838 SDUM[0] 15650.95 174.5 890 S[38] 15146.55 174.5
787 DUMMY 14814.5 -417.5 839 SDUM[1] 15641.25 294.5 891 S[39] 15136.85 294.5
l
788 DUMMY 14853.5 -417.5 840 SXDUM[1] 15631.55 414.5 892 SX[568] 15127.15 414.5
nl tia
789 DUMMY 14892.5 -417.5 841 S[1] 15621.85 54.5 893 S[40] 15117.45 54.5
790 DUMMY 14931.5 -417.5 842 S[2] 15612.15 174.5 894 S[41] 15107.75 174.5
O en
791 DUMMY 14970.5 -417.5 843 S[3] 15602.45 294.5 895 S[42] 15098.05 294.5
792 GOUT_R[22] 15009.5 -417.5 844 DUMMY 15592.75 414.5 896 SX[567] 15088.35 414.5
793 GOUT_R[21] 15048.5 -417.5 845 S[4] 15583.05 54.5 897 S[43] 15078.65 54.5
se id
794 GOUT_R[20] 15087.5 -417.5 846 S[5] 15573.35 174.5 898 S[44] 15068.95 174.5
y
795 GOUT_R[19] 15126.5 -417.5 847 S[6] 15563.65 294.5 899 S[45] 15059.25 294.5
U nf
796 GOUT_R[18] 15165.5 -417.5 848 DUMMY 15553.95 414.5 900 SX[566] 15049.55 414.5
797 GOUT_R[17] 15204.5 -417.5 849 S[7] 15544.25 54.5 901 S[46] 15039.85 54.5
o
798 GOUT_R[16] 15243.5 -417.5 850 S[8] 15534.55 174.5 902 S[47] 15030.15 174.5
799 GOUT_R[15] 15282.5 -417.5 851 S[9] 15524.85 294.5 903 S[48] 15020.45 294.5
尔 hC
800 GOUT_R[14] 15321.5 -417.5 852 DUMMY 15515.15 414.5 904 SX[565] 15010.75 414.5
801 GOUT_R[13] 15360.5 -417.5 853 S[10] 15505.45 54.5 905 S[49] 15001.05 54.5
802 GOUT_R[12] 15399.5 -417.5 854 S[11] 15495.75 174.5 906 S[50] 14991.35 174.5
803 GOUT_R[11] 15438.5 -417.5 855 S[12] 15486.05 294.5 907 S[51] 14981.65 294.5
韦 ec
804 GOUT_R[10] 15477.5 -417.5 856 DUMMY 15476.35 414.5 908 SX[564] 14971.95 414.5
805 GOUT_R[9] 15516.5 -417.5 857 S[13] 15466.65 54.5 909 S[52] 14962.25 54.5
博 lT
806 GOUT_R[8] 15555.5 -417.5 858 S[14] 15456.95 174.5 910 S[53] 14952.55 174.5
807 GOUT_R[7] 15594.5 -417.5 859 S[15] 15447.25 294.5 911 S[54] 14942.85 294.5
麦 ca
808 GOUT_R[6] 15633.5 -417.5 860 SX[576] 15437.55 414.5 912 SX[563] 14933.15 414.5
809 GOUT_R[5] 15672.5 -417.5 861 S[16] 15427.85 54.5 913 S[55] 14923.45 54.5
810 GOUT_R[4] 15711.5 -417.5 862 S[17] 15418.15 174.5 914 S[56] 14913.75 174.5
Fo
811 GOUT_R[3] 15750.5 -417.5 863 S[18] 15408.45 294.5 915 S[57] 14904.05 294.5
812 GOUT_R[2] 15789.5 -417.5 864 SX[575] 15398.75 414.5 916 SX[562] 14894.35 414.5
813 GOUT_R[1] 15828.5 -417.5 865 S[19] 15389.05 54.5 917 S[58] 14884.65 54.5
814 DUMMY 15893.45 54.5 866 S[20] 15379.35 174.5 918 S[59] 14874.95 174.5
815 DUMMY 15883.75 174.5 867 S[21] 15369.65 294.5 919 S[60] 14865.25 294.5
816 DUMMY 15874.05 294.5 868 SX[574] 15359.95 414.5 920 SX[561] 14855.55 414.5
817 DUMMY 15854.65 54.5 869 S[22] 15350.25 54.5 921 S[61] 14845.85 54.5
818 DUMMY 15844.95 174.5 870 S[23] 15340.55 174.5 922 S[62] 14836.15 174.5
819 DUMMY 15835.25 294.5 871 S[24] 15330.85 294.5 923 S[63] 14826.45 294.5
820 DUMMY 15825.55 414.5 872 SX[573] 15321.15 414.5 924 SX[560] 14816.75 414.5
821 DUMMY 15815.85 54.5 873 S[25] 15311.45 54.5 925 S[64] 14807.05 54.5
822 DUMMY 15806.15 174.5 874 S[26] 15301.75 174.5 926 S[65] 14797.35 174.5
823 DUMMY 15796.45 294.5 875 S[27] 15292.05 294.5 927 S[66] 14787.65 294.5
824 DUMMY 15786.75 414.5 876 SX[572] 15282.35 414.5 928 SX[559] 14777.95 414.5
825 VCOM_PASS_R 15777.05 54.5 877 S[28] 15272.65 54.5 929 S[67] 14768.25 54.5
826 VCOM_PASS_R 15767.35 174.5 878 S[29] 15262.95 174.5 930 S[68] 14758.55 174.5

Preliminary
FT8006S-AN
931 S[69] 14748.85 294.5 983 S[108] 14244.45 294.5 1035 S[147] 13740.05 294.5
932 SX[558] 14739.15 414.5 984 SX[545] 14234.75 414.5 1036 SX[539] 13730.35 414.5
933 S[70] 14729.45 54.5 985 S[109] 14225.05 54.5 1037 S[148] 13720.65 54.5
934 S[71] 14719.75 174.5 986 S[110] 14215.35 174.5 1038 S[149] 13710.95 174.5
935 S[72] 14710.05 294.5 987 S[111] 14205.65 294.5 1039 S[150] 13701.25 294.5
936 SX[557] 14700.35 414.5 988 DUMMY 14195.95 414.5 1040 SX[538] 13691.55 414.5
937 S[73] 14690.65 54.5 989 S[112] 14186.25 54.5 1041 S[151] 13681.85 54.5
938 S[74] 14680.95 174.5 990 S[113] 14176.55 174.5 1042 S[152] 13672.15 174.5
939 S[75] 14671.25 294.5 991 S[114] 14166.85 294.5 1043 S[153] 13662.45 294.5
r
Fo
940 SX[556] 14661.55 414.5 992 DUMMY 14157.15 414.5 1044 SX[537] 13652.75 414.5
941 S[76] 14651.85 54.5 993 S[115] 14147.45 54.5 1045 S[154] 13643.05 54.5
942 S[77] 14642.15 174.5 994 S[116] 14137.75 174.5 1046 S[155] 13633.35 174.5
943 S[78] 14632.45 294.5 995 S[117] 14128.05 294.5 1047 S[156] 13623.65 294.5
l
944 SX[555] 14622.75 414.5 996 DUMMY 14118.35 414.5 1048 SX[536] 13613.95 414.5
nl tia
945 S[79] 14613.05 54.5 997 S[118] 14108.65 54.5 1049 S[157] 13604.25 54.5
946 S[80] 14603.35 174.5 998 S[119] 14098.95 174.5 1050 S[158] 13594.55 174.5
O en
947 S[81] 14593.65 294.5 999 S[120] 14089.25 294.5 1051 S[159] 13584.85 294.5
948 SX[554] 14583.95 414.5 1000 DUMMY 14079.55 414.5 1052 SX[535] 13575.15 414.5
949 S[82] 14574.25 54.5 1001 S[121] 14069.85 54.5 1053 S[160] 13565.45 54.5
se id
950 S[83] 14564.55 174.5 1002 S[122] 14060.15 174.5 1054 S[161] 13555.75 174.5
y
951 S[84] 14554.85 294.5 1003 S[123] 14050.45 294.5 1055 S[162] 13546.05 294.5
U nf
952 SX[553] 14545.15 414.5 1004 DUMMY 14040.75 414.5 1056 SX[534] 13536.35 414.5
953 S[85] 14535.45 54.5 1005 S[124] 14031.05 54.5 1057 S[163] 13526.65 54.5
o
954 S[86] 14525.75 174.5 1006 S[125] 14021.35 174.5 1058 S[164] 13516.95 174.5
955 S[87] 14516.05 294.5 1007 S[126] 14011.65 294.5 1059 S[165] 13507.25 294.5
尔 hC
956 SX[552] 14506.35 414.5 1008 DUMMY 14001.95 414.5 1060 SX[533] 13497.55 414.5
957 S[88] 14496.65 54.5 1009 S[127] 13992.25 54.5 1061 S[166] 13487.85 54.5
958 S[89] 14486.95 174.5 1010 S[128] 13982.55 174.5 1062 S[167] 13478.15 174.5
959 S[90] 14477.25 294.5 1011 S[129] 13972.85 294.5 1063 S[168] 13468.45 294.5
韦 ec
960 SX[551] 14467.55 414.5 1012 DUMMY 13963.15 414.5 1064 SX[532] 13458.75 414.5
961 S[91] 14457.85 54.5 1013 S[130] 13953.45 54.5 1065 S[169] 13449.05 54.5
博 lT
962 S[92] 14448.15 174.5 1014 S[131] 13943.75 174.5 1066 S[170] 13439.35 174.5
963 S[93] 14438.45 294.5 1015 S[132] 13934.05 294.5 1067 S[171] 13429.65 294.5
麦 ca
964 SX[550] 14428.75 414.5 1016 SX[544] 13924.35 414.5 1068 SX[531] 13419.95 414.5
965 S[94] 14419.05 54.5 1017 S[133] 13914.65 54.5 1069 S[172] 13410.25 54.5
966 S[95] 14409.35 174.5 1018 S[134] 13904.95 174.5 1070 S[173] 13400.55 174.5
Fo
967 S[96] 14399.65 294.5 1019 S[135] 13895.25 294.5 1071 S[174] 13390.85 294.5
968 SX[549] 14389.95 414.5 1020 SX[543] 13885.55 414.5 1072 SX[530] 13381.15 414.5
969 S[97] 14380.25 54.5 1021 S[136] 13875.85 54.5 1073 S[175] 13371.45 54.5
970 S[98] 14370.55 174.5 1022 S[137] 13866.15 174.5 1074 S[176] 13361.75 174.5
971 S[99] 14360.85 294.5 1023 S[138] 13856.45 294.5 1075 S[177] 13352.05 294.5
972 SX[548] 14351.15 414.5 1024 SX[542] 13846.75 414.5 1076 SX[529] 13342.35 414.5
973 S[100] 14341.45 54.5 1025 S[139] 13837.05 54.5 1077 S[178] 13332.65 54.5
974 S[101] 14331.75 174.5 1026 S[140] 13827.35 174.5 1078 S[179] 13322.95 174.5
975 S[102] 14322.05 294.5 1027 S[141] 13817.65 294.5 1079 S[180] 13313.25 294.5
976 SX[547] 14312.35 414.5 1028 SX[541] 13807.95 414.5 1080 SX[528] 13303.55 414.5
977 S[103] 14302.65 54.5 1029 S[142] 13798.25 54.5 1081 S[181] 13293.85 54.5
978 S[104] 14292.95 174.5 1030 S[143] 13788.55 174.5 1082 S[182] 13284.15 174.5
979 S[105] 14283.25 294.5 1031 S[144] 13778.85 294.5 1083 S[183] 13274.45 294.5
980 SX[546] 14273.55 414.5 1032 SX[540] 13769.15 414.5 1084 SX[527] 13264.75 414.5
981 S[106] 14263.85 54.5 1033 S[145] 13759.45 54.5 1085 S[184] 13255.05 54.5
982 S[107] 14254.15 174.5 1034 S[146] 13749.75 174.5 1086 S[185] 13245.35 174.5

Preliminary
FT8006S-AN
1087 S[186] 13235.65 294.5 1139 S[225] 12731.25 294.5 1191 S[264] 12226.85 294.5
1088 SX[526] 13225.95 414.5 1140 SX[513] 12721.55 414.5 1192 SX[507] 12217.15 414.5
1089 S[187] 13216.25 54.5 1141 S[226] 12711.85 54.5 1193 S[265] 12207.45 54.5
1090 S[188] 13206.55 174.5 1142 S[227] 12702.15 174.5 1194 S[266] 12197.75 174.5
1091 S[189] 13196.85 294.5 1143 S[228] 12692.45 294.5 1195 S[267] 12188.05 294.5
1092 SX[525] 13187.15 414.5 1144 DUMMY 12682.75 414.5 1196 SX[506] 12178.35 414.5
1093 S[190] 13177.45 54.5 1145 S[229] 12673.05 54.5 1197 S[268] 12168.65 54.5
1094 S[191] 13167.75 174.5 1146 S[230] 12663.35 174.5 1198 S[269] 12158.95 174.5
1095 S[192] 13158.05 294.5 1147 S[231] 12653.65 294.5 1199 S[270] 12149.25 294.5
r
Fo
1096 SX[524] 13148.35 414.5 1148 DUMMY 12643.95 414.5 1200 SX[505] 12139.55 414.5
1097 S[193] 13138.65 54.5 1149 S[232] 12634.25 54.5 1201 S[271] 12129.85 54.5
1098 S[194] 13128.95 174.5 1150 S[233] 12624.55 174.5 1202 S[272] 12120.15 174.5
1099 S[195] 13119.25 294.5 1151 S[234] 12614.85 294.5 1203 S[273] 12110.45 294.5
l
1100 SX[523] 13109.55 414.5 1152 DUMMY 12605.15 414.5 1204 SX[504] 12100.75 414.5
nl tia
1101 S[196] 13099.85 54.5 1153 S[235] 12595.45 54.5 1205 S[274] 12091.05 54.5
1102 S[197] 13090.15 174.5 1154 S[236] 12585.75 174.5 1206 S[275] 12081.35 174.5
O en
1103 S[198] 13080.45 294.5 1155 S[237] 12576.05 294.5 1207 S[276] 12071.65 294.5
1104 SX[522] 13070.75 414.5 1156 DUMMY 12566.35 414.5 1208 SX[503] 12061.95 414.5
1105 S[199] 13061.05 54.5 1157 S[238] 12556.65 54.5 1209 S[277] 12052.25 54.5
se id
1106 S[200] 13051.35 174.5 1158 S[239] 12546.95 174.5 1210 S[278] 12042.55 174.5
y
1107 S[201] 13041.65 294.5 1159 S[240] 12537.25 294.5 1211 S[279] 12032.85 294.5
U nf
1108 SX[521] 13031.95 414.5 1160 DUMMY 12527.55 414.5 1212 SX[502] 12023.15 414.5
1109 S[202] 13022.25 54.5 1161 S[241] 12517.85 54.5 1213 S[280] 12013.45 54.5
o
1110 S[203] 13012.55 174.5 1162 S[242] 12508.15 174.5 1214 S[281] 12003.75 174.5
1111 S[204] 13002.85 294.5 1163 S[243] 12498.45 294.5 1215 S[282] 11994.05 294.5
尔 hC
1112 SX[520] 12993.15 414.5 1164 DUMMY 12488.75 414.5 1216 SX[501] 11984.35 414.5
1113 S[205] 12983.45 54.5 1165 S[244] 12479.05 54.5 1217 S[283] 11974.65 54.5
1114 S[206] 12973.75 174.5 1166 S[245] 12469.35 174.5 1218 S[284] 11964.95 174.5
1115 S[207] 12964.05 294.5 1167 S[246] 12459.65 294.5 1219 S[285] 11955.25 294.5
韦 ec
1116 SX[519] 12954.35 414.5 1168 DUMMY 12449.95 414.5 1220 SX[500] 11945.55 414.5
1117 S[208] 12944.65 54.5 1169 S[247] 12440.25 54.5 1221 S[286] 11935.85 54.5
博 lT
1118 S[209] 12934.95 174.5 1170 S[248] 12430.55 174.5 1222 S[287] 11926.15 174.5
1119 S[210] 12925.25 294.5 1171 S[249] 12420.85 294.5 1223 S[288] 11916.45 294.5
麦 ca
1120 SX[518] 12915.55 414.5 1172 SX[512] 12411.15 414.5 1224 SX[499] 11906.75 414.5
1121 S[211] 12905.85 54.5 1173 S[250] 12401.45 54.5 1225 S[289] 11897.05 54.5
1122 S[212] 12896.15 174.5 1174 S[251] 12391.75 174.5 1226 S[290] 11887.35 174.5
Fo
1123 S[213] 12886.45 294.5 1175 S[252] 12382.05 294.5 1227 S[291] 11877.65 294.5
1124 SX[517] 12876.75 414.5 1176 SX[511] 12372.35 414.5 1228 SX[498] 11867.95 414.5
1125 S[214] 12867.05 54.5 1177 S[253] 12362.65 54.5 1229 S[292] 11858.25 54.5
1126 S[215] 12857.35 174.5 1178 S[254] 12352.95 174.5 1230 S[293] 11848.55 174.5
1127 S[216] 12847.65 294.5 1179 S[255] 12343.25 294.5 1231 S[294] 11838.85 294.5
1128 SX[516] 12837.95 414.5 1180 SX[510] 12333.55 414.5 1232 SX[497] 11829.15 414.5
1129 S[217] 12828.25 54.5 1181 S[256] 12323.85 54.5 1233 S[295] 11819.45 54.5
1130 S[218] 12818.55 174.5 1182 S[257] 12314.15 174.5 1234 S[296] 11809.75 174.5
1131 S[219] 12808.85 294.5 1183 S[258] 12304.45 294.5 1235 S[297] 11800.05 294.5
1132 SX[515] 12799.15 414.5 1184 SX[509] 12294.75 414.5 1236 SX[496] 11790.35 414.5
1133 S[220] 12789.45 54.5 1185 S[259] 12285.05 54.5 1237 S[298] 11780.65 54.5
1134 S[221] 12779.75 174.5 1186 S[260] 12275.35 174.5 1238 S[299] 11770.95 174.5
1135 S[222] 12770.05 294.5 1187 S[261] 12265.65 294.5 1239 S[300] 11761.25 294.5
1136 SX[514] 12760.35 414.5 1188 SX[508] 12255.95 414.5 1240 SX[495] 11751.55 414.5
1137 S[223] 12750.65 54.5 1189 S[262] 12246.25 54.5 1241 S[301] 11741.85 54.5
1138 S[224] 12740.95 174.5 1190 S[263] 12236.55 174.5 1242 S[302] 11732.15 174.5

Preliminary
FT8006S-AN
1243 S[303] 11722.45 294.5 1295 S[342] 11218.05 294.5 1347 S[381] 10713.65 294.5
1244 SX[494] 11712.75 414.5 1296 SX[481] 11208.35 414.5 1348 SX[478] 10703.95 414.5
1245 S[304] 11703.05 54.5 1297 S[343] 11198.65 54.5 1349 S[382] 10694.25 54.5
1246 S[305] 11693.35 174.5 1298 S[344] 11188.95 174.5 1350 S[383] 10684.55 174.5
1247 S[306] 11683.65 294.5 1299 S[345] 11179.25 294.5 1351 S[384] 10674.85 294.5
1248 SX[493] 11673.95 414.5 1300 DUMMY 11169.55 414.5 1352 SX[477] 10665.15 414.5
1249 S[307] 11664.25 54.5 1301 S[346] 11159.85 54.5 1353 S[385] 10655.45 54.5
1250 S[308] 11654.55 174.5 1302 S[347] 11150.15 174.5 1354 S[386] 10645.75 174.5
1251 S[309] 11644.85 294.5 1303 S[348] 11140.45 294.5 1355 S[387] 10636.05 294.5
r
Fo
1252 SX[492] 11635.15 414.5 1304 DUMMY 11130.75 414.5 1356 SX[476] 10626.35 414.5
1253 S[310] 11625.45 54.5 1305 S[349] 11121.05 54.5 1357 S[388] 10616.65 54.5
1254 S[311] 11615.75 174.5 1306 S[350] 11111.35 174.5 1358 S[389] 10606.95 174.5
1255 S[312] 11606.05 294.5 1307 S[351] 11101.65 294.5 1359 S[390] 10597.25 294.5
l
1256 SX[491] 11596.35 414.5 1308 DUMMY 11091.95 414.5 1360 SX[475] 10587.55 414.5
nl tia
1257 S[313] 11586.65 54.5 1309 S[352] 11082.25 54.5 1361 S[391] 10577.85 54.5
1258 S[314] 11576.95 174.5 1310 S[353] 11072.55 174.5 1362 S[392] 10568.15 174.5
O en
1259 S[315] 11567.25 294.5 1311 S[354] 11062.85 294.5 1363 S[393] 10558.45 294.5
1260 SX[490] 11557.55 414.5 1312 DUMMY 11053.15 414.5 1364 SX[474] 10548.75 414.5
1261 S[316] 11547.85 54.5 1313 S[355] 11043.45 54.5 1365 S[394] 10539.05 54.5
se id
1262 S[317] 11538.15 174.5 1314 S[356] 11033.75 174.5 1366 S[395] 10529.35 174.5
y
1263 S[318] 11528.45 294.5 1315 S[357] 11024.05 294.5 1367 S[396] 10519.65 294.5
U nf
1264 SX[489] 11518.75 414.5 1316 DUMMY 11014.35 414.5 1368 SX[473] 10509.95 414.5
1265 S[319] 11509.05 54.5 1317 S[358] 11004.65 54.5 1369 S[397] 10500.25 54.5
o
1266 S[320] 11499.35 174.5 1318 S[359] 10994.95 174.5 1370 S[398] 10490.55 174.5
1267 S[321] 11489.65 294.5 1319 S[360] 10985.25 294.5 1371 S[399] 10480.85 294.5
尔 hC
1268 SX[488] 11479.95 414.5 1320 DUMMY 10975.55 414.5 1372 SX[472] 10471.15 414.5
1269 S[322] 11470.25 54.5 1321 S[361] 10965.85 54.5 1373 S[400] 10461.45 54.5
1270 S[323] 11460.55 174.5 1322 S[362] 10956.15 174.5 1374 S[401] 10451.75 174.5
1271 S[324] 11450.85 294.5 1323 S[363] 10946.45 294.5 1375 S[402] 10442.05 294.5
韦 ec
1272 SX[487] 11441.15 414.5 1324 DUMMY 10936.75 414.5 1376 SX[471] 10432.35 414.5
1273 S[325] 11431.45 54.5 1325 S[364] 10927.05 54.5 1377 S[403] 10422.65 54.5
博 lT
1274 S[326] 11421.75 174.5 1326 S[365] 10917.35 174.5 1378 S[404] 10412.95 174.5
1275 S[327] 11412.05 294.5 1327 S[366] 10907.65 294.5 1379 S[405] 10403.25 294.5
麦 ca
1276 SX[486] 11402.35 414.5 1328 DUMMY 10897.95 414.5 1380 SX[470] 10393.55 414.5
1277 S[328] 11392.65 54.5 1329 S[367] 10888.25 54.5 1381 S[406] 10383.85 54.5
1278 S[329] 11382.95 174.5 1330 S[368] 10878.55 174.5 1382 S[407] 10374.15 174.5
Fo
1279 S[330] 11373.25 294.5 1331 S[369] 10868.85 294.5 1383 S[408] 10364.45 294.5
1280 SX[485] 11363.55 414.5 1332 DUMMY 10859.15 414.5 1384 SX[469] 10354.75 414.5
1281 S[331] 11353.85 54.5 1333 S[370] 10849.45 54.5 1385 S[409] 10345.05 54.5
1282 S[332] 11344.15 174.5 1334 S[371] 10839.75 174.5 1386 S[410] 10335.35 174.5
1283 S[333] 11334.45 294.5 1335 S[372] 10830.05 294.5 1387 S[411] 10325.65 294.5
1284 SX[484] 11324.75 414.5 1336 DUMMY 10820.35 414.5 1388 SX[468] 10315.95 414.5
1285 S[334] 11315.05 54.5 1337 S[373] 10810.65 54.5 1389 S[412] 10306.25 54.5
1286 S[335] 11305.35 174.5 1338 S[374] 10800.95 174.5 1390 S[413] 10296.55 174.5
1287 S[336] 11295.65 294.5 1339 S[375] 10791.25 294.5 1391 S[414] 10286.85 294.5
1288 SX[483] 11285.95 414.5 1340 SX[480] 10781.55 414.5 1392 SX[467] 10277.15 414.5
1289 S[337] 11276.25 54.5 1341 S[376] 10771.85 54.5 1393 S[415] 10267.45 54.5
1290 S[338] 11266.55 174.5 1342 S[377] 10762.15 174.5 1394 S[416] 10257.75 174.5
1291 S[339] 11256.85 294.5 1343 S[378] 10752.45 294.5 1395 S[417] 10248.05 294.5
1292 SX[482] 11247.15 414.5 1344 SX[479] 10742.75 414.5 1396 SX[466] 10238.35 414.5
1293 S[340] 11237.45 54.5 1345 S[379] 10733.05 54.5 1397 S[418] 10228.65 54.5
1294 S[341] 11227.75 174.5 1346 S[380] 10723.35 174.5 1398 S[419] 10218.95 174.5

Preliminary
FT8006S-AN
1399 S[420] 10209.25 294.5 1451 S[459] 9704.85 294.5 1503 S[498] 9200.45 294.5
1400 SX[465] 10199.55 414.5 1452 SX[452] 9695.15 414.5 1504 SX[446] 9190.75 414.5
1401 S[421] 10189.85 54.5 1453 S[460] 9685.45 54.5 1505 S[499] 9181.05 54.5
1402 S[422] 10180.15 174.5 1454 S[461] 9675.75 174.5 1506 S[500] 9171.35 174.5
1403 S[423] 10170.45 294.5 1455 S[462] 9666.05 294.5 1507 S[501] 9161.65 294.5
1404 SX[464] 10160.75 414.5 1456 SX[451] 9656.35 414.5 1508 SX[445] 9151.95 414.5
1405 S[424] 10151.05 54.5 1457 S[463] 9646.65 54.5 1509 S[502] 9142.25 54.5
1406 S[425] 10141.35 174.5 1458 S[464] 9636.95 174.5 1510 S[503] 9132.55 174.5
1407 S[426] 10131.65 294.5 1459 S[465] 9627.25 294.5 1511 S[504] 9122.85 294.5
r
Fo
1408 SX[463] 10121.95 414.5 1460 SX[450] 9617.55 414.5 1512 SX[444] 9113.15 414.5
1409 S[427] 10112.25 54.5 1461 S[466] 9607.85 54.5 1513 S[505] 9103.45 54.5
1410 S[428] 10102.55 174.5 1462 S[467] 9598.15 174.5 1514 S[506] 9093.75 174.5
1411 S[429] 10092.85 294.5 1463 S[468] 9588.45 294.5 1515 S[507] 9084.05 294.5
l
1412 SX[462] 10083.15 414.5 1464 SX[449] 9578.75 414.5 1516 SX[443] 9074.35 414.5
nl tia
1413 S[430] 10073.45 54.5 1465 S[469] 9569.05 54.5 1517 S[508] 9064.65 54.5
1414 S[431] 10063.75 174.5 1466 S[470] 9559.35 174.5 1518 S[509] 9054.95 174.5
O en
1415 S[432] 10054.05 294.5 1467 S[471] 9549.65 294.5 1519 S[510] 9045.25 294.5
1416 SX[461] 10044.35 414.5 1468 DUMMY 9539.95 414.5 1520 SX[442] 9035.55 414.5
1417 S[433] 10034.65 54.5 1469 S[472] 9530.25 54.5 1521 S[511] 9025.85 54.5
se id
1418 S[434] 10024.95 174.5 1470 S[473] 9520.55 174.5 1522 S[512] 9016.15 174.5
y
1419 S[435] 10015.25 294.5 1471 S[474] 9510.85 294.5 1523 S[513] 9006.45 294.5
U nf
1420 SX[460] 10005.55 414.5 1472 DUMMY 9501.15 414.5 1524 SX[441] 8996.75 414.5
1421 S[436] 9995.85 54.5 1473 S[475] 9491.45 54.5 1525 S[514] 8987.05 54.5
o
1422 S[437] 9986.15 174.5 1474 S[476] 9481.75 174.5 1526 S[515] 8977.35 174.5
1423 S[438] 9976.45 294.5 1475 S[477] 9472.05 294.5 1527 S[516] 8967.65 294.5
尔 hC
1424 SX[459] 9966.75 414.5 1476 DUMMY 9462.35 414.5 1528 SX[440] 8957.95 414.5
1425 S[439] 9957.05 54.5 1477 S[478] 9452.65 54.5 1529 S[517] 8948.25 54.5
1426 S[440] 9947.35 174.5 1478 S[479] 9442.95 174.5 1530 S[518] 8938.55 174.5
1427 S[441] 9937.65 294.5 1479 S[480] 9433.25 294.5 1531 S[519] 8928.85 294.5
韦 ec
1428 SX[458] 9927.95 414.5 1480 DUMMY 9423.55 414.5 1532 SX[439] 8919.15 414.5
1429 S[442] 9918.25 54.5 1481 S[481] 9413.85 54.5 1533 S[520] 8909.45 54.5
博 lT
1430 S[443] 9908.55 174.5 1482 S[482] 9404.15 174.5 1534 S[521] 8899.75 174.5
1431 S[444] 9898.85 294.5 1483 S[483] 9394.45 294.5 1535 S[522] 8890.05 294.5
麦 ca
1432 SX[457] 9889.15 414.5 1484 DUMMY 9384.75 414.5 1536 SX[438] 8880.35 414.5
1433 S[445] 9879.45 54.5 1485 S[484] 9375.05 54.5 1537 S[523] 8870.65 54.5
1434 S[446] 9869.75 174.5 1486 S[485] 9365.35 174.5 1538 S[524] 8860.95 174.5
Fo
1435 S[447] 9860.05 294.5 1487 S[486] 9355.65 294.5 1539 S[525] 8851.25 294.5
1436 SX[456] 9850.35 414.5 1488 DUMMY 9345.95 414.5 1540 SX[437] 8841.55 414.5
1437 S[448] 9840.65 54.5 1489 S[487] 9336.25 54.5 1541 S[526] 8831.85 54.5
1438 S[449] 9830.95 174.5 1490 S[488] 9326.55 174.5 1542 S[527] 8822.15 174.5
1439 S[450] 9821.25 294.5 1491 S[489] 9316.85 294.5 1543 S[528] 8812.45 294.5
1440 SX[455] 9811.55 414.5 1492 DUMMY 9307.15 414.5 1544 SX[436] 8802.75 414.5
1441 S[451] 9801.85 54.5 1493 S[490] 9297.45 54.5 1545 S[529] 8793.05 54.5
1442 S[452] 9792.15 174.5 1494 S[491] 9287.75 174.5 1546 S[530] 8783.35 174.5
1443 S[453] 9782.45 294.5 1495 S[492] 9278.05 294.5 1547 S[531] 8773.65 294.5
1444 SX[454] 9772.75 414.5 1496 SX[448] 9268.35 414.5 1548 SX[435] 8763.95 414.5
1445 S[454] 9763.05 54.5 1497 S[493] 9258.65 54.5 1549 S[532] 8754.25 54.5
1446 S[455] 9753.35 174.5 1498 S[494] 9248.95 174.5 1550 S[533] 8744.55 174.5
1447 S[456] 9743.65 294.5 1499 S[495] 9239.25 294.5 1551 S[534] 8734.85 294.5
1448 SX[453] 9733.95 414.5 1500 SX[447] 9229.55 414.5 1552 SX[434] 8725.15 414.5
1449 S[457] 9724.25 54.5 1501 S[496] 9219.85 54.5 1553 S[535] 8715.45 54.5
1450 S[458] 9714.55 174.5 1502 S[497] 9210.15 174.5 1554 S[536] 8705.75 174.5

Preliminary
FT8006S-AN
1555 S[537] 8696.05 294.5 1607 S[576] 8191.65 294.5 1659 S[615] 7687.25 294.5
1556 SX[433] 8686.35 414.5 1608 SX[420] 8181.95 414.5 1660 SX[414] 7677.55 414.5
1557 S[538] 8676.65 54.5 1609 S[577] 8172.25 54.5 1661 S[616] 7667.85 54.5
1558 S[539] 8666.95 174.5 1610 S[578] 8162.55 174.5 1662 S[617] 7658.15 174.5
1559 S[540] 8657.25 294.5 1611 S[579] 8152.85 294.5 1663 S[618] 7648.45 294.5
1560 SX[432] 8647.55 414.5 1612 SX[419] 8143.15 414.5 1664 SX[413] 7638.75 414.5
1561 S[541] 8637.85 54.5 1613 S[580] 8133.45 54.5 1665 S[619] 7629.05 54.5
1562 S[542] 8628.15 174.5 1614 S[581] 8123.75 174.5 1666 S[620] 7619.35 174.5
1563 S[543] 8618.45 294.5 1615 S[582] 8114.05 294.5 1667 S[621] 7609.65 294.5
r
Fo
1564 SX[431] 8608.75 414.5 1616 SX[418] 8104.35 414.5 1668 SX[412] 7599.95 414.5
1565 S[544] 8599.05 54.5 1617 S[583] 8094.65 54.5 1669 S[622] 7590.25 54.5
1566 S[545] 8589.35 174.5 1618 S[584] 8084.95 174.5 1670 S[623] 7580.55 174.5
1567 S[546] 8579.65 294.5 1619 S[585] 8075.25 294.5 1671 S[624] 7570.85 294.5
l
1568 SX[430] 8569.95 414.5 1620 SX[417] 8065.55 414.5 1672 SX[411] 7561.15 414.5
nl tia
1569 S[547] 8560.25 54.5 1621 S[586] 8055.85 54.5 1673 S[625] 7551.45 54.5
1570 S[548] 8550.55 174.5 1622 S[587] 8046.15 174.5 1674 S[626] 7541.75 174.5
O en
1571 S[549] 8540.85 294.5 1623 S[588] 8036.45 294.5 1675 S[627] 7532.05 294.5
1572 SX[429] 8531.15 414.5 1624 DUMMY 8026.75 414.5 1676 SX[410] 7522.35 414.5
1573 S[550] 8521.45 54.5 1625 S[589] 8017.05 54.5 1677 S[628] 7512.65 54.5
se id
1574 S[551] 8511.75 174.5 1626 S[590] 8007.35 174.5 1678 S[629] 7502.95 174.5
y
1575 S[552] 8502.05 294.5 1627 S[591] 7997.65 294.5 1679 S[630] 7493.25 294.5
U nf
1576 SX[428] 8492.35 414.5 1628 DUMMY 7987.95 414.5 1680 SX[409] 7483.55 414.5
1577 S[553] 8482.65 54.5 1629 S[592] 7978.25 54.5 1681 S[631] 7473.85 54.5
o
1578 S[554] 8472.95 174.5 1630 S[593] 7968.55 174.5 1682 S[632] 7464.15 174.5
1579 S[555] 8463.25 294.5 1631 S[594] 7958.85 294.5 1683 S[633] 7454.45 294.5
尔 hC
1580 SX[427] 8453.55 414.5 1632 DUMMY 7949.15 414.5 1684 SX[408] 7444.75 414.5
1581 S[556] 8443.85 54.5 1633 S[595] 7939.45 54.5 1685 S[634] 7435.05 54.5
1582 S[557] 8434.15 174.5 1634 S[596] 7929.75 174.5 1686 S[635] 7425.35 174.5
1583 S[558] 8424.45 294.5 1635 S[597] 7920.05 294.5 1687 S[636] 7415.65 294.5
韦 ec
1584 SX[426] 8414.75 414.5 1636 DUMMY 7910.35 414.5 1688 SX[407] 7405.95 414.5
1585 S[559] 8405.05 54.5 1637 S[598] 7900.65 54.5 1689 S[637] 7396.25 54.5
博 lT
1586 S[560] 8395.35 174.5 1638 S[599] 7890.95 174.5 1690 S[638] 7386.55 174.5
1587 S[561] 8385.65 294.5 1639 S[600] 7881.25 294.5 1691 S[639] 7376.85 294.5
麦 ca
1588 SX[425] 8375.95 414.5 1640 DUMMY 7871.55 414.5 1692 SX[406] 7367.15 414.5
1589 S[562] 8366.25 54.5 1641 S[601] 7861.85 54.5 1693 S[640] 7357.45 54.5
1590 S[563] 8356.55 174.5 1642 S[602] 7852.15 174.5 1694 S[641] 7347.75 174.5
Fo
1591 S[564] 8346.85 294.5 1643 S[603] 7842.45 294.5 1695 S[642] 7338.05 294.5
1592 SX[424] 8337.15 414.5 1644 DUMMY 7832.75 414.5 1696 SX[405] 7328.35 414.5
1593 S[565] 8327.45 54.5 1645 S[604] 7823.05 54.5 1697 S[643] 7318.65 54.5
1594 S[566] 8317.75 174.5 1646 S[605] 7813.35 174.5 1698 S[644] 7308.95 174.5
1595 S[567] 8308.05 294.5 1647 S[606] 7803.65 294.5 1699 S[645] 7299.25 294.5
1596 SX[423] 8298.35 414.5 1648 DUMMY 7793.95 414.5 1700 SX[404] 7289.55 414.5
1597 S[568] 8288.65 54.5 1649 S[607] 7784.25 54.5 1701 S[646] 7279.85 54.5
1598 S[569] 8278.95 174.5 1650 S[608] 7774.55 174.5 1702 S[647] 7270.15 174.5
1599 S[570] 8269.25 294.5 1651 S[609] 7764.85 294.5 1703 S[648] 7260.45 294.5
1600 SX[422] 8259.55 414.5 1652 SX[416] 7755.15 414.5 1704 SX[403] 7250.75 414.5
1601 S[571] 8249.85 54.5 1653 S[610] 7745.45 54.5 1705 S[649] 7241.05 54.5
1602 S[572] 8240.15 174.5 1654 S[611] 7735.75 174.5 1706 S[650] 7231.35 174.5
1603 S[573] 8230.45 294.5 1655 S[612] 7726.05 294.5 1707 S[651] 7221.65 294.5
1604 SX[421] 8220.75 414.5 1656 SX[415] 7716.35 414.5 1708 SX[402] 7211.95 414.5
1605 S[574] 8211.05 54.5 1657 S[613] 7706.65 54.5 1709 S[652] 7202.25 54.5
1606 S[575] 8201.35 174.5 1658 S[614] 7696.95 174.5 1710 S[653] 7192.55 174.5

Preliminary
FT8006S-AN
1711 S[654] 7182.85 294.5 1763 S[693] 6678.45 294.5 1815 S[732] 6174.05 294.5
1712 SX[401] 7173.15 414.5 1764 SX[388] 6668.75 414.5 1816 DUMMY 6164.35 414.5
1713 S[655] 7163.45 54.5 1765 S[694] 6659.05 54.5 1817 S[733] 6154.65 54.5
1714 S[656] 7153.75 174.5 1766 S[695] 6649.35 174.5 1818 S[734] 6144.95 174.5
1715 S[657] 7144.05 294.5 1767 S[696] 6639.65 294.5 1819 S[735] 6135.25 294.5
1716 SX[400] 7134.35 414.5 1768 SX[387] 6629.95 414.5 1820 SX[384] 6125.55 414.5
1717 S[658] 7124.65 54.5 1769 S[697] 6620.25 54.5 1821 S[736] 6115.85 54.5
1718 S[659] 7114.95 174.5 1770 S[698] 6610.55 174.5 1822 S[737] 6106.15 174.5
1719 S[660] 7105.25 294.5 1771 S[699] 6600.85 294.5 1823 S[738] 6096.45 294.5
r
Fo
1720 SX[399] 7095.55 414.5 1772 SX[386] 6591.15 414.5 1824 SX[383] 6086.75 414.5
1721 S[661] 7085.85 54.5 1773 S[700] 6581.45 54.5 1825 S[739] 6077.05 54.5
1722 S[662] 7076.15 174.5 1774 S[701] 6571.75 174.5 1826 S[740] 6067.35 174.5
1723 S[663] 7066.45 294.5 1775 S[702] 6562.05 294.5 1827 S[741] 6057.65 294.5
l
1724 SX[398] 7056.75 414.5 1776 SX[385] 6552.35 414.5 1828 SX[382] 6047.95 414.5
nl tia
1725 S[664] 7047.05 54.5 1777 S[703] 6542.65 54.5 1829 S[742] 6038.25 54.5
1726 S[665] 7037.35 174.5 1778 S[704] 6532.95 174.5 1830 S[743] 6028.55 174.5
O en
1727 S[666] 7027.65 294.5 1779 S[705] 6523.25 294.5 1831 S[744] 6018.85 294.5
1728 SX[397] 7017.95 414.5 1780 DUMMY 6513.55 414.5 1832 SX[381] 6009.15 414.5
1729 S[667] 7008.25 54.5 1781 S[706] 6503.85 54.5 1833 S[745] 5999.45 54.5
se id
1730 S[668] 6998.55 174.5 1782 S[707] 6494.15 174.5 1834 S[746] 5989.75 174.5
y
1731 S[669] 6988.85 294.5 1783 S[708] 6484.45 294.5 1835 S[747] 5980.05 294.5
U nf
1732 SX[396] 6979.15 414.5 1784 DUMMY 6474.75 414.5 1836 SX[380] 5970.35 414.5
1733 S[670] 6969.45 54.5 1785 S[709] 6465.05 54.5 1837 S[748] 5960.65 54.5
o
1734 S[671] 6959.75 174.5 1786 S[710] 6455.35 174.5 1838 S[749] 5950.95 174.5
1735 S[672] 6950.05 294.5 1787 S[711] 6445.65 294.5 1839 S[750] 5941.25 294.5
尔 hC
1736 SX[395] 6940.35 414.5 1788 DUMMY 6435.95 414.5 1840 SX[379] 5931.55 414.5
1737 S[673] 6930.65 54.5 1789 S[712] 6426.25 54.5 1841 S[751] 5921.85 54.5
1738 S[674] 6920.95 174.5 1790 S[713] 6416.55 174.5 1842 S[752] 5912.15 174.5
1739 S[675] 6911.25 294.5 1791 S[714] 6406.85 294.5 1843 S[753] 5902.45 294.5
韦 ec
1740 SX[394] 6901.55 414.5 1792 DUMMY 6397.15 414.5 1844 SX[378] 5892.75 414.5
1741 S[676] 6891.85 54.5 1793 S[715] 6387.45 54.5 1845 S[754] 5883.05 54.5
博 lT
1742 S[677] 6882.15 174.5 1794 S[716] 6377.75 174.5 1846 S[755] 5873.35 174.5
1743 S[678] 6872.45 294.5 1795 S[717] 6368.05 294.5 1847 S[756] 5863.65 294.5
麦 ca
1744 SX[393] 6862.75 414.5 1796 DUMMY 6358.35 414.5 1848 SX[377] 5853.95 414.5
1745 S[679] 6853.05 54.5 1797 S[718] 6348.65 54.5 1849 S[757] 5844.25 54.5
1746 S[680] 6843.35 174.5 1798 S[719] 6338.95 174.5 1850 S[758] 5834.55 174.5
Fo
1747 S[681] 6833.65 294.5 1799 S[720] 6329.25 294.5 1851 S[759] 5824.85 294.5
1748 SX[392] 6823.95 414.5 1800 DUMMY 6319.55 414.5 1852 SX[376] 5815.15 414.5
1749 S[682] 6814.25 54.5 1801 S[721] 6309.85 54.5 1853 S[760] 5805.45 54.5
1750 S[683] 6804.55 174.5 1802 S[722] 6300.15 174.5 1854 S[761] 5795.75 174.5
1751 S[684] 6794.85 294.5 1803 S[723] 6290.45 294.5 1855 S[762] 5786.05 294.5
1752 SX[391] 6785.15 414.5 1804 DUMMY 6280.75 414.5 1856 SX[375] 5776.35 414.5
1753 S[685] 6775.45 54.5 1805 S[724] 6271.05 54.5 1857 S[763] 5766.65 54.5
1754 S[686] 6765.75 174.5 1806 S[725] 6261.35 174.5 1858 S[764] 5756.95 174.5
1755 S[687] 6756.05 294.5 1807 S[726] 6251.65 294.5 1859 S[765] 5747.25 294.5
1756 SX[390] 6746.35 414.5 1808 DUMMY 6241.95 414.5 1860 SX[374] 5737.55 414.5
1757 S[688] 6736.65 54.5 1809 S[727] 6232.25 54.5 1861 S[766] 5727.85 54.5
1758 S[689] 6726.95 174.5 1810 S[728] 6222.55 174.5 1862 S[767] 5718.15 174.5
1759 S[690] 6717.25 294.5 1811 S[729] 6212.85 294.5 1863 S[768] 5708.45 294.5
1760 SX[389] 6707.55 414.5 1812 DUMMY 6203.15 414.5 1864 SX[373] 5698.75 414.5
1761 S[691] 6697.85 54.5 1813 S[730] 6193.45 54.5 1865 S[769] 5689.05 54.5
1762 S[692] 6688.15 174.5 1814 S[731] 6183.75 174.5 1866 S[770] 5679.35 174.5

Preliminary
FT8006S-AN
1867 S[771] 5669.65 294.5 1919 S[810] 5165.25 294.5 1971 S[849] 4660.85 294.5
1868 SX[372] 5659.95 414.5 1920 SX[359] 5155.55 414.5 1972 DUMMY 4651.15 414.5
1869 S[772] 5650.25 54.5 1921 S[811] 5145.85 54.5 1973 S[850] 4641.45 54.5
1870 S[773] 5640.55 174.5 1922 S[812] 5136.15 174.5 1974 S[851] 4631.75 174.5
1871 S[774] 5630.85 294.5 1923 S[813] 5126.45 294.5 1975 S[852] 4622.05 294.5
1872 SX[371] 5621.15 414.5 1924 SX[358] 5116.75 414.5 1976 SX[352] 4612.35 414.5
1873 S[775] 5611.45 54.5 1925 S[814] 5107.05 54.5 1977 S[853] 4602.65 54.5
1874 S[776] 5601.75 174.5 1926 S[815] 5097.35 174.5 1978 S[854] 4592.95 174.5
1875 S[777] 5592.05 294.5 1927 S[816] 5087.65 294.5 1979 S[855] 4583.25 294.5
r
Fo
1876 SX[370] 5582.35 414.5 1928 SX[357] 5077.95 414.5 1980 SX[351] 4573.55 414.5
1877 S[778] 5572.65 54.5 1929 S[817] 5068.25 54.5 1981 S[856] 4563.85 54.5
1878 S[779] 5562.95 174.5 1930 S[818] 5058.55 174.5 1982 S[857] 4554.15 174.5
1879 S[780] 5553.25 294.5 1931 S[819] 5048.85 294.5 1983 S[858] 4544.45 294.5
l
1880 SX[369] 5543.55 414.5 1932 SX[356] 5039.15 414.5 1984 SX[350] 4534.75 414.5
nl tia
1881 S[781] 5533.85 54.5 1933 S[820] 5029.45 54.5 1985 S[859] 4525.05 54.5
1882 S[782] 5524.15 174.5 1934 S[821] 5019.75 174.5 1986 S[860] 4515.35 174.5
O en
1883 S[783] 5514.45 294.5 1935 S[822] 5010.05 294.5 1987 S[861] 4505.65 294.5
1884 SX[368] 5504.75 414.5 1936 SX[355] 5000.35 414.5 1988 SX[349] 4495.95 414.5
1885 S[784] 5495.05 54.5 1937 S[823] 4990.65 54.5 1989 S[862] 4486.25 54.5
se id
1886 S[785] 5485.35 174.5 1938 S[824] 4980.95 174.5 1990 S[863] 4476.55 174.5
y
1887 S[786] 5475.65 294.5 1939 S[825] 4971.25 294.5 1991 S[864] 4466.85 294.5
U nf
1888 SX[367] 5465.95 414.5 1940 SX[354] 4961.55 414.5 1992 SX[348] 4457.15 414.5
1889 S[787] 5456.25 54.5 1941 S[826] 4951.85 54.5 1993 S[865] 4447.45 54.5
o
1890 S[788] 5446.55 174.5 1942 S[827] 4942.15 174.5 1994 S[866] 4437.75 174.5
1891 S[789] 5436.85 294.5 1943 S[828] 4932.45 294.5 1995 S[867] 4428.05 294.5
尔 hC
1892 SX[366] 5427.15 414.5 1944 SX[353] 4922.75 414.5 1996 SX[347] 4418.35 414.5
1893 S[790] 5417.45 54.5 1945 S[829] 4913.05 54.5 1997 S[868] 4408.65 54.5
1894 S[791] 5407.75 174.5 1946 S[830] 4903.35 174.5 1998 S[869] 4398.95 174.5
1895 S[792] 5398.05 294.5 1947 S[831] 4893.65 294.5 1999 S[870] 4389.25 294.5
韦 ec
1896 SX[365] 5388.35 414.5 1948 DUMMY 4883.95 414.5 2000 SX[346] 4379.55 414.5
1897 S[793] 5378.65 54.5 1949 S[832] 4874.25 54.5 2001 S[871] 4369.85 54.5
博 lT
1898 S[794] 5368.95 174.5 1950 S[833] 4864.55 174.5 2002 S[872] 4360.15 174.5
1899 S[795] 5359.25 294.5 1951 S[834] 4854.85 294.5 2003 S[873] 4350.45 294.5
麦 ca
1900 SX[364] 5349.55 414.5 1952 DUMMY 4845.15 414.5 2004 SX[345] 4340.75 414.5
1901 S[796] 5339.85 54.5 1953 S[835] 4835.45 54.5 2005 S[874] 4331.05 54.5
1902 S[797] 5330.15 174.5 1954 S[836] 4825.75 174.5 2006 S[875] 4321.35 174.5
Fo
1903 S[798] 5320.45 294.5 1955 S[837] 4816.05 294.5 2007 S[876] 4311.65 294.5
1904 SX[363] 5310.75 414.5 1956 DUMMY 4806.35 414.5 2008 SX[344] 4301.95 414.5
1905 S[799] 5301.05 54.5 1957 S[838] 4796.65 54.5 2009 S[877] 4292.25 54.5
1906 S[800] 5291.35 174.5 1958 S[839] 4786.95 174.5 2010 S[878] 4282.55 174.5
1907 S[801] 5281.65 294.5 1959 S[840] 4777.25 294.5 2011 S[879] 4272.85 294.5
1908 SX[362] 5271.95 414.5 1960 DUMMY 4767.55 414.5 2012 SX[343] 4263.15 414.5
1909 S[802] 5262.25 54.5 1961 S[841] 4757.85 54.5 2013 S[880] 4253.45 54.5
1910 S[803] 5252.55 174.5 1962 S[842] 4748.15 174.5 2014 S[881] 4243.75 174.5
1911 S[804] 5242.85 294.5 1963 S[843] 4738.45 294.5 2015 S[882] 4234.05 294.5
1912 SX[361] 5233.15 414.5 1964 DUMMY 4728.75 414.5 2016 SX[342] 4224.35 414.5
1913 S[805] 5223.45 54.5 1965 S[844] 4719.05 54.5 2017 S[883] 4214.65 54.5
1914 S[806] 5213.75 174.5 1966 S[845] 4709.35 174.5 2018 S[884] 4204.95 174.5
1915 S[807] 5204.05 294.5 1967 S[846] 4699.65 294.5 2019 S[885] 4195.25 294.5
1916 SX[360] 5194.35 414.5 1968 DUMMY 4689.95 414.5 2020 SX[341] 4185.55 414.5
1917 S[808] 5184.65 54.5 1969 S[847] 4680.25 54.5 2021 S[886] 4175.85 54.5
1918 S[809] 5174.95 174.5 1970 S[848] 4670.55 174.5 2022 S[887] 4166.15 174.5

Preliminary
FT8006S-AN
2023 S[888] 4156.45 294.5 2075 S[927] 3652.05 294.5 2127 S[966] 3147.65 294.5
2024 SX[340] 4146.75 414.5 2076 SX[327] 3642.35 414.5 2128 DUMMY 3137.95 414.5
2025 S[889] 4137.05 54.5 2077 S[928] 3632.65 54.5 2129 S[967] 3128.25 54.5
2026 S[890] 4127.35 174.5 2078 S[929] 3622.95 174.5 2130 S[968] 3118.55 174.5
2027 S[891] 4117.65 294.5 2079 S[930] 3613.25 294.5 2131 S[969] 3108.85 294.5
2028 SX[339] 4107.95 414.5 2080 SX[326] 3603.55 414.5 2132 SX[320] 3099.15 414.5
2029 S[892] 4098.25 54.5 2081 S[931] 3593.85 54.5 2133 S[970] 3089.45 54.5
2030 S[893] 4088.55 174.5 2082 S[932] 3584.15 174.5 2134 S[971] 3079.75 174.5
2031 S[894] 4078.85 294.5 2083 S[933] 3574.45 294.5 2135 S[972] 3070.05 294.5
r
Fo
2032 SX[338] 4069.15 414.5 2084 SX[325] 3564.75 414.5 2136 SX[319] 3060.35 414.5
2033 S[895] 4059.45 54.5 2085 S[934] 3555.05 54.5 2137 S[973] 3050.65 54.5
2034 S[896] 4049.75 174.5 2086 S[935] 3545.35 174.5 2138 S[974] 3040.95 174.5
2035 S[897] 4040.05 294.5 2087 S[936] 3535.65 294.5 2139 S[975] 3031.25 294.5
l
2036 SX[337] 4030.35 414.5 2088 SX[324] 3525.95 414.5 2140 SX[318] 3021.55 414.5
nl tia
2037 S[898] 4020.65 54.5 2089 S[937] 3516.25 54.5 2141 S[976] 3011.85 54.5
2038 S[899] 4010.95 174.5 2090 S[938] 3506.55 174.5 2142 S[977] 3002.15 174.5
O en
2039 S[900] 4001.25 294.5 2091 S[939] 3496.85 294.5 2143 S[978] 2992.45 294.5
2040 SX[336] 3991.55 414.5 2092 SX[323] 3487.15 414.5 2144 SX[317] 2982.75 414.5
2041 S[901] 3981.85 54.5 2093 S[940] 3477.45 54.5 2145 S[979] 2973.05 54.5
se id
2042 S[902] 3972.15 174.5 2094 S[941] 3467.75 174.5 2146 S[980] 2963.35 174.5
y
2043 S[903] 3962.45 294.5 2095 S[942] 3458.05 294.5 2147 S[981] 2953.65 294.5
U nf
2044 SX[335] 3952.75 414.5 2096 SX[322] 3448.35 414.5 2148 SX[316] 2943.95 414.5
2045 S[904] 3943.05 54.5 2097 S[943] 3438.65 54.5 2149 S[982] 2934.25 54.5
o
2046 S[905] 3933.35 174.5 2098 S[944] 3428.95 174.5 2150 S[983] 2924.55 174.5
2047 S[906] 3923.65 294.5 2099 S[945] 3419.25 294.5 2151 S[984] 2914.85 294.5
尔 hC
2048 SX[334] 3913.95 414.5 2100 SX[321] 3409.55 414.5 2152 SX[315] 2905.15 414.5
2049 S[907] 3904.25 54.5 2101 S[946] 3399.85 54.5 2153 S[985] 2895.45 54.5
2050 S[908] 3894.55 174.5 2102 S[947] 3390.15 174.5 2154 S[986] 2885.75 174.5
2051 S[909] 3884.85 294.5 2103 S[948] 3380.45 294.5 2155 S[987] 2876.05 294.5
韦 ec
2052 SX[333] 3875.15 414.5 2104 DUMMY 3370.75 414.5 2156 SX[314] 2866.35 414.5
2053 S[910] 3865.45 54.5 2105 S[949] 3361.05 54.5 2157 S[988] 2856.65 54.5
博 lT
2054 S[911] 3855.75 174.5 2106 S[950] 3351.35 174.5 2158 S[989] 2846.95 174.5
2055 S[912] 3846.05 294.5 2107 S[951] 3341.65 294.5 2159 S[990] 2837.25 294.5
麦 ca
2056 SX[332] 3836.35 414.5 2108 DUMMY 3331.95 414.5 2160 SX[313] 2827.55 414.5
2057 S[913] 3826.65 54.5 2109 S[952] 3322.25 54.5 2161 S[991] 2817.85 54.5
2058 S[914] 3816.95 174.5 2110 S[953] 3312.55 174.5 2162 S[992] 2808.15 174.5
Fo
2059 S[915] 3807.25 294.5 2111 S[954] 3302.85 294.5 2163 S[993] 2798.45 294.5
2060 SX[331] 3797.55 414.5 2112 DUMMY 3293.15 414.5 2164 SX[312] 2788.75 414.5
2061 S[916] 3787.85 54.5 2113 S[955] 3283.45 54.5 2165 S[994] 2779.05 54.5
2062 S[917] 3778.15 174.5 2114 S[956] 3273.75 174.5 2166 S[995] 2769.35 174.5
2063 S[918] 3768.45 294.5 2115 S[957] 3264.05 294.5 2167 S[996] 2759.65 294.5
2064 SX[330] 3758.75 414.5 2116 DUMMY 3254.35 414.5 2168 SX[311] 2749.95 414.5
2065 S[919] 3749.05 54.5 2117 S[958] 3244.65 54.5 2169 S[997] 2740.25 54.5
2066 S[920] 3739.35 174.5 2118 S[959] 3234.95 174.5 2170 S[998] 2730.55 174.5
2067 S[921] 3729.65 294.5 2119 S[960] 3225.25 294.5 2171 S[999] 2720.85 294.5
2068 SX[329] 3719.95 414.5 2120 DUMMY 3215.55 414.5 2172 SX[310] 2711.15 414.5
2069 S[922] 3710.25 54.5 2121 S[961] 3205.85 54.5 2173 S[1000] 2701.45 54.5
2070 S[923] 3700.55 174.5 2122 S[962] 3196.15 174.5 2174 S[1001] 2691.75 174.5
2071 S[924] 3690.85 294.5 2123 S[963] 3186.45 294.5 2175 S[1002] 2682.05 294.5
2072 SX[328] 3681.15 414.5 2124 DUMMY 3176.75 414.5 2176 SX[309] 2672.35 414.5
2073 S[925] 3671.45 54.5 2125 S[964] 3167.05 54.5 2177 S[1003] 2662.65 54.5
2074 S[926] 3661.75 174.5 2126 S[965] 3157.35 174.5 2178 S[1004] 2652.95 174.5

Preliminary
FT8006S-AN
2179 S[1005] 2643.25 294.5 2231 S[1044] 2138.85 294.5 2283 DUMMY 1634.45 294.5
2180 SX[308] 2633.55 414.5 2232 SX[295] 2129.15 414.5 2284 DUMMY 1624.75 414.5
2181 S[1006] 2623.85 54.5 2233 S[1045] 2119.45 54.5 2285 DUMMY 1615.05 54.5
2182 S[1007] 2614.15 174.5 2234 S[1046] 2109.75 174.5 2286 DUMMY 1605.35 174.5
2183 S[1008] 2604.45 294.5 2235 S[1047] 2100.05 294.5 2287 DUMMY 1595.65 294.5
2184 SX[307] 2594.75 414.5 2236 SX[294] 2090.35 414.5 2288 DUMMY 1585.95 414.5
2185 S[1009] 2585.05 54.5 2237 S[1048] 2080.65 54.5 2289 DUMMY 1576.25 54.5
2186 S[1010] 2575.35 174.5 2238 S[1049] 2070.95 174.5 2290 DUMMY 1566.55 174.5
2187 S[1011] 2565.65 294.5 2239 S[1050] 2061.25 294.5 2291 DUMMY 1556.85 294.5
r
Fo
2188 SX[306] 2555.95 414.5 2240 SX[293] 2051.55 414.5 2292 DUMMY 1547.15 414.5
2189 S[1012] 2546.25 54.5 2241 S[1051] 2041.85 54.5 2293 DUMMY 1537.45 54.5
2190 S[1013] 2536.55 174.5 2242 S[1052] 2032.15 174.5 2294 DUMMY 1527.75 174.5
2191 S[1014] 2526.85 294.5 2243 S[1053] 2022.45 294.5 2295 DUMMY 1518.05 294.5
l
2192 SX[305] 2517.15 414.5 2244 SX[292] 2012.75 414.5 2296 DUMMY 1508.35 414.5
nl tia
2193 S[1015] 2507.45 54.5 2245 S[1054] 2003.05 54.5 2297 DUMMY 1498.65 54.5
2194 S[1016] 2497.75 174.5 2246 S[1055] 1993.35 174.5 2298 DUMMY 1488.95 174.5
O en
2195 S[1017] 2488.05 294.5 2247 S[1056] 1983.65 294.5 2299 DUMMY 1479.25 294.5
2196 SX[304] 2478.35 414.5 2248 SX[291] 1973.95 414.5 2300 DUMMY 1469.55 414.5
2197 S[1018] 2468.65 54.5 2249 S[1057] 1964.25 54.5 2301 DUMMY 1459.85 54.5
se id
2198 S[1019] 2458.95 174.5 2250 S[1058] 1954.55 174.5 2302 DUMMY 1450.15 174.5
y
2199 S[1020] 2449.25 294.5 2251 S[1059] 1944.85 294.5 2303 DUMMY 1440.45 294.5
U nf
2200 SX[303] 2439.55 414.5 2252 SX[290] 1935.15 414.5 2304 DUMMY 1430.75 414.5
2201 S[1021] 2429.85 54.5 2253 S[1060] 1925.45 54.5 2305 DUMMY 1421.05 54.5
o
2202 S[1022] 2420.15 174.5 2254 S[1061] 1915.75 174.5 2306 DUMMY 1411.35 174.5
2203 S[1023] 2410.45 294.5 2255 S[1062] 1906.05 294.5 2307 DUMMY 1401.65 294.5
尔 hC
2204 SX[302] 2400.75 414.5 2256 SX[289] 1896.35 414.5 2308 DUMMY 1391.95 414.5
2205 S[1024] 2391.05 54.5 2257 S[1063] 1886.65 54.5 2309 DUMMY 1382.25 54.5
2206 S[1025] 2381.35 174.5 2258 S[1064] 1876.95 174.5 2310 DUMMY 1372.55 174.5
2207 S[1026] 2371.65 294.5 2259 S[1065] 1867.25 294.5 2311 DUMMY 1362.85 294.5
韦 ec
2208 SX[301] 2361.95 414.5 2260 DUMMY 1857.55 414.5 2312 DUMMY 1353.15 414.5
2209 S[1027] 2352.25 54.5 2261 S[1066] 1847.85 54.5 2313 DUMMY 1343.45 54.5
博 lT
2210 S[1028] 2342.55 174.5 2262 S[1067] 1838.15 174.5 2314 DUMMY 1333.75 174.5
2211 S[1029] 2332.85 294.5 2263 S[1068] 1828.45 294.5 2315 DUMMY 1324.05 294.5
麦 ca
2212 SX[300] 2323.15 414.5 2264 DUMMY 1818.75 414.5 2316 DUMMY 1314.35 414.5
2213 S[1030] 2313.45 54.5 2265 S[1069] 1809.05 54.5 2317 DUMMY 1304.65 54.5
2214 S[1031] 2303.75 174.5 2266 S[1070] 1799.35 174.5 2318 DUMMY 1294.95 174.5
Fo
2215 S[1032] 2294.05 294.5 2267 S[1071] 1789.65 294.5 2319 DUMMY 1285.25 294.5
2216 SX[299] 2284.35 414.5 2268 DUMMY 1779.95 414.5 2320 DUMMY 1275.55 414.5
2217 S[1033] 2274.65 54.5 2269 S[1072] 1770.25 54.5 2321 DUMMY 1265.85 54.5
2218 S[1034] 2264.95 174.5 2270 S[1073] 1760.55 174.5 2322 DUMMY 1256.15 174.5
2219 S[1035] 2255.25 294.5 2271 S[1074] 1750.85 294.5 2323 DUMMY 1246.45 294.5
2220 SX[298] 2245.55 414.5 2272 DUMMY 1741.15 414.5 2324 DUMMY 1236.75 414.5
2221 S[1036] 2235.85 54.5 2273 S[1075] 1731.45 54.5 2325 DUMMY 1227.05 54.5
2222 S[1037] 2226.15 174.5 2274 S[1076] 1721.75 174.5 2326 DUMMY 1217.35 174.5
2223 S[1038] 2216.45 294.5 2275 S[1077] 1712.05 294.5 2327 DUMMY 1207.65 294.5
2224 SX[297] 2206.75 414.5 2276 DUMMY 1702.35 414.5 2328 DUMMY 1197.95 414.5
2225 S[1039] 2197.05 54.5 2277 S[1078] 1692.65 54.5 2329 DUMMY 1188.25 54.5
2226 S[1040] 2187.35 174.5 2278 S[1079] 1682.95 174.5 2330 DUMMY 1178.55 174.5
2227 S[1041] 2177.65 294.5 2279 S[1080] 1673.25 294.5 2331 DUMMY 1168.85 294.5
2228 SX[296] 2167.95 414.5 2280 DUMMY 1663.55 414.5 2332 DUMMY 1159.15 414.5
2229 S[1042] 2158.25 54.5 2281 DUMMY 1653.85 54.5 2333 DUMMY 1149.45 54.5
2230 S[1043] 2148.55 174.5 2282 DUMMY 1644.15 174.5 2334 DUMMY 1139.75 174.5

Preliminary
FT8006S-AN
2335 DUMMY 1130.05 294.5 2387 DUMMY 625.65 294.5 2439 DUMMY 121.25 294.5
r
Fo
l
2348 DUMMY 1003.95 414.5 2400 DUMMY 499.55 414.5 2452 DUMMY -4.85 414.5
nl tia
O en
se id
y
U nf
o
尔 hC
韦 ec
博 lT
麦 ca
Fo

Preliminary
FT8006S-AN
2491 DUMMY -383.15 294.5 2543 DUMMY -887.55 294.5 2595 DUMMY -1391.95 294.5
r
Fo
l
nl tia
O en
se id
y
U nf
o
尔 hC
韦 ec
2521 DUMMY -674.15 54.5 2573 DUMMY -1178.55 54.5 2625 S[1081] -1682.95 54.5
博 lT
2522 DUMMY -683.85 174.5 2574 DUMMY -1188.25 174.5 2626 S[1082] -1692.65 174.5
2523 DUMMY -693.55 294.5 2575 DUMMY -1197.95 294.5 2627 S[1083] -1702.35 294.5
麦 ca
2525 DUMMY -712.95 54.5 2577 DUMMY -1217.35 54.5 2629 S[1084] -1721.75 54.5
2526 DUMMY -722.65 174.5 2578 DUMMY -1227.05 174.5 2630 S[1085] -1731.45 174.5
Fo
2527 DUMMY -732.35 294.5 2579 DUMMY -1236.75 294.5 2631 S[1086] -1741.15 294.5
2529 DUMMY -751.75 54.5 2581 DUMMY -1256.15 54.5 2633 S[1087] -1760.55 54.5
2530 DUMMY -761.45 174.5 2582 DUMMY -1265.85 174.5 2634 S[1088] -1770.25 174.5
2531 DUMMY -771.15 294.5 2583 DUMMY -1275.55 294.5 2635 S[1089] -1779.95 294.5
2533 DUMMY -790.55 54.5 2585 DUMMY -1294.95 54.5 2637 S[1090] -1799.35 54.5
2534 DUMMY -800.25 174.5 2586 DUMMY -1304.65 174.5 2638 S[1091] -1809.05 174.5
2535 DUMMY -809.95 294.5 2587 DUMMY -1314.35 294.5 2639 S[1092] -1818.75 294.5
2537 DUMMY -829.35 54.5 2589 DUMMY -1333.75 54.5 2641 S[1093] -1838.15 54.5
2538 DUMMY -839.05 174.5 2590 DUMMY -1343.45 174.5 2642 S[1094] -1847.85 174.5
2539 DUMMY -848.75 294.5 2591 DUMMY -1353.15 294.5 2643 S[1095] -1857.55 294.5
2541 DUMMY -868.15 54.5 2593 DUMMY -1372.55 54.5 2645 S[1096] -1876.95 54.5
2542 DUMMY -877.85 174.5 2594 DUMMY -1382.25 174.5 2646 S[1097] -1886.65 174.5

Preliminary
FT8006S-AN
2647 S[1098] -1896.35 294.5 2699 S[1137] -2400.75 294.5 2751 S[1176] -2905.15 294.5
2648 SX[288] -1906.05 414.5 2700 SX[275] -2410.45 414.5 2752 SX[262] -2914.85 414.5
2649 S[1099] -1915.75 54.5 2701 S[1138] -2420.15 54.5 2753 S[1177] -2924.55 54.5
2650 S[1100] -1925.45 174.5 2702 S[1139] -2429.85 174.5 2754 S[1178] -2934.25 174.5
2651 S[1101] -1935.15 294.5 2703 S[1140] -2439.55 294.5 2755 S[1179] -2943.95 294.5
2652 SX[287] -1944.85 414.5 2704 SX[274] -2449.25 414.5 2756 SX[261] -2953.65 414.5
2653 S[1102] -1954.55 54.5 2705 S[1141] -2458.95 54.5 2757 S[1180] -2963.35 54.5
2654 S[1103] -1964.25 174.5 2706 S[1142] -2468.65 174.5 2758 S[1181] -2973.05 174.5
2655 S[1104] -1973.95 294.5 2707 S[1143] -2478.35 294.5 2759 S[1182] -2982.75 294.5
r
Fo
2656 SX[286] -1983.65 414.5 2708 SX[273] -2488.05 414.5 2760 SX[260] -2992.45 414.5
2657 S[1105] -1993.35 54.5 2709 S[1144] -2497.75 54.5 2761 S[1183] -3002.15 54.5
2658 S[1106] -2003.05 174.5 2710 S[1145] -2507.45 174.5 2762 S[1184] -3011.85 174.5
2659 S[1107] -2012.75 294.5 2711 S[1146] -2517.15 294.5 2763 S[1185] -3021.55 294.5
l
2660 SX[285] -2022.45 414.5 2712 SX[272] -2526.85 414.5 2764 SX[259] -3031.25 414.5
nl tia
2661 S[1108] -2032.15 54.5 2713 S[1147] -2536.55 54.5 2765 S[1186] -3040.95 54.5
2662 S[1109] -2041.85 174.5 2714 S[1148] -2546.25 174.5 2766 S[1187] -3050.65 174.5
O en
2663 S[1110] -2051.55 294.5 2715 S[1149] -2555.95 294.5 2767 S[1188] -3060.35 294.5
2664 SX[284] -2061.25 414.5 2716 SX[271] -2565.65 414.5 2768 SX[258] -3070.05 414.5
2665 S[1111] -2070.95 54.5 2717 S[1150] -2575.35 54.5 2769 S[1189] -3079.75 54.5
se id
2666 S[1112] -2080.65 174.5 2718 S[1151] -2585.05 174.5 2770 S[1190] -3089.45 174.5
y
2667 S[1113] -2090.35 294.5 2719 S[1152] -2594.75 294.5 2771 S[1191] -3099.15 294.5
U nf
2668 SX[283] -2100.05 414.5 2720 SX[270] -2604.45 414.5 2772 SX[257] -3108.85 414.5
2669 S[1114] -2109.75 54.5 2721 S[1153] -2614.15 54.5 2773 S[1192] -3118.55 54.5
o
2670 S[1115] -2119.45 174.5 2722 S[1154] -2623.85 174.5 2774 S[1193] -3128.25 174.5
2671 S[1116] -2129.15 294.5 2723 S[1155] -2633.55 294.5 2775 S[1194] -3137.95 294.5
尔 hC
2672 SX[282] -2138.85 414.5 2724 SX[269] -2643.25 414.5 2776 DUMMY -3147.65 414.5
2673 S[1117] -2148.55 54.5 2725 S[1156] -2652.95 54.5 2777 S[1195] -3157.35 54.5
2674 S[1118] -2158.25 174.5 2726 S[1157] -2662.65 174.5 2778 S[1196] -3167.05 174.5
2675 S[1119] -2167.95 294.5 2727 S[1158] -2672.35 294.5 2779 S[1197] -3176.75 294.5
韦 ec
2676 SX[281] -2177.65 414.5 2728 SX[268] -2682.05 414.5 2780 DUMMY -3186.45 414.5
2677 S[1120] -2187.35 54.5 2729 S[1159] -2691.75 54.5 2781 S[1198] -3196.15 54.5
博 lT
2678 S[1121] -2197.05 174.5 2730 S[1160] -2701.45 174.5 2782 S[1199] -3205.85 174.5
2679 S[1122] -2206.75 294.5 2731 S[1161] -2711.15 294.5 2783 S[1200] -3215.55 294.5
麦 ca
2680 SX[280] -2216.45 414.5 2732 SX[267] -2720.85 414.5 2784 DUMMY -3225.25 414.5
2681 S[1123] -2226.15 54.5 2733 S[1162] -2730.55 54.5 2785 S[1201] -3234.95 54.5
2682 S[1124] -2235.85 174.5 2734 S[1163] -2740.25 174.5 2786 S[1202] -3244.65 174.5
Fo
2683 S[1125] -2245.55 294.5 2735 S[1164] -2749.95 294.5 2787 S[1203] -3254.35 294.5
2684 SX[279] -2255.25 414.5 2736 SX[266] -2759.65 414.5 2788 DUMMY -3264.05 414.5
2685 S[1126] -2264.95 54.5 2737 S[1165] -2769.35 54.5 2789 S[1204] -3273.75 54.5
2686 S[1127] -2274.65 174.5 2738 S[1166] -2779.05 174.5 2790 S[1205] -3283.45 174.5
2687 S[1128] -2284.35 294.5 2739 S[1167] -2788.75 294.5 2791 S[1206] -3293.15 294.5
2688 SX[278] -2294.05 414.5 2740 SX[265] -2798.45 414.5 2792 DUMMY -3302.85 414.5
2689 S[1129] -2303.75 54.5 2741 S[1168] -2808.15 54.5 2793 S[1207] -3312.55 54.5
2690 S[1130] -2313.45 174.5 2742 S[1169] -2817.85 174.5 2794 S[1208] -3322.25 174.5
2691 S[1131] -2323.15 294.5 2743 S[1170] -2827.55 294.5 2795 S[1209] -3331.95 294.5
2692 SX[277] -2332.85 414.5 2744 SX[264] -2837.25 414.5 2796 DUMMY -3341.65 414.5
2693 S[1132] -2342.55 54.5 2745 S[1171] -2846.95 54.5 2797 S[1210] -3351.35 54.5
2694 S[1133] -2352.25 174.5 2746 S[1172] -2856.65 174.5 2798 S[1211] -3361.05 174.5
2695 S[1134] -2361.95 294.5 2747 S[1173] -2866.35 294.5 2799 S[1212] -3370.75 294.5
2696 SX[276] -2371.65 414.5 2748 SX[263] -2876.05 414.5 2800 DUMMY -3380.45 414.5
2697 S[1135] -2381.35 54.5 2749 S[1174] -2885.75 54.5 2801 S[1213] -3390.15 54.5
2698 S[1136] -2391.05 174.5 2750 S[1175] -2895.45 174.5 2802 S[1214] -3399.85 174.5

Preliminary
FT8006S-AN
2803 S[1215] -3409.55 294.5 2855 S[1254] -3913.95 294.5 2907 S[1293] -4418.35 294.5
2804 SX[256] -3419.25 414.5 2856 SX[243] -3923.65 414.5 2908 SX[230] -4428.05 414.5
2805 S[1216] -3428.95 54.5 2857 S[1255] -3933.35 54.5 2909 S[1294] -4437.75 54.5
2806 S[1217] -3438.65 174.5 2858 S[1256] -3943.05 174.5 2910 S[1295] -4447.45 174.5
2807 S[1218] -3448.35 294.5 2859 S[1257] -3952.75 294.5 2911 S[1296] -4457.15 294.5
2808 SX[255] -3458.05 414.5 2860 SX[242] -3962.45 414.5 2912 SX[229] -4466.85 414.5
2809 S[1219] -3467.75 54.5 2861 S[1258] -3972.15 54.5 2913 S[1297] -4476.55 54.5
2810 S[1220] -3477.45 174.5 2862 S[1259] -3981.85 174.5 2914 S[1298] -4486.25 174.5
2811 S[1221] -3487.15 294.5 2863 S[1260] -3991.55 294.5 2915 S[1299] -4495.95 294.5
r
Fo
2812 SX[254] -3496.85 414.5 2864 SX[241] -4001.25 414.5 2916 SX[228] -4505.65 414.5
2813 S[1222] -3506.55 54.5 2865 S[1261] -4010.95 54.5 2917 S[1300] -4515.35 54.5
2814 S[1223] -3516.25 174.5 2866 S[1262] -4020.65 174.5 2918 S[1301] -4525.05 174.5
2815 S[1224] -3525.95 294.5 2867 S[1263] -4030.35 294.5 2919 S[1302] -4534.75 294.5
l
2816 SX[253] -3535.65 414.5 2868 SX[240] -4040.05 414.5 2920 SX[227] -4544.45 414.5
nl tia
2817 S[1225] -3545.35 54.5 2869 S[1264] -4049.75 54.5 2921 S[1303] -4554.15 54.5
2818 S[1226] -3555.05 174.5 2870 S[1265] -4059.45 174.5 2922 S[1304] -4563.85 174.5
O en
2819 S[1227] -3564.75 294.5 2871 S[1266] -4069.15 294.5 2923 S[1305] -4573.55 294.5
2820 SX[252] -3574.45 414.5 2872 SX[239] -4078.85 414.5 2924 SX[226] -4583.25 414.5
2821 S[1228] -3584.15 54.5 2873 S[1267] -4088.55 54.5 2925 S[1306] -4592.95 54.5
se id
2822 S[1229] -3593.85 174.5 2874 S[1268] -4098.25 174.5 2926 S[1307] -4602.65 174.5
y
2823 S[1230] -3603.55 294.5 2875 S[1269] -4107.95 294.5 2927 S[1308] -4612.35 294.5
U nf
2824 SX[251] -3613.25 414.5 2876 SX[238] -4117.65 414.5 2928 SX[225] -4622.05 414.5
2825 S[1231] -3622.95 54.5 2877 S[1270] -4127.35 54.5 2929 S[1309] -4631.75 54.5
o
2826 S[1232] -3632.65 174.5 2878 S[1271] -4137.05 174.5 2930 S[1310] -4641.45 174.5
2827 S[1233] -3642.35 294.5 2879 S[1272] -4146.75 294.5 2931 S[1311] -4651.15 294.5
尔 hC
2828 SX[250] -3652.05 414.5 2880 SX[237] -4156.45 414.5 2932 DUMMY -4660.85 414.5
2829 S[1234] -3661.75 54.5 2881 S[1273] -4166.15 54.5 2933 S[1312] -4670.55 54.5
2830 S[1235] -3671.45 174.5 2882 S[1274] -4175.85 174.5 2934 S[1313] -4680.25 174.5
2831 S[1236] -3681.15 294.5 2883 S[1275] -4185.55 294.5 2935 S[1314] -4689.95 294.5
韦 ec
2832 SX[249] -3690.85 414.5 2884 SX[236] -4195.25 414.5 2936 DUMMY -4699.65 414.5
2833 S[1237] -3700.55 54.5 2885 S[1276] -4204.95 54.5 2937 S[1315] -4709.35 54.5
博 lT
2834 S[1238] -3710.25 174.5 2886 S[1277] -4214.65 174.5 2938 S[1316] -4719.05 174.5
2835 S[1239] -3719.95 294.5 2887 S[1278] -4224.35 294.5 2939 S[1317] -4728.75 294.5
麦 ca
2836 SX[248] -3729.65 414.5 2888 SX[235] -4234.05 414.5 2940 DUMMY -4738.45 414.5
2837 S[1240] -3739.35 54.5 2889 S[1279] -4243.75 54.5 2941 S[1318] -4748.15 54.5
2838 S[1241] -3749.05 174.5 2890 S[1280] -4253.45 174.5 2942 S[1319] -4757.85 174.5
Fo
2839 S[1242] -3758.75 294.5 2891 S[1281] -4263.15 294.5 2943 S[1320] -4767.55 294.5
2840 SX[247] -3768.45 414.5 2892 SX[234] -4272.85 414.5 2944 DUMMY -4777.25 414.5
2841 S[1243] -3778.15 54.5 2893 S[1282] -4282.55 54.5 2945 S[1321] -4786.95 54.5
2842 S[1244] -3787.85 174.5 2894 S[1283] -4292.25 174.5 2946 S[1322] -4796.65 174.5
2843 S[1245] -3797.55 294.5 2895 S[1284] -4301.95 294.5 2947 S[1323] -4806.35 294.5
2844 SX[246] -3807.25 414.5 2896 SX[233] -4311.65 414.5 2948 DUMMY -4816.05 414.5
2845 S[1246] -3816.95 54.5 2897 S[1285] -4321.35 54.5 2949 S[1324] -4825.75 54.5
2846 S[1247] -3826.65 174.5 2898 S[1286] -4331.05 174.5 2950 S[1325] -4835.45 174.5
2847 S[1248] -3836.35 294.5 2899 S[1287] -4340.75 294.5 2951 S[1326] -4845.15 294.5
2848 SX[245] -3846.05 414.5 2900 SX[232] -4350.45 414.5 2952 DUMMY -4854.85 414.5
2849 S[1249] -3855.75 54.5 2901 S[1288] -4360.15 54.5 2953 S[1327] -4864.55 54.5
2850 S[1250] -3865.45 174.5 2902 S[1289] -4369.85 174.5 2954 S[1328] -4874.25 174.5
2851 S[1251] -3875.15 294.5 2903 S[1290] -4379.55 294.5 2955 S[1329] -4883.95 294.5
2852 SX[244] -3884.85 414.5 2904 SX[231] -4389.25 414.5 2956 DUMMY -4893.65 414.5
2853 S[1252] -3894.55 54.5 2905 S[1291] -4398.95 54.5 2957 S[1330] -4903.35 54.5
2854 S[1253] -3904.25 174.5 2906 S[1292] -4408.65 174.5 2958 S[1331] -4913.05 174.5

Preliminary
FT8006S-AN
2959 S[1332] -4922.75 294.5 3011 S[1371] -5427.15 294.5 3063 S[1410] -5931.55 294.5
2960 SX[224] -4932.45 414.5 3012 SX[211] -5436.85 414.5 3064 SX[198] -5941.25 414.5
2961 S[1333] -4942.15 54.5 3013 S[1372] -5446.55 54.5 3065 S[1411] -5950.95 54.5
2962 S[1334] -4951.85 174.5 3014 S[1373] -5456.25 174.5 3066 S[1412] -5960.65 174.5
2963 S[1335] -4961.55 294.5 3015 S[1374] -5465.95 294.5 3067 S[1413] -5970.35 294.5
2964 SX[223] -4971.25 414.5 3016 SX[210] -5475.65 414.5 3068 SX[197] -5980.05 414.5
2965 S[1336] -4980.95 54.5 3017 S[1375] -5485.35 54.5 3069 S[1414] -5989.75 54.5
2966 S[1337] -4990.65 174.5 3018 S[1376] -5495.05 174.5 3070 S[1415] -5999.45 174.5
2967 S[1338] -5000.35 294.5 3019 S[1377] -5504.75 294.5 3071 S[1416] -6009.15 294.5
r
Fo
2968 SX[222] -5010.05 414.5 3020 SX[209] -5514.45 414.5 3072 SX[196] -6018.85 414.5
2969 S[1339] -5019.75 54.5 3021 S[1378] -5524.15 54.5 3073 S[1417] -6028.55 54.5
2970 S[1340] -5029.45 174.5 3022 S[1379] -5533.85 174.5 3074 S[1418] -6038.25 174.5
2971 S[1341] -5039.15 294.5 3023 S[1380] -5543.55 294.5 3075 S[1419] -6047.95 294.5
l
2972 SX[221] -5048.85 414.5 3024 SX[208] -5553.25 414.5 3076 SX[195] -6057.65 414.5
nl tia
2973 S[1342] -5058.55 54.5 3025 S[1381] -5562.95 54.5 3077 S[1420] -6067.35 54.5
2974 S[1343] -5068.25 174.5 3026 S[1382] -5572.65 174.5 3078 S[1421] -6077.05 174.5
O en
2975 S[1344] -5077.95 294.5 3027 S[1383] -5582.35 294.5 3079 S[1422] -6086.75 294.5
2976 SX[220] -5087.65 414.5 3028 SX[207] -5592.05 414.5 3080 SX[194] -6096.45 414.5
2977 S[1345] -5097.35 54.5 3029 S[1384] -5601.75 54.5 3081 S[1423] -6106.15 54.5
se id
2978 S[1346] -5107.05 174.5 3030 S[1385] -5611.45 174.5 3082 S[1424] -6115.85 174.5
y
2979 S[1347] -5116.75 294.5 3031 S[1386] -5621.15 294.5 3083 S[1425] -6125.55 294.5
U nf
2980 SX[219] -5126.45 414.5 3032 SX[206] -5630.85 414.5 3084 SX[193] -6135.25 414.5
2981 S[1348] -5136.15 54.5 3033 S[1387] -5640.55 54.5 3085 S[1426] -6144.95 54.5
o
2982 S[1349] -5145.85 174.5 3034 S[1388] -5650.25 174.5 3086 S[1427] -6154.65 174.5
2983 S[1350] -5155.55 294.5 3035 S[1389] -5659.95 294.5 3087 S[1428] -6164.35 294.5
尔 hC
2984 SX[218] -5165.25 414.5 3036 SX[205] -5669.65 414.5 3088 DUMMY -6174.05 414.5
2985 S[1351] -5174.95 54.5 3037 S[1390] -5679.35 54.5 3089 S[1429] -6183.75 54.5
2986 S[1352] -5184.65 174.5 3038 S[1391] -5689.05 174.5 3090 S[1430] -6193.45 174.5
2987 S[1353] -5194.35 294.5 3039 S[1392] -5698.75 294.5 3091 S[1431] -6203.15 294.5
韦 ec
2988 SX[217] -5204.05 414.5 3040 SX[204] -5708.45 414.5 3092 DUMMY -6212.85 414.5
2989 S[1354] -5213.75 54.5 3041 S[1393] -5718.15 54.5 3093 S[1432] -6222.55 54.5
博 lT
2990 S[1355] -5223.45 174.5 3042 S[1394] -5727.85 174.5 3094 S[1433] -6232.25 174.5
2991 S[1356] -5233.15 294.5 3043 S[1395] -5737.55 294.5 3095 S[1434] -6241.95 294.5
麦 ca
2992 SX[216] -5242.85 414.5 3044 SX[203] -5747.25 414.5 3096 DUMMY -6251.65 414.5
2993 S[1357] -5252.55 54.5 3045 S[1396] -5756.95 54.5 3097 S[1435] -6261.35 54.5
2994 S[1358] -5262.25 174.5 3046 S[1397] -5766.65 174.5 3098 S[1436] -6271.05 174.5
Fo
2995 S[1359] -5271.95 294.5 3047 S[1398] -5776.35 294.5 3099 S[1437] -6280.75 294.5
2996 SX[215] -5281.65 414.5 3048 SX[202] -5786.05 414.5 3100 DUMMY -6290.45 414.5
2997 S[1360] -5291.35 54.5 3049 S[1399] -5795.75 54.5 3101 S[1438] -6300.15 54.5
2998 S[1361] -5301.05 174.5 3050 S[1400] -5805.45 174.5 3102 S[1439] -6309.85 174.5
2999 S[1362] -5310.75 294.5 3051 S[1401] -5815.15 294.5 3103 S[1440] -6319.55 294.5
3000 SX[214] -5320.45 414.5 3052 SX[201] -5824.85 414.5 3104 DUMMY -6329.25 414.5
3001 S[1363] -5330.15 54.5 3053 S[1402] -5834.55 54.5 3105 S[1441] -6338.95 54.5
3002 S[1364] -5339.85 174.5 3054 S[1403] -5844.25 174.5 3106 S[1442] -6348.65 174.5
3003 S[1365] -5349.55 294.5 3055 S[1404] -5853.95 294.5 3107 S[1443] -6358.35 294.5
3004 SX[213] -5359.25 414.5 3056 SX[200] -5863.65 414.5 3108 DUMMY -6368.05 414.5
3005 S[1366] -5368.95 54.5 3057 S[1405] -5873.35 54.5 3109 S[1444] -6377.75 54.5
3006 S[1367] -5378.65 174.5 3058 S[1406] -5883.05 174.5 3110 S[1445] -6387.45 174.5
3007 S[1368] -5388.35 294.5 3059 S[1407] -5892.75 294.5 3111 S[1446] -6397.15 294.5
3008 SX[212] -5398.05 414.5 3060 SX[199] -5902.45 414.5 3112 DUMMY -6406.85 414.5
3009 S[1369] -5407.75 54.5 3061 S[1408] -5912.15 54.5 3113 S[1447] -6416.55 54.5
3010 S[1370] -5417.45 174.5 3062 S[1409] -5921.85 174.5 3114 S[1448] -6426.25 174.5

Preliminary
FT8006S-AN
3115 S[1449] -6435.95 294.5 3167 S[1488] -6940.35 294.5 3219 S[1527] -7444.75 294.5
3116 DUMMY -6445.65 414.5 3168 SX[182] -6950.05 414.5 3220 SX[169] -7454.45 414.5
3117 S[1450] -6455.35 54.5 3169 S[1489] -6959.75 54.5 3221 S[1528] -7464.15 54.5
3118 S[1451] -6465.05 174.5 3170 S[1490] -6969.45 174.5 3222 S[1529] -7473.85 174.5
3119 S[1452] -6474.75 294.5 3171 S[1491] -6979.15 294.5 3223 S[1530] -7483.55 294.5
3120 DUMMY -6484.45 414.5 3172 SX[181] -6988.85 414.5 3224 SX[168] -7493.25 414.5
3121 S[1453] -6494.15 54.5 3173 S[1492] -6998.55 54.5 3225 S[1531] -7502.95 54.5
3122 S[1454] -6503.85 174.5 3174 S[1493] -7008.25 174.5 3226 S[1532] -7512.65 174.5
3123 S[1455] -6513.55 294.5 3175 S[1494] -7017.95 294.5 3227 S[1533] -7522.35 294.5
r
Fo
3124 DUMMY -6523.25 414.5 3176 SX[180] -7027.65 414.5 3228 SX[167] -7532.05 414.5
3125 S[1456] -6532.95 54.5 3177 S[1495] -7037.35 54.5 3229 S[1534] -7541.75 54.5
3126 S[1457] -6542.65 174.5 3178 S[1496] -7047.05 174.5 3230 S[1535] -7551.45 174.5
3127 S[1458] -6552.35 294.5 3179 S[1497] -7056.75 294.5 3231 S[1536] -7561.15 294.5
l
3128 SX[192] -6562.05 414.5 3180 SX[179] -7066.45 414.5 3232 SX[166] -7570.85 414.5
nl tia
3129 S[1459] -6571.75 54.5 3181 S[1498] -7076.15 54.5 3233 S[1537] -7580.55 54.5
3130 S[1460] -6581.45 174.5 3182 S[1499] -7085.85 174.5 3234 S[1538] -7590.25 174.5
O en
3131 S[1461] -6591.15 294.5 3183 S[1500] -7095.55 294.5 3235 S[1539] -7599.95 294.5
3132 SX[191] -6600.85 414.5 3184 SX[178] -7105.25 414.5 3236 SX[165] -7609.65 414.5
3133 S[1462] -6610.55 54.5 3185 S[1501] -7114.95 54.5 3237 S[1540] -7619.35 54.5
se id
3134 S[1463] -6620.25 174.5 3186 S[1502] -7124.65 174.5 3238 S[1541] -7629.05 174.5
y
3135 S[1464] -6629.95 294.5 3187 S[1503] -7134.35 294.5 3239 S[1542] -7638.75 294.5
U nf
3136 SX[190] -6639.65 414.5 3188 SX[177] -7144.05 414.5 3240 SX[164] -7648.45 414.5
3137 S[1465] -6649.35 54.5 3189 S[1504] -7153.75 54.5 3241 S[1543] -7658.15 54.5
o
3138 S[1466] -6659.05 174.5 3190 S[1505] -7163.45 174.5 3242 S[1544] -7667.85 174.5
3139 S[1467] -6668.75 294.5 3191 S[1506] -7173.15 294.5 3243 S[1545] -7677.55 294.5
尔 hC
3140 SX[189] -6678.45 414.5 3192 SX[176] -7182.85 414.5 3244 SX[163] -7687.25 414.5
3141 S[1468] -6688.15 54.5 3193 S[1507] -7192.55 54.5 3245 S[1546] -7696.95 54.5
3142 S[1469] -6697.85 174.5 3194 S[1508] -7202.25 174.5 3246 S[1547] -7706.65 174.5
3143 S[1470] -6707.55 294.5 3195 S[1509] -7211.95 294.5 3247 S[1548] -7716.35 294.5
韦 ec
3144 SX[188] -6717.25 414.5 3196 SX[175] -7221.65 414.5 3248 SX[162] -7726.05 414.5
3145 S[1471] -6726.95 54.5 3197 S[1510] -7231.35 54.5 3249 S[1549] -7735.75 54.5
博 lT
3146 S[1472] -6736.65 174.5 3198 S[1511] -7241.05 174.5 3250 S[1550] -7745.45 174.5
3147 S[1473] -6746.35 294.5 3199 S[1512] -7250.75 294.5 3251 S[1551] -7755.15 294.5
麦 ca
3148 SX[187] -6756.05 414.5 3200 SX[174] -7260.45 414.5 3252 SX[161] -7764.85 414.5
3149 S[1474] -6765.75 54.5 3201 S[1513] -7270.15 54.5 3253 S[1552] -7774.55 54.5
3150 S[1475] -6775.45 174.5 3202 S[1514] -7279.85 174.5 3254 S[1553] -7784.25 174.5
Fo
3151 S[1476] -6785.15 294.5 3203 S[1515] -7289.55 294.5 3255 S[1554] -7793.95 294.5
3152 SX[186] -6794.85 414.5 3204 SX[173] -7299.25 414.5 3256 DUMMY -7803.65 414.5
3153 S[1477] -6804.55 54.5 3205 S[1516] -7308.95 54.5 3257 S[1555] -7813.35 54.5
3154 S[1478] -6814.25 174.5 3206 S[1517] -7318.65 174.5 3258 S[1556] -7823.05 174.5
3155 S[1479] -6823.95 294.5 3207 S[1518] -7328.35 294.5 3259 S[1557] -7832.75 294.5
3156 SX[185] -6833.65 414.5 3208 SX[172] -7338.05 414.5 3260 DUMMY -7842.45 414.5
3157 S[1480] -6843.35 54.5 3209 S[1519] -7347.75 54.5 3261 S[1558] -7852.15 54.5
3158 S[1481] -6853.05 174.5 3210 S[1520] -7357.45 174.5 3262 S[1559] -7861.85 174.5
3159 S[1482] -6862.75 294.5 3211 S[1521] -7367.15 294.5 3263 S[1560] -7871.55 294.5
3160 SX[184] -6872.45 414.5 3212 SX[171] -7376.85 414.5 3264 DUMMY -7881.25 414.5
3161 S[1483] -6882.15 54.5 3213 S[1522] -7386.55 54.5 3265 S[1561] -7890.95 54.5
3162 S[1484] -6891.85 174.5 3214 S[1523] -7396.25 174.5 3266 S[1562] -7900.65 174.5
3163 S[1485] -6901.55 294.5 3215 S[1524] -7405.95 294.5 3267 S[1563] -7910.35 294.5
3164 SX[183] -6911.25 414.5 3216 SX[170] -7415.65 414.5 3268 DUMMY -7920.05 414.5
3165 S[1486] -6920.95 54.5 3217 S[1525] -7425.35 54.5 3269 S[1564] -7929.75 54.5
3166 S[1487] -6930.65 174.5 3218 S[1526] -7435.05 174.5 3270 S[1565] -7939.45 174.5

Preliminary
FT8006S-AN
3271 S[1566] -7949.15 294.5 3323 S[1605] -8453.55 294.5 3375 S[1644] -8957.95 294.5
3272 DUMMY -7958.85 414.5 3324 SX[150] -8463.25 414.5 3376 SX[137] -8967.65 414.5
3273 S[1567] -7968.55 54.5 3325 S[1606] -8472.95 54.5 3377 S[1645] -8977.35 54.5
3274 S[1568] -7978.25 174.5 3326 S[1607] -8482.65 174.5 3378 S[1646] -8987.05 174.5
3275 S[1569] -7987.95 294.5 3327 S[1608] -8492.35 294.5 3379 S[1647] -8996.75 294.5
3276 DUMMY -7997.65 414.5 3328 SX[149] -8502.05 414.5 3380 SX[136] -9006.45 414.5
3277 S[1570] -8007.35 54.5 3329 S[1609] -8511.75 54.5 3381 S[1648] -9016.15 54.5
3278 S[1571] -8017.05 174.5 3330 S[1610] -8521.45 174.5 3382 S[1649] -9025.85 174.5
3279 S[1572] -8026.75 294.5 3331 S[1611] -8531.15 294.5 3383 S[1650] -9035.55 294.5
r
Fo
3280 DUMMY -8036.45 414.5 3332 SX[148] -8540.85 414.5 3384 SX[135] -9045.25 414.5
3281 S[1573] -8046.15 54.5 3333 S[1612] -8550.55 54.5 3385 S[1651] -9054.95 54.5
3282 S[1574] -8055.85 174.5 3334 S[1613] -8560.25 174.5 3386 S[1652] -9064.65 174.5
3283 S[1575] -8065.55 294.5 3335 S[1614] -8569.95 294.5 3387 S[1653] -9074.35 294.5
l
3284 SX[160] -8075.25 414.5 3336 SX[147] -8579.65 414.5 3388 SX[134] -9084.05 414.5
nl tia
3285 S[1576] -8084.95 54.5 3337 S[1615] -8589.35 54.5 3389 S[1654] -9093.75 54.5
3286 S[1577] -8094.65 174.5 3338 S[1616] -8599.05 174.5 3390 S[1655] -9103.45 174.5
O en
3287 S[1578] -8104.35 294.5 3339 S[1617] -8608.75 294.5 3391 S[1656] -9113.15 294.5
3288 SX[159] -8114.05 414.5 3340 SX[146] -8618.45 414.5 3392 SX[133] -9122.85 414.5
3289 S[1579] -8123.75 54.5 3341 S[1618] -8628.15 54.5 3393 S[1657] -9132.55 54.5
se id
3290 S[1580] -8133.45 174.5 3342 S[1619] -8637.85 174.5 3394 S[1658] -9142.25 174.5
y
3291 S[1581] -8143.15 294.5 3343 S[1620] -8647.55 294.5 3395 S[1659] -9151.95 294.5
U nf
3292 SX[158] -8152.85 414.5 3344 SX[145] -8657.25 414.5 3396 SX[132] -9161.65 414.5
3293 S[1582] -8162.55 54.5 3345 S[1621] -8666.95 54.5 3397 S[1660] -9171.35 54.5
o
3294 S[1583] -8172.25 174.5 3346 S[1622] -8676.65 174.5 3398 S[1661] -9181.05 174.5
3295 S[1584] -8181.95 294.5 3347 S[1623] -8686.35 294.5 3399 S[1662] -9190.75 294.5
尔 hC
3296 SX[157] -8191.65 414.5 3348 SX[144] -8696.05 414.5 3400 SX[131] -9200.45 414.5
3297 S[1585] -8201.35 54.5 3349 S[1624] -8705.75 54.5 3401 S[1663] -9210.15 54.5
3298 S[1586] -8211.05 174.5 3350 S[1625] -8715.45 174.5 3402 S[1664] -9219.85 174.5
3299 S[1587] -8220.75 294.5 3351 S[1626] -8725.15 294.5 3403 S[1665] -9229.55 294.5
韦 ec
3300 SX[156] -8230.45 414.5 3352 SX[143] -8734.85 414.5 3404 SX[130] -9239.25 414.5
3301 S[1588] -8240.15 54.5 3353 S[1627] -8744.55 54.5 3405 S[1666] -9248.95 54.5
博 lT
3302 S[1589] -8249.85 174.5 3354 S[1628] -8754.25 174.5 3406 S[1667] -9258.65 174.5
3303 S[1590] -8259.55 294.5 3355 S[1629] -8763.95 294.5 3407 S[1668] -9268.35 294.5
麦 ca
3304 SX[155] -8269.25 414.5 3356 SX[142] -8773.65 414.5 3408 SX[129] -9278.05 414.5
3305 S[1591] -8278.95 54.5 3357 S[1630] -8783.35 54.5 3409 S[1669] -9287.75 54.5
3306 S[1592] -8288.65 174.5 3358 S[1631] -8793.05 174.5 3410 S[1670] -9297.45 174.5
Fo
3307 S[1593] -8298.35 294.5 3359 S[1632] -8802.75 294.5 3411 S[1671] -9307.15 294.5
3308 SX[154] -8308.05 414.5 3360 SX[141] -8812.45 414.5 3412 DUMMY -9316.85 414.5
3309 S[1594] -8317.75 54.5 3361 S[1633] -8822.15 54.5 3413 S[1672] -9326.55 54.5
3310 S[1595] -8327.45 174.5 3362 S[1634] -8831.85 174.5 3414 S[1673] -9336.25 174.5
3311 S[1596] -8337.15 294.5 3363 S[1635] -8841.55 294.5 3415 S[1674] -9345.95 294.5
3312 SX[153] -8346.85 414.5 3364 SX[140] -8851.25 414.5 3416 DUMMY -9355.65 414.5
3313 S[1597] -8356.55 54.5 3365 S[1636] -8860.95 54.5 3417 S[1675] -9365.35 54.5
3314 S[1598] -8366.25 174.5 3366 S[1637] -8870.65 174.5 3418 S[1676] -9375.05 174.5
3315 S[1599] -8375.95 294.5 3367 S[1638] -8880.35 294.5 3419 S[1677] -9384.75 294.5
3316 SX[152] -8385.65 414.5 3368 SX[139] -8890.05 414.5 3420 DUMMY -9394.45 414.5
3317 S[1600] -8395.35 54.5 3369 S[1639] -8899.75 54.5 3421 S[1678] -9404.15 54.5
3318 S[1601] -8405.05 174.5 3370 S[1640] -8909.45 174.5 3422 S[1679] -9413.85 174.5
3319 S[1602] -8414.75 294.5 3371 S[1641] -8919.15 294.5 3423 S[1680] -9423.55 294.5
3320 SX[151] -8424.45 414.5 3372 SX[138] -8928.85 414.5 3424 DUMMY -9433.25 414.5
3321 S[1603] -8434.15 54.5 3373 S[1642] -8938.55 54.5 3425 S[1681] -9442.95 54.5
3322 S[1604] -8443.85 174.5 3374 S[1643] -8948.25 174.5 3426 S[1682] -9452.65 174.5

Preliminary
FT8006S-AN
3427 S[1683] -9462.35 294.5 3479 S[1722] -9966.75 294.5 3531 S[1761] -10471.15 294.5
3428 DUMMY -9472.05 414.5 3480 SX[118] -9976.45 414.5 3532 SX[105] -10480.85 414.5
3429 S[1684] -9481.75 54.5 3481 S[1723] -9986.15 54.5 3533 S[1762] -10490.55 54.5
3430 S[1685] -9491.45 174.5 3482 S[1724] -9995.85 174.5 3534 S[1763] -10500.25 174.5
3431 S[1686] -9501.15 294.5 3483 S[1725] -10005.55 294.5 3535 S[1764] -10509.95 294.5
3432 DUMMY -9510.85 414.5 3484 SX[117] -10015.25 414.5 3536 SX[104] -10519.65 414.5
3433 S[1687] -9520.55 54.5 3485 S[1726] -10024.95 54.5 3537 S[1765] -10529.35 54.5
3434 S[1688] -9530.25 174.5 3486 S[1727] -10034.65 174.5 3538 S[1766] -10539.05 174.5
3435 S[1689] -9539.95 294.5 3487 S[1728] -10044.35 294.5 3539 S[1767] -10548.75 294.5
r
Fo
3436 DUMMY -9549.65 414.5 3488 SX[116] -10054.05 414.5 3540 SX[103] -10558.45 414.5
3437 S[1690] -9559.35 54.5 3489 S[1729] -10063.75 54.5 3541 S[1768] -10568.15 54.5
3438 S[1691] -9569.05 174.5 3490 S[1730] -10073.45 174.5 3542 S[1769] -10577.85 174.5
3439 S[1692] -9578.75 294.5 3491 S[1731] -10083.15 294.5 3543 S[1770] -10587.55 294.5
l
3440 SX[128] -9588.45 414.5 3492 SX[115] -10092.85 414.5 3544 SX[102] -10597.25 414.5
nl tia
3441 S[1693] -9598.15 54.5 3493 S[1732] -10102.55 54.5 3545 S[1771] -10606.95 54.5
3442 S[1694] -9607.85 174.5 3494 S[1733] -10112.25 174.5 3546 S[1772] -10616.65 174.5
O en
3443 S[1695] -9617.55 294.5 3495 S[1734] -10121.95 294.5 3547 S[1773] -10626.35 294.5
3444 SX[127] -9627.25 414.5 3496 SX[114] -10131.65 414.5 3548 SX[101] -10636.05 414.5
3445 S[1696] -9636.95 54.5 3497 S[1735] -10141.35 54.5 3549 S[1774] -10645.75 54.5
se id
3446 S[1697] -9646.65 174.5 3498 S[1736] -10151.05 174.5 3550 S[1775] -10655.45 174.5
y
3447 S[1698] -9656.35 294.5 3499 S[1737] -10160.75 294.5 3551 S[1776] -10665.15 294.5
U nf
3448 SX[126] -9666.05 414.5 3500 SX[113] -10170.45 414.5 3552 SX[100] -10674.85 414.5
3449 S[1699] -9675.75 54.5 3501 S[1738] -10180.15 54.5 3553 S[1777] -10684.55 54.5
o
3450 S[1700] -9685.45 174.5 3502 S[1739] -10189.85 174.5 3554 S[1778] -10694.25 174.5
3451 S[1701] -9695.15 294.5 3503 S[1740] -10199.55 294.5 3555 S[1779] -10703.95 294.5
尔 hC
3452 SX[125] -9704.85 414.5 3504 SX[112] -10209.25 414.5 3556 SX[99] -10713.65 414.5
3453 S[1702] -9714.55 54.5 3505 S[1741] -10218.95 54.5 3557 S[1780] -10723.35 54.5
3454 S[1703] -9724.25 174.5 3506 S[1742] -10228.65 174.5 3558 S[1781] -10733.05 174.5
3455 S[1704] -9733.95 294.5 3507 S[1743] -10238.35 294.5 3559 S[1782] -10742.75 294.5
韦 ec
3456 SX[124] -9743.65 414.5 3508 SX[111] -10248.05 414.5 3560 SX[98] -10752.45 414.5
3457 S[1705] -9753.35 54.5 3509 S[1744] -10257.75 54.5 3561 S[1783] -10762.15 54.5
博 lT
3458 S[1706] -9763.05 174.5 3510 S[1745] -10267.45 174.5 3562 S[1784] -10771.85 174.5
3459 S[1707] -9772.75 294.5 3511 S[1746] -10277.15 294.5 3563 S[1785] -10781.55 294.5
麦 ca
3460 SX[123] -9782.45 414.5 3512 SX[110] -10286.85 414.5 3564 SX[97] -10791.25 414.5
3461 S[1708] -9792.15 54.5 3513 S[1747] -10296.55 54.5 3565 S[1786] -10800.95 54.5
3462 S[1709] -9801.85 174.5 3514 S[1748] -10306.25 174.5 3566 S[1787] -10810.65 174.5
Fo
3463 S[1710] -9811.55 294.5 3515 S[1749] -10315.95 294.5 3567 S[1788] -10820.35 294.5
3464 SX[122] -9821.25 414.5 3516 SX[109] -10325.65 414.5 3568 DUMMY -10830.05 414.5
3465 S[1711] -9830.95 54.5 3517 S[1750] -10335.35 54.5 3569 S[1789] -10839.75 54.5
3466 S[1712] -9840.65 174.5 3518 S[1751] -10345.05 174.5 3570 S[1790] -10849.45 174.5
3467 S[1713] -9850.35 294.5 3519 S[1752] -10354.75 294.5 3571 S[1791] -10859.15 294.5
3468 SX[121] -9860.05 414.5 3520 SX[108] -10364.45 414.5 3572 DUMMY -10868.85 414.5
3469 S[1714] -9869.75 54.5 3521 S[1753] -10374.15 54.5 3573 S[1792] -10878.55 54.5
3470 S[1715] -9879.45 174.5 3522 S[1754] -10383.85 174.5 3574 S[1793] -10888.25 174.5
3471 S[1716] -9889.15 294.5 3523 S[1755] -10393.55 294.5 3575 S[1794] -10897.95 294.5
3472 SX[120] -9898.85 414.5 3524 SX[107] -10403.25 414.5 3576 DUMMY -10907.65 414.5
3473 S[1717] -9908.55 54.5 3525 S[1756] -10412.95 54.5 3577 S[1795] -10917.35 54.5
3474 S[1718] -9918.25 174.5 3526 S[1757] -10422.65 174.5 3578 S[1796] -10927.05 174.5
3475 S[1719] -9927.95 294.5 3527 S[1758] -10432.35 294.5 3579 S[1797] -10936.75 294.5
3476 SX[119] -9937.65 414.5 3528 SX[106] -10442.05 414.5 3580 DUMMY -10946.45 414.5
3477 S[1720] -9947.35 54.5 3529 S[1759] -10451.75 54.5 3581 S[1798] -10956.15 54.5
3478 S[1721] -9957.05 174.5 3530 S[1760] -10461.45 174.5 3582 S[1799] -10965.85 174.5

Preliminary
FT8006S-AN
3583 S[1800] -10975.55 294.5 3635 S[1839] -11479.95 294.5 3687 S[1878] -11984.35 294.5
3584 DUMMY -10985.25 414.5 3636 SX[89] -11489.65 414.5 3688 SX[76] -11994.05 414.5
3585 S[1801] -10994.95 54.5 3637 S[1840] -11499.35 54.5 3689 S[1879] -12003.75 54.5
3586 S[1802] -11004.65 174.5 3638 S[1841] -11509.05 174.5 3690 S[1880] -12013.45 174.5
3587 S[1803] -11014.35 294.5 3639 S[1842] -11518.75 294.5 3691 S[1881] -12023.15 294.5
3588 DUMMY -11024.05 414.5 3640 SX[88] -11528.45 414.5 3692 SX[75] -12032.85 414.5
3589 S[1804] -11033.75 54.5 3641 S[1843] -11538.15 54.5 3693 S[1882] -12042.55 54.5
3590 S[1805] -11043.45 174.5 3642 S[1844] -11547.85 174.5 3694 S[1883] -12052.25 174.5
3591 S[1806] -11053.15 294.5 3643 S[1845] -11557.55 294.5 3695 S[1884] -12061.95 294.5
r
Fo
3592 DUMMY -11062.85 414.5 3644 SX[87] -11567.25 414.5 3696 SX[74] -12071.65 414.5
3593 S[1807] -11072.55 54.5 3645 S[1846] -11576.95 54.5 3697 S[1885] -12081.35 54.5
3594 S[1808] -11082.25 174.5 3646 S[1847] -11586.65 174.5 3698 S[1886] -12091.05 174.5
3595 S[1809] -11091.95 294.5 3647 S[1848] -11596.35 294.5 3699 S[1887] -12100.75 294.5
l
3596 DUMMY -11101.65 414.5 3648 SX[86] -11606.05 414.5 3700 SX[73] -12110.45 414.5
nl tia
3597 S[1810] -11111.35 54.5 3649 S[1849] -11615.75 54.5 3701 S[1888] -12120.15 54.5
3598 S[1811] -11121.05 174.5 3650 S[1850] -11625.45 174.5 3702 S[1889] -12129.85 174.5
O en
3599 S[1812] -11130.75 294.5 3651 S[1851] -11635.15 294.5 3703 S[1890] -12139.55 294.5
3600 DUMMY -11140.45 414.5 3652 SX[85] -11644.85 414.5 3704 SX[72] -12149.25 414.5
3601 S[1813] -11150.15 54.5 3653 S[1852] -11654.55 54.5 3705 S[1891] -12158.95 54.5
se id
3602 S[1814] -11159.85 174.5 3654 S[1853] -11664.25 174.5 3706 S[1892] -12168.65 174.5
y
3603 S[1815] -11169.55 294.5 3655 S[1854] -11673.95 294.5 3707 S[1893] -12178.35 294.5
U nf
3604 DUMMY -11179.25 414.5 3656 SX[84] -11683.65 414.5 3708 SX[71] -12188.05 414.5
3605 S[1816] -11188.95 54.5 3657 S[1855] -11693.35 54.5 3709 S[1894] -12197.75 54.5
o
3606 S[1817] -11198.65 174.5 3658 S[1856] -11703.05 174.5 3710 S[1895] -12207.45 174.5
3607 S[1818] -11208.35 294.5 3659 S[1857] -11712.75 294.5 3711 S[1896] -12217.15 294.5
尔 hC
3608 SX[96] -11218.05 414.5 3660 SX[83] -11722.45 414.5 3712 SX[70] -12226.85 414.5
3609 S[1819] -11227.75 54.5 3661 S[1858] -11732.15 54.5 3713 S[1897] -12236.55 54.5
3610 S[1820] -11237.45 174.5 3662 S[1859] -11741.85 174.5 3714 S[1898] -12246.25 174.5
3611 S[1821] -11247.15 294.5 3663 S[1860] -11751.55 294.5 3715 S[1899] -12255.95 294.5
韦 ec
3612 SX[95] -11256.85 414.5 3664 SX[82] -11761.25 414.5 3716 SX[69] -12265.65 414.5
3613 S[1822] -11266.55 54.5 3665 S[1861] -11770.95 54.5 3717 S[1900] -12275.35 54.5
博 lT
3614 S[1823] -11276.25 174.5 3666 S[1862] -11780.65 174.5 3718 S[1901] -12285.05 174.5
3615 S[1824] -11285.95 294.5 3667 S[1863] -11790.35 294.5 3719 S[1902] -12294.75 294.5
麦 ca
3616 SX[94] -11295.65 414.5 3668 SX[81] -11800.05 414.5 3720 SX[68] -12304.45 414.5
3617 S[1825] -11305.35 54.5 3669 S[1864] -11809.75 54.5 3721 S[1903] -12314.15 54.5
3618 S[1826] -11315.05 174.5 3670 S[1865] -11819.45 174.5 3722 S[1904] -12323.85 174.5
Fo
3619 S[1827] -11324.75 294.5 3671 S[1866] -11829.15 294.5 3723 S[1905] -12333.55 294.5
3620 SX[93] -11334.45 414.5 3672 SX[80] -11838.85 414.5 3724 SX[67] -12343.25 414.5
3621 S[1828] -11344.15 54.5 3673 S[1867] -11848.55 54.5 3725 S[1906] -12352.95 54.5
3622 S[1829] -11353.85 174.5 3674 S[1868] -11858.25 174.5 3726 S[1907] -12362.65 174.5
3623 S[1830] -11363.55 294.5 3675 S[1869] -11867.95 294.5 3727 S[1908] -12372.35 294.5
3624 SX[92] -11373.25 414.5 3676 SX[79] -11877.65 414.5 3728 SX[66] -12382.05 414.5
3625 S[1831] -11382.95 54.5 3677 S[1870] -11887.35 54.5 3729 S[1909] -12391.75 54.5
3626 S[1832] -11392.65 174.5 3678 S[1871] -11897.05 174.5 3730 S[1910] -12401.45 174.5
3627 S[1833] -11402.35 294.5 3679 S[1872] -11906.75 294.5 3731 S[1911] -12411.15 294.5
3628 SX[91] -11412.05 414.5 3680 SX[78] -11916.45 414.5 3732 SX[65] -12420.85 414.5
3629 S[1834] -11421.75 54.5 3681 S[1873] -11926.15 54.5 3733 S[1912] -12430.55 54.5
3630 S[1835] -11431.45 174.5 3682 S[1874] -11935.85 174.5 3734 S[1913] -12440.25 174.5
3631 S[1836] -11441.15 294.5 3683 S[1875] -11945.55 294.5 3735 S[1914] -12449.95 294.5
3632 SX[90] -11450.85 414.5 3684 SX[77] -11955.25 414.5 3736 DUMMY -12459.65 414.5
3633 S[1837] -11460.55 54.5 3685 S[1876] -11964.95 54.5 3737 S[1915] -12469.35 54.5
3634 S[1838] -11470.25 174.5 3686 S[1877] -11974.65 174.5 3738 S[1916] -12479.05 174.5

Preliminary
FT8006S-AN
3739 S[1917] -12488.75 294.5 3791 S[1956] -12993.15 294.5 3843 S[1995] -13497.55 294.5
3740 DUMMY -12498.45 414.5 3792 SX[57] -13002.85 414.5 3844 SX[44] -13507.25 414.5
3741 S[1918] -12508.15 54.5 3793 S[1957] -13012.55 54.5 3845 S[1996] -13516.95 54.5
3742 S[1919] -12517.85 174.5 3794 S[1958] -13022.25 174.5 3846 S[1997] -13526.65 174.5
3743 S[1920] -12527.55 294.5 3795 S[1959] -13031.95 294.5 3847 S[1998] -13536.35 294.5
3744 DUMMY -12537.25 414.5 3796 SX[56] -13041.65 414.5 3848 SX[43] -13546.05 414.5
3745 S[1921] -12546.95 54.5 3797 S[1960] -13051.35 54.5 3849 S[1999] -13555.75 54.5
3746 S[1922] -12556.65 174.5 3798 S[1961] -13061.05 174.5 3850 S[2000] -13565.45 174.5
3747 S[1923] -12566.35 294.5 3799 S[1962] -13070.75 294.5 3851 S[2001] -13575.15 294.5
r
Fo
3748 DUMMY -12576.05 414.5 3800 SX[55] -13080.45 414.5 3852 SX[42] -13584.85 414.5
3749 S[1924] -12585.75 54.5 3801 S[1963] -13090.15 54.5 3853 S[2002] -13594.55 54.5
3750 S[1925] -12595.45 174.5 3802 S[1964] -13099.85 174.5 3854 S[2003] -13604.25 174.5
3751 S[1926] -12605.15 294.5 3803 S[1965] -13109.55 294.5 3855 S[2004] -13613.95 294.5
l
3752 DUMMY -12614.85 414.5 3804 SX[54] -13119.25 414.5 3856 SX[41] -13623.65 414.5
nl tia
3753 S[1927] -12624.55 54.5 3805 S[1966] -13128.95 54.5 3857 S[2005] -13633.35 54.5
3754 S[1928] -12634.25 174.5 3806 S[1967] -13138.65 174.5 3858 S[2006] -13643.05 174.5
O en
3755 S[1929] -12643.95 294.5 3807 S[1968] -13148.35 294.5 3859 S[2007] -13652.75 294.5
3756 DUMMY -12653.65 414.5 3808 SX[53] -13158.05 414.5 3860 SX[40] -13662.45 414.5
3757 S[1930] -12663.35 54.5 3809 S[1969] -13167.75 54.5 3861 S[2008] -13672.15 54.5
se id
3758 S[1931] -12673.05 174.5 3810 S[1970] -13177.45 174.5 3862 S[2009] -13681.85 174.5
y
3759 S[1932] -12682.75 294.5 3811 S[1971] -13187.15 294.5 3863 S[2010] -13691.55 294.5
U nf
3760 DUMMY -12692.45 414.5 3812 SX[52] -13196.85 414.5 3864 SX[39] -13701.25 414.5
3761 S[1933] -12702.15 54.5 3813 S[1972] -13206.55 54.5 3865 S[2011] -13710.95 54.5
o
3762 S[1934] -12711.85 174.5 3814 S[1973] -13216.25 174.5 3866 S[2012] -13720.65 174.5
3763 S[1935] -12721.55 294.5 3815 S[1974] -13225.95 294.5 3867 S[2013] -13730.35 294.5
尔 hC
3764 SX[64] -12731.25 414.5 3816 SX[51] -13235.65 414.5 3868 SX[38] -13740.05 414.5
3765 S[1936] -12740.95 54.5 3817 S[1975] -13245.35 54.5 3869 S[2014] -13749.75 54.5
3766 S[1937] -12750.65 174.5 3818 S[1976] -13255.05 174.5 3870 S[2015] -13759.45 174.5
3767 S[1938] -12760.35 294.5 3819 S[1977] -13264.75 294.5 3871 S[2016] -13769.15 294.5
韦 ec
3768 SX[63] -12770.05 414.5 3820 SX[50] -13274.45 414.5 3872 SX[37] -13778.85 414.5
3769 S[1939] -12779.75 54.5 3821 S[1978] -13284.15 54.5 3873 S[2017] -13788.55 54.5
博 lT
3770 S[1940] -12789.45 174.5 3822 S[1979] -13293.85 174.5 3874 S[2018] -13798.25 174.5
3771 S[1941] -12799.15 294.5 3823 S[1980] -13303.55 294.5 3875 S[2019] -13807.95 294.5
麦 ca
3772 SX[62] -12808.85 414.5 3824 SX[49] -13313.25 414.5 3876 SX[36] -13817.65 414.5
3773 S[1942] -12818.55 54.5 3825 S[1981] -13322.95 54.5 3877 S[2020] -13827.35 54.5
3774 S[1943] -12828.25 174.5 3826 S[1982] -13332.65 174.5 3878 S[2021] -13837.05 174.5
Fo
3775 S[1944] -12837.95 294.5 3827 S[1983] -13342.35 294.5 3879 S[2022] -13846.75 294.5
3776 SX[61] -12847.65 414.5 3828 SX[48] -13352.05 414.5 3880 SX[35] -13856.45 414.5
3777 S[1945] -12857.35 54.5 3829 S[1984] -13361.75 54.5 3881 S[2023] -13866.15 54.5
3778 S[1946] -12867.05 174.5 3830 S[1985] -13371.45 174.5 3882 S[2024] -13875.85 174.5
3779 S[1947] -12876.75 294.5 3831 S[1986] -13381.15 294.5 3883 S[2025] -13885.55 294.5
3780 SX[60] -12886.45 414.5 3832 SX[47] -13390.85 414.5 3884 SX[34] -13895.25 414.5
3781 S[1948] -12896.15 54.5 3833 S[1987] -13400.55 54.5 3885 S[2026] -13904.95 54.5
3782 S[1949] -12905.85 174.5 3834 S[1988] -13410.25 174.5 3886 S[2027] -13914.65 174.5
3783 S[1950] -12915.55 294.5 3835 S[1989] -13419.95 294.5 3887 S[2028] -13924.35 294.5
3784 SX[59] -12925.25 414.5 3836 SX[46] -13429.65 414.5 3888 SX[33] -13934.05 414.5
3785 S[1951] -12934.95 54.5 3837 S[1990] -13439.35 54.5 3889 S[2029] -13943.75 54.5
3786 S[1952] -12944.65 174.5 3838 S[1991] -13449.05 174.5 3890 S[2030] -13953.45 174.5
3787 S[1953] -12954.35 294.5 3839 S[1992] -13458.75 294.5 3891 S[2031] -13963.15 294.5
3788 SX[58] -12964.05 414.5 3840 SX[45] -13468.45 414.5 3892 DUMMY -13972.85 414.5
3789 S[1954] -12973.75 54.5 3841 S[1993] -13478.15 54.5 3893 S[2032] -13982.55 54.5
3790 S[1955] -12983.45 174.5 3842 S[1994] -13487.85 174.5 3894 S[2033] -13992.25 174.5

Preliminary
FT8006S-AN
3895 S[2034] -14001.95 294.5 3947 S[2073] -14506.35 294.5 3999 S[2112] -15010.75 294.5
3896 DUMMY -14011.65 414.5 3948 SX[25] -14516.05 414.5 4000 SX[12] -15020.45 414.5
3897 S[2035] -14021.35 54.5 3949 S[2074] -14525.75 54.5 4001 S[2113] -15030.15 54.5
3898 S[2036] -14031.05 174.5 3950 S[2075] -14535.45 174.5 4002 S[2114] -15039.85 174.5
3899 S[2037] -14040.75 294.5 3951 S[2076] -14545.15 294.5 4003 S[2115] -15049.55 294.5
3900 DUMMY -14050.45 414.5 3952 SX[24] -14554.85 414.5 4004 SX[11] -15059.25 414.5
3901 S[2038] -14060.15 54.5 3953 S[2077] -14564.55 54.5 4005 S[2116] -15068.95 54.5
3902 S[2039] -14069.85 174.5 3954 S[2078] -14574.25 174.5 4006 S[2117] -15078.65 174.5
3903 S[2040] -14079.55 294.5 3955 S[2079] -14583.95 294.5 4007 S[2118] -15088.35 294.5
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3904 DUMMY -14089.25 414.5 3956 SX[23] -14593.65 414.5 4008 SX[10] -15098.05 414.5
3905 S[2041] -14098.95 54.5 3957 S[2080] -14603.35 54.5 4009 S[2119] -15107.75 54.5
3906 S[2042] -14108.65 174.5 3958 S[2081] -14613.05 174.5 4010 S[2120] -15117.45 174.5
3907 S[2043] -14118.35 294.5 3959 S[2082] -14622.75 294.5 4011 S[2121] -15127.15 294.5
l
3908 DUMMY -14128.05 414.5 3960 SX[22] -14632.45 414.5 4012 SX[9] -15136.85 414.5
nl tia
3909 S[2044] -14137.75 54.5 3961 S[2083] -14642.15 54.5 4013 S[2122] -15146.55 54.5
3910 S[2045] -14147.45 174.5 3962 S[2084] -14651.85 174.5 4014 S[2123] -15156.25 174.5
O en
3911 S[2046] -14157.15 294.5 3963 S[2085] -14661.55 294.5 4015 S[2124] -15165.95 294.5
3912 DUMMY -14166.85 414.5 3964 SX[21] -14671.25 414.5 4016 SX[8] -15175.65 414.5
3913 S[2047] -14176.55 54.5 3965 S[2086] -14680.95 54.5 4017 S[2125] -15185.35 54.5
se id
3914 S[2048] -14186.25 174.5 3966 S[2087] -14690.65 174.5 4018 S[2126] -15195.05 174.5
y
3915 S[2049] -14195.95 294.5 3967 S[2088] -14700.35 294.5 4019 S[2127] -15204.75 294.5
U nf
3916 DUMMY -14205.65 414.5 3968 SX[20] -14710.05 414.5 4020 SX[7] -15214.45 414.5
3917 S[2050] -14215.35 54.5 3969 S[2089] -14719.75 54.5 4021 S[2128] -15224.15 54.5
o
3918 S[2051] -14225.05 174.5 3970 S[2090] -14729.45 174.5 4022 S[2129] -15233.85 174.5
3919 S[2052] -14234.75 294.5 3971 S[2091] -14739.15 294.5 4023 S[2130] -15243.55 294.5
尔 hC
3920 SX[32] -14244.45 414.5 3972 SX[19] -14748.85 414.5 4024 SX[6] -15253.25 414.5
3921 S[2053] -14254.15 54.5 3973 S[2092] -14758.55 54.5 4025 S[2131] -15262.95 54.5
3922 S[2054] -14263.85 174.5 3974 S[2093] -14768.25 174.5 4026 S[2132] -15272.65 174.5
3923 S[2055] -14273.55 294.5 3975 S[2094] -14777.95 294.5 4027 S[2133] -15282.35 294.5
韦 ec
3924 SX[31] -14283.25 414.5 3976 SX[18] -14787.65 414.5 4028 SX[5] -15292.05 414.5
3925 S[2056] -14292.95 54.5 3977 S[2095] -14797.35 54.5 4029 S[2134] -15301.75 54.5
博 lT
3926 S[2057] -14302.65 174.5 3978 S[2096] -14807.05 174.5 4030 S[2135] -15311.45 174.5
3927 S[2058] -14312.35 294.5 3979 S[2097] -14816.75 294.5 4031 S[2136] -15321.15 294.5
麦 ca
3928 SX[30] -14322.05 414.5 3980 SX[17] -14826.45 414.5 4032 SX[4] -15330.85 414.5
3929 S[2059] -14331.75 54.5 3981 S[2098] -14836.15 54.5 4033 S[2137] -15340.55 54.5
3930 S[2060] -14341.45 174.5 3982 S[2099] -14845.85 174.5 4034 S[2138] -15350.25 174.5
Fo
3931 S[2061] -14351.15 294.5 3983 S[2100] -14855.55 294.5 4035 S[2139] -15359.95 294.5
3932 SX[29] -14360.85 414.5 3984 SX[16] -14865.25 414.5 4036 SX[3] -15369.65 414.5
3933 S[2062] -14370.55 54.5 3985 S[2101] -14874.95 54.5 4037 S[2140] -15379.35 54.5
3934 S[2063] -14380.25 174.5 3986 S[2102] -14884.65 174.5 4038 S[2141] -15389.05 174.5
3935 S[2064] -14389.95 294.5 3987 S[2103] -14894.35 294.5 4039 S[2142] -15398.75 294.5
3936 SX[28] -14399.65 414.5 3988 SX[15] -14904.05 414.5 4040 SX[2] -15408.45 414.5
3937 S[2065] -14409.35 54.5 3989 S[2104] -14913.75 54.5 4041 S[2143] -15418.15 54.5
3938 S[2066] -14419.05 174.5 3990 S[2105] -14923.45 174.5 4042 S[2144] -15427.85 174.5
3939 S[2067] -14428.75 294.5 3991 S[2106] -14933.15 294.5 4043 S[2145] -15437.55 294.5
3940 SX[27] -14438.45 414.5 3992 SX[14] -14942.85 414.5 4044 SX[1] -15447.25 414.5
3941 S[2068] -14448.15 54.5 3993 S[2107] -14952.55 54.5 4045 S[2146] -15456.95 54.5
3942 S[2069] -14457.85 174.5 3994 S[2108] -14962.25 174.5 4046 S[2147] -15466.65 174.5
3943 S[2070] -14467.55 294.5 3995 S[2109] -14971.95 294.5 4047 S[2148] -15476.35 294.5
3944 SX[26] -14477.25 414.5 3996 SX[13] -14981.65 414.5 4048 DUMMY -15486.05 414.5
3945 S[2071] -14486.95 54.5 3997 S[2110] -14991.35 54.5 4049 S[2149] -15495.75 54.5
3946 S[2072] -14496.65 174.5 3998 S[2111] -15001.05 174.5 4050 S[2150] -15505.45 174.5

Preliminary
FT8006S-AN
4051 S[2151] -15515.15 294.5 4065 SDUM[2] -15650.95 54.5 4079 VCOM_PASS_L -15786.75 294.5
4052 DUMMY -15524.85 414.5 4066 SDUM[3] -15660.65 174.5 4080 DUMMY -15796.45 414.5
4053 S[2152] -15534.55 54.5 4067 DUMMY -15670.35 294.5 4081 DUMMY -15806.15 54.5
4054 S[2153] -15544.25 174.5 4068 SXDUM[2] -15680.05 414.5 4082 DUMMY -15815.85 174.5
4055 S[2154] -15553.95 294.5 4069 DUMMY -15689.75 54.5 4083 DUMMY -15825.55 294.5
4057 S[2155] -15573.35 54.5 4071 DUMMY -15709.15 294.5 4085 DUMMY -15844.95 54.5
4058 S[2156] -15583.05 174.5 4072 DUMMY -15718.85 414.5 4086 DUMMY -15854.65 174.5
4059 S[2157] -15592.75 294.5 4073 VCOM_PASS_L -15728.55 54.5 4087 DUMMY -15864.35 294.5
r
Fo
4060 DUMMY -15602.45 414.5 4074 VCOM_PASS_L -15738.25 174.5 4088 DUMMY -15874.05 414.5
4062 S[2159] -15621.85 174.5 4076 DUMMY -15757.65 414.5 4090 DUMMY -15893.45 174.5
l
4064 DUMMY -15641.25 414.5 4078 VCOM_PASS_L -15777.05 174.5
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Preliminary
FT8006S-AN
9.4 Alignment Mark
--Alignment Mark coordinate
Upon Left (-15969.4, 442)
Upon Right (15969.4, 442)
--Alignment Mark size
20um
r
20um 25um 25um 25um 20um
Fo
25um
25um 20um
(-15969.4, 442)
25um
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25um
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20um 25um
(15969.4, 442)
25um
O en
20um 25um 25um 25um 20um 20um
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Preliminary
FT8006S-AN
10 DISCLAIMER
The information appearing in this publication is believed to be accurate.
Integrated circuits sold by FocalTech Systems are covered by the warranty and patent indemnification provisions stipulated in the terms of
sale only. FocalTech Systems makes no warranty, express, statutory implied or by description regarding the information in this publication
or regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, FocalTech Systems MAKES NO
WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. FocalTech Systems reserves the right to halt production or
alter the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other
information in this publication are current before placing orders. Products described herein are intended for use in normal commercial
applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support
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Fo
equipment, are specifically not recommended without additional processing by FocalTech Systems for such applications. Please note that
application circuits illustrated in this document are for reference purposes only.
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Preliminary
FT8006S-AN
11 REVISION HISTORY
Date Revision # Description Page Auditor
OCT. 20, 2020 0.1 Original 132 Frank Huang
Modifty Pin descriptions 10,

APR. 29, 2021 0.2 Modifty Power block diagram 13, Frank Huang
Modifty Pad ring 102,104, 106
Modify Power On/Off Sequence 111~113
Modify NVM program flow 89~90
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MAY. 21, 2021 0.3 Frank Huang
Modify Pin description 11~14
Fo
Add TP Festure Chapter 7 91~99
Modify NVM program flow 89~90
MAY. 24, 2021 0.3 Modify Application Circuit 16 CJ
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Modify Pin description 11~14
Modify I2C interface characteristics (THD;DATA) 104
JUN. 30, 2021 0.4 Brian Hsu
Modify SPI interface characteristics (TLS1,TLS2) 105
O en
JUL. 27, 2021 0.5 Modify Pin Definition 13 Brian Hsu
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DATA SHEET FT8006S-AN v05 麦博韦尔

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DATA SHEET FT8006S-AN v05 麦博韦尔

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DATA SHEET

Super In-Cell IC Integrates TFT LCD

Driver and Touch Panel Controller

Into a Single Chip for Amorphous

Support Real Multi-Touch

1. GENERAL DESCRIPTION ....................................................................................................................................................................... 6

3. BLOCK DIAGRAM ................................................................................................................................................................................... 8

3.1.2. SX driver circuit .................................................................................................................................................................. 9

3.1.3. AFE Controller ..................................................................................................................................................................... 9

3.1.5. I2C serial interface .............................................................................................................................................................. 9

3.1.7. Watch Dog ........................................................................................................................................................................... 9

3.1.9. Source driver circuit ........................................................................................................................................................... 9

3.1.10. Gate driver circuit ............................................................................................................................................................. 10

3.1.11. Grayscale voltage generating circuit .............................................................................................................................. 10

3.1.12. Oscillator (OSC) ................................................................................................................................................................ 10

3.1.13. LCD driving power supply circuit.................................................................................................................................... 10

4. PIN DESCRIPTIONS .............................................................................................................................................................................. 11

4.1. Pin Definition ................................................................................................................................................................................... 11

4.3. Power Supply Configuration............................................................................................................................................................ 15

5.1.1 System function command list and description ............................................................................................................................... 17

5.2 System Function Command Description ......................................................................................................................................... 19

5.2.2 BIST_MODE (02H): Enter BIST mode ................................................................................................................................ 20

5.2.3 RDDPM (0AH): Read Display Power Mode ........................................................................................................................ 21

5.2.5 DEEP_STBY (17H/18H) : Enter Deep Standby Mode ........................................................................................................ 24

5.2.6 DISPLAY_CTRL (28H/29H) : Display Control ..................................................................................................................... 25

5.2.7 OTP_STOP_RELOAD (41H/4EH): OTP Stop Reload Enable ............................................................................................ 27

5.2.8 EXT_ADR (42H): Extended Address of Command Interface ............................................................................................. 28

5.2.9 OTP_CTRL_STATUS (48H): OTP Control & Status ........................................................................................................... 29

5.2.10 FSC_CTRL (4AH/4BH) : MIPI FSC Function Control ......................................................................................................... 30

© FocalTech Technology Co., Ltd. 2 JUL. 27, 2021

5.2.12 DISBV_RD (52H/53H): Read Display Brightness Value ..................................................................................................... 32

5.2.13 DISBV_CTRL (53H): Display Brightness Value Control...................................................................................................... 33

5.2.14 RDDISBV_CTRL (54H): Read Display Brightness Value Control ....................................................................................... 34

5.2.17 OTP_PROG (58H/59H/5AH) : OTP Program ..................................................................................................................... 37

6.2.1 General description ............................................................................................................................................................. 46

6.2.2 Interface level communication ............................................................................................................................................ 46

6.2.3 DSI data lanes .................................................................................................................................................................... 52

6.2.4 Packet level communication ............................................................................................................................................... 62

6.2.5 Customer-defined generic read data type format ............................................................................................................... 73

6.3. I2C-Bus Interface ............................................................................................................................................................................ 74

6.3.1. Characteristics of I2C-bus................................................................................................................................................... 74

6.3.2. System configuration .......................................................................................................................................................... 74

6.3.3. Bit transfer ........................................................................................................................................................................... 74

6.3.4. START and STOP conditions .............................................................................................................................................. 75

6.3.5. Acknowledgment ................................................................................................................................................................. 75

6.4. Power Level Definition.................................................................................................................................................................. 76

6.4.1. Power level ......................................................................................................................................................................... 76

6.4.2. Power flow chart ................................................................................................................................................................. 76

6.5. Tear Effect Information ................................................................................................................................................................. 77

6.5.1.1. Tearing effect line models ................................................................................................................................................... 77

6.5.1.2. Tearing effect line timing ..................................................................................................................................................... 78

6.5.1.3. Example 1 MCU write is faster then panel read .................................................................................................................. 79

6.5.1.4. Example 1 MCU write is slower then panel read ................................................................................................................ 80

6.5.2. Tearing effect bus trigger .................................................................................................................................................... 81

6.5.2.1. Tearing effect bus trigger enable ......................................................................................................................................... 82

6.5.2.2. Tearing effect bus trigger disable ........................................................................................................................................ 83

6.5.2.3. Tearing effect bus trigger sequences .................................................................................................................................. 84

© FocalTech Technology Co., Ltd. 3 JUL. 27, 2021

7. TP FUNCTION DESCRIPTION ...................................................................................................................................................................... 91

7.7.2 Host Read Data from Slave................................................................................................................................................... 94

7.9.3 Host Read Data from Slave ................................................................................................................................................ 96

7.11 CTPM Register Map ...................................................................................................................................................................... 97

7.11.2 DEVICE_MODE .................................................................................................................................................................. 98