SYSTEM VERILOG

Statements within a program block (scheduled in the Reactive region) that are sensitive to changes in design signals declared in
modules (scheduled in the active region), as active region is scheduled before the reactive region this avoids the race condition
between testbench and design.

The syntax for the program block is,

program test (input clk, input [7:0] addr, output [7:0] wdata);
...
endprogram

Program block,
 can be instantiated and ports can be connected same as module.
 can contain one or more initial blocks.
 cannot contain always blocks, modules, interfaces, or other programs.
 In program variables can only be assigned using blocking assignments. Using non-blocking assignments with in the program
shall be an error.

5. INTERFACE:
Interface construct are used to connect the design and testbench.
 An interface is a named bundle of wires, aim of the interfaces is to encapsulate communication.
 Also specifies the,
 directional information, i.e. modports
 timing information, i.e. clocking blocks
 An interface can have parameters, constants, variables, functions and tasks.
 modports and clocking blocks are explained in later chapters.
 A simple interface declaration is,

interface interface_name;
...
interface_items
...
endinterface

 An interface can be instantiated hierarchically like a module, with or without ports.

interface_name inst_name;
 Interface can have parameters, constants, variables, functions and tasks.
Advantages of interface over the traditional connection,
 allows number of signals to be grouped together and represented as a single port, single port handle is passed instead of
multiple signal/ports.
 interface declaration is made once and the handle is passed across the modules/components.
 addition and deletion of signals is easy.

6. Virtual interface:
A virtual interface is a variable that represents an interface instance.
Syntax:
virtual interface_name instance_name;
example:
virtual mem_intf intf;

 Virtual interface must be initialized before using it. i.e., Virtual interface must be connected/pointed to the actual interface.
 accessing the uninitialized virtual interface result in a run-time fatal error.
 Virtual interfaces can be declared as class properties, which can be initialized procedural or by an argument to new().
 Virtual interface variables can be passed as arguments to the tasks, functions, or methods.
 All the interface variables/Methods can be accessed via virtual interface handle. i.e virtual_interface.variable
7. mod ports:
Modport groups and specifies the port directions to the wires/signals declared within in the interface.
By specifying the port directions, modport provides access restrictions.
The keyword modport indicates that the directions are declared as inside the module.

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