Course Name: Digital Design and Programming

Lab No: B38DB Lab 5

Lab Name: Implementation of ALU operation
using simple data path Verilog
Student Name: Ong Jing Yi (H00416422)
Date of submission: 16/12/2022

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Lab summary/ Purpose

- What is implemented in this lab?

This lab can be implemented by using the 7-segment display and simple CPU that have been
created in Lab 4. This lab can be accomplished using three equations which are the power
equation, P=I^2*R, cube of a number, x^3, and surface area of a cuboid, 2*(LB+BH+HL).
Moreover, the main Verilog codes for lab 5 were bcd and combination with the lab4 Verilog
codes, which are the ALU, Mux, Reg created a simple central processing unit (CPU) for
conducting the arithmetic computations. Therefore, verification of the operations by varying
the conducting lines is the aim of this lab.

- How does this lab compare to the previous labs and how does it build on those?
In lab 1, we have compiled the Verilog codes with 4 inputs to produce 1 output, as proved by
the simulation waveform. K-map and the derived logic expression derived are shown to
match the outputs on the truth tables. In lab2, we assigned pins on the FPGA board. We also
implicated the switches and observed the output responses via the LED lights, and the results
met the original design specifications. In lab 3, we designed the structural model of a Half
Adder, Full Adder and combination of four Full Adder. Lab 5 is more challenging than Lab
4. In lab 4, we combine the given ALU, Mux, and register codes to form complete lab 4
Verilog codes for compilation. Then, we carried out two operations by varying the control
lines. After compilation of the codes and simulation of the waveform, double-check the
process tables. We can complete Lab 5 because we have these fundamental
knowledges.However, in Lab 5, we must identify the three equations provided by the
procedure and perform simple operations by manipulating the control lines.

- Concepts learned and implemented in this lab.

The concepts learned in this lab are designed to improve our understanding of the simple data
path concept and its implications for the Quartus software. By forming a complete Verilog
code, obtaining the given codes of bcd from Canvas and acquiring the codes from previous
lab 4, which are the ALU, Mux, and Register codes, it is crucial to compile successfully in
this lab. Furthermore, deciding the specific values to identify the operations by referring to
those equations plays a significant role in completing the operation tables. For example, 110
in the ALU op indicates multiplication of WrA with WrB. The binary number 001 in Bus
Mux indicates 1 and will be carried out to register for temporary storage. As a result, the
tables are necessary to demonstrate where the data will flow to which components to form
complete equations. Besides, the waveform should be edited according to the table so that the
timing diagram results are proportional to the table formed. In a nutshell, we learned how to
programme, design, and test a simple data path in the last lab. This lab aims to implement
meaningful but simple mathematical equations to highlight some applications of this simple
data path.

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Explanation

What is Data Path, where is it found, how does it work?

Data path is a collection of functional units that carry out data processing operations, such as
ALU, registers and multiplexer and internal buses. Data path can be found at the central
processing unit (CPU) of a computing system. By using those Verilog codes given from the
sources, it will create a data path to carry out the data operations of the high-level state
machine. Therefore, the operations can be justified by observing and varying the control
lines. Data path also works as bit shifting to right and left, addition, subtraction and other
arithmetic operations.

- What are the components of Data Path, how do they interact?

Data Path consists of register, multiplexer (bus selector), and arithmetic logic unit (ALU).
Register is a temporary storage component to store temporary data sent by the memory unit
until the command for the next data is carried out. Besides, an ALU is a digital circuit that
provides simple arithmetic and logic operations. The output of the ALU will be stored in the
register. Moreover, a bus selector (MUX) is used to select data paths to carry data.

- What is the relation of a Data Path to ALU?

ALU control accepts inputs and generates a write signal for each state element and the
control signals for each multiplexer. For all instruction classes, there are just 8 ALU Op
codes that can be used. However, it never performs more than one function at once.
Therefore, the ALU control should be implemented using a simple logic data path. This is an
essential phase in the implementation process since the control unit is essential to data path
performance. Simple logic data path can thereby lower hardware costs and boost control
speed.

- What is the relation of a Data Path to a Controller and how are they integrated to make a
Processor (briefly)?
Processors are made up by two main components which are the controller and data path. The
relationship between them is like ‘employer and staff relationship’. The controller acts as an
employer by instructing the data path how to proceed in accordance with the commands in
the running programme. Whereas data path plays a role of a staff to undergo arithmetic
computations. Data paths have a register file for storing data, whose outputs are attached to
an ALU's inputs (arithmetic logic unit). Because of this, a controller can complete a particular
computation by reading values from the register file and instructing the ALU to carry out a
certain action.

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Implementation Details and Results

Verilog code

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5
1.Power equation, P= (I^2)*R
Reg[3]=Reg[1]^2*Reg[2], Reg[1]=Reg[1]* Reg[1]; Where R1=1 and R2=4

Cycle WA RA RW BS WrA WrB ALU Op Comments

1 001 0 001 Reg[1]=1
2 001 1 100 1 A=Reg[1]=1
3 001 1 100 1 B=Reg[1]=1
4 001 0 101 0 0 110 Reg[1]=1*1
5 010 0 011 Reg[2]=4
6 010 1 100 1 B=Reg[2]=4
7 001 1 100 1 A=Reg[1]= 1^2
8 011 0 101 0 0 110 Reg[3]=(1^2)*4

Simulation waveform

Timing diagram

Comments- Based on the ALU out, the final binary value is 00000100. By converting into
decimal, it known as 4. Based on the display drive, the final binary value is 10000000011001.
The value should be separate into two and complement it to become 0111111 and 1100110 as

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it is active low. By referring to the Verilog code in the bcd.v, it will transform into 04. This
value is proven by both verification methods as 4 is the same with the process table.

2.Cube of a number, x^3

X=2

Reg[3]=Reg[2]*Reg[1], Reg[2]=Reg[1]*Reg[1],where Reg[1]=2

Cycle WA RA RW BS WrA WrB ALU Op Comments

1 001 0 010 Reg[1]=2
2 001 1 100 1 A=Reg[1]=2
3 001 1 100 1 B=Reg[1]=2
4 010 0 101 0 0 110 Reg[2]=2*2
5 001 1 100 1 A=Reg[1]=2
6 010 1 100 1 B=Reg[2]=4
7 011 0 101 110 Reg[3]=4*2

Simulation waveform

Timing diagram

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Comments- Based on the ALU out, the final binary value is 00001000. By converting into
decimal, it known as 8. Based on the display drive, the final binary value is 10000000000000.
The value should be separate into two and complement it to become 0111111 and 1111111 as
it is active low. By referring to the Verilog code in the bcd.v, it will transform into 08. This
value is proven by both verification methods as 8 is the same with the process table.

3. Surface area of a cuboid = 2* (LB + BH + HL)

Length= 2 Breadth=2 Height= 4
Reg[1]=2 Reg[2]=2 Reg[3]=4
Reg[4]=Reg[1]*Reg[2] Reg[5]=Reg[1]*Reg[3] Reg[6]=Reg[2]*Reg[3]
Reg[1]=Reg[4]+Reg[5] Reg[2]=Reg[1]+Reg[6]
Reg[1]=Reg[2]*Reg[3] Reg[3]=2

Cycle WA RA RW BS WrA WrB ALU Comments

Op
1 001 0 010 0 0 Reg[1]=2
2 010 0 010 0 0 Reg[2]=2
3 011 0 011 0 0 Reg[3]=4
4 001 1 100 1 0 A=Reg[1]=2
5 010 1 100 0 1 B=Reg[2]=2
6 100 0 101 0 0 110 Reg[4]=2*2
7 011 1 100 0 1 B=Reg[3]=4
8 101 0 101 0 0 110 Reg[5]=2*4
9 010 1 100 1 0 A=Reg[2]=2
10 110 0 101 0 0 110 Reg[6]=2*4
11 100 1 100 1 0 A=Reg[4]=4
12 101 1 100 0 1 B=Reg[5]=8
13 001 0 101 0 0 001 Reg[1]=4+8
14 001 1 100 1 0 A=Reg[1]=12
15 110 1 100 0 1 B=Reg[6]=8
16 010 0 101 0 0 001 Reg[2]=12+8
17 011 0 010 0 0 Reg[3]=2
18 011 1 100 0 1 B=Reg[2]
19 010 1 100 1 0 A=Reg[3]
20 001 0 101 0 0 110 Reg[1]=20*2

Comments- Based on the ALU out, the final binary value is 00101000. By converting into
decimal, it known as 40. Based on the display drive, the final binary value is
00110011000000. The value should be separate into two and complement it to become
1100110 and 0111111 as it is active low. By referring to the Verilog code in the bcd.v, it will
transform into 40. This value is proven by both verification methods as 40 is the same with
the process table.

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Simulation waveform

Timing diagrams

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Significance

What is the importance of the lab?

It is important for us to participate in the lab because it could build up our fundamental
knowledge about digital design and strengthen our understanding regarding the application
and working principles of the simple data path. Hence, we are able to identify and enhance
the flows of the data path’s operations by varying the control lines. It is also crucial for us to
observe the simulation waveforms are identical with the process tables to resolve more
complicated operations in future.

How will you use the information you learned in this lab in the future?

With this basic knowledge that we have grasped, we hope that it could aid us in designing
and applying the circuits that require arithmetic operations, which are the core of the entire
computing system. If I am not mistaken, there is a module called Computer Architecture and
Embedded Systems in next semester that is almost related to what we have learned in this
module. Hence, it might be helpful for us, as this lab has strengthened our fundamental
knowledge about the simple data path in centre processing unit (CPU) of a computer system.
I will also use the information that I learned to teach my juniors and siblings that are
interested in this course to broaden their knowledge.

Indicate several learning outcomes similar to what you have done in Lab-3 Report.
The similar learning outcomes of this lab5 report and the lab 3 report are that we are able
to enhance our writing skills for a formal lab report that is helpful for our following core
modules. Moreover, the other similar outcome is that we have enhanced the operation of
Quartus software because it is our main platform for performing the compilation of Verilog
codes, simulation of waveforms, as well as assigning pins on the FPGA board. Furthermore,
we have completed the task given, which was to utilise the 7-segment display and simple
CPU to implement the 3 different equations shown above. Besides, we also build up the
fundamentals to understand how the complicated operations are being processed by varying
the control lines. Other than that, we are also able to edit and transform the waveform
corresponding to the process tables. In a nutshell, every single detail and piece of knowledge
are important for us to conduct a successful experiment and apply them to writing the lab
report.

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