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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES 1

Wide Dynamic-Range CMOS RMS Power Detector

Jaewon Choi, Member, IEEE, Jongsoo Lee, Yao Xi, Seong-Sik Myoung, Sanghyun Baek,
Dae Hyn Kwon, Student Member, IEEE, Quang-Diep Bui, Jaehun Lee, Student Member, IEEE,
Dongjin Oh, and Thomas Byunghak Cho, Senior Member, IEEE

Abstract—This paper presents a wide dynamic range (DR)

CMOS root-mean-square power detector with a temperature
variation compensation technique in a 28-nm CMOS process.
The cascaded gain amplifiers and squaring circuits in the pro-
posed power detector can achieve wide DR with the power level
segmented detection method using a switch driver with the help
of a modem. A 12-bit current digital-to-analog converter is used
to calibrate dc offset in the power detector with 25- V steps to
improve the accuracy. Measured DR is more than 40 dB from 700
MHz to 4 GHz. A temperature compensation bias circuit improves
the performance of the detector with maximum 0.8-dB error over
the temperature range 30 C 90 C. The chip area is 333
m 450 m and the power consumption is from 5.8 to 11.8 mW
depending on the input power using a 1.8-V power supply.
Index Terms—CMOS, power detector, power segment, root
mean square (rms), temperature coefficient doubler (TCDBL),
temperature compensation.
Fig. 1. Block diagram of a general power detector operation in RF transceiver.

I. INTRODUCTION

I N CELLULAR RF integrated circuits (RFICs), tightly

controlling the transmitted power level within the specified
limit is critical in order to achieve the range and the reliability
of the link among many users. For example, according to 3GPP
standards, when the base-station sends a transmit power control
(TPC) command containing the target output power level to a
mobile terminal, the mobile terminal has to output the specified
power level within the given time period. Among different
standards, UMTS specifies a very stringent power control re-
quirement called inner loop power control (ILPC) [1], where
the mobile terminal has to control its transmitted output power
by 1-dB step within a 0.5-dB step error. As a result, the trans-
mitted power is measured and compared to a set point level in
a feedback system requiring high-precision power detectors.
Fig. 1 shows the block diagram of a general power detector
operation in cellular applications. The power detector detects
the transmitting power at TX’s output through the coupler, and
generates dc voltage output. This voltage is sent to a modem,
which controls the gain of TX chain to adjust the output power.
Another important requirement for the power detector is
a wide detection dynamic range (DR) in order to enable the
power-saving feature such as average power tracking (APT).
Manuscript received March 16, 2015; revised October 08, 2015 and
November 27, 2015; accepted December 21, 2015.
J. Choi, J. Lee, S.-S. Myoung, S. Baek, D. H. Kwon, Q.-D. Bui, J. Lee, and
T. B. Cho are with Samsung Electronics, Hwaseong 18448, Korea (e-mail: jae-
wonc.choi@samsung.com).
Y. Xi was with Samsung Electronics, Hwaseong 18448, Korea.
D. Oh was with Samsung Electronics, Hwaseong 18448, Korea.
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TMTT.2016.2519030
APT uses a dc–dc converter to generate the power amplifier
supply, instead of a low-dropout regulator (LDO), in order to
minimize the energy loss through the regulator. If the power
detector can have the wide DR of the accurate detection level,
APT can be more accurately applied for more current saving,
leading to extended battery life for the given battery capacity.
The selection of the power detector type is also important for
today’s recent cellular systems, where several different mod-
ulation methods, such as binary phase-shift keying (BPSK),
quadrature phase-shift keying (QPSK), 16 quadrature amplitude
modulation (16QAM), and 64 quadrature amplitude modula-
tion (64QAM), are all having different peak-to-average ratios.
Peak power detectors [2] are simple and generally suitable for
constant envelope modulated signals, i.e., the global system for
mobile communications (GSM), but can make errors for high
peak-to-average ratio signals [3]. For high peak-to-average
ratio signal applications, a root-mean-square (rms) detector
is generally more desirable. RMS power detectors read the
average TX power over time, giving a more accurate result
for time-varying high peak-to-average ratio or noisy signals.
It is known that rms power detectors are implemented using
thermal detection, diode detection, and translinear detection
[3]–[5]. The thermal detection has a wideband characteristic
and high accuracy, but it is difficult to implement it in a CMOS
RFIC because of thermal coupling from adjacent circuits
through the substrate. Detectors based on a diode are com-
monly used in communication systems due to their low cost
and good performance at high frequencies [6]. However, the
performance of diode detectors depends on the temperature
variation and, thus, additional compensation techniques are
required [6]. Furthermore, certain RF diodes such as Schottky

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2 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES
Fig. 2. Block diagram of the proposed power detector and its operation over the power segment: (a)
diodes are not standard devices in the CMOS process [3], [6],
[7]. Another type of rms power detector is translinear-based
detection [4], [8], [9]. A voltage-to-current converter ( –
converter) transfers the RF voltage signal to a current signal,
which is then squared by a squarer divider. It is filtered out
by a low-pass filter, generating dc output proportional to the
power of the RF input signal [6]. However, translinear-based
detectors have bandwidth limitation compared to thermal and
diode-based detectors [3]. In addition to the above-mentioned
methods, CMOS power detectors are developed in [10]–[13],
where the cascaded multistage limiting amplifiers rectify the
RF signal, implementing linear-in-decibel conversion in [10].
Recently, a transformer-based CMOS power detector is de-
veloped in [14]. The power detector is integrated inside a power
amplifier. Transformer-coupling methodology is applied to pro-
vide a true rms power detection, where both the current and
voltage of the power amplifier are sensed and multiplied.
In this paper, a wide dynamic-range CMOS rms-type power
detector is presented. The cascading gain amplifiers (GAs) and
squaring circuits (SQRs) achieve wide DR with a power level
segmented detection method. Proposed power detector has only
four GAs and four SQRs to provide more than 40-dB DR. Its DR
can be extended as much as possible if necessary. Only one SQR
is on wherever the detected power range is. The proposed power
detector is integrated inside a cellular transceiver chip and is de-
signed using a standard CMOS process. It works at 1.8-V supply
voltage and no additional external components are required. A
temperature compensation bias circuit is added to improve the
accuracy of power detector output voltage over the temperature
variation. The proposed architecture of the power detector is
introduced in Section II. In Section III, the detailed explana-
tion of the circuit configuration and analysis will be presented.
Section IV shows the simulation and measurement results and
Section V concludes this paper.
II. PROPOSED ARCHITECTURE
As mentioned above, the rms detector is insensitive to the
signal shape and modulation form due to its averaging over
and (b) .
time. Therefore, it is suitable for recent communication stan-
dards such as third-generation (3G) W-CDMA and fourth-gen-
eration (4G) long-term evolution (LTE) that have a large peak-
to-average ratio and different modulation signal. The effective
rms value of a periodic current (or voltage) is defined as the dc
current (or voltage) that produces an equivalent average power
to a resistor as the periodic current (or voltage) [15].
The rms voltage is expressed as
(1)
where is the instantaneous voltage.
According to (1), squaring and averaging operations are re-
quired to obtain the rms power of an ac signal. Therefore, a SQR
and a low-pass filter are necessary to realize the rms power de-
tector. In Fig. 2, the block diagram of the proposed power de-
tector is presented. It consists of three blocks such as the RF core
including GAs and SQRs, transimpedance amplifier (TIA), and
differential to single-ended amplifier (D2S). The proposed de-
tector divides the detection range into four small segments to
cover a wide linear DR and each of them can be handled by
the aforementioned SQR. The RF input signal of the power de-
tector passes the GA and it is converted to the squared dc voltage
by an SQR block for mean square operation. The TIA converts
the output current of RF core to voltage by a feedback resistor
and D2S finally converts the differential signal to single-ended
voltage with RC filtering at the output node. Fig. 2 also ex-
plains the operation of the proposed power detector for each
segment in detail. In the proposed structure, each GA and SQRs
can be controlled on/off to segment the detected power range.
Each block has a separate control bit, which is set by the desired
power level segment according to the modem requirement. GA
successively turns on depending on the input level, where only
one SQR is used to feed the current to the TIA.
The output current of an SQR is fed into the TIA, which con-
verts the current to voltage with its load resistor . There is
an RC filter between the TIA and D2S and also RC circuits in the
TIA and D2S itself. These RC filters can remove undesired sig-
nals and can achieve the mean value for rms detection. As seen
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CHOI et al.: WIDE DYNAMIC-RANGE CMOS RMS POWER DETECTOR 3

Fig. 3. Conceptual output response of the proposed power detector.

in Fig. 3, four different segments, i.e., cover the

desired input power range and each of the segments is selected
by the modem in predefined steps. Each power detection range
is assigned with power selection (PS) control bits, which are de-
fined in a TX gain address. Each SQR responds on the assigned
power detection range based on the target transmitting power.
One SQR covers a predefined detection range with an overlap
range. Fig. 4 shows a flowchart and how the power segment
of the detector is decided by a user equipment (UE) modem.
If the received power in a base station is not satisfied with tar-
geted power, the base station requests the modem to change TX
output power. The modem determines a new gain code for TX
and a power range segment ( ) for the power
detector. TX sends new output power and the power detector
reads the new output power to monitor if the targeted power is
being transmitted. The modem receives new information on the
transmitted power from the power detector and adjusts TX gain
to control TX output power again if the monitored power infor-
mation does not match the targeted power.

III. CIRCUIT CONFIGURATION AND ANALYSIS Fig. 4. Flowchart of the proposed power with modem control.

A. GA
In Fig. 5, a conventional differential pair with resistive loads
is used for the input gain stage and a source follower is used for
the output buffer to drive a following SQR. The dominant pole
is placed at the buffer output node and its value is determined
by and of the buffer, where and are total
equivalent resistance and capacitance at the buffer output node
( ), respectively. A moderate and small are
required to have the wide bandwidth of the output buffer stage.
However, a large capacitive load of the follower stage and lim-
ited current budget reduce the bandwidth at the output source
following the buffer stage. Therefore, a source follower with a
cross-coupled NMOS pair is proposed to increase the bandwidth
of the output buffer with a given limited power budget. In Fig. 6,
the simplified equivalent schematic of the output buffer is de-
scribed. Intuitively, ac wise, this cross-coupled NMOS pair to-
gether with a source capacitor will create a negative impedance
( ), is equivalent impedance between
nodes and at the source of and in Fig. 6). Fig. 5. Schematic of a designed GA.
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4 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES

Fig. 6. Equivalent circuit of the output buffer stage.

Fig. 8. Schematic of the designed SQR.

terms. Basically, the differential pair and detects the

RF input power from GA and and makes a dc offset
as a dc reference to provide zero output when the input is zero.
Both pairs ( and ) are the same size and biased
with the same condition for small process and temperature vari-
ation. The cascode transistors ( and ) are added to im-
prove output impedance of amplifier and to achieve well-de-
fined drain voltage of differential pair. One drawback of the
Meyer’s squaring structure is that the more current is drawn
from resistive load as the power of the input RF signal increases.
This leads the output voltage drop and the input differential pair
cannot operate in the saturation region. As a result, it can re-
duce the input DR. To resolve this problem, a current output is
extracted from the SQR and then converted into voltage through
Fig. 7. Simulation response of an equivalent circuit of the output buffer stage.
following TIA. Therefore, PMOS current source is placed and
common mode feedback circuit (CMFB) is added to ensure the
When is 0, the gain of an equivalent circuit is approxi- output of SQR and set the same common mode voltage with
mately unity ( ) at dc ( ) and the output gain following TIA over the whole input DR, as shown in Fig. 8. In
( ) is 2 ( ) at the high fre- Fig. 8, the drain current of each pair is and . The drain cur-
quency because the cross-coupled pair is ac grounded. As a re- rent of each transistor ( , , , ) is expressed as ,
sult, the source follower has a high-pass characteristic, as shown , , and , respectively. For signal input pair, the RF
in Fig. 7 (red solid line). For , source–follower gain is input signal and are applied to and and each
1 at dc and 0 at the high frequency. Therefore, the source fol- drain current is expressed as
lower has a low-pass characteristic, as shown in Fig. 7 (blue (2)
solid line). Both the low- and high-pass characteristic are com-
bined with proper and a negative impedance technique. (3)
It can expand output bandwidth, as shown in Fig. 7 (green solid
line). Therefore, the gain at the high frequency of the GA can be where , , and are average electron mobility,
enhanced without additional current consumption. In dc view, gate–oxide capacitance per unit area, and threshold voltage,
the cross-coupled NMOS pair is heavily degenerated by a tail respectively. is the width and is the length of the transistor.
current source, which will make sure the negative resistance The drain current of signal pair ( ) is
presents at the source–follower load to be large enough, there-
fore, the circuits will not be latched up at dc.

B. SQR
Fig. 8 shows a designed SQR of the power detector. A CMOS (4)
differential structure of the Meyer RF power detector [2], [16]
is used to suppress common mode variation and odd harmonic where .
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CHOI et al.: WIDE DYNAMIC-RANGE CMOS RMS POWER DETECTOR 5

Similarly, the drain current of the reference pair ( ) is ex-

pressed as

(5)

The difference current at the output is

(6)

where .
The load RC operates as low-pass filter and filters out high-
frequency terms of (6). After filtering, (7) shows the differential
output current,

(7)

Equation (7) includes , which is the input voltage squaring

(i.e., power information). Thus, squaring and averaging opera-
tion are achieved by the designed SQR for the rms value of an
ac signal.
An SQR, especially based on a CMOS process, has mismatch
and it limits the detection DR. Fig. 9 shows how mismatches af-
fect power detection range. As we can see from Fig. 9(a), there
is no lower limit on DR up to the noise floor if the SQR is
free of any mismatch. However, as certain mismatch presents,
the lower end of power detector output deviates from the ideal
curve. As shown in Fig. 9(b), the DR is reduced to no more than
20 dB in a quick Monte Carlo simulation.
Hence, the most promising solution for covering such a large
DR is to slice the whole range into several small segments and Fig. 9. SQR mismatch simulation comparison. (a) Normal simulation.
(b) Monte Carlo mismatch simulation.
each of the segments can be handled by the aforementioned
SQR.

C. Temperature Compensation Bias Circuit

A GA and an SQR are RF core block and their performance
is an important factor to affect the overall performance of the
power detector. Both circuits have transconductance (
) dependence in operation and is temperature
dependent. Load resistors in a GA have temperature dependence
as well. Thus, it is desired to bias the transistors such that their
overall gain is independent of temperature variation. A common
approach for the temperature variation compensation is to use a
proportional-to-absolute temperature (PTAT) bias circuit. How-
ever, this approach has limitation that it has a fixed slope (a: blue
line) for the temperature variation and it does not provide dif-
ferent slope to cover large temperature variation, as shown in
Fig. 10. Thus, additional bias block is required to compensate
more variation like the (b)–(e) cases in Fig. 10, where “TCC” is
the temperature coefficient of temperature coefficient compen-
sation (TCC) block and if the coefficient becomes large, current
variation over temperature becomes steeper.
Fig. 11(a) shows a block diagram of the proposed bias block. Fig. 10. Simulated current output of PTAT and TCC circuit
There are four main blocks such as: 1) PTAT; 2) bandgap ( 30 C 90 C).
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6 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES

Fig. 11. Block diagram of the power detector with a compensation bias block. (a) Proposed bias block for the power detector. (b) Proposed power detector. (c)
Square circuit bias block with TCDBL.

Fig. 13. Schematic of TCDBL.

Fig. 12. Schematic of TCC.
reference (BGR); 3) TCC; and 4) squaring bias block with
the proposed circuit called the temperature coefficient doubler
(TCDBL). The schematics of the designed TCC and TCDBL
are presented in Figs. 12 and 13, respectively. In contrast to
the PTAT, the TCC can adjust the current slope by changing
and averaging the current of PTAT and BGR, as shown in the
Fig. 10(b)–(e) cases.
The output current of the TCC is expressed as
However, the TCC does not provide enough of a slope rate
in the case where larger slope is required. An additional com-
pensation block called a squaring circuit bias block (SQRBB) is
proposed as shown in Fig. 11(c). It consists of a current mirror
and two TCDBLs, as shown in Fig. 11(c), and the output cur-
rent is the summation of the BGR and TCDBLs. The output
current of the TCDBL is difference from and
as derived in (9). The current of a SQRBB is a function of mul-
tiple times of the PTAT current and larger slope can be achieved
with TCDBL combinations. Fig. 14 shows that SQRBB has a
larger temperature coefficient from 0.03 to 0.1 ( A C) over
30 C 90 C compared to only the PTAT,
(9)
(8)
where , , , , and constant.
The gain of an SQR with simple current mirroring of ref-
erence current with a poly resistor shows 1.1-dB varia-
tion when operating temperature goes from 30 to 90 . The
small-signal gain of the SQR depends on , which is biasing
independent, but highly temperature dependent. The gain of the
SQR shows 0.8-dB variation under the same temperature
, variation even though constant- biasing is applied. With the
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CHOI et al.: WIDE DYNAMIC-RANGE CMOS RMS POWER DETECTOR
Fig. 14. Simulated output current of a square bias circuit over the temperature
variation ( 30 C 90 C).
Fig. 15. SQR output voltage comparison over the temperature variation
( 30 C 90 C) without and with TCDBL.
help of TCDBL, the temperature variation of the SQR is reduced
from to 0.2 dB, as shown in Fig. 15.
The proposed bias circuit can provide a higher and flexible
temperature coefficient for the analog bias block with the pro-
posed bias block including the PTAT, TCC, squaring bias with
TCDBLs, and bias distribution block. As a result, it can achieve
less dependence of the temperature variation (i.e., less output
voltage variation for the power detector).
D. DC Offset Calibration
A DR of an SQR is an important factor that determines the
DR of a power detector. The DR of the SQR is limited by mis-
matches as mentioned. The mismatches lead to dc offset in the
circuit. DC offset value is added to the output voltage of a power
detector and it generates wrong detection voltage if dc offset is
not calibrated and increases detection error. DC offset is gener-
ated randomly and it has to be calibrated using an SW driver
with the help of a modem in advance before power detector
power calibration is done using external power measurement
7
equipment. Since dc offset calibration (DCOC) is done at the
power-up once, the calibrated bits information of all four stages
per each chip has to be stored in a storage space and is driven by
software whenever the power detector is operated. To calibrate
dc offset, a 12-bit DCOC digital-to-analog converter (DAC) is
included as a part of the TIA.
Calibration time of a mobile phone is limited to increase the
efficiency in production and power detector calibration time has
to be minimized to save the overall calibration time of a mo-
bile phone. The proposed power detector has four SQRs and all
of them have to be calibrated with small calibration time. One
simple approach for DCOC is to sweep all 12-bit DAC codes
and find an optimal code. However, it requires 4 2048 steps
iteration for the proposed detector to sweep all DAC codes. The
most commonly available dc offset algorithm is a binary search
or SAR algorithm where two times of the bit length of the DAC
measurements are required and steps are required
in the proposed power detector. To further optimize calibration
time, a new algorithm for DCOC is proposed to be done with
faster time.
Fig. 16 explains the method to find an optimal DAC code
for DCOC with the output voltage of the D2S. Fig. 16(a) de-
picts the input–output relation in linear scale. The blue line is
the in–out curve in an ideal case. In this case the output voltage
is zero when there is no input or the input power is zero. How-
ever, if there is a dc offset, the in–out curve is shifted like the
red line in Fig. 16(a) and the low limit of the DR is decreased.
Fig. 16(b) shows the relation between the D2S output voltage
and the DAC control code with the given dc-offset condition. If
the output voltage is zero, it means either zero offset or nega-
tive value, which does not exist at the D2S output. In the D2S
block, there is a switch to change the input voltage polarity. The
blue and red lines in Fig. 16(b) show the in–out curve with the
default polarity and opposite polarity.
Fig. 16(c) shows the difference between the blue and red
lines in Fig. 16(b). As shown in Fig. 16(c), the difference of
the two measured outputs with the different polarity setting is
very linear and the optimum DAC code for the dc-offset cance-
lation is the code where the difference becomes zero. Since the
difference is very linear and monotonic function, the optimum
code can be simply calculated by using the following arithmetic
derived in (10):
(10)
where and are DAC code and and are the
output voltage for each and . In this case, only four mea-
surements with two different DAC codes and different polarities
are enough to get the optimum code. Equation (10) shows the
optimal output code with simple slope calculation. The main ad-
vantage of this method is that it only needs original and flipped
voltages response and requires 4 2 steps iteration, saving cal-
ibration time.
IV. SIMULATION AND MEASUREMENT RESULTS
The proposed power detector was fabricated in a Sam-
sung 28-nm CMOS process with 1.8-V supply voltage. The
die photograph is shown in Fig. 17 and the silicon area is
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8 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES

Fig. 18. Power detector output voltage over operating frequencies. (a) Simu-
lation. (b) Measurement.

Fig. 16. Calibration method for an optimum DCOC DAC code. (a) Output
voltage response with and without dc offset. (b) Output voltage response over
DAC code. (c) PDET DCOC Calibration description.

Fig. 19. Simulated power detector output voltage over the temperature varia-
tion at 1.9 GHz.
Fig. 17. Die photograph of a fabricated power detector.

333 m 450 m. The power consumption is 5.8 mW when The input matching stage has a shunt 50- resistor to pro-
mode and 11.8 mW when mode. vide wideband matching from 700 MHz to 4 GHz. The p ploy
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CHOI et al.: WIDE DYNAMIC-RANGE CMOS RMS POWER DETECTOR
Fig. 20. Measured power detector output voltage over the temperature vari-
ation at 1.9 GHz for . (a) Before TCC optimization. (b) After TCC
optimization.
resistor is used for the input matching resistor to minimize the
resistance variation over temperature. Twenty of 1-K resistors
are connected in parallel to get an accurate 50- resistor.
The proposed power detector has four different PS modes
( ) and total output has four transfer functions for
the input range. They have an equal slope and are placed with
the same placement step ( 8 dB). One segment can detect
12 dB and all stages cover more than 40-dB DR. Fig. 18 shows
the power detector output voltage variation on the different op-
eration frequencies such as 1, 1.9, and 2.7 GHz. To compensate
9
Fig. 21. Power detector output voltage versus (solid lines: measurement;
dashed lines: simulation).
Fig. 22. Power detector input referred variation simulation by modulation
signal sources.
for cable and printed circuit board (PCB) losses by operating
frequencies, power detector output voltage was set to the same
target level at the same input power with the different operating
frequencies. As can be seen in Fig. 18, measured power de-
tector output voltage is insensitive to the operating frequencies
and the DRs are more than 40 dB. The measurement results
are well matched to the simulation results. Fig. 19 shows the
simulated power detector output voltage responses over the
different temperatures at 1.9-GHz operating frequency. The
simulated output voltage goes from 0.1 to 1.8 V within 12-dB
DR. The responses of each segment show different temper-
ature performance. The segment with the largest gain (four
amplifiers are all turned on) shows bigger temperature vari-
ation 0.4 dB. The segment with smallest gain (just one
amplifier is turned on) shows the least temperature variation
0.1 dB.
Fig. 20 shows the temperature variation measurement. The
measurement result of the mode ( ) at 1.9 GHz is selected
for the worst case, and the output error is referred to 30 C.
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10 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES

Fig. 23. Measured output voltage of the power detector for different modulation signals.

Fig. 24. Power detector output voltages and its detection errors before DCOC Fig. 25. Power detector output voltages and its detection errors after DCOC in
in three randomly selected samples. (a) Detector output voltage. (b) Detection one of three randomly selected samples. (a) Detector output voltage. (b) Detec-
error. tion error.

Five different temperature cases ( 30 C, 0 C, 30 C, 60 C, optimization. Before TCC is optimized, it shows the maximum
90 C) are measured and compared based on the TCC slope 3.5-dB error over the full temperature variation. After TCC is
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CHOI et al.: WIDE DYNAMIC-RANGE CMOS RMS POWER DETECTOR 11

TABLE I
PERFORMANCE COMPARISON WITH RECENT PUBLISHED RMS POWER DETECTOR

optimized, detection errors are reduced and it shows maximum V. CONCLUSION

0.8-dB error over the full temperature variation. In this paper, a wide DR CMOS rms power detector has been
The proposed detector can also adjust output voltages with proposed. The proposed detector has cascading GAs and SQRs
the fine step ( 1 dB) using the variable resistor of TIA ( ) to achieve wide DR using the power level segmented detec-
to compensate for the process variation. The measurements of tion method. GAs with a cross-coupled NMOS enhance the
the fine step are shown in Fig. 21 with the simulation results. The frequency response and they can achieve wideband operation
measurement results are well matched to the simulation results. for the detector. A temperature compensation bias circuit im-
TIA fine gain is used to adjust the output voltage of the proposed proves the performance of the detector with maximum 0.8-dB
power detector. TIA resistors are swept automatically using an error over the temperature range 30 C 90 C. A current
SW driver until detector output voltage is generated to the target DAC DCOC block is added and utilized to improve DR of the
voltage for the pre-defined input power. Once the TIA resistor SQR and power detection accuracy by removing residual dc.
is determined, the TIA resistor is set in a normal operation. TIA Measurement results show the proposed detector can achieve
gain can be adjusted up to 4 dB. more than 40-dB DR with 5.8 mW (Max. 11.8 mW) power
As mentioned earlier, a rms detector has to be insensitive to consumption.
the signal shape and modulation type for multi-mode applica-
tion such as cellular RFICs. To mimic the modulation signal APPENDIX
using continuous wave (CW) signal sources, a designed power ANALYSIS OF TCDBL
detector was simulated with multi-tone signals. One, two, and A detailed derivation of TCDBL output current is explained
four tones were used to run the simulation for checking modu- as follows:
lation variation. Fig. 22 shows input referred variation by multi-
tone signal sources. Simulated detection error between 1T and (11)
4T tones is 0.39 dB. Fig. 23 shows that the proposed power (12)
detector has consistent response for different modulation sig- (13)
nals such as CW, 3G W-CDMA, 4G LTE 10-MHz full resource
block (RB), and 4G LTE 10-MHz 1-RB.
Figs. 24 and 25 compare the performances of the proposed (14)
power detector without and with DCOC. Three samples were
randomly selected and measured for output voltages without (15)
DCOC. The measured output voltages were compared with
ideal curves to provide detection errors for each power segment
(16)
stage. As can be seen in Fig. 24, detector output voltages are
deviated from the ideal curves and detection errors becomes
larger, especially in the range where detector output voltages
become small, leading to the limited DR. One of three samples
was selected and calibrated for dc offset. The measurement
(17)
results after DCOC are shown in Fig. 25. Detector output
voltage of each stage becomes almost identical and DR placed Equation (17) shows that the output current of the TCDBL
in a certain detection error becomes wider. DCOC improves has two times the coefficient of the PTAT. The name of the dou-
DR and power detection accuracy of the power detector. bler came from (17).
Table I summarizes the results of the performance compar-
ison. The proposed power detector had the widest DR in which ACKNOWLEDGMENT
the linearity was maintained within the specified frequency The authors would like to thank J. Sangirov, HW Platform
with temperature variation, thanks to its use of power segment Team, for data gathering and J. H. Kim, LSI PE/TEST Team,
methods and temperature compensation bias circuits. for a chip photograph.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
12
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Jaewon Choi (S’09–GSM’12–M’13) received the
B.S. and M.S. degrees in electrical and electronic
engineering from Yonsei University, Seoul, Korea, in
2006 and 2008, respectively, and the Ph.D. degree in
electrical and computer engineering from Carnegie
Mellon University, Pittsburgh, PA, USA, in 2013.
He is currently with Samsung Electronics,
Hwaseong, Korea, where he is involved with cellular
RF integrated circuit (RFIC) development. His
research interests include RF CMOS transceiver ar-
chitectures and circuits for wireless communication
systems.
Jongsoo Lee received the B.S. degree in physics
from Chung-Ang University, Seoul, Korea, in
1999, and the M.S. and Ph.D. degrees in electrical
engineering from The Ohio State University (OSU),
Columbus, OH, USA, in 2003 and 2008, respec-
tively.
Since 2008, he has been with Samsung Elec-
tronics, Hwaseong, Korea, where he is currently
involved with cellular RF integrated circuit (RFIC)
development as a Principal Engineer. His research
interests include the design of analog/RF integrated
circuits and systems for a cellular application.
IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES
Yao Xi received the B.S. degree in electronic sci-
ence and technology from the Harbin Institute of
Technology, Harbin, China, in 2006, and the M.S.
degree in electronic and electrical engineering from
Sungkyunkwan University, Suwon, Korea, in 2009.
From 2009 to 2014, he was an Engineer with Sam-
sung Electronics, Hwaseong, Korea. His research in-
terests include RF power amplifiers and transceiver
integrated circuit (IC) design.
Seong-sik Myoung (S’02) received the B.S. degree
in electronics engineering from Soongsil University,
Seoul, Korea, in 2002, and the M.S. and Ph.D. de-
grees in electrical and electronic engineering from
Yonsei University, Seoul, Korea, in 2004 and 2009,
respectively.
He was a Visiting Scholar with the Georgia Insti-
tute of Technology, Atlanta, GA, USA, from 2007 to
2008. In 2009, he joined the RF Development Team,
Samsung Electronics, Hwaseong, Korea, where he
is currently involved with the development of trans-
ceivers for mobile communications.
Sanghyun Baek received the B.S., M.S., and Ph.D.
degrees from the Korea Advanced Institute of Sci-
ence and Technology (KAIST), Daejeon, Korea, in
2001, 2003, and 2009, respectively.
Since then, he has been with Samsung Electronics,
Hwaseong, Korea, where he designs RF circuits for
cellular phones. His research interests include the de-
sign and implementation of RF integrated circuits and
systems for cellular applications.
Dae Hyun Kwon (S’08) received the B.S. degree
in electronics engineering from Korea University,
Seoul, Korea, in 2002, the M.S. degree in electrical
engineering and computer science from Seoul
National University, Seoul, Korea, in 2004, and the
Ph.D. degree in electrical and computer engineering
from the University of Illinois at Urbana-Cham-
paign, Urbana, IL, USA, in 2010.
From 2010 to 2013, he was with the Broadcom
Corporation, San Diego, CA, USA, where he
designed RF transmitters with on-chip power am-
plifiers for wireless local area network (WLAN) products. Since 2013, he has
been with Samsung Electronics, Hwaseong, Korea, where he has been involved
with cellular RF transceivers.
Quang-Diep Bui received the B.S. degree in elec-
tronics and telecommunications from the Hanoi
University of Science and Technology, Hanoi,
Vietnam, in 2001, and the M.S. and Ph.D. degrees
in information and communications engineering
from the Korea Advanced Institute of Science and
Technology (KAIST), Daejeon, Korea, in 2007 and
2013, respectively.
In 2013, he joined Samsung Electronics,
Hwaseong, Korea, where he has been involved in
the design and development of RF integrated circuits
(RFICs) for wireless communications.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
CHOI et al.: WIDE DYNAMIC-RANGE CMOS RMS POWER DETECTOR
Jaehun Lee (S’11) received the B.S. and M.S.
degrees in electrical engineering from the Korea
Advanced Institute of Science and Technology
(KAIST), Daejeon, Korea, in 2011 and 2013, respec-
tively.
In 2013, he joined the RF Development Team,
Samsung Electronics, Hwaseong, Korea, where
he is currently involved with the development of
transceivers for mobile communications.
Dongjin Oh received the B.S. and M.S. degrees in
electrical engineering and computer science from
Ajou University, Suwon, Korea, in 2009 and 2011,
respectively.
From 2011 to 2015, he was an Engineer with
Samsung Electronics, Hwaseong, Korea, where his
research was focused was on CMOS RF/analog
integrated circuits.
13
Thomas Byunghak Cho (S’89–SM’12) received the
B.S. degree from the University of California at Los
Angeles, Los Angeles, CA, USA, in 1989, and the
M.S. and Ph.D. degrees from the University of Cali-
fornia at Berkeley, Berkeley, CA, USA, in 1991 and
1995, respectively, all in electrical engineering.
From 1995 to 1996, he was a Post-Doctoral
Researcher with the University of California at
Berkeley. From 1996 to 2000, he was with Level
One Communications, San Francisco, CA, USA,
where he developed CMOS RF transceiver products
for cordless phone applications. In 2000, he cofounded Wireless Interface
Technologies, Dublin, CA, USA, which develops CMOS RF transceivers for
wireless personal area network (WPAN)/wireless local area network (WLAN)
applications (the company was later acquired by Chrontel, San Jose, CA, USA).
In 2004, he joined Marvell Semiconductor, Santa Clara, CA, USA, where he
developed CMOS RF and analog integrated circuit (IC) products for various
wired and wireless connectivity applications. Since 2012, he has been the Vice
President of the RF Development Team, at Samsung Electronics, Hwaseong,
Korea, where he is focused on the development of CMOS RF/analog ICs and
data converter IPs for multi-mode multi-band cellular modem applications. His
research interests include CMOS analog ICs for high-speed analog-to-digital
interfaces and wireless communication systems.
Dr. Cho was a corecipient of the International Solid-State Circuits Conference
Jack Kilby Award for Outstanding Student Paper in 1997.