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The Obs need x signed nunbér to operate Ar nv VEEloy > when the seseltt of an operdlion fe oegattve a Fe stepiereited Yn “two's complerest asim dn VHDL Nate thal addition nd subtstdtion operattons can also be applied to siqrah defined by std logic -veeloet Let's give Hoee exampler On the urage of csfthnac Operations . The ficial example 97 09 asfithmelie operdltona Urry aN vay Syst ord constast ax shown below. Here, thiee catthneltc opexdbions Coddttion, attsiétton .and moltiptcation) axe applied on a Constant cet and Gapat doery num . Here, the rang ix defined 0“ Coooco!e”. Data low mrad ebing is Oped to deseorbing there operationsfsathnelie openibions on a Conilact and Aaergy Sn WHOL: Irbeney ieee; Use ieee. numeric — std all ; entity asfithondtic —conitank tx Posi Crom + %n signed C4 dounta 0); Hest. out signed (+ downto 0); Hesds out signed (4 downto 0); Ses out signed Cis dountoo)); contest coef + Signed (4 downto 6) + - " Qov0c0!0" ; end ay(ithmatic . constant 5 osichitectuxe dataflow. model of ostthmélre - conilat 9p begin —~ addstfon Hest z= num t coet ; ~~ sublsactton MesQ <=num -Coef 5 -~ mullpkedtion MES L= coef * pum : end dataflow — model ; “10 explarn Wwodt ling PoRncieler of athwalic opendlfans fncluding a conitart one shown below. Here, the tpul dvony to be processed fr token ar * Qo ootnth a ee The steond example 4% axtthmitic opedition bared on ane Con two eight -bit number) Here, six antthmalic openitfons Caddition, Sublimétion , multiplication » division , modulus , and stemdindes gue applied on two Gq - bit npat bony um! ond ung. The coseresponding VHDL descsdptton Ss gi below Datoflow modeling ¥% used 99 desea bing these operalion © This hein Sq the VHDL veigion of the one given bolow - We poovide The prt gchemilve of the vot desessplion ax shown below fig AR con be sean fo hey Fue , all ostthmelic opera che Stepresested ap haste blocks . num) (3: >: Ae techn GE run att) D9) . {> dest [7:0] L- ADD [tot o] ritual) ~ ac scat tL-SuR aess_t {Worse :0J [> nes 8 [7 TL-SUR a peak t rag OCIs:0 a pUISsO Lt. See rise] | TL Mul hocazot _ mees-? 7 : O30] | [HB maces | | TL_prv | (l0C3:0] oC3: (11 [3:0] nt ——{_)%es6[7 +0] Rt Mon Fy’ RTL sckemaltc of cxthnckic opexiffin on. tea asoraysTeathench fe or Astthnétic openittons on a conitait and Aoy ‘9 _NwOl ebocey ieee Ure ieee numenic -std - oll} etity asdthmeie - constant th 1, end arfithmiltc —corgtont th 5 csickitectume dataflow of artthmilic- conitaat-tb ‘x Cam ponent asithmel¥e_constoal Post Cum tn signed (4 dowrte 0; Hest + out signed ( downte 98); Hesa + ot signed (4 danto 0); HSS > out signed Cis dountoo)); end compare 5 signal fot: signed (% downto ©); Sqnal cult + signed (+ downto 0); Signal out & signed C4 downto); signal outa + signed Cs deunta ©, begin LUT + osittvmélic — conitaa post mp Coun => fn), s1est => out! , MEGA => outs, Hess => oul 8); Poocens begin wit fost ony:eng e ® int c= “Ooovor"; —- Wott; end process 5 end dalaflow ; Avathnettc paral fons on Tuo Eft - bet Asoays fo VHDL Irberey leee; Uge eee. numetic - etd all; eaitity ontthmélte - opesailions 5x Pos Cumt . %n unigned C4 dowito 0); AUB © On oniigoed (7 downto 0); Hes + oot unsigned CF dunto 0); mesa : ut unatgaed C3 chunto 0); FESS: oot unrigned (3 dounto 0 9; HEH? gut Unajgned Cay downto 0); ESS Zoot unsigned CF dourto 0; Hes : oat united CF dura 0); mest out ungfgred (4 downtao )) 5 end cotthmeic operations ; omekgtectone dataflow — model of orfithmalte gperdltons $x begin -- Addition SeS\ f= Num} + NMR 5 ~- subtsact ion =MSL <= Mumg - NMI ; S38 < = Numi - numa 5 ~ = moltyplicatton Ses <= numt * numg; —- dviston Tess <= Num | Numi 5 ~- Modulos SESE C= numa mod num; ~~ Stemdindes EST L= Numa Tem nunt ; ond dototloy _ model ; Hee, the tuo Sight bit Goonyk ane token a2 “ ooooine and “ootoo tts". Astthmeke operon setts one poniided below. Fg! Result OF astithmelic gpenaliens on tio Ciqht-bit araye in VHDL “Objects | Nome | valog Ola Tyre | WM [4:0] 00001116 Peery fQlFs02 OOloon Peony out 1320} Otto 101 Asetay \ . Out 2 C420 000 Noo) frevay lot $17207 root AScroy lout y (isto 000006 te00 1600 10 Ascray lout C7201 |aogocoto Asory jout € [7:03 | caooton Asma out #_ C720} | Coooto u __ Asovayote Qe @ The thd example sr cofthmelic aperilion bored on exdrpler Con Fixed -potat nunbor with Uag.y forxmat ) Hore, Fayed Poiat umber one srepsresealed by tuo 12 bst Sapal Qsemy4t Avi and uma. The Coseespandig VHDL desesdptran ‘ig given helow. The RIL gchemilte of “his desceaglion % He Same Or In shown above - Oly number of wiser Uned in operalions dyffer. “To be conssflent ulth fine - potit axtthmthic option exampler, We conibuet the tethench file + Here , tuo arrays ane provided . Ax to Fhe prevfoox example , the seades ‘Gun obsewe that vesotts oblteind here aoe the sime Ox shown (eld above. Faq! Real of astithondtic: operations on two 1 L3t ovonys ia vi ee am -NOme FI Citz0J 0000 W010 | Asoiay FnaCro] Ooo OV. | Ascty ot (C4150 Oooliooto loo | Arcray | Out ALit.0] Wrooriottoe | Ascoy | | outs (11:0) Conpon Aggot0 Necowre-tteo | Ascioy Out 493-01 Coooe Lovslo 1tocsole too | Astay OtS CUT Epoe00000010 | Asomy Ol 6LW0I Cooorotioote | Asetoy ot 7 TW:01 Ooeatg toate Asoray| siotler vellg all cothmetie operation, can be Perfotwned withoct ony dificotty 9a VHOL OR con be seen Ole Therelome, we usli rat expe dedicated arfthmatic operation Cot tq the fallouing chapter. we should wow the reader aboct pmultsplcalson gai diviston operlions at thix paid ANbowh there operation con be perfasoned the hestly dina the FraA resoudteer - Thesefore, mulfpltcatton and dSvi sion Qperdtions should be awotded shenever posribile. Concédenalion gponlos' The concdlendtten oparlesr in WHOL ollowr mayag two OH Morte oSomye + THir ty gore by the % operdlon. lel Jie ay Cample Aprume tat we woth to mene “tuo army Numt and num& .we can do thir by nvm & omg . The datotlw model of cncilentton operition on osenays Coe shown below + Here» two Numi and Numa ose Qncilended The RTL Sehemolic of THis descatiption u gfiven Leow “Testbench file 4 fost Aséthmelic opeudiont on Two Eight. Ist oxmays in vil ereee 9 Eo libstory ieee; Use ieee . numertic- Std - olf; eility onitthnalic — apendlion th % end onithmelte - opestilions th 5 Gndvtedune dataflow of ootithmilic . operitions th t, Conporen antithmilic — openilsons Posit Crum) + ta Unsigned C downto 0); uma i In unilqrel CF dewirtoo); Sest + oot vngigned C3 dunto 0); wes: ait vnatgned (9 dhuto 0); HSS + get unsigaed C4 downto 0); HEH Que unsigned Cis downte 0), mess gut unsigned Ca deunto o ); ses6: oat unsigned (4 deunto 0); aest? out Unatoned G7 downto 0); end component 5 Sigal tnt + unsigned C9 deunto 0; Smal nd unvigned (4 downto 0); Sorat out + varfgned (4 downta 0); ‘gral wt2 - unsigned GF deuntoo); ‘Sina outs + unsigned G dwunto 0); and auth - unatgned C15 downto 09; signal oto; unsigned (+ dowatoa ); ‘Signal out € : unsigned (3 deunto 0);Signal out + + unrtgned ( downto 0); begin LUT + astthmette - opsrittons past map (num =>ial, Nume =fna, segt => outt, mesa =>oula , sesg =Soutg, xesk =routy , mess =y outs, mesg => dute , MeS7 => outF)5 Paocers begin ust a1 SRS Inf <= “gooonre” 5 [598 €= NOoIeN”; -- dit ; end process 5 ond dato low 5 Acithiaic Qporatiom on Tao 12-4H Ascays tov | Kbstasy ieee 5 URE eee + Numeric - std all ; ofty oxfthmitic operon vee 4 ts Pod Coun) + 9a unatgred CLL doweka 0; num& = % unatgred CU doweto 0); Et out unvgned C11 dawata 0); mesa : oat unfqned Cy dowate a); Sess: oot Unaigned Cli duke 0); Mecu’ nuk Onstoned £92 duwata ay?% hs, wna 4 . © sess: ot unity ned Clr douilo 0); aes6 2 ovt us CA dowsto 0; 3es 7 + oct unsigned C1 duuinta 0); end anttthmdic_o penitfon ve s- bs ‘cochitectune dalatlow-model of dstithwalre ~ operaltons vas 5% begin ~ = Odds tion Hest <= Numt + numa, ~~ subtraction MESA <= Numa - Numi 5 TRS J ez num - Numa, ~~ multiplicaiion Hesh e= Num * numa; ~~ divisdon Hess c= numa / num; ~~ modulus ese <= mums mod numt; ~~ emdindesr HES? <= NUMA Tem NUM; end dolatlow - model 5 TTesthench file fox Aor Avtthonstic operations on Two ig_beh Ascnay# ty VHDL:Isboreoy ieee ; One Teee - numeste . std + all; wlity artthmetic ~ opouibtont yas uth Ta end astthmetic . gperaltona - ver 4th; ancksteetuse dataflow of axtthmetiec - opordtions ~ ves.4 tb fa componest onfithmetic — apendliont . ve 8-4 Pos Cromt 2% vawigned Cu dauaty o); num. in unaigaed Cit downto 0); Hest + Oat onafined C1 dounto 0 Hesa s Out unstgoed (1 dounto 0; ness > Oat onsgoed (4) dounto ¢), sesy > out vnfigned C82 downto oY) Hess: oil varoed Cr dovito 0); ' HeS6 soot unaignd Cn dante 0); west aol vnitgetl Cu dato g 9): end component _ Signal Gat + urrtgned Cur dowato o ); » Stonal toa: unsigned (11 deusto o; signa out: tansigned Cir doweto 0); Sena ota : unsigned CN daanto 0); Signol Ost + unstqned Ct doonto 0); | signed outh : unnigned C38 downto 0); signal ost ; unsigned Cy dowste 0), | signal out 6 : unsigned C1 dowota 0);nal out? : unifgned Ctl dewdlo 0); iti ® beafn, bur + osfithmette —aperdlions -ues-4 post map Caumt => Fat, AMA => Ing, HEsr=>r out, mesg => oA , Hess => outs , mesh -routh) mess=> outs , tee => ote, Hest => cut? ); Paocers begfn wort for ar 5 fn <= “Qooo ir ooote's WA Z= Qeloomrore’; ~~ udfit 5 end pswocery ; ond dotaftow ; Concalendion Qporition in vant: Irberamy ieee ; Une Vee. std _lagte - UbK all; ertity Coocalendte i Post Cnum\ Fn std - lagi _veeton (3 downto o ); numa 24a std— logic vecton C# duvide 0); Hest + out std -agic_veclon Cis downto o »; end Concitnite ;cnclitechine dalatlow - model of wncdlendle 4x begin Ses) <= numt & Numa ; end datotlaw — model » Here , two dodys one taken at “tere” ond “Coootn)’ The obtained xeult will be the some ox chown above. Applications On Dale. typer and Opendlasts * In Hts secbion, we ufll conitewat 0 posnitive culeulitan ty odd » sublsmet , multiply yond divide two fox bHt nunbore on the Loayt 3 board. Eppit bite and the apesalion type 48 | eensciaul by susttcher on the board. dilpal Wt volocr axe Stepreneated by LED's dn the board + Jn below we provide Veiloy desesgstion af te colcudonweir Chik @ {fe nang lcs Cred My ata-typr_ a epaens [Here We are tttoduced Several Operators to | Process data Poy thts Chaptey+ the alm heve | byting to Show the eacdey How these are Tmple mented th an EPEAstherefove, he ev She Can qracp The fundamental Tdea Po urtng mic device» Note “that pee Tplementations Provided Inthe Sectfo ave Not Untque + “hey aye the ones provided by Vevado + In Mhewworde, we ave bound by Vivadele opti ezatton +O04 Rey qenevat fag these Tenplementat tance, test bench fe Fox concatenattan operatton ty Veto Woravy Jeee + use feee,stel-legic—ll64 -all ! tneity concaternte-tbh te end concatenate-th* archttecture ataflon -of Concatenate th Ps Component concatenate Port Crum 4 fo Stdtogte vector | 4 downto 0}¢ NuM 2. Ba Std_tog&e vector (4 downto 0): Teel § Gut Std lagte —vectem (ts downto oe end Compo Dent 2 [Sat Tol § Std—logPe- vector C4 downto oy! |eiQnat Pn2- 4 std logic. vector bt downto ole signal Out { ¢ Std logfe_vectox ¢ is-dowmto 9)+ begtn UOT $ concatenate Port Map Cnum=y fat, mums => fo, vebl =yout 1)¢pro ce ge" begin Qtalt Fox sno + Mes Me tg” fa are ‘ , “ ovoottt’ end processes Lend clatat tou t | Pirpleme mation Detaiis OF Vector Operations v— ee '0 Show Frplementotton detadts on thte deéceviptton, letls set the Topas Vector Aength +0 four ac fopar [3:07 cumt. vot “PS News Com Vector entry f Sete cted Casstgn veole 4, Sub Part of a Vector PR gelect boa Vector btt ovder 2 ® Spectre url C3) y ed Cacstgn veo + MoraIts3}) Fa reverhed +Pptey Sgeebrio end ome Med TeTeel deserviprton fry Vivado , tS Schemmatfe warn pe O45 Shown fry Gave . AS per “the dfgram at Thpur foutpur Porta ave. Used Fr the Trnple mentatfan, Rectdes + @ach Popa OY Ourpur pevt hag an associated bupfey totth fre. Moreover» ONly tatrfng 84 done between tape and oukput poyts + therefove , thts Penpterme ntatfon, | ong wsed Trpuc Joutpat blocks And frterconnece Mfesources From the EpaA bloucs troduced Mm Sectton,a A PH | cunt yeor T pete > aut ann t -teor CH-Fact a muenl_IBur C2. fat \ TBF erat 8 wech cer - FOS Ceut seca OBUF EO 1 L-ieur iE EY) = eon -OBUEEN S, \ OBor eres 3- OBUE Co)- ast pa OBUE. rece DBUFLIJ fase t a : BUF vec 3.ogue C2} thst aan (e0r 1 Dunn. 1a Cay Fas OBUE ie 63. OURS} frat TBoe Tet Fost sas Frat Lean mpl R 4% Fee ‘plernent at fan. + Vedloy Ope vattoneCaleutat Pmplemented onthe Bosyss Board Fn Vert log | — — = 9 a MOdute Calculator ted MS OTAE YT and Sw as swage 2S) Output £13 6} ted: elie TT 10} acddetton 2 wore [72 oD Subtraction + Wye Tre ol MUItT platter . We T+ oC} Afviston + Ossian addtiton = SWOT 4 J+ SWT350}3 jASS ry Subtyattion = SOT14 42) ~ So Brols F4I* gorsgol: sw Csza): jOSsqn MULE Kaa Yon, = swt pssige AtvecFon — SOT ay / lacetgn ted e C{e fosw sit} & AsCvsw lal} & addi fan 4. (£2 few CaTyt & {stvswralyp & Subtrackton) 4 ({a(vsutel}] & {2fswtal pf} & TRUCE Patty | (La {sw lel ht &Lafswrary} Exdfvesfon) + end module*wd GA Enpexctng Vivade to Use Dep Block th —Artthmetfe operat Fone Fy Veltlog ( * Use _ dcp4g = tyes” *) module addfttdn ~ operatton_depasCnumy mun 2, yest): opat (140) numt: fopac C140) ums Qutpat [1% 0) vests Assign VveSl= nNuUMlL+ num: end moelele » Ope yatfors fy VHDL. (brary feee? Ure Peee npymentc stds ati: entity addfcton ~ opevatfon-dep4e fc Post Lnuml tte unsigned (4 downto oO)! numa & Tr Unsigned (4 downto oy: ect ¢ Out unsigned (4 downto oy ativipute Use_dep4e.t stving . attypute Ure fend add fon Opevatton _Acpae s arthitecture Aataflow model adder operaxti = n begtn MECLZ= Numi 4 NUM> © end catafiow - Modet ¢ Enporcinrg Vivado -fo Use Dep Block Pm ArEth met Fe ygorcing Vivadlo ‘ p el iC a ~dcp4g of addtt fon ~ opevatton—depa e $ entte Ps yeo"s ~Aspae reIngemar Schermatic Shout emphaste that no jvar fable ox memory element Ts Used frthe Aesfn ac Fry | Prograrnming shanquage . ony wotvee and ports aie Used, [the fe alee “the case Foy concatenation and repli carton | operat fons “Leple mentation Detat ic Of PrP thenette Gperatldns ¢ - | =e — —s Z Yenptementting axtinmett operatfanc Ph -the FPGA fs an Fmportant -topte by Tteetf + therefore » tetle Closely Janatye Tmplementatton cletalla OF “the descyiptiOn In above To UNderstand how evade Trnplements — ayfthmet i Operatfons + let's focuc onthe addttton Operatfon . AC inthe prevfous Sect fon ; tetle Spply addFifen on tus two-btt vectors + Schematte Of the clecevipt Fon artery Suynthe sfc wit! be ac chown PH C&urxe . “the Odditfor epevatfon fe fmplemented by two LUt's fy the Fparn- “tbe avehitecture fy ure % Kept when Subtraction , muttipttcatfon and dFvisfon aqperationc ave Emplemented . rttowevev, “the veacley Shoulcl memembey “thar “these Opevattonc ave Aone On two Vectors each having [two -brtc « rf “the veetov length Fc frereaced » NOsource Usage Afiference between aytthmet Opex at Fone became move OPppayenc. Foy eg When eat aba bit addftfon . subtiactten MULeETPLE cat ny and Aviston epevatfons Mm kfsted are Tnplementedet Pe rablons ‘9 Separately, acklfrton and Scbtract Fon Opera tOOe ® aes wr need et Lor's. | | | | t 1 | i | cost ag cots por 09) pares leur Fo} tose 3 9 VESILI2 oO} TRUE ur Cry Ans wy se 4 OBOF | | i | PGR Toplenmrentatfonofe addPrton Operas Grn { However, mutetpitcatton and AivPefon operatfone WI Aeeg jet and 6q LUTE Ye pecttrely . Moreover Cf the birt dengih & 12 Ge then addFttan and Subtryactfan | operations wr Geed : ngneased tO {2 Luts » the muttiptPeat fon, ' | Operateton USF Deed one Dep block. the atveckon j CPeratton wll Need 155 Lute. | ence the Mult tpl care Land aff Vicor Operation frp plementatfone Peed 2 ertkensive number ©F Luts ov Bsp blocke. Note. “that Lut and Dep Deage OumMbere aye Obtained ObEng -tools-we Can enforce vivado ~tp Sqmhe cPze arPihmett ec | Operatfons sth Dep block . the Way tole “th Py | vel?log Pe add Fog attirtbutre t* Use-dept@ eS yest Fn Foon lope module to be handted -thfe Wag + we py lan example. tlere phe oddBfan © sting the Dep block - fr VHOL > the. IM one bey odd ing Ovide Such Peratfon Pg Eorplemersted Same. Operation can be an attrPoute th the Port cle fen Fron part AYE pete OPeratfona ave Fmplemented 2Fthey the Enea. Becfdes , Apat fowrpur — blocs ove. Deeded dunt There Pe one cata +o be Proce SSed Afyoct ource. beage + MULEEP LEeatton and dfvec ton operation Macy Vequlse healg Vesouvce Usage When Hthe data atk trcveasec fesuer hye OFFecez -the veg, fmporta nt teoe @ Enthy pOTER tet C MEE wa lege? enea GM , Combinational chicutl, A digital systern can be froplemented in two forms. Sn the | Bist one, the oulput depends on cusrent fnput only this dorm can be vealtzed by combinational circuits. Sy tre second dorm, outpub depends on post tnpub or | ovbput values besfdes the current fnput A combirabioral circuth 15 composed of Logie gates 40 perlorm a Specttte task- To understand the evorking prindgeles | ot o comblrabtoncd etreutt, we usll shart sth baste deftnttions Then, We ofl reviec Jogie gate, hom a corsktnakonal Git) Ub. we will Sotroduee Jools to analyze combi nalrorad aca woe wil explore how o combinattonal ctveuth car be trnplem; ented on an Seid - proqrcwomatole gate anvau Gers). Then, | wit evaluate cortnabtonal civatt design: Logic Gales z- we how Inbroduced logie gates Be digital dle chronte. devices. we revteu there by foceesing on thelr cormbinaltonal chovactevishtes- Morover, we provide hhard-uwore description Sangu lage Chow) desevieton of att logic gates considered here. Bet the ok Gabe - Not 4s the Hysh loge gate to be considered Sb fs achuatly an inverter with Single fnguk and output. Let's assume that ‘input to the Not gate fg wepresented by rroa ‘Binary vertoble x; ord Set culeut of the gate be binary variable Yy- then, the Mot gate can be represented by the logte funckion yor Truth Jable of the wor qete based on thts Doge duntion with be a %n Table 31 Sy robo! o} the Not qote for Its Jogic tandion is as tn Fy 3 Snput | oubeut x Zex oO ' ! o Tolle 3-1 Twh Table of she NOT Gabe * xt Figure 3-1 Sy vo bal of the Wort ae the wot Gabe to vil — the VDL keyword ov the Nor gete 1s rot using th we Can describe the logic dandion yeh os Jollows: Mbyary ieee ; use tece.shd_ logic teu all; eotthy vol_gate is port Ox: tin Shi Sogie j ys out shiSogic) B end wolgode ; avdtlectue dolatlou model ot rolgote is begin y2= nol x; end dalaflous_roodel +2 OR 48 the second logic gate lo be considered. df ray have 40 OF roe Anpuls. Hocoever, the gote has one oulpul. the wor ns principles of the o@ gate ore as follows » whenever ony ok the inputs bas value |, output ofll be 4. oukpub uf! be O and only Walt inpubs have value 0: To represent the tnpul! oukpub charockerislics of the oR gofe, Let's assure tk has two ‘inputs as Vinay values sand y >and Seb output of the gk bbe Binony vortable z-the operakor to represen} she oe gale s+" Rosed on thee, the Fuso “inpul OR gake can be wpocs- hnted by the Soxie ferabion 2= ey: the truth table of the OR |apte bored on this hogte tundion will be os fin Table 32, | the syyobol of tre oR gole fos this logic funcion (18 as in i. Be Smvpucts oubput Zexty ° 1 ' --oo/f ° \ oO 1 \ ' Fy 37! Tsuth Table of o2 gabe ¥ y xy Fa 32 Syrobol of the or qate- ees",* y my | Fa 33: Syrobol doy the Nor qote A NoT gic can be woneced fo the oubpul of dhe an-goe: Tis corabiralfon dorms the Mog (wor-or) gake. As tm the on gale, | Jets assume “puts of this qete be zepreserted by binary vor) fables Land y; and Let oubeat of the gabe be binary vervalole Eee the hwo-inpub atoR gate can be represented by the Segte durdion z= ty. the truth table ch the slog goke bored on this Jogie fundion il be os tn table 3 3 only ovt-puk value ait | oe fnverted. the Syrabch of the noe qoke for thts dog: S$ as An Fiq 33 the OP Gale §in VHDL the vane keyword dor oP gale is ox. USing ih we Can dscr'be tt Function ‘the foie lunction Zexey a8 follows: | Mbrowy ‘eee; Use ieee.shd Sonic 1164.all; enlihy orgole ts Port Ox: in Std logs Yite std Sogic » Bs ouk to: end O_gote; Se toys archthechure dalatlow model of Orgate is beqin 2 =x ory, end dotaPlow model;5 [the auto Gale AND is the tied Logie gale fo be considered. Ag tin the oR gle wag hove juo or move inpubs: tpowever, T+ has one output ie working principles of the AYO gate axe ar follows wheneey all ob ths fnputs have vebue 1, outpul uSil bet. oukpat ustl be o thang of Fhe finpuls has value 0.10 repraent tnputloutpak chaxecleristis Ok the AND. qote. He's assume two inpuls as Binary varfables cand yj ond jel oubeut of the gate be birany veriable z opurator Jo represent the AND gele fg “eT. Based On these, the two-impub AND get can be represented Loy the ogte function z= XY the truth Jable of te ASD ote based on this Yogic function uf! be as ‘in table 34 he Syrobok ok the an qete for th’s Sogte launchd os fs Fq 34 ww Fig aye syrotooh ot the AND hate . A NOT qote can be comnected to oulpul of the AND gate. the combination forms the Nand gate -AS tn the AWD qote. Gea's assure ‘imeud to Hts gate be binary variables cand y; and output of the qote be binary variable 2 then, the }wo ~inpud MAND gore can be represented by the Bogie Function z= x-y. the teak lable of the xAND qete jbased on this logic functton afl be os tm Table s-ty-orly eubpudé [values wit tee Srverted the syrmbol of the HAND goke for ahi loyre fundtion 45. 08 fo Frq 35 Jneuts oukpuk x ¥ Za Ly oO o oO o ot ° ' o oa ) to} og 4 Table 34: Truth Talohe of the ANID Gabe DD» y xy Fg 3-5; Symbol of the HAND Gote it \= e v ote An VHDL she vie keyword for the ann gode ts and: using th, we can 1 Besertbe the logic Eunction Bexry. a follows : Mbrory ‘eee ; Use feee.Std_Vogic_iley all ; enttly ard gate is port (x: fn std Negic j yx to std logic; Zs oub sd Nogicd; end and_gote ; avchilectuve catatlocs_model ol ardagadte i¢ begin Zes Kard y¥; end datatlow_mode;v the 208 Gate the fourth and Mnal fogic gate to be considered 45 xoR (Cxclus: ive -08): THs goke can be constaucled by using. Ant,og,on8 oT goles theelore, tk may on maynot be taken as a dundoentat Bogie gatke- However, xoR 1s used tin Combtnattanal ctrcutt-therelore we explore th tn His geclfon. The working patnetples of the xon gale: are as dale when wo ‘finds of he gqete hee the Some logic Gevel sks outpuk ell be 0. wherever the 4u0 ‘inpuls of the gate hove di Herent Yogic levels ,t4s oukpub will be 1. To represent Inputloukpub chaveclertstes of dhe 10F) gete based on nis delintlton, Jet's assure dwo tpuls as Brory vovfalales cand y. Let oukeub ot the gate be kirory voxtable 2. then Awo-frpub xor gate con be veprsenied by the Jog te Juve Kon 22 Lagyr lay) this logic lundion can be sivmplitied by using the “@" operator to vepreent the mor gate os z= OY the truth dabble a the or gate besed on this Sogic dundion UB be as fin Table 5 the Syrelool of the xop gabe for His togie function 45 03 rq 36. dnpuds output | x ¥: B=xOy o Oo 9 °o 4 ! 1 0 \ ( i 0 | | iq a6 Teulh table ob the NOR Gate .D+ Fiq 3:6: Syrobol of the x0r Gate a et XOR Gy fn VHDL { the VHDL Keyword for the ror gale ts nor. using Heecan descriloe the. Sogte tuncton z= Oy as follows : Mhray tee ; ase. teee std _logie_itbu-all; entthy xor_gate ‘is port Cx: tn std logic ; Yitin std logic; Bout std bogie); tnd ror-gate; lavchtheture datatloredel of xor.gale is begin Z Lexy y; end dolotlow_modet » Combinaltenel efyeutl Analysts — Logic gale tnhoduced im the previous Section can be Used to Conshuct Corobinational cacils. to understand the coorking Ping plas ob a Wrmbinationnl ercatt, ve ghoutd analyze th. therefos wor thoutd Kast dorm a Sogic dunction between ths ‘neut & oubpul db needed, we can also fam the Huth table of combinationak creat based 09 this vepresenlation. the Binal slep to analysis “s xepresenting Me lominalional chrauth by Sess elements, udktch ts calla bZs Dstaarey hue Lead 40 Snputloutput character cvcutt as follows: 4q isles of the el | 22 (O60 @ Grup cae | this logte onan discon by an Hol in an | FPGA However, Some Siropltttcafons can be done on tt before its | |sieplanaethtedes Merk we estil consider hou Hhts an be done: Boalecn slacbra | We can benelitt rom Boolean algebra dor qate-level hint mization Boolean dacbra is the Prameuwork to sepresent and amabyre Sogie funckons foamed by binary variables ond logte gots , Beolear algetra can le explained tn a Vigorous woy ting mmathemakical delirtitons. However, we will fake a Sergler| approach tn Hs book. the tdea 4s fo cover haste deltrttrons, ol Boolean algebra Necessary for oux purposes. First, we wofll review boste dentthtes by Boolean alge: bre Let's assume tio Bnary Noviables x and Ye we Can define, Sdenttes on AND and OR gate as In Table 36-Although the Sdeniflies cam be jut by vsing a truth table, He reader con Consult te wertioned yelerene for mor. Vigorous Prod Nett, we will review beste Boolear, algebra, properties Om AND, OR, and wot qotes - these ore Anvolulion, coramutalive, arsocialtve, dishibMve and absorption Properties and Derorgan’s theory ax gunmnarized Gin Table aq. dnvollton Property tals]Fgotetod reining zation. Legis Tondlfen Founation belucen Inpuk and oubpul he Hck see ‘iy analyzing 0 torbtnaltonal etreuth ts fom fing the Logie dundion tehween ts tnpuls and oobpul Here, toe assume thak the Corresponding cheuth dtagrors is ob hand: then, we shouts “seag” dys dtagrars. Let's give a sireple, tenet Hise Frat a combinational circu has been destqred belowe hand by discrebe logic gets as %m q Br- we word Like bo torr the Corresponding Sogtc uncon. + 7 SE. > Fig 3! ch cutt Fegvarn of a wroblrabtonal Grcutt- dn Fy 39, ue specibicatly Sabeled orput oF each logic qate by a Binary varialle-Based on thee, we Can represent tnpublouded chovackerts} fos of the Cormbinabto rad efrcutt To do so, ux fest obtety Oubpud dt each Logie gale Sepeuately cs follows : Zlzx- 225 ey Bee th eg 25 = 2GI22_. 0 [4S trak applying wor on a Birary vorfatle Hotce gives Hs oni [Nols covomnutetive properly sells Us thal the ordex of vertables im Sogie gates is rob troportant Assoctods ve. Property tells es thed Ain end O8 operakions owe disht buktve ory each other AS the name Troplis ,absesphion pro erty dfsca: fi pevty ads, STEEL EBay variables. the wader fon remember ' Demorgars Hheorers as follows. jp the wor operation 1% applted On A> ANE ov OR optralfon,inpuls will be Inverted Move-pver, the opers- WW be changed thom Avo to OR or vice Versa -Agctin, vigoroul proof of thus, Proper} aon wil fs can be found. yond o8uFto}test ° Do lege yond _oeprLiLtest 4A Y_and(3:0) Yeandonurt).ish : 2, ‘aur Y-arLoRur(aL inst o 3, out yor-ogurco} st ives a} y.ov(3:03 OBUF | px or-ogurtii-inst ° sn ‘oRur {ov-0BUF [2] -tnst © 3 Ono Yor oRUF(s) inst o 3 our Fiq BB: Syotherte Tauks of Boolean fdentrtresthe of gate [the Art gale X40 =O . Ube! See |_xeper | Fiq 3-6 Boolean Algebra fdentrlies. Beolten sdenttly operations tm yupie Moroay Kece ; use Nece Std _egie ney all; Cottly Boolean tently #5 Pou Cx 2 ny Std_logte ; Y_ots oud td_ fogie_vectos C2 downto 0); ‘Land: out Std_logie_vectos C3 dovanto 0)); end Boolean. 4 denttly ; oxckitecture dataHlow moda of Boolean_t dent tly ts Constant one vakdlogte : = torstan 2410 ¢ S4d_logic + beatin Y-ovlo) z= 20 x or 2410; Yor) L= x or ore, Yoru) l= orx; Y0V03) d= x or rot x; Yard (9) <=xX and ‘Zex0 ) Yond) 2= x ard ore; Y-and(2) <= x and x ; Yuand¢3) <= % and not ay tnd dadatlow_roodet;Property : ne Snvolution Tau Cormmatattie | aug = yee wy yee Associattye deelytzd= Gaby te, Uelyez) = Gey)2, Dist bultve Roly tara Cerg) + 2) 24 (yea = Cay): Cray AbsorpHon Le Goyder SOY) =e DEMoIGarss teerern ay 2 gq 4 ety Table 3.9: Boolean Algebra properties on AD oR. and HOT operations . Inputs outPul |x z Gatetevd rfininization otros to Seoplthy npulloutpuk chowactertekes of a Lombi natvonal chrauth the tdea here 16 ob | Jointing the Sore truth table cwith bess murober of Nogic gots Ts | Operakton can be done using Boolean algebra i dentittes and properKes inlbroduced In tHe previous secon, However, this vequtves expertise: there ax also very eidective — rethads fos gale-level mininstzation TT