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11127J PDF
11127J PDF
28C17A
16K (2K x 8) CMOS EEPROM
2 RDY/BSY
• Fast Read Access Time—150 ns RDY/BSY •1 28 Vcc
32 Vcc
31 WE
3 NC
1 NU
30 NC
NC 2 27 WE
4 A7
• CMOS Technology for Low Power Dissipation A7 3 26 NC
- 30 mA Active A6 4 25 A8 A6 5 29 A8
- 100 µA Standby
DIP/SOIC
A5 5 24 A9 A5 6 28 A9
A4 6 23 NC A4 7 27 NC
• Fast Byte Write Time—200 µs or 1 ms
PLCC
A3 7 22 OE A3 8 26 NC
A2 8 21 A10 A2 9 25 OE
• Data Retention >200 years A1 9 20 CE A1 10 24 A10
14
15
16
17
18
19
20
- Internal Control Timer I/O2 13 16 I/O4
I/O1
I/O2
Vss
NU
I/O3
I/O4
I/O5
- Auto-Clear Before Write Operation VSS 14 15 I/O3
- On-Chip Address and Data Latches • Pin 1 indicator on PLCC on top of package
• Data Polling; Ready/Busy
• Chip Clear Operation BLOCK DIAGRAM
• Enhanced Data Protection I/O0 I/O7
- VCC Detector
- Pulse Filter VSS
Data Protection
- Write Inhibit VCC
Circuitry
• Electronic Signature for Device Identification CE Chip Enable/
Output Enable
• 5-Volt-Only Operation OE Control Logic
• Organized 2Kx8 JEDEC Standard Pinout WE Auto Erase/Write Data Input/Output
Rdy/ Timing Poll Buffers
- 28 Pin Dual-In-Line Package Busy
Program Voltage
- 32-Pin PLCC Package Generation
• Available for Extended Temperature Ranges: A0
- Commercial: 0°C to +70°C Y Y Gating
Decoder
L
- Industrial: -40°C to +85°C a
t
c
DESCRIPTION h
e X 16K bit
s Decoder Cell Matrix
The Microchip Technology Inc. 28C17A is a CMOS 16K non-
volatile electrically Erasable PROM. The 28C17A is A10
accessed like a static RAM for the read or write cycles with-
out the need of external components. During a “byte write”,
the address and data are latched internally, freeing the micro-
processor address and data bus for other operations. Fol-
lowing the initiation of write cycle, the device will go to a busy
state and automatically clear and write the latched data using
an internal control timer. To determine when the write cycle
is complete, the user has a choice of monitoring the Ready/
Busy output or using Data polling. The Ready/Busy pin is an
open drain output, which allows easy configuration in wired-
or systems. Alternatively, Data polling allows the user to read
the location last written to when the write operation is com-
plete. CMOS design and processing enables this part to be
used in systems where reduced power consumption and reli-
ability are required. A complete family of packages is offered
to provide the utmost flexibility in applications.
VCC and input voltages w.r.t. VSS ....... -0.6V to + 6.25V A0 - A10 Address Inputs
Voltage on OE w.r.t. VSS...................... -0.6V to +13.5V CE Chip Enable
Voltage on A9 w.r.t. VSS ...................... -0.6V to +13.5V
OE Output Enable
Output Voltage w.r.t. VSS .................-0.6V to VCC+0.6V
WE Write Enable
Storage temperature ..........................-65°C to +125°C
I/O0 - I/O7 Data Inputs/Outputs
Ambient temp. with power applied .......-50°C to +95°C
*Notice: Stresses above those listed under “Maximum Ratings” RDY/Busy Ready/Busy
may cause permanent damage to the device. This is a stress rat-
VCC +5V Power Supply
ing only and functional operation of the device at those or any
other conditions above those indicated in the operation listings of VSS Ground
this specification is not implied. Exposure to maximum rating con-
ditions for extended periods may affect device reliability. NC No Connect; No Internal Connec-
tion
NU Not Used; No External Connection
is Allowed
AC Testing Waveform: VIH = 2.4V; VIL = 0.45V; VOH = 2.0V; VOL = 0.8V
Output Load: 1 TTL Load + 100 pF
Input Rise and Fall Times: 20 ns
Ambient Temperature: Commercial (C): Tamb = 0°C to +70°C
Industrial (I): Tamb = -40°C to +85°C
V IH
Address Address Valid
V IL
V IH
CE
V IL
t CE(2)
V IH
OE
V IL t OFF(1,3)
t OE(2) t OH
V OH
Data High Z High Z
Valid Output
V OL
t ACC
V IH
WE
V OL
AC Testing Waveform: VIH = 2.4V; VIL = 0.45V; VOH = 2.0V; VOL = 0.8V
Output Load: 1 TTL Load + 100 pF
Input Rise/Fall Times: 20 ns
Ambient Temperature: Commercial (C): Tamb = 0°C to +70°C
Industrial (I): Tamb = -40°C to +85°C
VIH
Address
VIL
t AS t AH
VIH
CE, WE t WPL
VIL t DH
t DV t DS
VIH
Data In
VIL
t OES
VIH
OE
VIL
t OEH
VOH
Rdy/Busy Busy Ready
VOL t DB
t WC
VIH
CE
VIL
VH
OE
VIH
tS tH
tW
VIH
WE
VIL tW = 10ms
tS = tH = 1µs
VH = 12.0V ±0.5V
28C17A F T – 15 I /P
Package: L = Plastic Leaded Chip Carrier (PLCC)
P = Plastic DIP (600 mil)
Temperature Blank = 0°C to +70°C
Range: I = -40°C to +85°C
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.