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  • Turing Comp Inst

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    Noelia Guerrero Álvarez
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    The document describes the instruction set of an ALU (arithmetic logic unit) including instructions to: 1) Add two registers and store the result in a third register (ADDS); 2) Move the value of one register to another (MOV); 3) Decrement a register by 1 (DEC); 4) Load a value from memory into a register using the address in another register (LDR); 5) Load a register with an immediate/constant value (LDR #); and 6) Store the value of a register to memory (STR). It also describes a branch instruction (BVS).

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    Turing_comp_inst

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    The document describes the instruction set of an ALU (arithmetic logic unit) including instructions to: 1) Add two registers and store the result in a third register (ADDS); 2) Move the value of one register to another (MOV); 3) Decrement a register by 1 (DEC); 4) Load a value from memory into a register using the address in another register (LDR); 5) Load a register with an immediate/constant value (LDR #); and 6) Store the value of a register to memory (STR). It also describes a branch instruction (BVS).

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    7 views1 page

    Turing Comp Inst

    Uploaded by

    Noelia Guerrero Álvarez
    The document describes the instruction set of an ALU (arithmetic logic unit) including instructions to: 1) Add two registers and store the result in a third register (ADDS); 2) Move the value of one register to another (MOV); 3) Decrement a register by 1 (DEC); 4) Load a value from memory into a register using the address in another register (LDR); 5) Load a register with an immediate/constant value (LDR #); and 6) Store the value of a register to memory (STR). It also describes a branch instruction (BVS).

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    of 1

    ALU:

    15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
    0 0 WS OP3 OP2 OP1 OP0 RT2 RT1 RT0 RA2 RA1 RA0 RB2 RB1 RB0
    00 1 0110 111 000 001 = 2DC1 = ADDS R7, R0, R1
    00 0 0000 111 000 XXX = 01C0 = MOV R7, R0
    00 0 0101 010 010 XXX = 0A90 = DEC R2
    00 0 0000 000 000 XXX = 0000 = NOP
    LoaD Register:
    15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
    0 1 0 X X X X RT2 RT1 RT0 X X X RB2 RB1 RB0
    010 XXXX 110 XXX 011 = 4183 = LDR R6, [R3]
    LoaD Register #:
    15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
    0 1 1 X X X X RT2 RT1 RT0 X X X X X X
    D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
    011 XXXX 101 XXXXXX 7D12 = 6140 7D12 = LDR R5, #0x7D12
    STore Register:
    15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
    1 0 X X X X X X X X RA2 RA1 RA0 RB2 RB1 RB0
    10 XXXXXXXX 010 100 = 8014 = STR R2, [R4]
    Branch:
    15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
    1 1 CS VS ZS SS X X X X X X X X X X
    PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
    11 0100 XXXXXXXXXX 4E3E = D000 4E3E = BVS 0x4E3E
    2

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