IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO.

12, DECEMBER 1997 2089

A 2.7-V GSM RF Transceiver IC

Taizo Yamawaki, Masaru Kokubo, Member, IEEE, Kiyoshi Irie, Hiroaki Matsui, Kazuaki Hori, Takefumi Endou,
Hiroshi Hagisawa, Tomio Furuya, Yoshimi Shimizu, Makoto Katagishi, and Julian Robert Hildersley

Abstract—A 2.7-V RF transceiver IC is intended for small, low-

cost global system for mobile communications (GSM) handsets.
This chip includes a quadrature modulator (QMOD) and an
offset phase locked loop (OPLL) in the transmit path and a dual
IF receiver that consists of a low noise amplifier (LNA) with
an active-bias circuit, two Gilbert-cell mixers, a programmable
gain linear amplifier (PGA), and a quadrature demodulator
(QDEM). The IC also contains frequency dividers with a very
high frequency voltage controlled oscillator (VHF-VCO) to sim-
plify the receiver design. The system evaluation results are the
phase error of 2.7 rms and the noise transmitted in the GSM
receiving band of 0163 dBc/Hz for transmitters and the reference
sensitivity of 0105 dBm for receivers. Power-control functions are
provided for independent transmit and receive operation. The IC
is implemented by using bipolar technology with fT = 15 GHz,
0 = 150
, and 0.6-m features.
rbb
Index Terms— Active bias circuit, GSM, mobile communica-
tion, offset phase locked loop, programmable gain linear ampli-
fier, radio frequency.
I. INTRODUCTION
T HE needs for small, low-cost, and low-power wireless
transceivers have been growing with the increasingly
widespread use of mobile communication services. Such needs
have promoted the integration of semiconductor devices. Much
effort to integrate RF analog circuits, which are harder to
integrate than lower frequency digital baseband circuits, has
been made [1], and recently the single-chip configuration was
reported [2].
This paper describes a 2.7-V RF transceiver IC for global
systems for mobile communications (GSM). All that is re-
quired to implement a GSM terminal’s RF section is this IC
and a dual synthesizer. We do not include the dual synthesizer
into this IC to avoid digital noise leakage to the analog
block. The characteristic point of this IC is the transmitter
using offset phase locked loop (OPLL) technique. Fig. 1
shows the block diagram of the OPLL. The OPLL consists
of an offset downconverter mixer (OMIX), phase comparator,
Manuscript received June 30, 1997; revised August 11, 1997.
T. Yamawaki and M. Kokubo are with Central Research Laboratory,
Hitachi, Ltd., Kokubunji-shi, Tokyo 185, Japan.
K. Irie, H. Matsui, and K. Hori are with Semiconductor and Integrated
Circuits Division, Hitachi, Ltd., Totsuka-ku, Yokohama-shi 244, Japan.
T. Endou and H. Hagisawa are with Semiconductor and Integrated Circuits
Division, Hitachi, Ltd., Takasaki-shi, Gunma-ken 370, Japan.
T. Furuya is with System Engineering Technical Department 3, Sanwa Koki,
Ltd., Takasaki-shi, Gunma-ken 370, Japan.
Y. Shimizu is with Device Applications Engineering Department, Hitachi
Microcomputer System Ltd., Takasaki-shi, Gunma-ken 370, Japan.
M. Katagishi is with Multimedia Systems R&D Division, Hitachi Ltd.,
Hitachi Ltd., Yokohama-shi 244, Japan.
J. R. Hildersley is with The Technology Partnership plc., Royston, Hert-
fordshire SG8 6EE U.K.
Publisher Item Identifier S 0018-9200(97)08267-X.
0018–9200/97$10.00  1997 IEEE
Fig. 1. Block diagram of OPLL.
loop filter, and transmit voltage controlled oscillator (Tx-
VCO). The OMIX mixes the RF-LO with the Tx-VCO
signal to generate a feedback signal , that is,
The feedback signal is input to one
port of the phase comparator. The Gaussian-filtered minimum
shift keying (GMSK) modulated reference IF signal is
input to the other input port of the phase comparator. The
phase comparator generates an error current proportional to
the phase difference between the feedback signal from the
OMIX and the reference IF signal. This current is filtered by a
loop filter to generate an output voltage which depends on the
GMSK modulation and the desired channel frequency. This
voltage controls the Tx-VCO such that the Tx-VCO output
signal, centered on the correct RF channel, is frequency-
modulated with the original GMSK data. When the OPLL
gets locked to the reference IF signal, the frequency of the
feedback signal gets equal to that of the reference IF signal
. The center frequency of the Tx-VCO is
offset from the RF-LO frequency by
The OPLL acts as a tracking bandpass filter tuned to the
desired channel frequency. This reduces the wideband noise
floor of the modulation and upconversion process. The OPLL
results in a low-noise GMSK modulated signal at . Fig. 2
shows the block diagram of the OPLL transmitter. The OPLL
transmitter consists of quadrature modulator (QMOD), OPLL,
buffer amplifier, power amplifier (PA), and diode switch which
includes a low-pass filter. The QMOD generates the GMSK
modulated IF signal. The diode switch selects the signal paths
and also suppresses the harmonics of the PA output signal.
If the output level of the Tx-VCO is enough to drive the
PA, the buffer amplifier is not necessary. By using the OPLL
technique, a duplexer and a Tx surface acoustic wave (SAW)
filter can be replaced with the diode switch. That means fewer
off-chip components and less power loss of the desired signal;
that is, less current consumption of the PA. The prototype of
the OPLL is the GMSK modulator reported in 1981 [3]. The
important difference between a PLL and the OPLL is that the
frequency modulation of the reference input is reproduced at
the output of the Tx-VCO without scaling.

Authorized licensed use limited to: Foxconn Electronics Inc. Downloaded on January 12, 2009 at 03:00 from IEEE Xplore. Restrictions apply.
2090
Fig. 2. Block diagram of OPLL transmitter.
Fig. 3. System diagram of RF section.
II. ARCHITECTURE
Fig. 3 shows the system diagram of the RF section using
our IC. This IC includes the QMOD and the OPLL in the
transmit path and a dual IF receiver that consists of the
low noise amplifier (LNA) with the active-bias circuit, two
Gilbert cell mixers, the PGA, and the QDEM. The IC also
contains frequency dividers (DIV) with on-chip very high
frequency voltage controlled oscillators (VHF-VCO’s) and the
power control circuit which controls transmit, receive, and idle
modes. Except the LNA and the VHF-VCO, all circuits work
in differential to eliminate common-mode noise.
A. Transmit Path
A GMSK modulated signal is generated at a fixed 270-MHz
IF by the QMOD. The QMOD, which consists of a pair of
Gilbert cell mixers, is fed with quadrature phase (0, 90, 180,
and 270 ) carriers derived from an on-chip 540-MHz VHF-
VCO with a frequency divider. To maintain good performance,
the QMOD uses transistors with 12 times basic emitter size
to improve matching.
Fig. 4 shows a block diagram of the OPLL integrated in the
IC. It consists of a phase comparator, the OMIX, Tx-VCO, a
loop filter, and limiters. The output signal of the QMOD, a
270-MHz GMSK modulated signal, is used as the reference
input to the phase comparator. The OPLL converts it to the
final frequency in the 890 to 915-MHz band using the 1160
to 1185-MHz RF local oscillator (LO).
To integrate the OPLL in the IC, it is important to achieve a
constant gain in the phase comparator and sufficient suppres-
sion of undesired spurs. To ensure the constant gain, we use a
current-output-type phase comparator with input limiters. This
configuration provides a stable loop bandwidth for the OPLL
Authorized licensed use limited to: Foxconn Electronics Inc. Downloaded on January 12, 2009 at 03:00 from IEEE Xplore. Restrictions apply.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 12, DECEMBER 1997
and makes it possible to build the loop filter from simple
passive components. To eliminate undesired spurs, we use on-
chip RC low-pass filters and an off-chip LC filter in the input
paths of the phase comparator.
B. Receive Path
There are three major architectures for the receiver; that is,
direct conversion, single IF, and dual IF. The direct conversion
architecture has some problems such as dc offset and LO
leakage [4], [5]. We select the dual IF (Fig. 5) for two reasons.
One is that it can improve the half-IF problem by using high
first IF (225 MHz) and at the same time it can lower the current
consumption of the PGA and the QDEM by using low second
IF (45 MHz). The other reason is that the use of two IF-SAW
filters allows the relaxation of the isolation requirement for
a package and pins. To reduce the circuit area, the same LO
(540 MHz) is used to generate the LO of the second MIX
and the QDEM with frequency dividers. That makes the total
current consumption nearly equal to the single IF.
The flow of the received signal is as follows. The signal
from the antenna is filtered by the bandpass filter and input
to the LNA. The bias of the LNA is provided by the active
bias circuit. The active bias circuit is the feedback circuit
which monitors the collector current of the LNA and makes
it constant. Good noise performance is required for the GSM
receiver because of the stringent GSM specification of the
reference sensitivity. The main factors that determine the noise
performance are the first filter and the noise figure (NF) of the
LNA. The active bias circuit keeps the NF and the gain of the
LNA constant even when the temperature ( 20 80 ) and
the supply voltage (2.7 3.6 V) vary. The active bias circuit
is also available to an off-chip LNA.
YAMAWAKI et al.: 2.7-V GSM RF TRANSCEIVER IC 2091

Fig. 4. Block diagram of OPLL integrated in the IC.

Fig. 5. Dual IF receiver.

The output signal from the LNA is filtered by the SAW filter, generally off-chip between the QDEM and the baseband LSI,
input to the first MIX, and converted down to the 225 MHz is inserted after the QDEM.
first IF. The LO of the first MIX is generated from the dual
synthesizer. The signal from the first MIX is filtered by the III. CIRCUIT DESIGN
SAW filter, input to the second MIX, and converted down to
the 45 MHz second IF. The 270-MHz LO of the second MIX A. Offset Phase Locked Loop
is provided by the dual synthesizer with a frequency divider.
The important points in adopting the OPLL for use in
The output signal of the second MIX is filtered by the off-
the GSM transceiver are the suppression level of the noise
chip LC filter and input to the PGA. The PGA of our selection
transmitted in the GSM receiving band (Tx noise), the small
is that which controls its gain linearly and continuously, not
phase error, and the fast settling. A sufficient suppression
that which controls its gain by several-dB steps [6]. This type
level of the Tx noise is required to eliminate the duplexer
of PGA is more difficult to design and larger in size, but
and the Tx-SAW filter. The fast settling is required to lower
there are some advantages as follows. Because the relation current consumption of Tx mode because the OPLL is one of
between its control voltage and its gain in dB is linear and the feedback circuits and it needs some settling time before
continuous, all that is required to calculate the control voltage getting stable, so it must be activated before the Tx mode.
is one reference point and a slope. Therefore, the required Fig. 6 shows schematically the OPLL in the -domain. The
memory of the baseband LSI is less than that of the step- term is the phase comparator constant in A/rad, is
controlled PGA. One more advantage is the relaxation of the the loop filter transfer function, and is the Tx-VCO gain
dynamic range of the baseband LSI because of the precise in rad s V. The solution for the phase of the Tx-VCO
decision of the input level to the baseband LSI. output in terms of the reference phase and
The signal amplified by the PGA is input to the QDEM the closed-loop function is given by
and converted down to the I and Q baseband signals. The
45-MHz LO of the QDEM is provided by the dual synthesizer
with frequency dividers. The on-chip low-pass filter, which is

Authorized licensed use limited to: Foxconn Electronics Inc. Downloaded on January 12, 2009 at 03:00 from IEEE Xplore. Restrictions apply.
2092 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 12, DECEMBER 1997

Fig. 6. OPLL in s-domain.

Fig. 8. Phase comparator.

Fig. 7. Closed-loop function of OPLL.

The filter is chosen to set the OPLL to the fourth order. The
fourth order means that the order of in the denominator of the
closed-loop function is fourth. This selection is based on the
suppression level of the Tx noise. Fig. 7 shows an example of
the closed-loop function . The flat 0-dB region is defined
as the loop bandwidth. The input phase variation within the Fig. 9. LNA and active bias.
loop bandwidth is reproduced at the output, and the input phase
variation outside the loop bandwidth is suppressed because of
settle to the transmit frequency. We design the offset current
the minus gain. Namely, the OPLL forms a bandpass filter
coefficient to be 0.4 based on the settling characteristics of
whose bandwidth equals twice the loop bandwidth. When
the OPLL.
designing the OPLL, we must consider the tradeoff between
the Tx noise level and the phase error, which are both related
B. Low Noise Amplifier and Active Bias
to the loop bandwidth. For example, when we design the loop
bandwidth narrower in order to increase the suppression level Fig. 9 shows the LNA and the active bias circuit.
of the Tx noise, the range in which the input phase variation The active bias circuit consists of an operational amplifier,
can be reproduced at the output becomes narrower, so the a constant current supply, and two resistors, and The
phase error gets bigger. The settling time is almost independent value of is times that of . The amplifier senses the
of the loop bandwidth because of the addition of the dc offset difference between , the LNA collector voltage, and ,
current to the phase comparator output (mentioned later). the reference voltage. The output of this operational amplifier,
Fig. 8 shows the phase comparator circuit. It consists of a , controls the base of the LNA through the matching circuit
Gilbert cell and current mirrors. Two signals are input into the . For example, when is 3 mA, is designed to be
Gilbert cell. One is the QMOD output and the other is the three and to be 1 mA. The active bias feedback loop
OMIX output. The bias current, , is fed from the band gap provides a constant current to the LNA and at the same time
reference (BGR) circuit to keep the OPLL bandwidth stable. it reduces the collector voltage of the LNA. The LNA third-
The output of this Gilbert cell is converted into a current signal order input intercept point (IIP3) is greater than 0 dBm for
by current mirrors. This output current is added to the dc offset the on-chip LNA, so there is no severe IIP3 degradation of
current to achieve fast settling. In the standby mode, the reset the LNA caused by the collector-voltage drop. To compensate
switch is connected to the ground and the phase comparator for temperature variation, and have similar structures,
has a zero-voltage output. When the OPLL is activated, the so temperature variations between these two resistors offset
reset switch opens and the offset current charges up the loop each other. The bias current variation is 6% over a 100 C
filter capacitance. The settling time is almost determined by the temperature range from 20 to 80 C. An off-chip LNA can
values of the offset current and the capacitance. The control be used if the matching circuits are not connected to pin1 and
voltage of the Tx-VCO gradually increases then settles at a pin2.
stable level when the frequency of the OMIX is equal to the
QMOD output frequency. If we did not use this offset-current C. Programmable Gain Linear Amplifier
technique, the phase comparator output would drift due to the The gain range of 80 dB is required to the PGA to meet
transistor leakage current, and it would take a long time to the GSM specification; that is, the reference sensitivity of

Authorized licensed use limited to: Foxconn Electronics Inc. Downloaded on January 12, 2009 at 03:00 from IEEE Xplore. Restrictions apply.
YAMAWAKI et al.: 2.7-V GSM RF TRANSCEIVER IC
Fig. 10. PGA.
Fig. 11. Effect of attenuator (ICP versus gain).
102 dBm and the dynamic range of 62 dB. When the
dynamic range of an amplifier is wider, the NF generally
becomes worse. To improve both the NF at the minimum input
level (maximum gain) and the input 1 dB compression point
(ICP) at the maximum input level (minimum gain), we choose
the configuration shown in Fig. 10.
The first stage is the attenuator whose attenuation level is
variable, and the second stage is the gain control amplifier
whose gain is also variable. The linealizer controls the attenu-
ator and the gain control amplifier by its output bias currents
and , and it also compensates for the gain variation
of the PGA due to temperature. The preamplifier is inserted
before the attenuator to keep the input impedance of the PGA
constant. The attenuator and the load of the preamplifier are
connected in parallel. By changing the equivalent resistance
of the attenuator with , the attenuation range of 20 dB
is achieved. This range improves the ICP at the minimum
gain. The gain control amplifier consists of four amplifiers.
The output level of each amplifier is designed not to exceed
the ICP of the followed amplifier. Fig. 11 shows the simulation
result of the attenuator effect to the relation between the gain
and the ICP of the PGA. The ICP at the minimum gain with
the attenuator is 20 dB better than that without the attenuator.
The gain of the PGA is controlled by the control voltage
(0.15–2.3 V) from the baseband LSI. To accomplish
the linear control of the gain, and must be an
exponential function of the . The linealizer does this
conversion. The is divided by the resistors and
Authorized licensed use limited to: Foxconn Electronics Inc. Downloaded on January 12, 2009 at 03:00 from IEEE Xplore. Restrictions apply.
2093
Fig. 12. Tx noise and phase error versus loop bandwidth.
, and the transistor pair, and , generates the current
proportional to the . and are generated by
the transistors and which are used as an exponential
converter.
IV. EXPERIMENTAL RESULTS
A. IC Evaluation
Fig. 12 shows the Tx noise level and the phase error
(measured at the Tx-VCO output) plotted against the loop
bandwidth. The output level of the Tx-VCO is about 0 dBm
into a 50- load. The Tx noise level is shown on the right axis
and the phase error is on the left. The Tx noise level here is the
worst case value; that is, the transmit frequency is 915 MHz
and the Tx noise frequency is 935 MHz. The dominant Tx
noise source is the Tx-VCO when the loop bandwidth is less
than 1 MHz. On the other hand, the phase error is very large
when the loop bandwidth is narrower than 1 MHz. To meet
the GSM specification, at the OPLL output the Tx noise must
be less than 165 dBc/Hz and the phase error must be less
than 2 rms. From Fig. 12, it is clear that the loop bandwidth
between 0.6 and 2.6 MHz is the optimal bandwidth (Opt. BW)
which satisfies the GSM specifications for both characteristics.
Designing the OPLL with a typical bandwidth of 1.6 MHz
allows us to integrate the OPLL into the IC and produce the
transmitter without a duplexer or a Tx-SAW filter.
Fig. 13 shows the single-tone modulated spectrum at
902 MHz. Signals and are 67.7 kHz sinusoidal waves. All
of the spurs, that is, the carrier, the upper side-band (USB), and
the third-order intermodulation (IM3), are less than 40 dBc.
Fig. 14 shows the GMSK modulated spectrum. Here, signals
and are the 511-b pseudorandom sequence (PN9) data.
The spectrum meets the GSM specification. Fig. 15 shows
the control voltage of the Tx-VCO observed by storage
oscilloscope. The settling time from the start to the acquisition
is very fast; just 11 s.
Fig. 16 shows the NF and the gain of the on-chip LNA
plotted against the supply voltage for different temper-
atures. The NF and the gain are 2.4 0.3 dB and 13.1
0.5 dB, respectively. In the case of the off-chip LNA, the NF
and the gain are 1.3 0.1 dB and 16.7 0.2 dB, respectively.
2094
Fig. 13. Single-tone modulated spectrum at OPLL output.
Fig. 14. GMSK modulated spectrum at OPLL output.
Fig. 15. Control voltage of Tx-VCO.
The small variation of the NF and the gain are achieved by
using the active bias circuit.
Fig. 17 shows the relation between the control voltage
and the gain of the PGA for different temperatures.
The gain range of the PGA is from 30 to 50 dB. Namely,
a dynamic range of 80 dB is achieved. The linearity error is
less than 0.8 dB at any 20 dB window. The gain variation
due to temperature is within 3 dB for 20 85 C. The
NF achieves 10.4 dB when the gain is 50 dB, and the ICP
achieves 17.0 dBm when the gain is 30 dB.
B. System Evaluation
The system evaluation board consists of a dual synthesizer,
a PA, and other off-chip components. The OPLL transmitter
consists of the buffer amplifier, PA (Hitachi PF0145) and diode
switch (Fig. 2). The phase error is 2.7 rms and the Tx noise is
163 dBc/Hz at antenna when the loop bandwidth is 1.6 MHz.
Both results meet the GSM specification; that is, 5 rms and
Authorized licensed use limited to: Foxconn Electronics Inc. Downloaded on January 12, 2009 at 03:00 from IEEE Xplore. Restrictions apply.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 12, DECEMBER 1997
Fig. 16. NF and gain of LNA.
Fig. 17. Gain of PGA versus control voltage VCONT .
Fig. 18. Measurement system of Rx band.
162 dBc/Hz, respectively. Fig. 18 shows the measurement
system which we use to check the spurs in the Rx band. The
Tx signal is suppressed about 50 dB by using the Rx-bandpass
filter characteristics of the duplexers. The gain in the Rx band
is about 8 dB. Fig. 19 shows the spectrum observed at the
output of the measurement system. It is clear that no undesired
spurs exist in the Rx band.
GSM specifies that the residual bit error rate (RBER) should
be less than 2% under the conditions shown in Table I at
102 dBm into the receiver; that is, the reference sensitivity.
Fig. 20 shows the measured RBER with off-chip LNA. The
reference sensitivity is 105 dBm for the on-chip LNA or
106 dBm for the off-chip LNA. Both results meet the GSM
specification of 102 dBm. The degradation of RBER does
not occur at a large input signal level into the receiver.
The total current consumption in transmit, receive, and idle
modes is 31 mA, 42 mA (off-chip LNA: 44 mA), and 1 A,
respectively, at 3.0 V. Fig. 21 shows a photograph of our IC.
The IC is implemented in the 0.6- m bipolar process with
YAMAWAKI et al.: 2.7-V GSM RF TRANSCEIVER IC 2095

TABLE II
EVALUATION RESULTS

Fig. 19. Measurement system output spectrum.

TABLE I
EVALUATION CONDITIONS FOR REFERENCE SENSITIVITY

a duplexer and a Tx-SAW filter. The low Tx noise level of

163 dBc/Hz and the small phase error of 2.7 rms at antenna
are achieved. On the other hand, the dual IF architecture is
applied to the receiver. The good reference sensitivity less than
105 dBm is achieved. These results of the system evaluation
indicate that the IC meets the GSM specification.

REFERENCES
[1] C. Marshall, F. Behbahani, W. Birth, A. Fotowat, T. Fuchs, R. Gaethke,
Fig. 20. RBER of receiver. E. Heimerl, S. Lee, S. Navid, and E. Saur, “A 2.7 V GSM transceiver
IC’s with on-chip filtering,” in IEEE Int. Solid-State Circuits Conf., 1995,
pp. 148–149.
[2] T. D. Stetzler, I. G. Post, J. H. Havens, and M. Koyama, “A 2.7–4.5 V
single chip GSM transceiver RF integrated circuit,” IEEE J. Solid-State
Circuits, vol. 30, pp. 1421–1429, Dec. 1995.
[3] K. Murota, “GMSK modulation for digital mobile radio telephony,”
IEEE Trans. Commun., vol. COM-29, no. 7, pp. 1044–1050, July 1981.
[4] A. A. Abidi, “Direct-conversion radio transceivers for digital commu-
nications,” IEEE J. Solid-State Circuits, vol. 30, pp. 1399–1410, Dec.
1995.
[5] C. Takahashi, R. Fujimoto, S. Arai, T. Itakura, T. Ueno, H. Tsurumi,
H. Tanimoto, S. Watanabe, and K. Hirakawa, “A 1.9 GHz Si direct
conversion receiver IC for QPSK modulation systems,” in IEEE Int.
Solid-State Circuits Conf., 1995, pp. 138–139.
[6] F. Piazza, P. Orsatti, Q. Huang, and H. Miyakawa, “A 2 mA/3 V 71
MHz IF amplifier in 0.4 m CMOS programmable over 80 dB range,”
in IEEE Int. Solid-State Circuits Conf., 1997, pp. 78–79.

Fig. 21. Chip photograph.

GHz and The chip size is 13 mm . Taizo Yamawaki was born in Hiroshima, Japan,
Table II summarizes the IC characteristics. in 1969. He received the B.S. and M.S. degrees
in electronic engineering from Kyoto University,
Japan, in 1992 and 1994, respectively.
V. CONCLUSION After graduating, he was engaged in the develop-
ment of the RF-IC for GSM/PCN transceivers at the
A 2.7-V GSM RF transceiver has been developed using a Central Research Laboratory, Hitachi Ltd., Tokyo,
0.6- m bipolar process. The OPLL technique is used in the Japan, and in 1996 he started developing RF-IC by
transmit path as a frequency converter. The OPLL’s tracking using CMOS technology.
Mr. Yamawaki is a member of IEICE of Japan.
bandpass filter characteristics suppresses the Tx noise without

Authorized licensed use limited to: Foxconn Electronics Inc. Downloaded on January 12, 2009 at 03:00 from IEEE Xplore. Restrictions apply.
2096
Masaru Kokubo (M’94) was born in Ibaraki, Japan,
in 1959. He received the B.S. degree in electrical
engineering from Chiba University, Japan, in 1981.
After graduating, he engaged in the development
of switched-capacitor filters, A/D and D/A con-
verters of CODEC, and fast-switching frequency
synthesizers at the Central Research Laboratory,
Hitachi Ltd., Tokyo, Japan. His work is in the devel-
opment of the RF-IC for the GSM/PCN transceiver
and RF-IC using CMOS technology.
Mr. Kokubo is a member of IEICE of Japan.
Kiyoshi Irie was born in Tokyo, Japan, in 1966. He
received the B.S. degree in electronic engineering
from Science University of Tokyo in 1991.
In 1991, he joined the Image and System Labora-
tory, Hitachi Ltd. and was engaged in the research
and development of low-power, small, and low-cost
RF circuits for cellular handsets (ETACS, NTACS,
PDC, and PHS). Since 1995, he has been engaged
in the development of the RF-IC for the GSM/PCN
transceiver at the Semiconductor Technology De-
velopment Center, Semiconductor and Integrated
Circuits Division, Hitachi, Ltd., Yokohama, Japan.
Hiroaki Matsui was born in Shizuoka, Japan, in
1971.
In 1989, he joined the Image and System Lab-
oratory, Hitachi Ltd. and was engaged in the de-
velopment of mixer and PLL synthesizer LSI’s for
NTACS, ETACS, and AMPS. Since 1995, he has
been engaged in the development of the RF-IC for
GSM/PCN transceivers at the Semiconductor Tech-
nology Development Center, Semiconductor and
Integrated Circuits Division, Hitachi, Ltd., Yoko-
hama, Japan.
Kazuaki Hori was born in Fukuoka, Japan, in
1961. He received the B.S. degree in electronic
engineering from Yamaguchi University, Japan, in
1984.
In 1984, he joined Hitachi Ltd. and developed
video signal processing LSI for VTR, especially
modulator and demodulator of FM signal, FM filter,
video filter, and chroma filter. Since 1995, he has
been engaged in the development of the RF-IC for
GSM/PCN transceivers at the Semiconductor Tech-
nology Development Center, Semiconductor and
Integrated Circuits Division, Hitachi, Ltd., Yokohama, Japan.
Takefumi Endou was born in Nigata, Japan, in
1964. He received the B.S. degree in electronic
engineering from Nigata University in 1986.
In 1986, he joined Hitachi Ltd. and developed a
variety of analog circuits such as the AGC amplifier
for CDMA, IC for subscriber line interface circuits,
and driver-IC for optical data link. Since 1995,
he has engaged in the development of the RF-
IC for GSM/PCN transceivers at Analog Digital
Mixed LSI Engineering Departure, Multipurpose
Semiconductor Product Operation, Semiconductor
and Integrated Circuits Division, Hitachi, Ltd., Gunma, Japan.
Authorized licensed use limited to: Foxconn Electronics Inc. Downloaded on January 12, 2009 at 03:00 from IEEE Xplore. Restrictions apply.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 12, DECEMBER 1997
Hiroshi Hagisawa was born in Hokkaido, Japan, in 1953. He received the B.S.
and M.S. degrees in electronic physics from Tokyo Institute of Technology,
Japan, in 1976 and 1978, respectively.
In 1978, he joined Hitachi Ltd. and developed a variety of IC’s for wireless
communication. Since 1996, he has engaged in the development of RF-IC
by using CMOS technology at the Central Research Laboratory, Hitachi Ltd.,
Gunma, Japan.
Tomio Furuya was born in Shizuoka, Japan, in
1952. He received the B.S. degree in electrical
engineering from Aichi Industrial College, Japan,
in 1975.
In 1975, he joined Sanwa Koki Ltd., Gunma,
Japan, and developed a variety of IC’s for car audio.
Since 1996, he has engaged in the development of
the RF-IC for GSM/PCN transceivers.
Yoshimi Shimizu was born in Gunma, Japan, in
1967. He received the B.S. degree in mechanical
engineering from MESISEI University in 1991.
In 1991, he joined Hitachi Microcomputer System
Ltd., Gunma, and developed the FM demodulator
IC for BS tuners. From 1993, he developed the BS
tuner system which involves the FM demodulator IC
and GaAs mixer IC. From 1995, he developed the
RF circuit for PHS (Japanese personal handyphone
system) which involves GaAs MMIC. Since 1996,
he has engaged in the development of the system
evaluation board for GSM RF-IC.
Makoto Katagishi was born in Hokkaido, Japan,
in 1965. He received the B.S. degree in 1988 from
Kitami Institute of Technology, Japan.
In 1988, he joined Hitachi Ltd., Yokohama, Japan,
and developed high-frequency circuits for satellite
broadcasting receivers and cellular phones at Hi-
tachi Ltd. Since 1996, he has been involved in
development of RF IC’s for GSM applications.
Julian Robert Hildersley was born in Portsmouth,
England, in 1963. He received the B.S. degree in
electrical engineering from University of Reading
in 1984.
After graduating, he was involved in the devel-
opment of radio communications equipment for a
range of applications at Plessey Military Commu-
nications. He joined Roke Manor Research Ltd. in
1989, to develop GSM terminal equipment before
moving to The Technology Partnership plc, Hert-
fordshire, U.K., in 1995. Since then he has been
developing RF-IC’s for GSM applications.