Inst ruction Set of 8086 Microprocessor Syllabus Instruction set, Groups of Instructions ; ‘Addressing modes. Machine Language Instruction format, Instructions; Logical Instruction, Data transfor Instructions, pe Instructions, Program control transfer or branching Instructions, Process cor structions. 3.1_Introduction = In chapter 2, we have staied the art of assembly language programming for 8086 microprocessors. This chapter introduces the different format of instructions, acrssing mode, groups of instructions and instruction set of £8086 microprocessors. 2086 bas more than 20,000 instructions. Syllabus Topic : Machine Language Instruction Format ————————— Bit manipulation Instructions, Sting 1. One byte instruction 3. Register tovtrom memory with no displacement 4. Register ttrom memory with dlsplacene] 5. Immediate operand to register 8. Immediate operand to memory with 3.2 Instruction Format woth Seplacement | > qusate-s1n Fig. 3.2.1 : Instruction Format | fos2t wate we Da ae > 1. One-byte instruction | ~ This format is only one byte long and may bavi data or Tegister operands, ~ The least significant 3 bits of the op-code are walt format has one or more Specify the register operand, if any. - Tenens t - Otherwise, all the 8 bits form an opcode a # field, which inne etn code field of op-code ‘perands are implied, by he cru, ofthe operation tbe performed | = 2 Register-to-regist ~The second field is = * v1 18 Called ag 7 which CPU perform the oS SPINA field i, data field ~ Register to re; ; a Pon pei by tein et is of2 bytes long sini, de formato a imucon set tay ~ The fi , 7 Ist byte of ‘i 6 = FE Fomats of the instucton paren and eration sole 19 Imn09 may yay fon i Specified by W bit, width of the ~The instrctionf to six ~ Second i o ‘ty, re da ~ 7 a 7 Ie reser specified in the Re is oot "bister ope the REG field is on jsssors (MSBTE - Sem 4 ~ Cor ~The RIM field indicate another operand which may be register or memory location, I byte D; De Ds De Dy D; Dy Dy Op-Code Ww 2" byte Dy Ds __Ds Dy _Dy Dz Dy Dy 1] T I . REG RM Register to/from memory with no displacement = _Inthis type of instruction the format of instruction is of 2 bytes long. = The first byte is same as in the register-to-egister format but second byte contains MOD field as shown in below. = The MODE, R/M, REG and the W field are given from Table 3 Ibyte D; Ds Ds Dy Ds D:D; Dy [ Op-Code Ww 2 byte Dy De Dy Dy Dy D; Di__Do [moo [rec | nat > 4, Register to/from memory with displacement = This type of instruction format includes one or two additional bytes for displacement along with two bytes’ format of register tofrom memory as shown as follows. I byte Dy Dy Ds Ds Ds D: Di Do Op-Code 2 byte Dy Ds Ds Dy Ds Da ‘MOD: | REG 3" byte Dy Ds Ds Ds Dy Dy Ds Do Lower byte displacement 4" byte Dy Ds Ds Ds Ds Dy Di Do ‘Higher byte displacement > .5. Immediate operand to register In this type, the instruction format content the first bytes as well as the 3-bits from the second byte, which are used for Di Do RM 32 ition Set of 8086 Microprocessor In this type, instruction format includes one or two bytes of immediate data as shown below. Ist byte Dy _Ds_Dy_Dy Ds Ds Di Do OPCODE 2 byte Dy Dg Ds Di Dy Dy Di Do 1]1] orcove | RM a byte “Dy Dg Ds Ds Ds D, Dy Lower byte DATA a byte Dy De Ds Ds Dy Dr Di Do | Higher byte DATA, a > 6. Immediate operand to memory with 16-bit displacement = The length of this type of instruction format is five or six-byte long. = The first two consecutive bytes contain the information of OP- CODE, MODE and RIM fields. - ~The last four bytes contain two byte of displacement and two bytes of data shown as follows. I byte Ds Dy Ds Dy ‘OPCODE. 2 byte Dy Ds _Ds Ds Dy Dr Di Do Mop | orcope | Rat 3 byte Dy _Ds Ds Dy Dy D: Ds Do Lower byte of displacement 4 byte Dy_Ds Ds Dy Ds Dy Di Do ‘Higher byte of displacement S* byte Dy_Dg_Ds_Ds_Dy Di Di Dy ‘Lower byte DATA: 6" byte Dy_De_Ds Dy_Dy D; Dr Do (9. Higher byte DATA, Dy_De_Ds REG field, if it isa reister-to-reister format, are used for op- code. =eWD CET icroprocessors (MSBTE Sem 4 Instruction Set of 2086 ‘The op-code of instruction is usually appearing in the fist Table 32.2 byte, but in some instructions, a register destination is in the First | [Operands | Memory operanda Ore byte and some other instructions may have ther 3-bits of op-code ‘winout | win acite | win ieee | operende in the second byte. The op-code have single bit indicators and theit cttet_| “onset |" onaet Aefntions and significances are given below. cs rn 10 * = Webit : Indicates the width of operands ie. 8-its or 16-bit | UML data. If W = 0, the operand is of 8-bits and if W = 1, the Y wo T wet operand is of 16-bit. oof enecen | MRS] OI Te | mw Db Indicates one of the operand is register incase of WO a ae operand inservions. If D bit =0, he register specified by th | aay | fax econ | OE rr Ta | ox REG field is source operand els it isa destination operand. ee = “Sit Ieis sign extension bit and is used with W-bit 0 show TT gig | (amy ssn | 2 ee” | oo | ox the type of operation ie. iter byte or word operation. a eos _| — _Veblt : Used in case of shift and rotates instructions. If shift |] ory | ry+con | See a | ox itis if CL contains the sift count Siena omit |S tae meee ats = Zit : Used by REP insrction to conto the loping ||" | ©2_}_@9+00 + One ore 1 on on i id 16 ‘| sro | rect | (@P)+08 | Py+o1e | on |g. The REG cade ofthe diferent registers in the op-code bytes ee ze assign with binary codes given ia Table 3.2.1 a en Tee Deore baa Teble 32.1 W-bit] Register |Registers| Segment register|Segment| | | Note: 08 and D16 represent 8 and 16 bit displacements address bits| (16 bit)| (2bit code) _| reeister respectively. asbity | | - When a data is referred as an operand, then DS is the defait 0 aa AL ie ES data segment register, CS is the default code segment for a storing program codes, SS is the default stack segment 2 ao 2 cs register and ES is the default segment register for the o 010 DL. 10 ss destination data storage. o | on BL. tu Ds. o | 10 | aw Syllabus Topic : Addressing Modes of 8086 o | 1m cH 0 110 DH 3.3_ Addressing Modes of 8086 0 UL BH D> (MSBTE - $-14, W-14, 5-15, W-5, 1 | oo | ax S-16, W-16, S-17, We) 4 ca oe State example of immediate addressing mode. 1 010 Dx (Ref. sec. 3,3) EStisakaoeoe ; Pi a 9.3.3.2 Define addressing mode. List any two addressing 1 100 SP ‘mode of 8086 microprocessor. + [tot [ap Aaetirot Tan 0.3.33 Deserib S i} uo SI 9 Deseibo vaious addressing modes of 6085 wit one suitable example each, i ut DI (Ref. sec. 3,3) : = i - la.3.3. ‘ SE Firs the addressing mode ofthe instruction must be decided, 3.3.4 State and explain any four addressing modes en oe MOD and RIM elds of 2 particular 8086 microprocessor with instruction. The addressing mode depends on the operands (Ret, seo. 3.3) creo: and states how the effective address may be calcued fo, el locating the operand, if it store in memory, The differen addressing modes are listed in Table 3.2.2 on ~The R/M and addressing mode row content indi cate field and addressing mode specifies the MOD fie, ®tOL Any instruction of 8086, te can be used in one of svetion cannot be used ia any the data mory-addressing mode. “SO! Sequential control flow instructions are the i transfer the control to the nest inseuctn sprentan immediately after it in the program afer exceuon ey the arithmetic, logical, data transfer and ° sti process control ‘The control transfer instructions transfer the control to some predefined address of the memory which may or may specified in the instruction, ion ptndcabed ater their execution, For example, INT, CALL, JMP, RET étc, a Addressing modes of 8088 Addressing Modes of 6086, 1. Immediate addressing mode ‘3. Register addressing mode “4, Register indirect addressing mode 5. Indexed addressing mode 6. Register relative addressing mode 7. Base indexed addressing mode '8. Relative base indexed addressing mode ‘9. Implicit or implied addressing mode Fig. 3.3.1 : Addressing Modes of 8086 Immediate addressing mode = In this mode, the immediate data is the part of the instruction and appear in the form of successive byte or bytes after the op-code bytes. = So immediate data may be 8 bit [byte] or 16 bit [word] in leagt. Immediate ‘data can be accessed quickly as they are a lable in an instruction queue hence no extra bus cycle is required to read data. Examples MOV AL, 46H AL is loaded is with 8b immediate uta 46H, MOV BX, 1234H BX is loaded with 16-bit immediate data 1234H, > 2 Direct addressing mode Th this mode, a 16-bits. ‘operand 0 . ‘memory address (offeet) of is sissy specified nthe insrcton as part offset of displacement may be either 8 bit or 16 bit which follows the instruction op-code. So. the physical address is calculated by adding thi ing this offset to the base segment registers ie. CS, DS, ES, $S. Examples MOV AL, [3000H] AL will be loaded with the content (of memory location whose offset 3000H from base address. AND AX, [8000H] AX will be ANDed with the content ‘of memory location whose offiet is 0001 from the base, {In above examples, DS is the default base address register. ‘Suppose, data is stored in EXTRA segment, then data can be loaded in register by specifying address using following way. MOV AX, ES:(4000H] Register addressing mode In this mode, the data is stored in a registers adit is refered using the particular register i. all register except IP may be sed in this mode. Register may be source operands, déstination operand or both. The instruction of this addressing, mode are compact and faster in execution as all registers are reside in chip and no external bus if required to read data. Registers may be 8 bit or 16 bit. 3. Examples MOV AX.CX Copies the content of CX reg, to AX reg. AND AL,BL —‘ANDing the content of BL with AL, store result in AL. ROR AL,CL Rotate the contents of ALCL times. > 4, Register indirect addressing mode In this mode, the address of the memory location which ‘contains data or operand is available in an indirect way, using offset register such as BX, SI, DI register. ‘The default segment register is either DS or ES depending the instruction used. IF BP is used, then SS is the default segment register. Examples . Vv Copies the contents of memory location NOVAK IB) ore ofa isin BX Regist,‘the content of Suber ration whoseotTeet {8 =a memory location. Indexed addressing modes ths mate, he et ofthe operand vice the indexes. Land. DS and BS ae the deft egments Di eapoctvely depending mat awa ined placement sup (st), AL from the frat is Ia St rest ia stm stored in any for index register ST ‘onthe instruction used. ‘Examples memory byte ftom MOVBL (ST Coe evo sin index register SI to AL. ADDAX DIG] Cols te word fom meme tocaion whose offset will be calculated by adding ® With the content of DI register. > 6. Register relative addressing mode i ive address = In this mode, the data is availble at an effective formed by adding its ot 16-its displacement with content of any one ofthe registers such as BX, BP, SI and DI in the efalt DS and ES sepmeat. Examples MOV AX, SOBX] Copies the word from memory location whose offset will be calculated by adding the 50 with the ‘content of BX register, ADD AX, S0Q0[BP] Copies the word from memory location whose offset willbe calculated by ‘SOOOH to the Content of BP register, > 7. Base indexed addressing mode ~ In this mode, the effective address of data is calculated by Adding the content ofa base register BX or BP tothe content fan index register SI or DI with default segment DS or BS, Examples MOVAX.IBXIIS Copies the word fiom memory location whose offeet is. calculated by ‘ding the content of BX with the ‘contents of SI, ADD AL, (BX]{D1} : ry location whose offet is calculted by adding the content of BX with the ‘contents of DI, > 8 Relative base indexed addressing mode In this mode, the offset address of data is ca the B-bits or 16-bits displacement with culated by adding the sum of base ¥ DS and ES. Example wort fom | menary MOV AX,COBXIS er, hose offi canna’, [60+BX+S0) > 9, Implicit or Implied addressing numetioas using this mode Rave 90 Operands. In iy instruction itself will specify the data to be operated by the instruction. Examples - ‘This clears carry flag to zero. DAA Perform operation on AL register ____DAA _Performoperation on AL register Example 3.9.1 SSM Write | appropriate Instructions . to perform following ‘operations : 4 ‘(@) Init stack at 42000H (0) | Rotate register BX right 4 times. Solution : (@) Initalize stack at 42000H MOV AX, 4000H MOV SS, AX MOV SP, 20008 oR MOV AX, 42001 MOV SS, AX MOV SP, o000H ©). Rotate register BX right 4 times MOV.CL, 4 ROR BX, CL. Example 9.3.2 RUEHNIT ms ‘What will be the contents of AX Teglstar after excouton of following lines ot ‘code, MOV AL, 10 : %y 4 ‘MOV DL, 20 wend MUL OL. Solution ;= MUL at nserton ore sic is nothing but 200 in decimal TH! AX reiter ‘Eanple 333 TEENIE Mi lye acreesing mode o ho totowing emt MULAL, BL “¢l) Movax, x a MOVBX, [SI @)_ MOV DX, coaoH ‘olution : @ MULAL,BL + Register addressing mode (@ “MOV AX, Bx aister addressing mode (i) MOV BX, (st) + Indexed addressing mode Gs) MOV DX. 0040H —_; Immediate addressing mode Example 3.3.4 TAURINE What wil be the contents of AL, BL, AX, DX register ater ‘execution ofall ines. ea MOV AL, 03H MOV BL, 03H SUB AL, BL MUL AL, 08H ‘Aiso write which flags will be affected? ace Solution : (1) MOV AL, 03H instruction loads 03H | in AL register, @) MOV BL, 03F instruction loads 03H in BL register. @) SUB AL, BL instruction subtract BL from AL, as numbers in AL and BL are same so result will be 0 in AL and ZF will set. @) MUL AL, 08H instruction should be written as MUL 08H and this instruction does not execute because immediate addressing mode for this instruction is not allowed ic. 08H cannot be used. * Example 3.3.5 TETRA Write ‘assembly language Instructions to perform following ‘operations, () Move contains of memory location pointed by DI into “BX register {Copy a string from one memory location to another 1. “using string manipulation instruction, Solution : Move contains of memory location pointed by DI into BX register MoV BX, [DI] @) Copy a string from one memory location to another using string manipulation instruction. 36 lnstruction Set of 8986 Microprocessor ‘MOV-CX, count Toad esth of string ax cunt MOV Sloot ste; initialize menioey poimer for 5 tures string MOV Dost std Initialize memory pointe fo # destination; sting REP MOvSB. oR ‘MOV CX, count # Load length of string as a count’ MOV Sloot ste_s ; Initialize meniory pointer for : ‘ture string i MOV Diet ws titatie memory pointer for destination string. UP: Moysp LOOP UR | ; Sarees entity addressing modes in folowing instructiona, () MOVAX, 2050H: (STC! 3 ii), MOV AL; DS:{Si] (lv) INCBX: i Solution : (@ MOV AX, 2050H " ; Immediate addressing mode qi ste + Implicit addressing mode Gi) MOV AL, DS:{S1] _;Indirecuindexed addressing mode () INCBX + Register addressing mode Example 8 at wl te con of ater BX ate tn exoton ot instructions, MOV BX, 50H MOV CL, 05H. SHL’ BX, CL. Solution : out Ou ° olo ola sfololololo}olsfalsfolololololole| s cfofololololslolrfolojofofololole} 2 afofolofololo| + ofofolelolole| reas L_|__Fraty oitn 8x=cn00H ater sing oe ees ott —inst 37 truction Set of 8086 yrooessOe, | TE - Som 4 = Cony BEF vecoprcnssors (us Example 3.2.12 EXERT Example 3.3.8 EXCRETE ‘ Identity the addressing mod® used in following instructions: (@ MOVOS,AX——(b)_ MOVAX, [4172H] eee eee Solution = (@) MOVDS, AX + Register addressing mode (@) MOV AX, [4172H] - : Direct addressing mode © ADDAX.ISI = Indirect or indexed addressing mode (@) ADD AX{STI[BXI[O4]: Relative base index addressing 7 mode te Example 3.3.9 TEESEICS i Identity the addressing modes in folowing instructions (@ MULALBL (&) MOVAX, 21001 (© MOVAL,DS: [SI] (d) MOVAX, BX Solution (@) MULAL.BL —— : Register Addressing Mode (©) MOV AX.2100H — : Immediate Addressing mode (©) MOVAL, DS:[SI] _: Indexed or Indirect Addressing mode (© MOVAX,BX _: Register Addressing Mode Example 3.3.10 FSTSE0 ST Identity the addressing mode of following instructions. @ INC {4712H) (i) ADD AX, 4712H. Ov) (v) MOVAX. [BX+Si] ‘Solution : @ INC(4712H) + Direct addressing mode Gi)" ADD AX, 4712H + Immediate addressing mode ii) DIV BL Register Addressing mode (iv) MOV AX [BX + SI] : Base Indexed Addressing mode Example 3.3.11 EXPBONE ‘entity the addressing mode of following instructions, @ MOV AX, 2034H (i) MOV AL, [6000H) (ii) ADD AL, CL. (i) MOV AX, 50H [BX] {si} Solution : @ MOV AX, 2034H Immediate addressing mode @ MOV AL, (60008): Direct addressing mode Gi) ADD AL, CL ‘Register addressing mode (iv) MOV AX, SOH [BX] [SI] : Relative base index -mode re beeen identify the addressing modes for the following instruction : (. MOV CL, 34H (qo MOV BX, [4172 H} (iy MOV DS, AX (uy MOVAX (SI + 8X +04) Solution : @ MOVCL.34H + Immediate addressing mode (i) MOV BX, (4172 HI = Direct addressing mode GDMOVDS AX caer | (SI-+BX +04] _ : Base Index with 8 bi (MOV AX, (SI aac __ eee Example 33.19 SCRE ‘Analyze the content of AL register and status of carry and fausilary cary flag after the execution of following {nstructions. : MOV AL, SSH ADD AL, 01H DAA Solution : If AL =99 BCD and add AL with 01 BCD ‘Then ADD AL, O1H too1 1001 = AL=99BCD + _00000001_= BL=01BCD 1001 1010 = AL=9A Hand CF = 0,AF=0 Now, in above example after addition, Carry and Auxiliary carry flags are reset but lower and higher nibble is greater than or equal to 9. So DAA instruction adds 6 to higher as well as lover nibble of AL register to get correct BCD result i.e. 100 BCD of which 00 in AL and Cy = 1 as given below. After the execution of DAA instruction, the result is Cy=1 1001 1010 +01100110 0000 0000 AL= 9AHAF=1 Serres Syllabus Topic : Instruction Set SS Instruction Set of 8086 ——AStuction Setofsose 0.3.4.1 Select instructions for each of the folowing: |. Rotate register BL, right 4 times. 1h Mutily AL by oat li. Signed division of BL and AL 5000 to register DS, 3.4) (Ref. seo,1 Data transtor/ Copy isracione 2 5. Machine ‘Control instructions: 6. Flag Manipulation instructions 7. Shift and rotate instructions 8. String instructions Fig. 3.4.1: Instruction Set of 8086 ‘The £086 instructions are grouped into following main types, > 1 Data transfer instructions group ‘The instructions of this group ars used to transfer data from Sours (0 destination where source may be register, memory location or immediate data and destination may be register o¢ memory location. All the instruction which performs the store, move, load, exchange, ‘comes in this category. > 2 Arithmetic and logical instructions group ‘The instructions of this group are used to perform arithmetic and logical, increment, decrement, compare and scan operation. > 3. Branch instructions group input and output instructions ‘The instructions of this group are used to transfer the program execution control to the address specified in the instruction such as call, jump and return instructions. > 4 If these instructions use REP instruction prefix with CX used as count register, they can bé used to perform unconditional and conditional loops. The LOOP, a LOOPNZ and LOOPZ instruction belongs to this category. > 5. Process (Machine) control instructions group Loop instructions group The instnictions of this group controls the status of machine. NOP, HLT, WAIT and LOCK instructions are the example of this type. ‘> 6.. Bit Flag) manipulation instructions group The instructions of this group, which directly affect the flag register, such as CLD, STD, CLI, STIetc. > 1 Shift and rotate instructions : The instructions of shifting oF rotation i incx. % 8 String instructions group this group is used to perform bitwise neither direction with or without a coun Syllabus Topic : Data Transter Instruction 3.4.1 Data Copy / Transter Instructions > (usere-5-15, w-15, 16, w-16, S-17, WA17, $18) Diflereniate between instructions : MOV and LXI (Ret. sec. 3.4.1) SESE Explain the following instruction of 8086 : XLAT. (olse.349) EERE Explain the functions of following instruction with one example :(1)XLAT — (@) LEA (Pel. sec. 3.4.1) em With suitable example. explain following instruction XCHG (Ret. sec. 3.4.1) EURUTENG Explain the following instruction of 8086: , @ XLAT i) XCHE. (Ref. sec. 3.4.1) SO With example, describe XLAT instruction. (Ref, sec, 3.4.1) Ts 0.3.4.2 2.3.43 0.3.4.4 0.3.4.5 2.3.4.6 a. 3.4.7 ‘& MOV destination, source ~ This instruction is used transfers data from source i.e, register/memory location / immediate data to destination ie, another register-memory location. — The source of an instruction can be any one of the segmént register or other general or special purpose register ot a memory location and destination of an instruction can be a register or memory location. = But, in ion addressing mode, segment register should ‘not be a destination register means direct loading of the ‘segment registers with immediate data is not allowed. ~ _ Tolload segment registers with immediate data, we must have to load any general-purpose register with the immediate data and then it should be moved to that any segment register. Operation Destination «Sourcemen SSHSP~ 1] LSB of source Examples PUSH BX Deana! SP by 2, copy BX to sack ie stack to Bet tier to higher addres oy fact, BL repiner to lover adden © PUSH Ds sors (MSBTE - Som 4 - Comy mode. where mediate addressing ssn lmmediate data copied to BX register by this instruction, MOV BX, 3456H ‘MOV AL, [3000H] addressing mode where the Kee stig oe whe AX register by ths instruction. Indirect addressing mode where the data from memory location addressed by SI register by this instruction, Base register relative addressing mode where the displacement 50 H is added to BX register to get effective address from which data is copied to AH register by this instruction, Base index addressing mode where the fective address is calculated. by sdding the contents of BX and St eaister and data is copied to AL register, ‘MOV AX, BX ‘MOV AL, [ST] ‘MOV AH, SOHTBX) ‘MOV AL, [BXIIST] MOV AL, SOHTBXYDN ‘on in the stack segment where the stack Pointer points - TON of the word must be a 16it gener, AEaES tegnent register, or 16-bit memory en ~ Aber ine i sack eddeses he higher byte copies thle Se and he lover tte copes ke oe Address, Operation SP<-sp-2 SSSP]—MSB of source 3 Instruction Set of 8086 | PUSH AL Not allowed must push a word, ' PUSH [5000H] Decrement SP by 2, copy word from epee 8 bs comet of apg eat ek Hn OO SS address of stack, ‘7 POP destination ~ This instructioa stores a word from stack I Ta iter dentin ied inte ~The destination must be a 16-bit Beton Purpose reser, Segment register, or a 16-bit memory location, ~ The stack pointer is automatically Py 2 tin eck nd ey aN Plt he nex eat er ent Wort icoped the eco don Operation LSB of destination «SS;{SP}, MSB of destination « SS:{SP41). SP<-SP+2, Examples Pop Dx £0 2. word from top of stack to DX, SP = gp cael®. comtem of {SPI to DL renee a Content of [SP+1] to DH: register, Por ps Cary a word from top of the stick to Dg register, SP= SP +2, POP [8000] Copy word from top of stack to locations 8000H and 8001H, ‘7 XCHG destination, source ~ Ths instruction exchanges the contents of a register with the Somtents of another register or memory location. - auton cannot dsl exchange the cone of wo ‘memory locations, - sean ction canbe specified s the source ora te rarest YY MY of 24 addessng mote gies, Table 3.2.2, - tour eat 28 detinaion mst both be won or ey ans imate Ove: The segment repisier cians bee instruction, Operation performed Destination 4 Source Examples XCHG AX, BX Exchange the word in AX with wort inBx. XCHG BL, cH Exchange the byte in BL with byte in cH XCHG AX, (70004) Exchange the word in AX. with of memory ie. AH with the cotet ‘T000H memory location and AL with of the content of 7001H memory byte of DS register to |=2e3 WISUTE- Som 4-6, XCHG AL, NUM[BX] . 'Be the AL wit SEA = NUMIB. * memory © INaccumulator, port The IN instruction copies which may be AL or AX Le. ‘The address of the port directly or indirectly, from accumulator, '® destination For variable port type the 16-bit in DX register only, address of a port is ‘So DX register must always be address before the IN instruction, Operation AL € [port] for byte. AL « [port] and AH ¢ [port+1] for word Specified Yoaded withthe 16-bit por ‘Examples In fixed port type INAL, 80H, Input a byte from port whose address is 80H. IN AX; 80H ‘Input a word from port whose address is 80H. In variable port type ‘MOV DX, 8000H ize DX to point port with port address. INAL, DX ‘Input a byte from 8-bit port whose address is in DX to AL. IN AX, DX Input a word from 16-bit port whose address is in DX to AX. ‘ OUT port, accumulator The OUT instruction copies a byte from AL or a word from AX to the specified port. The address: of the port can be specified in the instruction directly or indirectly. For the fixed port type, the 8-bit address of a port is specified directly in the instruction. For variable port type the 16-bit address of a port is specified in DX register only. So DX register must always be loaded with the 16-its port address before the OUT instruction. Operation [port] — AL for byte. [port] « AL and [port+1] <— AH for word. OUT 801 Copy the contents of AL to byte from the address pointed ALXLATetangesnofage It then copies the (BX+AL) back into. Operation AL DS:BX+AL] Example DATA ‘TABLE CODE DB «CODE DB u "0123456789ABCDEF" MOV BX, offset TABLE Point BX to the start of lookup table in DS MOV AL, CODE” XLAT Replace code in AL with code from lockup table. The ‘content of AL will be OBH ‘© LEA 16-bit register, source . This instruction determines the offset of the variable or memory location names as the source and loads this offset the specified 16-bits register. Operation 16 bit register — effective address 7 LEA BX, ARRAY Load BX with the offset of variable ARRAY. LEA SI, LIST Load Si with the offset of variable ust. “ Load CX with effective address Se adding contents of BX and DI. OUT 80H, AX Copy the contents of AX to port 80H.BET mcroprocossors WSBTE Sems ee of first syllabi ‘a word from two consecutive memory fied in the instruction. two consecutive memory = These instroctions copy a word Iocations into the register speci It then copies a word from next Jocation into the DS resister. Operation For LDS instruction 16 bit register & [memory address] DS & [memory address +2} For LES instruction 16 bit register « [memory address) ES & [memory address + 2] ‘Examples Copy the contents of memory location LDS BX, [12341] ~ 123411 in BL, contents of 1235H to BH ‘and the contents of 1236H and 1237H in DS register. LESBX,[1234H] Copy the contents of memory location 1234H in BL, contents of 1235H to BH ‘and the contents of 1236H and 1237H in ES register. 7 LAKE This instruction stores lower byte of flag register of 8086 10 the AH register. Example : LAHF 7 SAHF This instction copies the content of AH register which is used to set or reset the flag in the lower byte of the flag register of 8086. : Example: SAHF © PUSHF : ‘Tis eseetion i wed soe ag register nt stack Stack pointer is decremented by two and stores the word in the flag register to the soe tase ‘memory locations pointed by the ‘Example : PUSHF > PopF ructions = $14, W-14, S-15, W-15, $-16, W-16, W-17, S-18) 3.4.2 Arithmetic Inst > (MsBTE two arithmetic instructions with their tettons, Give the syntax. with one Gamble each. (Ret. sec. 3.4.2) Explain the instruction with thoir syntax : ADD: (Ret. sec. 3.4.2) ‘of 8086 Tnicroprocessor Tena i te botween instructions : ADD and ea ‘ADC. (Ref. sec. 3.4.2) ‘of 8086 : DAA Explain the following instruction (Ref. sec. 3.4.2) Explain DAA instruction with suitable example. (Ref. seo. 3.4.2) Explain the following’ instruction of 8086 with suitable example : AAA. i SrA (Ref. sec. 3.4.2) lo. 3.4.11 1. 3.4.12 la. 3.4.13 a. 3.4.14 la.3.4.15 With suitable example explain following instructions. @) DAA (i) ADC: (iii) MUL (Ref. sec. 3.4.2) @. 3.4.16 Explain following instructions : INC (Ref. sect. 3.4.2) e |Q. 3.4.17 Explain with suitable example the instruction given below: (i) DAA (ii) AAM (Ref. sec. 3.4.2) : ‘These instructions perform the arithmetic operations, like addition, subtraction, multiplication and divi along with the respective ASCII and decimal adjust instructions. @ ADD/ ADC destination, source ~The ADD instruction adds a number from some source to 2 ‘number from some destination. ~The ADC instruction adds the carry flag into the result. - i ‘ource may be an immediate number, a reste, of * nemory location as specified by addressing modes given in Table 3.2.2. 7 a= ad ~The destination may i mory . i y be a register or a memory location a by any one of 24 addressing modes in Table 322. ee and destination must ad Cannot both be memory loeations, eM OF Destination should n lie ot be an immediate Flag affected : OF, CF, PF, AF, SF. ZR. =r 1550's (MSBTE - Sem 312 ortrne derinton ours fo ADD se dndenlon tress +e oe ADC. ruction Sot of 8086 Micr SBB AX, 1234H Immediate addressing mode instrction that subtracts the immediate number 1234H and ‘barrow from AX and stores result in AX. pesiton = SBBAX,BX Register addressing mode instruction that Berks, HH Immediate addres ing mode adds the immediate mm that Store result in AL. 74H 10 AL and AX, BX. Register addressi ‘ADD: eisier addressing mode instruction that subtracts the contents of BX and barrow from AX and stores result in AX. ‘7 INC destination ‘adds the contents (OF BX with AX and stores | — ‘This instruction as | to the indicated destination. resultin AX. ADDAL[6O00H] Direct addressing mode istration that ad ents of memory location s AL, stores result in AL. eee ‘ADDAL(S ——_ Register indirect addressing mode instru that i he coments of memory tn pointed by ST index Pointed by SI index register with AL and ADCAX, 1234H Immediate addressing mode instruction that ‘adds the ithmediate number 1234H to AX with cary and stores result in AL. ADCAX,BX Register addressing mode instruction that adds the contents of BX to AX with carry and stores result in AX. SUB/SBB destination, source ‘The SUB instruction is used to subtract the data in-souree from the data in destination and the stores result in source then CP = 0, ZF = 0, SF =0. oe Fat ()_ Méestination < source then CF = 1, ZF= 0, SF= |. (©) destination = source then CF = 0, ZF = 1, SF=0. Examples CMPAL,OFFH Compare AL with immediate number FFH. (CMP AX, BX Compare AX with BX. CMPCX,COUNT — Compare CX with COUNT. ‘= DAA (Decimal Adjust Accumulator) DAA instrocton is used to conver the result of the adlition of| two packed BCD numbers into a packed BCD number. DAA only works on AL register. So, DAA instruction must be used after the ADD/ADC instruction. ‘The ADD/ADC instruction adds the two BCD number in hexadecimal format and DAA instruction convert this Dexadecimal result to BCD result. “The working of DAA instruction is given below. If the value of the Jower nibble in AL accumulator is greater than 9 or if AF flag is se, the DAA instruction adds 6 tothe lower nibble of AL accumulator. I the value of the higher nibble in AL. accumulator is ‘greater than 9 or if CF flag is set, the DAA instruction adds 60 tothe higher nibble of AL accumulator, Flag affected : CF, PF, AF, SF, ZF and OF is undefined, Operation (@) Ilower nibble of AL>9 or AF=1, then AL = AL +06. (©) higher nibble of AL > 9 or CF =, then AL = AL +60, (© If both above condition ae satisfied, then AL = AL +66, ‘Example ITAL = 99 BCD and BL = 99 BCD ‘Then ADD AL, BL 1001 1001 = AL =99 BCD + _1001 1001 = BL=99 BCD 0011 0010= AL = 32H and CF=1, AF: Now, in above example after addition, Carry and Auxiliary ccamy flags are set. So DAA instruction adds 6 to higher as well as ower nibble of AL register to get correct BCD result ie. 198 BCD of which 98 in AL and Cy =1 as given below. fier the execution of DAA instruction, the result is Cy=1 0011 0010= AL = 32 Hand AF= 1 +0110 0110 1001 1000 = = 98 in BCD form = \DAS (Decimal Adjust after Subtraction) 4 ; — DAS instruction is used to convert the result of the previous Instruction Set of 8086 M DAS instruction only works on AL register. So, DAS instrction must be used after the supp instruction, : ‘The SUB/SBB instruction subtracts the WO BCD monte, hexadecimal format and DAS instruction conver, te hexadecimal result to BCD result. The working of DAS insti i given below. value of the lower nibble in AL accumy reece hue 9 ot AC ag ee DAS as subtracts 6 tothe lower nibble of AL accumulater, v higher nibble in AL Mer ta 9 orf C fg set he DAS ne subtracts 6 tothe higher nibble of AL accumulator, Flag affected: CF, PF, AF, SF, ZF and OF is undefined, Operation (2) flower nibble of AL> 9 or AF= | then AL = AL -06, (b)_ If higher nibble of AL > 9 or CF = 1 then AL = AL—60, (©) Ifboth above condition is satisfied then AL = AL ~66, Example MAL=55 BCD and BL = 49 BCD ‘Then SUB AL, BL 0101 0101 = AL = 55 BCD = 0100 1001 = BL =49 BCD (0000 1100= AL = 0C H and Cy =0, AF=1 Now, in above example after subtraction, the value of lower nibble of accumulator is greater than 9 as well as AF flag is set So DAS instruction subtracts 6 from lower nibble of AL register to gt correct BCD result ie. 06 BCD as given below. After the execution of DAS instruction, the result is Cy =0 0000 1100 = AL = OCH; AF= 1 and lower aibble >9 00000110 ‘0000 0110 = AL = 06 in BCD form fs ‘7 NEG destination ‘This instruction converts the number byteAvord in a destination in the 2's complemient and store result in the destination which may be a register or a memory’ location specified by any one of the addressing modes. Flag affected: OF, CF, PF, AF, SF, ZF. Operation Destination « 2" Complement of destination Examples NEG AX Replace the number in AX with its 2's complement. NEG BYTE PTR[BX] Replace byte at offset [BX] in DS with its 2's complement, ‘This instruction is used to multiply an unsigned byte fom Source with an unsigned byte in the AL: register, of # ‘unsigned word from source with an unsigned word in the AX register, ‘The Source must be a any register or a memory location. subtraction of two packed BCD numbers to a packed BCD number. aoa sean a TE Scans BH No A, nae LSW of rest register because the result of mutiplicaton or, @ AX A umber i maximum 32-bit, Tel mn -_Ifthe MSB or MSW of the resutis 3 will be set 2, then CF and OF both © ——_lagaffected : OF, CF and PR, AF, SF, Pare undefined (@) Ifsource is byte then AX ¢ AL * unsigned 8 bit source, If source is word then DX:AX © AX * untigne © : “AX € AX * unsigned 16 bit Eames MULBL Mal : MULL Matiply AL ty BL, retin acaal Maly AXby CX resin Dawe MUL BYTEPTR [BX] Multiply AL by byte in DS pointed by [BX], result in AX. = IMUL source =” This instruction is used to moitiply a signed byte from source with a signed byte in the AL register during signed byte multiplication and a signed word from source with a signed ‘word in the AX register during signed word multiplication. = The sourve must be a register or a memory location, * = When a byte is multiplied with the byte in AL, then the result is stored in AX because the resuit of two S-bit ie. bytes aumbers is maximum 16 bit = When a word is multiplied with the word in AX, then the MSB result is stored in DX and LSB in AX register because ‘the result of two 16-bits ie. words numbers is maximum 32-bit. = If the magnitude of the product does not requires all the bits of the destination, the unused bits are filled with the copies of the ‘sign bit. ‘Flag affected : OF, CF and PP, AF, SF, ZF are undefined. Operation (@) source is byte then AX < AL * signed 8 bit source, (©) Ifsource is word then DX:AX < AX * signed 16 bit source. Examples IMUL BL IMUL CX IMUL BYTE PTR [BX] ‘Multiply AL by BL, result in AX. Muitiply AX by CX, result in DX:AX. ; ‘Multiply AL by byte in DS pointed by [BX], result in AX. Example of multiplication of signed byte with signed word. MOV CX, multiplier Load signed word multiplier in cx, ‘MOV AL, multipticand Load signed byte multiplicand in AL: cow Extend sign of AL into AH. IMUL CX ‘Word multiplies, result in DX:AX. Instruction Set of 8096 Microprocessor ‘This insictfon divides an unsigned word by an unsigned by ding vio, an de raged dee ‘Word ic 32-its by an unsigned word during 32/16 division, ‘During the division ofa word by a byte, the word (dividend) ‘ost be in the AX register and a byte (divisor) may in any bit register or memory location. After the division operation, 8 bit quotient willbe available in AL register and 8 bit remainder will available in AH register While dividing double word by a word, the most significant word of the double word should be in DX and the Teast significant word of the double word shouldbe in AX. — Alter the division operation, 16 bit quotient will be available . ‘in AX register and 16 bit remainder in DX register = If word or double word is divided by 0 or the quotient is too large to fit in AL or AX ic. greater than FFH of FFFFH, the £8086 will automatically generates a type Ointerupt ie. divide ‘by O interrupt or divide overflow interrupt. During the division of double word by word, the dividend ust be in DX: AX for double word or AX for word, but source of the divisor should be a word or byte register of a ‘memory location. = During the division of a byte by a byte, we must first store dividend byte in AL and fill AH with all O's for unsigned dividend. = When we want to divide a word by a word, we must firs store dividend word in AX and fill DX. with all O's for unsigned dividend Flag affected : None and OF, CP, PF, AF, SF, ZF are undefined. Operation k (@) source is byte then : AL © AL / unsigned 8 bit source AH & ALMOD unsigned 8 bit source. (0) source is word then AX @ DX: AX / unsigned 16 bit source DX-DX:AX MOD unsigned 16 bit source. Examples DIVBL Divide word in AX by byte in BL, quotient in AL and remainder in AH. DIVCX Divide double word in DX and AX by word in CX, quotient in AX and remainder in DX. DIVNUM [BX] _ Divide word in AX by byte in memory location pointer by [BX]. AOI source = ‘This instruction divides an signed word by an signed byte during 1618 division, and to divide signed double word i, 32-bits by an signed word during 32/16 division. = Daring the division of a word by a byte, the word (dividend) ust be in the AX register and a byte (divisor) may in any 8 bit register or memory location. i= After the division operation, 8 bit quotient will be available ‘AL register and 8 bit remainder will available in AH register ~ During the division of double word by word, the dividend must be in DX: AX for double word or AX for word, but source of the divisor should be a word or byte register or 8 ‘memory location. = Daring the division of a byte by a byte, we must first store 9 or AF= I then. @AL=AL+6, ()AH=AH+1, (@AF=CF=1, (AL = AL AND OFH, of BM 11) ~The CBW operation AL=0BH : ‘must be done before performing divi Of a signed byte in Ore Performing division | After the i = meee the AL by another signed maine execution of AAA AH _ -AL=01 eee ee aehr 316 Instruction Set of 8086 Mi ‘= The binary number in AL register is divided by 10 and the |} quotient i stored in the register AH and remainder i stored in the AL register. © AAS [ASCII Adjust after Subtraction} 1 2 ‘This instruction can 8 used to conver the contents of the AL register to the BCD result. ‘The higher nibble ofthe AL register filled with zeros, = The working of AAM instruction is as follows + Flag affected : PP, SF, ZF Operation. (@ AL=ALMOD 10. () AH = AL/ 10 [Only integer pat is considered]. Example AL=06 = BL=08. MULBL — AX=30H (48 in decimal). AAM AH =04 and AL = 08. ‘7 AAD [ASCII adjust before division} = Tris instrction AAD can be used to convert the unpacked [BCD digit in AH and AL registers to the equivalent binary rurmber in the AL register. = This instruction shouldbe issued before division instruction. ~The division instretion will place the quotient in the AJ register and remainder inthe AH register. 7 = The higher nibble of AH and AL are filed Flag affected: PF, SP, ZF Operation @ AL= AH TIC GAL (b) AH=00 Example ‘This instruction sfaould be executed after the, SUB instrction, 1 AX = 19H (25 in decimal = {in decimal) AAD and the result is placed in the AL register. rain daieatanade = The working of AAS instruction is as Follows. Flag affected AF and CF. Operation CCear the higher order nibble of AL i.e. AL = AL AND OF. flower nibble of AL>9 or AF= 1 then (@ AL=AL-6. (®) AH=AH-1. (© AF=CF=1. (® AL=AL AND OFH. Example AAS Biaeteeeaton”, aus Sepomo Her te otend AS AH=0H, AL=08H. AH=O1H A= ‘7 AAM [ASCH Adjust after Multiplication) This instruction can be used”to convert the result’ of the ‘multiplication of two valid unpacked BCD numbers. This instruction should be issued after the multiplication instruction, wee reion ‘of MUL on unpacked BCD number is always than 100; hence, the result will be inthe register AL DIVBL —_AL-=03 quotient and AH = 04 remainder ‘7 Difference between ADD and ADC = ADD: The ADD instruction adds a number from some source ‘to a.number from some destination without carry. = ADC: The ADD instruction adds a number from some source to anumber from some destination with camry. ———__ TT Syllabus Topic : Logical or Bit Manipulation Instructions 3.4.3 Logical or Bit Manipulation Instructions > (MSBTE - $-14, W-14, S-15, W-16, W-17, $-18) fa. 3.4.18 Compare the following instructions (2 points) = AND and TEST. ’ ‘example. (Ref. sec. 3.4.3) la, 3.4.20 Write any two logical instructions. with thelr | functions, Give the syntax with one! example Pes | (Ref, sec, 9.4.3)(sBTE = Sem4- COM jour rotation intruction® Win 5003.43) oh example. ‘any twobit manipulation instees Describe o.3aZ9 at soc 949) oxpain folowing sta (Ret S00. 24.9) = AND destination, source tin 5 biy-bit the source operand Wi eed saad ea is stored i te destin estinsion ified inthe instroction. aera of xc it poston wil follow the uh ble fr & ‘wo input AND gate. fl : source operand immediate number, the content ee cmtel location specified by of a register, or the content of memory any one ofthe 24 ways given in Table 3.2.2. “The destination can be argister or amemory location. ‘The source and destination cannot both be memory locations in the same instrection. ‘lag affected : CF = 0, OF = 0, PF, SF, ZF. ‘Destinatiod ~destination AND source. ‘Examples ~ AND BH, CL. AND byte in CL Wits byte in BH, result in BEL —~ AND BX, 00FFH AND word in BX with immediaté~cdata (OOFFH. a ANDCX [SI] AND word at offset [ST in data segment with word in CX. Result in CX register. ‘ OR destination, source ~ This instruction OR’s each bit ina source byte or word with ‘he corresponding bits in the destination byte or word and the ‘result is stored in destination, ~ The result ofeach bit will follow the truth table of two inputs OR gate ~ The source operand can be an immediate data, the conten sof tie, o the contents of a memory locaton specified by any one of 24 ways given in Table 3.22, 7 ‘The cesnaton cn be apse ora memory locaton, ~The source and’ destination can " nase not both be 4 memory location Flag affected : CF =0,0F =0,Pp, gr, 2p: Operation Destination « destination 0 Paurrad R source ORBHCL ——ORbyein cy gs CL with byte in B ke ORBX, 0 H, result in B OR word in BX with ‘ | Resultin BX, immediate datg ORCX, [ST] & NOT destination = This imtruction inverts each Bit of the byte OF Word ag. Flag affected : None Operation Destination <- NOT desination Examples NOTBX Complenent the contents of BX register Nor (40008) Complement the contents of the memory NOT BYTE PIR [BX] Complemest the contents of the memory & XOR destination, source locations in the same instruction. Flag affected + CF =0, OF =0, PF, SF, and ZF. Operation Destination — destination XOR source. Examples XORBH,CL — XORsyte in CL with byte in BH, result in BH. XOR BX, OOFFHXOK word in BX with immediate data OOFFH., XOR CX, [SI] ‘TEST destination, source Instruction Set of 8086 Microp OR word at offset [SI] in data segmy word in CX. Result in CX regist with specified destination ie. I'scomplement, ‘The destnaion ean be a register OF @ metiory specified by an one of 24 ways given in Table 3.2.2, ‘ein location 4000H. location pointer by (BX). This instruction perform the.'ogical operation i. Exclusive ORs of each bit in a source byte or word with the same numer bit in a destination byte or word and stores resul in the destination. 7 ‘The result for each bit position willbe as per the truth table of two inputs XOR gate, ‘The source operand may be an immedate number, register, o¢ ‘memory location, ‘The destination may be register or a memary location. But, the source or destination should not both be memory XOR word at offset ED is -gment ; 1] in data segment with word in CX, Result in CX tester, This instructi ia tion ANDs the contents of a source byte or wend With the me = oi sree destination byte or word and The TEST inne Ott iter operand are changed “stn oa often used to set flags before & : repister P04 may be an immediate number, the * Othe memory location, :Mi sors (MSBTE - Som 4 - Com ~The desinton opeand mas be & # oF 16 rr or ag affected t CF, OF, PR, SP and ZF. Operation Flag + set for resol of (destination AND soure). Beamples TESTBH.CL AND byte in CL with byte in BH, no rest Update PP, SF, ZF. ‘TEST BX.OOFFH AND word in BX with immediate data OOFFH, no result, Update PP, SF, ZF. TESTCX,{S1] AND word at offset {SI} in data segment wih word in CX. no Rese U SF, ZF. ee ‘7 Difference between AND and TEST Sr "AND TEST No. 1. | Destructive AND instruction | Non Destructive AND ‘means destination is instruction means ‘modified after the execution | destination is not modified of Instructions after the execution of Instructions 2 | Flag affected : CF =0, OF = | Flag affected : CF, OF, PE, 0. PF. SF. ZF. SF, and ZF. 3. | Operation: Destination < destination AND source. 7 SHL/SAL destination, count = SHILand SAL are two mnemonics forthe same operation. = This instraction shifts each bit in the specified destination ‘counts times toward left = Asa bit is shifted out of the LSB position, a 0 is inserted in the LSB position and the MSB willbe shifted into the CF. = In the case of multiple shifts, CF will contain the bit most recently shifted in from the MSB and bits shifted into CF previously will be lost. = The destination operand can be a byte or a word in a register or in a memory location = If the desired number of shifts is one, this can, be done by putting a 1 in the count position of the instruction, = For shifts more than 1 bit position the desired number, then the count value ie, shift count must be loaded in CL register ‘and put CL register in the count position in the instruction. = The SAL and SHI instruction can be used to multiply an unsigned binary number by a power of two, Flag affected : CF, OF, PF, SF, ZP; and AF is undefined, Operation CF «+——MsB +——— LSB+— 0 Examples. Lo cF=0 BX = 11100101 11010011. struction Set of 8086 Microprocessor SALBX,1 Shit the contents of BX register by one toward le. cr-t BX-= 11001011 10100110, 2 MOVCL,O4H Load desired numberof shifts in CL. SAL AX.CL Shift word in AX left CL bits times. ‘7 SAR destination, count + This instruction shifts each bit in the specified destination count times toward right. = As the shifted out of MSB position, a copy of the old MSB is. on in the MSB postion ie, the sign bit i copied into the = The LB will be shifted into CF. = Incase ot mutiple shifts; CF will contain the bit most recently shite in on te USB, 30 ied into CP previo will be lost. " = The destination oyerand can be a byte or word in a register or in a memory location I the desired number of shifts is one, this can be done by putting a 1 in the count pcition of the instruction. = For shifts more than 1 bit yastion the desired umber, thea the count value i. shift count must be loaded in CL register and put CL register in the count psition inthe instruction. The SAR instruction can be used to divide an unsigned binary ‘number by a power of two. Flag affected : CF, OF, PF, SF, ZP and AF is uttefined. Operation ——+MsB ———+ LsB —+ cE Examples 1 CF=0 BX = 11100101 11010011, SARBX,1 Shift the contents of BX register by one toward left. cr BX = 11110010 11101001. 2. MOVCL,OSH Load desired number of shifts in CL. SARAX,CL Shift word in AX right CLbits times, & SHR destination, count = This instruction shifts each bit in the specified destination counts times to right. ~ _ Asabitis shifted right out of the MSB position, x0 is inserted. ints place. = The bit shifted out of the LSB position goes to the =, = In the case of multiple shifts, CF will contain the ‘it most recently shifted in from the LSB. = Bits shifted into CF previously will be lost. = The destination operand can be a byte or a word in aregiter ‘ot in a memory location specified by any one of 24 way specified in Table 3.2.2,Instruction Set of 8086 Micropro 3-19 (SBTE - Sem 4 jotate left without: this can be done by | a ROL dr tination, count [Fi carry] If the desired number of shifts is one, ‘writing 1 in the place of count. Bot, for mukipl shifts, the numberof desired shifts is loaded imo the CL register and CL is kept inthe place of count. “The SHR instruction can be used to divide an unsigned binary ‘number by a power of 10. Flag affected : CF, OF, PF, SF, ZF and AF is undefined. Operation 0 —* Mss ———+ Ls8 —+ CF Examples: 1 CRO BX =11100101 11010011, SHR BX.1 Shift the contents of BX register by “one toward left. CF=1 BX =01110010 11101001 2 SHRAX.CL Shift word in AX right CL bi'«s times. = ROR destination, count [Rotate right rgthout carry) = This insrution is used rotates all the bits, ofthe specified byte cc word ty count times toward right. The bit rotated out of LSB is g0e%s into the MSB and also expied to CF. ~ Inthe case of ruhiple bit rotates the CF will contain a copy of the bit most recenly moved Cat of LSB, ~ The destination operand may be a byte or word ina register or ina memory location. ~ Whe desined numtyr of ration is one, this can be done by ‘writing 1 inthe place of count. ~ But. for multe rotations, the number of desired rotation is = This struction = Tae bit moved out of io CF, = Inthe case of multiple bit rotates all ofthe bits ofthe specified byte og int times toward Tet d oe -MSB is rotated around into the LSB ang Pai rotates the CF will contain a copy of thbit mst recently moved ou oN ont in destination operand can be a byte or A register o¢ ~ Te “temory focation specified by one of the 24 ways iq Table 32.2. If the desired number of rotation is one, this can be done by ‘writing 1 in the place of count. But, for multiple rotations, the number of desired rotation is foaded into the CL register and CL is kept in the place of count. ‘This instruction can be used to swap the nibbles in a byte or to swap the bytes in a word. ‘This instruction can also be used to rotate a bit into the CF and then it can be checked and acted upon using the conditional jump instruction, JC jump if camy] or INC ‘(jump if n0 carry]. : Flag affected : OF, CF Keri into the CL. vepster and CL is kept in the place of 1 BL 1011 1010. 7 srry concn be wed swap the nites na byt orto iti pe eeeeeaecs : tombe Position, ~ Thean also be used to rote abit into the CF where es ie it can be BL =0111 0101. checked and acted upon by the conditional jun JC Gan far oe NC Yor esa ap instruction, | 2. MOV CL, 08H Load count in cL. cr=1 “a ae AX = 00011110 00111001. i ROL AX,CL Rotate all bits in AX left by 8 bit ap i Position i.e. swapping of byte. “f ; cr=0 AX = 00111001 00011110. Examples o ee scan ACR destination, count [Rotate right with carry] 1. ~ This instruction is Totate specified ROR BL, 1 Rotate all bits in BL tight by one bit or word wih cary en — pion ie. the LSB of the operand ie rete cary a Fst BL = 1001 1101, 1 its cany fis road it the MSB of val MOV CL, 08H Load count in CL, tra tale bitrates the CF town the bit moved i CFs AX-= 10011110 00111000, - tamer aust. — ROR AX, CL ina memory locaton seit, 07 Word ina gist t ion specified by it able 3.2 Y One of the 24 ways it CF=0 AX = 00111000 10011110,RORBL,1 BL=0011 1011, Rotate all bits i bitporiion 1 BL Met by one baal BL=0001 1101, 2 MOVCL, 08H Load count in CL, Las AX= 10011110001 1111000. ROR AX, CL. Rotate all bits in AX right by 8 bit ue Position ie. Swapping of byte, AX=01110001 10011110, © RCL destination, count [Rotate lott with carry} - This instruction is used to rotate all the bits in a speci ; : ina specified b cor word with cary by counts times towards left Le. the Mop ofthe operand is rotated into the cary flag andthe bitin carry flag is rotated into the LSB of the operand, - _In the case of multiple bit rotates the CF will contain a copy of ‘the bit most recently moved out of MSB. ~The destination operand can be a byte or word ina register or in a memory location specified by one of the 24 ways in Table 3.2.2. If the desired number of rotation is one, this can be done by ‘writing 1 in the place of count. But, for multiple rotations, the number of desired rotation is Joaded into the CL register and CL is kept in the place of count. Flag affected : OF, CF ‘Operation CFL MSB LSB: ‘Examples Lo CF=t BL =0011 1011. RCLBL,1 Rotate all bits in BL left by one bit position. CF=0 BL =0111 0111. 2. MOVCL, —_ 08H Load count in CL. CF=1 ‘AX = 10011110.00111000. RCL AX, CL Rotate all bits in AX left by 8 bit position i.e, Swapping of byte. .° CF=0 AX = 00111000 11001111. Use to rotate all the bits in | Use to rotate all the bits in 1, | fPeciied byte or word with | specified byte or word with Gin ‘by counts times to | carry by counts times to fi. i ‘LSThof operand goes to CF | MSB of operand goes to CF ‘and CF bit goes to MSB of | and CF bit goes to LSB of Rent Sperand. In case of multiple bits | In case of multiple bits ‘tation, CF will contains a | rotation, CF will contains 3. | copy of, the bit most | copy of the bit most recently moved outof LSB. | recealy moved out of MsB. Example: IECF=0,BL=0011 1011. 4, | RCRBL,1 ‘Then CF = 1, BL=0001 1101, Example: IfCF=0BL=0o11 1011. RCLBL,1 ‘Thea, CF=0 BL=o111 0110. 7 Difference between ROL and RCL, = ROL : This instruction rotates all of the bits ofthe specified byte or word count times toward left without carry. ~ RCL : This instruction rotates all of the bits ofthe specified byte or word count times toward left with cary. 1Q. 3.4.26 The shift and rotates Instructions are the same. |) etoepts: for: 2° bits. Which distinguish these. "Instructions from each other ? (Ref. sec. 3.4.3) “The op-code format of the entire shift and rotate instructions are given below. The etre shift and rotate instructions are of two bytes. Out of these two op-code bytes, first byte of the op-code of ‘entire shift and rotate instructions are same. en nonapanana onesies [Fosasav0 | ese3700] —— [ter covw|est oom | smnsnnemecsot [101 00vm| mod 01m | oe [irorcorw| noo 1m | rereRam Rot Pols Petete rash Ory Rega rena gy [rroroovw | maton tn ‘Byte t Byte2 shift and Now, compare above op-code formats of entire rotate instructions with the following general op-code format ofthe instriction. |.ssors (MSBTE - Sem 4 79543210 78 53 20 rerrrt et [Med Regt RM SO Fre aes ‘andlor addrosa Crrmprosonts an "modo spoctior = In second byte the bits 3.4.5 are different depending on the ‘operation specified by the instructions and remaining bits ie. 0.1.26,7 are same for entire shift and rotate instruction. The Reg field specifies general purpose register operands but for enire shift ‘and rotate instructions Reg field is used as op-code extension field ile. TTT. These op-code extension field TTT is different in entire shift and rotate instruction. These op-code extension field TTT differentiate between the entre shift and rotate instructions. ee nn ae Syllabus Topic : Program Control Transfer or Branching Instructions 3.4.4 Program Control Transfer or Branching Instructions “D> (MSBTE-W-14, W-15, 6-16, 5-17, W-17) IG.3.4.27 What are the functions of CALL and RET instruction? Write syntax of CALL and RET instructions. (Fit. sec. 34.4) MEVCTERSS RAIS 2.34.28 Name the different types of jump instructions used in 8086 assembly language program. (any sight) (Ref. sec. 3.4.4) BSS! [Q. 3.4.29 Explain the following instructions of 8086 witi: ‘Suitable example. @ LOOP i) INTO (Ret. sec. 3.4.4) Ea |. 3.430 Write any two conditional and two unconditional ‘branching instruction with their function. Give the syntax with one example each. (Rel, sec. 3.4.4) oR 2. 3.4.31 Explain following instructions : LOOP, g (Ref. sec. 3.4.4) Caer) Control Transfer or Branching Instructions 1. Unconditional ‘control transter or 2. Conditional control transfer or instructions change the path of flow of execution i dares specified in the instruction directly or indie is type of instruction is executed, the contents Wen Oe Toad wth new vals of C$ ang Srresponding to locaton where the Now or path of eee.” is going to be transferred. c = Depending onthe addressing modes specified in Table 9, the CS may or may not modify. = Ther are two ‘pes of control transfer OF traning instructions as given as follows. _ = (A) Unconditional control transfer or branching Instructions = This type of instruction transfers the contol of __ execution to the specified memory location independent of any condition or status. : ‘The CS and IP are unconditionally modified with ew CS and IP values. > (2 Conditional control transfer or branching instructions = This type of instruction transfers the control of execution to the specified memory location dependant of any condition or status provided by the result of the previous operation which satisfies a particular condition i.e. status of flags, otherwise, the execution continues in normal flow sequence. - In other word, using this type of instruction the control will be transferred to a particular memory loration, if a particular flag satisfies the condition. 1. Unconditional control transfer or branching Instructions : tm © CALLa procedure ~ "The CALL instruction is used to transfer the program control to the sub-program or subroutine. ~ There are two basic types of CALLs, near’ and far. A neat CALL is a call to a procedure, which is in the same code ‘Segment as the CALL instruction, ~ When the 8086 executes the near CALL instruction, the stack Pointer is decrement by two and Copies the offset i.e. IP of the next instruction after the CALL instruction on the stack. This offset value is used to transfer back the Program control {0 the calling program after the execution of subroutine of procedure, ‘Then, the 8086 loads the offset of first instruction of the Procedure into the IP and RET instruction at the end of the Procedure will retum execution to the instruction after the CALL instruction in the calling program by copying the offset Value stored back to IP,iS . % = Finally it loads CS with the sy : segment that contain te *EMEnt base address of the code iter nrc eee st ~ A RET instruction at the end of the procedne ‘execution to the next instruction ofthe calling peop hyn rir cle oe a en = Operation 1 TENEAR CALL, then SP « SP~2 Save IP on sta TP — address of procedure 2 IfFAR CALL then SP SP sp £CSie. Sue CS on sack 'S «New segment base adres of the called procedure SP-«- SP? SP & [Pic Save Pon sack IP «- New offset address ofthe called procedure Examples CALL DELAY Direct within the segment that calls the procedure of name DELAY. CALL BX Indirect within the segment where BX. contains the offset of the first Instruction of the procedure and replace the contents of IP with contents of BX register. CALL FAR PTR SHOW Direct to another segment i.e. far or inter-segment; SHOW is the name of procedure and must be declared FAR with SHOW PROC FAR at its start. ‘The assembler will determine the code segment base for the segment, which contains the procedure and the offset of the start of the procedure in that segment. © RET instruction ‘The RET instruction is used to return the program execution control from a procedure to the next instruction immediate after the CALL instruction in the calling program. If the procedure is a near procedure, then the retum will be done by restoring the value of IP with a word from the stack te word from the stack top is offset of the next instruction after the CALL instruction in the calling program that was pushed on the stack by the CALL instruction. : of the segment where CALL instruction resides — After the replacement of CS, again the stick pointer is incremented by two, Operation 1, ForNEAR Retum then IP content of tp of tack. SPeSP+2, 2 ForFAR Return then IP «contents of top of stack. SPeSP+2, CS «contents of top of stack. SPesP +2. ITN type of interrupt ‘This instrction causes the 8086 to calla far procedure in a manner similar to the way in which the 8086 respond to an interrupt signal on its INTR or NMI inputs. ‘The {crm type in the instruction refers to the number between and 255 that identifies the interrupt. When the 8086 execute an INT type instruction, it will perform following operation. (2) Decrement the stack pointer by two and push the flags, com the stack. 7 Decrement the stack pointer by two again and push the contents of the CS. Decrement the stack pointer by two again and push the offset of the next instruction after the INT type ‘instruction on the stack. Get the new value, for IP from an absolute memory address of 4 times the type specified in te instruction. For example, for an INT 8 instruction, the new IP will be read from address 000204 Get a new value for CS from an absolute memory address of 4 times the type specified in the instruction plus 2. : Reset both the IF and the TF flags, other flags are not affected by this instruction. ® © @ © o & INTO Instruction [Interrupt on overttow} If the overflow flag OF is set, this instruction will generate type 4 interrupt and causes the 8086 todo an indirect far call a procedure which is written by the user to handle the overflow condition. = When the 8086 executes an INTO instruction, it will perform following operation. (@) Decrement the stack ‘on the stack. pointer by two and push the fagsby eo and push CS on the “oy Decrement the stack pointe — in and posh IP inter by two agai Co) Desens ef est inacion aera Jnctuction onthe stack. (Gee te ew vaoe for IP from an absolve memory ‘xdress00010H in IVT fo. Get a new valve for CS from an absolute memory ‘address 00012H in IVT. (0 Reset te TF and the IF, other Mags are not affected by this instruction. © IRET Instruction ‘The IRET instruction is used atthe end ofthe interrupt service procedure to return the execution tothe interupted program. = During the execution of this instruction, the 8086 copies the saved value of IP from the stack to IP, the saved value of CS from the stack to CS and saved value of flags back to the fag. register. - sions performed by.this instruction are : (@) IPis popped from the stack then SP «SP +2. (©) CSis popped from the stack then SP «SP +2. (© Fag register is popped from the stack then SPe-SP+2, ‘7 JMP destination address [Jump unconditional] ~ This instmction unconditionally transfers the control of execution to the specified address using an 16-bit displacement or CS:IP. ~ No fags are affected or checked by this instruction, ~ Ifthe target of IMP is in the same code segment, it requires only the instruction pointer IP to be changed to transfer ‘control tothe target location. ~ Such a jump is called as intra-segment jump or near jump. ~ If the target for the instruction IMP is in different code Segment from that containing the instruction JMP, then TP and CS will be changed to transfer control to the target location. Such a jump is called as far or inter-segment jump, 7 Difference Between inter and intra Segment jump Sr No, | Tater Segment Jump | Intra-Segment Jump ‘The conditional JMP instruction transfer the control ty target location if some specified condition is satisfied, Conditional JMP instructions are normally used after, instruction or arithmetic or logical instructions, ‘The different types of conditional instruction are giveq Imp disp6 :direct intrases inersegment jumps can | inrasegment jumps are 1, | tssfer control to 2 | always between L_] tocation, contol (othe target, location, Table 3.4.1. Table 3.4.1 Instruction Funetion. 3) CXZ ‘Jump if CX registeris Zero |JCXZ labet LOOP. CX = CX~ 1, jump LOOP label if CX # Zero Loopey CX =CX~1, jump LOPE label LOOPZ. pee ere LOOPZ label LOOPNE/ |CX=CX-~1, jump LOOPNE label LOOPNZ | if CX #Zero and ZF =1 | LOOPNZ late} (CF =0 and ZF = 0) SNBE Jump if not below or equal | INBE label ICF=OandZF=0) TAE/ Jump if above or equal [CF = 0} |JAE label INB/ Jump if not below [CF =0]. | INB label INC Jump if no carry [CF = 0] INC label 1B Jump if below 3B label (CF= 1) [INAEY Pump it not above or equal INAB abel | {Re (if not above or equal | INAB intel qe Jump if carry IC label (CF= 1) Jey Jump if equal twang az (ZF=1) IZ label Jump if Zero (ZF =1)Instruction In 8086 D> (MSBTE- 6-15, S-18) (aaa ced la.34.32 Compate between Jump and Call instruction in 2086. (Vet. s2c.9.4.4(A)) EXE CSET ——— Fie. ronan Re or Simtax | 3.4.4(8) Instruction Sat of 8088 Mt eons Me, Oca i Compart =. ee ison of JNC and JMP. impttnaeatr Instructions in 8086 na. TOF |e. te > qrsere-8-15,5-18) SPEOF aersfonesings “P5Y/NGE tas —| |]? Nacsa suchas Se SF # OF after the LL tate ren 3448) fea 7 a.21434 Omen tien th touts rerio Ge ump if tera a : fe Pie so af SMP and JN. (soe 3' 8 Afrigator Ate Se se sesormf {LE commit ‘har at ahr ned nh 1 | Conon eecing | Udi Ba , Pane iret ql ZF = Tang] | | ele RZemtree eis 7 [cf tog Schad bya | No fap xw eect oe [pe ||} * | fons Cr hap | Sch in rcton P NO abe cafe ee co 3] CeO Gach, oe | Tee pommel jae [mn fot oo LRP tropa cone ner | wate to 20H et ro Jon slo baat Brey lean | coking be ceeon oy jump if not sign SF=0 [INS label 200, 50. [Jump if Overflow OF = 1 JO label —— awe yes Bent ifr feometon is somaly | lsracion ie pase EVEN TP label iearseg terms | opm conse 10 be Fe SPE abt we ioe ox sstmetc | Wunter any put of Be jump if Parity equal PF= 1 of logis instructions. | program air ay inscton ump ifsisn SF =1 1s et = pitierence between JP and JNC 34,4(A) Comparison of Jump and Call appl ied robe a ‘ INC If CF=0 (reset), the program control transfer to the specified memory location. Process Control Instructions ‘Syllabus Topi 3.4.5 Process (Machine) Control Instructions Sr. IMP Instruction CALL instruction i a. > (MSBTE- W-16, S-17) L ofA IMF instruction | A CALL instruction permanently changes the IP | store IP for near call and [a.336 ust tour moching cont a ‘and a for near jp and CS:IP for | CS:P for far call on the tholr function. (Rel. sec. 3 RES arn far jmp. stack so that the original |]{@.9.4:96 Uist and explain, Say four process. program execution instruction with their function, sequence can be (Rot. sec. 3.4.5) Sens resumed. 2 | Does not requires RET | RET instriction is instruction. required to rewum (0 calling program 3. | Conditional Twp | No such Conditional instructions are available | CALL instructions) are which transfer program | available. control to the target location ; if some specified condition is satisfied. = ‘Stack is nor used by IMP | Stack is used [>¥ CALL: instruction instruction. __] ]> 1. HLT: Halt ~The instruction HLT causes the processor to enter the halt state. = The CPU stops fetching and executing ofthe instruction. = The CPU can be brought out of the halt state with the ‘occurrence of any one of the following events. Interrupt signal on INTR pin. Interrupt signal on NMI pin Reset signal on RESET pin. > 2 NOP: No Operation This inseuction i used to add wait state of three-clock cycles and duting these three clock cycles CPU dose not perform any ‘operation. This instruction can be used to add delay loop in the program ‘and delaying the operation before proceeding to read or write from the port 3. WAIT ‘The instruction WAIT causes processor to enter into an ideal state or a wait state and continues to remain in that the processor ‘eecives state until one of the following signal. 1. Signal on processor TEST pin. 2. A valid iterrpt on INTR pin, 3. A valid imerrut on NME pin, This signal is used to synchronize with other extemal Ihandware such as math co-processor 8087, 7% 4 Lock ~ This instruction prevents other processors to take the control of shared resources — In multiprocessor system, the individual processors have theit own local buses and memory and then processor are Connected together by a system bus to access the shared ‘tem resources such as disk dives or memory or DMA, ~The LOCK instruction is used as a prefix to the eri instruction that as o execute, ou fea Example ep en 2 ‘This type of instruction are use changed the stay, or in the flag register such as CF, DF, IF. 2. CMG [Complerant Cary) 4. CLD [Clear Directin fag) 5. STD [Sot Direction fig] Fig. 3.4.4 : Flag Manipulation Instructins > 1. CLC[Clear Carry] This instruction clears the carry flag. CF <0. 2 CMC (Complement Carry] This instruction complements the carry flag. cre CR. > 3. STC [Set Carry] ‘This instruction set the carry flag. CF <1, > 4. CLD [Clear Direction flag) This intruction clears the direction flag. DF 0. 5. STD [Set Direction flag] ‘This instruction set the direction flag, DF <1, 6. CLI [Clear Interrupt flag] ‘This instruction clears interrupt flag. IF «0, 7. STU[Set Interrupt flag] Thisinstuction set the intemupt flag. TF «1. ee Syllabus Topic ; String Operation Instruction ee ation Instruction | 3.4.7 String Manipulation Instructions > (MSBTE-s.14, we14, 5-15, s-16, wa7, SE 9-24.30 Explain talowing suing manuals respective Prefix (@)REPMoVsW () REP CMPSB 3 28 et, sec. 3.4.7)rocessors (MSBTE - Sem 4 « Com (Ret. 200. 3.4.7) 9.4.41 Explain the instuction. of eos with their syntax: STROMP. (Ref. sec. 3.4.7) la. 3.442 Describe various string instructions i (Rot. soc. 2.4.7; ee [a.3443 List the string related instructions of 8086 microprocessor and explain i (Rot. see. 34.7) xplain any two instructions. [0.34.88 Explain ary two string operation instructi suitable example, ee a (Ref. sec. 3.4.7) Ea |0.3.4.45 Describe any two-string operation instruction of ‘8086 with syntax & one example of each. (Ref, soc. 3.4.7) Rureoonerce A string is cont guous block of bytes or words and can used to bold any type of data or information that will fit into bytes or words. There are number of operation performed with sting. The £086 microprocessor suppons string instruction for sting ‘movement, scan, comparison, load and store. Move String. Move String Byte. Move String Word. The instruction MOVS tranifers a byte or a word from the source string to the destination sting. The source must be in the data segment and destination must bein extra segment. The offset of the source byte oF a word must be placed in SI register, which is represented as DS:SI and offset of the estination byte ora word must be in DI register, which is represented as ES : DI. (On the execution of this instruction, SI and DI register are ‘automatically incremented by one to point next element of source and destination, If the direction flag is reset (DF=0], the register SI and DI will be incremented by one for byte move and incremented by two for word move. If the direction flag is set [DF=1], the register SI and DI will be decremented by one for byte move and decremented by wo for word move. The DS:SI and ES:DI register must be loaded prior to the ‘execution of MOVS instruction. Another way to move a byte or word string is by using implicit instruction MOVSB and MOVSW. ‘The instruction MOVSB is used to transfer a byte from source Instruction Sot of 8086 Mi byte movement ForDF=0 Sl¢-SI+ 1 and DI ¢-DI+1. ForDF=1 Sl+-SI-1 and DI-DI- If word movement For DF =0 Si 4-SI+2.and DI «-DI+2. ForDF=1 SI+St-2and DI-DI-2. Examples MOV AX, @data MOV DS, AX MOV ES, AX : ap : MOV SI, OFFSETS. MOV DI, OFFSET D_STRING MOVS $_STRING, D_STRING MovsB Movsw Loed String. Load String Byte. LODSW: — Load String Word. ‘The instruction LODS transfer a byte or a word from the source string pointed by SI in DS to AL for byte or AX for word. (On execution of string instruction, SI is automatically ‘updated to point next element of the source string. If DF = 0, the register SI will be incremented by 1 for byte and incremented by 2 for word If DF = 1, the register SI will be decremented'by 1 for byte ‘and decremented by 2 for word. In the instruction LODS, the source must be explicitly declared either with DB or with DW. ‘Another way to load a byte or word string is by using implicit instruction LODSB and LODSW. ‘The instruction LODSB is used to transfer a string byte from source to AL and the instruction LODSW is used to transfer a string word from source to AX. In multiple byte or word loads, the count must be loaded in CX register which functions as a counter. Operation Ifbyte movement AL DS:{SI] ForDF=0 SIe-SI+1 ForDF=1 SI@SI-1 If word movement AX'€ DS{{SI] - ForDF=0 SleSI+2 ForDF=1 Sie-SI-2 Example to destination and the instruction MOVSW is used to transfer ‘8 word from source to destination. MOV AX, @data ~ In muttiple byte or word moves, the count must be loaded in MOV DS, AX (CX register which functions as a counter. MOVES, AX Operation 2 y cLD e Ess[DI] € DS:iStl- ‘MOV SI, OFFSET S_STRINGsdaetne fatesigc 327 Al LODSS_STRING 3} Lopsp | Lonsw stos ‘Store String. STOSB Store String Byte, On execution of a string instruction, DI is irdated to point next element ofthe source string, ond sen te Btter DI wil be incremented by 1 for byte ‘nd incremented by 2 for word. deans sister DI wil be decremented by 1 for byte and by 2 for word, In the instruction STOS, the source ‘declared cither with DB or with DW. Another way to store a byte or word sting is by using implicit eR te or wor lod, he cout most be loaded in CX register which fonctions asa counter, Sting Byte, ‘String Word, compares weit i cer and destination mug byte oF & word = Das ties Ww Inst ton Soto 2006 | Abbe en) 0st be in DI repinen wins represented as ES:DI. ~ On te extn ofthis inst ton, SU Bd Dt reps toma incremented ty one 1 poat next linens source and destination, . i ~ Wie dieton fags reset (DF 0) the register St and Di wy the direction ag. “0. ie “ ~ {ite rection fag eset (DPI, the register St and DI wi | compare tnd decremented | Compare a word in source destination, ~ _ Bimuliple byte or word compar, the count must ‘be loaded in CX register which functions as a counter, Flags modified : AF, CF, OF, PF, SF. zp ~The instruct SAL ind wod ina ng yor a won! wire a TSS te pay otis,‘on execution of string i 228 Instruction Sot of 8086 Mic ena to st Cet ee ag aT cb DF = ster DI will be 8 MOV CX, length of e incremen sting eta by Vote | Mov st, OFFSETS STRING HDR = 1. the register DI wil be MOV DI, OFFSET D_STRING god decremented by 2 for won, SME! by 1 for byte wrasse acurew In the instrction STOS, the [REP : Repet wile eq - . the source ora declared either with DB or with Dw." PF explicitly | REPZ.1 Repeat while zero, = Another way to scan a byte of word = The instruction is used as a prefix instruction with the string impli instruction SCASB and seg * SUE by wing | intractions and interpreted x “repeat while nt end of = ‘The instroction SCASB is used toscana byte j eid tiger fk on opal etre iaruction SCASW is medtoncn sent nein andthe | ~ Com or epent mtb edn CX ee __Inmoliple bye or word tan, the count mane = Assembler generate same machine code for the instraction register which functions as a counter. incx oidnaana Flags modified : AF, CF, OF, PF, SF, ZF iT yaickeouate 1 aden 1. Execute sing instrction ; L jin AL or word in AX > destination stris 2 CXeCK-1 wort] then CF =0, ZF =0,SF=0 SB We oF | amples 2. [if byte in AL or word in AX < destination string byte or ‘MOV AX, @data word) then CF = 1, ZF=0,SF=1 MOV DS, AX 3. [if byte in AL or word in AX = destination string byte or MOVES, AX word] then CF = 0, ZF =1,SF=0 cLD For byte scan ‘MOV CX, length of string 1, HDF =Othen DI<-DI+1 ‘MOV SL OFFSET S_STRING ‘MOV DI, OFFSET D_STRING DF=1 thea 7 ibe eet [REPE CMPSB or CMPSW For word sean JESTREQU 1. IfDF=Othen DI DI+2 . NOT_EQU: MOV AX.O1H 2 UDF=1 thea DIe-DI-2 . Examples : MOV AX, @data . MOV DS, AX STREQU: MOV AX, 00H MOVES, AX - : cLD . MOV DI, OFFSET D_STRING REPNE : Repeat while not equal. MOV AL, ‘V" REPNZ : Repeat while not zero. . A} SCAS D_STRING “= The instruction is used as a prefix instruction with the sting, B] SCASB instructions and interpreted a a “repeat wile not end of SCASW sing string not equal” [CX not equal to Zero z#=0) REP : Repeat is ven ination i wed a a prefix instruction withthe sting, | ~ Count for repeat must be loaded in CX register. = The instroction ‘as a “repeat while not end of | — ‘Assembler generates same machine code for the instruction instructions and inter ‘ REPNZ and REPNE. string” [CX not equal to Zero}. leg la - ust be loaded in CX register. Operat (Count for pest While CX #0.and ZF =0 While CX#0 1, Execute string instruction 1 string instruction 2 CXHCX-1 2 Xe CK-1 Examples Examples . MOV AX, @data MOV AX, @data MOV DS, AX MOV DS, AX MOV ES, AX.licroprocessors (MSBTE - Sem cp MOV CX, length of string MOV SI, OFFSET $_STRING MOV DI, OFFSET D_STRING REPE CMPSB or CMPSW INE NOT_EQU STREQU: MOV AXOIH NOT_eQU: MOV AX, OH Se eee Example 3.4.1 SUE TES HAL, BL and CL contain 40H, 10H and 20H respectively. ‘State the effect of following instructions. ‘Solution : () CMP BL, CL : CF = 1, ZF = 0, SF = 1 35 compare instruction perform non-destructive subtract operation which indicate BL< CL. z ) XCHG AL, CL : After the execution AL coniain 20H and CL contain 10H ae Example 3.4.2 EYE ay ‘Write assembly language instructions of 8066” a microprocessor to fa) ‘Add 100H to contents of AX register ©) Rotate the contents of AX towards left by 2 bits ‘Solution : @ Add 100H to contents of AX register: ADD AX, 100H (©) Rotate the contents of AX towards left by 2 bits MoV CL, 2 ROL AX CL Example 34.3 ms instructions. {@) Move 2000 H into CS register, Solution : © Maliplying AL register contents by 4 using shin MOV CL,02H SHL ALCL @ Moving 2000 H into CS register ‘MOV AX, 2000H MOV CS, Ax 3-29 Instruction Set of 8086 1 Examplo 3.6.4 SAEDATIERET Write assembly language, instructions 4 microprocessor to (1) Divide the content of AX register by 50H (2) Rotate content of BX reser by 4 bt tomar pg nm: {Dine te content of AX register by SOH ‘MOV BL, 50H DIVBL - (2) Rotate the content of BX register by 4 bit toward ep ‘MOV CL, O44 ROL BX, CL or RCL BX, CL Example 245 SES | We an instructions of 8086 to pertorm following op (Shit he content of BX register 3 bit toward io, (i). Move 1234H in DS register. Solution : (@ Toshift the content of BX register 3 bit toward teh MOV CL, 03H SHL BX, CL or SAL BX, CL (i) Tomove 1234H in DS register MOV AX, 1234 MOV DS, AX Example 3.4.6 ERIS) How many times LOOP1 will be ‘executed in the Program. Wte the content of AL register afler the execuse ‘of fllowing program. 5 MOV CL, oo MOV AL, OOH LOOP: ADD AL, o1H DEC cL NZ LooPt ~ Hence the Loop will be executed 256 Times. The Value of Willbe decremented from FFH to OO ~ PReconteat of AL is ‘0 and itis incremented by 1 hence Valve of AL will g0 from OOH to FFH but after the iteration the Value of AL wit, be OOH, - ‘Tevlore he vale of AL = OH an CL nogPa deny Li "tions, 2 solution : (Move S000H to register __ MOV DX, soon " Moliply AL by ost: MOV BL, OSH MUL BL BaneeS42 Sg —————__ \Wirte assembly language instruction of Boae i 0 (Copy 1000H to register BX (Rotate register BL lott four ti mos Solution : (Copy 1000H to register BX MOV BX, 10008 Rotate register BL teft four tines MOV CLS ROL BL, CLOR RCL BLCL —_— a wal ba, ne ‘content of register AL after ths executon of MOV AL, 02H a MOV BL, 02H SUB AL, BL MUL 08H Solution : MOV AL, 02H; ‘MOV BL, 02H ; SUBAL,BL ; MULOSH Loads 02H byte in AL register ‘Loads 02H byte im BL Register Subtract BL from AL, AL becomes OOH MUL instruction cannot used in 3 immediate addressing mode Hence, during the execution of MUL 08H instruction, you will get the error. Example 3.4.10 | White an appropriate 8086 instruction to perform following operation Example 34.11 KSEE ro We assombylrguageinstucon ot e088 miroproceesr Multiply 4H by SH Rotate content of AX by 4tittowards oft) Solution : ©) Mottipty att by si MOV AL ttt MOV BLOsH MULBL (i) Rotate content of AX by 4 bit towards left MOV CLA ROL AX, CLOR RCLAXCL. Example 3. ‘What wil be the content of register ‘BX after execution of instruction? MOV BX, 20501. ‘MOV CL, OSH SALE. CL 8 2E Sotution : = MOV BX, 2050 instruction loads BX register with, valve 2050H [MOV CL, OSH instruction load CL register with value OSH ~SHL BX, CL instruction shifts the content of BX register toward left by 5 bits as given below. ‘x Rage = 20804 <——— Ps| 04] 05] 104] 04|04] 05] 04] 0.0 sfolololo |b | On] Om] 05 O4 ofolsfololololololsle Da bs ololrfololololololslolsfolofofolol s ololofolsfolrjolololojololo Foy met n BX = OADM rig ees ont Example 3.4.13 SSEROTETE ‘ : Write assembly !anguage instruction of 8086 microprocessor io. : (i) Add 100 H to the contents of AX register. (i) Rotate the contents of AX towards let by 2 bis. Solution : (Add 100 H to the contents of AX register. MOV AX, 100H () Initialize stack of 4200H (i) Muttiply AL by OSH Solution : 7 (@) Initialize stack of 4200H MOV AX, 4200H MOV SS, AX (i) Multiply AL by OSH MOV BL,0SH MULBL.i) Rotate the contents of AX towards left by 2 bits. MOV CL,02H ROL AX, CL OR RCL AX,CL How many times LOOPt wil be exéeuled In folowing program? What will be the contents of BL after the execution 7 MOV BL, OOH MOV CL, OSH ‘ADD BL, 02 H DEC CL NZ LOOP. LOOP! : Solution : : <= ~ In above program, initial counter value in CL is OSH ang when the instruction DEC CL is executed fs time, the yas in CL register became 04H. Hence the LOOP1 ee ea will be decremented from OSH to 00H. - Tic content of BL is ‘0" and after adding O2H five times the content of BL will be OAH. Chapter Ends, QoQ