Microprocessor 8086 - Interfacing

EC 1601 – Microprocessors and Microcontrollers Department of CSE 2022-2023
UNIT III I/O INTERFACING

1. Memory Interfacing and I/O interfacing
Interface is the path for communication between two components. Interfacing is of two types,
memory interfacing and I/O interfacing.
Memory Interfacing: When we are executing any instruction, we need the microprocessor to access
the memory for reading instruction codes and the data stored in the memory. For this, both the
memory and the microprocessor requires some signals to read from and write to registers.
The interfacing process includes some key factors to match with the memory requirements and
microprocessor signals. The interfacing circuit therefore should be designed in such a way that it
matches the memory signal requirements with the signals of the microprocessor.
IO Interfacing: There are various communication devices like the keyboard, mouse, printer, etc. So,
we need to interface the keyboard and other devices with the microprocessor by using latches and
buffers. This type of interfacing is known as I/O interfacing.
8086 architecture implements independent memory and input/output address spaces
Memory address space- 1,048,576 bytes long (1M-byte)—00000H-FFFFFH

Input/output address space- 65,536 bytes long (64K-bytes)—0000H-FFFFH
Input/output can be implemented in either the memory or I/O address space
Each input/output address is called a port: The 8086 microcomputers can employ two
different types of input/output (I/O):
St. Joseph’s College of Engineering & St. Joseph’s Institute of Technology Page 1 of 32
• Isolated I/O.
• Memory-mapped I/O
(a) Interfacing I/O
Minimum Mode Interface:
Similar in structure and operation to memory interface I/O devices—can represent LEDs, switches,
keyboard, serial communication port, printer port, etc. I/O data transfers take place between I/O
devices and MPU over the multiplexed-address data bus AD0-AD7, A8-A15 .
This interface use the control signals review:
• ALE = pulse to logic 1 tells bus interface circuitry to latch I/O address
• RD = logic 0 tells the I/O interface circuitry that an input (read) is in progress
• WR = logic 0 tells the I/O interface circuitry that an output (write) is in progress
• M IO = logic 0 tells I/O interface circuits that the data transfer operation is for the IO
subsystem
• DT R = sets the direction of the data bus for input (read) or output (write) operation
• DEN= enables the interface between the I/O subsystem and MPU data bus
Maximum Mode Interface:

Maximum-mode interface differences review
8288 bus controller produces the control signals for I/O subsystem
Signal changes
IORC replaces RD
IOWC and AIOWC replace WR
DEN is complement of DEN
M IO no longer needed (bus controller creates separate IO read/write controls)
(b) Interfacing Memory:

Any application of a microprocessor based system requires the transfer of data between external
circuitry to the microprocessor and microprocessor to the external circuitry. Most of the peripheral
devices are designed and interfaced with a CPU either to enable it to communicate with the user or
an external process and to ease the circuit operations so that the microprocessor works more
efficiently.
The use of peripheral integrated devices simplifies both the hardware circuits and software
considerable. The following are the devices used in interfacing of Memory and General I/O devices
• 74LS138 (Decoder / Demultiplexer).
• 74LS373 / 74LS374 3-STATE Octal D-Type Transparent Latches.
• 74LS245 Octal Bus Transceiver: 3-State.
74LS138 (Decoder / Demultiplexer):

The LS138 is a high speed 1-of-8 Decoder/ Demultiplexer fabricated with the low power Schottky
barrier diode process. The decoder accepts three binary weighted inputs (A0, A1, A2) and when
enabled provides eight mutually exclusive active LOW Outputs (O0–O7).
The LS138 can be used as an 8-output demultiplexer by using one of the active LOW Enable
inputs as the data input and the other Enable inputs as strobes. The Enable inputs which are not
used must be permanently tied to their appropriate active HIGH or active LOW state.
74LS245 Octal Bus Transceiver: 3-State:
The 74LS245 is a high-speed Si-gate CMOS device. The 74LS245 is an octal transceiver featuring
non- inverting 3-state bus compatible outputs in both send and receive directions. The 74LS245
features an Output Enable (OE) input for easy cascading and a send/receive (DIR) input for
direction control. OE controls the outputs so that the buses are effectively isolated. All inputs have
a Schmitt-trigger action.
These octal bus transceivers are designed for asynchronous two-way communication between data
buses. The 74LS245 is a high-speed Si-gate CMOS device. The 74LS245 is an octal transceiver
featuring non-inverting 3-state bus compatible outputs in both send and receive directions.
The 74LS245 features an Output Enable (OE) input for easy cascading and a send/receive (DIR)
input for direction control. OE controls the outputs so that the buses are effectively isolated. All
inputs have a Schmitt-trigger action. These octal bus transceivers are designed for asynchronous
two-way communication between data buses.
Memory Devices and Interfacing:
The memory interfacing circuit is used to access memory quit frequently to read instruction codes
and data stored in the memory. The read / write operations are monitored by control signals.
Semiconductor memories are of two types. Viz. RAM (Random Access Memory) and ROM (Read
Only Memory) The Semiconductor RAM‘s are broadly two types- static Ram and dynamic RAM
Static Memory Interfacing:
The general procedure of static memory interfacing with 8086 as follows:
Arrange the available memory chips so as to obtain 16-bit data bus width. The upper 8-bit
bank is called ‗odd address memory bank‘ and the lower 8-bit bank is called ‗even address
memory bank‘.
Connect available memory address lines of memory chips with those of the microprocessor
and also connect the memory RD and WR inputs to the corresponding processor control
signals. Connect the 16-bit data bus of the memory bank with that of the microprocessor
8086.
The remaining address lines of the microprocessor, BHE and Ao are used for decoding the
required chip select signals for the odd and even memory banks. The CS of memory is
derived from the output of the decoding circuit.
As a good and efficient interfacing practice, the address map of the system should be
continuous as far as possible
Dynamic RAM Interfacing:

The basic Dynamic RAM cell uses a capacitor to store the charge as a representation of
data. This capacitor is manufactured as a diode that is reverse-biased so that the storage
capacitance comes into the picture. This storage capacitance is utilized for storing the
charge representation of data but the reverse-biased diode has a leakage current that tends to
discharge the capacitor giving rise to the possibility of data loss.
To avoid this possible data loss, the data stored in a dynamic RAM cell must be refreshed
after a fixed time interval regularly. The process of refreshing the data in the RAM is known
as refresh cycle. This activity is similar to reading the data from each cell of the memory,
independent of the requirement of microprocessor, regularly. During this refresh period all
other operations (accesses) related to the memory subsystem are suspended.
The advantages of dynamic RAM. Like low power consumption, higher packaging density
and low cost, most of the advanced computer systems are designed using dynamic RAMs.
Also the refresh mechanism and the additional hardware required makes the interfacing
hardware, in case of dynamic RAM, more complicated, as compared to static RAM
interfacing circuit.
Basics in Memory Interfacing:
The data bus is 16-bits wide.

The IO/ M pin is replaced with M/ IO (8086/80186) and MRDC and MWTC for 80286 and
80386SX.
BHE , Bus High Enable, control signal is added.
Address pin A 0 (or BLE , Bus Low Enable ) is used differently.
The 16-bit data bus presents a new problem:

o The microprocessor must be able to read and write data to any 16-
bit location in addition to any 8-bit location.
o The data bus and memory are divided into banks:
o
BHE and BLE are used to select one or both:

BHE BLE Function
0 0 Both banks enabled for 16-bit transfer
0 1 High bank enabled for an 8-bit transfer
1 0 Low bank enabled for an 8-bit transfer
1 1 No banks selected
Bank selection can be accomplished in two ways:
Separate write decoders for each bank (which drive CS ).
A separate write signal (strobe) to each bank (which drive WE ).
There does not seem to be a big difference between these methods although the book claims
that there is.
Memory Architecture:
In order to build an N-word memory where each word is M bits wide (typically 1, 4 or 8
bits), a straightforward approach is to stack memory:
Memory Architecture
Add a decoder to solve the package problem:
This does not address the memory aspect ratio problem:

20 3
o The memory is 128,000 time higher than wide (2 /2 ) !
o Besides the bizarre shape factor, the design is extremely slow since the vertical wires are
VERY long (delay is at least linear to length).
Memory Architecture
The vertical and horizontal dimensions are usually very similar, for an aspect ratio of unity .
Multiple words are stored in each row and selected simultaneously:
Memory Architecture
This strategy works well for memories up to 64 Kbits to 256 Kbits.
Larger memories start to suffer excess delay along bit and word lines.
A third dimension is added to the address space to solve this problem:
Dynamic RAM:
DRAM requires refreshing every 2 to 4 ms .
o Refreshing occurs automatically during a read or write.
o Internal circuitry takes care of refreshing cells that are not accessed over this interval.
This special refresh occurs transparently while other memory components operate and is
called transparent refresh or cycle stealing .
A RAS -only cycle strobes a row address into the DRAM, obtained by 7- or 8-bit binary
counter.
The capacitors are recharged for the selected row by reading the bits out internally and then
writing them back.
For a 256K X 1 DRAM with 256 rows, a refresh must occur every 15.6us (4ms/256).
o For the 8086, a read or write occurs every 800ns .
o This allows 19 memory reads/writes per refresh or 5% of the time.
Dynamic RAM:
EDO and SDRAM Memory:

Extended Data Output memory :
o Any memory access in an EDO memory (including a refresh) stores the 256 bits in a set of
latches.
o Any subsequent access to bytes in this set are immediately available ( without the decode
time and therefore wait states).
o This works well because of the principle of spatial locality, and improves system performance
by 15 to 25 %
2. Parallel and Serial communication interface:
Parallel Communication Interface: 8255 Programmable Peripheral Interface

and Interfacing
The 8255 is a widely used, programmable parallel I/O device. It can be programmed to transfer data
under data under various conditions, from simple I/O to interrupt I/O. It is flexible, versatile and
economical (when multiple I/O ports are required). It is an important general purpose I/O device
that can be used with almost any microprocessor.
The 8255 has 24 I/O pins that can be grouped primarily into two 8 bit parallel ports: A and B, with
the remaining 8 bits as Port C. The 8 bits of port C can be used as individual bits or be grouped into
two 4 bit ports: CUpper (CU) and CLower (CL). The functions of these ports are defined by writing
a control word in the control register.
8255 can be used in two modes: Bit set/Reset (BSR) mode and I/O mode. The BSR mode is used to
set or reset the bits in port C. The I/O mode is further divided into 3 modes: mode 0, mode 1 and
mode 2. In mode 0, all ports function as simple I/O ports.
Mode 1 is a handshake mode whereby Port A and/or Port B use bits from Port C as handshake
signals. In the handshake mode, two types of I/O data transfer can be implemented: status check
and interrupt. In mode 2, Port A can be set up for bidirectional data transfer using handshake
signals from Port C, and Port B can be set up either in mode 0 or mode 1.
PPI 8255 is a general purpose programmable I/O device designed to interface the CPU with its
outside world such as ADC, DAC, keyboard etc. We can program it according to the given
condition. It can be used with almost any microprocessor.
It consists of three 8-bit bidirectional I/O ports i.e. PORT A, PORT B and PORT C. We can assign
different ports as input or output functions.
Block diagram :
It consists of 40 pins and operates in +5V regulated power supply. Port C is further divided into two
4-bit ports i.e. port C lower and port C upper and port C can work in either BSR (bit set rest) mode
or in mode 0 of input-output mode of 8255. Port B can work in either mode or in mode 1 of input-
output mode. Port A can work either in mode 0, mode 1 or mode 2 of input-output mode.
It has two control groups, control group A and control group B. Control group A consist of port A
and port C upper. Control group B consists of port C lower and port B.
Depending upon the value if CS‘, A1 and A0 we can select different ports in different modes as
input-output function or BSR. This is done by writing a suitable word in control register (control
word D0-D7).
CS’ A1 A0 SELECTION ADDRESS
0 0 0 PORT A 80 H
0 0 1 PORT B 81 H
0 1 0 PORT C 82 H
0 1 1 Control Register 83 H
1 X X No Seletion X
Pin diagram:
PA0 – PA7 – Pins of port A

PB0 – PB7 – Pins of port B
PC0 – PC7 – Pins of port C
D0 – D7 – Data pins for the transfer of data
RESET – Reset input

RD’ – Read input
WR’ – Write input
CS’ – Chip select
A1 and A0 – Address pins
Operating modes –
1. Bit set reset (BSR) mode
If MSB of control word (D7) is 0, PPI works in BSR mode. In this mode only port C bits are
used for set or reset.
2. Input-Output mode:
If MSB of control word (D7) is 1, PPI works in input-output mode. This is further divided into
three modes:
Mode 0 –In this mode all the three ports (port A, B, C) can work as simple input function or
simple output function. In this mode there is no interrupt handling capacity.
Mode 1 – Handshake I/O mode or strobbed I/O mode. In this mode either port A or port B
can work as simple input port or simple output port, and port C bits are used for handshake
signals before actual data transmission. It has interrupt handling capacity and input and
output are latched.
Example: A CPU wants to transfer data to a printer. In this case since speed of processor is
very fast as compared to relatively slow printer, so before actual data transfer it will send
handshake signals to the printer for synchronization of the speed of the CPU and the
peripherals.
Mode 2 – Bi-directional data bus mode. In this mode only port A works, and port B can
work either in mode 0 or mode 1. 6 bits port C are used as handshake signals. It also has
interrupt handling capacity.
8251 USART:
8251 universal synchronous asynchronous receiver transmitter (USART) acts as a mediator
between microprocessor and peripheral to transmit serial data into parallel form and vice versa.
It takes data serially from peripheral (outside devices) and converts into parallel data.
After converting the data into parallel form, it transmits it to the CPU.
Similarly, it receives parallel data from microprocessor and converts it into serial form.
After converting data into serial form, it transmits it to outside device (peripheral).
It contains the following blocks:

1. Data bus buffer –
This block helps in interfacing the internal data bus of 8251 to the system data bus. The data
transmission is possible between 8251 and CPU by the data bus buffer block.
2. Read/Write control logic –

It is a control block for overall device. It controls the overall working by selecting the operation
to be done. The operation selection depends upon input signals as:
In this way, this unit selects one of the three registers- data buffer register, control register,
status register.
3. Modem control (modulator/demodulator) –
A device converts analog signals to digital signals and vice-versa and helps the computers to
communicate over telephone lines or cable wires. The following are active-low pins of Modem.
DSR: Data Set Ready signal is an input signal.
DTR: Data terminal Ready is an output signal.
CTS: It is an input signal which controls the data transmit circuit.
RTS: It is an output signal which is used to set the status RTS.
4. Transmit buffer –
This block is used for parallel to serial converter that receives a parallel byte for conversion into
serial signal and further transmission onto the common channel.
TXD: It is an output signal, if its value is one, means transmitter will transmit the data.
5. Transmit control –
This block is used to control the data transmission with the help of following pins:
TXRDY: It means transmitter is ready to transmit data character.
TXEMPTY: An output signal which indicates that TXEMPTY pin has transmitted all the
data characters and transmitter is empty now.
TXC: An active-low input pin which controls the data transmission rate of transmitted data.
6. Receive buffer –
This block acts as a buffer for the received data.

RXD: An input signal which receives the data.
7. Receive control –
This block controls the receiving data.

RXRDY: An input signal indicates that it is ready to receive the data.
RXC: An active-low input signal which controls the data transmission rate of received data.
SYNDET/BD: An input or output terminal. External synchronous mode-input terminal and
asynchronous mode-output terminal
3. D/A and A/D Interface

The function of an A/D converter is to produce a digital word which represents the magnitude of
some analog voltage or current.
The specifications for an A/D converter are very similar to those for D/A converter:
The resolution of an A/D converter refers to the number of bits in the output binary word. An 8-bit
converter for example has a resolution of 1 part in 256.
Accuracy and linearity specifications have the same meaning for an A/D converter as they do for a
D/A converter.
Another important specification for an ADC is its conversion time. It is the time it takes the
converter to produce a valid output binary code for an applied input voltage. When we refer to a
converter as high speed, it has a short conversion time.
The analog to digital converter is treated as an input device by the microprocessor that sends an
initialising signal to the ADC to start the analog to digital data conversation process.
The start of conversion signal is a pulse of a specific duration. The process of analog to digital
conversion is a slow process, and the microprocessor has to wait for the digital data till the
conversion is over.
After the conversion is over, the ADC sends end of conversion (EOC) signal to inform the
microprocessor that the conversion is over and the result is ready at the output buffer of the ADC.
These tasks of issuing an SOC pulse to ADC, reading EOC signal from the ADC and reading the
digital output of the ADC are carried out by the CPU using 8255 I/O ports. The time taken by the
ADC from the active edge of SOC pulse (the edge at which the conversion process actually starts) till
the active edge of
EOC signal is called as the conversion delay of the ADC- the time taken by the converter to calculate
the equivalent digital data output from the instant of the start of conversion is called conversion
delay. It may range anywhere from a few microseconds in case of fast ADCs to even a few hundred
milliseconds in case of slow ADCs.
A number of ADCs are available in the market, the selection of ADC for a particular application is
done, keeping in mind the required speed, resolution range of operation, power supply requirements,
sample and hold device requirements and the cost factors are considered.
The available ADCs in the market use different conversion techniques for the conversion of analog
signals to digital signals.
Parallel converter or flash converter, Successive approximation and dual slope integration
A general algorithm for ADC interfacing contains the following steps.
o Ensure the stability of analog input, applied to the ADC.
o Issue start of conversion (SOC) pulse to ADC.
o Read end of conversion (EOC) signal to mark the end of conversion process.
o Read digital data output of the ADC as equivalent digital output.
It may be noted that analog input voltage must be constant at the input of the ADC right from the
start of conversion till the end of conversion to get correct results. This may be ensured by a sample
and hold circuit which samples the analog signal and holds it constant for a specified time duration.
The microprocessor may issue a hold signal to the sample and Hold circuit. If the applied input
changes before the complete conversion process is over, the digital equivalent of the analog input
calculated by the ADC may not be correct. If the applied input changes before the complete
conversion process is over, the digital equivalent of the analog input calculated by the ADC may not
be correct.
ADC 0808/0809: The analog to digital converter chips 0808 and 0809 are 8-
bit CMOS, successive approximation converters. Successive approximation technique is one of
the fast techniques for analog to digital conversion. The conversion delay is 100 μs at a clock
frequency of 640 kHz, which is quite low as compared to other converters.
These converters do not need any external zero or full scale adjustments as they are already taken
care of by internal circuits. These converters internally have a 3:8 analog multiplexer so that at a time
eight different analog inputs can be connected to the chips. Out of these eight inputs only one can be
selected for conversion by using address lines ADD A, ADD B and ADD C, as shown. Using these
address inputs, multichannel data acquisition systems can be designed using a single ADC.
The CPU may drive these lines using output port lines in case of multichannel applications. In case
of single input applications, these may be hard wired to select the proper input.
Only positive analog input voltages to their digital equivalents. These chips do not contain any
internal sample and hold circuit. If one needs a sample and hold circuit for the conversion of fast,
signals into equivalent digital quantities, it has to be externally connected at each of the analog
inputs.
INTERFACING DIGITAL TO ANALOG ONVERTERS:
The digital to analog converters convert binary numbers into their analog equivalent voltages or
currents. Several techniques are employed for digital to analog conversion.
i. Weighted resistor network
ii. R-2R ladder network
iii. Current output D/A converter
DAC 0800 8-bit Digital to Analog converter Features:

i. DAC0800 is a monolithic 8-bit DAC manufactured by National semiconductor.
ii. It has settling time around 100ms
iii. It can operate on a range of power supply voltage i.e. from 4.5V to +18V. Usually the
supply V+ is 5V or +12V. The V- pin can be kept at a minimum of - 12V.
iv. Resolution of the DAC is 39.06mV
DAC0808 is a D/A converter IC and is used for converting 8 bit digital data input to analog signal
output. It is a monolithic IC featuring a full scale output current settling time of 150 ns while
dissipating only 33 mW with ±5V supplies. The chip accuracy of conversion is good and power
consumption is also low to make it popular. The power supply currents of the DAC0808 are
independent of bit codes, and exhibits essentially constant device characteristics over the entire
supply voltage range.
Features and Electrical characteristics of DAC0808:
8 bit parallel digital data input
Fast settling time (typical value): 150 ns
Relative accuracy at ±0.19% maximum error
Full scale current match: ±1 LSB
Non-inverting digital inputs are TTL and CMOS compatible
High speed multiplying input slew rate: 8 mA/μs
Power supply voltage range: ±4.5V to ±18V
Low power consumption: 33 mW@ ±5V
Maximum Power dissipation: 1000 mW
Operating temperature range: 0ºC to +75ºC
4. Timer
The Intel 8253 and 8254 are Programmable Interval Timers (PTIs) designed for microprocessors
to perform timing and counting functions using three 16-bit registers. Each counter has 2 input
pins, i.e. Clock & Gate, and 1 pin for ―OUT‖ output. To operate a counter, a 16-bit count is loaded
in its register. On command, it begins to decrement the count until it reaches 0, then it generates a
pulse that can be used to interrupt the CPU.
Difference between 8253 and 8254
The following table differentiates the features of 8253 and 8254 −
8253 8254
Its operating frequency is 0 - 2.6 MHz Its operating frequency is 0 - 10 MHz
It uses N-MOS technology It uses H-MOS technology
Read-Back command is not available Read-Back command is available
Reads and writes of the same counter Reads and writes of the same counter can
cannot be interleaved. be interleaved.
8254 Architecture: The architecture of 8254 looks as follows:
8254 Pin Description
Here is the pin diagram of 8254 −
In the above figure, there are three counters, a data bus buffer, Read/Write control logic, and a
control register. Each counter has two input signals - CLOCK & GATE, and one output signal -
OUT.
Features of 8253 / 54:
The most prominent features of 8253/54 are as follows −

It has three independent 16-bit down counters.
It can handle inputs from DC to 10 MHz.
These three counters can be programmed for either binary or BCD count.
It is compatible with almost all microprocessors.
8254 has a powerful command called READ BACK command, which allows the user to
check the count value, the programmed mode, the current mode, and the current status of
the counter.
Data Bus Buffer:
It is a tri-state, bi-directional, 8-bit buffer, which is used to interface the 8253/54 to the system data
bus. It has three basic functions −
Programming the modes of 8253/54.

Loading the count registers.
Reading the count values.
Read/Write Logic:
It includes 5 signals, i.e. RD, WR, CS, and the address lines A0 & A1. In the peripheral I/O mode,
the RD and WR signals are connected to IOR and IOW, respectively. In the memorymapped I/O
mode, these are connected to MEMR and MEMW.
Address lines A0 & A1 of the CPU are connected to lines A0 and A1 of the 8253/54, and CS is tied
to a decoded address. The control word register and counters are selected according to the signals
on lines A0 & A1.
A1 A0 Result
0 0 Counter 0
0 1 Counter 1
1 0 Counter 2
1 1 Control Word Register
X X No Selection
Control Word Register:

This register is accessed when lines A0 & A1 are at logic 1. It is used to write a command word,
which specifies the counter to be used, its mode, and either a read or write operation. Following
table shows the result for various control inputs.
A1 A0 RD WR CS Result
0 0 1 0 0 Write Counter 0
1 1 1 0 0 Write Control Word
0 0 0 1 0 Read Counter 0
1 1 0 1 0 No operation
X X 1 1 0 No operation
X X X X 1 No operation
Counters:
Each counter consists of a single, 16 bit-down counter, which can be operated in either binary or
BCD. Its input and output is configured by the selection of modes stored in the control word
register. The programmer can read the contents of any of the three counters without disturbing the
actual count in process.
5. Keyboard /display controller:
8279 programmable keyboard/display controller is designed by Intel that interfaces a keyboard
with the CPU. The keyboard first scans the keyboard and identifies if any key has been pressed. It
then sends their relative response of the pressed key to the CPU and vice-a-versa.
The Keyboard can be interfaced either in the interrupt or the polled mode. In the Interrupt mode,
the processor is requested service only if any key is pressed, otherwise the CPU will continue with
its main task.
Architecture and Description:
In the Polled mode, the CPU periodically reads an internal flag of 8279 to check whether any key
is pressed or not with key pressure.
The keyboard consists of maximum 64 keys, which are interfaced with the CPU by using the key-
codes. These key-codes are de-bounced and stored in an 8-byte FIFORAM, which can be accessed
by the CPU. If more than 8 characters are entered in the FIFO, then it means more than eight keys
are pressed at a time. This is when the overrun status is set.
If a FIFO contains a valid key entry, then the CPU is interrupted in an interrupt mode else the CPU
checks the status in polling to read the entry. Once the CPU reads a key entry, then FIFO is
updated, and the key entry is pushed out of the FIFO to generate space for new entries.
I/O Control and Data Buffer:
This unit controls the flow of data through the microprocessor. It is enabled only when D is low.
Its data buffer interfaces the external bus of the system with the internal bus of the microprocessor.
The pins A0, RD, and WR are used for command, status or data read/write operations.
Control and Timing Register and Timing Control
This unit contains registers to store the keyboard, display modes, and other operations as
programmed by the CPU. The timing and control unit handles the timings for the operation of the
circuit.
Scan Counter:
It has two modes i.e. Encoded mode and Decoded mode. In the encoded mode, the counter
provides the binary count that is to be externally decoded to provide the scan lines for the
keyboard and display.
In the decoded scan mode, the counter internally decodes the least significant 2 bits and provides a
decoded 1 out of 4 scan on SL0-SL3.
Return Buffers, Keyboard Debounce, and Control:
This unit first scans the key closure row-wise, if found then the keyboard debounce unit debounces
the key entry. In case, the same key is detected, then the code of that key is directly transferred to
the sensor RAM along with SHIFT & CONTROL key status.
FIFO/Sensor RAM and Status Logic
This unit acts as 8-byte first-in-first-out (FIFO) RAM where the key code of every pressed key is
entered into the RAM as per their sequence. The status logic generates an interrupt request after
each FIFO read operation till the FIFO gets empty.
In the scanned sensor matrix mode, this unit acts as sensor RAM where its each row is loaded with
the status of their corresponding row of sensors into the matrix. When the sensor changes its state,
the IRQ line changes to high and interrupts the CPU.
Display Address Registers and Display RAM

This unit consists of display address registers which holds the addresses of the word currently
read/written by the CPU to/from the display RAM.
8279 − Pin Description:
Data Bus Lines, DB0 - DB7 : These are 8 bidirectional data bus lines used to transfer the data
to/from the CPU.
CLK: The clock input is used to generate internal timings required by the microprocessor.
RESET: As the name suggests this pin is used to reset the microprocessor.
CS Chip Select: When this pin is set to low, it allows read/write operations, else this pin should be
set to high.
A0: This pin indicates the transfer of command/status information. When it is low, it indicates the
transfer of data.
RD, WR: This Read/Write pin enables the data buffer to send/receive data over the data bus.
IRQ: This interrupt output line goes high when there is data in the FIFO sensor RAM. The interrupt
line goes low with each FIFO RAM read operation. However, if the FIFO RAM further contains
any key-code entry to be read by the CPU, this pin again goes high to generate an interrupt to the
CPU.
Vss, Vcc: These are the ground and power supply lines of the microprocessor.
SL0 − SL3: These are the scan lines used to scan the keyboard matrix and display the digits. These
lines can be programmed as encoded or decoded, using the mode control register.
RL0 − RL7: These are the Return Lines which are connected to one terminal of keys, while the other
terminal of the keys is connected to the decoded scan lines. These lines are set to 0 when any key is
pressed.
SHIFT: The Shift input line status is stored along with every key code in FIFO in the scanned
keyboard mode. Till it is pulled low with a key closure, it is pulled up internally to keep it high
CNTL/STB - CONTROL/STROBED I/P Mode

In the keyboard mode, this line is used as a control input and stored in FIFO on a key closure. The
line is a strobe line that enters the data into FIFO RAM, in the strobed input mode. It has an
internal pull up. The line is pulled down with a key closure.
BD
It stands for blank display. It is used to blank the display during digit switching.
OUTA0 – OUTA3 and OUTB0 – OUTB3

These are the output ports for two 16x4 or one 16x8 internal display refresh registers. The data
from these lines is synchronized with the scan lines to scan the display and the keyboard.
Operational Modes of 8279
There are two modes of operation on 8279 − Input Mode and Output Mode.
Input Mode
This mode deals with the input given by the keyboard and this mode is further classified into 3
modes.
Scanned Keyboard Mode − In this mode, the key matrix can be interfaced using either
encoded or decoded scans. In the encoded scan, an 8×8 keyboard or in the decoded scan, a
4×8 keyboard can be interfaced. The code of key pressed with SHIFT and CONTROL
status is stored into the FIFO RAM.
Scanned Sensor Matrix − In this mode, a sensor array can be interfaced with the processor
using either encoder or decoder scans. In the encoder scan, 8×8 sensor matrix or with
decoder scan 4×8 sensor matrix can be interfaced.
Strobed Input − In this mode, when the control line is set to 0, the data on the return lines
is stored in the FIFO byte by byte.
Output Mode
This mode deals with display-related operations. This mode is further classified into two output
modes.
Display Scan − This mode allows 8/16 character multiplexed displays to be organized as
dual 4-bit/single 8-bit display units.
Display Entry − This mode allows the data to be entered for display either from the right
side/left side.
6. Interrupt controller
8259 microprocessor is defined as Programmable Interrupt Controller (PIC) microprocessor.
There are 5 hardware interrupts and 2 hardware interrupts in 8085 and 8086 respectively. But by
connecting 8259 with CPU, we can increase the interrupt handling capability. 8259 combines the
multi interrupt input sources into a single interrupt output. Interfacing of single PIC provides 8
interrupts inputs from IR0-IR7.
For example, Interfacing of 8085 and 8259 increases the interrupt handling capability of 8085
microprocessor from 5 to 8 interrupt levels.
Features of 8259 PIC microprocessor:
Intel 8259 is designed for Intel 8085 and Intel 8086 microprocessor.
It can be programmed either in level triggered or in edge triggered interrupt level.
We can masked individual bits of interrupt request register.
We can increase interrupt handling capability upto 64 interrupt level by cascading further
8259 PIC.
Clock cycle is not required.
Pin Diagram of 8259:
Block Diagram of 8259 PIC:
The Block Diagram consists of 8 blocks which are – Data Bus Buffer, Read/Write Logic, Cascade
Buffer Comparator, Control Logic, Priority Resolver and 3 registers- ISR, IRR, IMR.
1. Data bus buffer :
This Block is used as a mediator between 8259 and 8085/8086 microprocessor by acting as a
buffer. It takes the control word from the 8085 (let say) microprocessor and transfer it to the
control logic of 8259 microprocessor. Also, after selection of Interrupt by 8259
microprocessor, it transfer the opcode of the selected Interrupt and address of the Interrupt
service sub routine to the other connected microprocessor. The data bus buffer consists of 8
bits represented as D0-D7 in the block diagram. Thus, shows that a maximum of 8 bits data
can be transferred at a time.
2. Read/Write logic:
This block works only when the value of pin CS is low (as this pin is active low). This block is
responsible for the flow of data depending upon the inputs of RD and WR. These two pins are
active low pins used for read and write operations.
3. Control logic :
It is the centre of the microprocessor and controls the functioning of every block. It has pin
INTR which is connected with other microprocessor for taking interrupt request and pin INT
for giving the output. If 8259 is enabled, and the other microprocessor Interrupt flag is high
then this causes the value of the output INT pin high and in this way 8259 responds to the
request made by other microprocessor.
4. Interrupt request register (IRR) :
It stores all the interrupt level which are requesting for Interrupt services.
5. Interrupt service register (ISR) :
It stores the interrupt level which are currently being executed.
6. Interrupt mask register (IMR) :
It stores the interrupt level which have to be masked by storing the masking bits of the
interrupt level.
7. Priority resolver :
It examines all the three registers and set the priority of interrupts and according to the priority
of the interrupts, interrupt with highest priority is set in ISR register. Also, it reset the interrupt
level which is already been serviced in IRR.
8. Cascade buffer :
To increase the Interrupt handling capability, we can further cascade more number of pins by
using cascade buffer. So, during increment of interrupt capability, CSA lines are used to
control multiple interrupt structure.
SP/EN (Slave program/Enable buffer) pin is when set to high, works in master mode else in slave
mode. In Non Buffered mode, SP/EN pin is used to specify whether 8259 work as master or slave
and in Buffered mode, SP/EN pin is used as an output to enable data bus.
7. DMA controller:
DMA stands for Direct Memory Access. It is designed by Intel to transfer data at the fastest rate. It
allows the device to transfer the data directly to/from memory without any interference of the
CPU. Using a DMA controller, the device requests the CPU to hold its data, address and control
bus, so the device is free to transfer data directly to/from the memory. The DMA data transfer is
initiated only after receiving HLDA signal from the CPU.
Following is the sequence of operations performed by a DMA:
Initially, when any device has to send data between the device and the memory, the device
has to send DMA request (DRQ) to DMA controller.
The DMA controller sends Hold request (HRQ) to the CPU and waits for the CPU to assert
the HLDA.
Then the microprocessor tri-states all the data bus, address bus, and control bus. The CPU
leaves the control over bus and acknowledges the HOLD request through HLDA signal.
Now the CPU is in HOLD state and the DMA controller has to manage the operations over
buses between the CPU, memory, and I/O devices.
Features of 8257:
It has four channels which can be used over four I/O devices.
Each channel has 16-bit address and 14-bit counter.
Each channel can transfer data up to 64kb.
Each channel can be programmed independently.
Each channel can perform read transfer, write transfer and verify transfer operations.
It generates MARK signal to the peripheral device that 128 bytes have been transferred.
It requires a single phase clock.
Its frequency ranges from 250Hz to 3MHz.
It operates in 2 modes, i.e., Master mode and Slave mode.
8257 Architecture:
8257 Pin Description
DRQ0−DRQ3: These are the four individual channel DMA request inputs, which are used by the
peripheral devices for using DMA services. When the fixed priority mode is selected, then
DRQ0 has the highest priority and DRQ3 has the lowest priority among them.
DACKo − DACK3: These are the active-low DMA acknowledge lines, which updates the requesting
peripheral about the status of their request by the CPU. These lines can also act as strobe lines for
the requesting devices.
Do − D7: These are bidirectional, data lines which are used to interface the system bus with the
internal data bus of DMA controller. In the Slave mode, it carries command words to 8257 and
status word from 8257. In the master mode, these lines are used to send higher byte of the generated
address to the latch. This address is further latched using ADSTB signal.
IOR: It is an active-low bidirectional tri-state input line, which is used by the CPU to read internal
registers of 8257 in the Slave mode. In the master mode, it is used to read data from the peripheral
devices during a memory write cycle.
IOW: It is an active low bi-direction tri-state line, which is used to load the contents of the data bus
to the 8-bit mode register or upper/lower byte of a 16-bit DMA address register or terminal count
register. In the master mode, it is used to load the data to the peripheral devices during DMA
memory read cycle.
CLK: It is a clock frequency signal which is required for the internal operation of 8257.
RESET: This signal is used to RESET the DMA controller by disabling all the DMA channels.
Ao - A3: These are the four least significant address lines. In the slave mode, they act as an input,
which selects one of the registers to be read or written. In the master mode, they are the four least
significant memory address output lines generated by 8257.
CS: It is an active-low chip select line. In the Slave mode, it enables the read/write operations
to/from 8257. In the master mode, it disables the read/write operations to/from 8257.
A4 - A7: These are the higher nibble of the lower byte address generated by DMA in the master
mode.
READY: It is an active-high asynchronous input signal, which makes DMA ready by inserting wait
states.
HRQ: This signal is used to receive the hold request signal from the output device. In the slave
mode, it is connected with a DRQ input line 8257. In Master mode, it is connected with HOLD
input of the CPU.
HLDA: It is the hold acknowledgement signal which indicates the DMA controller that the bus has
been granted to the requesting peripheral by the CPU when it is set to 1.
MEMR: It is the low memory read signal, which is used to read the data from the addressed
memory locations during DMA read cycles.
MEMW: It is the active-low three state signal which is used to write the data to the addressed
memory location during DMA write operation.
ADST: This signal is used to convert the higher byte of the memory address generated by the DMA
controller into the latches.
AEN: This signal is used to disable the address bus/data bus.
TC: It stands for ‗Terminal Count‘, which indicates the present DMA cycle to the present
peripheral devices.
MARK: The mark will be activated after each 128 cycles or integral multiples of it from the
beginning. It indicates the current DMA cycle is the 128th cycle since the previous MARK output
to the selected peripheral device.
Vcc: It is the power signal which is required for the operation of the circuit.
8. Programming and applications Case studies:
Traffic Light control:

Traffic light controller interface module is designed to simulate the function of four way traffic
light controller.
Combinations of red, amber and green LED‘s are provided to indicate Halt, Wait and Go signals for
vehicles.
Combination of red and green LED‘s are provided for pedestrian crossing. 36 LED‘s are arranged
in the form of an intersection.
A typical junction is represented on the PCB with comprehensive legend printing.
At the left corner of each road, a group of five LED‘s (red, amber and 3 green) are arranged
in the form of a T-section to control the traffic of that road.
Each road is named North (N), South(S), East (E) and West (W). LED‘s L1, L10, L19 & L28 (Red)
are for the stop signal for the vehicles on the road N, S, W, & E respectively.
L2, L11, L20 & L29 (Amber) indicates wait state for vehicles on the road N, S, W, & E
respectively. L3, L4 & L5 (Green) are for left, strait and right turn for the vehicles on road S.
similarly L12-L13-L14, L23-L22-L21 & L32-L31-L30 simulates same function for the roads E, N,
W respectively.
A total of 16 LED‘s (2 Red & 2 Green at each road) are provided for pedestrian crossing.
L7-L9.L16-L18, L25-L27 & L34-L36 (Green) when on allows pedestrians to cross and L6-L8,
L15-L17, L24-L26 & L33-L35 (Red) when on alarms the pedestrians to wait.
To minimize the hardware pedestrian‘s indicator LED‘s (both red and green are
connected to same port lines (PC4 to PC7) with red inverted.
Red LED‘s L10 & L28 are connected to port lines PC2 & PC3 while L1 & L19 are connected to
lines PC0 & PC1 after inversion. All other LED‘s (amber and green) are connected to port A & B.
Working:- 8255 is interfaced with 8086 in I/O mapped I/O and all ports are output ports. The basic
operation of the interface is explained with the help of the enclosed program. The enclosed program
assumes no entry of vehicles from North to West, from
road East to South.
At the beginning of the program all red LED‘s are switch ON, and all other LED‗s are switched
OFF. Amber LED is switched ON before switching over to proceed state from Halt state.
The sequence of traffic followed in the program is given below.
a) From road north to East From road east to north From road south to west From road west to
south From road west to north
b) From road north to East From road south to west From road south to north From road south to
east From road north to south From road south to north Pedestrian crossing at roads west & east d)
From road east to west
From road west to east Pedestrian crossing at roads north & south
Statement: Design a microprocessor system to control traffic lights. The traffic light arrangement is
as shown in Fig. The traffic should be controlled in the following manner.
1) Allow traffic from W to E and E to W transition for 20 seconds. 2) Give transition period of 5
seconds (Yellow bulbs ON) 3) Allow traffic from N to 5 and 5 to N for 20 seconds 4) Give
transition period of 5 seconds (Yellow bulbs ON) 5) Repeat the process.
Source program:
MVI A, 80H : Initialize 8255, port A and port B
OUT 83H (CR) : in output mode
START: MVI A, 09H
OUT 80H (PA) : Send data on PA to glow R1 and R2
MVI A, 24H
OUT 81H (PB) : Send data on PB to glow G3 and G4
MVI C, 28H : Load multiplier count (40ıο) for delay
CALL DELAY : Call delay subroutine
MVI A, 12H
OUT (81H) PA : Send data on Port A to glow Y1 and Y2
OUT (81H) PB : Send data on port B to glow Y3 and Y4
MVI C, 0AH : Load multiplier count (10ıο) for delay
CALL: DELAY : Call delay subroutine
MVI A, 24H
OUT (80H) PA : Send data on port A to glow G1 and G2
MVI A, 09H
OUT (81H) PB : Send data on port B to glow R3 and R4
MVI C, 28H : Load multiplier count (40ıο) for delay
MVI A, 12H
OUT PA : Send data on port A to glow Y1 and Y2
OUT PB : Send data on port B to glow Y3 and Y4
MVI C, 0AH : Load multiplier count (10ıο) for delay
JMP START
Delay Subroutine:
DELAY: LXI D, Count : Load count to give 0.5 sec delay
BACK: DCX D : Decrement counter
MOV A, D
ORA E : Check whether count is 0
JNZ BACK : If not zero, repeat
DCR C : Check if multiplier zero, otherwise repeat
JNZ DELAY
RET : Return to main program

Microprocessor 8086 - Interfacing

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Microprocessor 8086 - Interfacing

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EC 1601 – Microprocessors and Microcontrollers Department of CSE 2022-2023

UNIT III I/O INTERFACING

8086 architecture implements independent memory and input/output address spaces

Memory address space- 1,048,576 bytes long (1M-byte)—00000H-FFFFFH

Maximum Mode Interface:

(b) Interfacing Memory:

74LS138 (Decoder / Demultiplexer):

Dynamic RAM Interfacing:

Basics in Memory Interfacing:

The data bus is 16-bits wide.

The 16-bit data bus presents a new problem:

BHE and BLE are used to select one or both:

This does not address the memory aspect ratio problem:

EDO and SDRAM Memory:

2. Parallel and Serial communication interface:

Parallel Communication Interface: 8255 Programmable Peripheral Interface

PA0 – PA7 – Pins of port A

RESET – Reset input

It contains the following blocks:

2. Read/Write control logic –

This block acts as a buffer for the received data.

This block controls the receiving data.

3. D/A and A/D Interface

INTERFACING DIGITAL TO ANALOG ONVERTERS:

DAC 0800 8-bit Digital to Analog converter Features:

Difference between 8253 and 8254

The following table differentiates the features of 8253 and 8254 −

Its operating frequency is 0 - 2.6 MHz Its operating frequency is 0 - 10 MHz

It uses N-MOS technology It uses H-MOS technology

Read-Back command is not available Read-Back command is available

8254 Architecture: The architecture of 8254 looks as follows:

8254 Pin Description

Here is the pin diagram of 8254 −

Features of 8253 / 54:

The most prominent features of 8253/54 are as follows −

Programming the modes of 8253/54.

1 1 Control Word Register

Control Word Register:

1 1 1 0 0 Write Control Word

Display Address Registers and Display RAM

8279 − Pin Description:

CNTL/STB - CONTROL/STROBED I/P Mode

OUTA0 – OUTA3 and OUTB0 – OUTB3

Operational Modes of 8279

Block Diagram of 8259 PIC:

8257 Pin Description

AEN: This signal is used to disable the address bus/data bus.

8. Programming and applications Case studies:

Traffic Light control:

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