Counters & Shifters

By
Dr. Alok Kumar Rastogi
Professor of Physics
Department of Physics & Electronics
IEHE, Bhopal
COUNTERS:
INTRODUCTION:
• A counter by function is a sequential circuit consisting a set of flip
flops connected in a suitable manner to count the sequence of the
input pulses presented to it in digital form.
• Counters can be broadly classified under 3 heads as follows:
i. Asynchronous and Synchronous counters
ii. Single and multimode counters
iii. Modulus counters
Asynchronous or Ripple counters:
• They can be constructed using minimum hardware.
• In an asynchronous counter, each flip flop is triggered by the output
from the previous flip flop which limits its speed of operation.
• It is also called a serial counter.
• In synchronous counters, the speed limitation of ripple counters is
overcome by applying clock pulse simultaneously to all the flip flops
which leads to the settling time of the counter being equal to the
propagation delay of a single flip flop.
• Hence synchronous counters are also called parallel counters.
Single mode and Multimode counters:
• Single mode counters operate in a single mode, i.e., it counts either in
the UP mode or in the DOWN mode, where as multimode counters
operates in both UP and DOWN modes.
Modulus counters:
• Modulus counters are defined based on the number of states they
are capable of counting. For example, a MOD-10 counter has 10
states.
• Counters are fundamental components of digital system.
• Digital counters find wide applications like pulse counting, frequency
division, time measurement and control and timing operations.
Asynchronous (Ripple or Serial) Counter
• The asynchronous counter is the simplest in terms of logical
operations, and is therefore the easiest to design.
• In this counter, all the flip flops are not under the control of a single
clock.
• Here, the clock pulse is applied to the first flip flop, i.e., the least
significant bit stage of the counter, and the successive flip flop is
triggered by the output of the previous flip flop and thus the counter
has a cumulative settling time.
• Hence the speed of the operation is limited.
• As the triggers move through the flip flops like a ripple, it is called a
ripple counter.
4-bit Binary Ripple Counter:
• A 4-bit Binary Ripple Counter is constructed using clocked JKFFs.
• The system clock, a square wave, derives flip flop A. The output of A
derives flip flop B, the output of B derives flip flop C, and the output
of C derives flip flop D.
• The overall propagation delay time of the counter is the sum of the
individual delays of flip flops.
• All the J and K inputs are connected to Vcc, which means that each
flip flop toggles on the negative edge of its clock input.
Logic diagram of 4-bit Binary Ripple Counter
Truth Table of 4-bit binary ripple counter
Time diagram of 4-bit binary ripple counter
• Consider initially all flip flops to be in the logical 0 state (i.e.
QA=QB=QC=QD=0). A negative transition (1 to 0) in clock input which
derives flip flop A causes QA to change from logical 0 to 1.
• FF B does not change its state since it also requires negative transition
at its clock input, i.e. it requires its clock input (QA) to change from
logical 1 to logical 0.
• With the arrival to second clock pulse to the FF A, QA goes form 1 to
0. This change of state creates the negative going edge needed to
trigger flip flop B, and thus QB goes from 0 to 1.
• Before the arrival of the 16th clock pulse, all the flip flops are in the
logical state 1. Clock pulse 16 causes QA, QB, QC and QD to go to
logical 0 state in turn.
• Truth table of 4-bit binary ripple counter is shown:
IC -7493 (A 4-bit Binary Ripple counter)
Propagation Delay in Ripple Counter:
Asynchronous Up-Down Counter:
• The UP-DOWN counter is a combination of the up-counter and the down-
counter.
• As the UP-DOWN counter is having capability to counting upwards as well as
downwards, it is also called Multimode counter.
• In an UP – counter, each FF is triggered by the normal output of the preceding FF;
in a DOWN – counter, each FF is triggered by the inverted output of the preceding
FF.
• In both counters, the first FF is triggered by the input pulse.
• A 4-bit UP-DOWN counter whose operation is controlled by the UP and DOWN
control inputs is shown in Figure 1.
Fig. 1 Asynchronous 4-bit UP-DOWN counter
• The counting sequence of UP/DOWN counter in two modes of
counting is shown in Table 1:

Table 1. Truth Table of 4-bit UP-DOWN counter

Decade Counter (BCD Counter)
• A binary coded decimal (BCD) is a serial digital counter that counts
ten digits.
• It resets for every new clock input. As it can go through 10 unique
combinations of output, it is also called as “Decade counter”.
• A BCD counter can count 0000, 0001, 0010, 0011, 0100, 0101, 0110,
0111, 1000, 1001, 1010, 0000 and 0001 and so on.
• A 4 bit binary counter will act as decade counter by skipping any six
outputs out of the 16 (24) outputs.
• There are some available ICs for decade counters which we can
readily use in our circuit, like 74LS90.
• It is an asynchronous decade counter.
Logic Circuit of Decade Counter
• The above figure shows a decade counter constructed with JK flip
flop. The J output and K outputs are connected to logic 1. The clock
input of every flip flop is connected to the output of next flip flop,
except the last one.
• The output of the NAND gate is connected in parallel to the clear
input ‘CLR’ to all the flip flops. This ripple counter can count up to 16
i.e. 24.
Decade Counter Operation
• When the Decade counter is at REST, the count is equal to 0000. This
is first stage of the counter cycle. When we connect a clock signal
input to the counter circuit, then the circuit will count the binary
sequence. The first clock pulse can make the circuit to count up to 9
(1001). The next clock pulse advances to count 10 (1010).
• Then the ports X1 and X3 will be high. As we know that for high
inputs, the NAND gate output will be low. The NAND gate output is
connected to clear input, so it resets all the flip flop stages in decade
counter. This means the pulse after count 9 will again start the count
from count 0.
Truth Table of Decade Counter
• The above table describes the counting operation of Decade counter.
It represents the count of circuit for decimal count of input pulses.
The NAND gate output is zero when the count reaches 10 (1010).
• The count is decoded by the inputs of NAND gate X1 and X3. After
count 10, the logic gate NAND will trigger its output from 1 to 0, and
it resets all flip flops.
• The state diagram of Decade counter is given below
• If we observe the decade counter circuit diagram, there are four
stages in it, in which each stage has single flip flop in it. So it is
capable of counting 16 bits or 16 potential states, in which only 10 are
used. The count starts from 0000 (zero) to 1001 (9) and then the
NAND gate will reset the circuit.
• Multiple counters are connected in series, to count up to any desired
number. The number that a counter circuit can count is called “Mod”
or “Modulus”. If a counter resets itself after counting n bits is called
“Mod- n counter” “Modulo- n counter”, where n is an integer.
• The Mod n counter can calculate from 0 to 2n-1. There are several
types of counters available, like Mod 4 counter, Mod 8 counter, Mod
16 counter and Mod 5 counters etc.
Decade Counter (BCD counter)
Shift Registers:
• We know that one flip-flop can store one-bit of information. In order to
store multiple bits of information, we require multiple flip-flops. The group
of flip-flops, which are used to hold the binary data is known as register.
• If the register is capable of shifting bits either towards right hand side or
towards left hand side is known as shift register.
• An ‘N’ bit shift register contains ‘N’ flip-flops. Following are the four types
of shift registers based on applying inputs and accessing of outputs.
• Serial In − Serial Out shift register
• Serial In − Parallel Out shift register
• Parallel In − Serial Out shift register
• Parallel In − Parallel Out shift register
 Serial In − Serial Out (SISO) Shift Register

• The shift register, which allows serial input and produces serial output
is known as Serial In – Serial Out shift register. The block diagram of
3-bit SISO shift register is shown in the following figure.
• This block diagram consists of three D-flip-flops, which are cascaded. That
means, output of one D-flip-flop is connected as the input of next D-flip-flop.
• All these flip-flops are synchronous with each other since, the same clock signal
is applied to each one.
• In this shift register, we can send the bits serially from the input of left most D-
flip-flop.
• Hence, this input is also called as serial input.
• For every positive edge triggering of clock signal, the data shifts from one stage
to the next.
• So, we can receive the bits serially from the output of right most D-flip-flop.
Hence, this output is also called as serial output.
Example:
• Let us see the working of 3-bit SISO shift register by sending the
binary information “011” from LSB to MSB serially at the input.
Assume, initial status of the D-flip-flops from leftmost to
rightmost is Q2Q1Q0=000.
We can understand the working of 3-bit SISO shift
register from the following table.
No of positive edge of Serial Q2 Q1 Q0
Clock Input

0 - 0 0 0

1 1 1 0 0
LSB
2 1 1 1 0

3 0 0 1 1
MSB LSB
4 - - 0 1

5 - - - 0
MSB
• The initial status of the D-flip-flops in the absence of clock signal is
Q2Q1Q0=000.
• Here, the serial output is coming from Q0 , So, the LSB 1 is received at
3rd positive edge of clock and the MSB 0 is received at 5th positive
edge of clock.
• Therefore, the 3-bit SISO shift register requires five clock pulses in
order to produce the valid output. Similarly, the N-bit SISO shift
register requires 2N-1 clock pulses in order to shift ‘N’ bit
information.
 Parallel In − Serial Out (PISO) Shift Register

• The shift register, which allows parallel input and produces serial
output is known as Parallel In − Serial Out PISO shift register.
The block diagram of 3-bit PISO shift register is shown in the
following figure.
• This circuit consists of three D flip-flops, which are cascaded.
• That means, output of one D flip-flop is connected as the input of
next D flip-flop.
• All these flip-flops are synchronous with each other since, the same
clock signal is applied to each one.
• In this shift register, we can apply the parallel inputs to each D flip-
flop by making Preset Enable to 1.
• For every positive edge triggering of clock signal, the data shifts from
one stage to the next.
• So, we will get the serial output from the right most D flip-flop.
Example:
• Let us see the working of 3-bit PISO shift register by applying
the binary information “011” in parallel through preset
inputs.
• Since the preset inputs are applied before positive edge of
Clock, the initial status of the D flip-flops from leftmost to
rightmost will be Q2Q1Q0=011.
• We can understand the working of 3-bit PISO shift
register from the following table.
No of positive Q2 Q1 Q0
edge of Clock

0 0 1 1
LSB
1 - 0 1

2 - - 0
MSB
• Here, the serial output is coming from Q0. So the LSB 1
received before applying positive edge of clock and the MSB
0 is received at 2nd positive edge of clock.
• Therefore, the 3-bit PISO shift register requires two clock
pulses in order to produce the valid output. Similarly, the N-
bit PISO shift register requires N-1 clock pulses in order to
shift ‘N’ bit information.
 Serial In - Parallel Out Shift Register
• The shift register, which allows serial input and produces parallel
output is known as Serial In – Parallel Out SIPO shift register.
The block diagram of 3-bit SIPO shift register is shown in the
following figure.
• This circuit consists of three D flip-flops, which are cascaded. That
means, output of one D flip-flop is connected as the input of next D
flip-flop. All these flip-flops are synchronous with each other since,
the same clock signal is applied to each one.
• In this shift register, we can send the bits serially from the input of left
most D flip-flop. Hence, this input is also called as serial input. For
every positive edge triggering of clock signal, the data shifts from one
stage to the next. In this case, we can access the outputs of each D
flip-flop in parallel. So, we will get parallel outputs from this shift
register.
Example
• Let us see the working of 3-bit SIPO shift register by sending the
binary information “011” from LSB to MSB serially at the input.
• Assume, initial status of the D flip-flops from leftmost to rightmost is
Q2Q1Q0=000.
• Here Q2 and Q0 are MSB & LSB respectively. We can understand
the working of 3-bit SIPO shift register from the following table.
No of positive Serial Q2 MSB Q1 Q0
edge of Clock Input LSB

0 - 0 0 0

1 1 1 0 0
LSB
2 1 1 1 0

3 0 0 1 1
MSB
• The initial status of the D flip-flops in the absence of clock signal is
Q2Q1Q0=000. The binary information “011” is obtained in parallel at
the outputs of D flip-flops for third positive edge of clock.
• So, the 3-bit SIPO shift register requires three clock pulses in order to
produce the valid output. Similarly, the N-bit SIPO shift
register requires N clock pulses in order to shift ‘N’ bit information.
•