ia eat home dimes ptm Sime sdeShrue Complex than others and reguire more steps +0 Co The clock Speed of a processor determines J instructions it can execute per Second. 0 fast efock speed — @recute wer inStructions more quickly, 4 Dependency _'on previous instructions, 1 | : ' T y a ie Some | instruction ieee ett | Bepend © the vesut of previous instructions. L has to wait fr the resulk of a Previous instruction before it | Pp Ube executed, it will Joke longer Jo Complete. 6 Processor Architecture 2 x Different procersors have different ‘Str ction’ | Sets and may hove differ} performance characteristics For different | instrections, Because of that reas the hime Kanbe differeint to | ~lete the mStruchions, eid: |. Jed i he Lexecutiang He oF the Slowest tinshuction, whieh ul? instruction takes 12 ng bo execute. f eee Toa, agleGucle.rpplem en tolion , each imstrackien! fakes nly ¢ || eck ycle $6 evecute. There for, ‘ | | aabe ; eT Ws) tr |b have a Abia multe tycle tsteacts en mpi entation i = } Processoranove, a bihion cycles per Becond +4 : We —Com Ske cope - Find the duration of « Single Clock cycle,- Glock Cycle. me = \ Clock Speat Subs Hhaking the given Clock speed Hiss Cloek -egele dime f= tit t 2 Gir = 0.8'hs, Duerage cycley per Pinsiruction #CPersemtage—of-baches ¢ cycles ape per branch—wstracttont+-£ + CPercentage af Lead instructions » cycles per Coad instru Cegetessper percendage of shore Inshuction x cucies per Slo Be jet | ~ shake deteCacus Es 4 ot Prerage, rie icleutioe Toe May t fel. 3 Lat Tine Cin Clock Cycles) cc! Ce ! pil ccs \coq | ccs a cad oer 3 hay ilex ADD: RH Riya, | sel sua Ray Ro, Ry Mut Re, Ry, Re | im this Sequence ,-the . Second jnstruction +5 (SuB) is dependend on the Output. of the First “fnstruction (ADD), Since f+ uses the result oF the ADD Operation OS dm an imput, Similary, the third instruction Crmuyis depender = on the oulput OF the Second jngdruction C SUB2, Since. Th uses the yesutk.of the Su8 operation a3 an input. if these M@Stractions are “executed “na Pipeline , the- Pipeline IN have +o Stall when Exec utisng the SGB — and $6 MUL instructions Until the result OF the ADD and. SUB instructions , respectively, are OVallable «This | Can Cause.a delay in the execution oP the Sub oni MUL instructions » whitch Can reduce phe Hoag hour of the processor. } { 1