Layout vs Schematic Check

Ernesto Juárez Campos

Facultad de Ciencias de la Electrónica, BUAP

Puebla, México
Ernesto.juarezc@alumno.buap.mx

Abstract – This document shows a small tutorial of a tool

belonging to the Virtuoso software, called "Calibre", for
verifying the connections between the schematic circuit
and the geometric pattern made in said software.

I. INTRODUCTION
Today, the realization of complex circuits involves
an equally complex problem, which is to verify that the
connections between the geometric pattern and the
schematic circuit match. Fortunately, with the help of
technology, programs can be used to carry out this
Figure 2. Creation of a cellview from a cellview.
verification automatically, such is the case of the Caliber
tool, for which a short tutorial on how to use it will be
described.

II. DEVELOPMENT AND RESULTS

The first step is to make the inverter circuit, using the MOS
transistors and with their default settings, as shown below.

Figure 3. Setting the position of the symbol pins.

The program will launch the tool to edit the symbol. At this
point, we proceed to edit it to our liking. As it is an inverter,
we will make the symbol used in digital electronics. Once
done, we click on "check and save" again to verify that there
are no errors or warnings. We close the symbol window.

Figure 1. Schematic circuit of an inverter.

We click on "check and save" and then we go to Create >

Cellview > From Cellview, we ask you to create a symbol
and configure the position of the pins.

Figure 4. Inverter symbol.

In the schematic circuit window, we go to Launch > Layout shift+f keys we will see the layers that make up the device,
XL. It will open a small window like the one shown in figure as shown in figure 8.
5, we select "create new" and automatic configuration.

Figure 5. Layout XL home window.

Figure 8. NMOS and PMOS transistors placed.

In the next window that will appear, we leave the options set
by the program by default and click "ok". Once the tool First, we must make a connection to the substrate, press the
window is open, we go to the lower left, to the icon called "o" key and a window called "Create Via" will open. In this
“Generate All From Source”. A new window will open in part, we can select the type of road, as well as the number of
which we only have to select to generate the instances and rows and columns. For the NMOS transistor, the definition
select the option “Extract Connectivity after Generation”. via will be M1_PDIFF and with a 2 × 5 matrix. For the
PMOS transistor, the definition via will be M1_NWEL and
with a 2 × 5 matrix.

Figure 6. “Generate All From Source” icon.

Figure 9. “Create via” window.

Now, for the contacts to be part of the PMOS transistor, we

have to create a rectangle that encloses both elements, for
Figure 7. Layout configuration. this we press the "r" key and draw the geometry.

Now, with the “p” key we make the connections as they are
Once this is done, the NMOS and PMOS transistors will presented in the schematic circuit.
automatically be placed in the work area. If we press the
 With this, the geometric pattern is completely conformed, it
only remains to perform the verification between the
schematic circuit and the geometric pattern, we will use the
tool called "Calibre". For this we go to Calibre > Run LVS.
It will show us a window like the one shown below.

Figure 10. Connections made.

For pins A and B, we will place contacts with the “Create

Via” tool. Contact A will have a via definition of M1_POLY
and with a dimension of 2 × 1. For contact B we create a Figure 12. “Calibre” tool window.
path M1_M2 with a dimension of 2 × 1.

We will place labels to identify the connections, we press If we are shown a pop-up window, we simply select
the "l" key. In turn, a window will open, called "Create “Cancel”. Now, we go to the “Rules” section and in the part
Label", in which we will write the labels that we want to called “LVS Rules File” we click on the three points. Here
place. In the “Label Layer / Purpose” section we choose the we go to the CARUL180 folder and select the file called
“Select Layer” option and look for the one called “M1_CAD “LinkToLVS”. In the part called "LVS Run Directory" we
TEXT. Once this is done, we proceed to place the labels so delete what is written and instead we write "./LVS".
that they contact metal 1 (M1).

Figure 13. Configuration of the “Rules” section.

Now, we go to the “Inputs” section and enable the “Export

from layout viewer” option, as shown in figure 14.

Figure 11. Correctly placed labels.

Figure 14. Configuration of the “Inputs” section.

Finally, we click on “Run LVS”, consequently, several
windows will open, later, another window will open with the
Caliber logo, when it finishes loading, it should show us a
message like the one shown in figure 15.

Figure 15. Results of the comparison between the geometric

pattern and the schematic circuit.

III. CONCLUSION
We can conclude that the use of this type of tool greatly
facilitates the connection verification process, and in turn
speeds up the integrated circuit manufacturing process,
making their production and sale cheaper.

On this occasion, there was no problem when carrying out

the tutorial since the ability to use the software has been
gained and the procedures were followed step by step.

IV. REFERENCES
[1] V. R. Gonzales. Clase Diseño Circuitos Analógicos
Integrados. Microsoft Teams. September 8th, 2021. MP4
Format.

[2] V. R. Gonzales. Clase Diseño Circuitos Analógicos

Integrados. Microsoft Teams. September 13th, 2021. MP4
Format.