AN ADAPTIVE NETWORKS AN192 Powerline Network Communications Chip Set 4. Summary ‘Adaptive Networks’ ANI92 Powerline Network Communications Chip Set provides a cable-free aitenative to dedicated wing for distibuted systems communications in both control and monitoring and general data transfer applications. Using innovative spread spectium technology and networking protocols, the Chip Set can reliably network digital devices over electrical powerlines, iminating the high cost and inconvenience of whe installation The AN192 Chip Set uses a hierarchical approach to achieve reliable powerline communications at a 19.2 kbps throughput and a 1344 kbps raw data fale. The Chip Set combines spread spectium modulation, patented adaptive synchronization and equalization, error-control coding, and noise immune token passing protocols, All are optimized for the powerline environment. The AN192 Chip Set (AN192CS) consists of two chips, the PLC192 Powering Physcal Layer Controller and the DLP Data Link Layer and Applications Processor. The PLC192 is a custom, digitally-controlled analog chip that provides the powerline transceiver functions and implements Adoptive Networks’ patented adaptive spread spectrum synchronization, equalization, and modulation/demodulation functions, As the PLC492 is @ custom chip, with highly-integated analog functions, complicated extemal circuitry is not needed, The DIP is a network — communications microcontroller incorporating an enhonced 65C02 core, The DLP manages the PLC192, controls the AN492 Powering Communications Chip Set + Adaptive Networks, Inc. 1995 Features “ 19.2 kbps Data Communications Rate, 134.4 kbps Raw Data Rate * Reliable as Dedicated Wiring, Bit Error Rate < 10” “ Supports Up To 65,634 Nodes per Network “ Coverage Anywhere On One Side of a Transformer Transmission Over AC, DC Powerlines, or Noisy Wire ™ Field-Proven Reliable Technology Looks Like Wire, No Need for the OEM fo Change Existing Network Software Running on Twisted Pair or Other Wired Media Implements ISO Standard 10368 “ RS-232, Synchronous Serial, and Parallel Interfaces * Implements Powerline-Optimized, Noise-Immune Token Passing MAC Layer “ Includes Transparent, Reliable Low Level Link Protocol ™ Rapid Synchronizer and Adaptive Equalizer Enable ‘Spread Spectrum Communications Under the ‘Severe Attenuation and Noise Conditions Found on the Powerline " Integrated Forward Error Correction and Error Detection * Flexible Power Supply Voltage Requirements “ Custom, Highly-Integrated, Digitally-Controlled Analog Transceiver Chip incorporates Programmable Powerline Transceiver Functions ‘and Minimizes Extemal Circuitry * Highly4ntegrated Communications Controller Eliminates Extemal Interface Logic " Extended Temperature Version Available powering network communications protocols, and performs error correction and detection. In adeltion to supporting the powerline communications functions, the DLP has sufficient processing bandwidth to be used as the controler for OEM applications which otherwise would require an external microcontroler. The DLP contains 748 bytes of RAM and 12 kbytes of ROM which can also be used for resident OFM applications fimware, The DIP supports a set of OFM-definable network architecture options and provides standard RS-232, synchronous serial, and parallel interface protocols Poge + Document Number: DSSCS01924004.The highly:integrated Chip Set allows O&Ms to design a powerline communications subsystem into their products on a small section of a printed circuit board with minimal extemal components and flexible power supply options Table of Contents 4. Summary. 2. System Overview 24 PLC192 Powerline Physical Layer Controller 24.4 Receiver. 2.4.2 Tronsmittes... 22D1P Data Link Layer and Applications Processor 2.2.4 65C02 Processor. 2.2.2 interfaces. 2.2.3 Memory. 2.2.4 COUNTS on 2.2.5 Power Control 2.2.6Random Numbér GENEIAIOF jw ronnsonsnn 2.3 Extemal Circuitry. : 2.3.4 Power Transistors. 2.8.2 solation Module. 2.3.3 Clock Circuit 2.3.4Program Memory. 2.3. BEEPROM vu nsunnsninnnnsseunevn nani 2.4Fiimware Options. 2.44 Setlal SHEAM sosmenu nonnon nn 2.42 Command REs9ON6 ws 2.43 General Purpose Command Sal. 2.4.4Fimware Development SyStEM win ssnnn 2.4.5 Fimware Customization sensossnsninsnsnnn 2.5 The Powerline Communications Architecture. 7 RAAARAAARAOOO Haves oooe 2.54 The Powerline Physical LAE. ssnsssnnn7 2.5.2 The Reliable Low Lovel Link Protocol .unn8 2.5.3 The Token Passing Media Access Method for th POWETING.einicsunsnnnmsnnnaninnennen B 2.6 Applications of the AN192 Chip Set 9 8, PLCA92 sr snmnmnnnnrnnnnnnnnnenasennnen ene AO. BA ROCEWEE wns san 3.4.4 Input Selector and Conditioner 414 BA. ZEQUAI2AF wi sannmmninscnnnennnennn nonne 3.1.3 signal Conditioner. 14 34.4Synchronizer 44 BA.EDEMOAUIAOTrssnsnnssenmn ninemsn 3.2 Tronsmitter 414 3.2.4 Modulator. 44 3.2.2 Waveform Synth@sl26tvinuninnnnnen Ad 3.2.3 Automatic Gain Control 414 3.2.40utput Drivers. : 15 3.2.5 ANthJODDEF wrsucnnsnnsienn eS 3.2.6 Reset Circuit 45 8.3 Register DescripfioNS.nnnnmnnuniemnensnene AS 3.3.4 RyData Register 45 3.8.2 IxData Register 45 3.3.3 StONIS REBELS. nsnremneuinnnnen nnn AS 3.3.4 Control Registers. 415 3.3.5 Equalizer Register. 15 ANI92 Powerline Communications Chip Set 3.4PLC492 Electrical Specifications 3.44 Absolute Maximum Ratings 3.42 Power Requirements. 3.48 Logic Levels. 3. Timing Characteristics... iis 3.6PLC192 Mechanical Package Information DLP. 44 65C02 Processcr... A2UART. 424 Transmit FIFO. 42.2Receive FIFO.. i 43 Synchronous Serial Interface. 4.3.4 Serial Peripheral interface (SP. 43,2 MICROWIRE/PLUS™ InterfOC@.... 4.4Parallel Ports, 444 Pott A 442P ort B., 4.43 PortC. 45ROM ABRAM os 47 Counters. 47.4 General Purpose Counters. 47.2 Window Count nnn 47.3Real Time interrupt Counter 48 Power ConttOl BIOCK suns nounsnnnnnn in 48.4 Power Monitor. 48.2 External Reset, 4.8.3 Watchdog TMEF..annsssmsmnsennnrnn 48.4 State of DLP Pins After Reset 49Random Number Generator 440 Clock Circuit 441 DLP Electrical Specifications. 444.4 Absolute Maximum Ratings... 444.2 Powe! REQUIFOMENES. ss 414.3 Logic Levels. 442 Processor Timing Charactetstics ssn 4431/0 Port Timing Characteristics AAADLP Mechanical Package Information, 5 Ordering Information. ..rnssnnnnsssnsnsnie Page 2AN192CS Powerline Communications System Node Block Diagram 2. System Overview The block diagram above illustrates a typical powerline communications subsystem, The sections that follow descrive these functional blocks in more detoll 24 PLC192 Powerline Physical Layer Controller The PLC192 Powerline Physical Layer Controller provides the complete functionality of a powerline transceiver, including patented adaptive soread spectum synchronization, equalization, and modulation/ demodulation functions. As the PLC192 Is highly integrated, exteinai onalog circuitry Is minimized. The PLC192 implements the ISO 10368 powerline spread spectium physical layer for Telable powerline communications, 24.4 Receiver The extremely sensitive receiver clicult in the PLC192 consists of an amplifier, equalizer, rapid synchronizer, ‘and demodulator, The spread spectrum signals can be received In the presence of the frequency- dependent noise and altenuation found on the powerline and can be received from two Independent powerline paths, 24.2 Transmitters Amodulator connects to two independent digitally- controlled amplifiers each with Automatic Gain Control (AGC), The AGC is designed to allow for transmission into constantly changing powerline loads. AN492 Powering Communications Chip Set 22 DLP Data Link Layer and Applications Processor The DLP Date Link Layer and Applications Processor Is a highly-integrated custo microcontroller that provides powerline-oplimized error comection and detection, packetization, and token passing, with serial and parallel interfaces to standard application protocols, 2.24 65C02Processor The DIP integrates a compact 65C02 processor core and includes an enhanced 65C02 instruction set. 2.22 Interfaces RS-282 The — on-chip. Universal. Asynchronous Receiver!Transmitter (UART) _ provides the functionality of a standard 16450 UART with the enhancements of a 2 byte transmit FIFO and a 4 byte receive FIFO Synchronous Serial Communications The Synchronous Serial Interface functions as both a Seticl Peripheral Interface (SPI), as provided. in petipherals sourced by Motorola and Texas, Instuments, and the MICROWIRE/PLUS™ Interface, os, provided in peripherais sourced by National Semiconductor. The Synchronous Serial Port is offered fo provide simple peripheral expansion with commonly used components such as EEPROMs and ND converters. This interface can also be used for multiprocessor communications Poge 3Parallel Input/Output Thiee general purpose parallel ports (Port A, Port B, and Port C) can be configured as standard 1/0 ports, Port A can also be configured as an edge- triggered part for use with external interrupts. Port B can also be configured as an eventlatched input port or used in a RAM emulation mode. 223 Memory The DLP contains 768 bytes of RAM and 12 kbytes of ROM, sufficient to eliminate extemal memory requirements 224 Counters The DLP contains four on-chip counters. Two general Purpose counters provide four modes of operation Including interval timing, pulse generation, event counting, ond pulse width measurement. A 16bit synchronous count-up counter is fee running and resettable from an extemal input pin. A redi-time interrupt counter can be set to interrupt the processor at intervals between 29.7 us and 1,95 seconds 2.28 Power Control The Power Control block provides a Power Monitor, an Extemal Reset circuit, and a Watchdog Timer. Tne Power Monitor monitors the level of V., for an undervoltage condition, if an_undervoltage condition occurs, the processor is interrupted and the POWERFAIL signal is asserted LOW. The Power Monitor block also handles the power-up initilization process which occurs when power is frst applied to the DLP, after a low voltage condition, or when the DLP Is reset vic the External Reset circuit. The Watchdog Timer circuit detects and resets a malfunctioning processor. 2.26 Random Number Generator A Random Number Generator is provided and is used in dynamic access and address assignment protocols, particularly for large networks. 23 = External Circuitry In addition to the Chip Set, minimal extemal circuitry Is required for a complete design 2.34 Power Transistors Each transmitter amplifier block requires an extemal Pair of complementary power transistors to provide current amplification before the signal Is coupled onto the powerline, ANI92 Powerline Communications Chip Set 2.3.2 Isolation Module A coupling circuit is required to simultaneously Isolate powerine communications circuits from the higher voltage AC powerline while coupling the spread spectrum signals onto the powerline, 2.3.3 Clock Ciroult An external crystal is used with an amplifier inside the DLP to create the 8.6016 MHz system clock 2.3.4 Program Memory Some applications will require an external program memory, such as an EPROM or flash memory, which contains powerline network and application firmware, Adaptive Networks has a library of standard fimware versions which control the powerline network communications protocol. in Addition, it is possible to create customized firmware versions which are application-specific. An external EPROM or flash memory is not necessary in applications where the required fimware is included in the intemal DLP ROM. 2.3.6 EEPROM The DLP has @ built-in synchronous serial port which may be connected to an extemal EEPROM for stoing ond loading syslem parameters, system configuration data, or application information. The EEPROM is optional and is not required for basic powerline communications applications, Page 42.4 Firmware Options Adoptive Networks has on extensive library of standard and customized firmware versions for different network configurations, The most common standard configurations are «Serial Stream — for RS-232 steam-based direct cable replacement + Command Response — for simple Master/Siave command-response-based networks definable networks When selecting a fiimware version, the user should carefully consider network requirements and the trade-off between smplicity and flexibly. For instance, the General Purpose Command Sat offers complete flexbility but introduces network driver oveihead (customer-written software to implement the network driver), An altemative is to use the Command Response or Serial Steam firmware, which may restiict the flexibility, but it will smplify or even eliminate the network diver overhead, allowing the Chip Set to handle the networking functions, «General Purpose Command Set — for user MULTIPLE SERIAL LINKS MULTIPLE SLAVES: OF Oo @——® Dedloated Polnt-to-Polnt Links GENERAL PURPOSE COMMAND SET Network Architectures of the AN192CS AN492 Powering Communications Chip Set Poge §2.44 Setial Stream A distributed system often consists of dedicated RS- 282 serial connections between devices, Such configurations of muitiple Serial Steam connections are best handled transparently to the network user 50 that each attached device “thinks” its attached to an RS-282 serial cable, Additionally, several devices may need to contend over an RS-232 setial connection for a single resource such as a printer or @ modem and, once connected, have exclusive Use of the resource until the connection Is idle for a selectable time-out period, For devices sharing one resource, this is called a multiple PortContender architecture, The Sellal Stream fmware version for the Chip Set Is designed to accommodate single or multiple point- to-point networks (as in the diagram labeled "Multiple Serial Links"). A skeam of data sent to one Chip Set node Is delivered by the second Chip Set node. This fimwore version is most useful for integration of the Chip Set with existing equipment. It provides transparency to existing protocols and allows a host not capable of supporting a special network software driver, such as an industrial programmable logic controller, to be part of a powerline network, The Setial Steam fimware is also extremely useful for customer evaluation and demonstration of Adaptive Networks technology, It can be easly used In real customer environments to replace RS- 232 cables, for instance, in commercial or industrial applications such as PC-lo-PC communications or other RS-282 applications requiring a single, fixed link: 2.42 Command Response Many data acquisition and control systems consist of sensors, scanners, and actuators controlled by a single intelligent node. In such single-master, multiple-save networks, @ simple software diiver usually resides on the host machine attached to the Master node which communicates to multiple Slave nodes, one at a time, in a predetemined sequence, The monitoing and control devices attached to Save nodes require a transparent serial interface back to the host machine, which the Command Response fiimweare provides. Ina Command Response network, there is a single, inteligent Master device responsible for the control of a network of Slave devices. All communications originate from the Master, and the Slaves do not originate communications, as they only respond to a request from the Master. This frmware relieves the Master host ftom the powerline networking ANI92 Powerline Communications Chip Set overhead by implementing the Command Response communications control in the firmware, rather than being controlled by the host at the application level. If necessary, this firmware version con be adapted for custom packet formats, This version is most useful for systems sng a Master/Save architecture where transparency at the Stave devices and offloading the networking overhead from the host are both required features 2.43 General Purpose Command Set With the General Purpose Command Set fimware, the host retains complete flexbilily for medium access token passing —control_ methods, configuration, and operation of the network. The host to Chip Set interface is completely command- based requiring the host to support the network dtiver for the Chip Sel. The additional flexibility gained allows the host to implement the access protocol of its choice: master/save poling, peei-to- peer token passing, or a hybrid of both, (The same Nolse-immune token passing on the powerline is Used to implement both poling and token passing, 8 descilbed in Section 25.3) This fimware is useful for systems where the system needs to retain close Control of network operation In its most general configuration, the network can consist of a token-passing loop of Master nodes that ‘each control associated groups of slave nodes, The host at each node must support a diver running the General Purpose Command Set over the link-level Interface presented by each Chip Set. The flexblity of the command set gives control of the medium access functions to the host without creating a communications bottleneck. Furthermore, the network can then be dynamically configured by the host(s) to handle changing loads and use, 2.44 Fimware Development System Adaptive Networks offers a complete Fimware Development System which allows the designer to use the DLP to run the application as well handle the powerline communications functions The system includes an object lisrary which incorporates the standard powerine-optimized data link Protocols. enabling the designer to wite a completely customized application and include the powerline networking fimware, 2.45 Firmware Customization In some instances, it may be more efficient for Adaptive Networks to wiite custom fimware for a particular application. If a customized fimware version would provide a more effective solution, please contact a sales engineer for more details. Pages2.5 The Powerline Communications Architecture ‘Adoptive Networks! powerline communications technology is based upon a hierarchical design: Each level of the design is optimized specifically to overcome the inhospilable characteristics of the powerline environment. Both substantial noise and frequency-dependent signal attenuation are found on almost every powerline. Unlike dedicated wiring, without well designed error control coding, bit errors will occur at unacceptably high rates, Actual enor tes data throughput Is olways a fraction of the raw data rate. Adoptive Networks soread spectrum wideband modulation, fast synchronization, adaptive equalization, error control coding, and network protocols, provide immunity from powerline Gttenuation and noise. With a raw rate of 1344 Kops, the ANI92CS con provide a 19.2 kops throughput at less than a 10° error rate. equivalent to that of dedicated wire The Chip Set implements the Physical and Data Link layers of the ISO Open Systems Interconnection (OS) Reference Model. Often, the OS! Reference Model is implemented as an abbreviated three-layer communications architecture which is easly implemented using the Chip Set. Logical Link Control Sublayer tink. Communications Layer Protocol! Media Access Control Sublayer Reliable Low Level Link Protocol Adoptive Networks Three Layer Powerline Communications Architecture 2.51 The Powerline Physical Layer In general, a spread spectrum system will exhibit improved noise Immunity over narrowband systems on the powerline. However, using the traditional spread spectrum approaches (direct sequence, flequency hopping, chitp) does not solve the difficulty of signal synchronization in the presence of constantly-changing noise and —_frequency- dependent attenuation. AN492 Powering Communications Chip Set Adoptive Networks’ approach is based upon a unique physical layer spread spectrum technology that provides very rapid synchronization. Rapid synchronization isan important component of a fast, Practical, and reliable powerline communications system and Is achieved in an adaptive detection process As part of the Adaptive Networks protocol, data is transmitted in short frames The PLC192 quickly detects the stait of a frame followed by a fast verification process which eliminates the possiblity of a folse detection. The high raw data Poge 7rate of the physical layer is sufficient to implement protocol messages in single frames, Another important component of a reliable and robust spread spectrum powerline communications system is a method of adaptive equalization of the received signal, The physical layer provides such a method, which maximizes the received signal even In the presence of frequency-dependent noise and attenuation, 2.5.2 The Reliable Low Level Link Protocol Several key features of a data link layer are required for reliable operation of lage, mull-node networks on the powerline are: * decomposition of larger packets to powerline frames to create reliable communications * rigorous error correction and detection * effective adaptive equalization * reliable transfer of control Only @ certain amount of contiguous information can be sent before it is almost a certainty that a transmission will be corupted. This suggests a requirement for transmissions of short frames on the powerline, To further ensure the integrity of any frame of data, it is necessary to use both error cotrecting and detecting codes-forward error correction to minimize the numberof retransmissions, and error detection to know If there is aneed for a retransmission on a fame basis Each frame should be acknowledged by the receiver before the transmission proceeds to the next frame. To implement this low-level link protocol, the higher level packet is broken up into such short frames, Another benefit of the low-level link protocol is the effectiveness of adaptive equalization. Powerline conditions can change on the order of a few miliseconds, and the receiver must be able to ‘adapt to these changing conditions Using a low level link protocol built upon short frames, the receiver can adapt on a frame basis and, because acknowledgments are required, no information is lost Using forward error conection (FEC) and automatic repeat request (ARQ) developed specifically for the Powerline environment, the AN192CS transfers data with an effective throughput of 19.2 kbps at an error rate of 10°, using a raw data rate of 1344 kops. This provides ‘both the required reliability and bandwidth, ANI92 Powerline Communications Chip Set To provide reliable multraccess network communications, Adaptive Networks developed a noise-immune token passing protocol, For example, transfer of the token between nodes is done via a three-way handshake ensuring a transfer of control without loss of the token. 2.5.3 The Token Passing Media Access Method for the Powerline Different media access aigorithms have been demonstrated on dedicated wire. The algorithms aie generally based on either a cartier sense technique such as CSMA/CD or token passing However, resuits for other media are not transferable to the powerline, Token passing solves three problems that the powerline medium presents for a carrier sense technique: 4..On the powerline, there Is insufficient communications reliaiolity to distinguish between noise and signal, This makes cartier sense especially difficult. Nodes wil back off when there are no contending devices transmitting on the powerline, Token passing does not require colision detection by the nature of is structure. There is only one token holder at any point in time. A reliable three-way handshake is used to transfer the token between nodes, This ensures: ‘an orderly transfer of control without loss of the token, 2. Because the powerline characteristics are different for each node, a node wil not necessarily hear every transmission on the powerline, In cartier sense, a node may thus Incorrectly determine that the channel is quiet and start transmitting in the middle of nother transmission, Again, because powerline conditions are not symmetrical the other nodes involved in the ongoing transmission may hear the interfering node's transmission ond abort reception and/or transmission. In token passing schemes, nodes cannot transmit unless they hold the token. Therefore there is no possibilily of nodes starting to transmit in the midst of another node's transmission In CSMA/CD, each listening node hears a summation of the transmissions of each fronsmittng node, where the transmission of each transmitting node is transformed by the charactetisics of the particular powelline electical network seen between its position Pages‘and the listening node, Thus each listening node will in general hear a resultant transmission that Is not a smple sum but Is a summation with cancelation and distortion due to the different transformations of each node's transmission. Collsion detection under these conditions is difficult In token passing, these types of communication node, which acts problems are easily resolved by the token holding as an arbitrator of any ambiguities. There are additional benefits to using token passing that cannot be obtained with cartier sense: 4 2 3, Token passing allows for deterministic access fo the network under heavy loads. In fact, ‘one can predict the maximum time requiied to access the network ftom the maximum number of nodes in the logical ring. Silay ‘one can predict the maximum time requied for a response fo an interrogation Each node on the logical ring, and, when ‘applicable, each subnetwork, receives a fair share of the network bandwidth, The failure of a node on the logical ring can be easly detected without additional overhead. AN492 Powering Communications Chip Set 4 The architecture allows at rary mixes of inteligent and dumb nodes. A token pasting logical ting can be formed only of the intelligent nodes, with the dumb nodes granted access fo the network by the nodes on the logical ting, This provides for a smple and straightforward implementation of request-esponse interaction & The transmitting node can determine if the destination node is on the network, without resorting to detection at a higher layer in the protocol stack, 2.6 Applications of the AN192 Chip Set Adaptive Networks ANI92 powerline communications technology hos been proven in the fled In a broad group of applications worldwide. It Is the high data rate standard for communications aboard Teftigerated container ships as selected by the Intemnational Organization for Standardization (ISO), Additionally, it complies with Intemational standards such os IEC C57 Distioution Automation Using Distribution Line Cartier Systems, The AN192 technology has similariy found acceptance in applications sich as point-of-sale (POS) networks, vending machine monitoring, utlity tolemeteting, secutlt automated storage and retrieval, ‘access contiol, public transit vehicles, residential LANs, and factory automation. Poge °PLC192 Powerline Physical Layer Controller Features + Highly-Integrated Single-Chip Powerline Transceiver ‘+ Implements the ISO 10368 Powerline Spread Spectrum Physical Layer + Independently-Controllable Transmit Paths + Independently-Controllable Receive Paths ‘+ Stats Monitoring and Control of Powerline Interface + Automatic Gain Control Allows Transmission Into Low-impedance Powerline Loads + Equalizer Allows for Reception Under Severe Frequency-Dependent Atfenuation and Noise + Rapid Synchronizer Allows for Short Powerline Frames + 4Byte Transmit and Receive FIFO + On-Chip Anti-Jabber Protection g PLC192 Powerline Physical Layer Controller System Architecture Block Diagram ANI92 Powerline Communications Chip Set Page 10& , # B 8 > tee Szcewkge be 8 3 Ae) (5) [4] [8] [2] [41 [44] [4s] [42 [41] [ao o7 [7 eo [30 AGND De [8 | [ge REF2 0s [9 ‘ar REFt D4 [10 [Be PATH2 a [4] [a3 PATH ol PLC 192 Biron 0: fs aa-ph pice ‘wrest Do [14 ‘a2 SENSECAL CLK (16) ‘31] SENSE2 INT [16 ‘30 SENSE D@ND [17 ‘2a terB2 {el |9] [20] 2a] [22] [23] [2a] [2s] [26] [27] 20] = 2 Zz a < 5 2 Bi ie 1G eae IL IneIH SLE <5 @§ OOH cH oH eoHiHie: gF 5 & PLC192Pin Diagram AN492 Powering Communications Chip Set Poge 14PLC192 Pin Descriptions PLC192 Power Pins Power | Foslive Anciog Supply Power | Negative Anciog Supply Fower | Fostve Digital SuppIy Power | Anciog Ground Power | Digital Ground! PLC192 Digital Pins eg ‘ADA [input [Regiler Adcress Selection. Address Ines select the memory-mapped Data, Control, Status. oF Equatizer register fh any] Read or Write cycle DODT [TO Bata Bus Fight data ines or Bidvectional data exchange wii the memory-mapped register ContenTs RD Input |Reod Pubs. RD & owerled LOW dung © read cycle, Duing the Read cycle, data appears on the Data Bus| [corresponding fo the contents of he register selected by the Register Adchess ines We [input [Wie Puke, Wits aseried LOW during a Wille cycle, Duihg the Wille cycle, dala which appears on the Dafa Bus wiitten into the register selected by the Register Adctess ines S| input |Ghip Select, Cols axeried LOW To enable a Read or Wie cycle, CSs\Guld be NelGRIGA fo Gaselact he PLOTGD when reading rom of witing fo another device TY __|Ouip [Ready ROV dives the OV pul of he DIP ands axerled LOW dumg a Read cycle To provde one wal stale ut THT —_]Oup-[intenupt, INTs oxsarted LOW by Ihe PLCTO2 when an anor condition cocure When Ine PLCTO2 kin Receive mode, NTE ut |oiso asserted LOW if the RxData FFO contains one ot more bytes. When the PLC192is in Transmit Mode, INTis assertec LOW when the Data FIFO isempty. IK [input [Glock 8 G1 WiAz Clock Tw [Outp [TiensmitReceive. T/T Indicates the Transmit or Receive mode of the PLC192, HIGH Indicates the PLC192 isin Transmit mode, LOW hdicates the PLCt92 isin Recelve mode, TES [Trp [Reser RESis asserted LOW To resol he PLOT92, ReSshould be held HIGH dung normal operation, TAR [Ouip [for Bis aserled LOW by the PLOTO2 To inalcale @ Wanumilier eror condllion. HGH Indicates nomal operalion. Ey ut |may be used fo chive cn exteinal LED fo indicate @ hansmitler hardware erot. The pin supptes enough current fo [ckive on LED without an sitemal gate, This pin can alo be used os a wied-OR output, ANI92 Powerline Communications Chip Set Page 12PLC192 Analog Pins er PATH input JReceive Path 4. PATH! isthe differential receiverinpul of Path 4 with respect fo REF. PAZ | input {Golve Paih 2. PATH2 ik Ine difereniial eoeiver pul of Paih 2 wilh respect To REFZ Re [input "ava Path 4 Reference, REFI le the reverence far he Giierentiay coupled Racalve Paih 4 pul mea npur {Geive Path 2 Reference, REFZIs he reference for the diflerenfaly coupled Reoalve Path 2hput DUTA[Ouip [Tranamit Ou Path 1 10 NPN, OUTIA the fonemi Path 1 Gmpilier oulpul connected fo the base of an eemal NPN Ut power transetor OUT JOcip |irananit Out Path 4 fo PNP. OUTAB ke Ihe rananil Palh 1 ampllisr oulpul connected fo the bave of Gn extemal PNP ut power transtor DUT [Outp [ronan Out Path 2 fo NPN, OUTZA ke Ihe Wonemi Path 2 Gmpiiar oulpul Connecied lo the base of an extemal NPN ut power transtor ‘OUT |Ouip |iransnit Out Path 2 To PNP. OUTES isthe lransnil Palh 2 ompliar culpul connected fo the base of an extemal PNP ut power transtor THFBt__[Tnpu [Tronemil Feedback Pain‘. UFB1 isthe feedback palh from the oulpul of fie exlemal power Hansklows fo the Infernal PLC192 aitterential omaiifer THB2_[Tnpul |Tranemil Feedback Palh 2 FB2 is he feedback palh from the oulpul of ihe exlemnal powe' ansklos fo the Infernal PLA92 aitterential omaiifer ‘SENGET [Input Sense Tonal Path #. SENSE f fe vallage sens Input fo the Aulomalc Gan Contol (AGG) for the Pah # oulpull tive. “SENSED [Input [Sense Tonal Path 2 SENGE2 f he vallage sens Input fo the Aulomalo Gan Contiol (AGG) for the Pam 2 ouipul tive. THALTOUT JOuIp |Eviamal Filer Out! BFLTOUT k The oulput of fhe Waveform Syniheszer Tor connection to the Input of an extemal Ut Hhronsmilter spectrum shoping fiter. An extemal fer is nat requied, but ll may be useful for applications requting, fo lexompis. requency divsion multiplexing, of additional out-of-band transmit signal attenuation TGELIN [INBUT [Exiemol Fifer in. GILT is he npul To the final slagas of flening ond ampliicalion of fhe Wansmified signal Nomoly. when an extemal ster is not required. TEILTIN Is connected dtectly to THFILTOUT. TEST _[Oulp [Receive Tes. TESTIs used only h production Tesi of he reoehve Sages ut FLICAL | 7 |Fifer Galbration, An exteindl redsior connected lo FLIGAL k used fo ereale an reference current To Callrale he on: chie Store RICAL [TO |anirvabber Calbralion. & copaciior connected fo AICAL determines the maximum alowable coninuous lranamil ime. TENSECAT [InpuT [auTomalle Gan Control (AGC) Sense Caltralion, Te threshold vallage af which the AGG begins lo operale sel intematy. This threshold may be chonged by applying ¢ voltage to SENSECAL ‘OUTCAL input [Trcnsnit Oul Galiralion, The vollage Grop across on exlemal diode ond resslor connected belween OUIGAL ond JAGND is used as a reference fo set the internal bias voltage between OUTTA and OUTIB and between OUT2A and| Jourzs, The exteinal diode should be thermally coupled to the power transstors OUTSET [ABUT |Guiput Select. The voltage on OUTEEL b usediTo sol @ mullipier of the bios vollage est By OUIGAL, When OUTEEL lef Hocting. there isc voltage of two diode crops between the transmitter output pins (QUT A. QUTB and OUTZA, OUTZ)| or use with regular power transistors. When OUTSEL is fed fo V.. there is @ voltage of four diode drops between the| output pis fr use, for example, with Darlington transistors: AN492 Powering Communications Chip Set Poge #33, PLC192 The PLC192 Powerine Physical Layer Controller is a digitally-controlled analog circuit which implements the powerline transceiver functions using both analog and digital signal processing to provide patented adaptive —spread-——spectrum synchronization, equalization and modulation/demodulation functions, The chip can transmit and receive on two independent powerline paths The PLC192 is controlled by wiiling and reading the on-chip registers. The registers appear as consecutive memory locations allowing the PLC192 fo function as a memory-mapped peripheral on an B-bit microprocessor bus, The physical layer signaling follows ISO 10368. The PLC192 operates in either transmit (1x) or receive (Rx) mode. In Tx mode, the PLC192 will transmit bytes loaded into the TsData register. In Rx mode, the PLC192 will fist detect a frame from te powerline by recognizing its synchronization preamble, and then the data from the frame is loaded into the RxDate register. 34 Receiver The PLC192 receiver is a highly senstive signal processor containing on amplifier, equalizer, rapid synchronizer, and demodulator. The process of receiving is controlled by fimware running on the DLP. 34.4 Input Selector and Conditioner The Input Selector allows for dynamic selection of the receive path which can be controlled for each frame. The signal Is then differentially processed through low-pass and high-pass filters ond a differential amplifies 34.2 Equalizer An equalizer is required to optimize communications in the presence of the frequency-dependent attenuation and noise on the poweling, Fimware running on the DLP dynamically controls the equalizer by wilting to the Equalizer register Changes to the Equalizer setting can occur as frequently as each frame. 34.8 Signal Conditioner The signal conditioner amplifies the equalized signal without phase distottion, followed by analog to digital conversion. ANI92 Powerline Network Communications Chip Set Poge14 3.4.4 Synchronizer The synchronizer is @ digital fnite state machine that detects a synchronization preamble In a. setlal adaptive process over consecutive 1.86 ys intervals, An initial signal detection is followed by successive transitions fo states of greater or lesser certainty, eliminating the possiblity of a false detection 3.4.8 Demodulator Following the detection of the synchronization Preamble, the received signal is digitally demodulated and the received data bits are output to the Receive Data register. 3.2. Transmitter The PLC192 transmitter creates the spread spectrum waveform which is injected onto the powerline, The transmitter gain con be controlled automatically Using the on-chip Automatic Gain Control (AGC), or it can be controlled by writing specific attenuation values to the Control2 register. The process of transmitting Is controlled by fimware running on the DLP. 3.24 Modulator The digital modulator generates the digital pattem for each data bit output from the TOata register. 3.22 Waveform Synthesizer The analog signal waveform is synthesized for each data bit from the digital pattem of the modulator, creating a transmitted spectrum with @ nul-to-null bandwidth of 134.4 to 403.2 kHz and minimizing the out-of-band spectrum. The output of the waveform synthesizer Is fed to TxFILTOUT and may be used to drive an extemal filter if additional out-of-band filtering is necessary for certain markets or applications. The extemal filter output is then fed back Into the waveform synthesizer via TEILTIN where it is intemally low-pass fitered and divided Into the two separate transmitter paths, If an external fiter Is not required, then TELTOUT and T it Ja * hoe” ] UN MS :inch mn} PLC192 Powerline Physical Layer Controller Package Information, 44? in Plastic Leaded Chip Cartier (PLCC) AN102 Powerline Network Communications Chip Set Poge zaDLP Data Link Layer and Applications Processor Features ‘+ Enhanced 66CQ2 Instruction Set with Bit Manipulation /Branch Instructions * 232ns Minimum Instruction Execution Time at 16450 Compatible UART with FIFO ‘SPland MICROWIRE/PLUS™ Compatible ‘Synchronous Serial Interface 86016 MHz Operation + Paralle! Data 1/0 interface + Implements Complete Powerline + Two 16 Bit Programmable Counter/Timers ‘Communications Application Without Extemal + —-Real Time Counter Glue Logic + 16Bit Window Counter + 768 bytes RAM + Power Monitor + I2kbytes ROM + Watchdog Timer + 16Bit Address/8 Bit Data Extemal Bus + Random Number Generator + 24 Pins for User Programmable I/O Ports + Integrated Chip Select Logic for Memory-Mapped Including 8 Pins for Extemal Interrupts Peripherals vet 06N0Kt) ous exT8EL pice cnr uART SPUMCROWIRE ra vate! eet >a pg aaa c0-e7 ann92 PRUE ROHR HDK.LaKeS RSL ARRUERigns Processor System Architecture Block Diagram Page 258 pSeuzvzvzzze SEREERSSC See RaseetSs a (BSSLSFLBRSSSISREBRS EXTBUSL 18 © reo diss 78) PC3 XTLIC 3 acs XTLOL 4 Eesha DGNDL 5 Fen Pes MEMS 6 (ares DISRESETL 7 7D PO CNTBL 8 7p 0eN CNTAL 9 move CLKDIVE 10 le CLK 11 605 CaF mRCIG 68) WCNTZ WAL 13 sen Wor Si DLP 28 DGNDL 15 sen a pete 100-Pin PQFP 645 SCLK DIL17 arse Del 18 mac D3L19 se vec 20 moe DGND E21 eswocs D4 22 58-1 SOUT D523 BE sot Del 24 56. ATS D7l25 551 0TS aes 547 DIR AIL 27 aoe vec 28 ae DGNDL 29 ean “Magee geuggsasataasass ~~ ODOUUOUUOOCUUUOUUOUUOUO BEASZRASSSZVEzUAS RV BRB SSE R ESA B SSSR SES 2 DLP Pin Diagram, N12 Powetline Network Communications Chip Set Page 26DLP Pin Descriptions ry Type Deserinton Yeo 10 [Power | Postve Digital Supply. (SV) DEN Tt [Power | Digital Ground To | Out | Races Bus, AGGIES Ines for exieinal memany Gnd memoIymappeI TO ut BOOT 3 W0_[ Bata bos Data inet Tor biarectonal dala exchange wiht evlemal memory ond memanmapped 0. © T [Guts | Read Pure We aseried LOW by ha DIP dung a Read ovo, ut We 1 _[Oulp_| Wife Pubs. Wie asrerled LOW by fhe DIP dung a Wie vee ut SNE T | Sule _| Smnchronze. SINC i awseried HIGH by The DIP Tor he ful Glock cycle whan he DIP isperforming on ut | opcode fete. wy T_[ineot Ready. ROY halls the DIP af The end of a lock cycle ond f used for shaleslepana ondlor synchronizng the DLP with a Sow paiipharal device. With intsinal pullup, o 7 | Gut | Chip Select Cos osseted LOw by he DIP for a Read or Wife GyGis To The PLCTGd for Gadrawses OBaD tut | to 024F Hex. When the DLP reads or wiles to addratees outslde fis range, CSi¢ hala high Ere 7 | utp | External Adress SeiecT EXEL onerled LOW by the DIP when on @xieinal Gave fs GOGres=sd, with ut_| the exception of the PLC192 addresses 0340 fo O84 Hex. THENCE T [Gul | Memory Chip Selsct VENCS Ie cerafed LOW by The DIP when exfomnal memory Between GOOD To FFD ut | Hexis dderessed If EXTBUS is HIGH. then MENICS Is asserted LOW when exisinal memory between 8000 fo FFFF Hers addressed TBS 1 [inet [External bus When EXIBUS & awerled WIGH the upper a bylas of Ihe inlemal ROM vectors are {dsabled lo allow for extemaly-serviced inferupls. With nteinal pul down. x T_[inout | Grstal in XIU the Fput fo the mvering Clock oscBalor amplifier and Infemal clock generator Alternatively, XI con seive os the Input for an external clock source. For noimal operation the clock frequency issat of 8.6016 MHZ mo 7 [Cat] Ciyatar Oat, HILO f the output fom ihe invering clock orator omplter For noma operation The ut | clock tequency ie sat ot 86016 Mz ox T_[ Sule | Clock CIT fhe output oF The infernal clock generator for connection To The PICTOD ond Ofer ut_| extemal peripherals Fornoimal operation the frequency is 6.601 6MHE CDE [1 | Supa | Geek Duided by 8 CIKDIVE h provided os a avidedtby-eoht system lock for exlemnal perpherai + | Fornormal operation the flequency is 1.0752 MMe Tia 7 [input | Non Mashable Inferuph, Wih infemal pul up TERT T [input | Reset REST s owerted LOW Tor Two clock cycles To reset Pe DIP. REST should be held HGH Gung oimal operation. POWERFAL | 1 | Culp | Power Falure POWEWPAL & aserled [OW by Ine DIP when V._goes below 42 v (Iypical) POWENFAL ut | may be used to ctive an LED without an external gate. This pin con also be used as a wired-OR ‘output. wit intemal pull up. DIREET | 1 | Trout | Deable Reset Slafe Machine, Awering DERESET HIGH wil dicbls the Ress] Slate Machne. Wik intemal pul down. ow 7 input Serial n, UART sonal data input wih infernal pul up, TOT T | Oulp | SeralOut UART coral data output ul RE T [Gul [ Request To Send: UaRThandanaking Ine: ut oS T [input Gear To Send UART hanaihaning Ihe wilh nlernGi put up: AN#92 Powerline Network Communications Chip Set Page 27DR 1] Oulp | Data Termial Ready. UARThandihaking ne, ut DR 7 [Input | Bata Set Ready. UART handshaking Ine wih nfemal pulup. DoD 7 [pat | Data Gamer DeTech UART satus inpaT with infamnal pul up, ® 7 [input] Ring indicator UART satus put with intemal pulup: TAS 7 | WO | Masterin Save Oul, Smchronous senor interface ine with Infernal Bul up: WOH 7 [10] Mailer Out Slave i. Synchronous serial RTerface Ine wilh infemnol pulup- Sauk 1 [16] Synchronous Sefal Glock Glock Ter smnchronous saial nlerface. SCIK Ts an Inpul hn dave mode and fan ouput in master mode. With tern pul up. S 1 | 10 | Save Sect. Synchronous sercl dave select Input Ine for synchronous sell interface: Scan Gko be Used 05 6 general purpose output. With intemal pul up, WONT 7 [rat] Window Counter Taro WONTE used To raial the Window Counter To tere. The Window Counter Te resei on the rsng edge of the WCNTTZ lng. With infernal pull up. PROPAT | —& | 10 | Pont Port Aisa general purpare /O pot wi infemai pulups The Ines! Parl Acan ako be used as indivcually edge-higgered intenupt Ines Each tne of Pott A con be configuied asan interupt fo detect either or both input edges. in adlfion fo the standard /O functions, PAO con be configured fo function as the latch contol fot Por! B. PAD and PAT can also be used in Port B RAM emulation mode. PEDPET 3 | 10 [Farle Parle a general purpose 10 port wih nfainal pul ups POE aso offers alaich mode wi the latch functions controled by PAD and a RAM emulation mode controlled by PAD and PAK PooPT | 8 | 10 | Pon Por Giza general purpose /O por wih intemal puUpe oe 1 [16] Counter & CNTA fo TOI synchronous countdown counter which can be used for inferwal tning, pulse generation, event counting. or pulse low measurement. The count value may be read at any fine, With intemal pullup, ONE 7} 10 | Counter CNB 6 16 Bit amohronous Count Gown counter which Gan Be used Tor nfewel Hing, pulse generation, event counting, or pulse low measutement, The count volue may be ead at any fima. Witt intemal pullup, TorarPins | 100 N12 Powetline Network Communications Chip Set Page 284 DLP The DLP Date Link Layer and Applications Processor Is a custom network processor and microcontroller that provides powerline-optimized error correction/detection, packetization, and token passing, with sericl and parallel interfaces to standard application protocols. 44 65C02 Processor The 65C02 processor core is a custom CMOS block. It includes the enhanced 65C02 instruction set which Consists of the standard set with the addition of the bit manipulation and branch instructions 42 UART ‘4.16450 compatible UART with transmit and recelve FIFOs is provided as the main communications port from the DLP to an intelligent controller, The UART will emulate the standard 16450 functionality with the enhancement of a 2 byte transmit FIFO and a 4 byte receive FIFO. 424 Transmit FIFO 42 byte transmit FIFO has replaced the transmitter holding register. 42.2 Receive FIFO A Abyte receive FIFO can be enabled or disobled through the FIFO Control Register. When disabled, the UART will function like the 16450 with a receiver shift register and a receiver holding register. When, enabled, received bytes will be transferred through, the Receiver Holding Register into the FIFO. Any errors (framing, parity, or break) will be sent to the FIFO with the current byte, and will become active when that byte is at the top of the FIFO. 43 Synchronous Serial Interface The Synchronous Setial Interface can be configured to be compatible with the Setial Peripheral interface ($1), 08 provided in peripherals sourced by Motorola and Texas Instruments, or withthe MICROWIREIPLUS™ Interface, 3 provided in peripherals sourced by National Semiconductor, A 2 byte transmit FIFO and a 4 byle receive FIFO are Included to reduce processor overhead and provide 46 bit compatiblity 43.1 Serial Peripheral interface (SPI) The Serial Peripheral Interface is a Master-Siave synchronous serial interface requiring @ minimum of 4 wires. The 4 sgnals are Serial Clock (SCLK), Master Input/Siave Oulput (MISO), Master Qutput/Siave Input (MOS), and Slave Select ($8). MISO and MOS! are switchable /O functions Additionally, Master §PI devices must drive the select lines for each Slave attached to the interface. Any pins of the three general purpose I/O ports can be configured to provide these additional select lines. The following diagrams show the functional waveforms for the SPI interface transfer operations. Ne tt ray MSE of Carer toa $1 interface Functional Waveforms (Phase=0) AN#92 Powerline Network Communications Chip Set Page 2SK CYCLE 1 * Net dened bt reenay LSB of peasy Yaveitod aa SPI Interface Functional Waveforms (Phaso=1) 43.2 MICROWIRE/PLUS” Interface Like the SPI, the MICROWIRE/PLUS™ Interface is a Master-Slave synchronous setial interface requiring a minimum of 4 wires. The 4 sgnals are Serial Clock (SCLK), Master Inpul/Slave Output (MISO), Master Output/Slave Input (MOS), and Save Select (58). Unlike the SPI, MOS! is an outputonly function and MISO. is an input-only funtion, The following diagrams show the functional waveforms for the. MICROWIRE/PLUS™ Interface transfer operations MICROWIRE/PLUS" Interface Functional Waveforms (Alte mate SCLK Mode) AN192 Powerline Network Communications Chip Set Poge 30sek ost Miso > [ws + Th bt becomes validity trong teehee MICROWIRE/PLUS* Interface Functional Wavetorms (Normal Mode) 44 Parallel Ports There are three general purpose parailel ports, Port A, Port B, and Port C, The individual lines of each port can be configured as input or output, 4a4 Pot In addition to the general purpose 1/0 function, Port A provides edge-tiggered interrupt functions. Edge detect circuits are connected in parallel with the standard port and can be enabled while the port is in use. Each line of Port A can be configured to detect either or both input edges by setting the corresponding bits in the Port A configuration registers. A transition on any of these lines must remain longer than a clock cycle to be detected. When @ transition occurs, an interrupt will be generated if enabled. The PAD and PAM lines also function in conjunction with the latched input and the RAM emulation modes of Port B as described in the next section, 442 PortB In addition to the general purpose 1/0 functions, Pott B has a latched input mode. A set of latches in parallel with the Port B inputs may be used to store the value written to Port B by using the first ine of Port A (PAO) as. contol line. To latch in the current value on Port B, both PAO and Port B must be configured as inputs. The current value on Port B Is latched by either the rising or faling edge of a pulse of width greater than one clock cycle on PAO, The edge polarity Is determined by the Pot A Configuration Register. Port B also has a RAM emulation mode. In RAM emulation mode, the Port B Input is latched using PAO as a WR line. PAO controls the latch Independently of the clock. When PAO Is LOW, the latches are transparent. When PAO is HIGH, the AN#92 Powerline Network Communications Chip Set Page st current value on Port B is latched. The output of Port B is similarly controlled by PAI in this mode used as a RD line, When PAI Is LOW, the output on Port B Is enabled and the byle wiitten to Port B by the processor is available on the Port B lines, When in RAM emulation mode, PAO interrupts the processor when a wiite occurs and PAI interrupts the processor when @ read occurs [when the interupt is enabled). 443 Pot Port C is @ general purpose |/O port as described ‘above with no additional functions, 45 ROM The DLP contains 12 kbytes of mask programmable ROM. The intemal ROM is located at address 0400 The top six byles are mapped fo the top six locations in the address space (FFFA) to provide a location for the inteinal interrupt vectors. These sx bytes are disabled when EXTBUS isheld HIGH, 46 RAM The DLP contains 768 bytes of RAM, This memory starts at address 0020. allowing for 224 bytes of 2610 page RAM. 47 = Counters 47.4 General Purpose Counters Two general purpose counters, Counter A and Counter B, have four modes: interval timing, pulse generation, event counting, and pulse low measurement. The modes are selected by selfing the counter bits in the Mode Control Register, These counters are 16 bit synchronous countdowncounters The count value may be read at ony fime. 47.2. Window Counter The window counter Is a 16 bit synchronous counter. This counter Is free running and reset with the rising edge of an extemal pulse on WCNTZ The counter is used to determine the elapsed time since the last pulse on WCNTZ For example, the counter con provide a location within a 60 Kz or 80 Hz powerline half cycle delimited by zero crossings. In this example, the counter is reset by extemal circuitry detecting a powelline zero crossing and pulsing the \WCNIZ line, The counter may be read at any time to find the exact location in the time window. This example illustrates how the Window Counter can be used fo provide compatibility with X40" type systems, 47.3 Real Time interrupt Counter The Real Time Intertupt Counter is a 16 bit counter. It Is driven by the CLKDIV8 signal through a 5 bit prescaler providing an effective clock rate of 33.6 kHz This counter provides interupt intervals between 29.7 us and 1.955 48 Power Control Block The Power Control Block provides control of the power monitor, extemal reset, and watchdog timer functions. The power monitor and watchdog timer functions are controlled by the Reset State Machine {as shown in the Reset State Machine diagram. Any conailtion which causes a reset will cause POWERFAIL to be asserted LOW. When this happens, the POWERFAL condition must be cleared by the processor. The following sections describe the functions of the Power Control Block 484 Power Monitor The Power Monitor block provides the power-up circuit with cn inifiaization sequence which occurs when power Is applied, The Power Monitor block also continuously monitors V.,. for an undervoltage condition When power is fist applied, the power-up circuit initicizes the reset lines to all Internal blocks as soon as Vcc reaches 20 V (typical), When the vollage rises to 45 V (typical, oF after 400 ns, whichever is longer, the Watchdog Timer will be started. After Vic has been stable for one watchdog time-out petiod (244 ms), the inteinal reset lines will be released. All intemal biocks will be left at theit reset state, The processor will then be free to reset the POWERFAIL latch, N12 Powetline Network Communications Chip Set Poge 32 The Power Monitor block also monitors the level of V,.. Two undervoltage conditions are monitored: one at 42 V (typical) ond one at 35 V (typical). If bit 4 of the Mode Control Register equals 0 [the default state on power-up), when an undervoltage condition occurs at 42 V (typical), POWERFAIL will be asserted LOW and the DLP will be reset. When. the voltage rises above 45 V (typical), the Reset State Machine is started, If, after power-up, the processor has set bit 4 of the Mode Control Register to 4, when an undervoltage condition ocours at 42 V (Iypical), POWERFAIL is asserted LOW and cn NMI interrupt will be sent to the processor, The processor will continue to operate unless the voltage diops below 3.5 V (typical). If the voltage drops below 35 V (typical), the processor will be held in reset. When the Voltage rises to 4.5 V (typical), the initicl power-up sequence is repeated, 48.2 External Reset The RESET pin is a Schmitt-tiggered input, When the RESET line is asserted LOW, a reset pulse is intemally generated to reset all the intemal registers, counters, and /O ports to their default states. While RESET is held LOW, the processor core is disabled, but all the intemal registers, counters, memory, and 1/0 ports are accessble through the address and data buses for test purposes. When RESET is released, the processor core Is free to access the other intemal blocks of the DLP. When RESETIs asserted LOW, the POWERFAIL latch will be set and POWERFAIL will be asserted LOW. After RESET s released, the processor will then be free to reset the POWERFAIL latch, 483 Watchdog Timer A Watchdog Timer is provided to detect and reset a malfunctioning processor. It provides two signals, The first is an interrupt signal , which, if enabled, interupt the processor after 61 msin the absence of the Watchdog Timer being previously reset by the processor. The second is a reset signal which resets the processor, asserts POWERFAIL LOW, and starts the Power-up sequence. This reset signal will be generated after 244 ms in the absence of the Watchdog Timer being previously reset by the processor. In normal operation, the DISRESET pin is left unconnected (DISRESET is internally pulled down). If DISRESET is held HIGH, the Watchdog timer will only generate the interrupt signal and the reset signal will not be generated.48.4 State of DLP Pins After Reset Any conaliion which causes a reset will niialze the DLP pins to the folowing states ia Reached DOD? Input ROMS Input wD Input during Reset, LOW after Resat (Pulang with CLK) Ta HIGH SS HIGH EXISEL HIGH during Reset. After Reset, if EXTBUS is HIGH both EXTSEL and MEMS will be asserted LOW. WEMCS POWERFAL | LOW SOUT HIGH Te HIGH a HIGH MISO input MOST Input 3CK Input i Input PADPAT Input PBOPET Input POOPCT Input CNA Input CHIE input AN#92 Powerline Network Communications Chip Set Page 33POWER FAL = (POWERFAIL out asaroc LOW) [RESET = (Poona Rages: Wc met POWERFA expt eta LOW) POWER RESTORE = (Processor rest Reptrs ree: POWERFALcfpat seerma LOW) POWER G000 = (No mae POWERFAIL danearma WH procure ‘WATCHDOG =1 OR (POWERLOW = 1 AND Mate Const 4=0) OR PONERON = 0 POWERON= (v.50 ype) POWERLOW = (Vs <4.2V ype WaTCHOOG = (Watensegtar> tne Ye) Reset State Machine 49 Random Number Generator The Random Number Generator provides a pseudo- random sequence of bytes which repeat after 1023 clock cycles. A new seed written to the Random, Number Generator Register will create a new sequence, 410 Clock Circuit The Internal clock circuit congsts of an oscilator designed to be used with an extemal crystal. Under normal operation the crystal frequency is 846016 MHz, Two clock outputs are provided: CLK and CLEDIVE, CLK is the output of the intemal clock generator for connection to the PLC192 and other exteinal peripherals CLKDIVE Is provided as a divided-by-elgnt system clock for extemal peripherals With the 8.6016 MHz crystal connected, the frequency is 4.0752 MHz, The on-chip oscillator is designed for a crystal circuit to be connected between the XTL| and XILO inputs Altematively an extemal CMOS+level clock source can be used, In which case the extemal clock signal Is fed into XTLI and XILO is left floating. (An extemal TiL-level clock source is not recommended.) N12 Powetline Network Communications Chip Set Poge 34f TRO vader RESET Vedio Fre Nv Vector ‘SAkoytes User ec ue 12 kbytes ROM aa Physled Laver Cantal Registers et Rencem Number Canarcor Sid bes RAM os oe Woes I PEBORAT Infernal Regs DLP Data Link Layer and Applications Processor Memory Map |AN492 Powerline Network Communications Chip Set Page 35 } neo ExTeUS PRE ete vec441 DLP Electrical Specifications 414.4 Absolute Maximum Ratings Operation outside these rating limits may cause permanent damage to the device. All voltages are with respect toDGND. Sic Ca Poa Digital Supply Voltage -0.3V 7.0 Togic Input Voltage DEND-O3V | V..+03V Commercial Operating rc 70°C Temperature ig Extended Operating “40°C 85°C Temperature ai Slorage Temperature “55° 150 © 411.2. Power Requirements 2 | Logic Supply Voltage Tee _ [boule Supply Current P, | Total Power Consumption N12 Powstline Network Communications Chip Set Poge 36444.3. Logic Levels Rea ta V, input LOW Voltage “05 08 <| j, [Input HIGH Voltage: 20 Vv. <| s |OutputLOW Voltage 04 < é <| <| <| < [Output HIGH Voltage 24 Ta [Output LOW current 2 [ma IP AO-PAT. PCO-PCT, CS, SYNC, XILO, SOUT, RTS, DIR, CNTA. JCNTB, MEMCS [Output LOW current a [ma |D0-D7, AO-A15, MOSI, MISO, SCLK, $5, PBO-PB7, [Output LOW current @ [mA WR. RD, CLK, CLKDIVE [Output LOW current 7S [mA POWEREAIL [y [Output HIGH current 2 [mA |PAG-PA7, PCO-PC7, CS, SYNC, XTLO, SOUT, RTS, DIR, CNTA, JCNTB, MEMCS [Oulput HIGH current “a [mA ID0-D7, AD-A15, MOSi, MISO, SCLK, $5, PBO-PB7, [Output HIGH current & [mA lwre, RD, CLK, CLKDIVE [Output HIGH current a) A POWEREAL |___ |input LOW current of inputs with intemal pull up “10 -200 | pA IRDY. NM SIN, CTS, DSR, DCD, Rl, MISO, MOS, SCLK, $8, WONTZ, IPAO-PA7, PBO-PB7, PCO-PC7, CNTA, CNTB. T,_ [RPUFHIGH current of inputs with infernal pul down 10 200 | WA IEXTBUS, DISRESET 7, |input leakage current 10 | HA lD0-D7, xTU, RESET AN#92 Powerline Network Communications Chip Set Page 374412 Processor Timing Characteristics Processor Timing Information Delay XTLI 10 CLK Delay XILI10 RD or WR Data setup tine to XTL fallin [Data hod time fo XILI fallin Data appearance time from XT HIGH Data output hold time from xT LOW [Address appearance fime from xT LOW [Address Hold Time from XII LOW. CShold time from XTLILOW CS appearance time trom XTLOW Processor control signal setup time to xILI LOW Processor control signal hold fime fo XILILOW [Control signal disappearance time fo XTILOW ANI 92 Powstline Network Communications Chip Set Poge 38DATAIN DATA OUT fest Processor General Timing Waveforms at 0 Wait State AN492 Powering Network Communications Chip Set Page 30a ey ee tos 7 tow a a9 ita eat Inteinally Generated 1 Wait State Data Timing (via node control register bits 5 & 6) ANI92 Powstling Network Communications Chip Set Poge 40DATAIN DATA OUT VALID Extemally Generated 4 Wail State Data Timing AN492 Powering Network Communications Chip Set Page at~ Cn wm i TT Intemally Generated 2 Wait State Data Timing (via mode control register bits 5 & 6) ANI92 Powstling Network Communications Chip Set Poge a2opcove | ps1 | onan ee a one (Pe) PE = PRegram Courter Instruction Sequence Timing at 0 Wait State ait lel LPL LS LI] oWpratba Processorzunting 2 p} Pmocstoreunning Extemal Reset Timing AN492 Powering Network Communications Chip Set Page 434413 1/0 Port Timing Characteristics 1/0 Timing information Symbol Parameter Poo [x [Counter setup fmma to XILHIGH 3 ns fc... [Counternola time to XR HIGH 0 ns Ih Port A nferupt signal setup time To XT 5 ns HIGH fi, Port A nferuptsgnal hold time fe XIU HIGH a ag lena Port dota setup time to FAO 2 ns len, Port dota hold fime to AD i ns fz, [Port data appearance fime fom PAT 16 ns les Port B-dota disable ime from PAL 16 ns xTu COUNTER PORT A (edue) PAOIPAt / treos| nel PORT B (latch) Yo va trsoa > tho PORT B{out) vaup \ ANI92 Powstling Network Communications Chip Set Poge a4VO Pott Timing AN492 Powering Network Communications Chip Set Page 45414 Mechanical Package Information ¥ * * ancusiere DLP Data Link Layer and Applications Processor Package Information, 100-Pin Plastic Quad Flat Pack (PQFP) AN192 Powering Network Communications Chip Set Poge 465. Ordering Information ANI92CS__JAN192 Powerline Network Communications Chip Set Includes one (1) PLC192 Powerline Physical lLayer Controier and one (1) DLP Data Link Layer and Applications Processor. Rated for operation in la temperature range of 0°C to 70°C [ANTOZCSET |Same as AN192CS but rated for operation in an extended temperature range of AO" to BS For turher infomaton, please contact: Adaptive Networks Inc, P.O. Box 1020, Kendal Square Branch, Cambridge, MA 02142, Tat (617) 407-5160. Fax (617) 787-8168 Adoptive Networks reserves the right fo make changes without further notice fo any products herein fo improve rellabity, function, or sign. Adoptive Networks does not assume any lability crisng out of the appicction oF use of any product or crcult described herein: neither does it convey any license uncer ils patent ighis nor the sighs of others. Adaptive Networks products are nol desaned, iniended, oF authorized for use as components in systems intended for surgical implont into the body, or other applications intended to support or sustain life. or for any other application in which the folure of the Adoptive Networks product could create a stuation where personal injry oF death may occur. Should Buyer purchase or use Adoplive Networks products for any such unintended or unauthorized appiicotion, Buyer shall indemniy ond hold Adaptive Networks ang is officers, employees, subsiciates. offlates. and dishibutors hanless against all Clas. costs. damages and emenses. and reasonable attemay tees arsng out of. disctly oF indrectly. any claim of personal injury oF death asiociated with auch unintended or unauthorized use, even if such claim lleges that Adoptive Networks was negligent regarding the design or manufacture of the port. ANB, AN'92, AN1000, Adaptive Networks ond Alowne rrwane Ore trademarks of Adoptive Networks. Inc. MICROWIRE* and MICROWREIPLUS' ore registered trademarks of National Semiconductor Comporation, X40" & a registered trademark of X40 (USA) inc. AN492 Powering Network Communications Chip Set Page a7