5 4 3 2 1

MIMXRT595-EVK
D D

Table of Content Revision History

Page 1 TITLE_PAGE Rev. Code Date Description
A 20190311 First release
Page 2 SYSTEM_DIAGRAM B 20190516 1. Remove Q14 and related resistor
2. Add level translator for nRESET
3. Optimize MIPI power supply
4. VDDIO_2 is compatible with two power domains-3V3 and 1V8
Page 3 POWER_DIAGRAM 5. Change VDDIO_3 from 1.8V to 3.3V
6. Change eMMC IO power domain
7. Change SD card supply
Page 4 USB_SUPPLY_INTERFACE 8. Chage analog MIC circuit
9. Chage LED brightness
10. Change flexIO LCD and arduino IO power domain to 3.3V
Page 5 SYSTEM_POWER 11. Add disable circuits for external UART
12. Optimize reset circuit
20190705 1. Add AMP function
Page 6 RT595_POWER 2. Change power supply of SD card
20190709 1. add jumpers J29 and J30 instead of resistors R168 and R159
Page 7 RT595_IO 20190726 1. Merge the VDD_IO and VDDD to a single supply for U109 and U114, and removed C52 and C299.
20190731 1. Optimize PMIC circuit, and add L25 for FRO function
Page 8 MEMORY B1 20190906 1. Modify typo, this is a non-electrical change.
C 20200221 1. add load switch for SD card powe cycle
2. change DCDC U103 for M.2 supply
C
Page 9 AUDIO_CODEC 3. add low Vf diode D28 for I2C communication C

4. add load switch for M.2

5. optimzie link2 debug buffer
Page 10 AUDIO_AMP 6. add on board dmic
20200306 1. optimize de-coupling capacitors
2. optimize mcu symbol
Page 11 ACC_LED_BUTTON_UNO C1 20200423 1. correct j-trace interface
2. optimaize SDIO0 bus
Page 12 MIPI_DSI D 20201016 1. Connected VDDIO_2 to MCU_1V8
2. Updated the symbol for MIMXRT595SFFOC using
updated MUX table
Page 13 M2_FXIO_DMIC_I3C_INTERFACE 3. Added a note for the External DMIC connector connection
4. Added a note for JTAG Connection
5. Removed U116 (Only support Low Voltage SD Card now; No boot support)
Page 14 PMOD_ISP 6. Updated R179 and R180 for 5V VBUS detect (Previously using 3V VBUS detect)
7. U117 uses new GPIO (PIO4_0)

Page 15 SYSTEM_RESET D1 20210111 1. Change R547, R548 with RES 12K (470-30955) from 4.7K (470-82064).

Page 16 LINK2_DEBUG

Page 17 LINK2_DEBUG_TRANSLATOR

B B

Power Table
Block Net Name Design Voltage Design Current REF DES ASSY_OPT PAGE NAME REF DES JUMPER(DEFAULT) PAGE NAME
USB Connector USB_HS_HOST_VBUS
USB_EXT_5V0
5.0V
5.0V
0.5A/0.9A/1.8A(max)
0.5A/0.9A SS2,R149,SS4,C337,R750,R153, DNP 05_SYSTEM_POWER JP23,JS19,JS18,JP21,JP24 1-2 05_SYSTEM_POWER
Diode
LINK_5V0
SYS_5V0
5.0V
5.0V
0.5A/0.9A
0.5A/0.9A
SS1,SS3,R150,C336,L25,J37, JS21,JS20,JS30,JS23,JS25, 1-2 06_RT595_POWER
PMIC PMIC_LDO1_OUT 1.8V(default) 0.001A 1
s
R154 JS29,JS22,JS24
PMIC_LDO2_OUT 3.3V(default) 0.25A 3
PMIC_SW1_OUT 1.0V(default) 0.25A 4 q
n R656 DNP 06_RT595_POWER JS28 2-3 06_RT595_POWER
PMIC_SW2_OUT 1.8V(default) 0.5A 2
LDO VCC_3V3 3.3V 1.0A R679,R536 DNP 07_RT595_IO JS26 1-2 08_MEMORY
DCDC Buck
VCC_1V8
DCDC_3V3
1.8V
3.3V
1.0A
3.0A R456,R697,R457,R431,R430, DNP 08_MEMORY JP6,JP27,JP8,JP28,JP29,JP7 1-2 09_AUDIO_CODEC
Load Switch SDC_3V3 3.3V - R500,R693,R695,R691,R359, JP11 1-2 10_AUDIO_AMP
R700,R701,R458,R427,R692, JP33 1-2 11_ACC_LED_BUTTON_UNO
R434,R694,R696,R429,R358, JS9,JS27,JP13 1-2 14_PMOD_ISP
R790,R688,R699,R432 JS5,JP1,JS6 NONE 16_LINK2_DEBUG
C324 DNP 09_AUDIO_CODEC JS1,JP17,JP2,JP18,JP19 1-2 17_SWD_BUF
R57,R52,R653,R746,R652 DNP 10_AUDIO_AMP JP3 NONE 17_SWD_BUF
R140,R139,R137,R138 DNP 11_ACC_LED_BUTTON_UNO JP32,JP4 NONE 18_DEBUG_UART_SPI
C239,R478,R495,R494,R499, DNP 12_MIPI_DSI
R546,R477,R490,R476,R545
C321,C354,R671,Y8,R788,R712 DNP 13_M2_FXIO_DMIC_I3C_IF
JS17,J35 DNP 14_PMOD_ISP
A R12,JP30,R15,R734,R5 DNP 16_LINK2_DEBUG A

R125,R659 DNP 17_SWD_BUF

ICAP Classification: CP: ___ IUO: X PUBI: ___

Drawing Title:
MIMXRT595-EVK
Page Title:
Title and Rev History
Size Document Number Rev
C SCH-45800 PDF: SPF-45800 D1

Date: Monday, January 11, 2021 Sheet 1 of 18

5 4 3 2 1
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D D

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A A

ICAP Classification: CP: ___ IUO: X PUBI: ___

Drawing Title:
MIMXRT595-EVK
Page Title:
System Diagram
Size Document Number Rev
C SCH-45800 PDF: SPF-45800 D1

Date: Monday, January 11, 2021 Sheet 2 of 18

5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

ICAP Classification: CP: ___ IUO: X PUBI: ___

Drawing Title:
MIMXRT595-EVK
Page Title:
Power Diagram
Size Document Number Rev
C SCH-45800 PDF: SPF-45800 D1

Date: Monday, January 11, 2021 Sheet 3 of 18

5 4 3 2 1
 5 4 3 2 1

USB_HS_HOST_VBUS USB_HS_VBUS_TRGT

FB2 2 1 330 OHM

D D

C207

9
J38 2.2UF
10V

SHELL3

SHELL4
RT595 HOST/DEVICE VBUS
1
2 R715 0
D- 3 RT_USB1_DM [6]
TARGET Hi-SPD R716 0
D+ 4 RT_USB1_DP [6]
R640 0 RT_USB1_ID [7]
USB DEVICE / HOST ID

SHELL2

SHELL1
5
GND
MICRO AB U35

1
USB AB 5

USB ID
7

DP

DM
VBUS
TP509
5

GND
RClamp0854P.TCT SYS_5V0

7
TP507
D16
2

3
TP508
1

C PMEG4010CPA C

S3

S1
USB_EXT_5V0

J39
1 L16 1 2 220Ohm

D- VBUS
EXTERNAL POWER 2
C209
3 4.7UF
External +5V

D+
10V
Power only 4

ID
Micro-B 5

G
S4

S2
USB205FB-C1013223 D17
1

PMEG4010CPA

B B

USB_VBUS_LINK
LINK_5V0
S3

S1

C210 R186 470

1.0UF
J40 10V
LINK DEBUG USB 1 L17 2 1 220Ohm
D- VBUS

2
USB_DM_LINK [16]
Link 3
USB_DP_LINK [16]
D+

USB Device
4
Micro-B USB_ID_LINK [16]
ID

5
G

U36
6

USB205FB-C1013223
S4

S2

USB ID

DP

DM
VBUS

4
GND

RClamp0854P.TCT
7

A A

R786 100

C359 1000pF
500V
ICAP Classification: CP: ___ IUO: X PUBI: ___
Drawing Title:
MIMXRT595-EVK
Page Title:
USB Supply Interface
Size Document Number Rev
C SCH-45800 PDF: SPF-45800 D1

Date: Monday, January 11, 2021 Sheet 4 of 18

5 4 3 2 1
 5 4 3 2 1

MCU_1V8 PMIC_LDO1_OUT

SYS_5V0

DNP
DNP
DNP DNP DNP DNP
SS1 SS2 SS3 SS4
.635" LONG .635" LONG .635" LONG .635" LONG
PMIC_MODESEL1

100K
100K

100K

100K
2.2K
2.2K
PMIC_MODESEL0
TP38
TP39
R153 R154
D D
C148 C335 R155 0 100K 100K

R147
R148

R149
R150

R151

R152
2.2UF 22uF DNP DNP
10V 10V

C149 U30 1.0V default

1
2
C1 D4 OD

+
BT3 0.47uF PMIC_INT_B [6] mcu core supply
BAT-HLD-001 16V VIN INT C4 PMIC_ON_B
D2 ON E3 PMIC_MODESEL1 MCU_3V3

3
VBAT VBAT_BKUP MODESEL1 E4 PMIC_MODESEL0 PMIC_MODESEL1 [6] TP49 TP50 TP51 TP52

-
TP42 PMIC_SW1_OUT
MODESEL0 D5 PMIC_MODESEL0 [6] PMIC, read 0xc3, write 0xc2
SCL PMIC_I2C_SCL [6]
TP40 A1 E5 R748 0
PMIC_I2C_SDA [6]

1
VBAT SDA D3 OD
Battery Holder: TP41 SYSRST PMIC_SYSRST_B [15]
============ I A2
PSYS1 SW1_OUT
B2 R187
A3 LX1 L14 1 2 2.2uH PMIC_SW2_OUT C154 C332 C334 510
Option to Connect LX1 10uF 10uF 0.1UF
2025/ 2032 Size I C5
PSYS2 SW2_OUT
B4
B5 LX2 L15 1 2 2.2uH
TP43 10V 10V 16V

Coin Cell Battery

A
C150 C151 C152 LX2
1.0UF 1.0UF 2.2UF O B1 PMIC_LDO1_OUT 1.8V default D18
VBAT 10V 10V 10V ASYS E1 C153 C330 C333 LED_GREEN J41 J42
TP45 LDO1_OUT R164 0 10uF 22uF 0.1UF 1 1
C2 D1 10V 10V 16V 2 2
C155 TS LDO2_OUT 3.3V default 1.8V default TP44
J37

C
when power supply from Battery, 1 4.7UF B3 PMIC_LDO2_OUT HDR 1X2 HDR 1X2
need to short JP31(2-3). 2 10V C3 AGND1 A4 C157
and some functions that belong E2 AGND2 PGND1 A5 1.0UF
to 5V power domain are limited. S2B-PH-KL AGND3 PGND2 10V RT595 POWER-ON INDICATOR DEBUG GND HOOK
RT2
DNP 100K PCA9420UK TP46
t C156 PMIC_SW2_OUT
2.2UF
10V
HDR_1X3
C336 C337 JP31 R765
0.1UF 0.1UF
i Programmable Output Voltage Regulation:
=============================== MODE 0 by default 16V 16V SYS_5V0 VBAT 10
1. SW1: Core Buck, 0.5V~1.5V Output, 25mV/step, up to 250mA SW1 = 1.0V for core supply DNP DNP
C
2. SW2: System Buck, 1.5V~2.1V/2.7V~3.3V Output, 25mV/step, up to 500mA SW2 = 1.8V JS18 C

1
2
3
3. LDO1: Always-ON LDO, 1.70V~1.90V Output, 25mV/step, up to 1mA LDO1 = 1.8V for RTC always on HDR 1X2
4. LDO2: System LDO, 1.5V~2.1V/2.7V~3.3V Output, 25mV/step, up to 250mA reserved for SW2 U103 C351
LDO2 = 3.3V
2 5 0.1UF JUMPER (DEFAULT) = 1-2
IN BST 16V DCDC_3V3
MCU_3V3 L26 4.7uH

1
2
C274 C275 R567 6 3 1 2
22uF 0.1UF 47K EN/SYNC SW
SYS_5V0 VCC_3V3 10V 16V C352 C277 C276
U42 7 8 R766 C353 0.1UF
VCC FB 22uF 22uF 16V
1 4 15PF 10V 10V

GND
3
2
1
6 IN1 OUT C350 1 40.2K
C230 C231 IN2 5 C232 0.1UF SS
2.2UF 0.1UF SNS 1.0UF C355 16V MP1497 R767 33K R770

4
EPAD

10V 16V 3 10V 0.1UF C349

GND

EN JP24 16V R769 0.022uF 0

HDR_1X3 47K 250V
NCP692MN33T2G JUMPER (DEFAULT) = 1-2
2

Minimum value 1.0uF required R768

13K

MCU_1V8 R747 0 JS19

HDR 1X2 +2.5V_LINK
SYS_5V0 VCC_1V8 JUMPER (DEFAULT) = 1-2
U41 LINK_5V0
L25 1 2 47uH U33

1
2
1 4 DNP 3 2 R639 510

3
2
1
6 IN1 OUT VIN VOUT

GND

A
C226 C227 IN2 5 C228 Filter to reduce ripple for FRO. C203 C204 4 C201 C202
2.2UF 0.1UF SNS 1.0UF 4.7UF 0.1UF TAB 0.1UF 4.7UF D25
EPAD

10V 16V 3 10V 10V 16V NCP1117ST25T3G 16V 10V LED_ORANGE

GND

1
EN JP23
HDR_1X3
NCP692MN18T2G JUMPER (DEFAULT) = 1-2
2

C
Minimum value 1.0uF required
B B

2.5V- NCP1117ST25T3G LINK POWER-ON INDICATOR

Link 2.5v Power 3.3V- NCP1117ST33T3G

SKRPABE010
MCU_1V8 DCDC_3V3
1 4 PCA9420's ON# Pin have Internal Pull-up
to ASYS or VBA.

100K
USB HOST

DNP
MCU_1V8 __ON_B_SW
POWER SWITCH C343
USB_HS_HOST_VBUS USB_EXT_5V0 1.0UF
U34 10V U117 SDC_3V3 2 SW6 3 JP21
C2 B1 A2 1

R750
R183
D1 VBUS1 VINT1 B2 47K MCU_1V8 VIN A1 SILK = PMIC_ON PMIC_ON_B 2

GND
C205 C206 D2 VBUS2 VINT2 C1 R752 0 B2 VOUT 3
VBUS3 VINT3 1% [7,8] RT_PIO4_0 ON
4.7UF 4.7UF C344 Q18

100K
10V 10V A3 A2 OD FPF1504 1.0UF 2SK3018
P2_27_USB1_OC [7] HDR_1X3

B1
ILIM FAULT 10V
GND3
GND2
GND1

A1 R184 100K 1 3 JUMPER (DEFAULT) = 1-2

EN [6,10,11,15,17] nRESET_TRGT
R185
3

R795
47K NX5P3090UK R580 100K
D3
C3
B3

Current limit ~500mA 1% Q9 PMIC_LDO1_OUT

disable by default

2
1 Vgs(th) = 0.8 min, 1.5V max
P2_28_USB1_PWR_EN [7]
BSS138P
2

A A

ICAP Classification: CP: ___ IUO: X PUBI: ___

Drawing Title:
MIMXRT595-EVK
Page Title:
System Power
Size Document Number Rev
C SCH-45800 PDF: SPF-45800 D1

Date: Monday, January 11, 2021 Sheet 5 of 18

5 4 3 2 1
 5 4 3 2 1

JUMPER (DEFAULT) = 1-2

PMIC_LDO1_OUT JS29
HDR 1X2
U32A

2
1
__MCU_AO1V8 D4
B2 VDD_AO1V8_1 JUMPER (DEFAULT) = 1-2
C329 C190 VDD_AO1V8_2
JUMPER (DEFAULT) = 1-2 Put C329 near JS29 1.0UF 0.22UF JS25
HDR 1X2 10V 10V HDR 1X2 1.0V by default
JS30 PMIC_SW1_OUT
MCU_1V8

1
2

1
2
D __MCU_VDD1V8 __MCU_VDDCORE D
J14 G9
H6 VDD1V8_A VDDCORE_1 H10
C328 C168 C169 C170 C171 C172 C364 H7 VDD1V8_B LDO VDDCORE_2 H8 C174 C175 C176 C177 C178 C184 C368
Put C328 near JS30 1.0UF 10uF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF J7 VDD1V8_C VDDCORE_3 H9 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 10uF 1.0UF Put C368 near JS25
10V 10V 10V 10V 10V 10V 10V G6 VDD1V8_D VDDCORE_4 J10 10V 10V 10V 10V 10V 10V 10V
M6 VDD1V8_E VDDCORE_5 J11
E6 VDD1V8_F VDDCORE_6 J9
MCU_1V8 VDD1V8_G LDO_ENABLE VDDCORE_7 K10
VDDCORE_8 K8
R165 0 __MCU_VDD1V8_1 E8 VDDCORE_9 K9
VDD1V8_1 VDDCORE_10 L9
VDDCORE_11

U32D
Tie directly to J8 mipi core D2
__MCU_VDDA_ADC1V8 H13 MIPI_DSI_VDD11 [12] MIPI_DSI_CLKP MIPI_DSI_CLKP
R166 0 VDDCORE C225 D1
VDDA_ADC1V8 [12] MIPI_DSI_CLKN MIPI_DSI_CLKN
0.22UF
R182 0 __MCU_VREFP F12 10V B1
VREFP [12] MIPI_DSI_D0P MIPI_DSI_D0P
USB_HS_VBUS_TRGT C2
[12] MIPI_DSI_D0N MIPI_DSI_D0N
R480 0 __MCU_DSI_VDD18 F8 F5 __MIPI_VDDA_CAP OUT E3
MIPI_DSI_VDD18 MIPI_DSI_VDDA_CAP U32B [12] MIPI_DSI_D1P MIPI_DSI_D1P
LDO F3
[12] MIPI_DSI_D1N MIPI_DSI_D1N
C189 C185 C162 C229 C222 A1 R180
0.22UF 0.22UF 0.22UF 0.22UF 0.22UF VSS_1 A17
VSS_2 0
10V 10V 10V 10V 10V C11
VSS_3 C15
VSS_4 C3 5V tolerance T2
JUMPER (DEFAULT) = 1-2 VSS_5 C7 USB1_VBUS
JS20 VSS_6 E11
MCU_1V8 HDR 1X2 VSS_7 E7 R179 U2
__MCU_VDDIO_0 VSS_8 [4] RT_USB1_DP USB1_DP
J12 G10 T1
[4] RT_USB1_DM
1
2

J13 VDDIO_0_1 VSS_9 G11 51K USB1_DM

C365 C191 C192 K12 VDDIO_0_2 VSS_10 G13
C311 0.22UF 0.22UF 0.22UF M10 VDDIO_0_3 VSS_11 G14 MIMXRT595SFFOC
Put C311 near JS20 1.0UF 10V 10V 10V M12 VDDIO_0_4 VSS_12 G15
JUMPER (DEFAULT) = 1-2 10V VDDIO_0_5 VSS_13 G3
MCU_1V8 JS21 VSS_14 G4
C HDR 1X2 VSS_15 G5 C
VSS_16 G7
1
2

__MCU_VDDIO_1 E9 VSS_17 G8
F10 VDDIO_1_1 VSS_18 H11
C312 C194 C195 C196 F11 VDDIO_1_2 VSS_19 K11
Put C312 near JS21 1.0UF 0.22UF 0.22UF 0.22UF F9 VDDIO_1_3 VSS_20 K7
10V 10V 10V 10V J5 VDDIO_1_4 VSS_21 L10
JUMPER (DEFAULT) = 1-2 J6 VDDIO_1_5 VSS_22 L11
MCU_1V8 JS22 VDDIO_1_6 VSS_23 L12
HDR 1X2 VSS_24 L13
VDDIO_0,1,2,4 ONLY support 1.8V, and VDDIO_3 can support 1.8V and 3.3V VSS_25 L14
1
2

__MCU_VDDIO_2 N6 VSS_26 L15

P7 VDDIO_2_1 VSS_27 L3
C313 C198 VDDIO_2_2 VSS_28 L4
Put C313 near JS22 1.0UF 0.22UF VSS_29 L5
JUMPER (DEFAULT) = 1-2 10V 10V VSS_30 L6
MCU_3V3 JS23 VSS_31 L7
HDR 1X2 VSS_32 L8
VSS_33 M11
1
2

FXIO __MCU_VDDIO_3 M8 VSS_34 M7 MCU_1V8

N9 VDDIO_3_1 VSS_35 N11
C314 C199 VDDIO_3_2 VSS_36 N7
Put C314 near JS23 1.0UF 0.22UF VSS_37 P11 for evaluating GPS/Beidou/Galileo
10V JUMPER (DEFAULT) = 1-2 10V VSS_38 R11 C307
JS24 VSS_39 R15 0.01uF
MCU_1V8 HDR 1X2 VSS_40 R3 High or Floating - Active Y7 16V
VSS_41 R7 Low - High Impedacne (Default) 1 4
2
1

M.2 SD1 __MCU_VDDIO_4 F6 VSS_42 U1 TRI-STATE VDD

F7 VDDIO_4_1 VSS_43 U17
C315 C200 VDDIO_4_2 VSS_44 R713 2 3 R656 22 DNP
Put C315 near JS24 GND OUT CLK_26MHZ [7,11,14]
1.0UF 0.22UF 1K
10V 10V F4 26MHz
MIPI_DSI_VSS
Tie these D11
MCU_3V3 E12 VSSA_1 D7 Recommend placement
directly to
VDDA_BIAS Tie these to VSS VSSA_2
R181 0 K5 3.3V supply G12 RT595 Ex Clock
USB1_VDD3V3 VREFN
B B
R745 0
MIMXRT595SFFOC MIMXRT595SFFOC
C186 C160 PIO0_25/CLKIN Button
0.22UF 0.22UF
10V 10V

Trace_D3

U32C
R658 0 __XTALIN B4 K4 0 R176
XTALIN PMIC_I2C_SCL PMIC_I2C_SCL [5]
VDDIO_1 K6 0 R177
__XTALOUT PMIC_I2C_SDA PMIC_I2C_SDA [5]
R657 22 A4 PMIC_LDO1_OUT
R146 1M XTALOUT
D5
PMIC_IRQ_N PMIC_INT_B [5]
Y2 __RTCXIN A2 R157
RTCXIN D3
__RTCXOUT PMIC_MODE0 PMIC_MODESEL0 [5]
1 3 Y5 B3 E4 10K
RTCXOUT PMIC_MODE1 PMIC_MODESEL1 [5] JS28
1 2
VDD_AO1V8 L- disable internal LDO 1
32.768KHZ C5 H- enable internal LDO 2 when enable internal LDO, JS25 should be open
24MHZ
2

LDO_ENABLE 3 when disable internal LDO, JS25 should be short

C145 C144 C146 C147
15PF 15PF 18pF 18pF HDR_1X3
25V 25V C4 R648 0
RESET nRESET_TRGT [5,10,11,15,17]
JUMPER (DEFAULT) = 2-3
A R156 A
MIMXRT595SFFOC
1K

ICAP Classification: CP: ___ IUO: X PUBI: ___

Drawing Title:
MIMXRT595-EVK
Page Title:
RT595 Power
Size Document Number Rev
C SCH-45800 PDF: SPF-45800 D1

Date: Monday, January 11, 2021 Sheet 6 of 18

5 4 3 2 1
 5 4 3 2 1

U32E
codec AMP INT F14
U32G [9] RT_P0_0 PIO0_0/FC0_SCK/CTIMER0_MAT0/I2S_BRIDGE_CLK_IN/GPIO_INT_BMAT/SEC_PIO0_0
1.8V logic G16
M2/ISP_UART [13,14,18] RT_P0_1_FC0_TXD PIO0_1/FC0_TXD_SCL_MISO_WS/CTIMER0_MAT1/I2S_BRIDGE_WS_IN/SEC_PIO0_1

VDDIO_1 1.8V VDDIO_0 1.8V

U4 1.8V logic H16
[8] SD0_D0 PIO2_0/SD0_D[0]/SCT0_GPI2/SmartDMA_PIO0 M2/ISP_UART [13,14,18] RT_P0_2_FC0_RXD PIO0_2/FC0_RXD_SDA_MOSI_DATA/CTIMER0_MAT2/I2S_BRIDGE_DATA_IN/SEC_PIO0_2
T4 1.8V logic H15
[8] SD0_D1 PIO2_1/SD0_D[1]/SCT0_GPI3/SmartDMA_PIO1 M2/ISP_UART/ISP_GPIO [13,14] RT_P0_3_FC0_CTS PIO0_3/FC0_CTS_SDA_SSEL0/CTIMER0_MAT3/FC1_SSEL2/SEC_PIO0_3
T7 1.8V logic H14

VDDIO_2 1.8V
[8] SD0_D2 PIO2_2/SD0_D[2]/SCT0_OUT0/SmartDMA_PIO2 M2/ISP_UART [13,14] RT_P04_FC0_RTS PIO0_4/FC0_RTS_SCL_SSEL1/CTIMER_INP0/FC1_SSEL3/CMP0_OUT/SEC_PIO0_4
U6 F16
[8] SD0_D3 PIO2_3/SD0_D[3]/SCT0_OUT1/SmartDMA_PIO3 [11] UNO_P0_5_ADC0_0 PIO0_5/ADC0_0/FC0_SSEL2/SCT0_GPI0/SCT0_OUT0/CTIMER_INP1/SEC_PIO0_5
P6 F17
[8] SD0_WR_PRT_DS PIO2_4/SD0_WR_PRT/SCT0_OUT2/SD0_DS/SmartDMA_PIO4 [11] UNO_P0_6_ADC0_8 PIO0_6/ADC0_8/FC0_SSEL3/SCT0_GPI1/SCT0_OUT1/CTIMER0_MAT0/SEC_PIO0_6
P5 J15 VDDIO_0
[8] SD0_D4 PIO2_5/SD0_D[4]/SCT0_OUT3/FC8_SCK/SmartDMA_PIO5 VDDIO_2 [9] P0_7_I2S_BCLK PIO0_7/TRST/FC1_SCK/SCT0_GPI4/SCT0_OUT4/CTIMER1_MAT0/I2S_BRIDGE_CLK_OUT/SEC_PIO0_7
R4 codec & AMP H12
[8] SD0_D5 PIO2_6/SD0_D[5]/SCT0_GPI4/CTIMER1_MAT0/FC8_TXD_SCL_MISO_WS/SmartDMA_PIO6 [9] P0_8_I2S_WS PIO0_8/TCK/FC1_TXD_SCL_MISO_WS/SCT0_GPI5/SCT0_OUT5/CTIMER1_MAT1/I2S_BRIDGE_WS_OUT/SEC_PIO0_8
P4 H17
D [8] SD0_D6 PIO2_7/SD0_D[6]/SCT0_GPI5/CTIMER1_MAT1/FC8_RXD_SDA_MOSI_DATA/SmartDMA_PIO7 [9] P0_9_I2S_DATA_RX PIO0_9/TMS/FC1_RXD_SDA_MOSI_DATA/SCT0_GPI6/SCT0_OUT6/CTIMER1_MAT2/I2S_BRIDGE_DATA_OUT/SEC_PIO0_9 D
T6 K16
[8] SD0_D7 PIO2_8/SD0_D[7]/SCT0_OUT4/CTIMER1_MAT2/FC8_CTS_SDA_SSEL0/SmartDMA_PIO8 [11] USER_KEY_P0_10 PIO0_10/TDI/FC1_CTS_SDA_SSEL0/SCT0_GPI7/SCT0_OUT7/CTIMER1_MAT3/FC0_SSEL2/SEC_PIO0_10
T3 K15
[8] SD0_CARD_DET_N PIO2_9/SD0_CARD_DET_N/SCT0_OUT5/CTIMER1_MAT3/FC8_CTS_SDA_SSEL1/SmartDMA_PIO9 [11] RT_PIO0_11 PIO0_11/TDO/FC1_RTS_SCL_SSEL1/SCT0_GPI0/SCT0_OUT8/CTIMER_INP2/FC0_SSEL3/SEC_PIO0_11
N5 E14
[5,8] SD0_RST_N PIO2_10/SD0_RESET_N/SCT0_GPI6/CTIMER2_MAT0/FC8_SSEL2/SmartDMA_PIO10 [12] LCM_BL_PWM_1V8 PIO0_12/ADC0_1/FC1_SSEL2/SCT0_GPI2/SCT0_OUT2/CTIMER_INP3/SEC_PIO0_12
R2 F15
[4] RT_USB1_ID PIO2_11/SD0_VOLT/SCT0_GPI7/CTIMER2_MAT1/FC8_SSEL3/SmartDMA_PIO11 [11] UNO_P0_13_ADC0_9 PIO0_13/ADC0_9/FC1_SSEL3/SCT0_GPI3/SCT0_OUT3/CTIMER0_MAT1/SEC_PIO0_13
E15 PWM B12
[13] 32K_OUT_1V8 PIO2_14/CMP0_A/SCT0_OUT8/CTIMER_INP1/32KHZ_CLKOUT/SmartDMA_PIO14 [11] P0_14_PWM_RED_LED PIO0_14/FC2_SCK/SCT0_GPI0/SCT0_OUT0/CTIMER2_MAT0/I2S_BRIDGE_CLK_IN/SEC_PIO0_14
VDDIO_0 1.8V PWM D17 VDDIO_0 B15
[11] PIO2_15_CMP0_D PIO2_15/CMP0_D/SCT0_OUT9/CLKIN/SmartDMA_PIO15 [14,16] RT_P0_15_FC2_SCL PIO0_15/FC2_TXD_SCL_MISO_WS/SCT0_GPI1/SCT0_OUT1/CTIMER2_MAT1/I2S_BRIDGE_WS_IN/SEC_PIO0_15
N3 isp PWM A16
[17] P2_24_SWO PIO2_24/SWO/GPIO_INT_BMAT/SmartDMA_PIO24 [14,16] RT_P0_16_FC2_SDA PIO0_16/FC2_RXD_SDA_MOSI_DATA/SCT0_GPI2/SCT0_OUT2/CTIMER2_MAT2/I2S_BRIDGE_DATA_IN/SEC_PIO0_16
M2 B17
VDDIO_1 1.8V

[17] P2_25_SWD_CLK PIO2_25/SWCLK/SmartDMA_PIO25 [13] M2_UART_WK_B PIO0_17/FC2_CTS_SDA_SSEL0/SCT0_GPI3/SCT0_OUT3/CTIMER2_MAT3/FC5_SSEL2/SEC_PIO0_17

M4 B16
[14,17] P2_26_SWDIO PIO2_26/SWDIO/SmartDMA_PIO26 [13] M2_SD1_WK_B PIO0_18/FC2_RTS_SCL_SSEL1/SCT0_GPI6/SCT0_OUT6/CTIMER_INP4/FC5_SSEL3/SEC_PIO0_18
M3 F13
[5] P2_27_USB1_OC PIO2_27/USB1_OVERCURRENTN/SmartDMA_PIO27 [11] UNO_P0_19_ADC0_2 PIO0_19/ADC0_2/FC2_SSEL2/SCT0_GPI4/SCT0_OUT4/CTIMER_INP5/UTICK_CAP0/SEC_PIO0_19
P1 VDDIO_1 A14
[5] P2_28_USB1_PWR_EN RT_P2_29_I3C0_SCL B10 PIO2_28/USB1_PORTPWRN/SmartDMA_PIO28 [14] P0_21 PIO0_21/FC3_SCK/SCT0_GPI5/SCT0_OUT5/CTIMER3_MAT0/CTIMER_INP11/TRACECLK/SEC_PIO0_21
B14 VDDIO_1
RT_P2_30_I3C0_SDA D10 PIO2_29/I3C0_SCL/SCT0_OUT0/CLKOUT/SmartDMA_PIO29 [11,14] P0_22_ACC_INT PIO0_22/FC3_TXD_SCL_MISO_WS/SCT0_GPI6/SCT0_OUT6/CTIMER3_MAT1/CTIMER_INP7/TRACEDATA[0]/SEC_PIO0_22
C13
PIO2_30/I3C0_SDA/SCT0_OUT3/CLKIN/CMP0_OUT/SmartDMA_PIO30 [9,14] P0_23_I2S_DATA_TX PIO0_23/FC3_RXD_SDA_MOSI_DATA/SCT0_GPI7/SCT0_OUT8/CTIMER3_MAT2/CTIMER0_MAT3/TRACEDATA[1]/SEC_PIO0_23
C14 reset signal D13
[13] J_P2_31_I3C0_PUR PIO2_31/CMP0_B/I3C0_PUR/SCT0_OUT7/UTICK_CAP3/CTIMER_INP15/SWO/SmartDMA_PIO31 [14] P0_24 PIO0_24/FC3_CTS_SDA_SSEL0/SCT0_GPI2/SCT0_OUT9/CTIMER3_MAT3/FC2_SSEL2/TRACEDATA[2]/CLKOUT/SEC_PIO0_24
C12
[6,11,14] USER_KEY_P0_25 PIO0_25/FC3_RTS_SCL_SSEL1/FREQME_GPIO_CLK/CTIMER_INP6/FC2_SSEL3/TRACEDATA[3]/CLKIN/SEC_PIO0_25
MIMXRT595SFFOC A12
U32H reset signal pSRAM [8] P0_28_PSRAM_RESET RT_P0_29_FC4_SCL B11 PIO0_28/FC4_SCK/CTIMER4_MAT0/I2S_BRIDGE_CLK_OUT/SEC_PIO0_28
DMIC D16 RT_P0_30_FC4_SDA D14 PIO0_29/FC4_TXD_SCL_MISO_WS/CTIMER4_MAT1/I2S_BRIDGE_WS_OUT/SEC_PIO0_29
VDDIO_1 1.8V [13] DMIC_PDM_DAT23 DMIC C16 PIO3_1/PDM_CLK23/PDM_DATA23/FC0_TXD_SCL_MISO_WS/I3C1_SCL I2C D12 PIO0_30/FC4_RXD_SDA_MOSI_DATA/CTIMER4_MAT2/I2S_BRIDGE_DATA_OUT/SEC_PIO0_30
[13] DMIC_PDM_DAT45 PIO3_2/PDM_CLK45/PDM_DATA45/FC0_RXD_SDA_MOSI_DATA/I3C1_SDA VDDIO_1 [13] P0_31_WL_REG_ON PIO0_31/FC4_CTS_SDA_SSEL0/SCT0_GPI0/SCT0_OUT6/CTIMER4_MAT3/FC3_SSEL2/SEC_PIO0_31
DMIC D15
[13] DMIC_PDM_DAT67 PIO3_3/PDM_CLK67/PDM_DATA67/LCD_D23/FC0_CTS_SDA_SSEL0/I3C1_PUR/CMP0_OUT [6,11,14] CLK_26MHZ
A8 MIMXRT595SFFOC
[13] M2_SD1_CLK PIO3_8/SD1_CLK/LCD_D9/CTIMER0_MAT0/FC10_SCK U32F
B8
[13] M2_SD1_CMD PIO3_9/SD1_CMD/LCD_D10/CTIMER0_MAT1/FC10_TXD_SCL_MISO
C8 PWM A10
[13] M2_SD1_DATA0 PIO3_10/SD1_D[0]/LCD_D11/CTIMER0_MAT2/FC10_RXD_SDA_MOSI [11] P1_0_PWM_GRN_LED PIO1_0/FC4_RTS_SCL_SSEL1/SCT0_GPI1/SCT0_OUT7/CTIMER_INP8/FC3_SSEL3
C10 K2
VDDIO_4 SD1 1.8V

VDDIO_1 1.8V
[13] M2_SD1_DATA1 PIO3_11/SD1_D[1]/LCD_D12/CTIMER0_MAT3/FC10_CTS_SDA_SSELN0 [14] P1_3_SPI_CLK PIO1_3/FC5_SCK/HS_SPI1_SCK
A6 K1
[13] M2_SD1_DATA2 PIO3_12/SD1_D[2]/LCD_D13/CTIMER_INP0/FC10_RTS_SCL_SSELN1 [14] P1_4_SPI_MISO PIO1_4/FC5_TXD_SCL_MISO_WS/HS_SPI1_MISO
B7 L2
[13] M2_SD1_DATA3 PIO3_13/SD1_D[3]/LCD_D14/CTIMER_INP1/FC10_SSELN2 [14] P1_5_SPI_MOSI PIO1_5/FC5_RXD_SDA_MOSI_DATA/HS_SPI1_MOSI VDDIO_1
D9 N4
[11] PIO3_14_CMP0_E PIO3_14/CMP0_E/SD1_WR_PRT/LCD_D15/CTIMER3_MAT0/SD1_DS/FC10_SSELN3 [14] P1_6_SPI_SS0 PIO1_6/FC5_CTS_SDA_SSEL0/SCT0_GPI4/SCT0_OUT4/FC4_SSEL2/HS_SPI1_SSELN0
E10 M1
[12] LCM_PWR_EN_1V8 PIO3_15/SD1_D[4]/LCD_D16/CTIMER3_MAT1/FC5_SCK VDDIO_4 [11] ACC_RESET PIO1_7/FC5_RTS_SCL_SSEL1/SCT0_GPI5/SCT0_OUT5/CTIMER_INP9/FC4_SSEL3/HS_SPI1_SSELN1
C9 M5
[13] P3_16_BT_REG_ON PIO3_16/SD1_D[5]/LCD_D17/CTIMER3_MAT2/FC5_TXD_SCL_MISO_WS [9] RT_P1_10_MCLK PIO1_10/MCLK/FREQME_GPIO_CLK/CTIMER_INP10/CLKOUT
D8 K13
[11] P3_17_PWM_BLU_LED PIO3_17/SD1_D[6]/LCD_D18/CTIMER3_MAT3/FC5_RXD_SDA_MOSI_DATA [14,18] RT_P1_11_SPI_CLK PIO1_11/HS_SPI0_SCK/CTIMER2_MAT0
B6 K14
[12] LCM_LPTE PIO3_18/SD1_D[7]/LCD_D19/CTIMER4_MAT0/FC5_CTS_SDA_SSEL0 [14,18] RT_P1_12_SPI_MISO PIO1_12/HS_SPI0_MISO/CTIMER2_MAT1
C6 tied to Pmod SPI0 K17
[12] LCM_CTP_INT_1V8 PIO3_19/SD1_CARD_DET_N/LCD_D20/CTIMER4_MAT1/MCLK [14,18] RT_P1_13_SPI_MOSI PIO1_13/HS_SPI0_MOSI/CTIMER2_MAT2
D6 L16
[13] M2_SD1_RST_B PIO3_20/SD1_RESET_N/LCD_D21/CTIMER4_MAT2 [14,18] RT_P1_14_SPI_SS0 RT_PIO1_15_ISP0 PIO1_14/HS_SPI0_SSELN0/CTIMER2_MAT3

VDDIO_0 1.8V
E5 M16
[12] LCM_RESET_B PIO3_21/SD1_VOLT/LCD_D22/CTIMER4_MAT3/GPIO_INT_BMAT [14] RT_PIO1_15_ISP0 PIO1_15/ISP0/HS_SPI0_SSELN1/CTIMER3_MAT0
R16 T17
[13] M2_FC6_I2S_BCLK PIO3_25/FC6_SCK [8] FLEXSPI0_SCLK PIO1_18/FLEXSPI0_SCLK/SCT0_GPI0/CTIMER3_MAT3
T16 U16
VDDIO_0 1.8V

tied to NOR FLASH

[13] M2_FC6_I2S_WS PIO3_26/FC6_TXD_SCL_MISO_WS [8] FLEXSPI0_SS0_B PIO1_19/FLEXSPI0_SS0_N/SCT0_OUT0/CTIMER4_MAT0/CLKOUT
N14 T15
[13] M2_FC6_I2S_D_OUT RT_PIO3_28_ISP1 PIO3_27/FC6_RXD_SDA_MOSI_DATA VDDIO_0 [8] FLEXSPI0_DATA0 PIO1_20/FLEXSPI0_DATA0/SCT0_GPI1/CTIMER4_MAT1
C N13 T14 VDDIO_0 C
[14] RT_PIO3_28_ISP1 RT_PIO3_29_ISP2 PIO3_28/ISP1/FC6_CTS_SDA_SSEL0 [8] FLEXSPI0_DATA1 PIO1_21/FLEXSPI0_DATA1/SCT0_OUT1/CTIMER4_MAT2
M13 R13
PIO3_29/ISP2/FC6_RTS_SCL_SSEL1 [8] FLEXSPI0_DATA2 PIO1_22/FLEXSPI0_DATA2/SCT0_GPI2/CTIMER4_MAT3
R12
[8] FLEXSPI0_DATA3 PIO1_23/FLEXSPI0_DATA3/SCT0_OUT2/CTIMER_INP8
N12
MIMXRT595SFFOC [8] FLEXSPI0_DATA4 PIO1_24/FLEXSPI0_DATA4/SCT0_GPI3
R14
[8] FLEXSPI0_DATA5 PIO1_25/FLEXSPI0_DATA5/SCT0_OUT3
P14
[8] FLEXSPI0_DATA6 PIO1_26/FLEXSPI0_DATA6/SCT0_GPI4
P13
[8] FLEXSPI0_DATA7 PIO1_27/FLEXSPI0_DATA7/SCT0_OUT4
U14
[8] FLEXSPI0_DQS PIO1_28/FLEXSPI0_DQS/SCT0_GPI5
U12
[8] FLEXSPI0_SCLK_N R5 PIO1_29/FLEXSPI0_SS1_N/SCT0_OUT5/UTICK_CAP2/CTIMER_INP13/FLEXSPI0_SCLK_N
R6 PIO1_30/SD0_CLK/SCT0_GPI0 VDDIO_2
PIO1_31/SD0_CMD/SCT0_GPI1
[8] SD0_CLK
VDDIO_2 SD0 1.8V
[8] SD0_CMD MIMXRT595SFFOC

MCU_1V8
U32I
N15
[5] RT_PIO4_0 PIO4_0/FC7_SCK/FREQME_GPIO_CLK/CLKOUT
M15
VDDIO_0 1.8V

[5,11] RT_PIO4_1 PIO4_1/FC7_TXD_SCL_MISO_WS/CLKIN

M17
[13] M2_FC7_I2S_D_IN PIO4_2/FC7_RXD_SDA_MOSI_DATA
M14 R541 R542
[11,13] RT_PIO4_3 PIO4_3/FC7_CTS_SDA_SSEL0 VDDIO_0
P17
[12] LCM_CTP_RST_1V8 PIO4_4/FC7_RTS_SCL_SSEL1/FC1_SCK
P16 2.2K 2.2K
[15] RT_PIO4_5 PIO4_5/FC7_SSEL2/FC1_TXD_SCL_MISO_WS
P15 R537 0 connector TBD
[11] RT_PIO4_6 PIO4_6/FC7_SSEL3/FC1_RXD_SDA_MOSI_DATA RT_P0_30_FC4_SDA M2_I2C_SDA [13]
H2
[8] FLEXSPI1_SCLK PIO4_11/FC2_SCK/FLEXSPI1_SCLK/SD1_CLK
H1 R538 0 ACC, read 0x1f, write 0x1e
VDDIO_1 1.8V

[8] FLEXSPI1_DATA0 PIO4_12/FC2_TXD_SCL_MISO_WS/FLEXSPI1_DATA0/SD1_CMD ACC_I2C_SDA [11]

G2
[8] FLEXSPI1_DATA1 PIO4_13/FC2_RXD_SDA_MOSI_DATA/FLEXSPI1_DATA1/SD1_D[0]
F1 R543 0 connector
[8] FLEXSPI1_DATA2 PIO4_14/FC2_CTS_SDA_SSEL0/FLEXSPI1_DATA2/SD1_D[1] VDDIO_1 LCM_FX_I2C_SDA_1V8 [12]
K3
[8] FLEXSPI1_DATA3 PIO4_15/FC2_RTS_SCL_SSEL1/FLEXSPI1_DATA3/SD1_D[2]
H3
[8] FLEXSPI1_DQS PIO4_16/FC2_SSEL2/FLEXSPI1_DQS/SD1_D[3]
F2 R539 0
[8] FLEXSPI1_SCLK_N PIO4_17/FC2_SSEL3/FLEXSPI1_SS1_N/FLEXSPI1_SCLK_N/SD1_WR_PRT RT_P0_29_FC4_SCL M2_I2C_SCL [13]
E13
[8] FLEXSPI1_SS0_B PIO4_18/ADC0_6/FLEXSPI1_SS0_N/SD1_D[4]
R8 R540 0
[11,13] FXIO_D0 PIO4_20/DBI_CSX/SD1_D[6]/FC11_SCK/FLEXIO_D0 ACC_I2C_SCL [11]
P10
[11,13] FXIO_D1 PIO4_21/DBI_DSX/SD1_D[7]/FC11_TXD_SCL_MISO/FLEXIO_D1
U10 R544 0
[11,13] FXIO_D2 PIO4_22/SD1_CARD_DET_N/FC11_RXD_SDA_MOSI/FLEXIO_D2 LCM_FX_I2C_SCL_1V8 [12]
T8
B [11,13] FXIO_D3 PIO4_23/DBI_RWDX/LCD_ENABLE/SD1_RESET_N/FC11_CTS_SDA_SSELN0/TRACECLK/FLEXIO_D3 B
T10 MCU_1V8
[11,13] FXIO_D4 PIO4_24/DBI_WRX/LCD_DTCLK/SD1_VOLT/FC11_RTS_SCL_SSELN1/TRACEDATA[0]/FLEXIO_D4
T11
FLEX_IO 1.8V logic

[11,13] FXIO_D5 PIO4_25/DBI_E/LCD_HSYNC/FC11_SSELN2/TRACEDATA[1]/FLEXIO_D5

T12
[11,13] FXIO_D6 PIO4_26/LCD_VSYNC/FC11_SSELN3/TRACEDATA[2]/FLEXIO_D6 VDDIO_3
P9
[11,13] FXIO_D7
VDDIO_3

U8 PIO4_27/LCD_D0/DBI_D0/TRACEDATA[3]/FLEXIO_D7
[11,13] FXIO_D8 PIO4_28/LCD_D1/DBI_D1/FLEXIO_D8
P8 R679 R536
[11,13] FXIO_D9 PIO4_29/LCD_D2/DBI_D2/FLEXIO_D9
N8 2.2K 2.2K
[11,13] FXIO_D10 PIO4_30/LCD_D3/DBI_D3/FC12_TXD_SCL_MISO/FLEXIO_D10
N10 DNP DNP
[11,13] FXIO_D11 PIO4_31/LCD_D4/DBI_D4/FC12_RXD_SDA_MOSI/FLEXIO_D11
MIMXRT595SFFOC R469 0 codec, read 0x35, write 0x34
U32J RT_P2_30_I3C0_SDA CODEC_I3C0_SDA [9]
P12 OD R470 0 AMP1, read 0x69, write 0x68
[11,13] FXIO_D12 PIO5_0/LCD_D5/DBI_D5/FC12_CTS_SDA_SSELN0/FLEXIO_D12 AMP_I3C0_SDA [10] AMP2, read 0x6b, write 0x6a
M9
[11,13] FXIO_D13 PIO5_1/LCD_D6/DBI_D6/FC12_RTS_SCL_SSELN1/FLEXIO_D13 VDDIO_3
R9 R535 0 connector TBD
[11,13] FXIO_D14 PIO5_2/LCD_D7/DBI_D7/FC12_SSELN2/LOW_FREQ_CLKOUT/FLEXIO_D14 J_I3C0_SDA [13]
R10
[11,13] FXIO_D15 PIO5_3/LCD_D8/DBI_D8/FC12_SSELN3/LOW_FREQ_CLKOUT_N/FLEXIO_D15
P2
VDDIO_1 1.8V

[13] DMIC_PDM_CLK01 P3 PIO5_4/LCD_D9/DBI_D9/PDM_CLK01 ADS1=L, ADS2=L,

[13] DMIC_PDM_DAT01 H5 PIO5_8/LCD_D13/DBI_D13/PDM_DATA01 R467 0 read 01101001(0x69), write 01101000(0x68)
[8] FLEXSPI1_DATA4 PIO5_15/LCD_D20/FLEXSPI1_DATA4/FC4_CTS_SDA_SSEL0 RT_P2_29_I3C0_SCL CODEC_I3C0_SCL [9]
H4 VDDIO_1
[8] FLEXSPI1_DATA5 PIO5_16/LCD_D21/FLEXSPI1_DATA5/FC4_RTS_SCL_SSEL1 ADS1=H, ADS2=L,
J3 push-pull R468 0
[8] FLEXSPI1_DATA6 PIO5_17/LCD_D22/FLEXSPI1_DATA6/FC4_SSEL2 AMP_I3C0_SCL [10] read 01101011(0x6b), wirte 01101010(0x6a)
J4
[8] FLEXSPI1_DATA7 PIO5_18/LCD_D23/FLEXSPI1_DATA7/FC4_SSEL3 R534 0 J_I3C0_SCL [13]
MIMXRT595SFFOC

Port Device Address Level

M.2 TBD 1.8V
FC4_I2C Accelerator 0x1e+r/w 1.8V
MIPI-DSI display 0x70+r/w 3.3V
MCU_1V8 FlexIO-LCD display 0x5d+r/w 3.3V
Codec 0x1a+r/w 1.8V
I3C0 Amplifier-u109 0x34+r/w 1.8V
Switch Logic Amplifier-u114 0x35+r/w 1.8V
ON 0 I3C I/F TBD 1.8V
OFF 1 R188 R189 R190

SLKSCRN: ISP2, ISP1 & ISP0 SW7 100K 100K 100K

A A
3

R193 1K 3 4 RT_PIO3_29_ISP2 Boot mode PIO3_29 ISP2 PIO3_28 ISP1 PIO1_15 ISP0
R192 1K 2 5 RT_PIO3_28_ISP1 Reserved 0 0 0
R191 1K 1 6 RT_PIO1_15_ISP0 Reserved 0 0 1
USB ISP 0 1 0
1

ON
FLEXSPI Boot 0 1 1
418121160803 SDIO 0(eMMC) 1 0 0
Serial ISP (UART, SPI) 1 1 0
1K pull-down resistor is highly recommended for ISP pin. Serial download(UART, SPI) 1 1 1 ICAP Classification: CP: ___ IUO: X PUBI: ___
week pull-down may not pull down below Vil Drawing Title:
MIMXRT595-EVK
Page Title:
RT595 IO
Size Document Number Rev
C SCH-45800 PDF: SPF-45800 D1

Date: Monday, January 11, 2021 Sheet 7 of 18

5 4 3 2 1
 5 4 3 2 1

JUMPER (DEFAULT) = 1-2

JS26
HDR 1X2 QSPI Flash
MCU_1V8 MEM_1V8
MEM_1V8

2
1
S

C316 C317 Octal Flash C212 C213 MEM_1V8

1.0UF 1.0UF MEM_1V8 1.0UF 0.1UF
10V 10V 10V 16V
MEM_1V8 T
MEM_1V8
MEM_1V8 R358 R359
D D
M R360 33K 33K

8
Q U37 DNP DNP
C214 C215 C216 10K

VCC
R451 R450 U38 4.7UF 0.1UF 0.1UF 5 V1 R427 0 DNP
Frequency max = 166MHz F G B4 N 1 SI_IO0 2 V1 FLEXSPI0_DATA0 [7,8]
10V 16V 16V R455 R456 [7,8] FLEXSPI0_SS0_B R429 0 DNP R430 0 DNP
Data DDR feature VCC D1 H K CE SO_IO1 3 V1 FLEXSPI0_DATA1 [7,8]
51K 51K R431 0 DNP
VCCQ1 E4 10K 10K WP_IO2 7 V1 FLEXSPI0_DATA2 [7,8]
R432 0 DNP
FLEXSPI0_SS0_B A C2 VCCQ2 P 6 HOLD/RESET_IO3 FLEXSPI0_DATA3 [7,8]
[7,8] FLEXSPI0_SS0_B R435 0 DNP [7,8] FLEXSPI0_SCLK R434 0 DNP
R443 0 B A4 CS A5 OD SCK

GND
[15] RESET_OSPI_MEM RESET ECS
R444 0 C B2
[7,8] FLEXSPI0_SCLK SCLK
R445 0 D C3 B1 J R458 0 DNP
[7] FLEXSPI0_DQS DQS DNU_B1 FLEXSPI0_SCLK_N [7]
B5 IS25WP064AJBLE

4
R446 0 E1 D3 DNU_B5 A2 OD Close to OSPI Close to OSPI
[7,8] FLEXSPI0_DATA0 SIO0/SI NC_A2 FLEXSPI0_SS0_B
R447 0 E1 D2 A3 L R457 0 DNP for S27
[7,8] FLEXSPI0_DATA1 SIO1/SO NC_A3
R448 0 E1 C4 C5
[7,8] FLEXSPI0_DATA2 SIO2 NC_C5
R449 0 E1 D4
[7,8] FLEXSPI0_DATA3 SIO3
R680 0 E2 D5
[7] FLEXSPI0_DATA4 SIO4
R681 0 E2 E3 B3
[7] FLEXSPI0_DATA5 SIO5 GND
R682 0 E2 E2 C1
[7] FLEXSPI0_DATA6 SIO6 VSSQ1
R683 0 E2 E1 E5
[7] FLEXSPI0_DATA7 SIO7 VSSQ2 TYPE Populated DNP
MX25UW51345GXDI00 QSPI N,P,Q,S,V T,A,C,E1,F,L,E2,D
OSPI see OSPI/pSRAM table N,P,T,V1
and Q,S

P10
P11
P12
P13
P14

E10

K10
F10
P1
P2
P7
P8
P9

E9
This footprint supports: ** Base on OSPI/pSRAM table,
OSPI/pSRAM Populated DNP 1. S26KS256SDPBHV02 and DNP priority is higher than Populated, U111B
MX25UM51345GXDI00 A,B,C,D,E1,E2,F,G,H,M J,K,L 2. S27KS0641DPBHI023 (pin2pin with 3) If DNP and Populated coexist, choose DNP.

NC_P1
NC_P2
NC_P7
NC_P8
NC_P9
NC_P10
NC_P11
NC_P12
NC_P13
NC_P14

VSF1
VSF2
VSF3
VSF4
S26KS256SDPBHV02 A,B,C,D,E1,E2,F,G,H,J,K,M L 3. APS6408L-OBM-BA (pin2pin with 2) A1
4. MX25UM51345GXDI00 NC_A1
S27KS0641DPBHI023 B,C,D,E1,E2,F,G,J,L,M H,K A2 N14
APS6408L-OBM-BA B,C,D,E1,E2,F,G,J,L,M H,K A7 NC_A2 NC_N14 N13
A8 NC_A7 NC_N13 N12
A9 NC_A8 NC_N12 N11
A10 NC_A9 NC_N11 N10
A11 NC_A10 NC_N10 N9
MEM_1V8 A12 NC_A11 NC_N9 N8
pSRAM A13 NC_A12
NC_A13
NC_N8
NC_N7
N7
A14 N6
C B1 NC_A14 NC_N6 N3 C
C218 C217 C219 B7 NC_B1 NC_N3 N1
0.1UF 1.0UF 4.7UF B8 NC_B7 NC_N1 M14
R459 R460 16V 10V 10V B9 NC_B8 NC_M14 M13
51K 51K B10 NC_B9 NC_M13 M12
NC_B10 NC_M12
D1
B4 B11 M11

E4
U108 NC_B11 NC_M11
for testing B12 M10
VDDQ_1 B13 NC_B12 NC_M10 M9
VDDQ_2
VDD

R576 0 A4 B14 NC_B13 NC_M9 M8

[7] P0_28_PSRAM_RESET RST NC_B14 NC_M8
R689 0 A3 C1 M7
[7] FLEXSPI1_SS0_B CE NC_C1 NC_M7
R686 0 B2 C3 M3
[7] FLEXSPI1_SCLK CLK NC_C3 NC_M3
for testing C5 M2
[7] FLEXSPI1_SCLK_N NC_C5 NC_M2
MEM_1V8 for testing D3 R684 0 C7 M1
ADQ0 FLEXSPI1_DATA0 [7] NC_C7 NC_M1
Frequency max = 200MHz or 133MHz D2 C8 L14
ADQ1 FLEXSPI1_DATA1 [7] NC_C8 NC_L14
Data DDR feature for S26 R699 10K DNP A2 C4 C9 L13
NC_1 ADQ2 FLEXSPI1_DATA2 [7] NC_C9 NC_L13
for S26 R700 10K DNP A5 D4 C10 L12
NC_2 ADQ3 FLEXSPI1_DATA3 [7] NC_C10 NC_L12
for S26/7 R701 0 DNP B1 D5 R685 0 C11 L3
NC_3 ADQ4 FLEXSPI1_DATA4 [7] NC_C11 NC_L3
B5 E3 for testing C12 L2
NC_4 ADQ5 FLEXSPI1_DATA5 [7] NC_C12 NC_L2
C5 E2 C13 L1
NC_5 ADQ6 FLEXSPI1_DATA6 [7] NC_C13 NC_L1
E1 C14 K14
ADQ7 FLEXSPI1_DATA7 [7] NC_C14 NC_K14
D1 K13
R688 0 DNP for S26 C2 D2 NC_D1 NC_K13 K12
RSU NC_D2 NC_K12
VSSQ_1
VSSQ_2

C3 D3 K7
DQS/DM D4 NC_D3 NC_K7 K6
VSS

R687 0 D12 NC_D4 NC_K6 K3

[7] FLEXSPI1_DQS NC_D12 NC_K3
D13 K2
for testing APS6408L-OBM-BA D14 NC_D13 NC_K2 K1
B3
C1
E5

This footprint supports: APS6408L-OBx_BGA24L NC_D14 NC_K1

1. S26KS256SDPBHV02 APS6408L-OBM-BA

NC_G10
NC_G12
NC_G13
NC_G14

NC_H12
NC_H13
NC_H14
2. S27KS0641DPBHI023 (pin2pin with 3)

NC_E12
NC_E13
NC_E14

NC_F12
NC_F13
NC_F14

NC_J12
NC_J13
NC_J14
NC_G1
NC_G2
NC_G3

NC_H1
NC_H2
NC_H3
NC_E1
NC_E2
NC_E3
NC_E5
NC_E8

NC_F1
NC_F2
NC_F3

NC_J1
NC_J2
NC_J3
3. APS6408L-OBM-BA (pin2pin with 2)
4. MX25UM51345GXDI00

SDINBDA6-16G-I

E1
E2
E3
E5
E8
E12
E13
E14
F1
F2
F3
F12
F13
F14
G1
G2
G3
G10
G12
G13
G14
H1
H2
H3
H12
H13
H14
J1
J2
J3
J12
J13
J14
B B

MCU_1V8 DCDC_3V3
SDC_3V3
eMMC
SD Card C284 C283 C286 C290
C

2.2UF 0.1UF 0.1UF 0.1UF

D26 C285 Device* Populated DNP 10V 16V 16V 16V
R483 R482 R500 PESD3V3S1UB 4.7UF SD card R691~R697 R611~R620,R660,R661,R698
4.7K 10V eMMC R611~R620,R660,R661,R698 R691~R697

J10
*SD card and eMMC share the same bus, they cannot work at the same time.

E6

K9
F5
100K 100K DNP
A

J32 U111A
MEM_1V8

VCC1
VCC2
VCC3
VCC4
Fixed 1.8V
R696 0 DNP 9 R611 0 A3 C6
[7,8] SD0_D2 DAT2 [7,8] SD0_D0 DAT0 VCCQ1
R695 0 DNP 1 R612 0 A4 M4
[7,8] SD0_D3 CD/DAT3 [7,8] SD0_D1 DAT1 VCCQ2
R694 0 DNP 2 R613 0 A5 N4 C289 C288 C287
[7,8] SD0_CMD CMD [7,8] SD0_D2 DAT2 VCCQ3
3 R614 0 B2 eMMC P3 0.1UF 0.1UF 2.2UF
VSS1 [7,8] SD0_D3 DAT3 VCCQ4
4 R615 0 B3 P5 16V 16V 10V
VDD [7] SD0_D4 DAT4 VCCQ5
R693 0 DNP 5 G1 R616 0 B4
[7,8] SD0_CLK CLK GND1 [7] SD0_D5 DAT5
6
CD_SW

G2 R617 0 B5 C2
VSS2 GND2 [7] SD0_D6 DAT6 VDDI
R692 0 DNP 7 R618 0 B6
[7,8] SD0_D0 DAT0 [7] SD0_D7 DAT7
WP

R691 0 DNP 8 C4 C281 C322

[7,8] SD0_D1 DAT1 VSSQ1
R619 0 M5 N2 1.0UF 0.1UF
[7,8] SD0_CMD CMD VSSQ2
CONN_SD_CARD 9 N5 10V 16V
10
11

R620 0 M6 VSSQ3 P4
[7] SD0_CARD_DET_N [7,8] SD0_CLK CLK VSSQ4
R697 0 DNP P6
[7,8] SD0_WR_PRT_DS VSSQ5
R660 0 K5
[5,7] SD0_RST_N RST H5

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
min stub
RCLK
R790 R698
51K 51K SDINBDA6-16G-I

A6
E7
G5
H10
J5
K8
DNP MEM_1V8
A A

[7,8] SD0_WR_PRT_DS R661 0

ICAP Classification: CP: ___ IUO: X PUBI: ___

Drawing Title:
MIMXRT595-EVK
Page Title:
Memory
Size Document Number Rev
C SCH-45800 PDF: SPF-45800 D1

Date: Monday, January 11, 2021 Sheet 8 of 18

5 4 3 2 1
 5 4 3 2 1

SYS_5V0

R42
2.2K

D
MCU_1V8 P1 D
AMIC_IN1_R C323 1.0UF 1
10V OUT
C324
MCU_1V8 0.01uF 2 GND
R568 16V
0 DNP CMB-6544PF
single-end ELECTRET MIC

R484
0
C27
1.0UF
10V

C33 0.1UF

1
16V
L2
LININL C7 4.7UF __LININL_JACK 2
600OHM 10V 4
J3
Codec

2
C30 LININR C6 4.7UF __LININR_JACK 3 SJ-3524-SMT
C26 0.1UF 0.1UF 10V 1

1
16V 16V
L3

1
600OHM R19 R4 C8 C4 D4 Audio Line In
C21 47K 47K 220PF 220PF PESD5V0S2BT
VMIDC 4.7UF 50V 50V

2
10V
__MICBIAS

3
C34 C32 C35
4.7UF 4.7UF 4.7UF
10V 10V 10V

20
19

21

23
C C

4
6
7
U8

MICBIAS
MICVDD

VMIDC

DBVDD
DCVDD
CPVDD

AVDD
GND pour in audio analog
16
27 LINEOUTL 18 area tied to HPOUTFB pin.
AMIC_IN1_R 25 IN1L/DMICDAT1 LINEOUTR 17
IN1R/DMICDAT2 LINEOUTFB
LININL 26 13 HP_OUTL 2
IN2L HPOUTL 15 HP_OUTR 4
LININR 24 HPOUTR 14 J4
IN2R HPOUTFB C19 2.2UF
3 11 10V 3 SJ-3524-SMT
[7] CODEC_I3C0_SDA SDA CPVOUTP
2 12 1
[7] CODEC_I3C0_SCL SCLK CPVOUTN C18 2.2UF

1
28 MCLK_CODEC 10V C15 C17
ALT_INT_CODEC R48 22 1 MCLK 30 I2S_WS_CODEC 0.1UF 0.1UF D3
I2S_BCLK_CODEC 29 IRQ/GPIO1 LRCLK
I2S_DAI_CODEC BCLK/GPIO4
16V 16V C11 C2 PESD5V0S2BT Line out / headphone out
31 8
CPGND

220PF 220PF
DGND

ADCDAT CPCA
PGND
AGND

I2S_DAO_CODEC 32 10 R27 R38 50V 50V

DACDAT CPCB C20 20 20
2.2UF

3
WM8904 10V
9
5
33
22

GND pour in audio analog

Codec I2C addrs = 0b 0011 010X area tied to HPOUTFB pin.

B B

put them together JP27

JP8 MCLK_CODEC 1
I2S_DAI_CODEC 1 MCLK 2
[7] RT_P1_10_MCLK
2 for AMP 3
[7] P0_9_I2S_DATA_RX
3
[10] I2S_DAO_AMP
TP506 HDR_1X3
HDR_1X3 JUMPER (DEFAULT) = 1-2
JUMPER (DEFAULT) = 1-2
JP7 JP28
I2S_DAO_CODEC 1 I2S_WS_CODEC 1
R794 0 2 RLCLK/FS 2
[7,14] P0_23_I2S_DATA_TX [7] P0_8_I2S_WS
3 3
[10] I2S_DAI_AMP [10] I2S_WS_AMP

HDR_1X3 HDR_1X3
JUMPER (DEFAULT) = 1-2 JUMPER (DEFAULT) = 1-2

JP6 JP29
ALT_INT_CODEC 1 I2S_BCLK_CODEC 1
2 BCLK 2
[7] RT_P0_0 [7] P0_7_I2S_BCLK
3 3
[10] ALT_INT_AMP [10] I2S_BCLK_AMP
A A
HDR_1X3 HDR_1X3
JUMPER (DEFAULT) = 1-2 JUMPER (DEFAULT) = 1-2

ICAP Classification: CP: ___ IUO: X PUBI: ___

Drawing Title:
MIMXRT595-EVK
Page Title:
Audio Codec
Size Document Number Rev
C SCH-45800 PDF: SPF-45800 D1

Date: Monday, January 11, 2021 Sheet 9 of 18

5 4 3 2 1
 5 4 3 2 1

AMP_VBAT

AP L/R

C
R746 D27
EXTERNAL PWR SUPPLY FOR AMP 0 PMEG6020ETP
MAX INPUT PWR <5.5V DNP

A
USB_EXT_5V0
AMP_1V8
J24 AMP_VBAT
D D
1
3
2
CON_1_PWR C77 C78 C46 C41 C55
C76 C75 4.7UF 0.1UF 10uF 22uF 1.0UF

3
2
1
100UF 0.1UF 10V 16V 10V 10V 10V
16V 16V
JP11
HDR_1X3
JUMPER (DEFAULT) = 1-2 U109
B2 D5 L4 1 2 1.0uH
I2C addr setting C2 ADS1 VBAT
ADS2 L4 = 1.0uH TDK TFM201610ALM-1R0MTAA
A1 F1
A2 SCL INB
SDA F2 C295
B1 BST 1000pF
C1 VDD_IO F4 C49 C44 C53 50V
VDDD VDDP class-D 10uF 10uF 0.1UF
power supply C43 16V 16V 16V
10uF
16V

digital ground
MCU_1V8 AMP_1V8 E5
D4 GNDD1
B3 GNDD2
C3 GNDD3 E4
R571 0 D3 GNDD4 GNDP E1 R52 100 DNP
E3 GNDD5 GNDB1 E2
AMP_IO GNDD6 GNDB2 L5 120OHM J11
A3 F3 1
A4 BCK OUTA F5 A
B5 FS OUTB 2
R570 0 A5 DIO B
GAINIO B4 INT1_AMP L6 120OHM C45 C54
C5 INT D1 TB_1X2
18pF 18pF
C4 RST TEST1 D2 R57 100 DNP 25V 25V
TEST3 TEST2
TFA9896UK
C AMP_IO C

R654 100K

AMP_IO

C233 0.1UF
16V
5

U15 AMP_1V8
VCC AMP_VBAT
I1 1 INT1_AMP
4
[9] ALT_INT_AMP I2 INT2_AMP
O 2
C296 C297 C298
GND NC7SZ32P5X 10uF 22uF 1.0UF
10V 10V 10V
3

U114
I2C addr B2 D5 L19 1 2 1.0uH
setting C2 ADS1 VBAT
A1 ADS2 F1
[7] AMP_I3C0_SCL SCL INB
A2
[7] AMP_I3C0_SDA SDA F2 C300
B1 BST 1000pF
C1 VDD_IO F4 C301 C302 C303 50V
VDDD VDDP class-D 10uF 10uF 0.1UF
power supply C304 16V 16V 16V
10uF
B B
16V
E5
AMP_IO digital GND D4 GNDD1
B3 GNDD2
C63 0.1UF C3 GNDD3 E4 class-D power ground
16V D3 GNDD4 GNDP E1 R652 100 DNP
E3 GNDD5 GNDB1 E2
GNDD6 GNDB2 DC-to-DC booster ground L20 120OHM J46
U16 A3 F3 1
[9] I2S_BCLK_AMP BCK OUTA A
1 5 A4 F5
NC VCC [9] I2S_WS_AMP FS OUTB
B5 2
RESET_AMP [9] I2S_DAI_AMP DIO B
2 4 A5
[5,6,11,15,17] nRESET_TRGT A Y [9] I2S_DAO_AMP GAINIO INT2_AMP
B4 L21 120OHM C305 C306
3 RESET_AMP C5 INT D1 TB_1X2
18pF 18pF
GND C4 RST TEST1 D2 R653 100 DNP 25V 25V
74LVC1G04GW TEST3 TEST2
TFA9896UK

AMP_IO

R655 100K

ADS1=L, ADS2=L,
read 01101001(0x69), write 01101000(0x68)
ADS1=H, ADS2=L,
read 01101011(0x6b), wirte 01101010(0x6a)

A A

ICAP Classification: CP: ___ IUO: X PUBI: ___

Drawing Title:
MIMXRT595-EVK
Page Title:
Audio AMP class-D
Size Document Number Rev
C SCH-45800 PDF: SPF-45800 D1

Date: Monday, January 11, 2021 Sheet 10 of 18

5 4 3 2 1
 5 4 3 2 1

D19 DCDC_3V3
4

G
R472 1K 3 2

B
ACC sensor R473 1K 1

R
DCDC_3V3 MCU_1V8 OVSARGB4R8

R572 0 R145 0
D D

C29 C28

6
7

3
8
4.7UF 0.1UF C24 MCU_1V8 D1 D2 DCDC_3V3
10V 16V 0.1UF Q4
16V

R737 100 2 5
[7] P3_17_PWM_BLU_LED
MCU_1V8 R137 R138 G1 G2 R523
10K 10K 510

14

1
U6 DNP DNP R736 R471
PMDXB600UNEZ 1K

VDDIO
VDD
100K S1 S2

4
R139 R140 4 11 R40 100
[7] ACC_I2C_SCL P0_22_ACC_INT [7,14]

A
10K 10K SCL/SCLK INT1
DNP DNP 6 9 TP37 D20
[7] ACC_I2C_SDA SDA/MOSI INT2
[7] P1_0_PWM_GRN_LED R738 100 RED
7 8
SA0/MISO CRST
10 16 R677 1M R673 0 R739
ACC_RESET [7]

C
SA1/CS RST
2 3 active high VIHrst>1.04 100K reset LED
R135 R136 BYP RSVD1 C143 R141 VILrst<0.68 OFF during reset, ON during work normally

6
7

3
8
0 0 C31 15 13 0.1UF 1M D1 D2
NC_15 RSVD2

GND1

GND2
0.1UF 16V
16V Q3

FXOS8700CQ R740 100 2 5

[7] P0_14_PWM_RED_LED

12
G1 G2

R741
PMDXB600UNEZ
100K S1 S2

4
I2C Address 0X1E

C C

[15] SYS_RESET_LED

DCDC_3V3

Non-standard Arduino I/F

0000 00000
MCU_1V8

0000 00000
0000 00000
R742 R743

0000 00000
JUMPER (DEFAULT) = 1-2
4.7K 4.7K JP33 R11
00000 J28
DCDC_3V3 HDR 1X2 100K
SW2
JP14 DCDC_3V3 DCDC_3V3
HDR 1X2 J29 10 D15/I2C_SCL 1 3
R729 0

2
1
1 9 D14/I2C_SDA FXIO_D1 [7,11,13] FC11 2 4
R730 0 R552 1K
IOREF 2 8 AREF FXIO_D2 [7,11,13] [7] USER_KEY_P0_10
POR_B RESET_b 3 7 KMR221NG LFS
2
1

[5,6,10,15,17] nRESET_TRGT 3V3 4 6 D13/SPI_CLK R74 0

5V 5 5 D12/SPI_MISO FXIO_D15 [7,13]
C85 R75 0 C5
C

6 4 D11/OC2A/PWM/SPI_MOSI FXIO_D14 [7,13] 0.1UF

10uF R76 0
7 3 D10/SPI_CS FXIO_D13 [7,13]
D12 10V R77 0 16V
VIN 8 2 D9/OC1A/PWM FXIO_D12 [7,13]
SYS_5V0 MBR120VLSFT1G R731 0
1 D8/CLKO/ICP1 FXIO_D9 [7,13]
R732 0
FXIO_D8 [7,13]
A

SKT_1X8
B SKT_1X10 B

SYS_5V0

Special pins
Analog function: 0V to 1.8V J27
Digital function: 0V or 1.8V 8 D7/AIN1 R728 0
J30 7 D6/AIN0/PWM/OC0A PWM FXIO_D7 [7,13]
C90 R727 0
A0 1 6 D5/TI/PWM PWM FXIO_D6 [7,13]
[7] UNO_P0_5_ADC0_0 R99 1K 4.7UF R650 0 MCU_1V8
A1 2 5 D4/T0/XCK FXIO_D5 [7,13]
[7] UNO_P0_6_ADC0_8 R100 1K 10V R726 0
A2 3 4 D3/INT1/PWM/OC2B PWM FXIO_D4 [7,13]
[7] UNO_P0_19_ADC0_2 R101 1K R725 0
A3 4 3 D2/INT0 FXIO_D3 [7,13]
[7] UNO_P0_13_ADC0_9 R102 1K R675 0
SDA 5 2 D1/UART_TX FXIO_D0 [7,13]
R79 0 R10
SCL 6 1 D0/UART_RX FXIO_D10 [7,13] FC12
[7,11,13] FXIO_D2 R533 0 R80 0 FXIO_D11 [7,13] 100K
[7,11,13] FXIO_D1 R532 0 SW1
SKT_1X6 SKT_1X8
1 3
R553 1K 2 4
[6,7,14] USER_KEY_P0_25
The connectors used are 2.54mm sockets KMR221NG LFS

NOTE: Arduino shield used should not exceed 200 mA power requirements through 3V3. C3
0.1UF
16V

DCDC_3V3

A
J47 A
1 2
3 4
5 6
[5,7] RT_PIO4_1 RT_PIO4_6 [7]
enable M2_3V3 7 8
[7,13] RT_PIO4_3 RT_PIO0_11 [7]
9 10
[7] PIO3_14_CMP0_E PIO2_15_CMP0_D [7]

HDR 2X5
ICAP Classification: CP: ___ IUO: X PUBI: ___
Drawing Title:
MIMXRT595-EVK
Page Title:
ACC LED Button UNO
Size Document Number Rev
C SCH-45800 PDF: SPF-45800 D1

Date: Monday, January 11, 2021 Sheet 11 of 18

5 4 3 2 1
 5 4 3 2 1

back light circuit supports RK055IQH042-CT accessory

not support USMPA0MIPI & G1120B0MIPI accessories

L18 1 2 10uH D21 A C MBRA160T3G R490 0 DNP LEDA

D D
SYS_5V0
C238
U43 4.7uF
R494 0 DNP 6 1 50V
VIN LX
C236 C237 5
4.7UF 0.1UF 4 OVP
10V 16V CE 3 R499 0 DNP LEDK J44

GND
FB LEDK LEDK 1 S1
LEDA LEDA 2 S2
UM1661 NC 3

2
C239 R491 R492 GND 4
LCM_BL_PWM R495 0 DNP 0.1uF MIPI_TDN0 5
[6] MIPI_DSI_D0N
50V 10 10 MIPI_TDP0 6
[6] MIPI_DSI_D0P
Active H DNP GND 7
R493 MIPI_TDN1 8
[6] MIPI_DSI_D1N
100K MIPI_TDP1 9
[6] MIPI_DSI_D1P
GND 10
MIPI_TCN 11
[6] MIPI_DSI_CLKN
LCM_2V8 MIPI_TCP 12
[6] MIPI_DSI_CLKP
GND 13 1. RockTech RK055IQH042-CT.
MIPI_TDN2(NC) 14 * 2-lane
MIPI_TDP2(NC) 15 * 540 x 960
GND 16 * 5.5"
C245 * Cap touch @ 3V3
10uF MIPI_TDN3(NC) 17 * LCD control @ 1V8
10V MIPI_TDP3(NC) 18
MCU_1V8 GND 19 2. USMPA0MIPI* 2-lane
GND 20 * 400 x 400
1.8V logic LRSTB 21 * 1.4"
[7] LCM_RESET_B * Cap touch @ 3V3
1.8V logic LPTE 22
[7] LCM_LPTE * LCD control @ 1V8
C244 R476 0 DNP VDD_2V8 23
MCU_1V8 10uF LCD_ID(NC) 24 3. G1120B0MIPI
DCDC_3V3 10V R477 0 DNP IOVCC_1V8 25 * 390 x 390
LCM_I2C_SDA_3V3 3.3V logic CTP_SDA 26 * 1.2"
LCM_I2C_SCL_3V3 3.3V logic CTP_SCL 27 * Cap touch @ 3V3
DCDC_3V3 * LCD control @ 1V8
LCM_CTP_RST_B 3.3V logic CTP_RST 28 * Address 0x70
LCM_CTP_INT 3.3V logic CTP_INT 29
C R546 R545 R547 R548 R478 0 DNP VDD_3V3 30 C
2
4.7K 4.7K 12K 12K R498 10K GND 31
DNP DNP C240 C241 LCM_PWR_EN R497 0 3.3V logic POWER_EN 32
Q10 4.7UF 0.1UF GND 33
10V 16V LCM_BL_PWM R496 0 3.3V logic PWM 34
1 3 R717 0 LCM_I2C_SDA_3V3 GND 35
[7] LCM_FX_I2C_SDA_1V8
GND 36
2

2SK3018 SYS_5V0 GND 37

A C NC 38
Q11 D28 NSR0320 R489 0 VDD_5V 39
VDD_5V 40
1 3 R718 0 LCM_I2C_SCL_3V3 C234 C235 CON_1x40
[7] LCM_FX_I2C_SCL_1V8
2SK3018 4.7UF 0.1UF
10V 16V
Vgs(th) = 0.8 min, 1.5V max

R719 0
FX_I2C_SDA [13]
R720 0 FX_I2C_SCL [13]

MCU_1V8

R573
0 DCDC_3V3

B B

C254 C255
0.1UF 0.1UF
16V R561 16V
100K
16
1

U44
SYS_5V0 U40 LCM_2V8
VCCA

VCCB

3 14 LCM_CTP_RST_B
[7] LCM_CTP_RST_1V8 A1 B1 LCM_PWR_EN
4 13 3 2
[7] LCM_PWR_EN_1V8 A2 B2 LCM_BL_PWM VIN VOUT
5 12
[7] LCM_BL_PWM_1V8 A3 B3 LCM_CTP_INT
6 11 C246 C247 C248 C249

GND
[7] LCM_CTP_INT_1V8 A4 B4 10uF 0.1UF 10uF 0.1UF
R560 1K 9 10V 16V 10V 16V
OE UM1550S-28

1
2
NC/GND2

7 DIR1
DIR4
GND1

10
15 DIR3
DIR2
74AVC4TD245BQ
8

17

when DIR=L, Bn is input port

when DIR=H, An is input port

A A

ICAP Classification: CP: ___ IUO: X PUBI: ___

Drawing Title:
MIMXRT595-EVK
Page Title:
MIPI-DSI
Size Document Number Rev
C SCH-45800 PDF: SPF-45800 D1

Date: Monday, January 11, 2021 Sheet 12 of 18

5 4 3 2 1
 5 4 3 2 1

M2_3V3

J45

M2_3V3 R501 0 9 C250 C251 C252 C253

[7] M2_SD1_CLK SDIO_CLK
R502 0 11 2 10uF 0.1uF 10uF 0.1uF
[7] M2_SD1_CMD SDIO_CMD 3V3_1
R503 0 13 4 16V 16V 16V 16V
[7] M2_SD1_DATA0

1.8V logic except pin20

SDIO_DATA0 3V3_2

SDIO
R504 0 15 72
D [7] M2_SD1_DATA1 SDIO_DATA1 3V3_3 D
C321 R505 0 17 74
[7] M2_SD1_DATA2 SDIO_DATA2 3V3_4
0.01uF R506 0 19
[7] M2_SD1_DATA3 SDIO_DATA3 WL_REG_ON_3V3
Y8 16V R507 0 1.8V logic output 21 56 3.3V logic input<<
[7] M2_SD1_WK_B SDIO_WAKE W_DISABLE1 BT_REG_ON_3V3
1 4 DNP R508 0 1.8V logic input 23 54 3.3V logic input<< M2_3V3
Tri-State VDD [7] M2_SD1_RST_B SDIO_RST W_DISABLE2 6 3.3V logic
bt wakes up host LED1 16 3.3V logic D23 C A RED R525 510
2 3 R712 22 DNP M2_32K_3V3 R509 10K 3.3V logic output 20 LED2 50 3.3V logic

COMMU
GND Output [7] M2_UART_WK_B UART_WAKE SUSCLK
R510 0 output<< 22 44 input<< D22 C A RED R524 510
[7,14,18] RT_P0_2_FC0_RXD UART_RXD COEX3

UART
32.768KHZ R511 0 input>> 32 46
[7,14,18] RT_P0_1_FC0_TXD UART_TXD COEX2 M2_32K_3V3
DNP R512 0 output<< 34 48
[7,14] RT_P0_3_FC0_CTS UART_CTS COEX1
R513 0 input>> 36
[7,14] RT_P04_FC0_RTS UART_RTS 8 R515 0
I2S_SCK M2_FC6_I2S_BCLK [7]
47 10 R516 0 BT AUDIO
REFCLK_P0 I2S_WS M2_FC6_I2S_WS [7]
R709 49 12 output>> R517 0 1.8V logic

I2S
REFCLK_N0 I2S_SD_IN M2_FC7_I2S_D_IN [7]
10K 14 input<< R518 0
35 I2S_SD_OUT M2_FC6_I2S_D_OUT [7]
37 PET_P0
PET_N0 58
41 I2C_DATA 60 M2_I2C_SDA [7] 1.8V logic

I2C
43 PER_P0 I2C_CLK 62 M2_I2C_SCL [7]
PER_N0 ALERT
MCU_1V8 52 38
PERST0 VEN_DEF1

PCI EXPRESS
M2_3V3 53 40
55 CLKREQ0 VEN_DEF2 42
PEWAKE0 VEN_DEF3
71 3
73 REFCLK_P1 USB_D+ 5

USB
R703 R704 R706 R527 R526 R708 REFCLK_N1 USB_D-
4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 59 75

2
61 PET_P1 GND11 69
PET_N1 GND10 63 BH1
Q17 65 GND9 57 SMTSO-M25
67 PER_P1 GND8 51
1 3 M2_32K_3V3 PER_N1 GND7 45
[7] 32K_OUT_1V8 66 GND6 33 Stand-off for M.2
2 PERST1 GND5
68 39
2SK3018 70 CLKREQ1 GND4 18
C Q15 PEWAKE1 GND3 7 C
64 GND2 1
1 3 WL_REG_ON_3V3 RESERVED GND1
[7] P0_31_WL_REG_ON
M.2 KEY E
2

2SK3018 M.2 MINI CARD

Q16

1 3 BT_REG_ON_3V3
[7] P3_16_BT_REG_ON

2SK3018
C319 C320
Vgs(th) = 0.8 min, 1.5V max 0.1uF 0.1uF
16V 16V DCDC_3V3 U119 M2_3V3

6 1
VIN VOUT
C345 C348 3 C347 C346
for start up timing 10uF 0.1uF CT 0.1uF 10uF

EPAD
16V 16V 5 2 R787 0 16V 16V

GND
EN/UVLO QOD

TPS22810DRVT C367

4
7
0.01uF
R771 1K active H 16V
[7,11] RT_PIO4_3
Vih>1.3V

C354 R764
0.1uF 100K
16V
DNP

D//ͬ&
B B

&>y/Kͬ>^ŽĐŬĞƚ MCU_1V8

MCU_1V8
DCDC_3V3 DCDC_3V3
C318
0.1uF
16V C280
C220 R671 10uF
R788 10uF 2.2K 10V
100K 10V LCD is 3.3V logic DNP J31
DNP J43 1 2
1 2 R777 0 3 4
[7] DMIC_PDM_CLK01 [7] J_I3C0_SCL
I2C1_ SCL/SIOC 3 4 I2C1_ SDA/SIOD 5 6
[12] FX_I2C_SCL FX_I2C_SDA [12] DMIC_PDM_DAT23 [7]
INT 5 6 GPIO0 7 8
[7,11] FXIO_D10 FXIO_D8 [7,11] DMIC_PDM_DAT45 [7] [7] J_I3C0_SDA
RST 7 8 D/C 9 10
[7,11] FXIO_D12 FXIO_D11 [7,11] DMIC_PDM_DAT67 [7]
CS 9 10 WR LOW_FREQ_CLKOUT/PIO5_2 11 12
[7,11] FXIO_D13 FXIO_D14 [7,11]
LOW_FREQ_CLKOUT_N/PIO5_3RD 11 12 TE Note: R118
[7,11] FXIO_D15 FXIO_D9 [7,11] Remove R782 and R781 in order to use J18
D0 13 14 D1 1K
[7,11] FXIO_D0 FXIO_D1 [7,11] HDR 2X6 external DMIC board via this connector.
D2 15 16 D3 1
[7,11] FXIO_D2 FXIO_D3 [7,11] B No change required in the case of on board DMIC
D4 17 18 D5 2
[7,11] FXIO_D4 FXIO_D5 [7,11] usage
D6 19 20 D7 3
[7,11] FXIO_D6 FXIO_D7 [7,11] [7] J_P2_31_I3C0_PUR
D8 21 22 D9 R781 0 4
DMIC_PDM_DAT01 [7]
D10 23 24 D11
R789 D12 25 26 D13 R782
A HDR_1X4
I2C address 4.7K D14 27 28 D15 MCU_1V8 MCU_1V8
INT: H 0x28/0x29, L 0xBA/0xBB 0
CON 2X14 C356 0.1uF C357 0.1uF
16V 16V
female
U120 U121
5

5
VDD

VDD
1 R776 0 R775 0 1
DATA DATA
A 4 R773 0 R774 0 4 A
CLOCK CLOCK
Left channel 2 R783 1K 2 Right channel
GND

GND
SELECT MCU_1V8 SELECT

SPH0641LM4H-1 R784 4.7K SPH0641LM4H-1

3

3
ICAP Classification: CP: ___ IUO: X PUBI: ___
Drawing Title:

CAD Note: MIMXRT595-EVK

Microphones U120 and U121 to be placed Usage Note: Page Title:
66cm apart. - Gently remove tape before use
Acoustic holes should face to the top and - Do not touch the port hole M2 FXIO DMIC I3C
not to the bottom - Avoid liquid contact near the microphones
Size Document Number Rev
C SCH-45800 PDF: SPF-45800 D1

Date: Monday, January 11, 2021 Sheet 13 of 18

5 4 3 2 1
 5 4 3 2 1

D D

MCU_1V8 MCU_1V8
MCU_1V8

R105
R58 10K JP26
100 HS_SPI1 interface 6
5
J19 4
JTAG_VREF [7] P1_3_SPI_CLK
1 2 SWDIO 3
P2_26_SWDIO [7,17] [7] P1_4_SPI_MISO
JTAG_PWR 3 4 SWDCLK 2
IF_TCK_SWCLK [17] [7] P1_5_SPI_MOSI
5 6 SWO 1
IF_TDO_SWO [17] [7] P1_6_SPI_SS0
7 8
9 10 CON_1X6
TRACE_CLKOUT IF_RST [15,17]
11 12
P5V_TRG_JTAG 13 14 TRACE_D0 P0_21 [7]
R793 0
15 16 TRACE_D1 P0_22_ACC_INT [7,11]
TP12 R792 0
17 18 TRACE_D2 P0_23_I2S_DATA_TX [7,9]
19 20 TRACE_D3 P0_24 [7]
R714 0
USER_KEY_P0_25 [6,7,11]

HDR 2X10
R104
10K

DEBUG CONNECTOR
50mil pitch header DCDC_3V3

JP25
C J_FC0_RTS 6 C
J_FC0_RXD 5
J_FC0_TXD 4
3
J_FC0_CTS 2
1

CON_1X6

VCC_1V8 JS9 VDD_PMOD

HDR 1X2

[7] RT_PIO1_15_ISP0 MCU_1V8

1
2

JUMPER (DEFAULT) = 1-2

JP13
3 R586 DCDC_3V3
2 0
1 BRIDGE_INTR_ISP [18]
JUMPER (DEFAULT) = 1-2

HDR_1X3
[7] RT_PIO3_28_ISP1
C278 C279
0.1UF 0.1UF
16V 16V
R589 R590

16
1
VDD_PMOD U105 10K 10K
RT_P0_1_FC0_TX is the transmition pin of MCU

VCCA

VCCB
R593 0 3 14 J_FC0_TXD
J36 [7,13,18] RT_P0_1_FC0_TXD A1 B1 J_FC0_RXD
R594 1K 4 13
B [7,13,18] RT_P0_2_FC0_RXD A2 B2 J_FC0_RTS B
R109 100 1 2 R108 100 R592 0 5 12
[7,18] RT_P1_14_SPI_SS0 [7,13] RT_P04_FC0_RTS A3 B3 J_FC0_CTS
R111 100 3 4 R110 100 R591 1K 6 11
[7,18] RT_P1_13_SPI_MOSI RT_P0_3_FC0_CTS [7,13,14] [7,13,14] RT_P0_3_FC0_CTS A4 B4
1.8V logic R112 100 5 6 R113 100
[7,18] RT_P1_12_SPI_MISO RT_P0_15_FC2_SCL [7,16]
R114 100 7 8 R115 100 JUMPER (DEFAULT) = 1-2 9
[7,18] RT_P1_11_SPI_CLK RT_P0_16_FC2_SDA [7,16] JS27 OE
9 10
11 12 C134 0.1UF MCU_1V8 HDR 1X2 R582 1K 2

NC/GND2
16V R583 1K 7 DIR1
DIR4

GND1
R584 1K 10
CON_2X6 DIR3
R585 1K 15

1
2
R721 10K DIR2
MCU_1V8 74AVC4TD245BQ

17
when use external UART,
please disconnect JS27 and then short JP4 R581

100K when DIR=L, B is input port

PMIC_LDO1_OUT when DIR=H, A is input port

R134
100K

JS17
1
2

HDR 1X2
DNP

R106 J35
1 2
[15] nRESET_POR 3 4
100
SKT_2X2
DNP
A A

ICAP Classification: CP: ___ IUO: X PUBI: ___

Drawing Title:
MIMXRT595-EVK
Page Title:
PMOD ISP
Size Document Number Rev
C SCH-45800 PDF: SPF-45800 D1

Date: Monday, January 11, 2021 Sheet 14 of 18

5 4 3 2 1
 5 4 3 2 1

RST_1V8

MCU_1V8 PMIC_LDO1_OUT
0 R132

A
short by default
D D

RST_1V8 PMIC_LDO1_OUT
PMIC_LDO1_OUT

C326
R3 0.1UF R124
SLKSCRN: RESET_PB 100K 16V 100K

14
SW3 U24A

3 1 R2 100 1 2
4 2
C1 7
KMR221NG LFS 0.1UF 74LVC07APW
16V

nRESET_TRGT [5,6,10,11,17]
C C

RST_1V8

R575 0 SYS_RESET_LED [11]

14
tied to PMIC U24B

3 4
[5] PMIC_SYSRST_B
MCU_1V8
7
74LVC07APW RST_1V8

R128

14
U24E 100K

11 10
RESET_OSPI_MEM [8]
7
74LVC07APW
TP32 TP34
PMIC_LDO1_OUT

RST_1V8
R723

100K
14

tied to conn U24C

5 6
[14] nRESET_POR
7 MCU_1V8
74LVC07APW
RST_1V8
B B
R131

14
100K U24F

R791 0 13 12
[7] RT_PIO4_5
7
PMIC_LDO1_OUT 74LVC07APW
TP33
RST_1V8
R724

51K
14

tied to debug I/F U24D

9 8
[14,17] IF_RST
7
74LVC07APW

A A

ICAP Classification: CP: ___ IUO: X PUBI: ___

Drawing Title:
MIMXRT595-EVK
Page Title:
System Reset
Size Document Number Rev
C SCH-45800 PDF: SPF-45800 D1

Date: Monday, January 11, 2021 Sheet 15 of 18

5 4 3 2 1
 5 4 3 2 1

+2.5V_LINK

2
L13
+2.5V_LINK 600OHM

1
3v3_LINK_CORE
C94 C92 C99 C100
0.1UF 0.1UF 0.1UF 0.1UF +2.5V_LINK
16V 16V 16V 16V C93 C96 C91
D D
0.1UF 0.1UF 4.7UF
16V 16V 10V JS6
HDR 1X2
JUMPER (DEFAULT) = NONE

F10
C5

B2

K5

E4
E5
F4

1
2
U1A R126 R127 RT_P0_15_FC2_SCL [7,14]

VDDA

VDDIO1
VDDIO2

VDDREG1
VDDREG2
VDDREG3
VBAT
A2 2.2K 2.2K
ADC0_0/ADC1_0/DAC A1 JS5
ADC0_1/ADC1_1 B3 HDR 1X2
ADC0_2/ADC1_2 A3 JUMPER (DEFAULT) = NONE
TRACE_D0 G2 ADC0_3/ADC1_3
TRACE_D1 G1 P0_0/GPIO0[0]/SSP1_MISO/ENET_RXD1/SGPIO0/I2S0_TX_WS/I2S1_TX_WS D6

1
2
P0_1/GPIO0[1]/SSP1_MOSI/ENET_COL/SGPIO1/ENET_TX_EN/I2S1_TX_SDA I2C0_SCL E6
I2C0_SDA RT_P0_16_FC2_SDA [7,14]
CUR_MEAS_SEL H1
BOOT0_LED K2 P1_0/GPIO0[4]/CTIN_3/EMC_A5/SSP0_SSEL/SGPIO7/EMC_D12 E1
K1 P1_1/GPIO0[8]/CTOUT_7/EMC_A6/SGPIO8/SSP0_MISO/EMC_D13 USB0_DP E2 USB_DP_LINK [4]
BOOT1
J1 P1_2/GPIO0[9]/CTOUT_6/EMC_A7/SGPIO9/SSP0_MOSI/EMC_D14 USB0_DM USB_DM_LINK [4]
[18] BRIDGE_L_MISO P1_3/GPIO0[10]/CTOUT_8/SGPIO10/EMC_OE/USB0_IND1/SSP1_MISO/SD_RST
J2 E9
[18] BRIDGE_L_MOSI P1_4/GPIO0[11]/CTOUT_9/SGPIO11/EMC_BLS0/USB0_IND0/SSP1_MOSI/EMC_D15/SD_VOLT1 USB1_DP USB_VBUS_LINK
J4 E10
[17] TMS_SWDIO_TXEN P1_5/GPIO1[8]/CTOUT_10/EMC_CS0/USB0_PWR_FAULT/SSP1_SSEL/SGPIO15/SD_POW USB1_DM +2.5V_LINK
K4
[17] TMS_SWDIO P1_6/GPIO1[9]/CTIN_5/EMC_WE/EMC_BLS0/SGPIO14/SD_CMD
G4 E3
H5 P1_7/GPIO1[0]/U1_DSR/CTOUT_13/EMC_D0/USB0_PPWR USB0_VBUS F1 __USB_ID R14 0
BRIDGE_L_INTR-ISP J5 P1_8/GPIO1[1]/U1_DTR/CTOUT_12/EMC_D1/SD_VOLT0 USB0_ID F3 USB_ID_LINK [4]
[18] BRIDGE_L_INTR-ISP R13 12.1K MCU_3V3
H6 P1_9/GPIO1[2]/U1_RTS/CTOUT_11/EMC_D2/SD_DAT0 USB0_RREF R735 0
BRDG_INTR-ISP_DIR J7 P1_10/GPIO1[3]/U1_RI/CTOUT_14/EMC_D3/SD_DAT1 D1
[18] BRDG_INTR-ISP_DIR P1_11/GPIO1[4]/U1_CTS/CTOUT_15/EMC_D4/SD_DAT2 USB0_VDDA3V3_DRIVER
TRACE_CLK K7 D2 R734 0 DNP
H8 P1_12/GPIO1[5]/U1_DCD/EMC_D5/T0_CAP1/SGPIO8/SD_DAT3 USB0_VDDA3V3
J8 P1_13/GPIO1[6]/U1_TXD/EMC_D6/T0_CAP0/SGPIO9/SD_CD D3 C98 C95 C97
[17] TDO_SWO P1_14/GPIO1[7]/U1_RXD/EMC_D7/T0_MAT2/SGPIO10 USB0_VSSA_TERM +2.5V_LINK
TRACE_D2 K8 F2 0.1UF 0.1UF 10uF
TRACE_D2 H9 P1_15/GPIO0[2]/U2_TXD/SGPIO2/ENET_RXD0/T0_MAT1/EMC_D8 USB0_VSSA_REF 16V 16V 10V
H10 P1_16/GPIO0[3]/U2_RXD/SGPIO3/ENET_CRS/T0_MAT0/EMC_D9/ENET_RX_DV A6 R31 12.1K
[17] TCK_SWCLK P1_17/GPIO0[12]/U2_UCLK/ENET_MDIO/T0_CAP3/CAN1_TD/SGPIO11 DBGEN
J10
[17] JTAG_TDI P1_18/GPIO0[13]/U2_DIR/ENET_TXD0/T0_MAT3/CAN1_RD/SGPIO12/EMC_D10
BRIDGE_L_SCK K9 A4 R32 100K
[18] BRIDGE_L_SCK P1_19/ENET_TX_CLK/ENET_REF_CLK/SSP1_SCK/CLKOUT/I2S0_RX_MCLK/I2S1_TX_SCK WAKEUP0
BRIDGE_L_SSEL K10
[18] BRIDGE_L_SSEL P1_20/GPIO0[15]/SSP1_SSEL/ENET_TXD1/T0_CAP2/SGPIO13/EMC_D11 B6 R30 12.1K
C K3 RESET C
K6 CLK0/EMC_CLK0/CLKOUT/SD_CLK/EMC_CLK01/SSP1_SCK/ENET_TX_CLK/ENET_REF_CLK C3
+2.5V_LINK CLK2/EMC_CLK3/CLKOUT/SD_CLK/EMC_CLK23/I2S0_TX_MCLK/I2S1_RX_SCK RTC_ALARM A5 C13
G3 RTCX1 B5 27PF

2
B4 TDI RTCX2 50V
H3 TRST B1 Y1
TDO/SWO XTAL1

VSSA
C4 C1

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
TMS/SWDIO XTAL2 12MHZ
JP30 R33 H2
1 TCK/SWDCLK
2 12.1K LPC4322JET100 C14

C8
D4
D5
G8
J3
J6

C2

1
3 27PF
4 __nTRST_LINK2 50V
5 __SWDIO_LINK2
6 __SWDCLK_LINK2

CON_1X6
DNP R8

2.2K

U1B
B
G10
Link2 B
[18] BRIDGE_UART_RXD P2_0/SGPIO4/U0_TXD/EMC_A13/USB0_PPWR/GPIO5[0]/T3_CAP0/ENET_MDC
[18] BRIDGE_UART_TXD
G7
P2_1/SGPIO5/U0_RXD/EMC_A12/USB0_PWR_FAULT/GPIO5[1]/T3_CAP1
LPC4322 Boot Mode
TARGET_UART_CTRL F5
D8 P2_2/SGPIO6/U0_UCLK/EMC_A11/USB0_IND1/GPIO5[2]/CTIN_6/T3_CAP2/EMC_CS1 +2.5V_LINK DFU USB0 = B3:0 = 0101
D9 P2_3/SGPIO12/I2C1_SDA/U3_TXD/CTIN_1/GPIO5[3]/T3_MAT0/USB0_PPWR
D10 P2_4/SGPIO13/I2C1_SCL/U3_RXD/CTIN_0/GPIO5[4]/T3_MAT1/USB0_PWR_FAULT
[17] JTAG_RESET P2_5/SGPIO14/CTIN_2/USB1_VBUS/ADCTRIG1/GPIO5[5]/T3_MAT2/USB0_IND0
G9 R9 2.2K BOOT1
[17] JTAG_RESET_TXEN LINK2_ISP_BOOT P2_6/SGPIO7/U0_DIR/EMC_A10/USB0_IND0/GPIO5[6]/CTIN_7/T3_CAP3/EMC_BLS1
C10
BOOT2 C6 P2_7/GPIO0[7]/CTOUT_1/U3_UCLK/EMC_A9/T3_MAT3 R29 2.2K BOOT2
BOOT3 B10 P2_8/SGPIO15/CTOUT_0/U3_DIR/EMC_A8/GPIO5[7]
E8 P2_9/GPIO1[10]/CTOUT_3/U3_BAUD/EMC_A0 R21 2.2K BOOT3
ISP_CTRL A9 P2_10/GPIO0[14]/CTOUT_2/U2_TXD/EMC_A1
B9 P2_11/GPIO1[11]/CTOUT_5/U2_RXD/EMC_A2
R28 1.5K A10 P2_12/GPIO1[12]/CTOUT_4/EMC_A3/U2_UCLK LINK2_ISP_BOOT
[17] IF_DETECT P2_13/GPIO1[13]/CTIN_4/EMC_A4/U2_DIR

1
2
A8
F7 P3_0/I2S0_RX_SCK/I2S0_RX_MCLK/I2S0_TX_SCK/I2S0_TX_MCLK/SSP0_SCK Short JP1 to force DFU boot mode
G6 P3_1/I2S0_TX_WS/I2S0_RX_WS/CAN0_RD/USB1_IND1/GPIO5[8]/LCD_VD15 to re-program LPC4322 internal flash
SSP0_SCK_LINK A7 P3_2/I2S0_TX_SDA/I2S0_RX_SDA/CAN0_TD/USB1_IND0/GPIO5[9]/LCD_VD14 HDR 1X2
B8 P3_3/SPI_SCK/SSP0_SCK/SPIFI_SCK/CGU_OUT1/I2S0_TX_MCLK/I2S1_TX_SCK
P3_4/GPIO1[14]/SPIFI_SIO3/U1_TXD/I2S0_TX_WS/I2S1_RX_SDA/LCD_VD13 JP1
B7
SSP0_MISO_LINK C7 P3_5/GPIO1[15]/SPIFI_SIO2/U1_RXD/I2S0_TX_SDA/I2S1_RX_WS/LCD_VD12 JUMPER (DEFAULT) = NONE
SSP0_MOSI_LINK D7 P3_6/GPIO0[6]/SPI_MISO/SSP0_SSEL/SPIFI_MISO/SSP0_MISO
SSP0_SSEL_LINK E7 P3_7/SPI_MOSI/SSP0_MISO/SPIFI_MOSI/GPIO5[10]/SSP0_MOSI +2.5V_LINK
P3_8/SPI_SSEL/SSP0_MOSI/SPIFI_CS/GPIO5[11]/SSP0_SSEL
H7
G5 P6_0/I2S0_RX_MCLK/I2S0_RX_SCK R6 2.2K BOOT0_LED
[17] SW_SEL P6_1/GPIO3[0]/EMC_DYCS1/U0_UCLK/I2S0_RX_WS/T2_CAP0
J9
F6 P6_2/GPIO3[1]/EMC_CKEOUT1/U0_DIR/I2S0_RX_SDA/T2_CAP1
F9 P6_4/GPIO3[3]/CTIN_6/U0_TXD/EMC_CAS R7
F8 P6_5/GPIO3[4]/CTOUT_6/U0_RXD/EMC_RAS
C9 P6_9/GPIO3[5]/EMC_DYCS0/T2_MAT2 2.2K
P6_11/GPIO3[7]/EMC_CKEOUT0/T2_MAT3
H4

A
PF_4/SSP1_SCK/GP_CLKIN/TRACECLK/I2S0_TX_MCLK/I2S0_RX_SCK
R5 R15 R12 R17 D2
2.2K 2.2K 2.2K 2.2K LPC4322JET100
A DNP DNP DNP RED A

LINK2 BOOT MODE

C ICAP Classification: CP: ___ IUO: X PUBI: ___
Drawing Title:
MIMXRT595-EVK
Page Title:
Link2 Debug
Size Document Number Rev
C SCH-45800 PDF: SPF-45800 D1

Date: Monday, January 11, 2021 Sheet 16 of 18

5 4 3 2 1
 5 4 3 2 1

Note:
+2.5V_LINK Remove jumpers on JP17,18,19 in order to connect with
JTAG for debugging purpose. By Default they should be MCU_1V8
VDD_LINK ON to work with LPC-LINK-2.

C339 C16 0.1UF JP18

0.1UF 16V HDR 1X2
D D
16V U3 JUMPER (DEFAULT) = 1-2 C338
1 8 0.1UF
VCCA VCCB 16V

14
2
1
2 7 R35 100 IF_TCK_SWCLK U7
[16] TCK_SWCLK 1A 1B Link2 probe connected to: JP3

VCC
3 6 R26 100 IF_JTAG_TDI
[16] JTAG_TDI 2A 2B On-board Target Open (default)
4
GND DIR
5 R24 100K SUPPLY PATH SWITCH Off-board Target Shorted
1
74AVC2T45DP H A->B +2.5V_LINK 1Y0 16
L A<-B 15 1Z
1Y1

DATA PATH SWITCH

5
2Y0 4
IF_TCK_SWCLK 2Z P2_25_SWD_CLK [7]
3
2Y1

9
3Y0 8 R125 0 DNP
+2.5V_LINK 7 3Z nRESET_TRGT [5,6,10,11,15]
VDD_LINK 3Y1

VDD_LINK 13
C340 4Y0 12
IF_TDO_SWO 4Z P2_24_SWO [7] MCU_1V8
0.1UF C25 0.1UF R41 11
16V U5 16V 4Y1
100K
1 6
H A->B 5 VCCA VCCB 10 2 S# L:Z-Y0, H:Z-Y1 R39 100K
L A<-B DIR NC S
3 4 IF_TDO_SWO R659 0 DNP

GND
[16] TDO_SWO A B SW_SEL [16]
JP3
1
2 NX3DV2567GU 2

6
GND
C
74LVC1T45GW,125
default open C
HDR 1X2
JUMPER (DEFAULT) = NONE

+2.5V_LINK

C341
0.1UF VDD_LINK
VDD_LINK
10-pin SWD
16V
C10 0.1UF JP19
U2 16V R16 HDR 1X2
H A->B 1 6 JUMPER (DEFAULT) = 1-2 MCU_1V8
L A<-B 5 VCCA VCCB 100K
[16] TMS_SWDIO_TXEN DIR
2
1

3 4 R18 100 P2_26_SWDIO

[16] TMS_SWDIO A B

R20 2 VDD_LINK JP2

Buffer Power Select: JP2

A
GND 1
2.2K
74LVC1T45GW,125 2 D5
3 PMEG1020EH
On-board Target 1 - 2 (default)
Off-board Target 2 - 3
HDR_1X3

C
JUMPER (DEFAULT) = 1-2
B B

Target
MIMXRT5xx
C12
10uF SWD Debug
10V
J2
1 2 P2_26_SWDIO
+2.5V_LINK 3 4 IF_TCK_SWCLK P2_26_SWDIO [7,14]
IF_TDO_SWO IF_TCK_SWCLK [14]
5 6
IF_JTAG_TDI IF_TDO_SWO [14]
7 8
VDD_LINK VDD_LINK 9 10 IF_RST
[16] IF_DETECT IF_RST [14,15]
C342
0.1UF HDR 2X5

6
16V C36 0.1UF JP17
U10 16V R43 HDR 1X2 D13
H A->B 1 6 JUMPER (DEFAULT) = 1-2 JS1 PESD3V3L5UY
L A<-B 5 VCCA VCCB 100K JUMPER (DEFAULT) = 1-2 1
[16] JTAG_RESET_TXEN DIR 2
2
1

2
3 4 R44 100 IF_RST
[16] JTAG_RESET A B HDR 1X2

2
R47 GND
74LVC1T45GW,125
2.2K

JTAG Name Pin Name Net Name CONN Ref#

TRST PIO0_7 P0_7_I2S_BCLK JP29-2
TCK PIO0_8 P0_8_I2S_WS JP28-2
A TMS PIO0_9 P0_9_I2S_DATA_RX JP8-2 A
TDI PIO0_10 USER_KEY_P0_10 JP33-2
TDO PIO0_11 RT_PIO0_11 JP47-8
**if need boundary scan, an external JTAG or on-board
JTAG is required and tie to these pins.

ICAP Classification: CP:

<Classification > IUO: PUBI:
Drawing Title:
MIMXRT595-EVK
Page Title:
SWD Buffer
Size Document Number Rev
C SCH-45800 PDF: SPF-45800 D1

Date: Monday, January 11, 2021 Sheet 17 of 18

5 4 3 2 1
 5 4 3 2 1

Link2 Level Translators

Link2 side Target MIMXRT5xx side

MCU_1V8
D D

+2.5V_LINK R577
0

+2.5V_LINK C38 0.1UF

JP4
16V C37 0.1UF
1 16V
when use ISP UART, 2 R772 0
please disconnect JP4 and then short JS27

16
1
U9
HDR 1X2

VCCA

VCCB
JUMPER (DEFAULT) = NONE 3 14
4 A1 B1 13 R595 0
[16] BRIDGE_UART_RXD A2 B2 RT_P0_2_FC0_RXD [7,13,14]
5 12 R596 0
[16] BRIDGE_UART_TXD A3 B3 RT_P0_1_FC0_TXD [7,13,14]
6 11
+2.5V_LINK A4 B4
R763 2.2K 9
OE
R762 100K 2

NC/GND2
R761 100K 7 DIR1
DIR4

GND1
R759 2.2K 10
R760 100K 15 DIR3
DIR2
74AVC4TD245BQ

17
C C
MCU_1V8

R579
+2.5V_LINK 0

C23 0.1UF C22 0.1UF

16V 16V

16
1
U4
master slave

VCCA

VCCB
3 14 R641 0
[16] BRIDGE_L_SSEL A1 B1 RT_P1_14_SPI_SS0 [7,14]
4 13 R642 0
[16] BRIDGE_L_SCK A2 B2 RT_P1_11_SPI_CLK [7,14]
5 12 R644 0
[16] BRIDGE_L_MISO A3 B3 RT_P1_12_SPI_MISO [7,14]
6 11 R643 0
[16] BRIDGE_L_MOSI A4 B4 RT_P1_13_SPI_MOSI [7,14]
+2.5V_LINK R23 2.2K 9
OE
R37 100K 2

NC/GND2
R753 100K 7 DIR1
DIR4

GND1
R755 2.2K 10
R754 100K 15 DIR3
DIR2
DIR# 74AVC4TD245BQ

17
H: An to Bn
L: Bn to An

+2.5V_LINK
JP32
B B
2
1 R758 0
MCU_1V8
R756 0
HDR 1X2
JUMPER (DEFAULT) = NONE
+2.5V_LINK

R578

C140 0.1UF 0
16V
C139 0.1UF
16V
7

6
U118
VCCA

VCCB

R757 2.2K 2
OE
R34 2.2K 8 5 R36 2.2K
[16] BRIDGE_L_INTR-ISP A1 B1 BRIDGE_INTR_ISP [14]
9 4
A2 B2
10
[16] BRDG_INTR-ISP_DIR DIR1
1
DIR2
GND

BRDG_INTR-ISP_DIR: R25
2.2K
DIR3 = 0 Link2 < MIMXRT5xx SN74AVC2T245
3

DIR#
DIR3 = 1 Link2 > MIMXRT5xx H: An to Bn
L: Bn to An

A A

ICAP Classification: CP: ___ IUO: X PUBI: ___

Drawing Title:
MIMXRT595-EVK
Page Title:
Debug Translator
Size Document Number Rev
C SCH-45800 PDF: SPF-45800 D1

Date: Monday, January 11, 2021 Sheet 18 of 18

5 4 3 2 1