ARM Accredited Microcontroller

Engineer (AAME) Program

Drew Barbier – ARM Field Application Engineer

October 8 th, 2014

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External Use
Become an ARM Accredited Engineer!
Overview

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External Use 2
What is the AAE program

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External Use 3
Characteristics of the AAE program
Computer-
Based Tests
(Series of
Multiple Exams Multiple Choice Industry-Wide
Questions) Standard
Subject, Scope,
Difficulty Level Same exam
throughout the world

Administered 3rd Party

Through Training
Prometric Ecosystem
(Leading CBT and Trainers and
Certification body) universities

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External Use 4
How do Individuals Benefit?

 Stand out from the crowd –

Accreditation differentiates
 Accredited engineers more likely to be
promoted, get pay-rises and/or better
jobs
 Students can use accreditation to help
secure first job
 Use AAE syllabus as a guide for self
study and skills development

 Gain credible evidence of ARM-related knowledge

 Technology consultants and journalists can use to
enhance technical credibility

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External Use 5
How do Employers Benefit

 Consistent benchmark for

ARM-related recruitment
 Use during recruitment
selection and interview
process
 Use as skills development
target for existing staff
 Measure success of
training programs

 Use during selection of external consultants & trainers

 Use to motivate and incentivize existing staff
 Accredited engineers likely to be more productive and
have deeper ARM knowledge

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External Use 6
Prometric – A Market Leader in CBT

• AVAILABLE NOW –
www.prometric.com/arm

• Established infrastructure and proven track

record in global test program delivery across I.T.
and academic markets
• Over 6000 secure test centres worldwide
• Robust security processes
• Online Registration for candidates
Available worldwide 24 x 7; local call
rates for booking via contact centres
• Flexible Voucher Schemes for
Test Facility in Taiwan
specific country or partner promotions

BOOK DIRECT via Prometric

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External Use 7
What to expect in the AAME exam?

System Startup
5%
Software
Optimization
10%

Architectural
Software 35%
Development
30%

Software Debug
Implementation 13%
7%

• ARMv6m and ARMv7m

• 70 multiple choice questions
• 90 minutes to complete
• Pass/fail (no letter grades)

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External Use 8
Prepare for the Test

Materials on
Self-study
Read AAE Syllabus ARM Infocentre
Document + many books

Online training ARM website

AAE Syllabus is the most and other
important starting point partners

Instructor-led
ARM training,
training
ARM is committed to ATCs and AATPs
growing the range of
options available to help
test-takers prepare for
Further/higher AAUPs and other
AAE accreditation education universities

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External Use 9
Architecture

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External Use 10
Development of the ARM Architecture

v4 v5 v6 v7
SIMD Instructions Thumb-2
Halfword and Improved Multi-processing NEON™
signed halfword ARM/Thumb v6 Memory architecture TrustZone®
/ byte support Interworking Unaligned data support Virtualization
System mode CLZ Architecture Profiles
Thumb Saturated arithmetic Extensions v7-A (Applications): NEON
instruction set DSP multiply- Thumb-2 (v6T2)
accumulate TrustZone (v6Z) v7-R (Real-time): Hardware divide
instructions Multicore (v6K)
Thumb only (v6-M) v7-M (Microcontroller): Hardware
divide, Thumb-only

 Note that implementations of the same architecture can be different:

 ARM Cortex-A8 - architecture v7-A with a 13-stage pipeline
 ARM Cortex-A9 - architecture v7-A with an 8-stage pipeline
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External Use 11
ARMv7 Architecture Profiles

• Application profile (ARMv7-A)

− Memory management support (MMU)
− Highest performance at low power
 Influenced by multi-tasking OS system requirements
− TrustZone and Jazelle-RCT for a safe, extensible system
− e.g. ARM Cortex-A8, ARM Cortex-A9 processors
• Real-time profile (ARMv7-R)
− Protected memory (MPU)
− Low latency and predictability ‘real-time’ needs
− Evolutionary path for traditional embedded business
− e.g. Cortex-R4
• Microcontroller profile (ARMv7-M, ARMv6-M)
− Lowest gate count entry point
− Deterministic and predictable behavior a key priority
− Deeply embedded use
− e.g. Cortex-M3

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External Use 12
ARM Cortex-M Processors

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External Use 13
ARMv7-M Profile Overview

• v7-M Cores are designed to support the microcontroller market

− Simpler to program – entire application can be programmed in C
− Fewer features needed than in application processors
• Register and ISA changes from other ARM cores
− No ARM instruction set support
− Only one set of registers
− xPSR has different bits than CPSR
• Different modes and exception models
− Only two modes: Thread mode and Handler mode
− Vector table is addresses, not instructions
− Exceptions automatically save state (r0-r3, r12, lr, xPSR, pc) on the stack
• Different system control/memory layout
− Cores have a fixed memory map
− No coprocessor 15 – controlled through memory mapped control registers

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External Use 14
ARMv7-M Register Set

• Registers R0-R7
R0
R1 − Accessible to all instructions
R2
R3 • Registers R8-R12
R4
− Accessible to a few 16-bit instructions
R5
R6 − Accessible to all 32-bit instructions
R7
R8 • R13 is the stack pointer (SP)
R9
− V7-M cores have two banked versions
R10
R11 • R14 is the link register (LR)
R12
• R15 is the program counter (PC)
R13
R15
(SP)
(PC)
• xPSR (Program Status Register)
R14 (LR)
− Not explicitly accessible
R15 (PC)
− Saved to the stack on an exception
PSR − Subsets available as APSR, IPSR, and EPSR

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External Use 15
xPSR – Program Status Register

31 28 27 26 25 24 23 16 15 10 7 0

N Z C V Q IT T IT/ICI ISR Number

• APSR - Application Program Status Register

− Only ALU flags
• IPSR - Interrupt Program Status Register
− Interrupt/Exception Number
• ESPR - Execution Program Status Register
− IT field – If/Then block information
− ICI field – Interruptible-Continuable Instruction information
− T bit ( s/b =1, to show core is in Thumb state)
• xPSR
− Composite of the 3 PSRs
− Stored on the stack on exception entry

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External Use 16
Stacks

• Two run-time models supported

− Single Stack Pointer – MSP for entire application
− Two Stack Pointers
 MSP for Handler Mode (Exception Handling)
 PSP for Thread Mode (Application Code)

• Main Stack Pointer (MSP)

− Used by Thread Mode out of reset
 Initial MSP value is taken from first entry of Vector Table
− Always used by Handler Mode
• Process Stack Pointer (PSP)
− Optionally used for Thread Mode
− PSP is enabled using CONTROL.SPSEL
 Must be initialized by user before being used

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External Use 17
Processor Mode Usage

• Processor mode may change when exceptions occur

− Thread Mode is entered on Reset
− Handler Mode is entered on all other exceptions

ARM Processor

Application Code
Thread Reset
Exception Mode
Entry
Exception
Return
Exception Code
Interrupts
Handler Faults
Mode

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External Use 18
Exception Handling

• Exception types
− Reset
− Non-maskable Interrupts (NMI)
− Faults
− PendSV
− SVCall
− External Interrupt
− SysTick Interrupt
• Exceptions processed in Handler mode
− Uses privileged mode
• Interrupt handling
− Interrupts are a sub-class of exception
− Automatic save and restore of processor registers ({PC, xPSR, R0-R3, R12, R14)
− Allows handler to be written entirely in ‘C’

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External Use 19
Instruction Set Support

• ARMv7-M cores implement the Thumb Instruction Set with Thumb-2

technology
− Mix of 16-bit and 32-bit instructions – implements almost all of the ARM instruction set
functionality
− Superset of the complete 16-bit Thumb instruction set
− Load/Store instruction set; no direct manipulation of memory contents
− Instruction length can vary, depending on functionality
• Two optional architecture extensions are available:
− v7E-M adds DSP instructions
 Currently supported on Cortex-M4
− Single precision floating point instructions
 Currently supported on Cortex-M4 with FPU
(the processor formerly known as Cortex-M4F)
• See the Technical Reference Manual (TRM) for the core for more detail

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External Use 20
Instruction Set Examples:

• Data Processing:
MOV r2, r5 ; r2 = r5
ADD r5, #0x24 ; r5 = r5 + 36
ADD r2, r3, r4, LSL #2 ; r2 = r3 + (r4 * 4)
LSL r2, #3 ; r2 = r2 * 8
MOVT r9, #0x1234 ; upper halfword of r9 = #0x1234
MLA r0, r1, r2, r3 ; r0 = (r1 * r2) + r3

• Memory Access:
STRB r2, [r10, r1] ; store lower byte in r2 at
address {r10 + r1}
LDR r0, [r1, r2, LSL #2] ; load r0 with data at address
{r1 + r2 * 4}
• Program Flow:
BL <label> ; PC relative branch to <label>
; location, and return address
; stored in LR (r14)
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External Use 21
System Address Map

• ARMv7-M is a memory-mapped architecture

− Same address view for physical memory and processor control & status registers
• Memory is divided into 8 x 512MB segments

0xFFFFFFFF
System

Device

Device

RAM

RAM

Peripheral

SRAM

Code 512MB
0x00000000

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External Use 22
Memory bus structure

• The Bus Matrix partitions memory access via the AHB and PPB
buses
FFFFFFFF
System (XN)
E0100000
APB Debug Components
E0040000
CM3 Instruction SCS + NVIC
E0000000
Core Data
External Peripheral
1 GB
Bus Matrix INTERNAL PPB
A0000000
with SYSTEM AHB
SYSTEM AHB External RAM
Debug Bit- Bander
Debug ICODE AHB 1 GB
Aligner
and Patch DCODE AHB EX
60000000
Peripheral ½GB
BB
40000000
RAM
½GB
EX+BB
20000000
EX – Code execution support Code Space
HX
½GB
HX – High performance code execution 00000000
BB – Bit banding

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External Use 23
Instruction and Data Alignment

• Instruction alignment
− Thumb instructions must be 16-bits wide and halfword-aligned
− Thumb-2 instructions are 16 or 32-bits wide and are halfword-aligned
• Data alignment
− Core can be configured for optional unaligned data accesses
• Instruction fetches in ARM Cortex-M Profile are always little-endian
• Data accesses can support both big and little-endian
− Cortex-M3 is switchable at reset
− System Control Space accesses are always little-endian

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External Use 24
Power Management

• Multiple sleep modes supported - controlled through the NVIC

− Sleep Now
 (Wait for interrupt/event) instructions
− Sleep On Exit
 Sleep immediately on return from last ISR
− Deep Sleep
 Long duration sleep, so PLL can be stopped
 Exports additional output signal SLEEPDEEP

• Core may be clock gated in all sleep modes

− Sleep signal is exported allowing external system to be clock gated also
− NVIC interrupt Interface stays awake

• Wake-Up Interrupt Controller (WIC)

− External wake-up detector allows core to be fully powered down
− Effective with State-Retention / Power Gating (SRPG) methodology

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External Use 25
Exceptions

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External Use 26
Exceptions Overview

• The ARM v7-M (and v6-M) exception architecture is very different from
other ARM architectures
• Designed for microcontroller applications
− Support for many interrupt sources
− Efficient handling of nested interrupts
− Flexible interrupt architecture (highly configurable)
− Built in RTOS support
• Main Features
− Nested Vector Interrupt Controller (NVIC)
− Micro-coded architecture handles the “dirty work”
 No software overhead for Interrupt Entry/Exit and Interrupt Nesting
− Only one mode and one stack for all exception handling
 Handler mode / Main stack
− Easy to program
 All exception handlers may be coded in “C”

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External Use 27
Interrupt Overheads

 Comparison with traditional ARM7 core

Higher Priority

IRQ1

IRQ2

ARM7TDMI
Push ISR 1 Pop Push ISR 2 Pop
Interrupt Handling
26 Cycles 16 Cycles 26 Cycles 16 Cycles

ARM Cortex®-M ~65% Saving

Push ISR 1 TC ISR 2 Pop
Interrupt Handling Cycle Overhead
12 Cycles 6 Cycles 10 Cycles
Tail-Chaining

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External Use 28
External Interrupts

• External Interrupts handled by Nested Vectored Interrupt Controller (NVIC)

− Tightly coupled with processor core
• One Non-Maskable Interrupt (NMI) supported
• Number of external interrupts is implementation-defined
− ARMv7-M supports up to 496 interrupts

INTNMI
INTISR[0] ……
… NVIC
… Cortex-Mx
INTISR[N] Processor Core

Cortex-Mx Integration Layer

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External Use 29
Micro-coded Interrupt Mechanism

• Interrupt architecture designed for low latency

• Interrupt prioritization mechanism is built into NVIC

• Interrupt entry/exit is “micro-coded” – controlled by hardware

− Automatically saves and restores processor context
− Allows late determination of highest priority pending interrupt
− Allows another pending interrupt to be serviced without a full restore/save
of processor state (tail-chaining)
− Interrupt Service Routines (ISRs) can be written entirely in C

• Some multi-cycle instructions are interruptible for improved

interrupt latency

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External Use 30
Exception Priorities Overview

Name Exception Number Exception Priority No. Lowest

Interrupts #0 - #495 (N interrupts) 16 to 16 + N 0-255 (programmable)
SysTick 15 0-255 (programmable)
PendSV 14 0-255 (programmable)
SVCall 11 0-255 (programmable)
Usage Fault 6 0-255 (programmable)
Bus Fault 5 0-255 (programmable)
Memory Management Fault 4 0-255 (programmable)
Hard Fault 3 -1
Non Maskable Interrupt (NMI) 2 -2
Reset 1 -3
Highest
• The lower the priority number, the higher the priority level
• Priority level is stored in a byte-wide register, which is set to 0x0 at reset
• Exceptions with the same priority level follow a fixed priority order using the exception
number
− Lower exception number has higher priority level

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External Use 31
 Vector Table for ARMv7-M

Address Exception #
• First entry contains initial Main SP 0x40 + 4*N External N 16 + N
• All other entries are addresses for exception … … …
handlers
0x40 External 0 16
− Must always have LSBit = 1 (for Thumb)
0x3C SysTick 15
• Table has up to 496 external interrupts
0x38 PendSV 14
− Implementation-defined
− Maximum table size is 2048 bytes
0x34 Reserved 13

• Table may be relocated 0x30 Debug Monitor 12

− Use Vector Table Offset Register 0x2C SVC 11

− Still require minimal table entries at 0x0 for 0x1C to 0x28 Reserved (x4) 7-10
booting the core 0x18 Usage Fault 6
• Each exception has an exception number 0x14 Bus Fault 5
− Used in Interrupt Control and State Register 0x10 Mem Manage Fault 4
to indicate the active or pending exception
type 0x0C Hard Fault 3

• Table can be generated using C code 0x08 NMI 2

− Example provided later 0x04 Reset 1

0x00 Initial Main SP N/A

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External Use 32
Reset Behavior

Main
5

4
Reset Handler

0x04 Reset Handler Vector

1 0x00 Initial value of MSP r13 (MSP)
2

1. A reset occurs (Reset input was asserted)

2. Load MSP (Main Stack Pointer) register initial value from address 0x00
3. Load reset handler vector address from address 0x04
4. Reset handler executes in Thread Mode
5. Optional: Reset handler branches to the main program
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External Use 33
Coming Out of Reset

• Processor will be in thread mode with privileged operation

• Processor will use main stack
• Core will fetch the MSP and PC from the vector table
− Vector table will be located at address 0x0 (generally non-volatile memory)
− PSP (if used) can be set later in reset handler using MRS instruction
• All interrupts are disabled
− Vectortable must contain valid value for NMI Handler and Hard Fault
Handler
− PRIMASK, FAULTMASK and BASEPRI are cleared
• MPU is disabled
− Default memory map is used

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External Use 34
Interrupt Service Routine Entry

• When receiving an interrupt the processor will finish the current instruction
for most instructions
− To minimize interrupt latency, the processor can take an interrupt during the
execution of a multi-cycle instruction - see next slide
• Processor state automatically saved to the current stack
− 8 registers are pushed: PC, R0-R3, R12, LR, xPSR
− Follows ARM Architecture Procedure Calling Standard (AAPCS)
• During (or after) state saving the address of the ISR is read from the Vector
Table
• Link Register is modified for interrupt return
• First instruction of ISR executed
− For Cortex-M3 or Cortex-M4 the total latency is normally 12 cycles, however,
interrupt late-arrival and interrupt tail-chaining can improve IRQ latency
• ISR executes from Handler mode with Main stack

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External Use 35
Internal Exceptions

• SysTick Timer
− Provides system heart-beat for RTOS (or custom program executive)
− Periodic interrupt drives system task scheduling
− Better than a standard Timer Interrupt
 Integrated into the NVIC
 Does not vary between vendor implementation and Cortex-M families
• System Service Call (SVC)
− Similar to “SVC” instruction on other ARM cores
− Allows non-privileged software to make system calls
 RTOS services requests from non-privileged mode
 Provides protection to important system functionality
 Examples: Open Serial Port, Remap Memory, Enter Low Power Mode, etc.
• Pended System Call (PendSV)
− Operates with SVC to ease RTOS development
− Intended to be an interrupt for RTOS use

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External Use 36
Fault Exceptions on v7-M

• Three classes of faults

− Bus – Memory access error (Prefetch or Data Access)
− Memory Manage – MPU permissions mismatch
− Usage – Undefined instruction, CP access, illegal state transition (i.e. T=0)
 Can optionally trap divide by zero and unaligned memory accesses
• Bus, Memory Manage and Usage Faults
− Manually enabled in the System Handler Control and State Register
− Disabled by default – only enable if required
− User-defined priority level
• Hard Fault – “Fall Back” Fault
− Always enabled with priority level “-1”
− Executes through “Fault Escalation”

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External Use 37
Advanced Features and Debug

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External Use 38
Motivation: Memory Protection

Memory

Privileged OS
modes code + data

OS

User mode Application

code + data
Application code

ARMxyz

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External Use 39
Memory Protection Overview

• MPU architecture same as ARM Cortex-R4 - ARM v7 PMSA

• Supports 8 regions
− Each region applies to both instruction and data accesses (unified regions)
• Access controlled by region attributes
− Individual Instruction access, Data access and Memory attributes
− Controls Cacheability, Data/Peripheral Type selection
• Regions have variable base address and size
− Base address must be aligned to the region size boundary
• Regions may overlay other regions
• MPU is optional
− Absent or disabled MPU uses the default memory map
• Sub-regions also possible within each region
• MPU can modify some attributes of the default memory map
− Cannot modify addresses of Code or System spaces
− Top 0.5GB of the memory map is always “Execute Never”, so cannot be changed by MPU
− Bit-Band regions (if implemented) cannot be moved
− PPB is always strongly-ordered
• MPU primarily provides access protection
− Can also make Peripheral memory partitions executable
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External Use 40
v7-M Bit-banding

Traditional Method of Read-Modify-Write Manipulation

0 0 0 0 0 0 0 0 Read byte from SRAM

0x02000000

Mask and Modify Bit x x x x x 1 x x

Element
0x02000000

0 0 0 0 0 1 0 0 Write byte to SRAM

0x02000000

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External Use 41
v7-M Bit-banding

• Writes to a word address in the

bit-band alias affect a single bit in
the bit-band region
• The write is translated to an atomic
read-modify-write by the Cortex-M3
bus matrix
• Bit 0 of the stored register is written
to the appropriate bit

Word alias 32MB Bit-band alias

32MB

31MB

Physical bit 1MB Bit-band region

32MB Bit-band alias

31MB

1MB Bit -and region

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External Use 42
ARM Cortex-M3/M4 Debug Features

• Compliant with ARMv7-M Debug Architecture (CoreSight™ based)

• Traditional ARM Debug Features
− Two debug modes (Halt mode and Monitor mode)
− Two stepping modes (with and without interrupts taken)
− BKPT instruction
− Vector Catch
− Optional Embedded Trace Macrocell (ETM)
• CoreSight Debug Features
− Flash Patch and Breakpoint (FPB)
 Instruction Breakpoints and Code Patching
− Data Watchpoint and Trace (DWT)
 Hardware Breakpoints, Event Counters and PC Sampling
− Instrumentation Trace Macrocell (ITM)
 Low bandwidth trace driven by application software or DWT
 Serial Wire Viewer

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External Use 43
Cortex-M3/M4 Debug Access Paths

Flash Patch & Data Instrument.

Breakpoint Watchpoint & Trace
(FPB) Trace (DWT) Macrocell
(ITM)

Cortex-M3
Core Bus AHB - Internal Private Peripheral Bus

Matrix
APB - External Private Peripheral Bus

Embedded Trace Port

ROM Table Trace Interface Unit
Macrocell (TPIU)
(ETM)

AHB-
SW/J-DP
AP

DAP

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External Use 44
Flash Patch and Breakpoint Unit (FPB)

• Flash Patching
− Allows runtime patching of firmware
 Remaps reads from the Code space to System space using a Patch Table
− Total of 8 addresses may be patched
 6 instruction comparators (for instruction fetches from Code space)
 2 literal comparators (for literal data loads from Code space)
− Only reads are patched
 Writes will be performed as normal
− Intended Usage
 ROM-based designs (costly fix)
 Firmware field upgrades
• Hardware Breakpoints – maximum of 6
− The 6 instruction comparators can return a BKPT to halt the core
− Instruction comparators are shared with Flash Patch functionality
 If 3 instructions are flash patched, only 3 hardware breakpoints are available

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External Use 45
Data Watchpoint and Trace (DWT)

• DWT component useful for Debug, Trace and Profiling

− Enabled by setting TRCENA bit in Debug Exception and Monitor Control Reg
• Debug Support
− Traditional data watchpoint for halt mode debug
− Can break on [data value && data address] match (x1)
• Trace Support
− Generate trace trigger for Embedded Trace Macrocell (ETM)
• Profiling / Event Support
− Provides non-invasive view of application execution
− Packets output through Instrumentation Trace Macrocell (ITM)
 Must have debug tools connected to view the output
− Packets generated for selected events of interest
 Data Address matching
 Periodic PC Sampling
 Exception Entry, Exit and Return
 Hardware performance counting

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External Use 46
Instrumentation Trace Macrocell (ITM)

• Generates and outputs Trace Packets

• Packet types (in priority order):
− Software trace
 Software can write directly to ITM stimulus registers, causing packets to be emitted
 Similar to using printf() to debug a C program
− Hardware trace
 Packets are generated by the DWT and emitted by the ITM
− Timestamps
• Timestamp Packets
− Must be enabled in ITM Trace Control Register
− Local Timestamp (differential) value generated from 21-bit counter
 Counter clocked from either core clock or TPIU clock
− Global Timestamp (absolute) value generated from 48-bit counter
− Packet generation
 When any other trace packet is generated (which resets timestamp counter)
 When timestamp counter overflows

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External Use 47
Physical Interfaces

• New 10-pin and 20-pin interfaces available

− Higherpin density (0.05”) over standard JTAG IDC interface (0.10”)
− Reduces connector footprint
• Serial Wire Debug is the preferred solution
− SWO likely not available when using JTAG interface
• Trace can use a 20-pin connector
− Legacy 38-pin Mictor connector not recommended
• Consult CoreSight Component TRM or Device Data Sheet

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External Use 48
Software

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External Use 49
Introduction

Software Tools Debug Adapters Development Targets

 Keil® Microcontroller
Development Kit (MDK)  ULINKpro  MCU development boards
 DS-5  ULINK2  µVision Simulator
 ULINK-ME

 DSTREAM  MCU development boards

 Fast Models

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External Use 50
Keil MDK: ARM Compiler

• Compiler compile/assemble

• Assembler C/C++ source armcc object

• Linker
assembler source armasm object
• Format Converter
• Libraries link
• Librarian
objects armar library
• These are all command line tools
− Easy to script libraries armlink image
• All tools emit useful statistics
− e.g. code size, data size, symbol table, executable
call graph, image memory map etc. object binary
− See the documentation fromelf
image stats

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External Use 51
Language Support

• Single compiler armcc can compile standard ISO C/C++

• Source language modes
− ISO C90
 1990 C standard, compile option --c90 (default)
− ISO C99
 1999 C standard, compile option --c99
− ISO C++
 2003 C++ standard, compile option –cpp

• Language compliance
− Default mode supports several common extensions
− Strict mode enforces compliance with language standard: --strict
− GNU mode offers partial support for GCC extensions: --gnu

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External Use 52
Variable types supported

• The compiler supports these basic types

int / long 32 bit (word) integer
short 16-bit (half-word) integer
char 8-bit byte, unsigned by default

long long 64-bit integer

float 32-bit single-precision IEEE floating point

double 64-bit double-precision IEEE floating point

bool 8-bit Boolean (C++ only)

wchar_t 16-bit “wide character” type (C++ only)

Pointers 32-bit integer addresses

• Take care when porting legacy code from other vendors’

architectures

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External Use 53
Optimization Levels

• Level of optimizations carried out by the compiler is selectable

-O0
− Minimum optimization
− The least optimized code, but with the best debug view
-O1
− Restricted optimization
− Optimized code and a good debug view
-O2 (default)
− High optimization
− Well optimized code but with limited debug view
-O3
− More aggressive optimization, weighted toward -Ospace / -Otime choice
− Enables multifile compilation by default (more later)

• Select optimization for code size or execution speed with -Ospace (default) or -
Otime
• Use -g or --debug to generate source level debug information

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External Use 54
Selecting an Architecture or Core

• Each new version of the ARM Architecture typically supports extra instructions and
models of operation
• Implementation of an architecture version may vary between cores
− Use the most specific setting you can when compiling
• Inform the compiler of the architecture or processor
− The default CPU setting is ARM7TDMI (Architecture 4T)
− Either specify an architecture version, or a specific core
--cpu 7-M (Do not prefix with a ‘v’)
--cpu Cortex-M3

• Some examples of features the compiler and libraries can take advantage of:
− UDIV and SDIV (7-M and 7-R)
− REV (v6) can be used to reverse byte endianness
− Unaligned memory access (v6)

• When using the Cortex-M3 it is essential to specify 7-M or Cortex-M3 to ensure the
correct (Thumb only) libraries are used

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External Use 55
CMSIS Structure

 There are five main components to CMSIS:

 CMSIS-CORE API for Cortex-M processor and core peripherals
 CMSIS-DSP DSP Library with 61 function types for Cortex-M
 CMSIS-SVD XML system view description for peripherals
 CMSIS-RTOS API for RTOS integration
 CMSIS-DAP API for debug and trace integration (not shown in diagram)

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External Use 56
Using CMSIS-CORE

 To use the CMSIS-CORE the following files are added to the embedded
application:
 Startup File startup_<device>.s with reset handler and exception vectors
 System Configuration Files system_<device>.c and system_<device>.h with
general device configuration (clock setup)
 Device Header File <device.h> gives access to processor core and all peripherals

 Silicon vendors create these device-specific CMSIS-CORE files based on

template files provided by ARM
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More Information

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Next Steps

• Find out more about the program, the test and how to prepare for it:
Visit www.arm.com/aae

• Recommended Reading
− Joseph Yiu – The Definitive Guide to the Cortex-M3 and Cortex-M4
Processors. ISBN 0124080820
− ARMv7m Architecture Reference Manual
 http://infocenter.arm.com/help/topic/com.arm.doc.ddi0403c/index.html
− ARM Cortex-M Generic User Guide
 http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/index.html

• Schedule a test at a local test center:

Visit www.prometric.com/arm

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